User Manual
Contents
1. Pd EEO ELL KE EEN x void init_finale_FMC_card CommandType cmd decodeCommand ws LMKO4828 0000 90 decodeCommand ws LMKO4828 0000 OO decodeCommand ws LMKO4828 0002 00 decodeCommand ws LMKO4828 0100 decodeCommand ws LMKO4828 0101 55 Ox5 decodeCommand ws LMKO4828 0103 OO clear DCLKoutO_MUX decodeCommand ws LMKO4828 0104 22 decodeCommand ws LMKO4828 0105 00 decodeCommand ws LMKO4828 0106 FO DCLKoutO ADLYg PD set DCLKoutO ADLY PD decodeCommand ws LMKO4828 0107 15 decodeCommand ws LMKO4828 0108 OE decodeCommand ws LMKO4828 0109 55 0x5 decodeCommand ws LMK04828 O10B OO clear DCLKout2_MUX decodeCommand ws LMK04828 010C 22 decodeCommand ws LMK04828 010D OO decodeCommand ws LMK04828 010E F9 DCLKout2_ADLYg_PD set DCLKout2_ADLY_PD decodeCommand ws LMK04828 O10F OO decodeCommand ws LMK04828 0110 1C decodeCommand ws LMK04828 0111 55 0x5 Fidus Systems Inc FMCs by Fidus amp cmd executeCommand amp cmd set RESET and SPI_3WIRE_DIS amp cmd executeCommand amp cmd clear RESET and SPI 3WIRE DIS amp cmd executeCommand amp cmd clear POWERDOWN amp cmd executeCommand amp cmd set DCLKoutO DIV to OxOe amp cmd executeCommand amp cmd set DOLKoutO DDLY CNTH to Ox5 set DCLKoutO_DDLY_CNTL to amp cmd executeCo2. 17 6 3 EXTERNAL CLOCK INPUT PEE 17 6 4 EXTERNAE TRIGGER INPUT sesactsd caicclavaacestervereuvessaderuedvas a a a A ques Ux vac Ure yea puedes Dua eue Ux rn Rr vaE a prope aue 18 6 5 COMMUNICATION AND CONTRO scu aerea 19 D LE a EE s TR 19 6 5 1 1 COCK GONE EI P MEET E O m 20 6 5 1 2 Analog to DiBltal CONV CILCKS sm cacus eedpt actes ood vs emt cos ocu adt amt ka ops edocet e E ens ec dot ergo focum oaa peucoc ed sum Roc cem e 20 MEME zr Tet 21 T ENVIRONMENTAL AND MECHANICAL ccccscceccscceccscssccccecceccsccssesccscecceccuscusonsesccsceccuccusansessescuscuscuscususenees 22 Tad ENVIBONMEND usto e dito dun ebrius m MM MR M 22 7 2 THERMAL E 22 1 3 TESTED 23 1 3415 vRrontBezelil 36eplate xbuseuuidbxspo euam ep bad quos n DUE vada mnt e Dc Odi DE Ee Reus 23 Toa 5 24 8 Bauen ege O N a ed 25 8 1 FIARDWARE INSTALLATION gs cocus disset a coc ew ER Saxa S abu meu
3. NXP PCF85102C 12V_FMC SWITCHER_SYNQ1 SWITCHER_SYNQ2 PROJECT NAME FSF AD8200A DATE TITLE DRAWN ST LM CHECK lt CH INIT gt DESIGN LQ ST ADDITIONAL INFO SCALE gd SWITCHER 6 15 13 mee jo 15 13 INTERMEDIATE POWER INDICATOR EN PWR o PWR GOOD POWER SYSTEM 44V TI TPS84250 3V3_CLOCKING LP38798 3V3_VCXO TI LP38798 ADC4_LC_ 1V8 ADC3_ 1V8 SWITCHER TPS84250 a TPS74801 amp 35 Fitzgerald Road Ottawa ON K2H 1E6 tidus IDT TI JESD204B OCTAL ADC FMC ROHS SIZE CODE IDENT DWG NO 6 ADC BD REV 2 0 T 11 15 2013 10F1 FSF AD8200A User Manual 3 GLOSSARY ADC BW C2M CML FMC HPC IMD M2C MGT OFDM SFDR SNR Analog to Digital Converter Bandwidth Carrier to Mezzanine i e a signal output from carrier input to FMC Current Mode Logic FPGA Mezzanine Card High Pin Count Intermodulation Mezzanine to Carrier i e a signal output from the FMC input to the carrier Multi Gigabit Transceiver Orthogonal Frequency Division Multiplexing Spurious Free Dynamic Range Signal to Noise Ratio Xilinx Virtex and Vivado are registered trademarks of Xilinx ChipScope is a trademark of Xilinx 4 REFERENCE DOCUMENTS Reference Document FSF AD8200A Hyperlink Function Mezzanine Card FMC Standard 885731 49 3 ANSI VITA 57 1 FPGA http www vita
4. GND HA11 P GND C2M CLKGEN CSn GND HA13 P LAOS_N GND ADC1A_CML_P GND us maoe liao ecm vaos scel com poca waocen serre scc 5 iA HA10 P HA11 N 07 P CAM VADJ SCLK 2 VADJ CSn HA12 P HA13 N GND GND CML N GND o MEME MEME o ooo oo HA10 N GND C2M SDIO DIR GND HA12 N GND C2M ADC2 CSn C2M ADCA CSn GND ADC2B CML P o A ooo ovo NENNT GND HA14 P GND CLKGEN VADJ MAN SYNC C GND HA16 P C2M ADC3 CSn C2M SDIO ADC GND ADC2B CML N LA11 P C2M SDIO CLKGE DP6 2 P HA17 P CC HA14 N N LA12 N nPOWER FAULT HA15 P HA16 N GND GND CML P GND 17 HA17 N GND CLKGEN VADJ RESETn GND HA15 N GND C2M_VADJ_SWITCHER SYNQ1 GND ADC1B_CML_N GND NM iT Eee GND HA18 P GND LA16 P GND HA20 P LA13 N CARD ID 4K12 PD C2M VADJ SWITCHER SYNQ GND ADC2A CML P hs war uen vus uen uus HA21 P HA18 N LA15 P LA16 N HA19 P HA20 N GND LA14 N GND ADC2A CML N MEMMEM ee RI EE HA21 N GND LA15 N GND HA19 N GND ADCA LVDS FRAMEP GND GND M NENNEN NEM BN 21 GND HA22 P GND LA20 P GND HBO3 P ADC4_LVDS_FRAMEN GND GND a mase wn wor ty ee neoon o o HA23 P HA22 N LA19 P LA20 N HBO2 P HBO3 N GND ADC1 LVDS FRAMEP GND DP1 C2M P 2 o MEM CO HA23 N GND LA19 N GND HBO2 N GND LA23 P ADC1 LVDS FRAMEN GND DP1 C2M N
5. ML FSF AD8200A 8 Channel 185MSPS JESD204B ADC FMC User Manual January 2014 Version 1 0 Fidus Systems Inc 35 Fitzgerald Road Suite 400 Ottawa ON K2H 1E6 CANADA Tel 613 828 0063 Fax 613 828 3113 Fidus Systems Inc is at the forefront of technology innovation and for this reason reserves the right to alter without notice the specification design or conditions of supply of any product or service Information provided by Fidus Systems is believed to be accurate and reliable However no responsibility is assumed by Fidus Systems Inc for its use nor any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Fidus Systems Inc 2014 Fidus Systems Inc All Rights Reserved Fidus name Fidus logo and FMCs by Fidus brand are trademarks of Fidus Systems Inc Other registered and unregistered trademarks are the property of their respective owners Information is subject to change without notice FSF AD8200A User Manual Revision History Revision Author Release Date DescriptionofChange 06 18 2013 12 12 2013 Updates 0 3 EJD 12 19 2013 Updated section 4 to add info on Command Interface Scripts and refer to the Getting Started Guide and Command Interface Guide 01 03 2014 Update Release Fidus Systems Inc FMCs by Fidus Page i of ii F
6. set PLL2 R 11 8 to OxO amp cmd executeCommand amp cmd set PLL2 R 7 0 to OxOO amp cmd executeCommand amp cmd set PLL2 P to Ox2 set OSCin FREQ Ox1 clear PLL2 XTAL amp cmd executeCommand amp cmd clear PLL2 CAL 17 16 to OxO amp cmd executeCommand amp cmd clear PLL2 CAL 15 8 to amp cmd executeCommand amp cmd set PLL2 CAL 7 0 to OxOc amp cmd executeCommand amp cmd set OPT REG 1 to 0x15 amp cmd executeCommand amp cmd set REG 2 to 0x33 amp cmd executeCommand amp cmd clear PLL2 FCAL DIS clear PLL2_N 17 16 to OxO amp cmd executeCommand amp cmd clear PLL2 N 15 8 amp cmd executeCommand amp cmd set PLL2 N 7 0 to OxOa amp cmd executeCommand amp cmd set PLL2 WND SIZE to Ox2 set PLL2 CP GAIN to Ox1 clear amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd cmd amp cmd amp cmd amp cmd executeCommand amp cmd set PLL2 DLD CNT 15 8 to 0x20 executeCommand amp cmd clear PLL2 CNT 7 0 to executeCommand amp cmd clear PLL2 R4 to OxO clear PLL2 R3 to OxO executeCommand amp cmd clear PLL2 CA to OxO clear PLL2 C3 to OxO executeCommand amp cmd set PLL2 LD MUX to Ox1 set PLL2 LD TYPE to Ox3 executeCommand amp cmd clear PLL2 PD clear PLL2 PD executeCommand amp cmdQd clear SPI LOCK 2
7. amp cmd amp cmd amp cmd executeCommand amp cmdQd executeCommand amp cmdQd executeCommand amp cmdQd executeCommand amp cmdQd executeCommand amp cmdQd executeCommand amp cmdQd executeCommand amp cmd executeCommand amp cmdQd executeCommand amp cmdQd executeCommand amp cmdQd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd 7 SSS Na et aaa Se ee a SS ee Page 34 of 36 FSF AD8200A User Manual decodeCommand ws AD1443D_3 0004 08 delay_ms 400 decodeCommand ws AD1443D_3 0004 10 delay_ms 400 decodeCommand ws AD1443D_3 0004 20 delay_ms 400 decodeCommand ws AD1443D 3 0043 C7 decodeCommand ws AD1443D_3 081C 4A decodeCommand ws AD1443D_3 0822 01 decodeCommand ws AD1443D_3 0810 CO decodeCommand ws AD1443D_3 0811 40 decodeCommand ws
8. directory holding an empty Vivado project This project contains no source files but it does contain a customer release sub directory The necessary bitfiles and debug probe files and other documentation to exercise the FSF AD8200A card on a Xilinx VC707 Evaluation Card are all contained in this customer release directory Please look in customer release docs directory and observe 3 important documents there First there is the Getting Started Guide which is a step by step guide to installing the necessary software configuring it downloading a bitfile and obtaining waveform traces Another important document is the Command Interface Guide which explains all commands available through the command interface running on the VC7O Evaluation Card Finally a copy of this document is also stored there Inside the empty project directory find the customer release directory which contains the documents and datafiles sub directories The datafiles directory holds the FPGA download bit file which is downloaded into the FPGA on the VC70O carrier board It configures the hardware of the FPGA to receive data from the FSF AD8200A card using a Xilinx JESD204B core Note the FPGA design includes an on chip processor the software for this processor is bundled into the download bit file and the probes file debug netx Itx which allows data to be displayed using the ILA The download bit file contains both the configuration for the FPGA
9. 0004 10 delay_ms 400 decodeCommand ws AD1443D_1 0004 20 delay_ms 400 decodeCommand ws AD1443D 1 0043 C7 decodeCommand ws AD1443D_1 081C 4A decodeCommand ws AD1443D 1 0822 01 decodeCommand ws AD1443D 1 0810 CO decodeCommand ws AD1443D 1 0811 40 decodeCommand ws AD1443D 1 0812 OA decodeCommand ws AD1443D 1 081E 08 decodeCommand ws AD1443D_1 O86B 02 decodeCommand ws AD1443D 1 086C 02 decodeCommand ws AD1443D_1 0872 04 decodeCommand ws AD1443D 2 0803 00 decodeCommand ws AD1443D 2 0802 08 decodeCommand ws AD1443D 2 0100 d1 decodeCommand ws AD1443D 2 0200 01 decodeCommand ws AD1443D 2 OOff 80 decodeCommand ws AD1443D 2 0102 07 decodeCommand ws AD1443D 2 0103 66 decodeCommand ws AD1443D 2 0012 10 decodeCommand ws AD1443D 2 0108 a3 decodeCommand ws AD1443D 2 010a cO decodeCommand ws AD1443D 2 0154 01 decodeCommand ws AD1443D 2 0155 03 decodeCommand ws AD1443D 2 0156 d8 Fidus Systems Inc FMCs by Fidus amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd amp cmd executecCommand amp cmd executeCommand amp cmd J amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd am
10. MSPS chda T I Hz WiMAX centered 165 MHz 170 4 7 MSPS Input 4 B dBFS pk 13 8 dBFS RMS Noise floor is dominated by Agilent N5102A signal generator pk T T Input 1 8 dBFS pk pk 14 4 dBFS RMS Noise floor is dominated by ailent N51B82A signal generator Figure 14 OFDM center 165MHz BW 10MHz amp 14 4dBFS RMS Nyquist Zone 2 Fidus Systems Inc FMCs by Fidus Page 12 of 36 FSF AD8200A User Manual 6 INTERFACES The FSF AD8200A is comprised of both external and internal interfaces The following interfaces are discussed in this section FMC interface and pin out ADC analog inputs External clock and trigger inputs SPI interface to the clock generator SPI interface to the ADC devices 6 1 FMC Interface Pin support and other requirements The FSF AD8200A requires that the FMC carrier card contain a suitable HPC FMC connector As the FMC standard allows designers a certain amount of flexibility in pin selection and voltage support just because a carrier card as an HPC connector it does not mean that it will be compatible with every FMC with an HPC connector Compatibility must be carefully assessed on a case by case basis The following sub sections describe the support that the FSF AD8200A requires from the carrier card Fidus Systems Inc FMCs by Fidus Page 13 of 36 FSF AD8200A User Manual 6 1 1 FSF AD8200A HPC FMC pin assignment and defini
11. NO N NS mn AN AM ae eer ae eee HOLDOVER_HITLESS_SWITCH set HOLDOVER_EN decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMK04828 Fidus Systems Inc FMCs by Fidus 0151 02 0152 00 0153 00 0154 02 0155 00 0156 02 0157 00 amp cmd executeCommand amp cmd set HOLDOVER DLD CNT 13 8 to OxO2 amp cmd executeCommand amp cmd set HOLDOVER DLD CNT 7 0 to OxOO amp cmd executeCommand amp cmd set CLKinO_R 13 8 to OxOO amp cmd executeCommand amp cmd set CLKinO_R 7 0 to 0x02 amp cmd executeCommand amp cmd set CLKin1 R 13 8 to OxOO amp cmd executeCommand amp cmd set CLKin1 R 7 0 to 0x02 amp cmd executeCommand amp cmd set CLKin2_R 13 8 to OxOO mL Page 31 of 36 FSF AD8200A User Manual decodeCommand ws LMKOA4828 decodeCommand ws LMKO4828 decodeCommand ws LMKOA4828 decodeCommand ws LMKO4828 to Oxf decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMK04828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMK04828 decodeCommand ws LMKOA828 clear PLL2_REF_2X EN decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCo
12. Refer to the LMKO4828B datasheet for more details on SPI communications and appropriate register settings or contact Fidus Systems if you would like assistance in your application 6 5 1 2 Analog to Digital Converters Figure 17 presents the SPI format details for communications with each of the ADC1443D analog to digital converter devices The SCS N line is active low and corresponds to the four individual CSn signals one for each ADC from the FMC connector Fidus Systems Inc FMCs by Fidus Page 20 of 36 FSF AD8200A User Manual p bytes MEE MOM Register N data ca Gees N 1 data Figure 17 SPI Communications with the ADC1443D Converters The software code contained within the provided bitfile provides an example default configuration for SPI communications and register configuration for the ADC1443D Other configuration settings are of course possible Refer to the ADC1443D datasheet for more details on SPI communications and appropriate register settings or contact Fidus Systems if you would like assistance in your application 6 5 2 EEPROM The FSF AD8200A contains non volatile storage as defined by the FMC standard The EEPROM is solely accessed via an 12C bus and is mastered by the carrier card s FMC The EEPROM contains critical information that describes the operational demands of the FMC The end user must ensure that their application first reads the contents of the EEPROM to ensure that the carrier card will be
13. and the software which runs on a soft processor in the FPGA to provide a simple command interface This command line interface allows access to the key chips on the FSF AD8200A and the supporting blocks in the FPGA The command line interface is controlled using any simple terminal program running on the host computer connected to the carrier board For instance if the host computer is a PC then Tera Term PRO can be used running in 8 N 1 mode at 115200 baud with Xon Xoff flow control enabled 6 and screwing the heat sink to the carrier card if available Fidus Systems Inc FMCs by Fidus Page 25 of 36 FSF AD8200A User Manual When the command interface first runs it prints some diagnostic information including the current FPGA hardware version and the Command Interface Software version and then it presents the Command gt prompt The help command can be entered to get more information Full information on the commands supported by this interface is available in the FSF AD8200A Finale Command Interface Guide This can be found in the docs sub directory of the customer release directory Typically the first command entered is init which sends a fixed sequence of commands to the FSF AD8200A intended to configure the LMKO4828B clock generator the ADC1443D converters and the JESD20AB core in the FPGA Users can also create their own command sequences as text files on the host PC and send them to the command interface
14. compatible prior to enabling power to the FMC connector site If this step is ignored and compatibility is not validated prior to powering either the carrier card or the FMC or both could be permanently damaged or destroyed As per the VITA 57 1 standard the EEPROM is powered by 3V3AUX thus enabling communication with the EEPROM independent of any other onboard voltages EEPROM Information PCF85102C 21 03 2kbit 20 EEPROM Address Ob10100xx where xx is specified by the GA O 1 signals from the carrier card Table 9 EEPROM Information EEPROM CONTENTS AVAILABLE SOON Fidus Systems Inc FMCs by Fidus Page 21 of 36 FSF AD8200A User Manual T ENVIRONMENTAL AND MECHANICAL 7 1 Environment The FSF AD8200A is primarily designed for laboratory experimentation and development It is specified for operation as follows Parameter Min Typ Max Unit Conditions Comments Ambient Operating 45 C This is the guaranteed operating Temperature range and that which the FSF AD8200A is verified to FSF AD8200A individual 40 85 C This is the basic temperature rating component ratings of the components used in the design as per the component s datasheet ESD Not evaluated A level of ESD protection is present Not designed for or evaluated User responsibility Not designed for or evaluated Not designed for or evaluated o oOo O oo Table 10 Environmental Operating Conditions 7 2 Thermal Consider
15. coupling to A E F G H dB vs Frequency MHz Figure 8 Typical Channel Channel Crosstalk input C to non adjacent channels Input D coupling to C amp E dB vs Frequency MHz Figure 9 Typical Channel Channel Crosstalk input D to adjacent channels Fidus Systems Inc FMCs by Fidus Page 9 of 36 FSF AD8200A User Manual Input D coupling to A B F G H dB vs Frequency MHz Figure 10 Typical Channel Channel Crosstalk input D to non adjacent channels Fidus Systems Inc FMCs by Fidus Page 10 of 36 FSF AD8200A User Manual 5 1 4 Intermodulation 2 Tone IM3 Fsample 170 4 7 MSPS cha I T I I T Fi 168 574 MHz 7 dB X 10 X 1499 F2 amp 193 560 MHz FS 7 dB 397 v 30 40 gp a a 4 986 v 35 l x 13 X Bis Figure 11 Two tone IM3 F1 188 574MHz F2 193 560MHz amp FS 7dB 2 Tone IM3 F sample 178 4 7 MSPS T I I j I T I a a F1 n 153 574 MHr FS 18 dB X 10 X 1499 F2 193 560 MHz FS 18 dB 40 gp a BO 100 Figure 12 Two tone IM3 F1 188 574MHz F2 193 560MHz amp FS 18dB Fidus Systems Inc FMCs by Fidus Page 11 of 36 FSF AD8200A User Manual X 1407 Y 14153 x 40 Or a a Figure 13 Multi tone centered 160MHz amp 13 8dBFS RMS Nyquist Zone 2 EN a 00 20 100 110 12 Tone input centered 160 MHz 170 4 7
16. using the send file feature of the Tera Term PRO program The command interface running on the VC707 Evaluation Card will also accept typed commands one at a time It supports writes and reads from each device It can also check reads against expected values and count any mismatches An example command line script file init scr is supplied in the datafiles sub directory It does the same job as the built in init command Once the LMKO4828B clock generator ADC1443D ADCs and JESD2046 core in the FPGA are configured using the init command or a script the system is ready to capture data simultaneously from all 8 channels The captured data is stored in FPGA block RAM using Xilinx ILA cores ILA stands for Integrated Logic Analyzer formerly called Chipscope Using the Xilinx Vivado tool the data in the ILA cores can be extracted and displayed graphically or saved to the host PC for subsequent numerical analysis A probe file debug nets Itx is provided in the datafiles sub directory of the customer release directory Vivado requires the probes file when it tries to access the ILA cores to allow it to make sense of the data stored in the RAMs on the FPGA For a step by step description of the bitfile download procedure including many screen captures please see the document FSF AD8200A Getting Started Guide 7 See Appendix A for the init script contents Fidus Systems Inc FMCs by Fidus Page 26 of 36 FSF A
17. 24 c NOt NO eose vo Cro come 25 HBooP cc HBoOLN LAN Bos n oro co 26 N cc CGN os GN CN S pow 28 Heos pcc laap HB08P ors cave 29 _HBos n_cc GND Lu WENN sos c CC tC sov 3o 0 Heap NOt eNO ne sccrvcsc Drs CM P 34 HB10P t8P LA29N HB12P HBI3N TDO FMC TDO SDA FMC SDA 5 16 2 2 Heson sos Ee Erna 5 Nt eNO v se Nerv 341 HBi4P tas0P lLA3IN Big P HBMI9N GACGAO0 15 pr CM P 35 GND itso nN usu 36 0 Heis p MENO ts eNO GND 35 ue Ncc GND GND GND GND GND GND Table 3 FMC Pinout Fidus Systems Inc FMCs by Fidus Page 14 of 36 FSF AD8200A User Manual The following table defines the signals the I O type and their usage Signal s Type Dir Description JESD204B Interface ADC 4 1 B A CML P N M2C FPGA LVDS SYSREF P N ADC 4 1 LVDS FRAME P N M2C FPGA LVDS1 CLK P N JESD20AB data signals AC coupled JESD204B SYSREF signal AC coupled JESD204B SYNC DC coupled Clock intended for JESD20O4B core reference clock typically not r
18. 28 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKOA4828 decodeCommand ws LMKO4828 OxO clear FB MUX EN decodeCommand ws LMKOA4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 CLKinO_TYPE decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 0137 15 0138 00 0139 03 013A 07 O13B EO 013C 00 013D 08 O13E 03 O13F 00 0140 01 0141 00 0142 00 0143 10 0144 00 0145 7F 0146 OF 0147 06 0148 02 0149 02 014A 02 O14B 16 O14C OO O14D OO O14E CO O14F 7F 0150 1B amp cmd executeCommand amp cmd set CLKout13 FMT to Ox1 set CLKout12 FMT to Ox5 amp cmd executeCommand amp cmd clear VCO_MUX to OxO clear OSCout_MUX clear OSCout_FMT to amp cmd executeCommand amp cmd set SYSREF MUX to 0x3 amp cmd executeCommand amp cmd set SYSREF DIV 12 8 to 0x07 amp cmd executeCommand amp cmd set SYSREF DIV 7 0 to OxeO amp cmd executeCommand amp cmd set SYSREF DDLY 12 8 to OxOO amp cmd executeCommand amp cmd set SYSREF DDLY 7 0 to 0x08 amp cmd executeCommand amp cmd y
19. 2C LVTTL M2C Unconnected nPOWER_FAULT VADJ M2C O Power fault on FMC 1 Power OK on FMC Power Rails Min Max 3 6 Volts Range provided by level shifters on input of all single ended signals Connected to VADJ Not connected Not connected VIO B M2C VREF A M2C VREF B M2C 3P3V AUX 3 135 3 465 Volts 3P3V 3 135 3 465 Volts 12POV 11 4 12 6 Volts Notes a Type VADJ indicates that the input and output thresholds are governed by the level shifters which are powered by Ol The level shifting system is comprised of two different level shifters from Texas Instruments SN74AVC1T45 and SN 4AVC8T245 As the thresholds depend on the value of VADJ please refer to the respective Texas Instruments datasheets for complete threshold information Table 4 FMC Signal Definition 6 1 2 FMC Voltage and Current requirements The following table lists the voltages and associated currents used by the FSF AD8200A including those required to be listed by VITA 57 1 FMC HPC Voltage V Current mA Pins 12POV 3P3V 3 135 5465 td 1 5 VADJ 5 346 td SPSVAUX 3 135 346 Table 5 FSF AD8200A Voltages and Currents 6 1 3 Multi Gigabit Serial Communications Lines The JESD204B defines a high speed serial standard by which information is passed from a transmitter to a receiver In the case of the FSF AD8200A the transmitters are the onboard ADCs and t
20. 3 16 to OxOO executeCommand amp cmdQd clear SPI LOCK 15 8 to OxOO executeCommand amp cmd set SPI LOCK 7 0 to 0x53 executeCommand amp cmd set SYNC DISSYSREF set SYNC DIS12 set SYNC DIS10 set SS es Oe es S M Fo om SYNC_DIS8 set SYNC DIS6 set SYNC DISA set SYNC DIS2 set SYNC DISO decodeCommand ws AD1443D 1 0803 00 decodeCommand ws AD1443D_1 0802 08 ws AD1443D 1 0100 d1 ws AD1443D 1 020001 decodeCommand decodeCommand decodeCommand ws AD1443D 1 0102 O7 decodeCommand decodeCommand ws AD1443D_1 OOff 80 Fidus Systems Inc FMCs by Fidus ws AD1443D_1 0103 66 amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd 7 Page 32 of 36 FSF AD8200A User Manual decodeCommand ws AD1443D_1 0012 10 decodeCommand ws AD1443D_1 0108 a3 decodeCommand ws AD1443D 1 010a cO decodeCommand ws AD1443D 1 0154 01 decodeCommand ws AD1443D 1 0155 03 decodeCommand ws AD1443D 1 0156 d8 decodeCommand ws AD1443D 1 0160 ff decodeCommand ws AD1443D 1 0161 17 decodeCommand ws AD1443D 1 0170 10 decodeCommand ws AD1443D 1 0171 10 decodeCommand ws AD1443D 1 0400 30 delay_ms 400 decodeCommand ws AD1443D_1 0004 08 delay_ms 400 decodeCommand ws AD1443D_1
21. AD1443D_3 0812 OA decodeCommand ws AD1443D 3 081E 08 decodeCommand ws AD1443D 3 O86B 02 decodeCommand ws AD1443D 3 086C 02 decodeCommand ws AD1443D_3 0872 04 decodeCommand ws AD1443D 4 0803 00 decodeCommand ws AD1443D_4 0802 08 decodeCommand ws AD1443D 4 0100 d1 decodeCommand ws AD1443D 4 0200 01 decodeCommand ws AD1443D 4 OOff 80 decodeCommand ws AD1443D 4 0102 decodeCommand ws AD1443D 4 0103 66 decodeCommand ws AD1443D 4 0012 10 decodeCommand ws AD1443D 4 0108 a3 decodeCommand ws AD1443D 4 010a cO decodeCommand ws AD1443D 4 0154 01 decodeCommand ws AD1443D 4 0155 03 decodeCommand ws AD1443D 4 0156 d8 decodeCommand ws AD1443D 4 0160 ff decodeCommand ws AD1443D 4 0161 17 decodeCommand ws AD1443D 4 0170 10 decodeCommand ws AD1443D 4 0171 10 decodeCommand ws AD1443D 4 0400 30 delay ms 400 decodeCommand ws AD1443D 4 0004 08 delay_ms 400 decodeCommand ws AD1443D_4 0004 10 delay_ms 400 decodeCommand ws AD1443D_4 0004 20 delay_ms 400 Fidus Systems Inc FMCs by Fidus amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd amp cmd amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd executeCommand amp cmd executeCommand amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCo
22. D BALUN TERMINATION sse ADC2_LVDS_FRAME PN 1 8V enur OE pE BALIN OBALUN oll nes 1 ADC2A CML PN E lt lt Nun 55 3 B vw 3i BALUN BALUN 500 TE TERMINATION sew ADC3_LVDS_FRAME PN 1 8V eners Oe 13 E D S BALUN BALUN ES ADC3A CML PN FMC AD o W ud EE m lt lt TERMINATION C3 ra ADC3B CML PN CONNECTOR SSMC oe O ne m E S EA BALUN BALUN 500 NXP TERMINATION ADC4_LVDS_FRAME PN 1 8V AF INPUT EI 1 2 l1 Sn ee es ee C4 J SSMC 7 ADC4B_CML PN RF INPUT 8 Emi ADC SCRAMBLER 1 8 ADC SCRAMBLER VADJ BALUN BALUN 500 NXP ADC SPI BUS 1 8V ADC SPI VADJ 4435 ITCHER SYNQ 1 2 3 3V SWITCHER SYNQ 1 2 VADJ TERMINATION LEVEL CLK INPUT 1 EV CLK SPI BUS 3 3V CLK SPI VADJ ae 3 oino qos coe 63 TRANSLATE e CLKGEN RESETn 3 3V CLKGEN RESETn VADJ a Y SYNC 3 3V SYNC VADJ o VCXO paeem OSCIN LOW JITTER CLOCK LOOP G E N E RATO R 74AVC1T45 74AVC8T245 SAMTEC FILTER ASP 134488 01 2 FPGA LVDS 2 1 CLK PN 120 MHz 2 FPGA LVDS3 CLK PN 2 FPGA LVDS SYSREF PN TI LMK04828 O LOCK TESTPOINT Figure 1 Detailed Block Diagram of the FSF AD8200A Fidus Systems Inc FMCs by Fidus Page 3 of 36 lac VKEF A M2C NOT CONNECTED VKEF B M2C NOT CONNECTED VIO B M2C 2 5V 1 15A max 12V FMC 3V3_FMC VADJ EEPROM 2K
23. D8200A User Manual 8 3 Performing an 8 Channel Capture The FPGA download bit configuration file supplied with the FSF AD8200A allows the VC707 Evaluation Card to use 8 large capture buffers accessible through ILA formerly ChipScope to store data incoming from the FSF AD8200A daughter card Each buffer can hold 65 536 samples Simultaneous capture on all 8 channels begins when the Vivado ILA manual trigger button labeled gt gt is left clicked and continues until the capture buffers are full Once a capture is complete the raw data can be exported for external analysis by entering the following command on the TCL command line at the bottom of the Vivado window write hw ila data filename zip upload ila hw_ila_1 The command window will indicate where it has placed the captured data file once the file has been completely written Fidus Systems Inc FMCs by Fidus Page 27 of 36 FSF AD8200A User Manual O ORDERING INFORMATION Part Number Description FSF AD8200A DS FSF AD8200A demonstration unit early release FSF AD8200A FSF AD8200A production unit 10 WARRANTY The FSF AD8200A comes with a 6 month warranty The warranty is governed by Fidus Systems Terms of Sale Fidus Systems Inc FMCs by Fidus Page 28 of 36 FSF AD8200A User Manual 11 APPENDIX A INIT SCRIPT CONTENTS NOTES ws write
24. FSF AD8200A FMC card The majority of this supervisory activity is completed by SPI bus however there are also other signals that make up this host interface These control signals are discussed in this section 6 5 1 SPI Interface The SPI bus provides the main control system for the onboard clock generator and each individual ADC on the FSF AD8200A It is important to note that this is a 3 wire SPI bus implementation thus SDIO is bidirectional and directionality must be carefully considered To avoid bus contention it is critically important to control the SDIO direction at the appropriate time The following schematic capture shows the SDIO level shifting system VADJ 1 8 or 3 3V so that the FPGA designer understands how to avoid SDIO bus contention issues C2M VADJ SDIO DIR must be switched at the appropriate time The SDIO signal to all 4 ADCs at the VADJ voltage SATAY ITASDRL IL Sangha He Du il 5 pipi Bars Tamara RoHS The SDIO signal to all 4 ADCs at 1 8V The SDIO signal to the LMK04828B clock generator 9 ting buffers at the VADJ voltage SDIO directional control signal TO AVOID BUS CONTENTION AND POSSIBLE DAMAGE TO EITHER THE DEFAULT DIR B gt A CARRIER OR FMC aM re IT IS CRITICAL THAT THIS SIGNAL CHANGE AT THE TED Ti DIR GHI T APPROPRIATE mul db m cm TIME iC Sangia Bit Dual Supply Bus Transceiver RoHS The SDIO signal to the EFA
25. SF AD8200A User Manual Table of Contents 1 SAFETY INFORMATION AND PRODUCT AND COMPLIANCE 1 2 GENERAL OVERVIEW E S AA 2 3 GLOSSARY TRENT T TR 4 4 REFERENCE DOGUMENTS 3 uci seu tuetur eme exo doe toa oe NUS ven ee vue oed eve ve vx coe Ye o Fe ev Eo VER ER ven eU No desea eve e ove Uude 4 5 DETAILED SPEGIFIGATIONS k es ecu d eod coe ate ee ret sata idco a to ne 5 5 PERFORMANCE M CIT I D II E CL T D D E 5 Jbputtredquency RESPONSE muisire acuta bid EUR dn vara a Dee cuo vdd ea t ca 5 512 SNR SFDR and FAD PIOS idtm MEE Rome E ERES MERPADDPEEL T 513 Adjacehnt Channel COUP Qs DR a EAD 8 ove dntenmnoduletorissaveetensdees adieu dase a 11 6 INTERFACES cte c 13 6 1 FMC INTERFACE PIN SUPPORT AND OTHER REQUIREMENTS cccecceecceeeceuceececeeeuueeneeeeeeeueeneeueeeueeeneaeneeeueanueeneenueees 13 6 1 1 FSF AD8200A HPC FMC pin assignment and definition eeeeeeeeeeeeeeeeeee enne 14 6 1 2 FMC Voltage and Current requirements esseeeeeeeieeeeeeeee nennen nennen nnn nnn nnn n nhan aan 16 6 2 9 M ltiGigabit Serial Communications LINES acceso abet eden deceit 16 6 2 ADC P
26. SNR SFDR and THD Plots The following plots provide the basis for the numbers in the typical performance table above MHz 2 FS 1 5 dB m E 5 PE SHR 69 0 dB bere SFDR 83 2 dB THD 73 0 dB Power dB Frequency MHz Figure 4 typical spectrum Fin24 989 MHz Amp FS 1 5dB Nyquist Zone 1 183 551 MHz p F2 179dB cha I i I T T I I x 4g SHR 617 dB y amp F R 70 2 dB THD 74 8 dB Power tB I j L 1 J FM il n n mii ll AI LI a dd 1 IT 14 Lh LL I il D in 20 3 ap Frequency MHz Figure 5 typical spectrum Fin 183 561 MHz Amp FS 1 9dB Nyquist Zone 3 Fidus Systems Inc FMCs by Fidus Page of 36 FSF AD8200A User Manual 5 1 3 Adjacent Channel Coupling To limit coupling the FSF AD8200A has strategic ground plane design as well as individual front end Shields The following information describes the typical measured coupling between channels When referred to adjacent and second adjacent are defined as SSMCs 2nd 2nd Adjacent Fin Adjacent victim adresser victim Adjacent Adjacent victim victim Figure 6 Coupling terminology explanation Input C coupling to B amp D dB vs Frequency MHz Figure 7 Typical Channel Channel Crosstalk input C to adjacent channels Fidus Systems Inc FMCs by Fidus Page 8 of 36 FSF AD8200A User Manual Input C
27. ULT DIB B 5A LMK04828B clock generator at the 3 3V Figure 15 SDIO buffer direction control Fidus Systems Inc FMCs by Fidus Page 19 of 36 FSF AD8200A User Manual 6 5 1 1 Clock Generator Figure 16 presents the SPI format details for communications with Texas Instrument s LMKO4828B clock generator distribution device The CS line is active low and corresponds to the CSn signal on pin G12 LAO8 P of the FMC connector SDIO WRITE SCLK Read V2 Dat lid acti ad um Figure 16 SPI Communications with the LMKO4828B Clock Generator Data applied to the SDIO pin is clocked into the device on the rising edges of SCK A rising CS line completes the SPI transaction Note that activity on any of the SPI lines while the LMKO4828B is locked may degrade the phase noise of the output clocks This can happen when device registers are being accessed or to a lesser degree when other devices sharing the same level translator IC have SPI transactions occurring The design of the FSF AD8200A isolates the FMC SPI lines from the device SPI lines in an effort to minimize SPI noise contamination A slew rate of 30 volts usec or faster is recommended for all SPI signals The software code contained within the provided bitfile provides an example default configuration for SPI communications and register configuration for the LMKO4828B Other configuration settings are of course possible
28. Yg_PD set DCLKout4_ADLY_PD decodeCommand ws LMKO4828 0117 11 decodeCommand ws LMKO4828 0118 1C decodeCommand ws LMKO4828 0119 55 Ox decodeCommand ws LMKO4828 O11B OO DCLKout6 MUX to OxO decodeCommand ws LMKO4828 011C 22 decodeCommand ws LMKO4828 011D OO decodeCommand ws LMKO4828 011E FO DCLKout6 ADLYg PD set DCLKout6 ADLY PD decodeCommand ws LMKO4828 O11F 11 decodeCommand ws LMKO4828 0120 OE decodeCommand ws LMKO4828 0121 55 Ox decodeCommand ws LMKO4828 0123 00 DCLKout8_MUX to OxO decodeCommand ws LMKO4828 0124 22 decodeCommand ws LMKO4828 0125 00 decodeCommand ws LMKO4828 0126 FO DCLKout8 ADLYg PD set DCLKout8 ADLY PD decodeCommand ws LMKO4828 0127 15 decodeCommand ws LMKO4828 0128 OE decodeCommand ws LMKO4828 0129 55 to Ox5 decodeCommand ws LMKO4828 0128 OO DCLKout10 MUX to OxO decodeCommand ws LMKO4828 012C 22 decodeCommand ws LMKO4828 012D OO decodeCommand ws LMKO4828 012E FO amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd executeCommand executeCommand executeCommand executeCommand clear DCLKout4_ADLY to OxO clear DCLKout4 MUX to OxO set SDCLKout5_DDLY to 0x1 clear SDCLKout5 ADLY EN clear SDCLKout5 ADLY to OxO set DCLKout4 DDLY PD set DCLKout4 HSg PD set L NA NN ee ee amp cmd executeCommand amp cmd set CLKout5_FMT to Ox1 set CLKout4_FMT to Ox1 amp cmd executeCommand amp cmd DCLKout6_DIV t
29. age should not be disposed of in normal household waste as products with electrical or electronic components can be recycled and could also be harmful to the environment if sent to landfill 5 This product is intended for incorporation into an apparatus that will carry the FCC 15 declaration Warning Any unauthorized modification to this equipment may cause violation of the FCC or EMC rules resulting in the revocation of the authorization to operate the equipment Notes d This equipment must be disposed of and treated properly in compliance with WEEE directive 2012 19 EU This equipment in ESD sensitive and must be handled using industry accepted methods to help avoid damage from discharge events This includes the wearing of grounding straps prior to and while handling the circuit board S Sensitive electronic device Fidus Systems Inc FMCs by Fidus Page 1 of 36 FSF AD8200A User Manual 2 GENERAL OVERVIEW The Fidus Systems FSF AD8200A provides 8 channels of high performance analog capture in a VITA 57 1 2010 compatible conduction cooled single width FMC form factor Performance specifics include Contains four IDT ADC1443D200 dual analog to digital converters JESD204B interface for low pin count low noise and deterministic latency Up to 185 MSPS conversion rate on each channel default L8OMSPS 14 bit conversion on each channel Capable of sampling jitter below 100fsec RMS1 Extremely low channel to channel crossta
30. ations The FSF AD8200A is designed as a conduction cooled single width FMC That being said it is impossible to predict every conduction cooled situation It is also very possible that conduction cooling will not be supported by the selected carrier card Ultimately it is the user s responsibility to ensure that their cooling solution ensures that they are not exceeding the temperature requirements of the FSF AD8200A components this would void the warranty To mitigate thermal concerns each FSF AD8200A comes with a heat sink shown installed below This heat sink was designed to maintain appropriate thermal margins in a natural convection environment with ambient temperatures reaching a maximum of 45 C Thermal margins can be maintained at higher ambient temperatures if the user employs forced air flow appropriately 5 Operation over the industrial temperature range of 40 to 85 C is possible but not warranted all components are rated for this range but thermal margins will depend on conduction and airflow Fidus Systems Inc FMCs by Fidus Page 22 of 36 FSF AD8200A User Manual Figure 18 FSF AD8200A with heat sink installed There may be scenarios where the end user must remove the heat sink e g carrier card interference In this situation the user must provide forced air and is solely responsible for ensuring that the board maintains adequate thermal margins In summary the FSF AD8200A with its heat sink installed do
31. com 2010 ISBN 1 IDT ADC1443D datasheet p www idt com document dst adc1443d ser datasheet TI LMKO4828B Clock http www ti com lit gon Imk04828 datasheet Generator Level shifter htto www ti com lit ds symlink sn74avc8t245 pdf Level shifter htto www ti com lit ds symlink sn74avc1t45 pdf EEPROM hito www nxp com documents data_sheet PCF85102C 2 pdf CTS VF R3306 120MHz VCXO http www ctsvalpey com Collateral Documents English US Products FrequencyControl Oscillators VCXO R3306 pdf Table 1 Reference Documents Fidus Systems Inc FMCs by Fidus Page 4 of 36 FSF AD8200A User Manual 5 DETAILED SPECIFICATIONS 5 1 Performance The following sections present typical performance results under the documented test conditions Test Conditions Ambient temperature 25 5 C Description Controlled laboratory environment Test Platform Xilinx VC7O7 development kit Sample Rate 178 4 7 MSPS Min Max Unit Conditions Comments Usable analog input BW 110700 MHz S41 better than 7dB Fin 4 989MHz 1 5dBFS dBc dBc dBc Coupling adjacent dB averaged based on both adjacent results dB averaged based on both 2nd adjacent results Coupling 2 adjacent Fin 183 561MHz 1 9dBFS dBc dBc dBc Coupling adjacent dB averaged based on both adjacent results dB averaged based on both 2nd adjacent results Table 2 Typical Performance at 4 989 and 183 561MHz Coup
32. d executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmdQd amp cmd executeCommand amp cmd 7 7 7 7 decodeCommand ws JESD204B 04 O1 amp cmd executeCommand amp cmd decodeCommand ws JESD204B OC 40008 amp cmd executeCommand amp cmd decodeCommand ws JESD204B OO 790 amp cmd executeCommand amp cmd decodeCommand ws AD1443D 4 081E O8 decodeCommand ws JESD204B OO 712 xil_printf n rlnfo Done Initialization Fidus Systems Inc FMCs by Fidus amp cmd executeCommand amp cmd Page 36 of 36
33. decodeCommand ws AD1443D 2 0043 C7 decodeCommand ws AD1443D 205160 4A decodeCommand ws AD1443D 2 0822 01 decodeCommand ws AD1443D 2 0810 CO decodeCommand ws AD1443D 2 0811 40 decodeCommand ws AD1443D 2 0812 OA decodeCommand ws AD1443D 2 081E 08 decodeCommand ws AD1443D 2 O86B 02 decodeCommand ws AD1443D 205660 02 decodeCommand ws AD1443D 2 0872 04 decodeCommand ws AD1443D 3 0803 00 decodeCommand ws AD1443D 3 0802 08 decodeCommand ws AD1443D 3 0100 d1 decodeCommand ws AD1443D 3 0200 01 decodeCommand ws AD1443D 3 OOff 80 decodeCommand ws AD1443D 3 0102 decodeCommand ws AD1443D 3 0103 66 decodeCommand ws AD1443D 3 0012 10 decodeCommand ws AD1443D 3 0108 a3 decodeCommand ws AD1443D 3 010a cO decodeCommand ws AD1443D 3 0154 01 decodeCommand ws AD1443D_3 0155 03 decodeCommand ws AD1443D 3 0156 d8 decodeCommand ws AD1443D 3 0160 ff decodeCommand ws AD1443D 3 0161 17 decodeCommand ws AD1443D 3 0170 10 decodeCommand ws AD1443D 3 0171 10 decodeCommand ws AD1443D 3 0400 30 delay ms 400 Fidus Systems Inc FMCs by Fidus amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd
34. du e exu ee 2b 8 2 SORTWARE INS TACEATION E EE aura Dosab esce sud rs arated coc ev 2b 8 3 PERFORMING AN S CHAN NPI OA TU RE c esses tici iere le raotde uv esder tud is Laut r aaaea aaa 27 9 ORPERING 28 10 a ca 28 11 APPENDIX A 5 5 29 Fidus Systems Inc FMCs by Fidus Page ii of ii FSF AD8200A User Manual 1 SAFETY INFORMATION AND PRODUCT AND COMPLIANCE LIMITATIONS 1 This product is designed for use and operation by an experienced electrical engineer or someone with similar experience knowledge and capabilities 2 This product is not an apparatus in accordance with the definition in EMC directive 2004 108 EC it is intended to be incorporated into an apparatus that is compliant to EMC directive 3 To comply with the LVD directive 2006 95 EC all the power sources for this card 12V 3 3V etc have to comply with LPS requirements as defined in IEC 60950 1 4 This equipment must be disposed of and treated properly in compliance with WEEE directive 2012 19 EU any product marked with this im
35. equired Clock intended for JESD204B core reference clock to be half of the sampling frequency by default 9OMHz Clock intended for JESD204B core reference clock typically not required M2C FPGA LVDS2 CLK P N M2C FPGA LVDS3 CLK P N SPI Bus C2M ADC 4 1 CSn VAD C2M C2M_CLKGEN_VADJ_CSr VAD C2M C2M VADJ SCLK VAD C2M C2M_VADJ_SDIO_CLKGEN VADJ BIDIR C2M_VADJ_SDIO_ADC VADJ BIDIR C2M SDIO DIR VAD C2M to the I2C bus FMC_SCL LVITL C2M SDA LVITL BIDIR EEPROM only pce ee ee l JTAG JTAG unused TCK TMS TRST L all unconnected LVTTL C2M LVTTL M2C MISC CONTROL C2M_VADJ_SWITCHER_SYNQ 2 1 VADJ C2M Clock signals used to synchronize the two onboard switchers Default is 45OkHz and each are expected to be 180 out of phase 2 O Reset clock generator 1 Clock generator active C2M Synchronization signal to LMKO4828B clock generator typically not required CAM 0 Disable ADC scramblers M2C Trigger signal from front bezel Either rising or CLKGEN_VADJ_RESETn VADJ CLKGEN_VADJ_MAN_SYNCn VADJ C2M_VADJ_ADC4 1_SCRAMBLER VADJ M2C_VADJ_EXT_TRIGGER VADJ falling edge active depending on FPGA code CARD D LVTTL M2C 4 12kQ to ground Fidus Systems Inc FMCs by Fidus Page 15 of 36 FSF AD8200A User Manual CLK_DIR LVTTL M2C 10kQ to 3P3V C2M LVTTL CAM O Disable power on FMC 1 Enable power on FMC PG_M
36. es not require conduction cooling and can operate reliably in a natural convection environment up to 45 C Removing the heat sink is not recommended but if required ensure and monitor that sufficient air flow is applied for the given ambient temperature conditions Parameter Min Typ Max Unit Conditions Comments Onboard Power Dissipation TBD W All converters active and sampling at 180MSPS Table 11 Power Dissipation 7 3 Mechanical 7 3 1 Front Bezel Faceplate The following diagram illustrates the FSF AD8200A s front bezel construction The front bezel is attached to the FMC by two M2 5 machine screws QDQaemoawuonrd se Figure 19 FSF AD8200A Front Bezel Fidus Systems Inc FMCs by Fidus Page 23 of 36 FSF AD8200A User Manual 7 3 2 Heat Sink The following diagram illustrates the FSF AD8200A s custom heat sink Compressible thermal pads provide the buffer and ensure a good thermal connection between the onboard components and the heat sink 8X 1 6 THRU ALL r J amp R SEE NOTE 5 M2X0 4 6H THRU ALL 2X 2 1 THRU ALL t M2 5X0 45 6H THRU ALL MARKED A Figure 20 FSF AD8200A Heat Sink The heat sink is connected to the carrier card or conduction cooling solution using ten machine screws 8x M2 2x M2 5 Loosely fit the heat sink on with all screws first then proceed to tighten in a criss cross pattern to help ensure the equal pressure Avoid over t
37. hen receiver is the FPGA Each ADC sends its conversion data over high speed serial current mode logic lines CML P CML N These are received by multi gigabit transceiver MGT IO in the FPGA and are compatible with JESD204B protocol requirements The bit rate carried on each serial interface is 20 times the 3 Due to framing and other overhead the serial line rate is greater than simply the sample rate multiplied by the converter resolution Fidus Systems Inc FMCs by Fidus Page 16 of 36 FSF AD8200A User Manual ADC sample rate yielding a 3 6Gbps rate on each of the 8 lanes and providing an aggregate data bandwidth of 28 8Gbps It is important to note that FMC carrier cards are not required to support all 10 of the gigabit transceiver lanes specified in the FMC HPC specification It is always important to validate the number of MGTs connected to the FMC connector 6 2 ADC Analog Inputs The 8 analog inputs of the FSF AD8200A labeled A through H are each ESD protected and AC coupled to a 500 termination The following table describes the expected operation of these inputs Parameter Min Typ Max Unit Conditions Comments Inputimpedance 5 Ja impuRetumloss 2 dB 5MHzio14OMHz Absolute donotexceed 4 Vep Peak power of 19dBm FS Full Scale Input 2 25 Vpp By default but each Range ADC can be programmed to lower FS values in 1dB steps Table 6 Analog Input Requirement
38. ightening as this may result in damage to the heat sink the circuit board and or the carrier card Fidus Systems Inc FMCs by Fidus Page 24 of 36 FSF AD8200A User Manual 8 DEMONSTRATION This section describes how to experiment with the FSF AD8200A paired with a VC707 using the Fidus provided bitfile For detailed instructions refer to FSF AD8200A Quick Start Guide 8 1 Hardware Installation Installation of the FSF AD8200A mezzanine card is as simple as plugging the FMC connector onto a carrier card with a compatible HPC FMC connector all power is supplied through the FMC connection It is recommended that the carrier card not be powered when the FSF AD8200A is installed or removed Follow normal ESD prevention procedures and avoid flexing both the mezzanine and carrier boards as much as possible For the VC 707 use the FMC connector closest to the center of the board labeled FMC2 HPC Once the HPC FMC connector is seated power can be applied to the main carrier board The green power LED on the FSF AD8200A should come on The mezzanine card is now ready for SPI configuration followed by analog inputs on any or all of the SSMC input connectors In no case should the input level applied to any SSMC analog input channel exceed 4 volts peak to peak 8 2 Software Installation The FSF AD8200A software distribution includes an empty Vivado Project called FSF AD8200A zip Once unzipped it creates the FSF AD8200A
39. is the reference to which output sine waves from the signal generator are locked Supplying this 10 MHz reference to the External Clock Input will precisely lock the FSF AD8200A ADC sampling clocks to the 10 MHz reference frequency This capability is useful when post capture FFT analysis is to be performed on sine wave inputs applied to the ADCs If you would like to learn more about this capability contact Fidus Systems for related documentation or assistance with other synchronization options 6 4 External Trigger Input The External Trigger SSMC connector input labeled TR is terminated in a shunt 4 12k0O resistor and ESD protection device The signal is DC coupled to a buffer gate that sends its output through a 220 series termination directly to the FMC connector Fidus Systems Inc FMCs by Fidus Page 18 of 36 FSF AD8200A User Manual External Trigger Input Levels specification Parameter Min Typ Max Unit Conditions Comments Input Type lVWMOSAVTL Absolute donotexceed 05 65 v CETT SR rv M if oe v Sewe 80 ves Table 8 External Trigger Input Requirements Note that the standard FPGA configuration supplied with the FSF AD8200A does not make use of signals from the External Trigger input Contact Fidus Systems if you need help applying this input in your own application 6 5 Communication and Control The carrier card s FPGA is responsible for configuring and controlling the
40. ling 2 adjacent Notes a These results were captured without the heat sink and with additional applied air flow The heat sink was added for customer ease of adoption and is not expected to affect the results presented within this section 5 1 1 Input Frequency Response The ADC1443D converter claims a typical analog input bandwidth of 1GHz On the FSF AD8200A both the low end and high end frequency response is limited by front end components filters The following plots describe the typical frequency performance of the inputs when swept Fidus Systems Inc FMCs by Fidus Page 5 of 36 FSF AD8200A User Manual Tr6 511 Log Mad 5 000dB Ref 0 000 Tr 511 Log Mag 5 000 dr 511 Log mag 5 5 000 1 Start 300 kHz IFBW 70 kHz Stop 1 2 GHz a Meas 5 Figure 2 Overlay of typical Return Loss S11 for all 8 Analog Input Channels note log scale on x axis The following plot describes the amplitude response and similarity of two analog inputs Channel C and Channel D Input C amp D Amplitude Response dB vs Frequency MHz 300 400 500 600 700 800 900 1000 Figure 3 Typical Amplitude Response vs Frequency Fidus Systems Inc FMCs by Fidus Page 6 of 36 FSF AD8200A User Manual 5 1 2
41. lk Input 3 dB bandwidth of gt 500MHz The product has planned hardware compatibility with the following Xilinx evaluation boards Virtex VC7O7 Virtex VC7092 Kintex KC705 capable of 4 lanes due to the MGT assignment Virtex 605 capable of 2 JESD204B cores of 4 lanes each The VC707 package includes all necessary FPGA code files to Form a single link 8 lane JESD204B connection Either load a default setting to all configuration registers or experiment with custom settings Capture ADC samples from each converter into FPGA block memory resources Access the captured ADC samples through ILA formerly known as ChipScope where they may then be exported for post processing e Access all FSF AD8200A registers through a command line UART terminal session Figure 1 presents a detailed block diagram of the FSF AD8200A functionality 1 Integrated phase noise in a 12kHz 20MHz offset from a 180MHz clock frequency Although the existing hardware is theoretically compatible with these development boards at the time of writing Fidus has only verified operation with the VC707 development kit Fidus Systems Inc FMCs by Fidus Page 2 of 36 FSF AD8200A User Manual TERMINATION NXP SSMC 74LVC1G125 TRIGGER INPUT LVTTL 5V TOL 4KQ TERMINATION sew L ADC1_LVDS_FRAME PN 1 8V m tote EL BAUN AUN Tue me ADC1A CML PN M e le ae TERMINATION ADC1 B CM L PN wee er E30 EL BALUN BALUN 500 NXP ADC1443
42. mmand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmdq executeCommand amp cmd SS SS Sees amp cmady amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd 7 N NS amp cmd executeCcCommand amp cmd amp cmd amp cmd amp cmd amp cmd executeCommand amp cmd executeCommand amp cmdQd executeCommand amp cmd executeCommand amp cmd Se ee amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd Page 35 of 36 FSF AD8200A User Manual decodeCommand ws AD1443D_4 0043 C7 decodeCommand ws AD1443D_4 081C 4A decodeCommand ws AD1443D 4 0822 01 decodeCommand ws AD1443D 4 0810 CO decodeCommand ws AD1443D 4 0811 40 decodeCommand ws AD1443D 4 0812 OA decodeCommand ws AD1443D 4 O86B 02 decodeCommand ws AD1443D 4 O86C 02 decodeCommand ws AD1443D 4 0872 04 7 amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cm
43. mmand amp cmd clear DOLKoutO DDLY ADLY to OxO clear DCLKoutO ADLY MUX amp cmd executeCommand amp cmd set SDCLKout1_MUX set SDCLKout1_DDLY to Ox1 amp cmd executeCommand amp cmd clear SDCLKout1 ADLY EN clear SDCLKout1_ADLY to OxO amp cmd executeCommand amp cmd set DCOLKoutO DDLY PD set DCLKoutO HSg PD set amp cmd executeCommand amp cmd set CLKout1_FMT to Ox1 set CLKoutO FMT to Ox5 amp cmd executeCommand amp cmd set DCLKout2_DIV to Oxe amp cmd executeCommand amp cmd set DCLKout2_DDLY_CNTH to Ox5 set DCLKout2_DDLY_CNTL to amp cmd executeCommand amp cmd clear DOLKout2 DDLY ADLY to OxO clear DCLKout2 ADLY MUX amp cmd executeCommand amp cmd set SDCLKout3 MUX set SDCLKout3_DDLY to Ox1 amp cmd executeCommand amp cmd clear SDCLKout3 EN clear SDCLKout3_ADLY to OxO amp cmd executeCommand amp cmd set DOLKout2 DDLY PD set DCLKout2 HSg PD set set CLKout2 3 PD set SDCLKout3 PD amp cmd executeCommand amp cmd clear CLKout3 FMT to OxO clear CLKout2_FMT to OxO amp cmd executeCommand amp cmd set CLKout4_DIV to Ox1c amp cmd executeCommand amp cmd set DCLKout4_DDLY_CNTH to Ox5 set DCLKout4_DDLY_CNTL to Page 29 of 36 FSF AD8200A User Manual decodeCommand ws LMKO4828 0113 0 decodeCommand ws LMKO4828 0114 02 decodeCommand ws LMKO4828 0115 00 decodeCommand ws LMKO4828 0116 FO DCLKout4_ADL
44. mmand amp cmd set SDCLKout11 MUX set SDCLKout11 DDLY to amp cmd executeCommand amp cmd clear SDCKLout11 ADLY EN clear SDCLKout11 ADLY to OxO amp cmd executeCommand amp cmd set DOLKout10 DDLY PD set DCLKout10 HSg PD set DCLKout10_ADLYg_PD set DCLKout10 ADLY PD decodeCommand ws LMKO4828 O12F 15 decodeCommand ws LMKO4828 0130 OE decodeCommand ws LMKO4828 0131 55 to Ox5 decodeCommand ws LMKO4828 0133 00 DCLKout12_MUX to OxO Fidus Systems Inc FMCs by Fidus amp cmd executeCommand amp cmd set CLKout11_FMT to Ox1 set CLKout1O_FMT to Ox5 amp cmd executeCommand amp cmd set DCLKout12_DIV to OxOe amp cmd executeCommand amp cmd set DCLKout12_DDLY_CNTH to Ox5 set DCLKout12_DDLY_CNTL amp cmd executeCommand amp cmd clear DCLKout12_ADLY to OxO clear DCLKout12_ADLY_MUxX clear Page 30 of 36 FSF AD8200A User Manual decodeCommand ws LMKO4828 decodeCommand ws 828 decodeCommand ws LMKO4828 0134 22 0135 00 0136 FO amp cmd executeCommand amp cmd set SDCLKout13 MUX set SDCLKout13_DDLY to 0x1 amp cmd executeCommand amp cmd clear SDCLKout13 ADLY EN clear SDCLKout13 ADLY to OxO amp cmd executeCommand amp cmd set DOLKout12 DDLY PD set DCLKout12 HSg PD set DCLKout12 ADLYg PD set DCLKout12 ADLY PD decodeCommand ws LMKO4828 decodeCommand ws LMKOA4828 OxO decodeCommand ws LMKO4828 decodeCommand ws LMKO48
45. mmand ws LMKO4828 decodeCommand ws LMKOA4828 decodeCommand ws LMKO4828 POL clear PLL2 CP TRI decodeCommand ws LMKOA4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 decodeCommand ws 828 decodeCommand ws LMKO4828 x decodeCommand decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 ws LMK0O4828 decodeCommand ws LMKO4828 decodeCommand ws LMKO4828 0158 96 0159 00 015A 19 0158 DF 015C 20 015D 00 015 00 O15F OB 0160 00 0161 01 0162 44 0163 00 0164 00 0165 OC 017C 15 017D 33 0166 00 0167 00 0168 OA 0169 59 016A 20 0168 00 016C OO 016D 00 O16E 13 0173 00 1 00 1 00 1 53 0144 FF amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd set CLKin2 R 7 0 to Ox96 set PLL1 N 13 8 to set 1 N 7 0 to 0x19 set PLL1 WND SIZE to Ox3 set PLL1 CP POL set PLL1 GAIN executeCommand executeCommand executeCommand executeCommand wer wer 5 8 woe amp cmd executeCommand amp cmd set PLL1_DLD_CNT 13 8 to 0x20 amp cmd executeCommand amp cmd set PLL1_DLD_CNT 7 0 to OxOO amp cmd executeCommand amp cmd set PLL1 R DLY to OxO set Ox15E O O PLL1_R_DLY to OxO amp cmd executeCommand amp cmd set PLL1 LD MUX to OxO1 set PLL1 LD TYPE to Ox3 amp cmd executeCommand amp cmd
46. o Ox1c amp cmd executeCommand amp cmd set DCLKout6_DDLY_CNTH to Ox5 set DCLKout6_DDLY_CNTL to amp cmd executeCommand amp cmd clear DCLKout6_ADLY to OxO clear DCLKout6_MUX clear amp cmd executeCommand amp cmd set SDCLKout MUX set SDCLKout DDLY to Ox1 amp cmd executeCommand amp cmd clear SDCLKout ADLY EN clear SDCLKout ADLY to OxO amp cmd executeCommand amp cmd set DCLKout6_DDLY_PD set DCLKout6 96 PD set amp cmd executeCommand amp cmd set CLKout FMT to Ox1 set CLKout6_FMT to Ox1 amp cmd executeCommand amp cmd set DCLKout8_DIV to Oxe amp cmd executeCommand amp cmd set DCLKout8_DDLY_CNTH to Ox5 set DCLKout8_DDLY_CNTL to amp cmd executeCommand amp cmd clear DCLKout8_ADLY to OxO clear DCLKout8_MUX clear amp cmd executeCommand amp cmd set SDCLKout9 MUX set SDCLKout9 DDLY to 0x1 amp cmd executeCommand amp cmd clear SDCLKout9 ADLY EN clear SDCLKout9_ADLY to OxO amp cmd executeCommand amp cmd set DCLKout8_DDLY_PD set DCLKout8_HSg_PD set amp cmd executeCommand amp cmd set CLKout9 FMT to Ox1 set CLKout8_FMT to Ox5 amp cmd executeCommand amp cmd set DCLKout10_DIV to Oxe amp cmd executeCommand amp cmd set DOLKout10 DDLY CNTH to Ox5 set DCOLKout10 CNTL amp cmd executeCommand amp cmd clear DOLKout10 ADLY to OxO clear DCLKout10 ADLY MUX clear amp cmd executeCo
47. p cmd executeCommand amp cmdq amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd cmd amp cmd executeCommand e cmd executeCommand amp cmd iF amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd jr amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd e cmd executeCommand amp cmd e cmd executeCommand amp cmd e cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd 7 amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cma amp cmd executeCommand amp cmd Page 33 of 36 FSF AD8200A User Manual decodeCommand ws AD1443D_2 0160 ff decodeCommand ws AD1443D_2 0161 17 decodeCommand ws AD1443D_2 0170 10 decodeCommand ws AD1443D_2 0171 10 decodeCommand ws AD1443D_2 0400 30 delay_ms 400 decodeCommand ws AD1443D_2 0004 08 delay_ms 400 decodeCommand ws AD1443D_2 0004 10 delay_ms 400 decodeCommand ws AD1443D_2 0004 20 delay_ms 400
48. s Note that a small amount of sampling clock energy including harmonics leaks out from each ADC input and appears at the corresponding SSMC connector This is normal for un buffered high speed ADCs and is caused by the internal sampling switches For the FSF AD8200A with the ADC1443D devices this level is typically 47dBm 3 dB at the second harmonic of the sampling frequency as measured at each of the 8 SSMC connectors 6 3 External Clock Input The External Clock SSMC connector input labeled CL is ESD protected and AC coupled to a 500 termination before proceeding to the clock generator chip The external clock input supports both sine and square wave inputs as per the requirements below Min Conditions Comments a T E 115 dBm measured on 500 1446 dBm measured on 500 500 v 40 60 Table 7 External Clock Input Requirements 4 Refer to Input Return Loss plot Figure 2 Fidus Systems Inc FMCs by Fidus Page 17 of 36 FSF AD8200A User Manual This input can be left open and the 8 channel capture application included with the FSF AD8200A will operate correctly but with a small frequency error in the ADC sampling clock typically no more than 25ppm If synchronization of the ADCs sampling clock frequency with an external reference is desired the External Clock input can be driven with a 10 MHz source This is commonly available at the back of many signal generators and
49. set SYSREF PULSE CNT to 0x3 amp cmd executeCommand amp cmd clear PLL2 NCLK MUX clear PLL1 NCLK MUX clear FB MUX to amp cmd executeCommand amp cmd set SYSREF DDLY PD amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd amp cmd executeCommand amp cmd set SYNC EN amp cmd executeCommand amp cmd amp cmd executeCommand amp cmdq this is a fixed value not sure why we write it amp cmd executeCommand amp cmd set CLKinO EN set CLKin2_TYPE set CLKin1_TYPE set amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd amp cmd executeCommand executeCommand executeCommand executeCommand executeCommand executeCommand set CLKin1 OUT MUX to Ox1 set CLKinO OUT MUX to Ox2 clear CLKin SELO MUX to OxO set CLKin SELO TYPE to Ox2 clear CLKin SEL1 MUX to OxO set CLKin SEL1 TYPE to Ox2 clear RESET MUX to OxO set RESET TYPE to Ox2 Set TRACK EN set MAN DAC EN set MAN DAC 9 8 to Ox2 set MAN DAC 7 0 to amp cmd executeCommand amp cmd set DAC TRIP LOW to OxOO amp cmd executeCommand amp cmd set DAC CLK MULT to Ox3 set DAC TRIP HIGH to OxOO amp cmd executeCommand amp cmd set DAC CLK CNTR to amp cmd executeCommand amp cmd set HOLDOVER PLL1 DET set HOLDOVER LOS DET set NE NN N i
50. tion FMC HPC Connector Details Unshaded Cells are No Connect NC and list the VITA pin name Shaded Cells list the VITA pin name followed by FSF AD8200A connection details LOOK Eod Ho o Good Fo E o D oC o B oA I EN umm VREF B M2C GND VREF A 2 GND PG M2C GND PG C2M GND 3P3V FMC 10K PU GND MEN GND CLK3 BIDIR P PRSNT M2C L GND 2 FPGA LVDS SYSREFP GND HAO1 P CC GND DPO C2M P GND ADC3B CML P EE S NEM E GND CLK3 BIDIR N M2C FPGA LVDS SYSREFN GND HAO1 N CC GND DPO C2M N GND ADC3B CML N CLK2 BIDIR P GND DP9 M2C P G GND ND DP9 M2C N MICH HAO0 CC I gt Q o z Q p GND p GND s CLK2_BIDIR_N GND GND N GND E o BER DEM M GND HAO3 P GND ADC2 LVDS FRAMEP GND P GND DPO M2C P ADC3A CML P GND ADCAA CML P a moe 07MM 7 2 P HAO3 N 1 SCRAMBLER ADC2 LVDS FRAMEN HAO4 P N GND DPO M2C N ADC3A CML N GND CML N er A ooo EM 2 GND M2C VADJ EXT TRIGGER GND N GND ADC3 LVDS FRAMEP GND DP8 M2C P GND f vos wow GND 7 P GND LAO3 P GND HAO9 P ADC3 LVDS FRAMEN GND DP8 M2C N GND ho wes mow ue oce ioon ce NN P 7 N LAOA P LAO3 N HAO8 P HAO9 N GND LAOG P GND ADCAB CML P o MEME 8 6 N GND LAOA N GND HAO8 N GND LAO5 P LAOG N GND ADC4B_CML_N EE O anap
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