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1. 43 3 spy 4 7Kx9 43 3 L o wosooreot SP2 aro ee 1 o wosooreot CLPRPPPPE SnLacIrcoreso soreoorcogrnagzuSNESSZ XXX agere FERTTTT COP SANESESRSESEZ A nat 4 fitarara 008888689885555555555888888888888 AI IRQS BESs o8E 2 IRQS FFEEEEEE A3 IRQ7 88 A4 A5 AS AS RW A7 TA H AB TS A9 CF RSTI A10 A11 BR A12 BD A13 BA 4 A14 A15 BWEO A16 BWEt A17 BWE2 A18 BWE3 A19 A20 sizo A21 sizi A22 A23 R RASO SO02 Lt A24 PP8 R_RAS1 SO2 B38 A mm MCF5307FT90 A25 PP9 KR CASO DQMO RAO 7 CASUDQMO A26 PP10 IR CAST DOMI CAS1 DQM1 d A27 PP11 UR CAS2 DQM2 B A 28 CaseipaM2 ColdFire A28 PP12 LR_CAS3 DQM3 3E gt 2H CASS DOMS A29 PP13 R DRAMW pes s 34 DRAMW ASO PP14 R SRASQ os 2 94 SRAS A31 PP15 R_SCASS R24 2 95 SCAS 60 C es IN R SCKE SCKE cs 5 PA 5s 145 CS6 es Red CS6 DSCLK_TRS 143 DSCLK TRST css lt lt 685 TCK 130 1 TCK csa oe lt 6 084 DSDO_TDO 1217 DSO TDO css gt a 4 CS3 DSDI TDI t 154 DSI TD CS2 F1 ESI lt cs2 BKPT TMS 155 BKPT TMS cSt Heg Ie lt cs1 HIZ 155 Hiz cso CS0 BCLKO BCLKO vis RSTO 172 RSTO DE 2 OF K OE CLKIN_SLOW HH CLKIN ie gr PSTCLK 184 PSTCLK 8588 2x29 scl os DA POS EDGESEL EDGESEL S
2. M 3 0 MUX Inputs Corresponding Configuration 0000 8 columns 11 rows 8 MBytes 16 Mbit or 16 MBytes 64 Mbits 0001 9 columns 11 rows 16 MBytes 16 Mbits or 64 Mbits 0010 10 columns 11 rows 32 MBytes 16 Mbits or 64 Mbits 0011 8 columns 12 rows 16 MBytes 64 Mbits or 32 MBytes 64 Mbits or 128 Mbits 0100 9 columns 12 rows mE 64 MBytes 64 Mbits or 128 Mbits 0101 10 columns 12 rows 128 MBytes 64 Mbits or 128 Mbits 0110 11 columns 12 rows 256 MBytes 128 Mbits double sided 0111 8 columns 13 rows 32 MBytes 64 Mbits or 64 MBytes 256 Mbits 1000 9 columns 13 rows 64 MBytes 64 Mbits or 128 MBytes 256 Mbits 1001 10 columns 13 rows 128 MBytes 64 Mbits or 256 MBytes 256 Mbits 1010 11 columns 13 rows 512 MBytes 256 Mbits double sided 1011 1111 Reserved MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 7 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 2 2 Helper MUX Implementation An in system programmable device was chosen for the helper MUX implementation because it can easily be reconfigured while on the board The ispGAL22v 10 has a 500 gate density which easily fits the required logic for the helper MUX Using Lattice Semiconductor s freeware package ispEXPERT M System Starter Kit the ispGAL was programmed in ABEL HDL For more information on obtaining the starter kit please re
3. Freescale Semiconductor Inc FOO IO IIIS IC III IC IOI IO IOI IC IC IC IO aM 7 constants C P X Z H L C P X 2 1 0 FIO I IOI IOI IC III IOC IC IO IC I aM MO PIN 33 Mux Input 0 M1 PIN 4 Mux Input 1 M2 PIN En Mux Input 2 M3 PIN 6 Mux Input 3 CA18 PIN 2 Input ColdFire driven address 18 CA19 PIN s Input ColdFire driven address 19 CA20 PIN 9 Input ColdFire driven address 20 CA21 PIN 1 05 Input ColdFire driven address 21 CA22 PIN 11 Input ColdFire driven address 22 CA23 PIN 12 Input ColdFire driven address 23 CA24 PIN I3 Input ColdFire driven address 24 CA25 PIN 16 Input ColdFire driven address 25 CA26 PIN 23 Input ColdFire driven address 26 CA27 PIN Aty Input ColdFire driven address 27 SA8 PIN 24 Output SDRAM input address A8 SA9 PIN 19 Output SDRAM input address A9 SA10 PIN 253 Output SDRAM input address A10 SA11 PIN 175 Output SDRAM input address A11 SA12 PIN 2s Output SDRAM input address A12 SA13 PIN 20 Output SDRAM input address A13 BAO PIN 18 Output SDRAM input address BAO BA PIN 26 Output SDRAM input address BA1 select M3 M2 M1 M0 WK KKK KKK KKK KKK KKK KK KKK KK KKK KKK ck ck k W t Lattice attributes TIO RIO II IO ke RO RR koe em pLSI property CLK XCLKO CLKO pLSI property CLK CLK8MHZ SLOWCLK pLSI property ISP ON pLSI property PULLUP ON 12 Connecting the MCF5307 t
4. damaged in shipping Contact Cadre for further instructions 1 11 M5307C3 Jumper Setup 1 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The jumpers on the board are discussed in Chapter 3 However a brief discussion of the jumper settings is as follows Id Tee Ts Jumper JP1 Flash Upper Half Lower Half Boot This jumper allows the MCF5307 to boot from the lower or upper half of the flash The default is the lower half 1 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 1 JP1 Upper Lower Half BOOT Lower default 1 11 2 Jumper JP2 This jumper selects between CSO to Flash or a header Table 2 JP2 CSO select Flash default 1 12 USING THE BDM The MCF5307 has a built in debug mechanism referred to amp M The M5307C3 has the necessary connector J1 to facilitate this connection In order to use the BDM simply connect the 26 pin IDC header at the end of the BDM wiggler cable provided Motorola from P amp E Microcomputer Systems to the J1 connector No specialsettingisneeded Refer to the ColdFire User s Manual BDM Section for additional instructions 1 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc CHAPTER 2 USING THE MONITOR DEBUG FIRMWARE The M5307C3 sing
5. A28_PP1 A29_PP1 A30_PP1 A31_PP1 Mii em EN 23 swe2 24 227 pe1 NN ua 30 EA 80 31 62 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Tabl 8 Th J4 Connector pin assignment zZ ep FU z n J N n ee a a E mw Ja Jo D O1 a JP JU JU O JO jojo jt ooo a o o Ja c D D a a Be gt P gt gt gt P gt 9 lu vNliele eIe Il le ele o wv o lola lo lies o mv 5 o op ei e o la lua es Jus fas fw fw lo co o m m wm m S ple Sealing co la lis lo ov lus olola lis ln lo lo la la Im lo as D p feo feo lia lia lu H H H H H H UU JU JO JO O J D WO OIA IDIOTS O Dn 5 BD N A e O1 W D 00 D Ee v Ree 3 45 a7 49 E aM 53 Q zi Jg Tabl 9 Th J5 Connector pin assignment N SIGNAL PIN SIGNAL O NAME NO NAME BCLKOHEA 2 33 3 DER 6 Z m FJ 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc R Ea R_RASOSO R_RAS1_SO R SRAS DRAMW BEN NN The LA2 Connector pin assignment SIGNAL NAME A21 64 For More Information On This Product Go to www freescale com A23 A27 PP11 Fr
6. Even registers NATURAL16 PSTOP PSTOP rd CLDA1 wr NATURAL16 TPSR Transmit Page Start Address rd NATURAL16 ACU Address Counter Upper 6 6 NATURAL1 NATURAL reserved0 reserved2 58 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc NATURAL16 NATURAL16 NATURAL16 reserved 0x1 RCR DCR ym Receive Configuration Register rd Data Configuration Register rd 0000 0x0010 2 PSTART rd CLDAO wr Remote Next Packet Pointer Local Next Packet Pointer Address Counter Lower Odd registers NATURAL16 PSTART NATURAL16 RNPP NATURAL16 LNPP NATURAL16 ACI S NATURAL16 reservedl NATURAL16 reserved3 NATURAL16 TCR NATURAL16 IMR page2 regs NS8390 Transmit Configuration Register rd Interrupt Mask Register rd The main purpose forthissetup isto allow the use of Ethernet card NE2000 compatible to facilitateetwork download refer to chapter 2 for network download command DN The dBUG driver is 100 NE2000 compatible The Ethernet Bus interrupt request line is connected via the 2032V PLD to The on board ROM MONITOR is programmed from a network to memory supported are S Record COFF ELF or Image 3 7 THE CONNECTORS AND THE EXPANS to allow a user to download files in differ
7. IRD Internal Registers Display IRD lt module register gt This commands displays the internal registers of different modules inside the MCF5307 In the command line the module refers to the module name wher the register is located and the register refers to the specific register neede The registers are organized according to the module to which they belong The available Example ird modules on the MCF5307 are SIM UART1 UART2 TIMER M Bus DRAMC and Chip Select Refer to MCF5307 User s Manual sim sypcr display the SYPCR register in the SIM module 2 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 15 IRM Internal Registers MODIFY IRM Usage IRM module register data This commands modifies the contents of the internal registers of different modules inside the MCF5307 In the command line the module refers to the module name where the register is located register refers to the specific register needed and data is the new value to be written into that register The registers are organized according to the module to which they belong The available modules on the MCF5307 are SIM UART1 UART2 TIMER M Bus DRAMC Chip Select Refer to MCF5307 User s Manual Example irm timer tmrl 0021 write 0021 into TMR1 register in
8. To download an S record file with the name srec out the command is dn s srec out To download a COFF file with the name coff out the command is dn c coff out 2 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc To download a fileusing the default filetypewith the nam bench out the command is dn bench out To download a file using the default filename and filetype the command is dn This command requires proper Network address and parameter setup Refer to Appendix A for this procedure 2 2 For More Information On This Product Go to www freescale com 2 45 11 Usage The GO command executes Go Freescale Semiconductor Inc Execute GO lt addr gt GO target code startingat address addr The value for addr may be an absolute address specified as a hexadecimal value osymbol name the current program counter When the GO command into the target code Ifno argument isprovided the GO command begins executing instructionsat is executed alluser defined breakpoints are inserted and the context is switched to the target program Control is onlyegained when the target code encounters a breakpoint illegal instruction or other exception which causes control to be handed back to ABUG Examples To execut cod To execut cod To execut cod
9. 1 9 NSTALLATION AND SETUP The following sections describe allthe steps needed to prepare the board for operation Please read the following sections carefully before usimmg atis When you are preparing the board for the firsttime be sure to check that all jumpers are in the default locations The standard configuration does not require any modifications After the board is functional in its standard configuration you may use the Ethernet by followitkhe instructionsprovided in Appendix A d Dig Ms Unpacking Unpack the computer board from itsshippingbox Save the box for storingor reshipping Refer to the following listand verify that allthe items are present You should have received 1 M5307C3 Single Board Computer 1 4 For More Information On This Product Go to www freescale com Freescale Semiconductor I M5307C3 User s Manual this documentation One RS 232 communication cable Debug wiggler cable Programmers Reference Manual O OF C MN A selection of Third Party Developer Tools WARNING nc and Literature AVOID TOUCHING THE MOS DEVICES STATIC D SCHARGE CAN AND WILL DAMAGE THESE DEVICES Once you verifiedthat allthe items are present rem ove the board from its protective jacket Check thmard for any visibledamage Ensure that there are no broken damaged or missing parts If you have
10. CS TEN amp DOCS Ql D Q1 Q CS 00 Q EN CS 202 D y equations GUARRA H HEE HH HEE HH HE EH HH EH AA EE Ht AAA Bidirectional circuit equations NPE HE EH H HEE HH HEE HH HEE HH HE EH HH EE HH EE EH HE EE OT21 TAL DA DAOE OB21 IORL IOR OB21 IOWL IOW OB21 RST_L RST_H SBHEL 1 IRQ3 ETHER_IRQ DB_CS_L RST_H amp CS3_1 ABORTML ABORTIL ABORTML clk CLK8MHZ ABORTOL ABORTML ABORTOL clk CLK8MHZ RSTMH RSTIN_L 3 For More Information On This Product Go to www freescale com s 702 0 amp CS 00 0 01 0 EN CS Freescale Semiconductor Inc RST H RSTMH PORIN L BDM_RST_L IHIZ L RST_L HIZ L 1 DAOE 1CS3_L DA DAOE clk XCLKO A0 STZ1 amp SIZO AOIN A16 SBHE STARTISA amp SIZ1 SIZO amp AOI STARTISA amp SIZ1 SIZO AOI STARTISA amp SIZ1 amp SIZO AOIN CLK16MHZ CLK16MHZ CLK16MHZ clk XCLKO CLK8MHZ CLK8MHZ amp CLK16MHZ CLK8MHZ amp CLK16MHZ CLK8MHZ clk XCLKO CLK4MHZ CLK4MHZ CLK16MHZ CLK8MHZ CLKAMHZ clk XCLKO g DA CS3 L END16 amp ENDIT IIOCS16L RD amp CLK8MHZ SBHE CS3 L amp END8 ENDIT amp RD amp CLK8MHZ DLYDA am
11. MO amp Ml amp M2 amp M3 amp CA23 IMO amp M1 amp MO amp M1 M2 M3 amp MO amp M1 amp M2 amp M3 amp MO amp Ml amp M2 M3 amp MO amp Ml amp M2 amp M3 amp IMO amp M1 M2 amp M3 amp MO amp M2 amp M3 amp CA23 MO amp Ml amp M2 amp M3 amp CA24 IMO amp M1 amp M2 amp M3 amp CA24 amp M2 amp M3 amp CA24 IMO amp M IMO M1 amp MO amp M1 amp M2 amp M3 MO amp M1 amp M2 amp M3 IMO amp Ml amp M2 amp M3 MO amp MI M2 amp M3 amp amp amp amp M2 amp M3 amp CA25 CA25 CA26 CA26 CA27 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs MOTOROLA 18 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mfax is a trademark and Coldfire is a registered trademark of Motorola Inc ispEXPERT is a trademark of Lattice Semiconductor Intel is a registered trademark of Intel Corporation Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of t
12. Go to www freescale com Freescale Semiconductor Inc VERSION Display dBUG Version VERSION Usage VERSION The VERSION command display the version information for dBUG The dBUG version number and build date are both given The version number isseparated by a decimal for example v1 1 The first number indicates theversion of the CPU specificcode and the second number indicates the version of the board specific code The version date isthe day and time at which the entire dBUG monitor was compiled and built Examples To display the version of the dBUG monitor the command is version 2 4 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 5 TRAP 15 Functions An additional utility within the dBUG firmware is a function called the TRAP handler This function can be called by the user program to utilize various routines within the dBUG to perform a special task and to return control to the dBUG This section describes the TRAP 15 handler and how it is used There are four TRAP 15 functions These are OUT_CHAR IN_CHAR CHAR PRESENT and EXIT TO dBUG Zug dis OUT CHAR This function function code 0x0013 sends a character which is in lower 8 bits of D1 to terminal Assembly example assume dl contains the character move l 50013 d0 Selects the function TRAP 15 The character in dl is sen
13. zie Q Zzi z aja Z aja za Q BWE3 BWE 1 TOUT1 NC GNI GNI GNI Z Q kJ O DPB O ww Co Co FW ITN NH ho NH hd ile le pa O Table 14 The LA5 Connector pin assignment zZ ui zz s jp spe 68 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 69 For More Information On This Product Go to www freescale com 4 Freescale Semiconductor Inc The Debug Connector J1 The MCF5307 does have background Debug Port Real Time Trace Support and Real Time Debug Support Thaecessary signalsare availableat connector Jl Table 15 The J1 Connector pin assignment shows the pin assignment Table 15 The J1 Connector pin assignment GNAL NAME No Connect BKPT onnect B RST S Ground LK BDM I O N Connect 3 3 5V selectable NO ESO M 10 foso 16 META TEN Ground thur 70 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc APPENDIX A Configuring dBUG for Network Downloads The dBUG module has the abilityto perform downloads over an Ethernet network using the TrivialFileTransfer Protocol TFTP Prior to using this feature several parameters are required for n
14. 0x00012008 beq start 2 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 2 BC Compare Blocks of Memory BC Usage BC first second length The BC command compares two contiguous blocks of memory the first block starting at address first the second block starting at address second b of length length If the blocks are not identical then the addresses of the first mismatch are displayed The value for addresses first and second may be an absolute address specified as a hexadecimal value or a symbol name The value for length may be a symbol name or a number converted according to the user defined radix normally hexadecimal Examples To verify that the code in the first block of user FLASH space 128K is ident to the code in user SDRAM space the command is bc 20000 FFE20000 20000 2 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 3 BF Block of Memory Fill BF Usage BF width begin end data The BF command fills contiguous block of memory startingat address begin stopping at address end with the value data Width modifies the size of the data that is written The value for addresses begin and end may be an absolute addrespecifiedas a hexadecimal value or a symbol name The value for data may be a symbol name or a number converted according to
15. 4 L Tie MCF5307 Evaluation Board Bize Document Number Fev B MCF5307 ETHERNET 30 late Thursday April 01 1999 Bheet 5 of D o 31 gt RS2 u2 E TXD1 To DH TX x o RXD1 154 Doi Xt FS 8 9 A 0 31 gt RTS1 Tr Di2 TD o CTS1 a 002 RRB ame 12 3 TX3 9 2 D03 RX8 zs 3 C2 Ct 18 t 1 o 97 C2 cH Ao BCLKOHEADER 43 3 12 vcc vss H J33 SIZO SIZ1 C24 FS VDD GND 1 10 UF TANT TN 4 2 2a BR 10 UF TANT 1 i z PPO BD IRQ3 MC145407DW cis TOUT 3 a PP1 IRQ CS1 TINO PP2 CS2 CS3 10 UF TANT TOUTO T se PP3 CS6 CS7 sc Y 2 PP4 CF_RST TS SDA 13 14 PPS TXD1 TXD2 C16 Rt T 7 PPG AXD1 RXD2 ROS 31 7 PP7 RTSt RTS2 5 y CS0_HEADERQ 17 Sy A24 CTS CTS2 BWEO 22 2 A25 MTMODO HIZ 10 UF TANT BWE er
16. BD_CS 21 voe 1 025 CF_RSTI T 083 557 1 07 1 024 Fz 26 Hoe vos Pag 20 RT 27 109 11022 43 SIZO 28 1 010 1 021 41 Voltage Supervi ETH_IRQ3 5g O11 11020 Fay y dB ES ARGS 28 1 1 012 1019 Fas TA us ETH_RESET 11013 11018 MA16 GREEN LED 37 1014 1017 5 RESIN n x Hz gt 11015 11016 lt lt IOR vec gt SENSE 2i is 5 25 TDO IN1 vecoj p 793 a RESET 57 TDI IN o VCCI cT R7 357 ispEN NC RESET X 33 IMS NC 1 250 117 Toke 1 c18 REF BCLK_FPLA gt 57 YO GNDO H5 17 REsET YI GND1 atur GND GOEO i ane e 0 1 UF h ispLSI2032V 100LJ SMT socket d spo 43 3 so 45 MODE gt gt A SCLK gt C54 C14 C30 C113 C19 0 1 UF 0 1 UF 0 1 UF 0 1 UF 0 1 UF 43 3 4 R6 4 7K 45 R5 47K w R4 47K e e R3 47K i 4 Se R11 4 7K ex e 6 ela e 8 c2 itle 0 01 UF MCF5307 Evaluation Board Bize Document Number Rev B MCF5307 PLD 30 late Thursday April 01 1999 Bheet 7 of Ethernet 10 Base T u12 R18 sDo MSD7 HEX 47K SD1 MSD6 SLOT go SD2 MSD5 BNCSW SD3 MSb4 EX U13 Ethernet E2 SD
17. Disassemble DI 2 21 2 4 9 DL Download Serial DL 2 22 24 4 T0 DN Download Network DN 2 23 2 AM ll Go Execute GO 2 25 i For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 12 GT Execute Till a Temporary Breakpoint GT 2 26 2 4 13 HELP Help HE 2 27 2 4 14 IRD Internal Registers Display IRD 2 28 2 4 15 IRM Internal Registers MODIFY IRM 2 29 2 4 16 MD Memory Display MD 2 30 2 4 17 MM Memory Modify MM 2 31 2 4 18 RD Register Display RD 2 32 2 4 19 RM Register Modify RM 2 33 2 4 20 RESET Reset the board and dBUG RESET 2 34 2 4 21 SET Set Configuration SET 2 35 2 4 22 SHOW Show Configuration SHOW 2 37 2 4 23 STEP Step Over ST 2 38 2 4 24 SYMBOL Symbol Name Management SYMBOL 2 39 2 4 25 TRACE Trace Into TR 2 40 2 4 26 UPDBUG Update the dBUG Image UPDBUG 2 41 Die ASK ss UPUSER Update User Code In Flash UPUSER 2 42 225 TRAP 15 Functions 2 44 Des a OUT CHAR 2 44 23 5 52 IN CHAR 2 45 2 50 2 CHAR PRESENT 2 45 229 TA EXIT_TO_dBUG 2 46 CHAPTER 3 48 Jod THE PROCESSOR AND SUPPORT LOGIC 48 N he Processor 48 The Reset Logic 49 The HIZ Signal 49 The Clock Circuitry 49 atchdog Timer 49 nternal SRAM 51 he MCF5307 Registers and Memory Map 51 W Interrupt Sources 50 I T Reset Vector Mapping 53 Qs TA Generation 53 Ta Wait State Generator 54 WWW CO WWW C
18. Operating system from the network Validvalues are on and off This option is not implemented on the current of dBUG nicbase this is base address the network interface Thiscommand isused to informthe dBUG of the address of the network interface The default value shows 0x0000 However this parameter is hard coded to 0x300 DO NOT CHANGE THIS OPTION macaddr This is the ethernet MAC address of the board For network communications the MAC address isrequired to be set to a unique value Any address that is not already in use is suitable Examples To see all the available options and supported choices the command is set To set the baud rate of the board to be 19200 the command is set baud 19200 Now press the RESET button RED or RESET command forthe new baud to take effect This baud will be programmed Hrash ROM and willbe used during the power up 2 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 22 SHOW Show Configuration SHOW Usage SHOW option SHOW The SHOW command displays the settings of the user configurable options within dBUG Mostoptions configurableviathe SET command can be displayed with the SHOW command Ifthe SHOW command isissued without any option it will show all options Examples To display all the current options the command is show To display the current baud rate of the board the comm
19. 252 1 TIR Nl PANASONIC IDEM GREEN LE D4 1N5404CT P521TR NI PANASONIC D6 1 D SMT RED RED LED DH DSMI RED LED P521TR ND PANASONIC JL dg 2 SUE EN 1x3 100 mil Jumper JUMPER3 i JEI header 6mm high 14 JPI15 yes IP17 Pi P21 DA LED SMT GRN IDEM IRO7 Lx eade 1x2 1 eade E Sco eade 1552 eade LG 1x2 1 il jum RSEN header 6mm high ME HJ2X 9 1 TRIER TEE w plastic 2x13 100 mil header 6mm high Sus ixe 100 mil 6m high 100 igh 100 Lib 100 igh JUMP1X8 HOAX ESOS HOAX Mictor_Connec EOC AME 2 For More Information On This Product Go to www freescale com LAL LAZ LAS LA4 LAS Freescale Semiconductor Inc 767054 1 FERRITE BEAD AMM PE SOE NEWARK 46F89 Red Momentary a Sw 3L iE cla NEWARK 93F77 Black Momentary 15 Swab ic cla DISS INSZS 2 OIL THRU HOLE DB9 PIS RJ45 Thur Hole Rel TOR 0905 body styl Re RoR Ro Pio alee en 2 I 14 RIS RI7 RIS IRIS I2 0r 1 2 5 RAG R27 7 ASL REZ IS y R34 R42 R43 R44 R45 R46 RAT y RAS y RAS R50 RSI ROPT 15 3 ROAT RSS R56 R T ROLI ROD ROO R71 RIS RTS In p RO RAI RO REQ RG 3 PN ROA IRGSD ROG ING ROS ROS y 7 0 p 1872 RIS RLO 49 1 6 R24 R28 AZO RSO RIGS y de IRS 9 RS
20. ASSEMBLY PP X Be ia avi OA 4A2 4Y2 Ppa 27 22 4A3 4Y3 PP7 26 23 MAr Qe Rez Res Re4 Res Ree Rez Res 7 ld R61 93 18 veo 108 Fag 2709 270 2709 2709 2709 2709 270 a1 Voc 20E 25 270 42 ar L24 NGG 408 Zo 8 8 a a a Motorola ColdFire 28 4 8 os e Fo Fe Fo de pa Ve ga GND GND Tig ha ie E E eae B ae Sot GND GND H Y sw a WZ We E Te GND GND x 2 o xo xo xo E Na YE MCF5307 Evaluation Board u mu m y m Y zi y MO7ALCX16244DT 4 4 Bize Document Number Rev B MCF5307 BUFFERS 30 CF_RSTI gt Baie Thursday Anni 1999 EL FB D 16 31 D 0 31 gt MA 0 19 gt R54 SRAM 4 7K U19 30 CS0_EN X SAO QD35 39 X lt SA1 QD34 28 SA2 QD33 25 CS0 HEADER Bat Oost 24 CS0 SA4 QD31 A 433 43 3 433 433 res apse 22 JP SA6 apes Hie 5 SA7 apes Hg 080 gt SAB QD27 i SA9 da SA10 QC26 x RAZ Qoid SA11 aces H 47K 4 7K 47K 4 7K SA12 QC24 oEY SA13 ces FS SA14 Qc22 6 iw SA15 QC21 3 D 10 SA16 QC20 5 D25 AOS RESET acts FF Ded ADSP QC18 ADV s AM29LV004T 100EC ADSC 0817 59 X 8 FLAS OW QB16 FLASH LOWER 78 wr u21 BCLK_SRAM gt K QB15 75 Dee 13 km QB14 74 D20 Fe A18 D7 Sw
21. Freescale Semiconductor Inc Pid T DATA Data Conversion DATA Usage DATA data The DATA command displays data in both decimal and hexadecimal notation The value for data may be a symbol nameor an absolute value Ifan absolute value passed into the DATA command is prefixed by Ox then data is interpreted as a hexadecimal value Otherwise data is interpreted as a decimal value All values are treated as 32 bit quantities Examples To display the decimal equivalent of 0x1234 the command is data 0x1234 To display the hexadecimal equivalent of 1234 the command is data 1234 2 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ee nem oar DI Disassemble DI Usage DI lt addr gt The DI command disassembles target code pointed to by addr The value for addr may be an absolute address specified as a hexadecimal value osymbol name Wherever possible the disassembler willuse information from the symbol tableto produce a more meaningful disassembly Thisisespeciallyuseful for branch target addresses and subroutine calls The DI command attempts to track the address of the last disassembled opcode Ifno address isprovided to the DI command then the DI command uses the address of the last opcode that was disassembled Examples To disassemble code that starts at 0x00040000 the
22. On This Product Go to www freescale com Freescale Semiconductor Inc Once the network parameters have been obtained the Rom Monitor must be configured The following commands are used to configure the network parameters set client lt client IP gt set server lt server IP gt set gateway lt gateway IP gt set netmask lt netmask gt set Macaddr lt macaddr gt For example the TFTP server is named santafe and has IP address 123 45 67 1 The board is assigned the IP address of 123 45 68 15 The gateway IP address is123 45 68 250 and the netmask 1s 255 255 255 0 The commands to dBUG are set client 123 45 68 15 set server 123 45 67 1 set gateway 123 45 68 250 set netmask 255 255 255 0 set Macaddr 00 00 00 00 00 00 The laststep isto inform dBUG of the name and type of the fileto download Prior to giving the name of the file keep in mind the following Most if not all TFTP servers willonly permit access to filesstartingat a particular sub directory Tha a security feature which prevents reading of arbitraryfilesby unknown persons For example SunOS uses the directory tftp_boot as the default TFTP directory When specifyinga filename to a SunOS TFTP server allfilenames are relativeto tftp_boot As a result you normally willbe required to copy the fileto download intothe directory used by the TFTP server A default filename for network download
23. PC100 memory per Intel PC SDRAM specification Thus the MCF5307 to SDRAM Setup Time can be found by the calculation below 22nS Bus Frequency 11nS BCLKO to Valid Output time 3nS PCDRAM setup time 8nS timing margin 5nS MUX PLD max propagation delay 3nS worst case timing margin This indicates that even at the worst case there is enough margin for the MCF5307 signals to reach a PC66 SDRAM while using the helper MUX 1 4 1 Write Bus Cycle A write bus cycle was also evaluated as valid since the published hold time to BCLKO for the MCF5307 is 2 0 nS Parameter B11 and the input hold time for a PC66 memory is 1 5 nS leaving 0 5 nS as timing margin 1 4 2 Read Bus Cycle Read cycles also meet timing margins for setup and hold times to the MCF5307 For SDRAM to MCF5307 setup time the following calculation was used 22 nS BCLKO period 10 nS Clock to valid data for PC66 memory This is 7 nS for PC100 memory 5 5 nS Valid input to BCLKO falling setup time parameter B1 6 5nS timing margin This corresponds to the parameter value found in the Electrical Specification Section of the MCF5307 User s Manual MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 9 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc For SDRAM to MCF5307 hold time the following calculation was used 3 nS Output hold time for PC66 and PC100 memory 2
24. System Starter Kit ISP Synario 5 01 Device Utilization Chart SDRAM Mux Controller for the MCF5307EVM Input files ABEL PLA file Device library Output files Report file Programmer load file mux tt3 P22V10C dev SDRAM Mux Controller for P22V10C Programmed Logic 16 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 16 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SA8 CA18 amp MO amp M1 MO amp M1 IMO amp M1 ae dE do db Se IM1 amp M2 SA9 z o Rr x B MO amp M1 IMO amp Ml MO amp M1 IMO amp Ml MO amp M1 Se 3 Se ode dk se SA10 MO amp M1 amp MO M1 MO amp M1 MO amp M1 IMO amp M1 IMO amp Ml aE Ho db o dB Sk db Se IMO amp Ml SA11 x MO amp M1 amp MO amp M1 MO amp M1 IMO amp M1 SE dE db o db oc IMO amp M1 MOTOROLA amp amp amp amp amp amp amp amp CA18 amp MO amp IMO M1 amp IMO amp M1 amp 1M2 IMO amp M2 amp M3 M3 M3 M2 amp M2 amp M3 amp CA20 IMO amp M1 amp M2 M2 M2 M2 M3 M2 amp M3 M1 amp amp amp amp amp amp amp amp amp amp M2 amp CA19 CA19 CA19 CALS j amp M3 amp CA19 M3 amp CA19 M3 amp CA20 M3 a
25. Terminal or similar packages Then connect as described in 1 9 6 Connecting the Terminal 1 t For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Once the connection to the PC ismade you are ready to power up the PC and run the terminal emulation software When you are inthe terminal mode you need to selectthe terminal emulation so press the p key whil character format baud rate and the character format forthe channel Most ftware packages provide a command known as Alt p le pressing the Alt key to choose the baud rate and Make sure you select 8 bits no parity one stop bit see section The Terminal Character Format Then select the baud rate as 19200 Now you are ready to apply power to the board Figure 2 Pin Receive NO i WN FP 7 Request to Send 8 Clear to send 9 Not connected Data Carrier Transmit Data input output eC che de O gO CJ O OE assignment for P4 Terminal connector Detect Output shorted to pins 4 and 6 Data Output from board receive refers to terminal side Input to board transmit refers to terminal side Data Terminal Ready input shorted to pin 1 and 6 Signal Ground Data Set Ready Output shorted to pins 1 and 4 lt For More Information On This Product Go to www freescale com 1P10 1
26. The ROM monitor sets the default SDRAM access provided to 4 2 2 2 burst The ROM monitor also uses 54 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc the Serial Presence DetectSPD functionalityf the SDRAM to determine what SDRAM is populated in the evaluation board and configures the system appropriately Please refer to the SDRAM Application Note in Appendix E for address muxing 3 3 FLASH ROM There aretwo 512Kbyte Flash ROM on the M5307C3 U20 high even byte and U21 low odd byte The board is shipped with two 29LV004 512K byte FLASH ROM for a totallMf bytes The first128K of the Flash contains ROM Monitor firmware The last 896K is available to the user The chip select signal generatee MGF5307 CS0 enables both chips The MCF5307 chip select logic can be programmed to generate theTA for CS0 signal after a certain number of wait states The dBUG programs this parameter to three wait states 3 3 1JP1 Jumper and User s Program This jumper allows users to test code from the boot without having to overwrite the ROM Monitor When the jumper isset between pinsl and 2 the behavior isnormal When the jumper isset between pins2 and 3 the board boots from the second half of Flash 0x80000 Procedure 1 Compile and linkas though the code was to be place at the base of the flash but setup so that itwilldownload to the SDRAM startingat a
27. This Product Go to www freescale com Freescale Semiconductor Inc Because different density SDRAM devices have different asymmetries a single direct connection scheme is not possible An easy connection scheme for each specific module type can be derived by referring to Table 1 and the MCF5307 address multiplexing scheme in the asynchronous operation section of the MCF5307 User s Manual Since there is some commonality with respect to the connection scheme of each module type an in between helper MUX can be conceived that interfaces between the MCF5307 and SDRAM DIMM Table 2 and Table 3 depict the MCF5307 SDRAM controller to SDRAM connections necessary for different SDRAMs Table 2 lists the address line connections for various SDRAMs while Table 3 lists the required bank select interface Table 2 SDRAM Address Line Connections CF Address Condition SDRAM Address Column Address Row Address A15 Always AO A2 A15 A14 Always A1 A3 A14 A13 Always A2 A4 A13 A12 Always A3 A5 A12 A11 Always A4 A6 A11 A10 Always A5 A7 A10 A9 Always A6 A8 A9 A17 Always AT A16 A17 A18 8 columns A8 N A A18 A19 9 10 or 11 columns A18 A19 A19 8 columns A9 N A A19 A20 9 columns N A A20 A21 10 or 11 columns A20 A21 A20 8 columns A10 N A A20 A21 9 columns N A A21 A22 10 columns N A A22 A23 11 columns A22 A23 A21 8 columns A11 N A A21 A22 9 columns N A A22 A23 10 col
28. certain the client IP address is unique for the board Check for proper insertion or connection of the network cable IS statustLE indicating that network traffic is present Check for proper configurationand operation of the TFTP server Most Unix workstations can execute a command named tftp which can be used to connect to the TFTP server as well Is the default TFTP root directorypresent and readable f ICMP DESTINATION UNREACHABLE or similarICMP message appears then a Serious error has occurredReset the board and wait one minute for the TFTP server to time out and terminate any open connections Verify that the IP addresses for the server and gateway are correct 3 For More Information On This Product Go to www freescale com APPENDIX module isa2 title isa Oct 12 isa2 device 98 version H ColdFire to Freescale Semiconductor Inc ISA Abel IRO7 and Reset Logic code controller v3 of the 5307 ispLSI 0 KC CK C CK C CK CC CK CC CC CC CK CC CC CK CCS C CK Ck KC C CK SK CK SK S A S KU KU A KM This abel file contains the code for a NE200 for the 5307 ColdFire processor as well as reset and It was targeted to Lattice ispLSI LV 2032 PLD CS B25D e ko C CK C CK CK CC CK CC C CK CC CK CK CC CC CK Ck CK CK S CK S A KK KK KK M kA CK C CK CK CC CK C000 CC CK CC CC CK SCC C CK CC C CK CK
29. chip select logic also allows programmable number of wait statesatdow the use of slower memory referto MCF5307 User sManual by Motorola for detailed information about thS8IM The M5307C3 only uses three of the chip selects toaccess the Flash ROM s CS0 SRAM CS2 which isnot populated on board may be added by the user and the Ethernet CS3 The DRAM controller is used to control one DIMM module up twWl2M of SDRAM both RAS linesand all four CAS lines are used otAer functions of the SIM are availableto the user A block diagram of the board is shown in Figure 1 1 2 For More Information On This Product Go to www freescale com RAS gt AMAA MA Tm NrRa RS232 M CF5307 gt XCEIVERS JA J7 Flach 1M bit U20U 21 TO PORTS ADDRBUS CONTROLBUS DATA BUS M ictorand E xpansion Connectors Figure 1 Block Diagram of the board Freescale Semiconductor Inc 1 3 SYSTEM MEMORY There are two on board Flash ROM s U20 U21 U2hkhe most significantbyte and the U21 is the least significantbyte The M5307C3 comes with two 29LV004 Flash ROM s programmed with a debugger monitor firmware Both AM29LV004DT Flash are 4Mbits each giving a total of l1Mbyte of Flash memory There is one 168 pin DIMM socket for SDRAM System ships with M8 Bank x 16 Bits SDRAM totaling 16M ofvolatilememory Various SDRAM
30. clears the entisymbol table the loption liststhe contents of the symbol table and the s option displaysusage information for the symbol table Symbol names contained inthe symbol table are truncated to 31 characters Any symbol table lookups either by the SYMBOL command or by the disassembler willonly use the first31 characters Symbol names are Case sensitive Examples To define the symbol main to have the value 0x00040000 the command is symbol a main 40000 To remove the symbol junk from the table the command is symbol r junk To see how full the symbol table is the command is symbol 8 To display the symbol table the command is symbol I 2 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 25 TRACE Trace Into TR Usage TRACE num Ihe TRACE command allows singleinstructionexecution If num is provided then num instructions ar xecuted before control is handed back to dBUGe value for num is a decimal number The TRACE command sets bits in the processors supervisuwsgistersto achieve single instruction execution ake target code executed Control returns to dBUG after a single instruction execution of the target code Examples To trace one instruction at the program counter the command is EE To trace 20 instructions from the program counter the command is ter 20 2 41 Fo
31. clookCLKIN pin of the processor In addition to U22 there also exista 20MHz oscillator U6 which feeds into the Ethernet chigLhe bus clock out of the MCF5307 drivesa clock buffer chip U18 which is fed intoth dge select pin of the MCF5307 the ispLSI2032 for Ethernet timing 1 4 bus clock SRAM U19 and SDRAM U23 33d 3 Bs Watchdog Timer 49 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The duration of the Watchdog isselectedby BMTO 1 bitsin System Protection Register The dBUG initializetshis registerwith the value 00 which provides for 1024 system clock time out but dBUG does not enable it Jc 6 Interrupt Sources The ColdFire family of processors can receive interruptsfor seven levelsof interrupt priorities When the processor receives an intemtfupth has higher priority than the current interrmeisk instatus register itwillperform an interruptacknowledge cycle at the end of the current instructioncycle This interruptacknowledge cycle indicatesto the source of the interruptthat the request is being acknowledged and the device should provide the proper vector number to indicatewhere the service routine for thisinterruptlevelis located If the source of interruptisnot capable of providing a vector its interrupt should be set ugs autovector interruptwhich directsthe processor to a predefined entry into the exception t
32. configurations are supported The MCF5307 has 4K bytes organized as 1024x32 bits of internal SRAM The internal cache of the MCF5307 isa non blocking 8kbyte 4 way set associative unified instructiorand data cache with a 16 byte linesize Th ROM Monitor currentlydoes not utilizethe cache but programs downloaded with the ROM Monitor can use the cache The M5307C3 evaluation board has a foot print for 512 K SRAM but is unpopulated 1 4 SERIAL COMMUNICATION CHANNELS The MCF5307 has 2 built inmMART s UARTO and UART1 with independent baud rate generators The signals of channel one are passed through external Driver Receiversto make the channel compatible with RS 232 UARTO isused by the debugger for the user to access with a terminal In addition the signals of both channels are availabletoe mictor connectors LAI and LA3 to be viewed by a logicanalyzer UARTO channel isthe TERMINAL channel used by the debugger for communication with external terminal PCThe TERMINAL baud rate is set at 19200 1 5 PARALLEL 1 0 PORTS MCF5307 offersone 16 bit general purpose parallell O port Each pin can be individuallyprogrammed as input or output The parallelport bitsPP 7 0 is multiplexed with TT 1 0 TM 2 0 DREQ 1 0 and XTIP The second set of parallelport bitsPP 15 8 ismultiplexed with address bus bitsA 31 24 Both bytes of the parallelport are controlledby
33. not received allthe items listed above othey are damaged please contact Cadre immediately in order to correct the problem 1 2 25 Preparing the Board for Use The board as shipped is ready to be connected toa terminal and the power supply without any need for modification Howevefollow the steps below to insure proper operation from the firsttime you apply the power Figure 3 Jumper Table and Locations shows the placement of the jumpers and the connectors which you need torefer to inthe following sections The steps to be taken ar a Connecting the power supply b Connecting the terminal 295535 Providing Power to the Board The board acceptstwo means of power supply connections Connector P2 isa 2 1mm power jack and Pl lever actuated connector Theoard accepts 6 5V to 9V DC regulated or unregulated at 1 5 Amp via either one of the connector Contact NO Voltage 1 6 5 9V 2 Ground 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 9 4 Selecting Terminal Baud Rate The serialchannel of MCF5307 which isused for serialcommunication has a builtin timer used by the ROM MONITOR to generate the baud rate used to communicate with a terminal It can be programmed to a number of baud rates After the power up or a manual RESET the ROM Monitor firmware configures the channel for 19200 baud A
34. seamlessly interface to standard SDRAM components and DIMMs Although the number of row column and bank select lines can vary from module to module the multiplexing scheme in the MCF5307 is designed to support a large variety of SDRAM configurations To extend this MCF5307 feature further a PLD can be designed to interface to the MCF5307 SDRAM controller that allows the connection of a wide variety of SDRAM DIMMs having different row and column configurations Thus rather than hardwiring one specific SDRAM DIMM to a MCF5307 board design SDRAM DIMMs with varying row and column combinations can be swapped without re design This document details a method of connecting the MCF5307 to single sided DIMMs with 8 9 10 or 11 column address lines 11 12 or 13 row address lines and up to 2 bank address lines using a PLD design This design can support up to 512 MBytes of memory which is compatible with the MCF5307 s addressing capability 1 1 1 Definitions Before the PLD design is presented it is helpful to review some of the terminology that will be used in this document e MCF5307 Memory Bank This refers to any group of memories that are selected by one of the MCF5307 RAS 1 0 signals Thus the MCF5307 can support two SDRAM banks Note that the RAS 1 0 signals interface to the chip select signals CS on SDRAMs SDRAM Bank This term is often used by SDRAM manufacturers to distinguish between the internal partitions or banks in a
35. section 3 3 The Ethernet Bus interfacemaps allthe I O space of the Ethernet bus to the MCF5307 memory at address FE600000 Refer to section 3 6 52 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Tabl 4 Th M5307C3 memory map SIGNAL and DEVICE 00 DRAM space for dBUG ROM Monitor 00 use Internal SRAM 4K bytes System Integration Module SIM registers CS3 1M Ethernet Bus area External SRAM 512K bytes unpopulated SFFE00000 SFFEFFFFF CSO 1M bytes of Flash ROM 1 Not installed Level 2 cache footprint accepts Motorola s MCM69F737T chip and any other SRAM with the same electrical specifications and package All the unused area of the memory map is available to the user Su v9 Reset Vector Mapping After reset the processor attempts to get the initias tack pointer and initial program counter values from locations 000000 000007 the firsteight bytes of memory space This requires the board to have a nonvolatilememory device inthisrange with proper information However insome systems itis preferred to have RAM startingat address 00000000 In MCF5307 the CSO responds to any accesses after reset untilthe CSMRO iswritten Since CS0 the global chip select isconnected to Flash ROM s the Flash ROMs appear to be at address 00000000 which provides the initias tack poin
36. t 26 1 10E vec He 33 14 vec 557 20E vec FS it vcc 20E 2DIR VCC 377 vec vec 4 28 GND GND lo jano cno fj Ze GND eND Hs 1t GND GND He 39 GND GND d GND GND 24 GND GND S GND GND MG74LCX16245DT bs B_0 16 31 pue i mE MC74LCX16244DT Uig Bi Buffers i 7181 iat Hie aa DIA 0 1a aa E DIA u10 Dis 6 43 BD19 R71 Ais 2 18 MAIG pon S 184 1A4 PE EDA s2 dU AT 4 1D0 100H MAT D21 9 185 1S 40 B D21 A18 5101 A101 a4 MA18 D22 a1 188 145 38 B D22 Lcx ar A19 8102 19h MA19 3 D15 R72 D23 12 pg 1A8 HZ I 1 124 500 200 IRa7 D24 15 281 241 H8 B D24 34201 200 4 Bee 167 282 2n2 Ts B De 1RQ7 Wr 202 202155 ES 17 283 2A3 35 X 2D3 203 x IRQ7 270 2B4 2A4 285 PAS tourtant O 1 20 D 0 31 gt 2B6 2A6 1 19 10E vcc 2B7 2A7 w 20E D31 23 588 2a 26 B_D31 is RW 1 iji vec H 33 ae 48 1DIR 18 A BD CS Se 10 vec har 25 20E vec H2 MC74LCX244DW 2DIR VCC Hono an HS TOUT o E L433 15 OND GND 38 TOUTI Reo Q R70 A 3 21 GND GND 45 C45 PETIT PTT 270 270 P X B MC74LCX16245DT INITIAL RESET CONFIGURATIO Jg SUMI a all Do ae als C29 cas 027 C28 C46 C60 C42 C26 C44 46 3 D1 E a 01UF O1UF O1UF O1UF O1UF 01UF 01UF 0tUF 0 1UF 041 UF 44 122 1215 D se wo 1 49 143 TY3 g D3 xS wu 217 1A4 1v4 5 pz 4 ie iE B 4 4 4 4 4 38 2A2 2Y2 11 De M LIN 2Y3 32 D7 7 ppo 36 2M 2 4 18 PP1 35 341 avia pez 33342 Sarig PP 32 943 307 ASSET ppa 30 2M 3Y4 y DURING
37. the TIMER module 2 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 16 MD Memory Display Usage MD lt width gt lt begin gt lt end gt The MD command displaysa contiguous block of memory startingat address begin and stopping at address end The value for addresses begin and end may be an absolute address specifiedas a hexadecimal value or a symbol name Width modifies the size of the data that is displayed Memory display starts at the address begin If no beginning address is provided the MD command uses the lastaddress that was displayed If no ending address is provided then MD will display memory to an address that is 128 beyond the starting address This command firstalignsthe startingaddress for the data access size and then increments the address accordingly during the operation Thus for the duration of the operation this command performs properly aligned memory accesses Examples To display memory at address 0x00400000 the command is md 400000 To display memory inthe data section definedby the symbols data start and data end the command is md data start To display a range of bytes from 0x00040000 to 0x00050000 the command is md b 40000 50000 To displaya range of 32 bit values startingat 0x00040000 and ending at 0x00050000 the command is ma l 40000 50000 This command may be repe
38. the board ina way which best suits an application Options availableare up to 512M SDRAM 512K SRAM Timer I O Ethernet and 1M of Flash In addition all of the signals are easily accessible to any logical analyzer with mictor probes to assistin debugging Most of the processor s signalsare also availablevia berg connectors J3 J4 and J5 for expansion purposes 1 2 GENERAL HARDWARE DESCRIPTION The M5307C3 board provides the RAM Flash ROM on board NE2000 compatible Ethernet interface 10M bit sec RS232 and allthe built inl O functions of the MCF5307 for learningand evaluating the attributesof the MCF5307 The MCF5307 isa member of the ColdFire family of processors It isa 32 bit processor with 32 bitsof addressing and 32 linesof data The processor has eight 32 bit data registers eight 32 bit address registers a 32 bit program counter and a 16 bit status register le For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The MCF5307 has a System IntegrationModule referred to as the SIM The module incorporatesmany of the functions needed for system design These include programmable chip select logic System Protection logic General purpose I O and Interruptontrollerlogic The chip selectlogiccan select up to eight memory banks and peripheralsin addition to two banks of DRAM s The
39. the command is mm 10000 22 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 18 RD Register Display RD Usage RD lt reg gt The RD command displays the register set of the target If no argument for reg is provided then all registers are displayed Otherwise the value for i is displayed Examples To display all the registers and their values the command is rd To display only the program counter the command is rd pc 22 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 19 RM Register Modify RM Usage RM reg data The RM command modifies the contents of theregisterreg to data The value for reg isthe name of the register and the value for data may be a symbol name or it is converted according to the user defined radix normally hexadecimal dBUG preserves the registersby storinga copy of the registerset ina buffer The RM command updates the copy of the registerin the buffer The actual value will not be written to the register until target code is executed Examples To change register DO to contain the value 0x1234 the command is rm DO 1234 22 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 220 20 RESET Reset the board and dBUG RESET Usage RESET The RESET command
40. the originaldate of purchase This warranty extends to the originalcustomer only and is in lieu of all other warrants including implied warranties of merchantability and fitness Inno event willthe sellerbe liablefor any incidentalor consequential damages During the warranty period Matrix Design will replace at no charge components that ferolW ided the product is returned properlypacked and shipped prepaid to Matrix Design at address below Dated proof of purchase such as a copy of the invoice must be enclosed with the shipment We will return the shipment prepaid via UPS Thiswarranty does not apply if inthe opinion of Matrix Design the product has been damaged by accident misuse neglect misapplication or as a result of service or modification other than specified in the manual by others Please send the board and cables with a complete descriptionof the problem to Matrix Design amp Manufacturing Inc 2914 Montopolis Drive 290 Austin TX 78741 Phone 512 385 9210 Fax 512 385 9224 http www cadreiii com Motorola is a registered trademark of Motorola Inc i For More Information On This Product Go to www freescale com IBM PC and 2 All other registered trade IBM AT ar Freescale Semiconductor Inc registered trademark of IBM Corp C Bus is a proprietary Philips interface bus trademark names mentioned in this manual a
41. 0 SA10 CA21 SA11 CA22 SA12 CA23 BA0 CA24 BA1 CA25 when select 9 then SA8 CA19 SA9 CA21 SA10 CA22 SA11 CA23 SA12 CA24 BA0 CA25 BA1 CA26 when select h0A then SA8 CA19 SA9 CA21 SA10 CA23 SA11 CA24 SA12 CA25 BA0 CA26 BA1 CA27 WK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KAN Test Vector Section M ck Ck KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK ck ck ck cock ck ck ck ck ck kk kk kk kt test vectors MO M1 M2 M3 Test Vector M3 M2 Ml MO CA18 CA19 CA20 CA21 CA22 CA23 CA24 CA25 CA26 CA27 gt SA8 SA9 SA10 SA11 SA12 BAO BA1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 2 X X X X X X X 0 0 0 1 1 0 1 0 1 0 1 0 1 0 gt X X X X X X X MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 15 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 0 0 1 0 1 O XM Er CX Co 0 0 1 1 1 0 1 0 9 1 Ud 0 1 1 0 1 1 0 1 04 1 15 1 1 1 0 0 0 1 1 0 0 1 1 end X X X X X X X X X X X X X X X X X X X X X gt X X X X X X X 5 X X X X X X X 2 X X X X X X X X X X X X X X OE Do XX E gt DN e o wc G wx X X X X X X X 1 7 PAL Equations The following code represents the PAL equations generated by compiling the PAL ABEL HDL files using Lattice Semiconductor s freeware package ispEXPERT M
42. 1 1 0 1 0 1 0 1 0 1 0 X X X X X X X 0 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X D 0y 3 0 1 0 1 0 1 0 1 0 gt X X X X X X X 0 1 0 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X l j OL 001 3 r0 Ly Oy Ly Oy 1 07 1 0 gt 1X X X X X X X Oy 7 0 0 1 0 1 0 1 0 1 0 gt X X X X X X X Odd PI O A A AA DORA Test Vector Section WAKKKKKKKKKKKKKKKKK KKK KK KKK KKK KK KKK KKK AAA AAA AAA AM 4 For More Information On This Product Go to www freescale com CA25 CA26 CA2 Freescale Semiconductor Inc 1 0 1 0 1 0 gt X X X X X X X 1 0 1 0 1 0 gt X X X X X X X 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc APPENDIX FSDRAM MUX WHITE PAPER AN1802 D Motorola Order Number Application Note Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs William R Benner Jr 68K ColdFire Applications Team Pangolin Laser Systems Motorola Inc William_Benner msn com imaging oakhill sps mot com A special note of appreciation goes to William Benner Jr of Pangolin Laser Systems the primary author of this application note Mr Benner is gracious enough to allow Motorola to share his experience and knowledge with other customers This application note shows how to interchange various standard synchro
43. 10 5 nS timing margin For the SDRAM to MCF5307 hold time 3 nS Output hold time for PC66 and PC100 memory 2 nS Input hold time for MCF5307 parameter B4 1 nS advance from clock 0 nS timing margin Taking into account the 1 nS clock advance with 2 nS required for the MCF5307 the 3 nS hold time of the SDRAM leaves 0 nS timing margin Hold times are probably less critical because trace impedances and capacitances on the board will tend to extend these hold times In conclusion using a zero delay buffer in the negative one nanosecond model works with PC100 memory assuming that the MCF5307 from the 0H55J mask set is used 1 6 ABEL Code The following is the ABEL code file for the helper MUX for interfacing between a MCF5307 and standard 168 pin unbuffered SDRAM module SDRAMmux title SDRAM Mux Controller for the MCF5307EVM 5307mux device ispLSI22LV10 HILL This abel file contains the code to mux the address lines allowing the MCF5307 to support all 168 pin 1 Bank x 64 bit PC compliant DIMMS It was targeted to Lattice ispLSI 22LV10 PAL P All logic with this PAL is com P CS XXX OR RI K AE IRI III IIA II II IIA A RR IIA II A IC II IIA A M ORI ICR ICICI I ICRI IO ICR ICR ICI IO IR k kK kkk IO ICAI AO kN Declaration Section MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 11 AST For More Information On This Product Go to www freescale com
44. 4 MSD3 ec X 2 z R17 SD5 MSD2 EECK 88 21 sk NC x SD6 MSD1 EEDO 64 4D 6 4 7K SD7 MSDO_EED1 DO ORG x SD8 SD9 SD10 EECS H j vec H gt 5 SD11 BPCS EX cs MA 0 19 gt SD12 5 T SD13 56 GND Te SD14 PAT HS ds SD15 eae 58 AT93C46 10SC 2 7 not populated during assembly 714 sao X SAO PA4 pee Ti2 SA1 PAS F61 2S 13 SA2 PA2 67 Tia SAS PAI eS SA4 PAO SAS SAG SA7 nos Fe amp ETH IRQ3 SAB IRQ4 57 45 SA9 IRQS Hg SA10 IRQS 54 SA11 IRQ10 Fog R12 IRQ11 SA14 IRQ12 HE 47K SA15 IRQ15 Ethernet Ose SA16 ue SA17 SA18 1016 99 1016 tine vec 4 45 SA19 5 45 45 locurpy 25 amp IOCHRDY 8 1 BALE XH BALE z CLK GND i Gad ECLK DH svscik x HE i io ds ER OSC 20 MHZ R14 RIS HOR 7 or x2 Ax Bie V 4 7k ow 51 ow BNCEN X 4 7K 22 i 23 SMEMA Te ES 1 35 TX 40 PS ETH_RESET 25 RST RX Lag u7 l RX 24 AEN CD 2 iD TPTX 1 r 89 CD xX 2 15 MEMW AGND1 net Ex 2 2 30 1 MEMR TPTX E 34 no TPTX H4 s4 OO e AVDD1 TPTX 48 a 3 ut AVDD2 ae RXL TPRX AVDD3 TPRX FERRITE_BEAD 7 10 4 d Ten 68 AGND2 NC2 X x C65 C64 Y 8 9 AGND1 RXI TPRX 10 UF TANT 0 01 UF AGND2 LiLED 5S x amp FO AGND3 Rer NC voci Hz 5 FD22 101G i ATK E i VCC2 72 GND1 V6C3 Rig Rio GND2 49 9 49 9 E GNDS 100 Ca ca x10 GND4 GNDO UE eur DM9008F O n ES RJ45 Thur Hole 0 01 UF T T D3 R21 M 5 C63 C47 C31 C34 C33 GREEN LED 270 0 1 UF 0 1 UF 0 1 UF 0 1 UF 0 1 UF
45. 7 POWER 30 late Thursday April 01 1999 Bheet 8 of 8 10 Freescale Semiconductor Inc APPENDIX D SDRAM MUX PAL EQUATION module SDRAMmux t MAR 16 99 First revision of the code based on Bill Benners application no itle SDRAM Mux Controller for the MCF5307EVM 5307mux device ispLSI22LV10 MK KKK KKK KKK KK KK KKK KKK KKK KK KKK KK KKK KKK CC KKK AAA AAA KK M allowing the MCF5307 to support all 168pin 1Bank x 64 bit PC compliant D Se Se This abel file contains the code to mux the address lines IMMS It was targeted to Lattice ispLSI 22LV10 PAL All logic with this PAL is com NCS24C86 T WAKKKKKKKKKKKK KKK KKK KKKK KKK KKK KK KKKKKK KK KKK S S S E e KU KK KM MK KKK KKK KK KKKKK KKK KKK KKK KKKK KKK KKK KK KKK KK KKK KKK A S KU KU KU KK M Se Declaration Section WKKKKKKKKKKKK ck kokokok ck ck ck Kok Kok ok ck Kk KK KK kk KK KK Sk Sk Kk KK KK KK Kk Sk Sk Kk Kk Kk Kk Kk KM constants C P X A H L Copo Porra LO VLA CA CK CK CK CC CC CC CC SCC CK COCOS CK CK KC CK SK S AAA AAA AAA KM MO PIN 3 Mux Input 0 M1 PIN 4 Mux Input 1 M2 PIN 5 Mux Input 2 M3 PIN 6 Mux Input 3 CA18 PIN 2 Input ColdFire driven address 18 CA19 PIN 7 Input ColdFire driven address 19 C
46. 8 JS JP7 JP 1 AUX erminal JP8 9 JP13 12 Pees Figure 3 Jumper Table and Locations us JP2 BACKGROUND DEBUG DM Canrector U LL R32 TERM NAL TES amc SDRAM AMM 6 5V to 9V Input M TROPROCESSOR EXPANSDN BUS Figure 4 System Configuration Freescale Semiconductor Inc 1 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 10 SYSTEM POWER UP AND NITIAL OPERATION Now that you have connected all the cables you may apply power to the board After power is applied the dBUG initializes the board then display power up message on the terminal which includes the amount of the memory present Hard Reset DRAM Size 8M NE2000 0x300 Copyright 1997 1998 Motorola Inc All Rights Reserved ColdFire MCF5307 EVS Debugger Vx x x xxx 199x Xxx xx xx Enter help for help dBUG The board is now ready for operation under the control of the debugger as described in Chapters 2 If you do not get the above response perform the following checks 1 Make sure that the power supply is properly set and connected to the board 2 Check that the terminal and board are set for the same character format and baud 3 Press the red RESET button to insure that the board has been initialized properly If you still are not receiving the proper response your board may have bee
47. A20 PIN 9 Input ColdFire driven address 20 CA21 PIN 10 Input ColdFire driven address 21 CA22 PIN 11 Input ColdFire driven address 22 CA23 PIN 12 Input ColdFire driven address 23 CA24 PIN 13 Input ColdFire driven address 24 CA25 PIN 16 Input ColdFire driven address 25 CA26 PIN 23 Input ColdFire driven address 26 CA27 PIN 21 Input ColdFire driven address 27 SA8 PIN 24 Output SDRAM input address A8 SA9 PIN 19 Output SDRAM input address A9 SA10 PIN 25 Output SDRAM input address A10 SA11 PIN 17 Output SDRAM input address A11 SA12 PIN 27 Output SDRAM input address A12 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SA13 PIN 20 Output SDRAM input address A13 BAO PIN 18 Output SDRAM input address BAO BA1 PIN 26 Output SDRAM input address BA1 select M3 M2 M1 M0 VA CA CK CK CK C CC CK CC CC CC CK S S KU A X MK KG KU Lattice attributes VA CA CK CK CK C CC CK CCS CK C S S KK M X MK KM pLSI property CLK XCLKO CLKO pLSI property CLK CLK8MHZ SLOWCLK pLSI property ISP ON pLSI property PULLUP ON pLSI property Y1 AS RESET OFF equations Md COMBINATORIAL Logic Only dd when select 0 then SA8 CA18 SA9 CA19 SA10 CA20 BAO CA21 BA1 CA22 when select 1 then
48. A26 R_CASO DOMO A_CAS1 DQM1 3 BWE2 22 A A27 R_CAS2 DQM2 R CASS DQMS us 5 BWE3 22 26 A28 R_RASO SO R RAS1 SO2 14 3 2 OE z 28 A29 R DRAMW R SRAS TXD2 h on H 0 CS4 a x A30 R SCAS R SCKE RXD2 i2 DO RX1 Fe il C95 2233 34 A31 5 RTS2 22 13 DI2 TX2 4 EUR RSTO CTS2 10 DO2 RX2 7 Te E TH O s TRETE Al 3 R W 7 Dos RX3 aie E 1 0 PORT t e 433 45x d vec vss s 1 VDD GND 1 SION EA MC145406DW AUXILAR 3 3 1 R2 4 7K P 398 J 0 1 UF R34 1 2 JP7 x BKPT_TMS 47K op sus Ue us E 4 SET Sr gt x PSTIO 3 u22 BDM_RSTI X 7 7 DSDI TDI ifyo Vat 1 12 DSDO_TDO pgrg gulat r PST2 13 14 PSTI u17 R35 PSTO 15 16 DDATAG EROS CU 1 Fe CLKIN SLOW mE E 22 2 vn Q vouT 2 433 DDATA 0 3 gt 22 ee PSTCLK DERE J C49 ces U18 10 UF TANT 0 1 UF yi 283___B78_ 022 BcLK SRAM d y2 SL __R86_n A 22 T BCLKOB BCLKO X a ya 2 Bas 22 BCLK_FPLA Pi A ya HB R84 2 BCLK_SDRAMO T WN og VONT iis L Po 2 16 R83 22 C36 vs 22 XC EDGESEL Pi S O UF TANT 10 UF TANT C37 i ve H4 R82 22 BCLK SDRAM A 2 1 amp BCLK SDRAM 0 3 433 ijwe wH R81 22 BCLK_SDRAM2 i 1 1 1N5404CT gt VCC2 1 15 Voss va 2 R80 22 BCLK_SDRAM3 r x o vec4 i 4 vo BB A A 22 BOLKOHEADER 3 200 UF 5 72 GND1 2 M 13 802 vio EX gt n 17 GND4 C55 C56 71 c72 C73 h 20 GNDS O 1UF O1UF 0 1 UF 0 1 UF sit e z Gna 4 4 i ody MCF5307 Evaluation Board 1 the 10uF which re TAN Size Document Number Rev CDO351DW Pede B MCF530
49. CK CK S A UK KK KU KM EI Declaration Section POL ORAN NI RRA RR RSIS a GN IS o S as Ru Rs Qd Adv woo A sb adu dc a ai ut E sons AMT constants Ci Pyke Zig By SC pe Ps pea A O kA CC CK KKK KKK KK KK KKK KKK KKKK KKK KKK KKK KKKK KKK KKK AAA KM LRO 0 compatible ethernet abort DLY TOCHRDYO node ISTYPE DLY IOCHRDY EN D STARTISA node ISTYPE SBHE DA OR IOW DLYDA node SAOE node ISTYPE ABORTML DAOE CLK16MHZ node reg d buffer reg d buffer ISTYPE reg d buffer T END16 END8 node reg d buffer CLK4MHZ node ISTYPE reg_d buffer RSTMH node BCLKO node ISTYPE reg_d buffer BCLK1 node ISTYPE reg d buffer BCLK2 node ISTYPE reg d buffer ABORTOL prn 3 ISTYPE reg d butter RST L pin 4 Output to ColdFire DB CS L pin 5 Output Data buffer ethernet AOIN pin 6 INPUT A0 received from IOCHRDY pia Input asserted by TOCS16L pin 9 Input asserted by SIAL pin 10 For More Information On This Product Go to www freescale com reset enable for CF through buffers ethernet ethernet Freescale Semiconductor Inc XCLKO pin 11 Input global clock TOWL pin 15 Input writ
50. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 1 Example SDRAM DIMMs Capacity of Chips Chip Organization Chip Density rado as 8 MBytes 4 1 Mbits X 16 16 Mbits 11 rows 8 columns 1 bank select 16 MBytes 8 2 Mbits X 8 16 Mbits 11 rows 9 columns 1 bank select 32 MBytes 16 4 Mbits X 4 16 Mbits 11 rows 10 columns 1 bank select 16 MBytes 2 2 Mbits X 32 64 Mbits 11 rows 8 columns 2 bank select 32 MBytes 4 4 Mbits X 16 64 Mbits 12 rows 8 columns 2 bank select 64 MBytes 8 8 Mbits X 8 64 Mbits 12 rows 9 columns 2 bank select 128 MBytes 16 16 Mbits X 4 64 Mbits 12 rows 10 columns 2 bank select 32 MBytes 2 4 Mbits X 32 128 Mbits 12 rows 8 columns 2 bank select 64 MBytes 4 8 Mbits X 16 128 Mbits 12 rows 9 columns 2 bank select 128 MBytes 8 16 Mbits X 8 128 Mbits 12 rows 10 columns 2 bank select 256 MBytes 16 32 Mbits X 4 128 Mbits 12 rows 11 columns 2 bank select 64 MBytes 2 8 Mbits X 32 256 Mbits 13 rows 8 columns 2 bank select 128 MBytes 4 16 Mbits X 16 256 Mbits 13 rows 9 columns 2 bank select 256 MBytes 8 32 Mbits X 8 256 Mbits 13 rows 10 columns 2 bank select 512 MBytes 16 64 Mbits X 4 256 Mbits 13 rows 11 columns 2 bank select One bank select line selects between two banks within the SDRAM component Denotes a double sided module The memory from only one side can be used due to the SDRAM controller
51. Freescale Semiconductor Inc M5307C3 USER S MANUAL REVISION ld Matrix Design amp Manufacturing Inc 2914 Montopolis Drive 290 Austin TX 78741 Phone 512 385 9210 Fax 512 385 9224 http www cadreiii com For More Information On This Product Go to www freescale com Freescale Semiconductor Inc COPYRIGHT Copyright 1999 by Motorola SPS All rights reservedNo part of thismanual and the dBUG software provided in Flash ROM s EPROM s may be reproduced stored ina retrievalsystem or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise Use of the program or any part thereof for any purpose other than single end user by the purchaser is prohibited DISCLAIMER The informationinthismanual has been carefullyexamined and isbelievedto b ntirelyreliable However no responsibilitysassumed for inaccuracies Furthermore Motorola reserves the rightto make changes to any product s herein to improve reliabilitfunction or design The M5307C3 board is not intended for use in lifeand or property criticalapplications Here such applicationsare defined to be any situationin which any failuremalfunction or unintended operation of the board could directly or indirectlyfhreaten life resultin personal injury or cause damage to property Although every effort has been made to make the suppliedoftware and itsdocumentation
52. O C0 WwW Ww PrRFoO DONA ADA OB WN ER THE SDRAM DIMM 54 RESI FLASH ROM55 3 3 1 JP1 Jumper and User s Program 55 4 THE SERIAL COMMUNICATION CHANNELS 56 UL The MCF5307 2 UARTs 56 3 14 De Motorola Bus M Bus Module 56 2 THE PARALLEL I O Port 56 6 ON BOARD ETHERNET LOGIC 57 27 THE CONNECTORS AND THE EXPANSION BUS 59 S E The Terminal Connector P4 59 3 7 2 The Auxiliary Serial Communication Connector P3 60 3447 Logical Analyzer connectors LA1 5 and Processor Expansion Bus J3 61 Su 13 The Debug Connector J170 V For More Information On This Product Go to www freescale com J4 amp JS Freescale Semiconductor Inc APPENDIX A Configuring dBUG for Network Downloads 1 A 1 Required Network A 2 Configuring dBUG Parameters l Network Parameters l A 3 Troubleshooting Network Problems 3 APPENDIX B ColdFire to ISA IRO7 and Reset Logic APPENDIX C Schematics 2 APPENDIX D SDRAM MUX APPENDIX E SDRAM MUX APPENDIX F EVALUATION MCF5307EVM_BOM 1 PAL EQUATION 1 WHITE PAPER 1 BOARD BOM 1 vi For More Information On This Product Go to www freescale com Abel code 1 Freescale Semiconductor Inc TABLES Table Table Table Table Table Table Table Table 9 0 10 tt Non JPl Upper Lower Half BOOT JP2 CSO select dBUG Commands The M5307C3 memory map The P4 Terminal Connector pin assignment The P3 Connector pin a
53. P D53 H4 pat 23 126 411 D52 142 D19 o Q5 24 132 A12 D51 141 D18 voae 34 A13 D50 HAL Bi 15 voa C22 122 D49 39 Die 16 vojas H 28 Bao Das 152 Dis 17 violas 128 BAI D47 Hes Dar 18 R_SCKE 253 69 CKEo D46 191 D29 19 EH CKE1 Das 191 D no 43 3 R55 R ScAs 115 CAS D44 99 D2 i R_SRAS JH RAS pas 2 Dar SCLK 3e 47K R DRAMW WE D42 Pee Sol 22 1D 131 Dai Tos D24 SDO 2 T00 vec 1354 Daz Dao H Dat MODE MODE GND 113 DQM6 D39 93 D22 iSpGALZ2LV10 SMT socket E AS hd 1 3 Bama E 32 D21 R_CAS2 DQM2 1 44 ava D36 fet pag amk RLCAS3 DOM3 46 pov D35 2 F 28 DOMI D34 87 D17 DOMO D33 haz mn R_RAS1 SO2 451 soz bat E Dis Aso Re R73 o 773 76 Did R58 433 RCRASO SOQ 114 00 D30 775 D13 4 7K 4 7K 4 7K 129 so1 D29 74 D12 47K so3 D28 72 I 82 D27 771 D10 SDA 22 SDA D26 75 Be SCL SCL D25 2 B ul dr 166 SAT D22 66 DA 165 65 D5 SA0 D21 60 D4 D20 58 D3 43 3 VDD1 D19 57 D2 E VDD2 Dis ee e VDD3 D17 E oi VDD4 D16 Pee po VDD5 D15 H2 pie VDD6 D14 HS Dr VDD7 DISHE B VDD8 D12 H Di VDD9 Dit H Bit VDD10 D10 13 Da VDD11 Do H be VDD12 Ds D VDD13 07 Ly bz VDD14 Ds De VDD15 os H Ds VDD16 D4 HE o VDD17 Ds m 1 D2 3 Dt vsst D1 H al vss2 Do vss ee vssa DU is VSS5 DU2 455 vsss bus 8 vss7 cBo Hat VSS8 CB ES vsso CB2 C107 C108 C109 C110 C111 VSS10 CB3 53 O1UF O1UF O1UF O1UF 0 1UF VSS11 CB4 2S VSS12 CBs HRES d vssi3 CB6 1372 vssi4 CB7 gt vss1s VREF1 43 3 vssig V
54. PF 1500PF 1500PF 1500PF 1500PF 1500PF 1500PF 1500PF 1500PF 1500 PF MCFS307 Evaluation Board A A Y T Bize Document Number Fev B MCF5307 CONNECTORS 3 0 ale Thursday April 01 1999 Bheet 2 o FB_D 16 31 gt U25 Bi Buffers AJO 31 gt Fe KMA 0 19 D16 2 VEA a we Ag fin mao 27183 1A3 Al 46 tap TE 6 A 44 M 8 1B4 1A4 A3 43 1A3 MA3 1B5 1A5 1A4 186 1A6 Ad 41 2M m Dee 11 igz 1A7 A 40 a2 T D23 312 188 1A8 n 38 1 223 Ls D24 15 281 2A1 A 37 2A4 M D25 14 28 PA AB 36 2M MAS A9 35 MA9 m fe Ma 285 2A5 All 32 3a MALL D29 20 2B6 2A6 A1 30 4A1 MAL pao 22 286 S A13 29 Ap MAIS Dai 25 287 ro Ald 27 442 MA14 A15 26 443 MA15 RW Hir vec H 33 CS0_EN pa
55. QB13 2 E A17 D6 sew QB12 Z2 5 A16 D5 QB11 Ts Dig A15 D4 BWE2 2 SBD QB10 68 DIS A14 D3 BWEO SBC QB9 T A13 D2 BWE1 39 SBB E a A12 D1 BWE3 SBA aas 6 gt X D A11 Do QA7 HS B A10 LBO Qas Fee E A9 QA5 5 Y AB RY BY SET aas 5 is AT NC4 SE2 QAS 23 7 e AG NC3 cs2 X SE3 QA2 25 2 A5 NC2 QA HT M NGI Net QAO A3 NC2 E A2 vcc1 NC3 nos Fes E A VCC2 NC4 NC e6 33 3 MA 0 19 gt A0 NC5 NCB 22 cee GND1 VDD1 24 GND2 VDD2 oE GND2 GND3 VDD3 r GND1 GND4 VDD4 R45 We GNDS VDD5 io GND6 VDD6 43 3 RESET GND7 VDD7 GND8 VDD8 47K GND9 VDD9 AM29LVODAT 100EC GND10 VDD10 GND11 VDD11 GND12 VDD12 MCM69F737TQ11 not populated at assembly 43 3 j 4 C77 C78 C58 C92 ces 0 1 U 0 1 UF 0 1 UF 0 1 UF 0 1 UF 1 ak ille t MCF5307 Evaluation Board ze Document Number Rev B MCFS307 FLASH 3 0 ate Thursday April 01 1999 Bheet E MA 0 19 gt U23 161 1 Ao D63 L Dat Al D62 159 D29 A2 D61 158 D28 SDRAM MUX A3 D60 136 I U24 M D59 155 D26 A5 D58 134 D25 vo ao AG D57 1 Bas CLK vodi ES 207 A7 D56 12 a 9 VOIQ2 7 48 D55 ep D n 1O Q3 51 5g 49 D54 49 2 10 Q4 7384 A1O_A
56. REF2 146 17 VSS18 amp BCLK_SDRAM 0 3 CLKO T 1 t t t t t 35 Nco CLK 4 7 BOEK SDRAME 3 NC1 CLK2 En Nez GL 163 BCLK SDRAMS C95 C97 C99 C100 C101 C102 C103 C105 Xx 61 3 109 5 0 1 UF o1UF orur o1UF o1uF o1UF 0 1UF O1UF 0 1 UF EIN Nes Nos 49 Me MCFS307 Evaluation Board NOS Noto 108 145 T 2 d d gt zu le hebt Er Size Document Number Rev B MCF5307 SDRAM 3 0 PC100 Unbuffered 1 Bank x 64 DIMM 8M or 16M support up to 512M late Thursday April 01 1999 Bheet lt D 0 31 D R51 T4 HARD RESET 47K aid st y T6 AA Ti6 v T17 o d 5 vec y y SENSE 4 A RESET E D2 Ro A cT 6 4 RESET Ki T15 T2 CONTROL H GREENLED 270 e 4 GND T3 0 1 UF oW 18 uoo vost He s z TLC77331D RW Qe TH 1101 1030 F2 1016 ECLK Tg O2 vo29 7 BALE Qo 184 vos vo28 FS IOCHRDY SAO 20 104 11027 Fs MAO 22 1 vos 11026
57. Refer to the MCF5307 User s Manual for programming and the register map 344 2 s Motorola Bus M Bus Module The MCF5307 has a builtinM Bus module which allows interchipbus interface fora number of I O devices Itiscompatible with industry standard I C Bus The M5307C3 uses thisto access the SDRAM eeprom parameters The two M Bus signalsare SDA and SCL which are availableat LA4 connector These signalsare open collectorsignals However they have pull up resistorson the M5307C3 These signalsare connected to the SDRAM DIMM module I C interfacebut not used by the debugger The interruptcontrolregisterfor M Bus is set for Level 3 priority 0 and autovector 3 5 THE PARALLEL I O Port The MCF5307 has one 16 bit parallelport Allthe pins have dual functions They can be configured as I O or their alternate function via the Pin Assignment register Allparallelport pins are configured as I O pins by the ROM Monitor 56 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc P 3 0 connects to the SDRAM mux control and LEDs P 7 4 connects to LEDs P 15 8 are general purpose parallel port inputs 3 6 ON BOARD ETHERNET LOGIC The M5307C3 includesthe necessary logic drivers and the NE2000 compatible Ethernet chip to allow 10M bit transfer rate oretework The Ethernet spac ad
58. S SSBSSSS IE Picea SANSA EEA a 2299 Mara EB FEF SDA SDA 2222222220909090009099099009290900 8 ZEEE agpo een z233 Rag 2K 660600000066666666666666666666656 S S555 F Filio EELS aaa prea HKPL 3 3 lt Ann R22 _ 2K y E dddd J d E TA 4 MTMODS amp DDATA 0 3 4 7K 338i MTMODI DUE MTMODO Pn R25 2 R312R32 R33 DDATAO PLL3 3 4 7K 4 7K 947K 94 7K TOUT lt gTouTo R74 a TOUT TINO R49 C85 C86 TIN1 TINA 4 7K 1500 PF 1500 PF 10 CSL CTS2 SE SS RTS2 IS HARD WIRED i SS AXD2 CST mos CTSt 43 3 RIS1 mE RTSt m RXD1 TXD1 c6 c7 C8 c9 C10 C11 C12 C13 C79 C80 C81 C82 C83 itle 1500PF 1500PF 1500PF 1500PF 1500PF 1500PF 1500PF 1500PF 1500PF 1500PF 1500 PF 1500 PF 1500PF MGF5207 Evaluation Board 1 Bize Document Number Fev x 5 B MCFS307 CPU 30 ate Thursday April 01 1999 Bheet 1 of B k Ei ll ES z 2 Mictor NTROL o G1 G2 G3 G4 39 40 41 42 43 Gs V stor Connector AMP 767054 1 43 3 A AH A C20 C21 1500 pr 1500 PF A C38 1500 PF 43 3 Mictor Al A s 77 Mictor DEBUG Mictor DRAM LA3 D 0 31 PSTCLK gt gt 38 Las LAS LA2 37 NC4 38 38 27 NC3 37 NC4 Sar NC4 NC4 2 NC2 2 1 Nes 27 Nes NC3 X NC1 3 2 Ne
59. SA8 CA19 SA9 CA20 SA10 CA21 BAO CA22 BA1 CA23 when select 2 then SA8 CA19 SA9 CA21 SA10 CA22 BAO CA23 BA1 CA24 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc when select 3 then SA8 CA18 SA9 CA19 SA10 CA20 SA11 CA21 BAO CA22 BA1 CA23 when select 4 then SA8 CA19 SA9 CA20 SA10 CA21 SA11 CA22 BAO CA23 BA1 CA24 when select 5 then SA8 CA19 SA9 CA21 sA10 CA22 sA11 CA23 BA0 CA24 BA1 CA25 when select 6 then SA8 CA19 SA9 CA21 SA10 CA23 SA11 CA24 BAO CA25 BA1 CA26 when select 7 then SA8 CA18 SA9 CA19 SA10 CA20 SA11 CA21 SA12 CA22 BAO CA23 BA1 CA24 3 For More Information On This Product Go to www freescale com when select when select when select Freescale Semiconductor Inc 8 then SA8 CA19 SA9 CA20 SsA10 CA21 SA11 CA22 SA12 CA23 BAO CA24 BA1 CA25 9 then SA8 CA19 SA9 CA21 SA10 CA22 SA11 CA23 SA12 CA24 BAO CA25 BA1 CA26 h0A then SA8 CA19 SA9 CA21 SA10 CA23 sA11 CA24 SA12 CA25 BAO CA26 BA1 CA27 WIXKKXKKKKXKKKXKKXKXKKXKKKXKKKKKKKKKKKKKKKAAAKAKKAKAAAAAA AAA AAA NM gt test vectors MO M1 M2 M3 Test Vector M3 M2 M1 MO CA18 CA19 CA20 CA21 CA22 CA23 CA24 SA8 SA9 SA10 SA11 SA12 BAO BA1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X15 0 0 0
60. SDRAM address of the memory installedin the board When first learning the system the user should limit his her activities to thisfarea the memory map Address range 00000000 0001FFFF is used by dBUG 2 If a command causes the system to access an unused address i e no memory or peripheral devicee mapped at that address a bus trap ermoay occur Thisresultsinthe terminal printingout a trap error message and the contents of all thMCF5307 core registers Control isreturned to the dBUG monitor 2 3 TERMINAL CONTROL CHARACTERS The command line editor remembers the last five commands in a history buffer which were issued They can be recalled and then executed using control keys Several keys are used as a command lineeditand controlfunctions Itisbest to be familiarwith these functions before exercising the system These functions include a RETURN carriage return willenter the command lineand causes processing to begin b Delete Backspace ke or CTRL H will delete the last character entered on the terminal c CTRL D Go down in the command history bufferyou may modify then press enter key d CTRL U Go up inthe command historybuffer you may modify then press enter key 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc e _CTRL R Recalland execute the last comm
61. T 5 RSS I 9 REO R41 RETO y RIS ROO ROL RS y ROOI R84 R85 R86 IRZ 3 1822 0805 body style R74 0805 body style a c Olas 100mi IL SePil SPA2 SP 3 524 inline iesxstor package Si 1 C amp K 2 11 C amp K 3 For More Information On This Product Go to www freescale com P 7 P4 P3 5 1 0205 body styl Freescale Semiconductor Inc L e to mA tS SP T i d TROT Points S TLO T11 T112 T13 T 15 T16 11 MEP SS07E 190 Motorola Colle Motorola RS232 drivers Motorola R2232 drivers TECT 1018 Jr 3c EAS ANGUS Ar d OSC 20 MHZ Plerronics P1100 HC5S 2191212 OE Halo Electronice Topu P0 S7 LOL SMT socket MC145407DW MC145406DW Lattice 44pin PLCC w SMT socket MOEOLOLA Gioxi Wini MC74LCX244DW directional buffer MC74LCX16244 He ES DT directional buffer DM9008F Davicom ANOS ES Zal Mot populated during assembly O E seen 10 MC74LCX16245 Messsesss EMEN DT directional buffer CASAS SDE Sb DW I 24pin SMT package MEMEO RETE NOI 1 not populated during assembly AM2 9LV004T AMT 40 pin T OP dE gu 6 package OSC 45 MHZ Plerronics P1100 HCV PC100 Unbuffered 1 Bank x 64 DIMM 8M or LOM support up ce 168 DIMM socket w 4 For More Information On This Prod
62. This Product Go to www freescale com Freescale Semiconductor Inc The M5307C3 uses IRQ7 to support the ABORT functionusing the ABORT switch S1 black switch This switsmsed to force a non maskable interrupt level 7 priority 3 if the user s program execution shou ldobted without issuing a RESET referto Chapter 2 for more information on ABORT Since the ABORT switch is not capable of generating a vector in response to level seven interrupt acknowledge from the processor the debugger programs this request for autovector mode The IRQ1 line of the MCF5307 is not used on tard However the IRQl1 is programmed for Level 1 with priority dnd autovector The user may use this linefor external interruptrequest Refer to MCF5307 User sManual for more information about the interrupt controller Sud Vs Internal SRAM The MCF5307 has 4K of internal memory This memory is mapped to 0x20000000 and isnot used by the dBUG It isavailableto the user The memory is relocatable to 32K byte boundary Salag The MCF5307 Registers and Memory Map The memory and I O resources of the M5307C3 are divided into three groups MCF5307 Internal External resources and the ethernet controller Allthe 1 0 registers are memory mapped The MCF5307 has builtin logicand up to eight chip selectpins CSO to CS7 which are used to enabl xternal memory and I O devices In additionthere are two RAS lines
63. YIOCHRDYO IOCHRDY DLYIOCHRDYO clk CLK8MHZ DLYIOCHRDY IOCHRDY amp CLK8MHZ DLYIOCHRDY amp CLK8MHZ PEEL i didi di ir di dii di diri dio ir di iri di ir di dir ir di ii do ir di ir d ir di diro ir di iri i rdi iro di rdi dir ir di ri AM Test Vector Section e kA CK C CK CC CK 0C CC CK CC CC CC CK CK Ck CK C Sk S C E KK A KK MK KU KU KM test vectors HIZ L Test Vector XCLKO RSTIN L PORIN L BDM RST L CS3 L RST H P 1 1 1 1 1 gt X ec 1 1 1 1 1 gt X Ej y SA TE C 1 0 1 1 gt X Cpl ply gt X Clipe gt X C7 0 2 ply Ll XT 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc X X X X m Mies gt gt 1 0 0 4 end For More Information On This Product Go to www freescale com DUJ 1032npuooiuies 9 e2so94J C Schematics APPENDIX DUJ 1032npuoaoiuies 9 e2sooJJ
64. able referto the MCF5307 User s Manual The processor goes to a exception routine via the exception taBhestableis in the Flash andhe VBR points to it However a copy of thistableismade in the RAM starting at 00000000 To set an exception vector the user pt ees address of theexception handler inthe appropriate vector inthe vector table located at 00000000 and then points the VBR to 00000000 The MCF5307 has four external interruptrequest lines You can program the external interruptrequest pinsto levell 3 5 and 7 or levels2 4 6 and 7 The M5307C3 configures these linesas levell 3 5 and 7 There are also six internalinterrupt requests from Timerl Timer2 Software watchdog timer UART1 UART2 and MBUS Each interruptsource external and internal can be programmed forany prioritylevel In case of similarprioritylevel a second relative priority between 0 to 3 will be assigned However the software watchdog is programmed for Level 7 priority2 and uninitializewector The UART1 is programmed for Level 3 priority2 and autovector The UART2 isprogrammed for Level 3 priorityl and autovector The M Bus isat Level 3 priority and autovector The Timers are at Level 5 with Timer 1 with priority3 and Timer 2 with priority2 and both for autovector NOTE No interrupt sources should have the same level and priori as another 50 For More Information On
65. ale com Freescale Semiconductor Inc NATURAL16 reserved 0x10000 0x0012 2 Odd registers NATURAL16 CLDAO CLDAO rd PSTART wr NATURAL16 BNRY Boundary pointer rd wr NATURAL16 NCR NCR rd TBCRO wr NATURAL16 ISR Interrupt Status Register rd wr NATURAL16 CRDA1 CRDA1 rd RSAR1 wr NATURAL16 RBCRI1 Remote Byte Count 1 wr NATURAL16 CNTRO CNTRO rd TCR wr NATURAL16 CNTR2 CNTR2 rd IMR wr paged struct Even registers NATURAL16 PARI Physical Address Byte 1 NATURAL16 PAR3 Physical Address Byte 3 NATURAL16 PAR5 Physical Address Byte 5 NATURAL16 MARO Multicast Address Byte 0 NATURAL16 MAR2 Multicast Address Byte 2 NATURAL16 MAR4 Multicast Address Byte 4 NATURAL16 MAR6 Multicast Address Byte 6 NATURAL16 reserved 0x10000 0x0010 2 Odd registers NATURAL16 PARO Physical Address Byte 0 NATURAL16 PAR2 Physical Address Byte 2 NATURAL16 PAR4 Physical Address Byte 4 NATURAL16 CURR Current Page Register rd wr NATURAL16 MARI Multicast Address Byte 1 NATURAL16 MAR3 Multicast Address Byte 3 NATURAL16 MAR5 Multicast Address Byte 5 NATURAL16 MAR7 Multicast Address Byte 7 pagel struct
66. and entered does not need the enter key to be pressed For characters requiring the control key CTRINe CTRL should be pushed and held down and then the other key H should be pressed 2 4 dBUG COMMAND SET Table 3 liststhe dBUG commands Each of the individual commands is described in the following pages 2 t For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 dBUG Commands SYNTAX PAG ASSEMBLE AS addr inst tion 25 11 BLOCK COMPARE IRST SECOND ENGTH 25 14 BLOCK FI BF WIDTH BEGI DATA BLOCK MOVE BM BEG DEST BLOCK SEARCH BS WIDTH BEGI BREAKPOI BR ADDR R C COUNT T IGGER DATA CONVERT DATA VALUE Hisce N do NN DOWNLOAD SERI DL OFFSET DOWNLOAD DN C E S O OFFSET 2 NETWORK ENAME Go TI GT AD BREAKPOI HELP HELP COM INTERNAL STER 1 INTERNAL I T T DATA gt ISTER MEMORY IDTH gt lt BEGI Nin N NIN NIN NF NIe NYFF Dir N Oo N Fo fa Jo Jo o a Jg Z H eG i um m y m ri um LAN E E NIN NIN NIN NIN LH Fo fo FY o 2 For More Information On This Product Go to www freescale com Freescale Semiconduct
67. and is show baud To display the TFTP server IP address the command is show server 223 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 23 STEP Step Over ST Usage STEP The ST command can be used to step over a subroutine call rather than tracing every instruction in the subroutifite ST command sets a breakpoint one instructionbeyond the current program counter and then executes th target code The ST command can be used for BSR and JSR instruction amp he ST command will work for other instructionsas well but note that ifthe ST command is used with an instruction that will not return i e BRA then the temporary breakpoint may never be encountered and thus dBUG may not regain control Examples To pass over a subroutine call the command is step 22 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 24 SYMBOL Symbol Name Management SYMBOL Usage SYMBOL lt symb gt a symb value r symb gt lt c 1 s gt The SYMBOL command adds or removes symbol names from the symbol table Ifonly a symbol name isprovided to the SYMBOL command then the symbol table is searched for a match on the symbol name and its information displayed The a option adds a symbol name and itsvalue intothe symbol table The r option removes a symbol name from the table The c option
68. as accurate and functional as possible Motorola Inc will not assume responsibilityfor any damages incurred or generated by this product Motorola does not assume any liabilitgrisingout of the applicationor use of any product or circuitdescribed herein neither does it convey any license under its patent rights if any or the rights of others WARNING THIS BOARD GENERATES USES AND CAN RADIATE RADIO FREQUENCY ENERGY AND IF NOT INSTALLED PROPERLY MAY CAUSE NTERFERENCE IO RADIO COMMUNICATIONS AS TEMPORARILY PERMITTED BY REGULATION TE HAS NOT BEEN TESTED FOR COMPLIANCE WITH THE LIMITS FOR CLASS A COMPUTING DEVICES PURSUANT TO SUBPART J OF PART 15 OF FCC RULES WHICH ARE DESIGNED TO PROVIDE REASONABLE PROTECTION AGAINST SUCH For More Information On This Product Go to www freescale com Freescale Semiconductor Inc NTERFERENCE OPERATION OF THIS PRODUCT IN A RESIDENTIAL AREA IS LIKELY TO CAUSE NTERFERENCE N WHICH CASE THE USER AT HIS HER OWN EXPENSE WILL BE REQUIRED TO CORRECT THE NTERFERENCE LIMITED WARRANTY Matrix Design warrants this product against defects in material and workmanship for a period of sixty 60 days from
69. at the current program counter the command is go at the C function main go _main at the address 0x00040000 go 40000 the command is the command is For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 2 GT Execute Till a Temporary Breakpoint GT Usage GT lt addr gt The GT command executes the target code startingat address inPC whatever the PC has untila temporary breakpoint as given in the command line is reached Example Io execute code at the current program counter and stop at breakpoint address 0x10000 the command is GT 10000 2 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 13 HELP Help HE Usage HELP command The HELP command displaysa brief syntax of the commands availablewithin dBUG In addition the address of where user code may start is given If command is provided then a brief listingof the syntax of the specified command is displayed Examples To obtain a listing of all the commands available within dBUG the command is help The help listislonger than one page The help command displaysone screen full and ask for an input to display the rest of the list To obtain help on the breakpoint command the command is help br 2 2 For More Information On This Product Go to www freescale com 2 05 34 Usage Freescale Semiconductor Inc
70. ated by simply pressing the carriage return Enter key Itwillcontinue with the address after the last display address 2 31 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 17 MM Memory Modify MM Usage MM width addr data The MM command modifies memory at the address addr The value for address addr may be an absolute address specifiedas a hexadecimal value or a symbol name Width modifies the size of the data that ismodified The value for data may be a symbol name or a number converted according to the user defined radix normally hexadecimal Ifa value for data isprovided then the MM command immediately sets the contents of addr to data If no value for data is provided then the MM command enters intoa loop The loop obtains a value for data sets the contents of thecurrent address to data increments the address according to the data sizeand repeats The loop terminates when an invalidentry for the data value is entered i e a period This command firstalignsthe startingaddress for the data access size and then increments the address accordingly during the operation Thus for the duration of the operation this command performs properly aligned memory accesses Examples To set the byte at location 0x00010000 to be OxFF the command is mm b 10000 FF To interactively modify memory beginning at 0x00010000
71. attempts to reset the board and dBUG to their initial power on states The RESET command executes the same sequence of code that occurs altpower on Thiscode attempts to initializehe devices on the board and dBUG data structures If the RESET command fails to reset board to your satisfaction Cycle power or press the reset button Examples To reset the board and clear the dBUG data structures the command is reset 2 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 244 23 SET Set Configuration SET Usage SET option value SET The SET command allows the settingof user configurableoptions within dBUG The options are listedbelow Ifthe SET command isissued without option it will show the available options and values The board needs a RESET after this command inorder for the new option s to take effect baud This is the baud rate for the first serialport on the board All communications between dBUG and the user occur using either 9600 or 19200 bps eight data bits no parity and one stop bit 8N1 Do not choose 38400 baud base Thisisthe default radix for use inconverting number from theirASC text representation to the internal quantity used by dBUG The default is hexadecimal base 16 and other choices are binary base 2 octal base 8 and decimal base 10 client Thisisthe network Inter
72. breakpoint isone but the t option allows setting the initial trigger for the breakpoint If no address is specifiedin conjunction with the c or t options then all breakpoints are initialized to the values specified by the c or t option Examples To set a breakpoint at the C function main the command is br _main When the target code isexecuted and the processor reaches main control will be returned to dBUG To set a breakpoint at the C function benchnd set itstriggervalue to 3 the command is br bench t 3 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc When the target code isexecuted the processor must at function bench a third time before returning control tempt to execut th To remove all breakpoints the command is br 2e For More Information On This Product Go to www freescale com back to dBUG Freescale Semiconductor Inc BS Block Search Usage BS lt width gt begin end data The BS command begin stopping at address end forthe the data that is compared during the The value for addresses begin and end a hexadecimal value or a symbol name converted accordin name or a number hexadecimal This command firstalignsthe starting searches a contiguous b BS lock of memory startingat address lue data Width modifies th of search val Siz may be an abso
73. command is bm 40000 80000 200000 To copy the target code data section definedby the symbols data start and data end to 0x00200000 the command is bm data start data end 200000 2 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc eS Six BR Breakpoint BR Usage BR addr lt r gt lt c count gt lt t trigger gt The BR command insertsor removes breakpoints at address addr The value for addr may be an absolute address specifiedas a hexadecimal value or a symbol name Count and trigger arenumbers converted according to the user defined radix normally hexadecimal If no argument is provided to the BR command a listingof all defined breakpoints is displayed The r option to the BR command removes a breakpoint defined at address addr Ifno address is specifiedin conjunction with the r option then all breakpoints are removed Each time a breakpoint iencountered during the execution of target code its count value isincremented by one By default the initiatount value fora breakpoint is zero but the c option allows settingthe initiatount for the breakpoint Each time a breakpoint is encountered during the executiontefget code the count value is comparedagainst the triggervalue Ifthe count value isequal to or greater than the triggervalue a breakpoint isencountered and control returned to dBUG By default the initiatriggervalue fora
74. command is di 40000 To disassemble code of the C function main the command is di _ main 2 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pid bie 2 DL Download Serial DL Usage DL lt offset gt The DL command performs an S record download of data obtained from the serialport The value for offset is converted according to the user defined radix normally hexadecimal If offset is provided then the destination address of each S regaddusted by offset The DL command checks the destinationaddress for validitylIf the destination is an address below the defined user space 0x00000000 0x00020000 then an error message is displayed and downloading aborted If the S record file contains the entry point address th amp qmrogram counter is set to reflect this address Examples To download an S record file through the serial port the command is al To download an S record file through the serial port and adjust the destination address by 0x40 the command is al 0x40 2 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Da WO DN Download Network DN Usage DN c e lt 1 gt lt s gt o offset filename The DN command downloads code from the network The DN command handle fileswhich ar ither S record COFF or ELF formats The DN command use
75. ddress 0x80000 The user shoul to refer to the compiler for this since it will depend upon the compiler used usingDiab Data a LOAD command in the linker file is used 2 Set up the jumper for Normal operation pinl connected to pin 2 3 Download to SDRAM Ifusing serialor ethernet start ROM Monitor first If using BDM viawiggler download first then start ROM Monitor by pointing PC to Oxffe00400 and run 4 In ROM Monitor run upuser command 229 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 Move jumper to 3 3V and reset pin 2 connected to pin3 User code should be running 3 4 THE SERIAL COMMUNICATION CHANNELS The M5307C3 offers a number of serial communications They are discussed i this section 3 4 1 The MCF5307 2 UARTs The MCF5307 has two builtinUART each with itsown software programmable baud rate generators one channel isthe ROM Monitor to Terminal output and the other isavailableto the user The ROM Monitor however programs the interrupt level for UART1 to Level 3 priority2 and autovector mode of operation The interruptlevelfor UART2 to Level 3 priorityl and autovector mode of operation The signals of thesbannels are availableon port LA1 and LA3 The signalsof UART1 and UART2 are also passed through the RS 232 driver receiverand are availableon DB 9 connectors J4 and J7
76. dresses are located starting at 0x40000000 The interfacebase address is 0x300 and uses IRQ3 However the Ethernet base address inour system as mentioned earlieris0x40000000 Which brings the address of chip to 0x40000300 Note that all registers should be addressed as WORD accesses even though the registersare bytes Note that the even address registersare addressed as they are no change the read word will have the byte of the data in the lower byte of the word For odd addressed bytes the address ismapped to 0x400083xx 1 Note that odd bytes are addressed as even addresses butincreased by 0x8000 Stilthe read byte will be in the lower byte of the read word Below isan example of the data structure used to define the registers For the description of the registers refer to the Data SheebDav com DM9008 a copy of this document in on ColdFire Website http www Motorola com ColdFire typedef struct NATURAL16 CR union struct Even registers NATURAL16 CLDA1 CLDA1 rd PSTOP wr NATURAL16 TSR TSR rd TPSR wr NATURAL16 FIFO FIFO rd TBCR1 wr NATURAL16 CRDAO CRDAO rd RSARO wr NATURAL16 RBCRO Remote Byte Count 0 wr NATURAL16 RSR RSR rd RCR wr NATURAL16 CNTR1 CNTR1 rd DCR wr NATURAL16 DATAPORT 57 For More Information On This Product Go to www freesc
77. e DIMM CKEO pin 128 and CKEI pin 63 which activate a low power self refresh mode of an SDRAM It is recommended that the CKE control line be left floating while the CKEO pin is connected to the SCKE pin of the MCF5307 The CKE line controls the clock select line on the back side of DIMMs and has a 10 K Ohm pull up resistor on the module itself 8 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs MOTOROLA 8 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 4 Timing Analysis To ensure the helper MUX did not interfere with the timing requirements of a standard SDRAM a timing analysis was done based on the following design assumptions BCLKO frequency 45 MHz 22 nS period BCLKO 90 MHz core clock e Clock Driver Delay 0 nS EDGESEL Connection Tied high through a pull up Data Bus Connection Connected directly to the SDRAM DIMM with no buffer in between Address Bus Connection Connected directly through the MUX to the SDRAM DIMM with no buffer in between SDRAM Control Signal Connections Connected to SDRAM DIMM through a 22 Q resistor BCLKO Rising to Valid Output The MCF5307 output signals are guaranteed to be valid a maximum of 11 nS after BCLKO is clocked high parameter B 10 SDRAM Input Setup Time 3 nS for PC66 memory and 2 nS for PC100 memory per Intel PC SDRAM specification SDRAM Input Hold Time 1 5 nS for PC66 memory and 1 0 nS for
78. e pin configuration for interfacing to a standard 168 pin unbuffered SDRAM DIMM is shown in Figure 1 however this same concept can be carried over to other PLD and pin configurations This MUX configuration is implemented in a single PLD device that has a low cost and profile minimal propagation delay and matches the drive capability of the MCF5307 This example uses a 3 3 volt Lattice ispGAL22LV 10K which has almost identical output characteristics to the MCF5307 and only presents a 5 nS max propagation delay This PLD also is available in an SSOP package 6 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs MOTOROLA 6 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc M3 2 M2 3 M1 4 M0 5 A26 6 A25 7 A24 9 A23 10 A22 11 A21 12 A20 13 14 28 27 SDRAM A13 26 SDRAM A12 25 SDRAM BA1 24 SDRAM A8 23 SDRAM A11 22 21 SDRAM A10 20 SDRAM BAO 19 SDRAM A9 18 spare 17 A19 16 A18 15 Figure 1 Pin Configuration for ispGAL22LV10K Interface to Standard 168 pin SDRAM DIMM The M 3 0 lines represent the MUX select configuration mapped from Table2 and Table3 A recommended encoding of M 3 0 is shown in Table 5 These signals can be driven by spare parallel port lines on the MCF5307 Table 5 MUX Select M 3 0 Encoding
79. e signal from ethernet RD pin 16 INPUT R W from the ColdFire CLK8MHZ pin 17 ISTYPE reg d buffer BALE pin 18 Output address latch enable AO pin 19 OUTPUT AO sent to the ethernet PORIN L pin 26 Input Suppy Voltage Supervisor CS3 L pin 22 Input From ColdFire RSTIN_L pin 27 Inpu Hard Reset switch ETHER_IRQ pin 28 Input Ethernet IRQ 3 IRQ3 pin 29 Output IRQ 3 into the ColdFire RST H pin 30 Output to the Ethernet ABORTIL pin 31 INPUT abort signal received from the Abor swith HIZ L pin 32 Output to ColdFire HIZ IORL pin 37 Input read signal from ethernet A16 pin 39 TAL pin 40 Input Output Transfer acknowledge SBHEL pin 41 Output sent to the ethernet SIZO pin 43 BDM_RST_L pin 44 Input BDM reset input VLA CA CK CK CK C CC CK CCS CC S A e KK MK x MK KK Lattice attributes WIXXKXKKKKXKXKKKXKXKXKKXKXKKXKKXKXXKKXKXXXXK KM pLSI property CLK XCLKO CLKO pLSI property CLK CLK8MHZ SLOWCLK pLSI property ISP ON pLSI property PULLUP ON pLSI property Y1 AS RESET OFF Output inverter macro OB21 MACRO X00 AO XO0 2A0 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Tristate Output inverter macro OT21 MACRO X00 AO OE XO0 0E OE X00 1 2405 CBU43 MACRO 00 01 02 CLK EN CS 200 02 clk CLK TOUD 00 Q amp
80. eescale Semiconductor Inc cw a2 cw A18 A14 A10 A8 A6 A4 A2 NC NC NC GND GNI GND GNI GND py 65 For More Information On This Product Go to www freescale com Table Table Freescale Semiconductor Inc 11 The LA1 Connector pin assignment zZ ep H zz O N Z zi N Q Jg Q Z Jg ds is GO co O Co ju N Riejeje H H x Eee Espe 12 The LA3 Connector pin assignment zZ ep GNAL NAME NC PSTCLK PSTO PST2 DREQI PP MTMOD1 RTS2 po we cn 3 ester 5 sro BAECS tem ii wrwopi L39 mes al PIN 2 4 12 14 Eo d DEA Eus DREQO PP Eli kaia i2 Rxp2 RXD2 14 exo 66 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc BKPT_TMS MT DI DI DATA1 E TDO MOD3 NC GND GND ND 67 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 13 The LA4 Connector pin assignment zZ ep N SIGNAL NO NAME 2 4 1 TINO PPLTPA C N BCLKOB R CAS2 R CASO R CAS3 a DRAMW R SCKE TOUTO DGSEL A wile ajaja O E
81. eescale Semiconductor Inc INITIALIZE COMMAND LINE INPUT FROM TERMINAL EXEGUTE COMMAND FUNGTION DOES COMMAND LINE CAUSE USER PROGRAM EXECUTION v JUMP TO USER PROGRAM ANG BEGIN EXECUTION Figure 5 Flow Diagram of dBUG Operational Mode 2 4 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Zo 22x System Initialization The act of powering up the board willinitializehe system The processor is reset and dBUG is invoked dBUG performs the following configurationsof internalresources during the initializationThe instructioncache is invalidatedand disabled The Vector Base Register VBR points to the Flash However a copy o xdc ption table is made at address 00000000 in SDRAM To take ovem exception vector the user places the address of the exception handler in the appropriate vector in the vector table located at 0x00000000 and then points the VBR to 0x00000000 The Software Watchdog Timer is disabled Bus Monitor enabled and internal timers are placed ia stop condition Interrupt controllerregistersinitialized with unique interrupt level priority pairs After initialization the terminal will display Hard Reset DRAM Size 8M NE2000 0x300 Copyright 1997 1998 Motorola Inc All Rights Reserved ColdFire MCF5307 EVS Debugger Vx x x xxx 199x Xxx xx xx En
82. ent formats The current formats ON BUS There are 8 connectors on the M5307C3 which are used to connect theard to external I O devices and or expansion boards This section provides a brief discussion and the pin assignments of the connectors Bi Desde The Terminal Connector P4 The signalson UART1 that runs through RS 232 driver receiversare used to drivethe Terminal The M5307C3 uses a 9 pin D sub female connector P4 for connecting the board to a terminal or a PC with terminal emulation software 59 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The available signals are a working subset the RS 232C standard Table5 The P4 Terminal Connector pin assignmentshows the pin assignment Tabl 5 Terminal Connector pin assignment IGNAL NAME Data Carrier Detect shorted to 4 amp 6 Receive data Lm Transmit data Data Terminal Ready shorted to amp 6 Signal Ground utput Data Set Ready shorted to 1 amp 4 ET Request to Send Clear to Send Not Used S4 4 2 The Auxiliary Serial Communication Connector P3 The MCF5307 has two built iWARTs One channel isnot used by the M5307C3 ROM Monitor and isavailableto the user Thissignalisavailableon port P3 The availablesignalsform a working subset of the RS 232C standard Table 6 shows the pin assig
83. ered either in upper or lower case depending upon the user s equipment and preference Only symbol names require that the exact case be used Most commands can be recognized by using an abbreviated name For instance entering h is the same as entering helus itisnot necessary to type th ntire command name 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The commands DI GO MD STEP and TRACE are usedepeatedly when debugging ABUG recognizes thisand allows for repeated execution of these commands with minimal typing After a command isentered simply press lt RETURN gt or lt ENTER gt to invoke the command again The command is executed as if no command line parameters were provided An additional function called the TRAPhandler allows the user program to utilizevarious routines within dBUG The TRAP 15 handler is discussed at the end of this chapter The operationalmode of dBUG isdemonstrated inFigure 5 After the system initializatiorhe board waits for a command line input from the user terminal When a proper command isentered the operation continues in one of the two basic modes If the command causes execution of the user program the dBUG firmware may ormay not be r ntered depending on the discretionof the user For the alternate case the command willbe executed under con
84. estroying the present state of the System This is accomplished by forcing a non maskable interrupt whatcall a ROM monitor routine to preserve the current state of the registers to shadow registerin the monitor for display to the user The user willbe returned to the ROM monitor prompt after exception handling 2 2 2 3 Software Reset Command dBUG does have a command that causes the dBUG to restartas ifa hardware reset was invoked The command is RESET 2 2 2 4 USER Program The user can return control of the system to the firmware by recalling viBUG his her program Instructionscan be inserted into the user program to call dBUG via the TRAP 15 handler Zia Os System Operation After system initialization the terminal will display Hard Reset DRAM Size 8M NE2000 0x300 Copyright 1997 1998 Motorola Inc All Rights Reserved ColdFire amp MCF5307 EVS Debugger Vx x x xxx 199K Xxx xx xx Enter help for help dBUG 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc and waits for a command The user can call any of the commands supporteby the firmware A standard input routine controls the system while the user types a line of input Command processing begins only afterthe linehas been entered and followed by a carriage return NOTES 1 Th user memory is located at addresses 00020000 SXXXXXXXX S XXXXXXXX is the maximum
85. etwork downloads to occufhe information that isrequired and the steps for configuringdBUG are described below A 1 Required Network Parameters For performing network downloads dBUG needs 6 parameters 4 are network related and 2 are download related The parameters are listedbelow with the dBUG designation following in parenthesis All computers connected to an Ethernet network running the IP protocol n ed network specific parameters These parameters are e Internet Protocol IP address for the computer client IP IP address of the Gateway for non local traffic gateway IP and e Network netmask for flagging traffic as local or non local netmask In addition the dBUG network download command requiresthe followingthree parameters IP address of the TFTP server server IP e Name of the file to download filename Type of the file to download filetype of S record COFF ELF or Image Your localsystem administrator can assign a unique IP address for the board and also provide you the IP addresses of the gateway netmask and TFTP server Fill out the lines below with this information Client IP IP address of the board Server IP s z A IP address of the TFTP server Gateway IP address of the gateway Netmask Network netmask A 2 Configuring dBUG Network Parameters 1 For More Information
86. fer to http www lattice com ftp ispstarter html Both the ABEL HDL and PLD equation files for the helper MUX pictured in Figure 1 can be found at the end of this application note in section 1 6 on page 11 and section 1 7 on page 16 1 2 3 Helper MUX Initialization Once implemented in a system the helper MUX in Figure 1 can be used to interface to various 168 pin SDRAM DIMMs by initializing the MUX select pins M 3 0 to the proper SDRAM configuration SDRAM configuration information can be read at boot time through a serial presence detect SPD EEPROM on the SDRAM DIMM This EEPROM contains data about the number of rows columns banks access times etc of the DIMM The SPD portion of this module is accessed on pins 82 and 83 of a 168 pin DIMM and can be connected to the SDA and SCL pins of the MCF5307 respectively Information can be read from the SPD by using these PC pins on the MCF5307 to determine the configuration of the memory This information should be read at boot time and it should be used to initialize the M 3 0 lines on the helper PLD as well as the internal MCF5307 SDRAM configuration registers Information on the MCF5307 SDRAM Controller initialization sequence can be found in the Motorola application note AN1766 D The specification for the Intel PC100 can be found at http developer intel com design chipsets memory sdram htm 1 3 System Design Besides interfacing the helper MUX to the MCF5307 other board design require
87. for DRAM s There are registers to specify the address range type of access and the method of TA generation for each chip select and RAS pins These registersare programmed by dBUG to map the external memory and 1 0 devices The M5307C3 uses chip selectzero CS0 to enable the Flash ROM s referto Section 3 3 The M5307C3 uses RAS1 RAS2 CASO CASIAS2 and CAS3 to enable the SDRAM DIMM module referto Section 3 2 CS2 for SRAM not populated and CS3 for Ethernet Bus I O space The chip selectmechanism of the MCF5307 allows the memory mapping to be defined based on the memory space desired User Supervisor Program Data Spaces 51 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Allthe MCF5307 internalregisters configuration registers parallell O port registers DUART registersand system controlregistersare mapped by MBAR registerat any 1K byte boundary Itismapped to 0x10000000 by dBUG For complete map of these registers refer to the MCF5307 User s Manual The M5307C3 board can have up to 16M bytes of SDRAM installed The first 16M bytes are reserved for this memory Refer to Section 3 2 for a discussion of RAM The dBUG is programmed in two 29LV004B Flash ROM s which only occupies 1M bytes of the address space The first 18 tes are used by ROM Monitor and the remainder is left for user use Refer to
88. fter the ROM Monitor isrunning you may issue the SET command to choose any baud rate supported by the ROM Monitor Refer to Chapter 2 for the discussion of this command 4 9 5 The Terminal Character Format The character format of the communication channel is fixed at the power up or RESET The charact pbrmat is8 bitsper character no parity and one stop bit You need to insure that your terminal or PC is set to this format 15956 Connecting the Terminal The board isnow ready to be connected to a terminal Use the RS 232 serial cable to connect the PC to the M5307C3 The cable has a 9 pin female D sub connector at one end and a 9 pin male D sub connector at the other end Connect the 9 pin male connector to P4 connector on M5307C3 Connect tBe pin female connector to one of the availableserialcommunication channels normally referred to as COMI COM2 etc on the IBM PC s or compatible Depending on the kind of serialconnector on the back of your PC the connector on your PC may be a male 25 pin or 9 pin You may need obtain a 9 pin to 25 pin adapter to make the connection If you need to build an adapter refer to Figure 2 which shows the pin assignment for the 9 pin connector on the board Tou Ys Using a Personal Computer as a Terminal You may use your personal computer as a terminal provided you also have a terminal emulation software such as PROCOMM KERMIT OMODEM Windows 95 Hyper
89. gh an open collector buffer witho pull upresistor a pull upresistorisincludedon the board All the TA s from the expansion boasdmld be connected to this line Sud Wait State Generator The Flash ROM and SDRAM DIMM on the board may require som adjustments on the cycle time of the processor to make them compatible with processor Speed To extend the CPU bus cycles for the slower devices the chip select logic of the MCF5307 can be programmed to generate TA aftex given number of wait states Refer to Sections 3 2 and 3 3 for information about the wait state requirements of SDRAM and Flash ROM respectively 3 2 THE SDRAM DIMM The M5307C3 one 168 pin DIMM socket U23 for a SDRAM DIMM This socket supports SDRAM DIMM s of 1M x 4 x 16 Bits SDRAM x 2 No special configurationis needed The DIMM speed should be a minimum of 70ns The SDRAM Access timing is 2 4 2 y LOS tiw tu Pus bus end Ey fespectrulby These timings determine how long the data idelayed after the CAS signal or the read command is asserted during a SDRAM access Thicerresponds to the tgp Specificationsin most SDRAM The other timings that correspond to the SDRAM are the active command to precharge command t ras Precharge command to active command t p last data input to precharge command Cin and lastdata out to early precharge t4
90. he application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and Ak are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Literature Distrib
91. id Output time 2 nS PC100 Memory Setup time 1 nS Clock Driver Advance 8 nS timing margin 5 nS MUX PLD max propagation delay 3 nS worst case timing margin e MCF5307 to SDRAM hold time for writes 1 nS worst case Output hold time MCF5307 for SDRAM controls 1 nS advance from clock driver 1 nS 1 nS skew from termination resistors 1 nS input hold time for PC100 Memory O0 nS timing margin The OH55J mask set MCF5307 Errata published hold time from clock rising edge is 0 0 nS Parameter B11 for normal signals and 1 0 nS for SDRAM control signals Given the additional 1 nS advance on the clock with the loaded reference signal this leaves a 1 0 nS hold time for normal 10 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs MOTOROLA 10 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc signals and 0 0 nS for control signals However SDRAM control signals are routed through 22 Ohm series termination resistors before hitting their nominal 50 pF SDRAM input load This would skew these signals by at least 1 0 nS Because 1 0 nS is required for PC100 memory this leaves 0 0 nS timing margin an adequate outcome e SDRAM to MCF5307 setup time for reads 22 nS BCLKO period 7 nS Clock to valid data for PC100 memory This is 10 nS for PC66 memory 1 nS advance from clock driver 5 5 nS Valid input to BCLKO falling setup time parameter B1
92. ion On This Product Go to www freescale com Freescale Semiconductor Inc Seed tees The Reset Logic The reset logicprovides system initializatiorrhe reset occurs during power on and asserts the signal RSTI which causes totalsystem reset The reset is also triggered by the red reset switch and resets the entire processor U5 isused to produce active low power on RESET signalwhich feeds intothe ispLSI2032 The reset switch is fed into U4 which generates a signal into U5 which then drive U9 s input for reset The U9 degenerates the system reset CF RSTI and Ethernet RESET ETH RST signals ROM Monitor performs the following configurations of internal resources during the initialization The instruction calatwalisdiatedand disabled The Vector Base Register VBR points to the Flash However a copy of the exception table is made at address 00000000 in the SDRAM The Software Watchdog Timer is disabled Bus Monitor enabled and internal timers are placed ina stop condition Interrupt controllerregisters are initializedith unique interrupt level priorityairs The parallellI O port is configured for I O Sae 3 The HIZ Signal The HIZ signalisactivelydriven by the LSI2032 U9 ThisSignalisavailable formonitor on connector LA3 and J5 Thissignalshould not be driven by the user dud The Clock Circuitry The M5307C3 uses a 45MHZ oscillator U22 to provide the
93. leboard computer has a resident firmware package that provides a self contained programming and operating environment The firmware named BUG provides the user with monitor debug disassembly program download and I O control functions This Chapter isa how to use descriptionof the dBUG package includingthe user interface and command structure 2 1 WHAT IS dBUG dBUG isa resident firmware package for the ColdFire family single board computers The firmware stored in two 512Kx8 FlastOM devices provides a self containedprogramming and operating environment dBUG interactswith the user through pre defined commands that are entered via the terminal The user interfaceto dBUG isthe command line A number of features have been implemented to achieve an easy and intuitive command line interfac dBUG assumes that an 80x24 character dumb terminal isutilizecto connect to the debugger For serialcommunications dBUG requires eight data bits no parity and one stop bit 8N1 The baud rate is 1920 arbie changed after the power up The command lineprompt is dBUG gt Any dBUG command may be entered from this prompt dBUG does not allow command lines to exceed 80 characters Wherever possible dBUG displays data in 80 columsess dBUG echoes each character as it typed eliminatingthe need for any localecho on the terminal side In general dBUG isnot case sensitive Commands may b nt
94. ler permi is provided to the AS command and the AS command has not been used since system reset then AS defaults to the beginning board If no instruction is passed to the AS command then AS prompts with the and continues to assemble instructions the AS command by inputting a period ts the use of case sensitive symbols defined by equate statements and labels which are stored in the symbol table The syntax for defining symbols and labels is as follows Symbo Symbol Symbol Symbol Label Label Constants and operands foll foll fol fol equ value equ value equ value equ value instruction may be input in several different bases decimal constant owed by hexadecimal cons owed by hexadecimal cons owed by octal constant owed by binary constant can can The assembler also supports the different syntax for the indexed displacement and immediate addressing modes 12 An 4 PC Xn or Or 12 An 4 PC Xn 2T For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 0x1234 Lor 0x1234 L Examples To assemble one move instructions at the next assemble address the command is as move l 0x25 d0 To assemble multiple lines at 0x12000 the command is as 12000 then 0x00012000 start nop 0x00012002 nop 0x00012004 lsr 1 1 d0 0x00012006 cmp 4 d0
95. lute addrespecifiedas The value for da g to th ta may be a symbol user defined radix normally address for the data access size and then increments the address according duration of the operation this command accesses Examples To search for the 16 bit value 0x123 0x00040000 and ending at 0x00 bs 40000 80000 1234 This reads the 16 bit wordocated at 0x 16 bit value 0x1234 0x00040002 and the next 16 bit value If no matabs found then the address ly during the operation Thus for the performs properly aligned memory 4 in the memory block starting at 080000 the command is 00040000 and compares itagainst the isincremented to is read and compared To search for the 32 bit value OxABCI D in the memory block starting at 0x00040000 and ending at 0x00080000 bs 1 40000 80000 ABCD This reads the 32 bit wordocated at Ox 32 bit value 0x0000ABCD If no mai incremented to 0x00040004 and the nex the command is 00040000 ch is found 32 bit value and compares itagainst the then the address is read and compared is To search the BSS section definedby th the byte value OxAA the command is bs b bss_start bss_end e symbols bss_start and bss_end for AA 2 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 For More Information On This Product Go to www freescale com
96. ments must be met to allow for the swapping of various DIMMs One consideration is the number of clock inputs Some 168 pin SDRAM DIMMs only require a single clock input on CLKO pin 42 Other DIMMs require two clocks on either CLKO pin 42 and CLK1 pin 125 or on CLKO pin 42 and CLK2 pin 79 Yet others require four clocks CLKO pin 42 CLK1 pin 125 CLK2 pin 79 and CLK3 pin 163 Thus a clock driver with at least four outputs is recommended in the board design to satisfy the requirements of a four clock input DIMM DIMMs have on board termination for unused clock inputs Use of zero delay PLL type clock driver such as the Cypress Semiconductor CY2305 CY2308 or CY2309 is highly recommended The next consideration is the connection to the DIMM chip select lines that control the module For single sided or double sided 168 pin DIMMs the MCF5307 RASO should be connected to CSO pin 30 of the module and RAST should be connected to CS2 pin 45 of the module The remaining module chip select lines CS1 pin 114 and CS3 pin 129 should be connected to the 3 3 volt DIMM power supply through pull up resistors This ensures that chips on the back side of double sided modules remain deselected i e inactive and prevents any possible contention on the data bus Because the back side of the DIMM is not being used in this design its clock select line should also be disabled A 168 pin DIMM has two clock enable lines for each side of th
97. mp CA20 CA21 M3 amp CA21 CA21 M3 amp CA20 IMO Ml amp IMO amp Ml amp amp amp amp amp amp M2 amp M2 amp MO amp M1 amp M2 amp M3 amp CA21 M3 amp CA21 M3 amp CA21 M2 amp M3 CA21 M2 amp M3 amp CA22 M2 M2 amp amp M3 amp M3 amp CA22 CA22 M2 amp M3 amp CA23 amp M2 amp M3 amp M3 amp CA21 IMO amp M1 amp amp amp amp amp IMO amp M1 amp M2 amp M3 amp CA22 M2 amp M3 amp M2 amp M3 amp M2 amp M3 M2 amp M3 amp CA23 M2 amp M3 amp CA22 CA23 CA23 CA24 CA24 M3 M3 amp CA20 i Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 17 For More Information On This Product Go to www freescale com 17 SA12 BAO BA1 18 af Il Ho dk Se ode dk Sk db Ho dk do db o dB o dk Sk Sk e Freescale Semiconductor Inc MO amp Ml amp M2 amp IMO amp MO amp M1 amp IM0 amp M1 amp IMO amp M1 MO amp M2 amp MO amp M1 IMO M1 amp M2 amp M3 amp CA22 IM1 amp M2 amp M3 amp CA23 M2 amp M3 amp CA24 M2 amp M3 amp CA25 amp M2 amp M3 amp CA21 M3 amp CA22 amp M2 amp M3 amp CA23 M3 amp CA23 M2 amp M3 amp CA24 CA24 CA25 CA25 CA26 CA22
98. n this text and a bar over the signal name in the schematics 3 1 THE PROCESSOR AND SUPPORT LOGIC This part ofhe Chapter discusses the CPU and general supporting logicon the M5307C3 board Bred Qe E The Processor The microprocessor used in the M5307C3 isthe highly integrated MCF5307 32 bit processor The MCF5307 uses a ColdFireG processes the core with 8K bytes of unified cache two UART channels two Timers 4K bytes of SRAM Motorola M Bus Module supporting the I C two byte wide parallelI O port and the supporting integrated system logic Allthe registers of the core processor are 32 bitwide except for the Status Register SR which is16 bits wide Thisprocessor communicates with external devices over a 32 bit wide data bus DO D31 with support for 8 and 16 bit ports This chdgaress 4 G Bytes of memory Space using internalchip selectlogic Allthe processor s signalsare availablethrough mictor connectors LA1 LA2 LA3 LA4 LA5 and through 100 mil headers J1 23 J4 and J5 Refer to section 3 7 for pin assignment The MCF5307 has an IEEE JTAG compatible port and BDM port used with third party tools These signals are availablgort J1 The processor alsohas the logicto generate up to eight 8 chip selects CSO0 to CS7 and support for 2 banks of ADRAM noton evaluation board or 2 banks of SDRAM on evaluation board 48 For More Informat
99. nS Input hold time for MCF5307 Parameter B4 1 nS timing margin Thus this analysis indicates all timing has adequate margin even for PC66 memory as long as a zero delay clock driver is used Although this timing analysis example is for a PC66 memory there are no timing violations when using PC100 memory either 1 5 Timing Considerations for Older OH55J Mask The timing analysis reviewed in the previous section applies to the most recent MCF5307 mask the 00J20C For those using the 0H55J mask of the MCF5307 the output hold time parameter B11 and parameter B11a have different values from the 0H55J mask Specifically the output hold time for address data and normal bus control signals is 0 0 nS and for DRAM control lines such as RAS and CAS the hold time is 1 0 nS Thus for write cycles the subtracting a 1 5 nS PC66 input hold time from a 1 5 nS MCF5307 output hold time results in a 3 nS timing margin for SDRAM signals 2 5 nS for PC100 memory In other words there is insufficient hold time The proposed solution is to use a clock driver that can provide a 1 0 nS negative propagation delay This is actually possible with the zero delay buffers from Cypress The reference output can be loaded with a 20 pF capacitor yielding a positive setup time in advance of the clock output The following is the resultant analysis for all important times e MCFS307 to SDRAM setup time 22 nS Bus Frequency 11 nS BCLKO to Val
100. net Protocol IP address of the board For network communications the clientIP isrequired to be set to a unique value usually assigned by your local network administrator server Thisisthe network IP address of the machine which contains files accessible via TFTP Your local network administrator will have this information and can assist in properly configuring a TFTP serwae dies not exist gateway This is the network IP address of the gateway for your local subnetwork Ifthe clientIP address and server IP address are not on the same subnetwork then thisoption must be properly set Your localnetwork administrator will have this information netmask This i amp he network address mask to determine ifuse of a gateway is required Thisfieldmust be properly set Your localnetwork administrator will have this information 2 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc filename Thisisthe default filename to be used for network download ifno name is provided to the DN command filetype Thisisthe default filetype to be used for network download ifno type is provided to the DN command Valid values are s record coff image and elf autoboot Thisoption allows for the automatic downloading and execution of a filefrom the network This option can be used to automatically boot an
101. nment for P3 60 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Tabl 6 N DIRECT N P3 Connector pin assignment SIGNAL NAME Data Carrier Detect shorted to 4 amp 6 output Receive data Cd Input Transmit data Th O Output Output Input Input Data Terminal Ready Out Input Out shorted to 1 amp 6 Signal Ground tput Data Set Ready shorted to 1 amp 4 Input Request to Send Clear to Send Net Usea 5 San PSs Logical Analyzer connectors LAl 5 and Processor Expansion Bus J3 J4 JD Allthe processors signalsare availableon 5 mictor connectors LAl 5 User may refer to the data sheets for the major parts arke schematic at the end of this manual to obtain an accurate loading capability A mfbshe signals are availableon J8 and J9 for easier access Tables 7 14 show the pin assignment for J3 J4 J5 LA1 LA2 LA3 LA4 and LA5 respectively Tabl 7 Th J3 Connector pin assignment PIN SIGNAL PIN SIGNAL NO NAME NO NAME 2 4 12 14 J tit 2 E eee ae ee ee tivo e f mope Tovro e mires sch 10 mpra ABLA 2 6 6 For More Information On This Product Go to www freescale com BEIM Freescale Semiconductor Inc I 17 CSO_HEAI ER A26_PP1
102. nous DRAM SDRAM dual inline memory modules DIMMs in a ColdFire MCF5307 design without re routing the board The MCF5307 integrates a Version 3 core with an 8 KByte unified cache 4 KByte SRAM an asynchronous synchronous DRAM controller and various other popular embedded peripherals For further details on the MCF5307 refer to the MCF5307 Product Brief MCF5307 D 1 1 Intoduction As the demand for lower cost higher performance embedded products increase designers are discovering new techniques for lowering the price and complexity of their embedded board platforms By integrating inexpensive fast SDRAM devices on board designs many embedded board manufacturers are realizing lower board costs Due to their large volume This document contains information on a new product under development by Motorola Motorola reserves the right to change or discontinue this product without notice O Motorola Inc 1999 All rights reserved 68 cS MICROPROCESSORS 5 1999 REV 0 1 M MOTOROLA a For More Information On This Product Go to www freescale com Freescale Semiconductor Inc use in standard PCs SDRAM devices are currently the least expensive memory available in addition to being one of the fastest memory types These devices normally come packaged in handy upgradable modules called DIMMs which contain several SDRAM components on one or both sides of the memory card Using the SDRAM controller the MCF5307 can
103. o 168 Pin Unbuffered SDRAM DIMMs 12 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc pLSI property Y1_AS_RESET OFF equations TERR REE EHR ER AE EE HHH RAE EHH REE EHR HEAR EE EO COMBINATORIAL Logic Only TERRA EE HE HEAR EE HHH REE EHH RARE EHR HEAR EE EO when select 0 then SA8 CA18 SA9 CA19 SA10 CA20 BA0 CA21 BA1 CA22 when select 1 then SA8 CA19 SA9 CA20 SA10 CA21 BA0 CA22 BA1 CA23 when select 2 then SA8 CA19 SA9 CA21 SA10 CA22 BA0 CA23 BA1 CA24 when select 3 then SA8 CA18 SA9 CA19 SA10 CA20 SA11 CA21 BA0 CA22 BA1 CA23 MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 13 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc when select 4 then SA8 CA19 SA9 CA20 SA10 CA21 SA11 CA22 BA0 CA23 BA1 CA24 when select 5 then SA8 CA19 SA9 CA21 SA10 CA22 SA11 CA23 BA0 CA24 BA1 CA25 when select 6 then SA8 CA19 SA9 CA21 SA10 CA23 SA11 CA24 BA0 CA25 BA1 CA26 when select 7 then SA8 CA18 SA9 CA19 SA10 CA20 SA11 CA21 SA12 CA22 BA0 CA23 BA1 CA24 14 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs MOTOROLA 14 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc when select 8 then SA8 CA19 SA9 CA2
104. on zero value in DO means a character is present Assembly example move l 50014 d0 Select the function trap 15 Make the call d0 contains the response yes no C example int board char present void asm move 1 0x0014 d0 select the function asm trap 15 make the call 2 4 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Lidia Ben EXIT_TO_dBUG This function function code 0x0000 transfers the control back to thebgBUG terminating the user code The register context are preserved Assembly example move l 50000 d0 Select the function trap 415 Make the call exit to dBUG C example void board exit to dbug void asm move l 40x0000 d0 select the function asm trap 15 exit and transfer to dBUG 2 4 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc CHAPTER 3 HARDWARE DESCRIPTION AND RECONFIGURATION This chapter provides a functional description ofM amp hE7C3 board hardware With the description given here and the schematic diagram providedt ae end of thismanual the user can gain a good understanding of the board s design In thismanual an active low signalisindicatedby a preceding the signal name i
105. only supporting two CS signals Two bank select lines select between four banks within the SDRAM component 1 2 Hardware Configuration Unlike ADRAM memory SDRAM does not use a symmetrical multiplexed addressing scheme one in which each address line on the DRAM device connects to two internal address lines a row and column address ADRAM memories interfacing to the MCF5307 can use a simple wiring scheme in which a single wire is added each time an ADRAM address bus grows by one bit corresponding to one row address and one column address With SDRAM however the lower 8 or 9 or 10 or 11 address lines typically do connect internally to both row and column address lines but higher address lines do not connect to column address lines This is illustrated in Table 1 where the 8 MByte module has 8 column address lines but 11 row address lines The MCF5307 SDRAM controller was designed to interface to these asymmetrical SDRAMs seamlessly Standard SDRAM component can be directly connected to the MCF5307 by following the easy connection chart found in the Asynchronous Synchronous Operation Section of the MCF5307 User s Manual Because the MCF5307 SDRAM controller can be continually re programmed to support various SDRAM configurations this advantage can be leveraged to create a helper MUX that can support swapping of these various SDRAMs in hardware MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 3 3 For More Information On
106. or Inc MEMORY MODIFY MM lt WIDTH gt ADDR lt DATA gt D IF EG QR REGISTER MO RM REG DATA RESET RESET RESET SET SET CONFIGURAT SHOW SHOW CONFIGURATIO IF R STER SPLAY RD lt REG gt D iG IO STEP STEP OVER SYMBOL SYMBOL LEN m m TRACE TRACE INTO TRACE lt NUM gt DBUG UPDATE DBUG UPDBUG Pl P DATE USER E FU UPUSER U MANAGEMENT FLASH VERSION SHOW VERSION DD DEBUG COMMAN SET OPTION lt VALUE gt NS SHOW OPTION NS STEP SYMBOL lt SYMB gt lt A SYMB VALUE gt lt R SYMB gt lt ol lt FS N WNFW NJ N JW N Jo NIJO NJO NIJO N wo Fo Jo FR FH FN Fer i D oO UPUSER VERSION DS KKKKKKK For 25 More Information On This Product Go to www freescale com Zu AS AS Usage AS lt addr gt instruction The AS command assembles absolute address specified as a hexadecimal val Freescale Semiconductor Inc Assemble instruci Instruction may be any valid ins lue tions The value for addr may be an or a symbol name truction for the target processor The assembler keeps track of the address where the last instruction s opcode was written If no address address of user space for the target address where opcode will be written until the user terminates The inline assemb
107. ows 20 address lines 8 columns 12 rows A23 10 columns 11 rows 9 columns 12 rows 21 address lines 8 columns 13 rows A24 10 columns 12 rows 22 address lines 9 columns 13 rows A25 11 columns 12 rows 23 address lines 10 columns 13 rows A26 11 columns 13 rows 24 address lines A22 8 columns 11 rows 19 address lines BA1 A23 9 columns 11 rows 20 address lines 8 columns 12 rows A24 10 columns 11 rows 9 columns 12 rows 21 address lines 8 columns 13 rows A25 10 columns 12 rows 22 address lines 9 columns 13 rows A26 11 columns 12 rows 23 address lines 10 columns 13 rows A27 11 columns 13 rows 24 address lines MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc An example of a 2 Mbit x 32 bit x 4 bank 8 MByte SDRAM using Table 2 and Table 3 is shown in Table 4 Table 4 2 Mbit x 32 bit x 4 bank SDRAM Connection to MCF5307 MCF5307 Pins SDRAM Pins A15 AO A14 A1 A13 A2 A12 A3 A11 A4 A10 A5 A9 A6 A17 A7 A18 A8 A19 A9 A20 A10 A21 BAO A22 BA1 1 2 1 Helper MUX Design By organizing the MCF5307 SDRAM controller hardware connection information in Table 2 and Table 3 the configuration of the helper MUX inputs outputs and multiplex selects can be devised One possibl
108. p CS3 L DA amp CS3 L DA clk XCLKO DLYDA CS3_L END16 amp ENDIT IOCS16L amp RD CLK8MHZ amp SBHE CS3 L amp END8 ENDIT IOCS16L amp RD CLK8MHZ CS3 L amp END8 amp ENDIT SBHE amp RD CLK8MHZ DLYDA clk XCLKO0 STARTISA CS3 L amp ENDIT 4 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc STARTISA clk CLK8MHZ CBU43 BCLKO BCLK1 BCLK2 CLK8MHZ STARTISA STARTISA BALE STARTISA amp CLK8MHZ amp BCLK2 amp BCLK1 amp BCLKO IOR IOW TOR STARTISA amp BCLK2 BCLK1 BCLKO amp CLK8MHZ amp RD IOR CS3_L TOW STARTISA amp BCLK2 amp BCLK1 amp BCLKO amp CLK8MHZ amp RD IOW STARTISA END16 BCLK2 amp BCLK1 amp BCLKO CLK8MHZ END16 amp STARTISA END8 BCLK2 amp BCLK1 amp BCLKO CLK8MHZ END8 amp STARTISA ENDIT END16 IOCS16L IOCHRDY amp DLYIOCHRDYO amp DLYIOCHRDY SBHE amp STARTISA END8 amp IOCS16L amp IOCHRDY amp DLYIOCHRDYO amp DLYIOCHRDY STARTISA END8 SBHE amp IOCHRDY amp DLYIOCHRDYO amp DLYIOCHRDY amp STARTISA DL
109. r More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 26 UPDBUG Update the dBUG Image UPDBUG Usage UPDBUG The UPDBUG command is used for updating the dBUG image in Flash When updates to the MCF5307 EVS dBUG are available the updated image is downloaded to address 0x00020000 The new image is placed into Flash using the UPDBUG command The user is prompted for verification before performing the operation Use this command with extreme caution as any error can render dBUG and thus the board useless 2 4 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 244 21 UPUSER Update User Code In Flash UPUSER Usage UPUSER number of sectors The UPUSER command places user code and data into space allocatedfor the user inFlash There are sixsectors of 128K each availableas user space To place code and data in user Flash the image is downloaded to address 0x00020000 and the UPUSER command issued This command programs all six sectors of user Flash space l swxss thisspace startingat address OxFFE20000 To program lessthan six sectors supply the number of sectors you wish to program after the UPUSER command Examples To program all 6 sectors of user FLASH space the command is upuser Or upuser 6 To program only 128K of user FLASH space the command is upuser 1 2 4 For More Information On This Product
110. re the mark of respective owners ii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS CHAPTER 1 1 1 Lal INTRODUCTION l l qe 2 GENERAL HARDWARE DESCRIPTION 1 1 3 SYSTEM MEMORY 1 4 1 4 SERIAL COMMUNICATION CHANNELS 1 4 1 5 PARALLEL I O PORTS 1 4 1 256 PROGRAMMABLE TIMER COUNTER I 5 du ON BOARD ETHERNET 1 6 1 8 SYSTEM CONFIGURATION 1 6 Len 9 INSTALLATION AND SETUP 1 6 Unpacking 1 6 Preparing the Board for Use 1 7 Providing Power to the Board 1 7 Selecting Terminal Baud Rate 1 8 The Terminal Character Format 1 8 Connecting the Terminal 1 8 0 XO XO XO 0 0 0 JO OB WN Rp Using a Personal Computer as a Terminal 1 8 Tox SYSTEM POWER UP AND INITIAL OPERATION I 13 Taai M5307C3 Jumper Setup l 13 berti Jumper JP1 Flash Upper Half Lower Half Boot 1 14 1 11 2 Jumper JP2 This jumper selects between CSO to Flash or a header 1 15 Ded USING THE BDM 1 15 CHAPTER 2 2 1 Brood WHAT IS dABUG 2 1 242 OPERATIONAL PROCEDURE 2 3 2x2 4113 System Power up 2 3 2 52 52 i System Initialization 2 5 Deck yes System Operation 2 6 Zug TERMINAL CONTROL CHARACTERS 2 7 2 4 dBUG COMMAND SET 2 8 244 T AS Assemble AS 2 11 2 4 2 BC Compare Blocks of Memory BC 2 13 234 3 BF Block of Memory Fill BF 2 14 2 4 4 BM Block Move BM 2 15 2 4 5 BR Breakpoint BR 2 16 2 4 6 BS Block Search BS 2 18 2 4 7 DATA Data Conversion DATA 2 20 2 4 8 DI
111. s Trivial File Transfer Protocol TFTP to transfer files from a network host In general the type of file to be downloadad the name of the filemust be Specified to the DN command The c option indicatesa COFF download the e option indicatesan ELF download I option indicatesan image download and the s indicates an S record download The o option works only in conjunction with the s option to indicateand optionaloffset for S record download The filename ispassed directlyto the TFTP server and therefore must be a valid filename on the server If neither of thec e i s or filename options are specified then a default filename and file type will be usedefault filename and filetype parameters are manipulated using the set and show commands The DN command checks the destination address for validity If the destination is an address below the defined user spatben an error message is displayed and downloading aborted For ELF and COFF fileswhich contain symbolic debug information the symbol tables are extracted from the fileduring download and used by dBUG Only global symbols are kept in dBUGThe dBUG symbol tableisnot cleared priorto downloading so itis the user s responsibilityo clear the symbol table as necessary prior to downloading If an entry point address is specifiedin the S record COFF or ELF file the program counter is set accordingly Examples
112. s ismaintained by dBUG To change the default filename use the command set filename lt filename gt When using the Ethernet network for download ither S record COFF ELF or Image filesmay be downloaded A default filetypefor network downloads is maintained by dBUG as well To change the default filetype use the command set filetype lt srecord cofflelf image gt 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Continuing with the aboveexample the compiler produces an executable COFF file a out Thisfileiscopied to the tftp_boot directoryon the server with the command rcp a out santafe i tftp boot a out Change the default filename and filetype with the commands set filename a out set filetype coff Finallyperform the network download with the dn command Ihe network download process uses the configured IP addresses and the default filename and filetype for initiating a TFTP download from the TFTP server A 3 Troubleshooting Network Problems Most problems relatedto network downloads are a direct resultof improper configuration Verifythat allIP addresses configured into dBUG are correct This is accomplished via the show command Using an IP address already assigned to another machine will cause dBUG network download to fail and probably other severe networfsroblems Make
113. single SDRAM device For example one SDRAM component can have four internal SDRAM banks that is a 64 Mbit SDRAM is configured as 512K x 32 x 4 banks Bank selection is controlled through the bank select pins on the SDRAM SDRAM Synchronous dynamic random access memory These operate similar to asynchronous DRAMs ADRAMSs with the advantage of a synchronous clock a pipelined multibank architecture and faster speed These memories also maintain high memory density DIMM Dual inline memory module DIMMs contain rows of SDRAM components on one or both sides of the memory card This is not to be confused with the SDRAM row address lines called SRAS signals Note that in this application note all DIMMs mentioned in the design will be single sided since single sided DIMMs contain two CS lines in other words two MCF5307 banks that the MCF5307 can support Double sided DIMMs generally have four CS lines two on one side of the memory card and two on the other Because double sided modules present greater load to the address and data lines of a processor use of single sided modules are preferred Table 1 shows a fairly complete list of the extensive DIMM configurations along with their associated parameters Note that modules can have the same capacity but have different number of bank select lines row and column address lines depending on their organization 2 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs MOTOROLA 2
114. ssignment The J3 Connector pin assignment The J4 Connector pin assignment Figures Figure Figure Figure Figure Figure Ow Wh PF Block Diagram of the boardl 3 Pin assignment for P4 Terminal connectdr9Q Jumper Table and Locationsl 10 System Configuration 11 Flow Diagram of dBUG Operational Mode 2 4 vi For More Information On This Product Go to www freescale com 1 15 1 15 2 9 53 60 61 61 63 Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc CHAPTER 1 INTRODUCTION TO THE M5307C3 BOARD 1 1 INTRODUCTION The M5307C3 is a versatile singbeard computer based on MCF5307 ColdFire Processor It mawe used as a powerful microprocessor based controllerina variety of applications With the addition of a terminal it serves as a complete microcomputer for development evaluation trainingnd educational use The user must only connect an RS 232 compatibterminal ora personal computer with terminal emulation software and a power supply to have a fully functional system Provisionshave been made to connect thisboard to additionaluser supplied boards viathe Microprocessor Expansion Bus connectors to expand memory and I O capabilities Additionalboards may require bus buffers to minimize additional bus loading Furthermore provisions have been made in the PC board to permit configurationof
115. t to terminal C example void board_out_char int ch Tf your C compiler produces a LINK UNLK pair for this routine then use the following code which takes this into account J fif 1 LINK a6 40 produced by C compiler asm move l 8 a6 d1 put ch into dl asm move l1 0x0013 d0 select the function asm trap T1543 make the call UNLK a6 produced by C compiler else If C compiler does not produce a LINK UNLK pair the use the following code af asm move l 4 sp d1 put ch into dl asm move l 0x0013 d0 select the function asm trap FLO make the call 2 4 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc dendif 29 25 IN CHAR This function function code 0x0010 returns an input character from termina to the caller The returned character is in D1 Assembly example move l 50010 d0 Select the function trap 15 Make the call the input character is in dl C example int board in char void asm move l 0x0010 d0 select the function asm trap 115 make the call asm move l d1 d0 put the character in d0 Ds ed CHAR_PRESENT This function functiawde 0x0014 checks ifan input character ispresent to receive A value of zero isreturned inDO when no character is present A n
116. ter help for help dBUG If you did not get this response check the setup RefSectaon1 10 SYSTEM POWER UP AND INITIALOPERATION Note the date xxx 199x xx xx xx may vary in different revisions Other means can be used to re initializehe M5307C3 Computer Board firmware These means are discussed in the following paragraphs 2 2 2 1 Hard RESET Button Hard RESET is the red button located in the lower right side of the board Depressing thisbutton causes allprocesses to terminate resets the MCF5307 processor and board logicand restartsthe dBUG firmware Pressing the RESET button would be the appropriate action if all else fails 2t For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 2 2 2 ABORT Button ABORT is the blachutton located next to RESET button on the rightside of the board The abort function causes an interruptof the present processing a level7 interrupton MCF5307 and gives controlto the dBUG firmware This action differs from RESET in that no processor regicteemory contents are changed the processor and peripherals are not reset and dBUG is not restarted Also in response to depressing the ABORT button the contents of the MCF5307 core internal registers are displayed The abort functionsmost appropriate when software isbeing debugged The user can interruptthe processor without d
117. ter and program counter the first8 bytes of the Flash ROM The initializatiomoutine programs the chip selectlogic locates the Flash ROM s to startat SFFE00000 and the configures the rest of the internal and external peripherals Sec usd O a TA Generation 53 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The processor starts a bus cycle by providing the necessary information address R W etc and asserting TS The processor then waits for an acknowledgment TA by the addressed device before itcan complete the bus cycle TA isused not only to indicatethe presence of a device italso allows devices with different access times to communicate with the processor properly The MCF5307 as part of the chip select logic has a built in mechanism to generate TA for allexternal devices which do not have the capabilityto generate TA on their own The Flash ROM and SRAM can not generate TA The chip select logicis programmed by the ROM Monitor to generate TA internallyafter a preprogrammed number of wait states In order to support future expansionf the board the TA input of the processor is also connected to the Processor Expansion Bus J4 This allows the expansion boards to assert thislineto indicatetheir TA to the processor On the expansion boards however this signal should be generated throu
118. the PinAssignment Register PAR 1 4 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The pins are programmable ona pinby pin basis The settingof the multiplex pins are determined by the configurationbyte during reset After reset all pins are configures general purpose parallell O These pins are connected to J3 LA2 and LA3 1 6 PROGRAMMABLE TIMER COUNTER The MCF5307 has two builtin general purpose timer counters These timers are available to the user The sigfaetshe timer are availableon the LA4 to be viewed by a logic analyzer These pins are connected to J3 as well 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 7 ON BOARD ETHERNET The M5307C3 has an on board Ethernet NE2000 compatible operating at 10M bits sec The on board ROM MONITOR is programmed to allow a user to download filesfrom a network to memory indifferentformats The current formats supported are S Record COFF ELF or Image 1 8 SYSTEM CONFIGURATION The M5307C3 board requires only the following items for minimum system configuration Figure 3 1 The M5307C3 board provided 2 Power supply 6 5V to 9V with minimum of 1 5 Amp 3 RS 232C compatible terminal or a PC with terminal emulation software 4 Communication cable provided Refer to next sections for initial setup
119. the user defined radix normally hexadecimal This command firstalignsthe startingaddress for the data access size and then increments the address accordingly during the operation Thus for the duration of the operation this command performs properly aligned memory accesses Examples To fild memory block startingat 0x00010000 and ending at 0x00040000 with the value 0x1234 the command is bf 10000 40000 1234 To fill a block of memory starting at 0x00010000 and ending at 0x000406h a byte value of OxAB the command is bf b 10000 40000 AB To zero out the BSS section of the target code defined by the symbols bss start and bss end the command is bf bss start bss end 0 2 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Ped A acl BM Block Move BM Usage BM begin end dest The BM command moves a contiguous block of memory startingat address begin stopping at address end to the new address dest The BM command copies memory as a series of bytes and does not alter the original block The value for addresses begin end and dest may be an absolute address specifiedas a hexadecimal value or a symbol name If the destination address overlaps the block defined by begin and end an error message is produced and the command exits Examples To copy a block of memory startingat 0x00040000 and ending at 0x00080000 to the location 0x00200000 the
120. trol of the dBUG firmware and after command completion the System returns to command entry mode During command execution additionaluser input may be required depending on the command function For commands that accept an optional lt width gt to modify the memory access size the valid values are B 8 bit byte access W 16 bit word access cL 32 bit long access When no lt width gt option is provided the default width is W 16 bit The core ColdFire register set is maintained by dBUG These are listed belo AO A7 DO D7 BE SR All control registers on ColdFire are not readable by the supervisor programming model and thus not accessiblevia dBUG User code may change these registers but caution must be exercised as changes may render dBUG useless 227 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc A reference to SP actually refers to A7 2 2 OPERATIONAL PROCEDURE System power up and initiabperation are described in detailin Chapter 1 This information is repeated here for convenience and to prevent possible damage Leda Ls System Power up a Be sure the power supply is connected properly prior to power up b Make sure the terminal is connected to TERMINAL P4 connector c Turn power on to the board 2 For More Information On This Product Go to www freescale com Fr
121. uct Go to www freescale com Freescale Semiconductor Inc 512M ispGAL22LV10 MAA OS SMS O ce w SMT socket 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 6 For More Information On This Product Go to www freescale com
122. umns N A A23 A24 11 columns N A A24 Note that although the data bus and other control connections to SDRAM are not necessary to these discussions or detailed in these tables information on these hardware hookups can be found in the LAB5307 or SBC5307 schematics and the MCF5307 User s Manual at http www mot com ColdFire Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 4 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 2 SDRAM Address Line Connections Continued CF Address Condition SDRAM Address Column Address Row Address A22 8 columns A12 N A A22 A23 9 columns N A A23 A24 10 columns N A A24 A25 11 columns N A A25 A23 8 columns A13 N A A23 A24 9 columns N A A24 A25 10 columns N A A25 A26 11 columns N A A26 1 Note N A indicates that although a ColdFire address will be multiplexed during the column phase this does not matter because the number of column lines on the device is satisfied by lower address lines For example if an 8 column SDRAM is used the 8 column lines are satisfied by ColdFire address lines A9 A15 and A17 See the table above Table 3 SDRAM Bank Select Line Connections CF Address Condition SDRAM Bank Select A21 8 columns 11 rows 19 address lines BAO A22 9 columns 11 r
123. ution Centers USA EUROPE Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 Tel 1 800 441 2447 or 1 303 675 2140 World Wide Web Address http lddc nmd com JAPAN Nippon Motorola Ltd SPD Strategic Planning Office 4 32 1 Nishi Gotanda Shinagawa ku Tokyo 141 Japan Tel 81 3 5487 8488 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po New Territories Hong Kong Mfax RMFAX0 email sps mot com TOUCHTONE 1 602 244 6609 US amp Canada ONLY 800 774 1848 World Wide Web Address http sps motorola com mfax INTERNET http motorola com sps Technical Information Motorola Inc SPS Customer Support Center 1 800 521 6274 electronic mail address crc wmkmail sps mot com Document Comments FAX 512 895 2638 Attn RISC Applications Engineering World Wide Web Addresses http www motorola com PowerPC http www motorola com netcomm http www motorola com HPESD M MOTOROLA 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc APPENDIX FEVALUATION BOARD BOM MCF5307EVM_BOM O a Tm 3 O E Q o E O Y Q Q ibs ra 1 For More information On This Product Go to www freescale com Freescale Semiconductor Inc C67 CCO C710 C79 C80 C31 C82 CO3 COA C85 C86 CST 86 C 91 09 UNE LOW
124. z 2 1 Nez NC2 CLK 0 1 e lt XKPSTOLK X H nci 3 X New NC1 CLK 0 2 pg bse BLOB CLK_0_1 101 PST3 LX CLK 02 o2 PP1 R_RASO SOO 1071 10 3 PSTO TOUT 102 104 PP4 R_CAS2 DQM2 103 105 PST1 TINA 1074 106 PPO R_RAS1 SO2 1075 107 PST2 BWE 1076 108 PPS R_CASO DQMO 1077 109 PP6 BWE2 108 10_10 PP2 R_CAS1 DQM1 1079 10711 PP5 BWES IO 10 1012 PP7 R_CAS3 DQM3 10711 10713 MTMODO BWEO 10712 10714 DDATA3 gt R SRAS 1o 13 10715 MTMOD1 14 SX 1014 1016 DDATA2 S Ray R DRAMW lO 15 10 17 RXD2 10716 47 X 1016 1018 DDATA1 1017 RR SCAS 10 17 10719 RTS2 10718 15 lO 18 10 20 DDATAO 10 19 Ry lt A sckE 10 19 10721 RXD1 10720 GX 10_20 10_22 MTMOD3 IO 21 Ly TINO 1o 21 Io 23 MTMOD2 10 22 1X 10722 10 24 RTS1 10_23 34 TOuTO 10723 10725 SCLK TRST 10724 HX lO 24 10726 CTS1 10725 35 PLLTPA 1o 25 10727 DSDI TDI 10 26 47 X lO 26 39 lO 28 CTS2 10 27 22 XK EDGESEL 10727 30 61 10 29 TCK a 10 28 1g X 39 10_28 41 92 IO 30 DSDO TDO 20 G1 10 29 21 7 KSCL 20 81 G 10 29 41163 103 BKPT TMS Haz 10 305 47 62 G2 1030 o4 1032 HIZ 42 63 10 31 5 SDA 47 G3 G3 IO 31 G5 43 G4 lO 32 x 43 G4 G4 lO 32 G5 G5 G5 Mictor Connector AMP 767054 1 EE p Mictor_Connector AMP 767054 1 Mictor_Connector AMP 767054 1 Mictor_Connector AMP 767054 1 M C39 C50 C51 C52 1500 PF 1500 PF 1500 PF 1500 PF C67 C22 C23 C40 C41 C69 C70 C88 C87 C84 itle 1500

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