ART2543 User`s Manual
Contents
1. A4 A5 A6 A7 A8 A9 AIO All A4 A5 A6 A7 A8 A9 AIO All ON 220H _ mm 230H ADDR A4 A5 A6 A7 A8 A9 AIO All A4 A5 A6 A7 A8 A9 AIO All 250H A4 A5 A6 A7 A8 A9 AIO All A4 A5 A6 A7 A8 A9 AIO All 2710H A4 A5 A6 A7 A8 A9 AIO All A4 A5 A6 A7 A8 A9 AIO All 290H A4 A5 A6 A7 A8 A9 AIO All A4 A5 A6 A7 A8 A9 AIO All 2BOH ON ADDR ART2542 Counter Card ON A4 A5 A6 A7 A8 A9 A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 A8 A9 AIO All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A9 V6 0 15 A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A92. A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A9 A10 All A4 A5 A6 A7 AS A9 A10 All ART2542 Counter Card V6 0 15 Chapter 3 Signal Connectors 3 1 The Definition of Signal Input and Output Connectors 30 pin CNI definition 5V 5V OUTO CLKO GATEO OUTI CLKI GATEI OUT2 CLK2 GATE2 OUT3 CLK3 GATE3 OUT4 CLK4 GATE4 OUT5 CLK5 GATES OUT6 CLK6 GATE6 OUT7 CLK7 GATE7 DGND DGND DGND DGND Pin definition CLKO 7 Timer Counter clock source input the reference ground use O GND GATEO 1 5V DGND Output GND Output 45V power Digital ground Timer Counter gate input the reference ground use O GND OUTO 8 Timer Counter output the reference ground use O GND ART2542 Counter Card V6 0 15 3 2 Timer Counter Signal Connection Yel GATE A CLK T 1 OUT 2 DGND ART2542 Counter Card V6 0 15 Chapter 4 Timer Counter Function In the counter mode we can use CNTPara CNTMode to set Up or Down count When CNTPara CNTMode O it is subtraction do subtract 1 operation until the count value becomes 0 when CNTPara CNTMode 1 it is addition do add 1 operation until the counter value becomes 4294967295 OO 4 1 Subtraction Counter Mode 0 Interrupt on terminal count Under this mode when given the initial value if GATE is high level the counter im
3. Lowest bit 0 read IO channel ready to enable output output 0x001c Low 3 bit interrupt control Read interrupt control Lowest bit 0 interrupt request Lowest bit 0 interrupt request 16 ART2542 Counter Card V6 0 15 0x0024 0x0025 0x0026 0x0027 0x0028 Higher bit 1 DMA interrupt request Highest bit 2 IO channel ready Lowest bit 0 The first channel function selection 0 timer count 1 frequency measurement Lowest bit 0 The first channel clear signal 0 clear 1 normal count Lowest bit 0 is effective the first channel test frequency pulse width setting a period of high level that time 1s Lowest bit 0 is effective the second channel test frequency pulse width setting a period of high level that time Is Lowest bit 0 is effective the third channel test frequency pulse width setting a period of high level that time 1s Lowest bit 0 is effective the fourth channel test frequency pulse width setting a period of high level that time Is Lowest bit 0 is effective the fifth channel test frequency pulse width setting a period of high level that time 1s Lowest bit 0 is effective the sixth channel test frequency pulse width setting a period of high level that time 1s Lowest bit 0 is effective the seventh channel test frequency pulse width setting a period of high level that time Is Lowest bit 0 is effective the eighth channel test frequency pulse
4. 1 enables counting GATE 0 disables counting the count is permitted Time diagram is shown in figure 10 Mode 3 ek LLL LLL ni fe f WR n h 4 n l 5 IMS oe NET Mo M 3 OMe M 1 Mo OMe MET M OME OUT GATE id 4 il 3 il 4 NET M id 4 MES fil 2 M 1 MO OMe M a OUT n M 5 Figure 10 Mode 4 Software triggered strobe Under this mode the counter is given the initial count value n and begins to count the output OUT becomes high level When the count value becomes M it immediately outputs a negative pulse which is equal to the width of one clock cycle If given a new count value when counting it will be effective immediately GATE 1 enables counting GATE 0 disables counting Time diagram is shown in figure 11 Mode 4 l 4 il 3 Ml 2 M 1T M Figure 11 Mode 5 Hardware triggered strobe Under this mode when the signal of GATE is on the rising edge the counter starts to count so it is called hardware trigger the output OUT has remained high level When the count value becomes M it outputs a negative pulse which is equal to the width of one clock cycle And then the rising edge of GATE signal can re trigger the counter starts to count from the initial count value again in the count period the output has remained high level When the count addition of the counter has not yet reached M but it is given a new value nl Only when it is the rising edge of GATE the counter starts to count from n1 Time diagram is shown in figu
5. width setting a period of high level that time Is Lowest bit OJ The second channel clear signal 0 clear 1 normal count Lowest bit 0 The third channel clear signal Higher bit 1 DMA interrupt request Highest bit 2 IO channel ready Lowest bit 0 is valid the end flag signal of the first channel frequency measurement Q the end of frequency measurement doing frequency measurement counting Lowest bit 0 is valid the end flag signal of the second channel frequency measurement Q the end of frequency measurement doing frequency measurement counting Lowest bit 0 is valid the end flag signal of the third channel frequency measurement Q the end of frequency measurement doing frequency measurement counting Lowest bit 0 is valid the end flag signal of the fourth channel frequency measurement Q the end of frequency measurement doing frequency measurement counting Lowest bit 0 is valid the end flag signal of the fifth channel frequency measurement Q the end of frequency measurement doing frequency measurement counting Lowest bit 0 is valid the end flag signal of the sixth channel frequency measurement Q the end of frequency measurement doing frequency measurement counting Lowest bit 0 is valid the end flag signal of the seventh channel frequency measurement Q the end of frequency measurement doing frequency measurement counting Lowest bit 0 i
6. 4 Customers are responsible for shipping costs to transport damaged products to our company or sales office 5 To ensure the speed and quality of product repair please download an RMA application form from our company website BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 20 ART2542 Counter Card V6 0 15 Products Rapid Installation and Self check Rapid Installation Product driven procedure is the operating system adaptive installation mode After inserting the disc you can select the appropriate board type on the pop up interface click the button driver installation or select CD ROM drive in Resource Explorer locate the product catalog and enter into the APP folder and implement Setup exe file After the installation pop up CD ROM shut off your computer insert the PCI card If it is a USB product it can be directly inserted into the device When the system prompts that it finds a new hardware you do not specify a drive path the operating system can automatically look up it from the system directory and then you can complete the installation Self check At this moment there should be installation information of the installed device in the Device Manager when the device does not work you can check this item Open Start gt Programs gt ART Demonstration Monitoring and Control System gt Corresponding Board gt Advanced Testing Presentation System the program is a standard testing proce
7. ART To understand your rights and enjoy all the after sales services we offer please read the following carefully 1 Before using ART s products please read the user manual and follow the instructions exactly When sending in damaged products for repair please attach an RMA application form which can be downloaded from www art control com 2 All ART products come with a limited two year warranty gt The warranty period starts on the day the product is shipped from ART s factory gt For products containing storage devices hard drives flash cards etc please back up your data before sending them for repair ART is not responsible for any loss of data gt Please ensure the use of properly licensed software with our systems ART does not condone the use of pirated software and will not service systems using such software ART will not be held legally responsible for products shipped with unlicensed software installed by the user 3 Our repair service is not covered by ART s guarantee in the following situations Damage caused by not following instructions in the User s Manual Damage caused by carelessness on the user s part during product transportation Damage caused by unsuitable storage environments 1 e high temperatures high humidity or volatile chemicals VV V V Damage from improper repair by unauthorized ART technicians gt Products with altered and or damaged serial numbers are not entitled to our service
8. ART2543 User s Manual g Beijing ART Technology Development Co Ltd ART2542 Counter Card V6 0 15 Contents CGI A EI E E E ashi dete det ce A he bated eared tie cee bre tae E E A 2 CIC TOV CIV EIT l a 3 Chapter 2 Components Layout Diagram and a Brief Description ss ss ssssssnnnnnnznnennnnnnzzznnnnnnnznnzzznnaranenznnzzzanrnnannnnnzzana 4 2 1 The Main Component Layout Diagram EEA EEA EA AAAEEEKENAEKAAAEEEAAEEEE NEE ZEZENENEn En E EE Ent 4 2 2 The Function Description for the Main Component sess eeeennnnnnnnnnznnnszznnannnnznnnznnnnznnnnnnnnzznanannnnanannanznnznnznzznz 4 2 2 1 Signal Input and Output Connectors ccccccccceeecccceceeceeeeeeaaseesessseeeeeeeeeeeeeeeeeeaaeaeaeeeeeeeseeseeeeeeeeeeeaagaeegensnes 4 222 Board Basc Address SIEGHA taa ea ta a i A DI RRE 5 Chap er S Sonal CONNEC OTS sisa a N RSEN 7 3 1 The Definition of Signal Input and Output Connectors 0 0 cccccsssssssessseeeeececeeeeeeeeeeaaeaseesseessseeeeeeeeeeeeeeeeeaaaas l 3 2 Timer Counter Sigral Connection as cisacotssnaseniaamamnniasneisaeacdealelacaueaisnantoalsbunnassiseunduadaandenshanvniasiavutinedaexadeaiicnenceanewendussdeal 8 Chapier 4 Timer Counter TI OM esi sis us Sete ces wb ce tg atti nook dite ceeds e tA al g ti 9 4 l GSubtraction 2 LING ta a E sede 9 A PO OMIM ae ia ija sony cedeuasecedecanaieecasecadecasecesecasecadecanyieie e1eueie arya E 12 4 3 Frequency Measurement Function ccsssssssssseeccceceee
9. dure Based on the specification of Pin definition connect the signal acquisition data and test whether AD is normal or not Connect the input pins to the corresponding output pins and use the testing procedure to test whether the switch is normal or not Delete Wrong Installation When you select the wrong drive or viruses lead to driver error you can carry out the following operations In Resource Explorer open CD ROM drive run Others gt SUPPORT gt PCI bat procedures and delete the hardware information that relevant to our boards and then carry out the process of section I all over again we can complete the new installation BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 21
10. e shot The mode can work under the role of GATE After given the initial count value n OUT becomes high level the counter begins to count until the appearance of the rising edge of GATE at this moment OUT turns into low level when the count ends and the count value becomes M OUT becomes high level that is the output one shot pulse width is determined by the M and initial count value n M n If the current operation does not end and another rising edge of BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 12 ART2542 Counter Card V6 0 15 GATE appears then the current count stops the counter begins to count from n once again and then the output one shot pulse will be widened When the count reduction of the counter has not yet reached M but it is given a new value nl Only when it is the rising edge of GATE the counter starts to count from nl Time diagram is shown in Figure 8 Mode 1 WR n M 4 l GATE a a il 4 M a M 2 fid 1 M OUT imma a GATE il 4 MES M2 M4 Meo Ml 2 MET M OUT n 4 E Figure 8 Mode 2 Rate Generator Under this mode the counter is given the initial count value n and begins to count from n 1 OUT becomes high level When the count value becomes M OUT turns into low level After a CLK cycle OUT resumes high level and the counter automatically load the initial valuen and begin to count from n 1 Thus the output will continue to output a negative pulse its width
11. eeeeeeaeeseeeeseseeeeeeeeeeeeeeeeeeeeaaeaseeeseseeeeeeeeseeeeaaaaeaesaeeseseeeeees 15 Chapter 5 Address Allocation Table ss ss ssssennnnnnznnnnn nanna aa aa EEE E EEE A AAAS AAA LEEEEEEEE EEE EEE EE AEAA AAAS EEEEEEEEEEEEE HEHE 16 Chapter 6 Notes Calibration ANd Warranty PolicV ss eeeennnnnnnnnn rna n nata A nn a EFA EEA EA AAKAEEEEAAAAEEnnnnEEEEEEZZZZEZZZZZAE ETA 20 G 8 EEEE EIEEE E ETETE EETA TEETE EETA T TEET ETETE ATEEN ETAT TETTETETT 20 62 War A ONG E E ES A AEA EAA ada A A A A A S ET E A E ETTA 20 Products Rapid Installation and Self check ikabbar dat kd ra e a Beata Klara 21 Rapid Installation sascccsscssacctnnsiaeadvesseravaraiaceanctanessiaesaeasvadaasssaansacaraenbecasiessaeaaivadenaaneiiaeadisecennadesnanatatancataanbaendesteacesaeatanare 21 MELE CHECK E E A ET AS E A A A E E E A A A AE 21 Delete Wrong Installation cc cccccccccsssssssesesseseseeeeeeeeeeeeeeeeeeeeeeeeeesseeeeeeeeeeeeeeeeeeaaaeeeeeesseeeeeeeeeeeeeeeseaaaaaeeeesseeseeeeeeess 21 BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 2 ART2542 Counter Card V6 0 15 Chapter I Overview ART2543 is a Counter card based on PC104 bus It can be directly connected with PC104 interface of computer to constitute the laboratory product quality testing center and systems for different areas of data acquisition waveform analysis and processing It may also constitute the monitoring system for industrial production process Unpacking Check
12. er count 1 frequency measurement Lowest bit 0 the eighth channel function selection 0 timer count 1 frequency measurement The third channel frequency measurement standard counting value low 16 bit The third channel frequency measurement standard counting value high 16 bit The fourth channel frequency measurement standard counting value low 16 bit The fourth channel frequency measurement standard counting value high 16 bit The fifth channel frequency measurement standard counting value low 16 bit The fifth channel frequency measurement standard counting value high 16 bit The sixth channel frequency measurement standard counting value low 16 bit The sixth channel frequency measurement standard counting value high 16 bit The seventh channel frequency measurement standard counting value low 16 bit The seventh channel frequency measurement standard counting value high 16 bit The eighth channel frequency measurement standard counting value low 16 bit The eighth channel frequency measurement standard counting value high 16 bit The first channel frequency measurement the The first channel frequency measurement the The second channel frequency measurement the The second channel frequency measurement the 18 ART2542 Counter Card V6 0 15 Ox0039 The third channel frequencv measurement the measured frequency counting value low 16 bit Ox003a The third channel freq
13. is equal to one clock cycle the clock number between the two negative pulses is equal to the difference of the M and initial value that is given to the counter M n GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT If change the initial count when counting it will be effective next time Time diagram is shown in figure 9 Mode 2 WR n M 4 l n M 2 fl 4 Ml fil 1 M Wes fil 2 Ml 1 Ml l 1 Ml l 1 OUT GATE H GATE fT 4 tS il 3 il 2 M 1 Mo M d il 3 fil 2 il 1 M OUT n M 4 i L I Figure 9 Mode 3 Square wave mode Similar to Mode 2 the counter is given the initial count value n and begins to count from n 1 When the signal of GATE is high level it starts to count timer counter begins to count by addition 1 each time after finish the first half count the output OUT has remained high level when do the post half count the output OUT becomes low leve If the initial count value n is an even number the output is 1 1 square wave if the initial count value n is an odd number the output OUT has remained high level during the previous M n 1 2 count period but the output OUT becomes low level BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 13 ART2542 Counter Card V6 0 15 during the post M n 1 2 count period that is the high level has one clock cycle more than the low level If change the initial count when counting it will be effective next time GATE
14. list Check the shipping carton for any damage If the shipping carton and contents are damaged notify the local dealer or sales for a replacement Retain the shipping carton and packing material for inspection by the dealer Check for the following items in the package If there are any missing items contact your local dealer or sales gt ART2543 Data Acquisition Board gt ART Disk a user s manual pdf b drive c catalog gt Warranty Card Counter Timer Function 32 bit counter timer 8 independent counters can be set to Up or Down Counter by the software Count Mode 6 modes Electrical Standards TTL level Gate GATEn rising edge high level low level Counter Output OUTn high level low level Operating Temperature Range 0 C 55 C VV VV VV V Storage Temperature Range 20 C 70 C Frequency Measurement Function gt Frequency Measurement Channels 8 channel software selectable gt Frequency Measurement Signal 0 5V TTL level gt Frequency Measurement Type counting gt Frequency Measurement Range 1Hz 10MHz gt Frequency Measurement Accuracy 1Hz Other Features Board Base Address 300H Dimension 90 3mm L 96mm W 16mm H ART2542 Counter Card V6 0 15 Chapter 2 Components Layout Diagram and a Brief Description 2 1 The Main Component Layout Diagram BHR RRR HRS Bial B A 5 me eo 0 9 it ID LI
15. m englishs or CALL 86 0 10 51289836 CN 9 ART2542 Counter Card V6 0 15 Mode 1 Figure 2 Mode 2 Rate Generator Under this mode the counter is given the initial count value N and begins to count from N 1 OUT becomes high level When the count value becomes 0 OUT turns into low level After a CLK cycle OUT resumes high level and the counter automatically load the initial value N and begin to count from N 1 Thus the output will continue to output a negative pulse its width is equal to one clock cycle the clock number between the two negative pulses is equal to the initial value that is given to the counter GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT If change the initial count when counting it will be effective next time Time diagram is shown in figure 3 Mode 2 OUT n 4 Figure 3 Mode 3 Square wave mode Similar to Mode 2 the counter is given the initial count value N and begins to count from N 1 When the signal of GATE is high level it starts to count timer counter begins to count by subtracting 1 each time more than half the initial count value The output OUT has remained high level when the count value is more than half of the initial count value but the output OUT becomes low level when the count value is less than half of the initial value If the initial count value N is an even number the output is 1 1 square wave if the initial count value N is an odd n
16. mediately begins to count by subtracting 1 each time the counter output OUT turns into low level when the count ends and the count value becomes 0 the counter output OUT becomes and keeps high level until given the initial value or reset If a counter which is counting is given a new value the counter will begin to count from the new value by subtracting 1 each time GATE can be used to control the count GATE 1 enables counting GATE 0 disables counting OUT signal changes high from low can be used as interrupt request Time diagram is shown in Figure 1 Mode 0 Figure 1 Mode 1 Hardware retriggerable one shot The mode can work under the role of GATE After given the initial count value N OUT becomes high level the counter begins to count until the appearance of the rising edge of GATE at this moment OUT turns into low level when the count ends and the count value becomes 0 OUT becomes high level that is the output one shot pulse width is determined by the initial count value N If the current operation does not end and another rising edge of GATE appears then the current count stops the counter begins to count from N once again and then the output one shot pulse will be widened When the count reduction of the counter has not yet reached zero but it is given a new value NI Only when it is the rising edge of GATE the counter starts to count from N1 Time diagram is shown in Figure 2 BUY ONLINE at art control co
17. nt value again in the count period the output has remained high level When the count reduction of the counter has not yet reached zero but it is given a new value N1 Only when it is the rising edge of GATE the counter starts to count from N1 Time diagram is shown in figure 6 ART2542 Counter Card V6 0 15 Mode 5 Figure 6 4 2 Addition Counter For illustration make M 4294967295 2 1 the maximum count value of the addition If the initial value is 4 294 967 291 is recorded as M 4 if it is 4 294 967 292 is recorded as M 3 and so on Mode 0 Interrupt on terminal count Under this mode when given the initial value n if GATE is high level the counter immediately begins to count by addition 1 each time the counter output OUT turns into low level when the count ends and the count value becomes M the counter output OUT becomes and keeps high level until given the initial value or reset If a counter which is counting is given a new value the counter will begin to count from the new value by addition 1 each time GATE can be used to control the count GATE 1 enables counting GATE 0 disables counting OUT signal changes from low to high can be used as interrupt request Time diagram is shown in Figure 7 Mode 0 UK ILILILILILILILILILILILILIL nema a WR n id d Tu id 4 WES Ml 2 MET M TTT our GATE H WR n fid d NI Mess KAT hl 1 h OUT Figure 7 Mode 1 Hardware retriggerable on
18. re 12 ART2542 Counter Card V6 0 15 Mode 5 ME NN GATE OUT nEmA l id 4 Mes Me MELT OM id 4 M a il 4 fid 1 fil 4 il fil 4 Id 1 Ml Figure 12 4 3 Frequencv Measurement Function When the unknown frequency signal is a digital high frequency signal we can use of frequency measurement counting In this mode first set the timing tO of the counter hardware test count the number n in t0 then we can calculate the frequency signal cycle to get the signal frequency see figure below Time tO the number of pulses n Frequency Measurement Function As shown above the frequency of the signal is 1 tO n ART2542 Counter Card V6 0 15 Chapter 5 Address Allocation Table ART2543 register address allocation table Base address 0x0 Base address 40x2 write data Base address 40x2 read data write control address Ox0018 Low 8 bit counter UP and Down control Read counter UP and Down control signal Lowest bit 0 counter O addition and Lowest bit 0 counter 0 addition and subtraction control subtraction control Highest bit 7 counter 7 addition and Highest bit 7 counter 7 addition and subtraction control subtraction control Ox0019 Lowest bit 0 I O device interrupt enable Lowest bit 0 read I O device interrupt enable 0x00la Lowest bit 0 I O device DMA enable Lowest bit 0 read I O device DMA enable interrupt request interrupt request 0x001b Lowest bit 0 IO channel ready to enable
19. s valid the end flag signal of the eighth channel frequency measurement Q the end of frequency measurement doing frequency measurement counting The first channel frequency measurement standard counting value low 16 bit The first channel frequency measurement standard counting value high 16 bit The second channel frequency measurement standard counting value low 16 bit The second channel frequency measurement standard counting value high 16 bit 17 ART2542 Counter Card V6 0 15 Ox0029 Ox0034 Lowest bit 0 The fourth channel clear signal 0 clear 1 normal count Lowest bit 0 The fifth channel clear signal 0 clear 1 normal count Lowest bit 0 The sixth channel clear signal 0 clear 1 normal count Lowest bit 0 The seventh channel clear signal 0 clear 1 normal count Lowest bit 0 The eighth channel clear signal 0 clear 1 normal count Lowest bit OI The second channel function selection 0 timer count 1 frequency measurement Lowest bit 0 The third channel function selection 0 timer count 1 frequency measurement Lowest bit 0 the fourth channel function selection 0 timer count 1 frequency measurement Lowest bit 0 the fifth channel function selection 0 timer count 1 frequency measurement Lowest bit 0 the sixth channel function selection 0 timer count 1 frequency measurement Lowest bit 0 the seventh channel function selection 0 tim
20. u RIEAN i CNI 12 SN lfe mma i kar bee 1 lu LILI Vi Mt Te IMI HHH if ii Jih s HANAN a ARN EE LEJE fa HPHH ef E 18 ADDRI TE 6 te a ga Hinila i i IM Wate m n b w ra ba E T wee Li eB sonk BGGRPEF ot TR HE ippi j k jitddki Tt il ETON 2 a 83 2 2 The Function Description for the Main Component 2 2 1 Signal Input and Output Connectors CNI signal input output connector BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 4 ART2542 Counter Card V6 0 15 2 2 2 Board Base Address Selection ADDRI board base address DIP switches Board base address can be set to binary code which from 200H to 3EOH be divided by 16 board base address defaults 300H will occupy the base address of the date of 20consecutive I O addresses Switch No 1 2 3 4 5 6 7 correspond to address bits A4 A5 A6 A7 A8 A9 A10 A11 A10 A11 are reserved Board base address selection is as follows when the ADDRI switches dial to ON that means high virtual value is 1 the switch to the other side means the low virtual is 0 Board base address selection switch ADDR Ishown as following For example the default base addresses is300H shown as the following A4 A5 A6 A7 A8 A9 AIO All ON 1 2 3 4 5 6 9 8 ON Common base address A4 A5 A6 A7 A8 A9 AIO All
21. uency measurement the Ox003b The fourth channel frequency measurement the Ox003c The fourth channel frequency measurement the Ox003d The fifth channel frequency measurement the measured frequency counting value low 16 bit Ox003e The fifth channel frequency measurement the measured frequency counting value high 16 bit Ox003f The sixth channel frequency measurement the 0x0040 The sixth channel frequency measurement the Ox0041 The seventh channel frequency measurement the measured frequency counting value low 16 bit Ox0042 The seventh channel frequency measurement the measured frequency counting value high 16 bit 0x0043 The eighth channel frequency measurement the Ox0044 The eighth channel frequency measurement the BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 19 ART2542 Counter Card V6 0 15 Chapter 6 Notes Calibration and Warranty Policy 6 1 Notes In our products packing user can find a user manual ART2543 module and a quality guarantee card Users must keep quality guarantee card carefully if the products have some problems and need repairing please send products together with quality guarantee card to ART we will provide good after sale service and solve the problem as quickly as we can When using ART2543 in order to prevent the IC chip from electrostatic harm please do not touch IC chip in the front panel of ART2543module 6 2 Warranty Policy Thank you for choosing
22. umber the output OUT has remained high level during the previous n 1 2 count period but the output OUT becomes low level during the post n 1 2 count period that is the high level has one clock cycle more than the low level If change the initial BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 10 ART2542 Counter Card V6 0 15 count when counting it will be effective next time When GATE 0 the count is prohibited when GATE 1 the count is permitted Time diagram is shown in figure 4 Mode 3 Figure 4 Mode 4 Software triggered strobe Under this mode the counter is given the initial count value N and begins to count the output OUT becomes high level When the count value becomes 0 it immediately outputs a negative pulse which is equal to the width of one clock cycle If given a new count value when counting it will be effective immediately GATE 1 enables counting GATE 0 disables counting Time diagram is shown in figure 5 Mode 4 GATE H GATE A l QUT Figure 5 Mode 5 Hardware triggered strobe Under this mode when the signal of GATE is on the rising edge the counter starts to count so it is called hardware trigger the output OUT has remained high level When the count value becomes 0 it outputs a negative pulse which is equal to the width of one clock cycle And then the rising edge of GATE signal can re trigger the counter starts to count from the initial cou
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