1 Product Description
Contents
1. Bit Name Description 15 MSB Read 14 E Always 0 13 5 Write 12 No effect should be written with O s 11 10 9 amp 8 7 INT1_EN O IP A interrupt 1 disabled 1 IP A interrupt 1 enabled 6 INTO EN O IP A interrupt O disabled 1 IP A interrupt 0 enabled 5 INT1 SENSE 0 IP A interrupt 1 level sensitive 1 IP A interrupt 1 edge sensitive 4 INTO SENSE 0 interrupt 0 level sensitive 1 IP A interrupt 0 edge sensitive 3 ERR INT EN 0 error interrupt disabled 1 IP A error interrupt enabled 2 TIME INT EN 0 IP A timeout interrupt disabled 1 IP A timeout interrupt enabled 1 RECOVER 0 IP A recover time disabled 1 IP A recover time enabled O LSB CLKRATE 0 IP A clock rate 8 MHz 1 IP A clock rate 32 MHz Figure 4 7 IP A Control Register PCI Base Address 2 0x02 TPCI200 User Manual Issue 1 4 TEWS S TECHNOLOGIES Page 25 of 36 TEWS S TECHNOLOGIES Bit Name Description 15 MSB Read 14 E Always 0 13 Write No effect should be written with O s 10 9 8 2 7 INT1_EN IP B interrupt 1 disabled IP B interrupt 1 enabled IP B interrupt 0 disabled IP B interrupt 0 enabled 6 INTO EN 5 INT1 SENSE IP B interrupt 1 level sensitive IP B interrupt 1 edge sensitive 4 INTO SENSE IP B interrupt O level sensitive 0 1 0 1 0 1 0 1 IP B interrupt 0 edge sensitive 3 ERR INT EN 0 IP B erro2. Bit Name Description 15 MSB Read 14 E Always 0 13 Write 12 No effect should be written with O s 11 10 9 8 2 7 O IP D interrupt 1 disabled 1 IP D interrupt 1 enabled 6 INTO EN O IP D interrupt 0 disabled 1 IP D interrupt O enabled 5 INT1 SENSE 0 IP D interrupt 1 level sensitive 1 IP D interrupt 1 edge sensitive 4 INTO SENSE 0 IP D interrupt 0 level sensitive 1 IP D interrupt O edge sensitive 3 ERR INT EN 0 IP D error interrupt disabled 1 IP D error interrupt enabled 2 TIME INT EN 0 IP D timeout interrupt disabled 1 IP D timeout interrupt enabled 1 RECOVER O IP D recover time disabled 1 IP D recover time enabled O LSB CLKRATE O IP D clock rate 8 MHz 1 IP D clock rate 32 MHz Figure 4 10 IP D Control Register PCI Base Address 2 0x08 TPCI200 User Manual Issue 1 4 TEWS S TECHNOLOGIES Page 28 of 36 4 2 3 IP Reset Register TEWS S TECHNOLOGIES The IP Reset Register can be used to initiate an IP RESET cycle and to detect when the IP RESET cycle has finished Each IP RESET signal can be asserted separately Writing a 1 to bit 3 2 1 or O of the IP Reset Register initiates that the reset cycle and the corresponding IP RESET signal is asserted After 200 ms the on board logic automatically negates the IP RESET signal and completes the IP Reset cycle The IP Reset Register can be read to verify the IP Reset status At power up or board rese
3. PCI9030 IP Slot B IP Slot C Pin 50 Figure 6 1 1 O Pin Order TPCI200 User Manual Issue 1 4 Page 34 of 36 TEWS S TECHNOLOGIES 7 Indicators 7 1 ACK and Power LEDs For a quick visual inspection the TPCI200 offers 10 LEDs Each IndustryPack has its own ACK LED which is lit for about 200ms whenever an access to the corresponding IP happens Function Label Color Description IP A ACK A green Indicates access to IP A IP B ACK B green Indicates access to IP B IP C ACK C green Indicates access to IP C IP D ACK D green Indicates access to IP D Figure 7 1 IP ACK LED Additionally there are 6 green Power LEDs on the TPCI200 Function Label Color Description IP A 5V 45V A green IP B 5V 45V B green LED on IP power supply ok IP C 5V 45V C green IP D 5V 5V D green 12V common to all IP 12V green LED on 12V power ok 12V common to all IP 12V green LED on 12V power ok Figure 7 2 IP Power LED 7 2 Fuses and Filters All IP slots are fuse protected The fuses used on the TPCI200 are self healing fuses For improved performance the TPCI200 provides RF filtering and decoupling capacitors on all IP power lines TPCI200 User Manual Issue 1 4 Page 35 of 36 TEWS S TECHNOLOGIES 8 Pin Assignment 8 1IP Connectors The table below show
4. 0 00 00 00 00 Timer 0x10 PCI Base Address 0 for Mapped Configuration Registers Y FFFFFF80 0x14 PCI Base Address 1 for Mapped Configuration Registers Y FFFFFF81 0x18 PCI Base Address 2 for Local Address Space 0 Y FFFFFFOO 0x1C PCI Base Address 3 for Local Address Space 1 Y FFFFFCOO 0x20 PCI Base Address 4 for Local Address Space 2 Y 000000 0 24 PCI Base Address 5 for Local Address Space 3 Y FF000000 0x28 Cardbus CIS Pointer N 00000000 0x2C Subsystem ID Subsystem Vendor ID 300A 1498 0 30 PCI Base Address for Local Expansion ROM Y 00000000 0x34 Reserved Next Cap P 000000 40 0x38 Reserved 00000000 0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y 7 0 00 00 01 00 0x40 Power Management Capabilities Next Cap Capability ID N 4801 48 01 Pointer 0x44 Data PMCSR Bridge Power Management Y 00 00 0000 Support Control Status Extensions 0x48 Reserved Control Status Next Cap Capability ID Y 23 16 00 02 4C 06 Pointer 0x4C VPD Address Next_Cap Capability ID Y 31 16 0000 00 03 Pointer 0x50 VPD Data Register Y 00000000 Figure 3 1 PCI Configuration Register Map TPCI200 User Manual Issue 1 4 Page 8 of 36 TEWS S TECHNOLOGIES 3 1 2 PCI Base Address Initialization PCI host bus initialization software determines the required address space by an initialization write access writing a value of all ones 1 to a PCI Base Address Register and then reading back the value of the PCI Base Address Register Th
5. bit is set in the IP Status Register The TPCI200 supports read and write cycles to the IP INT space A read access to the IP INT space initiates an IP interrupt acknowledge cycle A read access with address A120 i e 0 0000 00 0 initiates an interrupt acknowledge cycle for INTOZ a read access with address A1 1 i e 0 0000 00C2 initiates an interrupt acknowledge cycle for IP INT1 The read access returns the interrupt vector This feature is helpful for IP modules that require an interrupt acknowledge cycle to remove their pending interrupt request The TPCI200 allows write cycles to the IP INT space If the IP does not support write access to its INT space no ACK will be generated by the IP and a local timeout will terminate the cycle after a timeout time of 8us and the timeout bit is set in the IP Status Register 4 1 3 Local Space 2 Address Map The PCI9030 local space 2 is used for the IP A D Memory space 16 bit port IP modules with Memory space that uses D7 0 only should be accessed via Local Space 3 See section below for details The PCI base address for local space 2 be obtained from the PCIBAR4 Register at offset 0x20 in the PCI9030 PCI configuration register space PCI Base Address 4 Size Description Start End Byte 0x0000_0000 0x007F_FFFF 8M IP A MEM Space 16 bit 0x0080_0000 OxOOFF_FFFF 8M IP B MEM Space 16 bit 0x0100_0000 0x017F_FFFF 8M IP C MEM Space 16 bit 0x0180
6. 6 TEWS S TECHNOLOGIES 4 3 IP Interrupts All IP interface interrupt sources Timeout Error IP A D INT0 IP A D INT1 are mapped to PCI interrupt INTA For quick interrupt source detection the IP Status Register can be read to determine the IP interrupt source Level sensitive IP interrupts which are most common for IP modules are cleared by either an interrupt acknowledge cycle to the IP or by accessing an Interrupt Status Register on the IP module A read access to the IP INT space initiates an IP interrupt acknowledge cycle A read access with address A1 0 i e 0x0000_00C0 initiates an interrupt acknowledge cycle for IP INT0 a read access with address A1 1 i e 0x0000_00C2 initiates an interrupt acknowledge cycle for IP INT1 The read access returns the interrupt vector This feature is helpful for IP modules that require an interrupt acknowledge cycle to remove their pending interrupt request Timeout interrupts and edge sensitive IP interrupts must be cleared in the IP Status Register IP Error interrupts must be cleared in the corresponding IP Control Register TPC1200 User Manual Issue 1 4 Page 32 of 36 TEWS S TECHNOLOGIES 5 IP Strobe Signal The IP strobe signal is an uncommitted line of the IP logic interface which may be used as an optional input to or output from an IP module It is reserved for a digital strobe or clock signal related to the functionality of the IP Strobe signals of all IP slots are
7. BS Technologies Inc Issue Description Date 1 0 Initial Issue August 2002 1 1 Local Bus Mode changed from Big to Little Endian September 2002 1 2 Block Diagram correction October 2002 1 3 Correction of 9030 EEPROM content November 2002 1 4 Correction Figure PCI to Local Byte lane swapping November 2003 TPCI200 User Manual Issue 1 4 Page 2 of 36 TPCI200 User Manual Issue 1 4 IP INTERFACE 4 1 PCI9030 Local Space Assignment 4 1 1 Local Space 0 Address Map 4 1 2 Local Space 1 Address Map 4 1 3 Local Space 2 Address Map 4 1 4 Local Space Address Map 4 2 IP Interface Register 4 2 1 Revision ID Register 4 2 2 IP Control Register 4 2 3 Reset Register 4 2 4 Status Register 4 3 IP Interrupts IP STROBE SIGNAL INSTALLATION OF INDUSTRYPACKS INDICATORS 7 1 ACK and Power LEDs 7 2 Fuses and Filters PIN ASSIGNMENT 8 1 IP Connectors Table of Contents PRODUCT DESCRIPTION TECHNICAL SPECIFICATION PCI INTERFACE 3 1 PCI Configuration CFG Registers 3 1 1 PCI Header 3 1 2 PCI Base Address Initialization 3 1 2 1 Base Address Implementation 3 1 2 2 Memory Base Address Implementation 3 1 2 3 Expansion ROM Base Address Implementation 3 2 Local Configuration Register 3 3 Target Configuration EEPROM 3 4 Endian Conventions 3 4 1 Intel CPU View 3 4 2 PowerPC CPU View 3 4 8 Intel CPU View w
8. E 1 BYTE 0 Cycle 15 Little Endian 13 BigEndian Figure 3 8 PCI to Local Byte lane swapping The local Endian mode of the PCI9030 can be changed for each local space separately This is done by changing the value of bit 24 in the corresponding Bus Region Descriptor Register To change local Space 0 that provides access to the local Control and Status Registers from Little Endian to Big Endian mode write OxD5 to PCI BARO 0x2B To change local Space 1 that provides access to IP I O ID and INT Space from Little Endian to Big Endian mode write 0x15 to PCI BARO Ox2F To change local Space 2 that provides access to the IP MEM Space 16 bit port from Little Endian to Big Endian mode write 0x15 to PCI BARO 0x33 Changing local Space 3 from Little Endian to Big Endian mode has no effect because this space has only an 8 bit port TPCI200 User Manual Issue 1 4 Page 19 of 36 TEWS S TECHNOLOGIES 4 IP Interface The IP FPGA provides the interface between the PCI9030 local bus and the IP slots The IP FPGA also provides the IP Interface Control Registers A PCI access to the TPCI200 will be terminated in every case If the IP does not generate an ACK a local timeout will terminate the IP access after a timeout time of 8us and the timeout bit is set in the IP Status Register All F s are returned for read cycles The IP FPGA is configured at power up or board reset by an on board serial PROM 4 1 PCI9030 Local Sp
9. I9030 local space 1 is used for the IP A D ID INT and I O space The PCI base address for local space 1 can be obtained from the PCIBAR3 Register at offset Ox1C in the PCI9030 PCI configuration register space PCI Base Address 3 Size Description Start End Byte 0x0000 0000 0x0000 007F 128 IP A I O Space 0x0000_0080 0x0000_00BF 64 IP A ID Space 0x0000 00 0 0x0000_00FF 64 IP A INT Space 0x0000_0100 0x0000_017F 128 IP B I O Space 0x0000_0180 0x0000_01BF 64 IP B ID Space 0x0000_01C0 0x0000_01FF 64 IP B INT Space 0x0000_0200 0x0000_027F 128 IP C I O Space 0x0000 0280 0x0000_02BF 64 IP C ID Space 0x0000_02C0 0x0000_02FF 64 IP C INT Space 0x0000_0300 0x0000_037F 128 IP D I O Space 0x0000 0380 0x0000 OSBF 64 IP D ID Space 0x0000_03C0 0x0000_03FF 64 IP D INT Space Figure 4 3 Local Space 1 Address Map IP A D ID INT I O Space TPCI200 User Manual Issue 1 4 Page 21 of 36 TEWS S TECHNOLOGIES The TPCI200 supports read and write cycles to the IP I O space The TPCI200 supports read and write cycles to the IP ID space A PCI access to the TPCI200 will be terminated in every case If the IP supports write access to its ID space data will be written to the ID PROM If the IP does not support write access to its ID space no ACK will be generated by the IP to the local control logic and a local timeout will terminate the IP write cycle after a timeout time of 8us and the timeout
10. Interrupt status of all IP interrupt lines can read in the IP Status Register If edge sensitive interrupt is enabled see IP Control Register for detail and an interrupt is active writing a 1 to bit 7 0 clears the corresponding interrupt status Bit Name Description 15 MSB TIME D Read 0 IP D timeout has not occurred 1 IP timeout has occurred Write O No effect 1 Clear IP_D timeout status 14 TIME_C Read 0 timeout has not occurred 1 IP_C timeout has occurred Write O No effect 1 Clear IP C timeout status 13 TIME B Read 0 IP B timeout has not occurred 1 IP_B timeout has occurred Write 0 No effect 1 Clear IP_B timeout status 12 TIME_A Read 0 IP A timeout has not occurred 1 IP_A timeout has occurred Write 0 No effect 1 Clear IP_A timeout status 11 ERR_D Read 0 IP_D ERROR signal de asserted 1 IP_D ERROR signal asserted Write 0 No effect 1 No effect 10 ERR C Read 0 C ERROR signal de asserted 1 1 C ERROR signal asserted Write 0 No effect 1 No effect 9 ERR B Read 0 ERROR signal de asserted 1 1 B ERROR signal asserted Write 0 No effect 1 No effect 8 ERR A Read 0 A ERROR signal de asserted 1 ERROR signal asserted TPCI200 User Manual Issue 1 4 Page 30 of 36 Bit Name Description Write 0 No effect 1 No effect INT1_D Read 0 No IP D
11. S 2 0X04 FIGURE 4 9 IP C CONTROL REGISTER PCI BASE ADDRESS 2 0X06 FIGURE 4 10 IP D CONTROL REGISTER PCI BASE ADDRESS 2 0X08 FIGURE 4 11 IP RESET REGISTER PCI BASE ADDRESS 2 0X0A FIGURE 4 12 IP STATUS REGISTER PCI BASE ADDRESS 2 0XO0C FIGURE 5 1 IP STROBE rennen EIGURE 6 1 PIN ORDER et re t t rer eere rd re FIGURE 7 12 IP ACK LED a aai FIGURE 7 24 IP POWERED coincide FIGURE 8 1 IP J1 LOGIC INTERFACE PIN 55 6 TPCI200 User Manual Issue 1 4 TEWS S TECHNOLOGIES Page 4 of 36 TEWS lt TECHNOLOGIES 1 Product Description The TPCI200 is a standard 33 MHz 32 bit PCI Carrier for up to 4 single size or two double size IndustryPack IP modules used to build modular flexible and high density I O solutions for applications in process control medical systems telecommunication and traffic control Four 50 pin 0 1 inch flat ribbon cable connectors provide access to all IP I O lines Status indicators for IP access 5V and 12V are provided The TPCI200 can operate with 3 3V 5 0V PCI I O signaling voltage for I O This guaranties compatibility with nearly all PC mainboards 3 3V required by on board logic is generated locally All IP interrupt request lines ar
12. TEWS 2 The Embedded Company TECHNOLOGIES TPCI200 PCI IP Carrier Version 1 0 User Manual Issue 1 4 November 2003 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 25469 Halstenbek Germany 1 E Liberty Street Sixth Floor Reno Nevada 89504 USA Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19 Phone 1 775 686 6077 Fax 1 775 686 6024 e mail info tews com www tews com e mail usasales tews com www tews com TPCI200 10 PCI Carrier for 4 IndustryPack modules TEWS S TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e IP_RESET Access terms are described as W Write Only R Read Only RW Read Write R C Read Clear R S Read Set 2002 2003 by TEWS TECHNOLOGIES GmbH IndustryPack is a registered trademark of S
13. V Power LED Self healing fuses and RF filtering on all IP power lines 280 mA typical 5V DC 1 mA typical O 12V DC 1 mA typical 12V DC Additional power is required by IP modules 40 C to 85 Storage 40 C to 100 227497 h 165 g no IndustryPack modules inserted 106 68 mm x 270 mm 5 95 non condensing TPCI200 User Manual Issue 1 4 Figure 2 1 Technical Specification Page 6 of 36 TEWS S TECHNOLOGIES 3 PCI Interface The TPCI200 is accessible in the PCI Memory space The PCI9030 PCI Target Chip from PLX Technology is used as PCI target device for accessing the IP interface A FPGA is used on the PCI9030 local bus to build the IP interface and provide IP interface Control Registers The PCI9030 provides four local spaces 0 3 that are used for the IP interface Basic PCI9030 register configuration is loaded from a serial EEPROM after power up or board reset TPCI200 User Manual Issue 1 4 Page 7 of 36 3 1 PCI Configuration CFG Registers 3 1 1 PCI Header TEWS S TECHNOLOGIES PCI CFG Write 0 to all unused Reserved bits PCI Read after Register write initialization wri 31 24 23 16 15 8 7 0 3a 0 00 Device ID Vendor ID 30C8 1498 0 04 Status Command Y 0280 0003 0x08 Class Code Revision ID N 068000 00 0x0C BIST Header Type PCI Latency Cache line Size Y 7
14. _0000 0x01 FF_FFFF 8M IP D MEM Space 16 bit Figure 4 4 Local Space 2 Address Map IP A D Memory Space 16 bit TPCI200 User Manual Issue 1 4 Page 22 of 36 TEWS S TECHNOLOGIES 4 1 4 Local Space 3 Address Map The PCI9030 local space 3 is used for the IP A D Memory space 8 bit port This space allows linear addressing of the IP memory space for IP s with 8 bit port width DO D7 only The PCI base address for local space 3 can be obtained from the PCIBAR5 Register at offset 0x24 in the PCI9030 PCI configuration register space Offset Base PCI Base Address 5 Size Byte Description Start End 0x0000 0000 0x003F_FFFF 4M A MEM Space 8 bit 0x0040_0000 0x007F_FFFF 4M IP B MEM Space 8 bit 0x0080_0000 Ox00BF_FFFF 4M IP C MEM Space 8 bit 0 00 0 0000 OxOOFF FFFF 4M IP D MEM Space 8 bit Figure 4 5 Local Space 3 Address Map IP A D Memory Space 8 bit 4 2 IP Interface Register 4 2 1 Revision ID Register The Revision ID Register shows the revision of the on board IP FPGA logic Initial Value is 0x00 Changes in the on board FPGA logic will be signed by incrementing the register value Bit Name Description 15 MSB 14 Read E Always 0 12 11 Write 10 No Effect 9 8 7 REV_ID 6 5 Read 4 FPGA Logic Revision ID x Write 2 No Effect 1 0 LSB Figure 4 6 Revision ID Register PCI Base Addre
15. accessible on the TPCI200 via a 4 pin jumper field C D Status LEDs N STROBE Local to IP Interface x Figure 5 1 IP Strobe Signal TPCI200 User Manual Issue 1 4 Page 33 of 36 6 Pin 50 Pin 2 TEWS S TECHNOLOGIES Installation of IndustryPacks Before installing an IndustryPack be sure that the power supply for the TPCI200 is turned off The component is an Electrostatic Sensitive Device ESD Use an anti static mat connected to a wristband when handling or installing the components Installing IndustryPacks on the TPCI200 is done by simply snapping them into one of the four IP slots The connectors are keyed so the IndustryPack can only be installed correctly After an IP has been installed it can be secured on the carrier board This is normally necessary only in high vibration or shock environments Screws and spacers are required to fix a single IP on the TPCI200 They can be ordered from TEWS TECHNOLOGIES Part number TIPxxx HK All IP modules mate with 50 pin flat cable receptacle connectors for their The PCB labeling indicates which connector is associated with the according IP slot Pin 1 for each cable is identified by the mark on the connector or a square solder pad Pin 25 Pin26 1 Pin1 ACK A B C D 45V A 2V 12 Pin 2 IP Slot A T IP Slot D
16. ace Assignment The PCI9030 local spaces must be used to access the IP Interface The PCI base address for each local space can be obtained from the PCI9030 PCI configuration register space Space 0 contains the IP Control and Status Register Space 1 provides access to I O ID and INT Space of all IP modules Space 2 is used for the IP A D Memory space Space 3 is also used for IP A D Memory space but provides linear addressing for IP modules that use only D7 0 PCI9030 Size Port Width Endian Mode IP Interface Space Local Space Byte Bit 0 256 16 Little IP Interface Register 1 1K 16 Little IP ID INT I O Space 2 32M 16 Little IP A D MEM Space 16 bit 3 16M 8 Little IP A D MEM Space 8 bit Figure 4 1 PCI9030 Local Space Assignment TPCI200 User Manual Issue 1 4 Page 20 of 36 TEWS S TECHNOLOGIES 4 1 1 Local Space 0 Address Map The PCI9030 local space 0 is used for the IP interface registers The PCI base address for local space 0 can be obtained from the PCIBAR2 Register at offset 0x18 in the PCI9030 PCI configuration register space PCI Base Address 2 Size Byte Register 0x00 2 REVISION ID 0x02 2 IP A CONTROL 0x04 2 IP B CONTROL 0x06 2 IP C CONTROL 0x08 2 IP D CONTROL Ox0A 2 RESET 0x0C 2 STATUS OxOE 2 Reserved 0x10 OxFF 240 Reserved Figure 4 2 Local Space 0 Address Map 4 1 2 Local Space 1 Address The PC
17. dress Local Expansion ROM Register is detected as the first bit set the device is requesting a 64 kilobyte block of memory address space 7 Write the start address of the requested memory address block to the PCI Base Address Local Expansion ROM Register This memory address region must not conflict with any other memory space utilized within the system The Expansion ROM is not used by the TPCI200 For further information please refer to the PCI9030 manual which is also part of the TPCI200 Engineering Documentation TPCI200 User Manual Issue 1 4 Page 11 of 36 3 2 Local Configuration Register After reset the Local Configuration Registers LCRs are loaded from the on board EEPROM The LCRs are accessible the PCI Base Address 0 Memory Mapped or in the PCI Base Address 1 Mapped Configuration Registers TEWS S TECHNOLOGIES Do not change the value of these registers because these values are hardware dependent PCI Offset Register Value Description from Local Base Address 0x00 Local Address Space 0 Range OxOFFFFFOO IP Interface Register 256 byte 0x04 Local Address Space 1 Range OxOFFFFCOO A D ID INT l O Space 1kByte 0x08 Local Address Space 2 Range 0x0E000000 A D MEM Space 16 bit 32Mbyte 0x0C Local Address Space 3 Range 0 0 000000 A D Space 8 bit 16Mbyte 0x10 Local Exp ROM Range 0x00000000 Not used 0
18. e Endian combinations in one system Little Endian CPU with TPCI200 Little Endian and IP module Big Endian Little Endian CPU with TPCI200 Big Endian and IP module Big Endian Big Endian CPU with TPCI200 Big Endian and module Big Endian Big Endian CPU with TPCI200 Little Endian and IP module Big Endian See the next four subchapters for a detailed view on these combinations TPCI200 User Manual Issue 1 4 Page 14 of 36 3 4 1 Intel CPU View During byte access byte lanes are swapped Correct 16 Bit access During 32 Bit access word lanes are swapped TPCI200 User Manual Issue 1 4 Expected by Intel CPU TPCI200 IPAC x lt 1 0 4 x x l x 7 P lt x P x P 20 20 28 20 lt 216 224 216 20 28 224 J 28 EE 20 Little Endian Little Endian Big Endian Figure 3 4 Intel CPU View TEWS S TECHNOLOGIES Higher Address 16 Bit Object 32 Bit Object Page 15 of 36 3 4 2 PowerPC CPU View Expected by PowerPC CPU TPCI200 IPAC 6 1 x During byte access byte lanes I lt X I are swapped P x P 204 2 28 During 16 Bit access byte lanes are swapped 20 4 28 20 1 t t i tH During 32 Bit 216 224 216 access byte lanes are swapped 28 A 20 28 4 20 25 20 Big Endia
19. e PCI9030 PCI Target chip returns zero 0 in don t care address bits specifying the required address space The PCI software then maps the local address space into the PCI address space by programming the PCI Base Address Register After programming the required address spaces the user must set bit O enables l O accesses and bit 1 enables memory accesses of the Command Register Offset 0x04 to 1 TPCI200 User Manual Issue 1 4 Page 9 of 36 TEWS S TECHNOLOGIES 3 1 2 1 I O Base Address Implementation 1 Write a value of 1 to all bits of the PCI Base Address Registers 0 to 5 2 Check that bit O of the register contains a value of 1 PCI9030 needs an I O address space 3 Starting at bit location 2 of the PCI Base Address Register search for the first bit set to a value of 1 This bit is the binary size of the total contiguous block of I O address space needed by the PCI9030 For example if bit 5 of the PCI Base Address Register is detected as the first bit set to 1 the PCI9030 is requesting a 32 byte block of I O address space 4 Write the start address of the requested l O address space to the PCI Base Address Register The PCI Base Address 1 for Mapped Configuration Registers 128 byte is used by the TPCI200 as address space 3 1 2 2 Memory Base Address Implementation 1 Write a value of 1 to all bits of the PCI Base Address Registers 0 to 5 2 Check that bit O of the r
20. e mapped to PCI INTA For fast interrupt source detection the TPCI200 provides a special IP Interrupt Status Register IP clock is selectable between 8 MHz and 32 MHz for each IP separately Two memory spaces are provided for each IP allowing linear addressing for either 16 bit or 8 bit memory on the IP The IP power lines are fuse protected by self healing fuses and RF filtered The operating temperature range is 40 C to 85 Status LEDs EX Local to IP Interface IP Slot C IP Slot B Figure 1 1 Block Diagram TPCI200 TPCI200 User Manual Issue 1 4 Page 5 of 36 TEWS S TECHNOLOGIES 2 Technical Specification PCI Card Interface PCI I O Signaling Voltage IP Interface IP Slots IP Access Mapping of IP Interrupts l O Access DMA 32 Bit Access Status LEDs Protection Power Requirements without IP Modules Temperature Range MTBF Weight Size Humidity PCI 2 2 compliant interface 3 3V or 5 0V According to IndustryPack specification ANSI VITA 4 1995 Four single size or two double size with I O 8 16 bit 8 32 MHz selectable per IP 8 Mbyte memory space per IP All IP interrupts are mapped to PCI INTA local interrupt Status Register 50 pin 0 1 inch flat ribbon cable connector per IP Not supported Not supported ACK LED for each IP slot 5V Power LED for each IP slot 12V and 12
21. egister contains a value of 0 PCI9030 needs a memory address space 3 Starting at bit location 4 of the PCI Base Address Register search for the first bit set to a value of 1 This bit is the binary size of the total contiguous block of memory address space needed by the PCI9030 For example if bit 15 of the PCI Base Address Register is detected as the first bit set to 1 the PCI9030 is requesting a 32 kilobyte block of memory address space 4 Write the start address of the of the requested memory address block to the PCI Base Address Register This memory address region must not conflict with any other memory space utilized within the system In addition it must comply with the definition contained in bits 1 and 2 of this register The PCI Base Address 0 for Memory Mapped Configuration Registers 128 byte and the PCI Base Addresses 2 to 5 for Local Address Space 0 to 4 are used by the TPCI200 as memory address space TPCI200 User Manual Issue 1 4 Page 10 of 36 TEWS S TECHNOLOGIES 3 1 2 3 Expansion ROM Base Address Implementation 5 Write a value of 1 to bits 11 through 31 of PCI Base Address Local Expansion ROM Register 6 Starting at bit location 11 of the PCI Base Address Local Expansion ROM Register search upward for the first bit set to a value of 1 This bit is the binary size of the total contiguous block of memory address space needed by the PCI9030 For example if bit 16 of the PCI Base Ad
22. interrupt 1 request 1 Active IP D interrupt 1 request Write O No effect 1 Clear edge sensitive D interrupt 1 status INTO D Read 0 No IP D interrupt O request 1 Active IP D interrupt 0 request Write O No effect 1 Clear edge sensitive D interrupt 0 status C Read 0 No IP C interrupt 1 request 1 Active IP C interrupt 1 request Write O No effect 1 Clear edge sensitive C interrupt 1 status INTO C Read 0 No IP C interrupt 0 request 1 Active IP C interrupt O request Write O No effect 1 Clear edge sensitive interrupt 0 status INT1_B Read 0 No IP B interrupt 1 request 1 Active B interrupt 1 request Write O No effect 1 Clear edge sensitive B interrupt 1 status INTO B Read 0 No IP B interrupt O request 1 Active B interrupt 0 request Write O No effect 1 Clear edge sensitive interrupt 0 status A Read 0 No IP A interrupt 1 request 1 Active IP A interrupt 1 request Write O No effect 1 Clear edge sensitive interrupt 1 status 0 LSB INTO_A Read 0 No IP A interrupt O request 1 Active IP A interrupt 0 request Write O No effect 1 Clear edge sensitive interrupt 0 status Figure 4 12 IP Status Register PCI Base Address 2 0 0 TPCI200 User Manual Issue 1 4 TEWS S TECHNOLOGIES Page 31 of 3
23. ith TPCI200 switched to Big Endian 3 4 4 PowerPC CPU View with TPCI200 switched to Big Endian 3 5 Big Little Endian Mode setting TEWS S TECHNOLOGIES Page 3 of 36 Table of Figures FIGURE 1 1 BLOCK DIAGRAM 200 FIGURE 2 1 TECHNICAL nemen FIGURE 3 1 PCI CONFIGURATION REGISTER FIGURE 3 2 LOCAL CONFIGURATION REGISTERS sse FIGURE 3 3 9030 CONFIGURATION EEPROM CONTENT FIGURE 3 4 INTEL CPU VIEW reiten t aedis ine ierat FIGURE 3 5 POWERPC CPU VIEW sese emnes FIGURE 3 6 INTEL CPU VIEW WITH TPCI SWITCHED TO BIG ENDIAN FIGURE 3 7 POWERPC CPU VIEW WITH TPCI200 SWITCHED TO BIG ENDIAN FIGURE 3 8 PCI TO LOCAL BYTE LANE SWAPPING ee FIGURE 4 1 PCI9030 LOCAL SPACE 5 0 FIGURE 4 2 LOCAL SPACE 0 ADDRESS FIGURE 4 3 LOCAL SPACE 1 ADDRESS MAP IP A D ID INT SPACE FIGURE 4 4 LOCAL SPACE 2 ADDRESS MAP IP A D MEMORY SPACE 16 BIT FIGURE 4 5 LOCAL SPACE 3 ADDRESS MAP IP MEMORY SPACE 8 BIT FIGURE 4 6 REVISION ID REGISTER PCI BASE ADDRESS 2 0X00 FIGURE 4 7 IP A CONTROL REGISTER PCI BASE ADDRESS 2 0X02 FIGURE 4 8 IP B CONTROL REGISTER PCI BASE ADDRES
24. n Little Endian Big Endian TPCI200 User Manual Issue 1 4 Figure 3 5 PowerPC CPU View TEWS S TECHNOLOGIES Page 16 of 36 TEWS S TECHNOLOGIES 3 4 3 Intel CPU View with TPCI200 switched to Big Endian Expected by Intel CPU TPCI200 IPAC X x e Xx Byte access can be done with addresses Higher described in the Address IP manual X A x v a P lt 20 4 28 98 During 16 Bit 7 access byte lanes 16 Bit Object are swapped 28 20 20 20 224 4 224 i 4 lt 3 During 32 Bit 28 216 216 access word 32 Bit Object and byte lanes are swapped 216 28 28 224 20 A 90 Little Endian Big Endian Big Endian Figure 3 6 Intel CPU View with switched to Big Endian TPCI200 User Manual Issue 1 4 Page 17 of 36 TEWS S TECHNOLOGIES 3 4 4 PowerPC CPU View with TPCI200 switched to Big Endian Expected by PowerPC CPU TPCI200 IPAC X 4 4 X X Byte access can be done with addresses Higher described in the Address IP manual X x x v P lt 28 l
25. n sequence from the on board EEPROM This EEPROM contains the following configuration data e From 0x00 to 0x27 PCI Configuration e From 0x28 to 0x87 Local Configuration EEPROM Address 0x00 0x02 0x04 0 06 0x08 Ox0A OxOC OxOE 0x00 0x30C8 0x1498 0 0280 0 0000 0 0680 0 0000 0x300A 0x1498 0x10 0 0000 0x0040 0x0000 0x0100 0 4801 0 0001 0 0000 0 0000 0x20 0 0000 0 4 06 0 0000 0x0003 OxOFFF OxFFOO OxOFFF OxFCOO 0x30 Ox0E00 0 0000 OxOFOO 0 0000 0 0000 0 0000 0 0800 0 0001 0x40 0 0400 0x0001 0x0000 0 0001 0 0200 0 0001 0 0000 0 0000 0 50 0xD441 0 60 0 Oxi441 Ox20A2 0 1441 Ox20A2 0 1401 Ox20A2 0x60 0 0000 0 0000 0 0800 0 0081 0 0400 0 0201 0 0100 0 0001 0 70 0 0280 0 0001 0 0030 0 0041 0 007 0 4000 0 0224 0 9252 0 80 0 0000 0 0000 0 0000 0x0000 OxFFFF OxFFFF OxFFFF OxFFFF 0 90 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxAO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF 0 0 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF 0xCO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxEO OxFFFF OxFFFF OxFFFF O
26. r interrupt disabled 1 0 1 0 1 0 1 IP B error interrupt enabled 2 TIME INT EN 0 IP B timeout interrupt disabled IP B timeout interrupt enabled 1 RECOVER IP B recover time disabled IP B recover time enabled IP B clock Rate 8 MHz IP B clock Rate 32 MHz O LSB CLKRATE Figure 4 8 IP B Control Register PCI Base Address 2 0x04 TPCI200 User Manual Issue 1 4 Page 26 of 36 Bit Name Description 15 MSB Read 14 E Always 0 13 Write 12 No effect should be written with O s 11 10 9 8 2 7 0 IP C interrupt 1 disabled 1 IP C interrupt 1 enabled 6 INTO EN 0 IP C interrupt O disabled 1 IP C interrupt O enabled 5 INT1 SENSE 0 IP C interrupt 1 level sensitive 1 IP C interrupt 1 edge sensitive 4 INTO SENSE 0 IP C interrupt 0 level sensitive 1 IP C interrupt O edge sensitive 3 ERR INT EN 0 IP C error interrupt disabled 1 IP C error interrupt enabled 2 TIME INT EN 0 IP C timeout interrupt disabled 1 IP C timeout interrupt enabled 1 RECOVER 0 IP C recover time disabled 1 IP C recover time enabled O LSB CLKRATE 0 IP C clock rate 8 MHz 1 IP C clock rate 32 MHz Figure 4 9 IP C Control Register PCI Base Address 2 0x06 TPCI200 User Manual Issue 1 4 TEWS S TECHNOLOGIES Page 27 of 36
27. s the complete IP J1 logic interface pin assignments Some of these signals are not used on the TPCI200 Pin Signal Pin 4 Signal Pin Signal Pin Signal 1 GND 2 CLK 26 GND 27 5V 3 Reset 4 DO 28 R W 29 IDSeltt 5 D1 6 D2 30 31 MemSel 7 03 8 D4 32 DMAReqi 33 IntSel 9 D5 10 D6 34 DMAck 35 lOSel 11 D7 12 D8 36 Reserved 37 1 13 D9 14 D10 38 DMAEnd 39 2 15 D11 16 D12 40 Error 41 17 D13 18 014 42 IntReq0 43 4 19 D15 20 BSO 44 IntReq1 45 5 21 BS1 22 12V 46 Strobe 47 6 23 412V 24 45V 48 49 Reserved 25 GND 50 GND Figure 8 1 IP J1 Logic Interface Pin Assignment The IP J2 I O connector routes the IP I O lines directly to the appropriate pins of the 50 pin IP I O ribbon cable connector The pin assignment of the IP J2 I O connector is IP specific TPCI200 User Manual Issue 1 4 Page 36 of 36
28. ss 2 0x00 TPCI200 User Manual Issue 1 4 Page 23 of 36 TEWS S TECHNOLOGIES 4 2 2 P Control Register The IP Control Registers can be used to control IP interrupts recover time and clock rate Each IP has its own IP Control Register After power up or board reset all bits in the IP Control Register are cleared 0 Each IP interrupt can be enabled or disabled separately Interrupt detection can be switched between level and edge sensitive Edge sensitive interrupts must be cleared by a write to the corresponding bit in the IP Status Register If the ERR INT EN bit is set to 1 an active IP ERROR line will generate an interrupt This interrupt can be cleared by setting the ERR INT EN bit of the corresponding IP to The status of the IP ERROR line be read from the IP Status Register If the TIME INT EN bit is set to 1 and an IP timeout occurs the TPCI200 will generate an interrupt This interrupt can be cleared by writing 1 to the corresponding IP Timeout Status bit in the IP Status Register If IP recover time is enabled for an IP slot an IP cycle for this slot will not begin until the IP recover time is expired The IP recover time is app 1 5 IP Clock Rate can be selected between 8 MHz and 32 MHz for each IP separately After power up or board reset the Clock Rate is set to 8 MHz for all IP modules TPCI200 User Manual Issue 1 4 Page 24 of 36
29. t 98 lt 28 Correct 16 Bit 16 Bit Object access 20 lt 20 lt 20 224 lt 224 224 216 lt 26 216 Correct 32 Bit 32 Bit Object access 28 28 28 200 20 20 Big Endian Big Endian Big Endian Figure 3 7 PowerPC CPU View with TPCI200 switched to Big Endian TPCI200 User Manual Issue 1 4 Page 18 of 36 TEWS S TECHNOLOGIES 3 5 Big Little Endian Mode setting The PCI target chip of the TPCI200 the PCI9030 can be set to convert to Big Endian data ordering on the local bus This is useful for IP modules that use Big Endian byte ordering Big Endian byte ordering is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention Changing Local Space 0 1 or 2 to Big Endian mode results in swapped data lines of the local bus A 32 bit access is separated by the PCI9030 into two local 16 bit accesses Byte lane 0 and 1 are swapped and byte lane 2 and 3 are swapped During 16 bit access the upper and lower bytes are displayed in reverse order During 8 bit access odd and even addresses are swapped To access Address 0x00 the Address 0x01 must be used An access to Address 0x01 is done by Address 0x00 Little Endian Little Endian 31 0 31 0 PCI Bus Little Endian 5 Big Endian Local Bus First Cycle S d po BYT
30. t all IP RESET signals are asserted simultaneously Bit Name Description 15 MSB Read 14 Always 0 13 i Write No effect should be written with O s 10 9 8 7 6 5 gt 4 3 IPD RESET Read 0 RESET signal is de asserted 2 IPC RESET 1 IP RESET signal is asserted 1 IPB RESET Write O No effect 1 Assert corresponding IP RESET signal 0 LSB IPA RESET automatic negation after 200 ms Figure 4 11 IP Reset Register PCI Base Address 2 0x0A TPCI200 User Manual Issue 1 4 Page 29 of 36 TEWS S TECHNOLOGIES 4 2 4 IP Status Register The IP Status Register can be used to read IP timeout error and interrupt status An IP timeout occurs if the IP module fails to generate the IP ACK signal within the IP timeout time The IP timeout time is app 8us An IP timeout is not reported to the PCI9030 or the PCI master but in the IP Status Register If the corresponding TIME EN bit in the IP Control Register is set an interrupt is generated if a timeout occurs This interrupt can be cleared by writing 1 to the timeout status bit If a timeout occurs during an IP read all ones OxFF are returned The ERROR signal is used to indicate component failure unrecoverable self test failures or serious hard wired configuration errors The status of the IP ERROR signals can be read in the Status Register
31. x14 Local Re map Register Space 0 0x08000001 Enabled 0x18 Local Re map Register Space 1 0x04000001 Enabled 0x1C Local Re map Register Space 2 0x00000001 Enabled 0x20 Local Re map Register Space 3 0x02000001 Enabled 0x24 Local Re map Register ROM 0x00000000 Not used 0x28 Local Address Space 0 Descriptor 0xD44160A0 Timing local Space O 0x2C Local Address Space 1 Descriptor 0x144120A2 Timing local Space 1 0x30 Local Address Space 2 Descriptor 0x144120A2 Timing local Space 2 0x34 Local Address Space 3 Descriptor 0x140120A2 Timing local Space 3 0x38 Local Exp ROM Descriptor 0x00000000 Not used 0x3C Chip Select 0 Base Address 0x08000081 CS for local Space 0 0x40 Chip Select 1 Base Address 0x04000201 CS for local Space 1 0x44 Chip Select 2 Base Address 0x01000001 CS for local Space 2 0x48 Chip Select 3 Base Address 0x02800001 CS for local Space 3 0x4C Interrupt Control Status 0x00000041 Interrupt Configuration 0x4E EEPROM Write Protect Boundary 0x00000000 No write protection 0x50 Miscellaneous Control Register 0x007A4000 Retry Delay max 0x54 General Purpose Control 0x02249252 2 52 GPI O3 CS3 0x70 Hidden 1 Power Management data select 0x00000000 Not used 0x74 Hidden 2 Power Management data scale 0x00000000 Not used Figure 3 2 Local Configuration Registers TPCI200 User Manual Issue 1 4 Page 12 of 36 TEWS S TECHNOLOGIES 3 3 Target Configuration EEPROM After reset the PCI9030 starts to load the configuratio
32. xFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF Figure 3 3 PCI9030 Configuration EEPROM Content TPCI200 User Manual Issue 1 4 Page 13 of 36 TEWS S TECHNOLOGIES 3 4 Endian Conventions This chapter tries to illuminate the mixed use of Big Endian and Little Endian convention in one system The major difference between Big Endian and Little Endian are swapped byte lanes The byte lanes for 16 bit and 32 bit data busses with Big Endian and Little Endian are shown below Little Endian convention on a 16 bit Data Bus Byte Lane Byte 1 Byte 0 Data Line D15 D8 D7 DO LSB Big Endian convention on a 16 bit Data Bus Byte Lane Byte 0 Byte 1 Data Line D15 D8 D7 DO LSB Little Endian convention on a 32 bit Data Bus Byte Lane Byte 3 Byte 2 Byte 1 Byte 0 Data Line D31 D24 D23 D16 D15 D8 D7 DO LSB Big Endian convention on a 32 bit Data Bus Byte Lane Byte 0 Byte 1 Byte 2 Byte 3 Data Line D31 D24 D23 D16 D15 D8 D7 DO LSB The PCI Bus and all Intel CPUs work in Little Endian mode VMEbus PowerPC and 68K CPUs work in Big Endian mode Most IP modules which are common in VMEbus systems also use Big Endian byte ordering The TPCI200 works in Little Endian mode by default but can be switched to work in Big Endian mode This leads to 4 major Big Littl
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