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GPL162002A/162003A Programming Guide

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1. P_ECC_ERRO_LB 0x785E ECC Low Byte Field 0 Error Flag Bit 15 14 13 12 11 101 9 8 7 6 5 4 3 2 1 0 Function 2ERR 1ERR FAILBIT FAILLINE Init 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 P_ECC_ERR1_LB 0x785F ECC Low Byte Field 1 Error Fla Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function 2ERR 1ERR FAILBIT FAILLINE Init 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 P_ECC_LPRL_HB 0x7848 ECC High Byte Line parity LSB Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LPRL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_ECC_LPRH_HB 0x7849 ECC High Byte Line parity MSB Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LERH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P ECC CPR HB 0x784A ECC High Byte Column parity Register Bit 151 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CPR Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P ECC LPR CKL HB 0x784B ECC High Byte Line parity Check LSB Register Bit 154 14 134 12 411 10 9 8 7 6 5 4 3 2 1 0 Function LPRCKL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P ECC LPR CKH
2. P_USBH_DveAddr 0x7B04 USB Device Address Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DAddr Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P USBH DveEP 0x7B05 USB Device Endpoint Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DEP Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P USBH TXCount 0x7B06 USB Host Transmit Count Regisiter Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TXC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P USBH RXCount 0x7B07 USB Host Receive Count Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RXC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBH_FIFOInPointer 0x7B08 USB Host FIFO Input Pointer Register Bit 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 Function HFIP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBH_FIFOOutPointer 0x7B09 USB Host FIFO Output Pointer Register Bit 154 14 133 12 1111 10 9 8 7 6 5 4 3 2 1 0 Function HFOP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P USBH AutolnByteCount
3. P_TFT_PIPO_V_START 0x7D1B TFT PIPO Vertical Start Location in Each Frame Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function PIPO V STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP1 V START 0x7D26 TFT PIP1 Vertical Start Location in Each Frame Bit 15 14 13 4 12 11 10 8 7 6 5 4 3 2 1 0 Function PIP1 V STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP2 Y START 0x7D31 TFT PIP2 Vertical Start Location in Each Frame Bit 45 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function gt PIP2 V STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 V START 0x7D3C TFT PIP3 Vertical Start Location in Each Frame Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function PIP3 V STR Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 real Reeves CC PIP V STR R W The PIP frame vertical start location in the main frame See the following diagram for details V1 0 Dec 20 2006 Generalplus Technology Inc PAGE 149 G Generalplus GPL162002A 162003A Programming Guide P TFT PIPO V END Ox7D1C TFT PIPO Vertical End Location in Each Frame Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPO V END Default 0 0 0 0 0 0 0
4. P_MCS1_Ctrl 0x7821 CS1 Device Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CS1SIZE CS1MD WARWAT CS1WAIT Default 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 P_MCS2_Ctrl 0x7822 CS2 Device Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CS2SIZE CS2MD WARWAT CS2WAIT Default O 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 P_MCS3 Ctrl 0x7823 CS3 Device Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CS3SIZE CS3MD WARWAT CS3WAIT Default 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 P_MCS4 Ctrl 0x7824 CS4 Device Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CS4SIZE CSAMD WARWAT CSAWAIT Default 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 P EMUCS Ctrl 0x7825 EMU Device Control Register Bit 15 14 13 12 41 10 9 8 7 6 5 4 3 2 1 0 Function EMCMD WARWAT EMUCSWAIT Default 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 P_MCS Byte Sel 0x7826 MCS Word Byte Data Select register Bit 15 14 13 4 12 11 10 7 6 5 4 3 2 1 0 Function EMU S4 S3 S2 S1 SO Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_MCS3_WETimingCtrl 0x7827 MCS3 WE timing control register Bit 15 14 13 12 11 10 7 6 5 4 3 2 1 0 Function WEB3NUM Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P MCS4 WETimingCtrl 0x7828 MCS4 WE timing control register Bit 15
5. Bit Function Type Description Condition 15 0 TMXPLR TimerX pre load register EE P TimerA CCP Reg 0x78C3 TimerA Capture Comparison PWM Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Function TMACCPR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 77 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TimerB_CCP_Reg 0x78CB TimerB Capture Comparison PWM Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMBCCPR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerC_CCP_Reg 0x78D3 TimerC Capture Comparison PWM Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMCCCPR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Gemen 15 0 TMXCCPR TimerX Capture Comparison PWM register QD
6. VCC 33 ug R29 1 48 GND x 1 48 MDT5 10k x 12 EE MD7 x 3 46 D 4 45 MDTA 514 a N47 GND ps N43 NFRDY TVS Bla MD5 NFRE 8 7 4 NAT NFCS 9 5 d 40 MD 10 39 x 10 39 SX vcc a3 X2 k EC aX VCC 33 GND GND Hu ZG 5714 35 x NECLE 76 115 34 33 X MD11 NFALE 47 46 391097 MDS NFWE 18 ae 321031 N31 NFWP 1918 31 30 N30 20129 30125 N29 7120 29 28 MDT caja Bf MDE X 21 2 Y MDO a 8 26 35 GND x 24 25 NAND NAND 3 13 NFWE 1 16 IOB5 NFRE 2 Is TOB6 NFCLE EN EXE EL TOB7 NFALE SCH EE o TOBE NFRDY s e TOBI x i X Xl FX JP62 x a x HEADER 2 SW DIP 8 voc_33 EN VCC 33 NFCS C100 Out GND CE SW5A MD7 N44 2 ei M6 SW 6P2T SW5B MD6 N43 5 o MD13 El SW 6P2T Du oi C0 SWSC MD4 E N41 8 MD12 P MD SW 6P2T so acd SW5D 10 MD2 N31 11 12 MD10 pt mn SW ane HEADER 12X2 SW5E 13 MD1 IOB 0 15 N30 14 MD 15 0 015 MD2 logo MDO SW 6P2T SW5F 16 MDO 1085 N29 17 18 MD9 018 MB SW 6P2T JP73 HEADER 3 VCC 33 En Mesa NFWP WP Generalplus Technology Inc PAGE 390 V1 0 Dec 20 2006 A Generalplus GPL162002A 162003A Programming Guide L Power c108
7. P_CHA_FIFO 0x78F2 CHA FIFO Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function FFUL FUDN FRST CHAFEILV CHAFINX Default 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 P CHB Ctrl 0x78F8 CHB DAC PWM Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function FEMIF C FEMIEN CHBEN SSF CHACFG MONO la 24 we Default 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O P_CHB_Data 0x78F9 CHB DAC PWM Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CHBDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_CHB_FIFO 0x78FA CHB FIFO Control Register Bit 15 14 13 12 M11 10 9 8 7 6 5 4 3 2 1 0 Function FFUL FUDN E FRST CHBFEILV CHBFINX Default 0 0 0 w0 On 0 0 0 1 0 0 0 0 0 0 0 P DAC Ctrl 0x78FD DAC Control Register Bit 45 14 413 12 211 109 8 7 6 5 4 3 2 1 0 Function 2 BPFIR AS S SP DLY AS CYCLE AS RANGE PWDAL PWDAR IIS DACLK Default 0 0 0 O 0 0 0 0 0 0 0 0 1 1 0 0 P HPAMP Ctrl 0x78FE Headphone Amplifier Control Register Bit 15 14 13 1211110 1 9 8 7 64 5 4 3 2 1 0 Function PWSPVR SPIN
8. VCC_33 C78 BEN dB A 10uF ICECK T 0 1uF ICEDA i 4 HEADER 5 R26 1006 80 cat VCC 33 68pF 68pF JP52 i 2 3 4 4 4 5 6 HEADER 6 G UART IrDA VCC 33 o 4 IOC O 15 cnn SE un C112 22u 10c9 10u 16 1 H vcc Cth k V C1 0 1 u v C c114 22u as vss C2 she P1 x T 10u A 7 amp UARTEDATX E Be TOUT rn RA UARTIDATA o XELSE OUT TIN Hs gt SUARTIDARX ot El 5 RIN RI OUT LR UARTIDARX o 5 AG RIN RAQUEL X O ox ol 1CL232 CONNECTOR DB9 HP3201 VCC_33 o 1 Ly 2 GND x NC Y EY T Sal vcc 9 Le ug o 5 AGND SHIELD C416 C117 UARTIDARK 6 SO 0 1 10 UARTIDATX 7 Ras u u T 150 2s a VCC_33 VLED zb Ohm UTZ VCC 33 o JP69 IRSD 1 3 HEADER 3 H Generalplus Technology Inc PAGE 387 V1 0 Dec 20 2006 A Generalplus GPL162002A 162003A Programming Guide H Key Scan JP53 SW DIP 8 IOA 0 15 9 8 IOA8 IOA0 9 10 7 TOAS 8 115 re TOATO 7 Pl TOATT D2 6 3 4 TOATZ 1 2 2 14 3 TOA13 15 E TOATS DIODE 3 16 L1 TOATS 2 1
9. 15 0 NIBSWAP R W Nibble swap Write B15 BO to this control register and thenread this control register to obtain B11 B8 B15 B12 B3 BO B7 B4 P TwoBit Swa 0x7BD2 2 Bit Swap Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 BO Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 305 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition 15 0 2BSWAP R W Two bits swap Write B15 BO to this control register and then read this control register to get B13 B12 B15 B14 B9 B8 B11 B10 B5 B4 B7 B6 B1 B0 B3 B2 P_Bit_Reverse 0x7BD3 Bit Reverse Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 JeB0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description gt condition 15 0 BITREV R W Bit reverse Write B15 BO to this control register and then read this control register to get B0 B15 22 3 Program example r1 0xFA50 P_Byte_Swap r1 P_Nibble_Swap r1 P_Bit_Reverse r1 r1 0x6996 P_TwoBi
10. P USBD EPStall 0x7B54 USB Endpoint Stall Bit Register Bit 151141131121 11 10 9 8 1 6 5 41 3 2 1 0 Function HISS BOSS BISS EPROSS IISB BOSB BISB EPOSB Default 0 0 0 O 0 0 0 0 0 0 00 0 0 0 0 P USBH Config 0x7B00 USB Host Configuration Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SUS ASOF SOFTR HOSTEN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBH_TimeConfi 0x7B01 USB Host Timing Configuration Register Bit 15 14 134 124 11 10 9 8 7 6 5 4 3 2 1 0 Function SAU PAC TC IPD Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBH_Data 0x7B02 USB Host Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function HDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBH_Transfer 0x7B03 USB Host Transfer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RST OD1 ODO ID1 IDO Setup SOF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NENNEN Generalplus Technology Inc PAGE 350 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide
11. P DMA MISCO 0x7B87 DMA miscellaneous Control Register 0 Bit 15 14 13 12 1 10 9 8 7 y6 5 4 3 2 1 0 Function DMARQ ERRW TRANS EN DMATO STATE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_MISC1 0x7B8F DMA miscellaneous Control Register 1 Bit 15 14 13 12 1 101918 1 17 16 11 51 1 1413121 1 10 Function DMARQ ERRW TRANS EN DMATO STATE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_MISC2 0x7B97 DMA miscellaneous Control Register 2 Bit 15 14 13 12 111001981716 51 413121110 Function DMARQ ERRW J TRANS EN DMATO STATE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_MISG3 0x7B9F DMA miscellaneous Control Register 3 Bit 15 14 13 12 111019817161 514113121110 Function DMARQ ERRW TRANS EN DMATO STATE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition DMARQ R DMA Terminal Count High 25 16 ERRW R CPU update the DMACONX when a DMA is bust Reeved _ j If this bit is set to 1 then when DMA read a data 1 Enable matched the TRANSPART this data will not be written to target address 15 TRANS EN R W DMA Transparent Enable 0 Disable Generalplus Technology Inc PAGE 275 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Description Condition DMATO R W DMA Time Out Counter 00 Time out function These bits are to set the time o
12. IOA 8 SUR tae Ske Ge Soe 1 IOA 9 a IE T I 1 3 i IOA 10 Rc p O L en t IOA 11 EIL AI 1 l l t IOA 12 Ex qp mI A i IOA 13 Edo ES RO ae xc Ge en i IOA 14 ET IGI atc 1r i IOA 15 EX IE ae oci Ly Fig1 Key Scan Application Circuit when INV in P KS Ctrl is set to 0 IOA 0 IOA 1 IOA 2 IOA 3 IOA 4 IOA 5 IOA 6 IOA 7 CLD 0 CLD 1 CLD 2 CLD 3 CLD 4 CLD 5 CLD 6 CLD 7 IOAIS FL P qd MO E i I IOA 9 P ed TNT SR e i IOA 10 El Kl Kl Kl CO Kl Kl Kl IOA 11 LI IT Ge 4 ie pipu I 3 IOA 12 LI AI ET ee KIKI ep KA IOA 13 RL L PT OL T OD IOA 14 ET 1 411 1 ET 1 45 IOA 15 EI Op e E en E O OD Fig2 Key Scan Application Circuit when INV in P_KS Ctrl is set to 1 Generalplus Technology Inc PAGE 295 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 21 4 Sample Time Configuration There are two modes of the sampling time of the key scan controller One is used only when the LCD is turned on and shares IO with key scan controller In this mode the scan time depends on the blank time of LCD interface between each line the length of this period is 6 T at least and 100 T at most depending on users definition on the LCD controller All the blank time will be used as one sampling time consequently it will take a sampling time to complete an
13. Function RST LRME SUS INNA IINPC BONA BOPS BINA BIPC EOSNA EOSC EOINNA EOINPC EQONA EOOPS EOSPS Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P USBD INTF 0x7B3A USB Interrupt Flag Register Bit 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Function RST RME SUS IINNA IINPC BONA BOPS BINA BIPC JEOSNA EOSC EOINNA EOINPC EOONA EOOPS EOSPS Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_SCINTEN 0x7B3B USB Standard Command Interrupt Enable Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function GSTS CFEA SFEA SADD GCON SCON GINT SINT Default 0 0 0 0 0 0 0 O 0 0 0 0 0 0 0 0 L Generalplus Technology Inc PAGE 347 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_USBD_SCINTF 0x7B3C USB Standard Command Interrupt Fl
14. 0x7BB1 DMA Sprite Size 9 0 Register 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SPRISIZE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x7BB2 DMA Sprite Size 9 0 Register 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SPRISIZE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x7BB3 DMA Sprite Size 9 0 Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SPRISIZE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x7BB8 DMA Transparent Pattern Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRANSPAT Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x7BB9 DMA Transparent Pattern Register 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRANSPAT Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_TRANSPAT2 0x7BBA DMA Transparent Pattern Register 2 Bit 15 4 14 134 121 41 10 9 8 7 6 5 4 3 2 1 0 TRANSPAT Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA TRANSPAT3 0x7BBB DMA Transparent Pattern Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRANSPAT Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_LINELENGTH 0x7BBD DMA Line Length Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LINELENGTH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L PAGE 365 V1 0 Dec 20 2006 Generalplus Technology Inc G Generalplus GPL162002A 162003A Programming Guide P_DMA SS 0x7BBE DMA Sourc
15. P EMUCS Ctrl 0x7825 EMU Device Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EMCMD WARWAT EMUCSWAIT Default 0 0 0 0 0 0 0 4 8 0 1 0 0 1 1 1 1 Bit Reseed ON 7 6 EMCMD R W EMU Memory Device Access Mode 00 ROM SRAM To define which memory device is on 01 ROM SRAM EMUCE such as ROM SRAM NOR or 10 NOR Flash NAND Flash memories 11 NAND Flash 5 4 WARWAT R W SRAM Write after Read Wait State WARWAT 1 0 SYSCLK When data is written to memory and then read it immediately from the same address CPU will wait WARWAT 1 0 SYSCLK to read it 3 0 EMUCS R W EMU Memory Device Access Wait State Range 0 15 WAIT Setup Criterion Tw EMUCEWAIT 3 0 1 EMUCSWAIT 3 0 1 SYSCLK cycle SYSCLK gt memory device access time GPL162002A 162003A allows programmers to define wait cycles for each external device by setting corresponding CSOWAIT CS1WAIT CS2WAIT CS3WAIT CS4WAIT and EMUCSWAIT control bits The default wait cycles are 16 system clock cycles to ensure system working reliably without any setup GPL162002A 162003A can support access 8 bit memory mode via setup P_MCS_Byte_Sel register The 8 bit mode for each chip select is based on bit 4 0 of P MCS Byte Sel In this mode only low Generalplus Technology Inc PAGE 33 V1 0 Dec 20 2006 G Generalplus GPL162002
16. P IOA Attrib 0x7863 IOA Attribution Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOAATT Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 318 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_IOB_Data 0x7868 IOB Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOBDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P IOB Buffer 0x7869 IOB Buffer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOBBUF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P IOB Dir 0x786A IOB Direction Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOBDIR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P IOB Attrib 0x786B IOB Attribution Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOBATT Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_IOB_Latch 0x786C IOB Latch for Key Change Wakeup Bit 15 14 13 12 11 4 10 9 8 7 6 5 4 3 2 1 0 Function E IOBLH
17. P TFT PIPO VIR EAL 0x7D16 TFT PIPO Virtual Frame Buffer End Low Address Bt 15 14 13 12 11 10 9 8 7 6 5 LAN 3 241 0 Function PIPO VIR EAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP1 VIR EAL 0x7D21 TFT PIP1 Virtual Frame Buffer End Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1 VIR EAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP2 VIR EAL 0x7D2C TFT PIP2 Virtual Frame Buffer End Low Address Bit 15 14 13 12 L 11 410 9 8 7 6 5 4 3 2 1 0 Function PIP2 VIR EAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 VIR EAL 0x7D37 TFT PIP3 Virtual Frame Buffer End Low Address Bit 154 14 139 122 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP3_VIR_EAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIPO STARTAH 0x7D17 TFT PIPO Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPO SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP1 STARTAH 0x7D22 TFT PIP1 Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1 SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology I
18. P_DMA_TCouniL1 0x7B8B DMA Terminal Count Low Register 1 Bit 15 44 13 12441 10 9 8 7 6 5 4 3 2 1 0 Function TCountL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_TCountL2 0x7B93 DMA Terminal Count Low Register 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA TCountL3 0x7B9B DMA Terminal Count Low Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 TCountL R W DMA Terminal Count Low Address 15 0 Generalplus Technology Inc PAGE 272 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide The P_DMA_TCountLx registers are the terminal count low registers for each DMA channel and contain 16 bits value of remaining number of DMA transfers The DMA transfer will start only when this register is not zero It should be noticed that the value in this register means the remaining DMA transfer counts not the remaining words to be transfered The number in these registers will be decreased by one when a DMA transfer is completed When the WRITEREQ in P_DMA Ctrl 15 is set to 1 only the writing operation will decrease the counter Nevertheless when the WRITEREQ in P
19. E 8 gt K Sg 2 2 HSVLI AWA weu ms iow E 3 2 T E 8 Z QNO 3M ES s QNO 3M le 30 Im AMW vt 00A 30 Di MN 3 aan 30 8 El B 39 LB Le a S ar r t g EJ TONNES 9 NVES 3OnW3 DS QNO 3148 Z I ano 8 E HH Aqu L t EE z aa sn EE S 1 am SE 8 bn n Or 8 is I s a 188 zi lt i A EN oy EXE 8 Eu D y gt D ayl Liv 3r 8 av 86 ory LE gt aty L I l sia stw EYN sta siy EY BE SION Flag piy SYN SIGN la piy Ler Sen row t era ery LE EIS MON leg ery ZZ ES Ein zia ziv EEN LOW X lg zv SZ ENN ZION EE ia iiy ZW aan fig tiy SE ZLYW LION log oiv SYN LOW ZE oq otv ZYN Tola i leq ey OONN ON Elea ev ONW san leq ac Z SV 6ean leq gy 22 6VW gan 0 lg E gym san 6 jq 1v AZ eva gn log gy Zen LON 9 sq gy DOZ VW SO v 6L 9v SaN SL Gl OV sa sv sa s san lg v OZ svw san lg sy SL sww PONT 8 leq cc IN pran leg ey S byw gon Eza v DZ Yn EAN 2g sy EYN QW te o ty LEE VA QN 8 iq ty E EVA Taw IE oq ov EE LYW LOW Blog ov LYW IRC SC OV oan T L OVN g S g 8 8 e 2 ZHSWIA4 3 CA ES o INVHS E s ONS ss 3 m os Vez E g 8 a QNO 3M S a QNO 3M QNO 3M pa 30 3 eu ao LA MN X qu 30 ET Ae amn 39 4 ee 39 LH ON ee 39 Liv Som AE SE 2 LE 9 ISOW 9 OSIN oa Ss QNO 3148 E i uc ano 8 E y I ano 8 E u SE AQ KR ajaan gh 1 Z aan an 5d U sz dM 8 o E Di ov E S H oy 8
20. Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P I2C Data 0x7B63 I2C Data Register Bit 1514113112 111110 9 8 7 6 5 4 3 2 1 0 Function Data Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P I2C DeCLK 0x7B64 DC De bounce Clock Register Bit 15 14 13 12 111410 9 8 7 6 5 4 3 2 1 0 Function DEBCLK Init 0 0 0 0 0 On 00 0 0 0 0 0 0 0 0 P_I2C_En 0x7B65 DC Enable Register Bit 154 14 134 12 411 10 9 8 7 6 5 4 3 2 1 0 Function I2CEN Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA Control Register Summary Table Name Address Description P DMA CtrlO 0x7B80 DMA Channel Control Register O O Generalplus Technology Inc PAGE 359 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Name Address Description P_DMA_TAR_AddrL1 0x7B8A DMA Target Low Address 15 0 Register 1 P_DMA_TCountL1 DMA Terminal Counter Low 15 0 Register 1 P_DMA_SRC_AddrH1 DMA Source High Address 25 16 Register 1 P_DMA_TAR_AddrH1 DMA Target High Address 25 16 Register 1 P_DMA_TCountH1 DMA Terminal Counter High 25 16 Register 1 P DMA MISC1 Ox7B8F DMA miscellaneous Control Register 1 P DMA Ctrl2 0x7B90 DMA Channel Control Register 2 P DMA SRC Addrt 2 DMA Source Low Address 15 0 R
21. P TFT INT CTRL 0x7D02 TFT Interrupt Control Register Bit 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Function UE EIC UE EN TEE F C FEEN Default 0 0 Om 0 0 0 0 0 0 0 0 0 0 0 0 0 15 UF_F C RW TFT FIFO Underflow Error Interrupt Flag Read 0 Not Occurred This bitis set to 1 by hardware when TFT LCD Read 1 Occurred buffer data are not prompt in transmittng out Write 0 No Effect Write 1 to clear the flag Write 1 Clear the flag 14 UE EN R W TFT FIFO Underflow Error Interrupt Enable 0 Disable If this bit set to 1 and FIFO underflow interrupt 1 Enable occurs hardware will issue an IRQ5 or FIQ to CPU If this bit is clear to 0 this interrupt will be marked To select between IRQ5 or FIQ Please refer to Chapter Interrupt stg Reseed 11 FE F C R W Frame End Interrupt Flag Read 0 Not Occurred This bit is set to 1 by hardware when TFT Read 1 Occurred complete one frame data trandmission Write 0 No Effect Write 1 to clear the flag Write 1 Clear the flag 10 FE EN R W TFT Frame End Interrupt Enable 0 Disable If this bit set to 1 and frame end interrupt 1 Enable Generalplus Technology Inc PAGE 135 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide occurs hardware will issue an IRQ5 or FIQ to CPU If this bit is clear to 0 this interrupt will be marked To select between IRQ5 or FIQ
22. P TFT PIP1 VIR SAH Ox7D1E TFT PIP1 Virtual Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1 VIR SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP2 VIR SAH 0x7D29 TFT PIP2 Virtual Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2 VIR SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 VIR SAH 0x7D34 TFT PIP3 Virtual Frame Buffer Start High Address Bit 15 14 13 12 11 10 L 9 8 7 6 5 4 3 2 1 0 Function PIP3 VIR SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition pswp NN Reseed 10 0 PIP _VIR_SAH R W PIPE Virtual Start High Address This register is valid only when PIPZSCREN is setto 1 The virtual frame start address means the real address of data not TFT PIP buffer start address See the following diagram for details P_TFT_PIPO VIR_SAL 0x7D14 TFT PIPO Virtual Frame Buffer Start Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPO_VIR_SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP1_VIR_SAL 0x7D1F TFT PIP1 Virtual
23. EPOWC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 198 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition psp Rena 3 0 EPOWC EPO Write Count Read these bits to acquire the number of data in the EPO FIFO P USBD BOWrtCount 0x7B42 USB Bulk OUT Write Count Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BOWC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description eil Reserve KG BOWC Bulk Out Write Count Read these bits to acquire the number of data in the Bulk Out FIFO P USBD EPOBufPointer 0x7B43 USB EndpointO Buffer Pointer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EPOWBP EPORBP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 aL D Reserved E X A These bits are used as the write pointer of EPO FIFO Emm These bits are used as the read pointer of EPO FIFO P USBD BliBufPointer 0x7B44 USB Bulk IN Buffer Pointer Register Bit 15 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BIBWP BIBRP Default 0 0 0 0 0 0 0 0 0 0 0
24. P_TimerA_UpCount 0x78C4 TimerA Up Count Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMAUCR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerB_UpCount 0x78CC TimerB Up Count Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMBUCR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TimerC UpCount 0x78D4 TimerC Up Count Bit 15 A4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMCUCR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerD_UpCount 0x78DC TimerD Up Count Bit 157 114 gt 13 112 11 10 19 8 7 6 5 4 3 2 1 0 Function TMDUCR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerE_UpCount 0x79C4 TimerE Up Count Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMEUCR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerF_UpCount 0x79CC TimerF Up Count Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMFUCR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L Generalplus Technology Inc PAGE 78 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition 15 0 TMXUCR TimerX up count The up counter s value can be read from this register 7 4 Program Examples DEFINE SYSCLK parao L_TimerCClockSourcePolling r1 0x0001 P IOC Attrib r1 P IOC Dir r1 Int off r1 0x10000 SYSCLK 2 8000 P TimerC Preload r1 r1 0x2000 P TimerC Ctrl r1 L CheckTimerCOv
25. P SPI Ctrl 0x7940 SPI Control Register Bit 15 14 13 12 11 10 9 8 746 5 4 212111 0 Function SPIEN LBM SPIRST J IMOD I SCKPHA SCKPOL SCKSEL Default 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 Bit Function Type Deserpion Condition 15 SPIEN RW ASPI enable 0 Disabled If thissbit is set to 1 and MOD 0 PortB 11 10 1 Enabled and PortD4 PortD11 become a SPI Interface If this bit is set to 1 and MOD 1 PortB11 and PortD4 PortD11 become a SPI Interface These pins cannot be used as GPIO once SPI is enabled Therefore any further setting on the selected GPIOs will be no effect Jl PE o 13 LBM Loop Back Mode Selection 0 Normal Mode When this bit is set to 1 the SPIRX will be 1 SPIRX SPITX connected to SPITX internally It is for test only 2 AAA G O 11 SPIRST W SPI Soft Reset 0 No effect If this bit is written by 1 the state machine of 1 Reset SPI Controller SPI controller and FIFO pointer will return to the original value oy TI Reserved ooo Generalplus Technology Inc PAGE 172 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide EE R W SPI Mode Selection register 0 Master In slave mode GPL162002A 162003A only 1 Slave supports SCKPHA 0 SCKPOL 0 timing And SPICSN becomes SPI chip select pin In master mode GPL162002A 162003A supports four SPI timing setti
26. ss 298 21 8 Control Reiser A A 298 21 9 3 EAS O WEE b VETE ee RP CLTC DLL Om 303 22 leien E OA E e EA A E dial 305 22 1 INTFOUCION s em WEE 305 22 2 A 305 22 3 Neie Al example L SSS tada 306 23 E FUSE OPTION o 307 23 1 tte ele EE 307 23 2 e ME 307 24 LINK YOUR PROGRAM ES 309 24 1 Resource File Alignment by Link Script File ss 309 25 APPENDIX 311 25 1 Normally used abbreviation list ss 311 25 2 Control Register Mapping List by function 312 25 3 Crystal Usage Guide iii ipei Obat et je sues Us ERE Ree d aue kashas Eua 371 Generalplus Technology Inc PAGE 7 V1 0 Dec 20 2006 G Generalplus 25 4 25 5 25 6 25 7 25 8 25 9 25 10 25 11 GPL162002A 162003A Programming Guide Development Emulation Board Configuration eee eee 372 25 4 4 Power Adjustment amp Selection si 375 2594 2 ROSES ER titu SIUE AED DE 375 2534 3 Le agapayu 375 254 4 A2MHz Crystal cee nents 375 254 5 CPU ee 376 29546 uM ERE 376 254 7 A dlo DU ea bios 376 254 8 Analog n But u cocci n ee creer cre eee ng dee ENEE SEENEN 376 25 4 9 Others Input and Output sde AN 378 Development Emulation Board Schematic es f t M 381 CPU Performance Downgrade lssue t t ta 393 25 6 1 L
27. Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bi Function Type Description Condition _ pss Reseed r0 Japan au Buk In Data BEEN Generalplus Technology Inc PAGE 186 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_USBD_BOData 0x7B35 USB Bulk OUT Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BODATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 Reserved rg sonara pw Bulk out Data EE P_USBD_INTINData 0x7B36 USB Interrupt IN Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function INTINDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition _ reg Reseed XA YN 7 0 INTINDATA RW lnteruptIN Data Po P_USBD_NullPkt 0x7B58 USB Null Packet Register Bit 15114113112111110 9 84716 5 44 3 2 1 0 Function hase VA IIN_NULLPKT BLNULLPKT EPO NULLPKT Default 0 0 0 O O 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition ps3 CN AP _ 2 IN NULLPKT RW Write 1 to enable USB device to send a null packet to the Interrupt IN endpoint
28. Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sg Reseed V_START R W TFT Horizontal Display Start Line Vertical start line This register is to set the number of TFT_Vsync V_START 1 to first meaningful TFT_Hsync See the following diagram for details Generalplus Technology Inc PAGE 137 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TFT_V_END 0x7D09 TFT Vertical End Location Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function V_END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Le ug Begin gei us Reserved V END R W TFT Vertical Display End Line Horizontal end location This register is to set the number of V_END 1 TFT Vsync to last meaningful TFT Hsync See the following diagram for details P TFT VSYNC SETUP 0x7D0A TFT Vsync Setup Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function VS_POL VS_WIDTH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 En L teton vee Design Sud VS_POL RAW TFT Vertical Synchronous Polarity 0 Negative Low pulse 1 Positive E pulse 14 9 9 NEXT TFT Vertical Line Width Vertical used line width This register is to set the number of VS WIDTH 1 real used vertical line See the following diagram for details L Generalplus Technology Inc PAGE 1
29. P RTC INT Ctrl 0x7936 HMS Alarm Schedule Interrupt Control Register Bit 1511411211211 10 9 8 7 6 5 4 3 2 1 0 Function ALMIEN SCHIEN HRIEN MINIEN SECIEN HSECIEN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description gt gt condition msm Reeved ND 10 ALMIEN R W Alarm Interrupt Enable 0 Disabled If this bit is set to 1 and alarm interrupt occurs 1 Enabled hardware will issue an IRQ7 to CPU If this bit is cleared to 0 this interrupt will be masked off Lal Reseves V IV O SCHIEN R W Scheduler Interrupt Enable 0 Disabled If this bit is set to 1 and schedule interrupt 1 Enabled occurs hardware will issue an IRQ6 to CPU If this bit is cleared to 0 this interrupt will be masked off Generalplus suggests programmers do not use scheduler as halt sleep mode wake up source because the scheduler interrupt occurs more quickly than the time that CPU wakes up from halt sleep mode As a result the scheduler interrupt flag will not be held from halt sleep wake up ga ET G 3 HRIEN R W Hour Interrupt Enable 07 Disabled If this bit is set to 1 and hour interrupt occurs 1 Enabled hardware will issue an HMS IRQ7 to CPU If this bit is cleared to 0 this interrupt will be masked off 2 MINIEN R W Minute Interrupt Enable 0 Disabled If this bit is set to 1
30. Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA TCountHO 0x7B86 DMA Terminal Count High Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H Generalplus Technology Inc PAGE 363 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_DMA TCountH1 0x7B8E DMA Terminal Count High Register 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA TCountH2 0x7B96 DMA Terminal Count High Register 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA TCountH3 0x7B9E DMA Terminal Count High Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA MISCO 0x7B87 DMA miscellaneous Control Register 0 Bit 15 14 13 12 11 107 9 817 F6 5413121110 Function D
31. G Generalplus GPL162002A 162003A Programming Guide 15 2 USB Device When GPL162002A 162003A is used as a USB device it supports 4 endpoints control pipe bulk in bulk out and interrupt in For control pipe when GPL162002A 162003A receives the standard command it will automatically reply it except Get Set Descriptor That is when it receives GET STATUS CLEAR_FEATURE SET_FEATURE SET_ADDRESS GET_CONFIGURATION SET_CONFIGURATION GET_INTERFACE and SET_INTERFACE GPL162002A 162003A will auto reply these standard commands For bulk in and bulk out the maximum packet size is 64 bytes GPL162002A 162003A supports non DMA or DMA transfers For non DMA mode it is 8 bits for MCU access and it is 16 bits access for DMA mode 15 3 USB Mini Host GPL162002A 162003A can be used as a USB mini host It supports commands IN and OUT transfer For command transfer it is 8 bits for each data For IN and OUT transfer the maximum packet size is 64 bytes and it is 8 bits for MCU access or 16 bits for DMA access When it uses DMA mode the data to be transferred must be mulitiple of 64 bytes 15 4 Serial Interface Control Pin Configuration eo Ne USR Da USB D pin 15 5 Control Registers USB Device Register Summary Table Name Address Description P USBD Config 0x7B30 USB Configuration Register P USBD EPOData 0x7B33 USB EndpointO Data Register Generalplus Technology Inc PAGE 180 V1 0 Dec 20 2006
32. CH3BY CH2BY CH1BY CHOBY CH3TOIF CH2TOIF CH1TOIF CHOTOIF CH3IF CH2IF CH1IF CHOIF Init 0000 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 12 Reserved NENNEN Generalplus Technology Inc PAGE 279 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Description Condition DMA Channel3 Busy Flag 07 Idle 1 Busy 1 Bus 1 Bus 1 Busy 7 CH3TOIF DMA Channel 3 Time Out flag 0 Not time out interrupt CH2TOIF CH1TOIF This bit will be clear if programmers write 1 1 Time out interrupt to CH3IF to clear interrupt flag DMA Channel 2 Time Out flag 0 Not time out interrupt This bit will be clear if programmers write 1 1 Time out interrupt to CH2IF to clear interrupt flag DMA Channel 1 Time Out flag 0 Nottime out interrupt This bit will be clear if programmers write 1 1 Time out interrupt to CH1IF to clear interrupt flag DMA Channel 3 complete Interrupt Flag Read 0 Not Occur Read 1 Occur Write 0 No Effect Write 17 Clear the Flag DMA Channel 2 complete Interrupt Flag Read 0 Not Occur Read 1 Occur Write 0 No Effect Write 17 Clear the Flag DMA Channel 1 complete Interrupt Flag Read 0 Not Occur Read 1 Occur Write 0 No Effect Write 17 Clear the Flag DMA Channel 0 complete Interrupt Flag Read 0 Not Occur Read 1 Occur Write 0 No Effect Write 1 Clear the Flag 4 CHOTOIF DMA Channel 0 Time Out
33. Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT LINE NUM 0x7D11 TFT Line Numbers in Each Line Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LINE NUM Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIPO_CTRL 0x7D12 TFT PIPO Control Register Bit 15 14 13 12 11 10 8 7Vye 5 4 3 2 1 4 0 Function PIPOEN PIPOSCREN hsl Default 0 0 o 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP1_CTRL 0x7D1D TFT PIP1 Control Register Bit 15 14 13 12 14 109 8 7 6 5 4 3 2 1 0 Function PIP1EN PIPISCREN esa Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP2_CTRL 0x7D28 TFT PIP2 Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2EN PIP2SCREN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP3 CTRL 0x7D33 TFT PIP3 Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1_0 Function PIP3EN PIPSSCREN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O P_TFT_PIPO_VIR_SAH 0x7D13 TFT
34. G Generalplus GPL162002A 162003A Programming Guide 6 4 Program Examples PUBLIC _BREAK _FIQ IRQ6 ee ee e e dee k RARA ee ER KER ee eee BREAK Software Break ISR reti _FIQ push r1 to sp J Save destroyed CPU register r1 to stack r1 P INT Status1 r1 r1 amp C INT AUDAFIFOEmpty ja L End AudioCHA ISR P CHA Ctrl r1 r1 P_CHA Ctrl 1 Clear Interrupt Flag L End AudioCHA ISR pop r1 from sp I Restore original CPU register r1 from stack reti J eoo IRQ6 push r1 r3 to sp H Save destroyed CPU register r1 r2 r3 to stack r2 P INT Status2 r1 r2 amp C INT TimeBaseC jz L End TimeBaseC ISR r1 P TimeBaseC Ctrl H Clear Interrupt Flag ID TimeBaseC Ctrl r1 L End TimeBaseC ASR 4 pop r1 r3 from sp Il Restore original CPU register r1 r2 r3 from stack reti Generalplus Technology Inc PAGE 67 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 7 1 7 2 7 Timer Counter Timer Introduction GPL162002A 162003A contains six 16 bit timers counters TimerA to TimerF TimerA TimerB and TimerC support Capture Comparison PWM CCP functions when cooperating with their own two 16 bit registers a preload register and a CCP register On the other hand TimerD TimerE and TimerF have only one 16 bit preload register and therefore these timers do not provide CCP functions The clock sources of these six timers can be programmed by
35. Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_KS_Data7 0x7BCF Sample Data of Line IOA 7 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data7 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Miscellaneous Register Summary Table Name Address Description P_Byte Swap Ox7BDO P Nibble Swap Ox7BD1 Nibble Swap P TwoBit Swap Ox7BD2 Two Bit Swap P Bit Reverse 0x7803 P_Byte_Swap 0x7BD0 Byte Swap Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function b15 b14 b13 bnz bin b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 bO Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_Nibble_Swap 0x7BD1 Nibble Swap Bit 15 14 1413 12 11 10 9 8 7 6 5 4 3 2 1 0 Function b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TwoBit Swap 0x7BD2 2 Bit Swap Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 BO Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_Bit_Reverse 0x7BD3 Bit Reverse Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 BA B3 B2 B1 BO
36. Generalplus Technology Inc PAGE 241 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Description Condition LPRCKH The ECC Line parity Check register MSB P_ECC_CPCKR_LB 0x785D ECC Low Byte Column parity Check Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CPRCK Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 12 Reserved rto CPRCK RW The ECC Column parity Check register A gt P_ECC_ERRO LB 0x785E ECC Low Byte Field 0 Error Fla Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function 2ERR 1ERR FAILBIT FAILLINE Init 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 Bit Function Type Description Condition 15 13 Reserved sS Sm E 1 error ae CS 1 error log ee E others m error on bit m Kl leet others n error on line n P_ECC_ERR1_LB 0x785F ECC Low Byte Field 1 Error Fla Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function 2ERR 1ERR FAILBIT FAILLINE Init 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 Bit Function Type Description Condition 15 13 Reserved 12 2ERR There are two error bits 0 error free 1 error The error bit position 3 error free 11 1ERR There is on
37. Generalplus Technology Inc PAGE 29 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Wait state setup has one limitation That is device access time should always be smaller than designated wait cycle which is determined by number of system clocks There is indeed access time information on memory device data sheet but this access time criterion is under certain operating voltage and bus loading Therefore programmers should weigh some margins while trying to determine the period of wait cycle especially when system voltage varies not fixed to some specified operating voltages and when there are too many memory devices in a system Bus loading P_MCSO Ctrl 0x7820 CS0 Device Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CSOSIZE CSOMD WARWAT CSOWAIT Default 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 15 8 CSOSIZE R W Memory Device Size on Chip Select 0 CS0 Range 0 255 unit is 64K words CSOSIZE 7 0 1 defines Size CSOSIZE 7 0 1 the number of page for the entire memory 64Kword device on CSO Page size is 64K word Size Range 64K word 16384K word 7 6 CSOMD RW CS0 Memory Device Access Mode 00 ROM SRAM To define which memory device on CSO suchi 012 ROM SRAM as ROM SRAM NOR or NAND Flash 102 NOR Flash memories If NAND Flash is selected the 112 NAND Flash MCSO pin
38. G Generalplus GPL162002A 162003A Programming Guide 15 0 IOABUF R W Executing the read operation in this register will IOABUF R read the setup value from I O PortA data OADATA W register which is previously latched by IOABUF W IOADATA writing operation P_IOA Dir 0x7862 IOA Direction Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOADIR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 IOADIR R W This control register sets the direction of Refer to the above table I O PortA In addition the direction setup VO port configuration value can be read back from he same and function control register P IOA Attrib 0x7863 IOA Attribution Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOAATT Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 IOAATT RM This control register defines the attribution Refer to the above table of VO PortA In addition the attribution VO port configuration setup value can be read back from the and function same control register P IOB Data 0x7868 IOB Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOBDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 IOBDATA R W Executing the writing operation in this Refe
39. SD Controller Interrupt 0 Touch panel stylus tapped wakeup H UART IrDA receive wakeup_ A NO Serial Peripheral Interface SPl feceivewakeup XA o LCD frame pulse rising edge iwakeup o ADC Auto Sampling FIFOFullwakeup W o TimerA wakeup XY X o TmerB wakeup 7322 o TimerC wakeup H Timerwakedp NL o Key Scanwakeup x NT Oo TimebaseA ep TimebaseB wakeup O TimebaseC Wakeup o HMS Hour Minute Second wakeup 9 Mamwakeup Schedulerwakeup Low voltage detectwakeup_ Audio Channel AFIFO Empty wakeup_ o Audio Channel B FIFO Empty wakeup O TFT Under Flow Error wakeup notet o TFT Frame End wakeup note 1 J o LADC Conversion Ready wakeup O U O Supported X Not Supported Note1 GPL162003 without TFT control interrupt wake up source Generalplus Technology Inc PAGE 55 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide All interrupts are level triggered That is an interrupt flag has to be cleared when interrupt service begins otherwise CPU will re enter the Interrupt service routine again Most interrupt flags depicted in this chapter are read only reference only To enable or clear these interrupts programmers must write corresponding control bits individually which are depicted in the following chapter for each module peripheral The exceptions are the key
40. G Generalplus GPL162002A 162003A Programming Guide V1 0 Dec 20 2006 4F 1 No 83 Sec 2 Gong Dao Wu Rd Hsinchu City Taiwan 30072 R O C U 886 3 516 0211 886 3 516 0212 ju www generalplus com G Generalplus GPL162002A 162003A Programming Guide Important Notice Generalplus Technology reserves the right to change this documentation without prior notice Information provided by Generalplus Technology is believed to be accurate and reliable However Generalplus Technology makes no warranty for any errors which may appear in this document Contact Generalplus Technology to obtain the latest version of device specifications before placing your order No responsibility is assumed by Generalplus Technology for any infringement of patent or other rights of third parties which may result from its use In addition Generalplus products are not authorized for use as critical components in life support devices systems or aviation devices systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user without the express written approval of Generalplus H Generalplus Technology Inc PAGE 2 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide PAGE 1 yA _ A A 10 2 INTRODUCTION cocos 11 2 1 General le arts steers ee nee dan ke dene ae se tierce teens 11 2 2 Significant Features sise 11 2 3 o te EE 12
41. START Parity bit STOP bt if enabled 4 bit LSB MSB 5 8 data bits Note that 1 and 0 mean logical level respectively and also represent VCC and GND in GPL162002A 162003A on the other hand 1 and 0 mean 12V and 12V in RS232 compatible line IrDA SIR characteristic frame is depicted in the following diagram UART Frame Data Bits IrDA Frame Data Bits 3 amp sofware programmable pulse duration Generalplus Technology Inc PAGE 155 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide According to IrDA physical layer specification the upper and lower limits of pulse width duration vary in various signal rates The following table is the relative specification for IrDA SIR physical layer Programmers must ensure to meet the IrDA SIR specification Rate tolerance Pulse duration Pulse duration Pulse duration Signal rate Modulation p of rate Minimum Normal Maximum 2400 bits Rz 087 141us 7843us 88 55 us 9600 bits Rz 087 tatus 19 53 us 22 13 us 19200bus Rz1 3087 t4tus as morus seaoobivs Rzi Lamp t4tus As zue sveoobivs Rz1 3087 t4tus 3 26us gaus 13 4 UART IrDA Control Pin Configuration Name VO Description 0 URX 1 _ UART Reception Pin shared with Porci ur o UART Transmission Pin shared
42. 12 7 Operation during Wait Halt Standby amp Wakeup Procedure In wait mode the TFT is able to remain functioning even CPU is turned off because GPL162002A keeps PLL clock activating On the other hand the PLL clock is shutdown in both halt and standby modes and it will cause TFT unable to display in such modes Therefore Generalplus recommends setting the TFTEN control bit to 0 before entering halt mode and standby mode After GPL162002A wakes up from those modes set the TFTEN control bit to 1 again Simply programmer is able to turn on off LCD panel by configuring TFTEN control bit The GPL162002A will automatically perform the TFT power on off procedures in order to avoid unexpected lines occurring on the LCD panel Programming Example 320 Segment x 240 Common color 8 bit interface one PIP DEFINE SEGMENT 320 DEFINE COMMON 240 r1 0x0800 P_TFT_Ctrl r1 r1 0x01 IITFT clock system clock 2 P TFT DCEK Girl r121715 IITFT Hsync timing setup P TET AE Width r1 r1 239 P_TFT_H_Start r1 r1 1199 P TFT A End r1 r1 0x0000 P_TFT_HSync_Setup r1 r1 261 IITFT Vsync timing setup P_TFT_V_Width r1 r1 20 P_TFT_V_Start r1 r1 260 P_TFT_V_End r1 r1 0x0000 P_TFT_VSync_Setup r1 r1 0x8003 set serial mode set odd even RGB data P_TFT_RGB_Ctrl r1 Itype ri T BMP r1 2 liget pic address r2 r1 P_TFT_DMAStart_AL r2 Generalplus Technology Inc PAGE 152 V1 0 Dec 20
43. As for ECC check error registers here are some descriptions For 8 bit type nand flash the unit of ECC logic calculation is 512 bytes and the results can correct 1 bit error for each 256 bytes and determine two bit errors for each 256 bytes For 0 255 byte the error information is stored in 0x785E P_ECC_ERRO_LB For 256 511 byte the error information is stored in 0x785F P ECC ERR1 LB For 16 bit type NAND flash the unit of ECC logic calculation is 256 words or 512 words For 256 words the ECC result can correct 1 bit for low 256 bytes and high 256 bytes respectively and determine two bit errors for low 256 bytes and high 256 bytes respectively For 0 255 low byte the error information is stored in 0x785E P ECC ERRO LB For 0 255 high byte the error information is stored in 0x784E P ECC ERRO HB For 512 words the error information is described as follows For 0 255 low byte the error information is stored in 0x785E P ECC ERRO LB For 256 511 low byte the error information is stored in 0x785F P ECC ERR1 LB For the error information is stored in Ox784E P ECC ERRO HB P ECC ERR HB 0 255 high byte For 256 511 high byte the error information is stored in 0x784F Generalplus Technology Inc PAGE 246 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 17 6 Program Example 8 bit type Nand Flash with DMA mode F WriteNAND Byte r1 0x00aa P_NF_
44. DPO TRST TSOFI ITOK TXO VSC AOX AIX RX TX SOF DSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 esa resevas Generalplus Technology Inc PAGE 209 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Generalplus Technology Inc Device Plug Out Interrupt This interrupt is asserted whenever host has detected device is plug out Write 1 to clear the interrupt Transmit USB Reset Interrupt This interrupt is asserted whenever host has sent USB RESET signal Write 1 to clear the interrupt Transmit SOF Interrupt This interrupt is asserted whenever host has senta SOF Write 1 to clear the interrupt IN Token Transmit Interrupt This interrupt is asserted whenever host has sent an IN Token Write 1 to clear the interrupt Transmit Data Interrupt This interrupt is asserted whenever host has sent a DATA packet Write 1 ro dear the interrupt VBUS Status Change 1nterrupt This interrupt is asserted whenever VBUS Status has been changed Automatic Out Transfer Interrupt This interrupt is asserted when the host has transmitted the data out to the device or host has received an ACK from the device Automatic In Transfer Interrupt Receive Interrupt This interrupt is asserted whenever the host receives a packet form the device Write 1 to clear the interrupt Transmit Interrupt This interrupt is asserted whenever the transmitting task is
45. Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Et reton RER KAEST CC H ee R W Device Plug Out Timer Enable Write 1 to this bit to enable the timer E 1 DPOTV RAW 4 Device Plug Out Timer Value If DEVICE PLUG OUT TIMER ENABLE is 1 the inside timer is enabled For each clock cycle if D and D are all 0 the timer is added by 1 Besides if one of D D is not 0 the timer is reset to 0 When it counts to DEVICE PLUG OUT TIMER VALUE an interrupt is happened and DEVICE PLUG TIMER OUT ENABLE is reset Software Reset o srst Rw Software Reset P_USBH_INAckCount 0x7B17 USB IN ACK Count Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function INACK Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 212 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition usog mack om NACKComt OU P_USBH_OutAckCount 0x7B18 USB OUT ACK Count Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function OUTACK Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function type Description Condition pss ourack rw oUTACKCout S P_USBH_RSTAckCount 0x7B19 USB Reset ACK Count Register Bit 15
46. P_AD Driving 0x781F Address Data Driving Control Register Bit 15 14 13 12 1110191 18 716 5 4 3 2 1 0 Function D POFF D PH D SR D SMT D DRIVE I ASR A SMTH A DRIVE Default 0 0 0 0 o 0 0 1 0 O 0 0 0 0 0 1 Memory Control Register Summary Table Name Address Description P_MCSO_ Ctrl 0x7820 Chip Selection 0 Memory Device Control Register P_MCS1 Ct P MCS2 Cii P MCS3 Cii P MCS4 Ctr P EMUCS Cii P MCS Bus Se P MCS3 WkETimingCtrl MCS3 WE timing control register P MCS4 WETimingCtrl MCS4 WE timing control register P MCS3 RDTimingCtrl MCS3 RD timing control register P_MCS4 RDTimingCtrl MCSA RD timing control register P MCS3 TimingCtrl MCS3 CS timing control register P MCSA TiminaCtrl MCS4 CS timing control register P Mem Ctrl Memory Control Register P Addr Ctrl Memory A17 A25 Control Register Bank Switch Control Register P MCSO Ctrl 0x7820 CS0 Device Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CSOSIZE CSOMD WARWAT CSOWAIT Default O 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Generalplus Technology Inc PAGE 315 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide
47. P_ASADC_ Data D r3 r1 r1 P_ASADC Data D r3 r1 r1 P_ASADC_ Data D r3 r1 r1 P_ASADC Data D r3 r1 r1 P_ASADC Pata D r3 r1 r1 P ASADC Ctrl P ASADC _ Ctrl r1 L EndAutoSample pop r1 from sp reti 1 Clear auto sample FIFO empty flag Generalplus Technology Inc PAGE 233 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Touch Panel Interface Example X channel only F_TouchPanel_ISR PROC push r1 to sp ri P INT Status1 r1 r1 amp 0x4000 jz L EndTPSample II If AD convert ready r1 P_MADC_ Data get manual AD data R_Xvalue r1 store X value ri P MADC Ctrl L EndTPSample P_MADC_Ctrl r1 JI clear int flag pop r1 from sp retf ENDP L_TPNotTapped Note that Generalplus also provides complete source codes of touch panel and voice recording Programmers might contact Generalplus for corresponding executable files L Generalplus Technology Inc PAGE 234 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 17 1 17 2 17 3 17 NAND Flash Interface Introduction As a mass storage device NAND gate flash becomes more and more popular nowadays for its large capacity and relatively low price To extend GPL162002A 162003A5s application field a NAND flash interface is incorporated GPL162002A 162003A provides easy to use control registers to generate read w
48. Type Description Condition 15 12 Reserved p o cpr r Joe ECC Column parity register A P_ECC_LPR_CKL_HB 0x784B ECC High Byte Line parity Check LSB Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LPRCKL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 Generalplus Technology Inc LPRCKL R W The ECC Line parity Check register LSB PAGE 243 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P ECC LPR CKH HB 0x784C ECC High Byte Line parity Check MSB Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LPRCKH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 LPRCKH R W The ECC Line parity Check register MSB P_ECC_CPCKR_HB 0x784D ECC High Byte Column parity Check Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CPRCK Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 12 Reserved 11 0 CPRCK The ECC Column parity Check register Po P ECC ERRO HB 0x784E ECC High Byte Field 0 Error Flag Bit 15 14 13 12 11 104 9 87 16 1514 1312 1 0 Function 2ERR
49. a low level is continuously 1 Send Break Signal output on the TX output pin after completing the current character transmission This bit must be asserted for at least one complete frame transmission time in order to generate aybreak condition The transmitting FIFO contents remain ineffective during a break condition For normal usage this bit must be cleared to 0 P_UART_BaudRate 0x7903 UART Baud Rate Setup Register Bit 15 14 13 12 11 10 M9 8 Y 6 5 4 3 2 1 0 Function BUAD Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Functon Type gt Deepen Condition 15 0 BUAD UART Buad Rate control Ps The Buad rate system clock BUAD For example system clock is 48MHz and 115200 bps of UART buad rate is desired BUAD 48000000 115200 P_UARTIrDA Status 0x7904 UART IrDA Status Register Bit 15414 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RXIF TXIF RTIF TXEF RXFF TXFF RXEF BY DCD DSR CTS Default 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 Bit Function Type Deepen Condition 15 RXIF Receive Interrupt Flag If FIFO is enabled For FIFO is enabled 8 depth Read 0 no in RX FIFO lt 8 FEN 1 Read 1 no in RX FIFO gt 8 This bit is set to 1 by hardware if the If FIFO is disabled receiving interrupt enable bit is set to Read
50. 00 ROM SRAM 012 ROM SRAM 10 NOR Flash 11 NAND Flash WARWAT 1 0 SYSCLK Range 0 15 Tw CS2WAIT 3 0 1 SYSCLK V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P LL gt memory device access time SS P_MCS3 Ctrl 0x7823 CS3 Device Control Register Bit 151141131121 1 10 9 8 7 6 5 4 3 2 1 0 Function CS3SIZE CS3MD WARWAT CS3WAIT Default 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Bit Function Type Description Condition 15 8 CS3SIZE RAW Memory Device Size on Chip Select 3 CS3 Range 0 255 unit is 64K words CS3SIZE 7 0 1 defines Size CS3SIZE 7 0 1 the number of page for the entire memory 64Kword device on CS3 Page size is 64K word Size Range 64K word 16384K word 7 6 CS3MD RW CS3 Memory Device Access Mode 002 ROM SRAM To define which memory device on CS3 such 012 ROM SRAM as ROM SRAM NOR or NAND Flash 10 NOR Flash memories If NAND Flash is selected the 112 NAND Flash MCS3 pin will keep low until it is changed to other memory type 5 4 WARWAT RW SRAM Write after Read Wait State WARWATT 1 0 SYSCLK When data is written to memory and then read it immediately from the same address CPU will wait WARWAT 1 0 SYSCLK to read it 3 0 CS3WAIT RW S3 Memory Device Access Wait State Range 0 15 Setup Criterion Tw CS3WAIT 3 0 1
51. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LCDOFST Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P LCD Timing Ctrl 0x7987 LCD Control Signal Timing Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LBVL LPW LPCPD Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_LCD Frame Ctrl 0x7988 LCD Frame Modulation Control Register Bit 15 14 113 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BCMOD MVAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P LCD Palette Ctrl 0x7989 LCD Palette Control Register Bit 15 14 13 12 11 10 9 8 7 6 amp k4 3 2 1 0 Function OVIF C BPR BPP LCDBW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P LCD Attri Ctrl 0x798A LCD Attribute Control Register Bit 15 14 13 12 11 10 9 8 7 164 5 4 3 2 1 0 Function Stee zs VerINV HORINV DATAINV NEGFILE Default 0 0 0 DD 0 0 0 0 0 0 O 0 0 0 0 TFT LCD Control Register Summary Table Generalplus Technology Inc PAGE 332 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Generalplus Technology Inc PAGE 333 V1 0 Dec 20 2006 G Generalplus GPL16
52. ADCRIP TFTUFIP TFTFEIP UTIRIP SPIP FPIP TPIP ASPIP AUDBIP AUDAIP USBIP DMAIP EXTBIP EXTAIP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 63 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition 1 FIQ ADCRIP R W AD Conversion Ready interrupts priority IRQ1 Mala H Se This bit is invalid on GPL162003 1 FIQ This bit is invalid on GPL162003 1 FIQ 1 FIQ 1 FIQ BEE priority 1 FIQ NK aie ue oe 1 FIQ remm a 1 HOMERO e Reseved SD NN MERE M 1 FIQ Dour er ml 1 FIQ Bir e a 1 FIQ A A 1 FIQ A 1 FIQ Kleng le A 1 FIQ P_INT_Priority2 0x78A5 Interrupt Priority 2 Register Bit 15 14 13 12 11 10 9 8 7 6 5 412121110 Function TMDIP TMCIP TMBIP TMAIP KSIP SD 12C NAND Default 0 0 0 0 0 0 0 0 0 0 0 0 100 0 0 TMDIP R W TimerD up counter or capture or comparison event overflow interrupt priority Generalplus Technology Inc PAGE 64 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 0 TMCIP R W TimerC up counter or capture or comparison event overflow interrupt priority TMBIP R W TimerB up counter or capture or comparison event overflow interrupt priority TMAIP R W TimerA up counter or captu
53. ADLOV IEN LINEGL Default 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Function Description Condition ADLOVP HQADC Left Channel Line in or MICIN Read 0 Not Occurred Top overflow interrupt flag Read 1 Occurred This bit is set to 1 by hardware if Write 0 No effect HQADC left channel line in or MICIN Write 1 Clear the flag overflow occurs Programmers can use this register to determine the setting of LINEGL or PGAS When top overflow occurs programmers need to reduce LINEGL or PGAS 14 ADLOVN R W HQADC Left Channel line in or MICIN Read 0 Not Occurred Bottom overflow interrupt flag Read 1 Occurred This bit is set to 1 by hardware if Write O No effect HQADG eft channel line in or MICIN Write 1 Clear the flag bottom overflow occurs Programmers can use this register to determine the setting of LINEGL or PGAS When bottom overflow occurs programmers need to reduce LINEGL or PGAS 13 ADLOV IEN RW HQADC Left Channel Overflow Interrup 0 Disable Enable 17 Enable If this bit is set to 1 and at the time when ADLOV is set to 1 this hardware will issue an IRQ1 or FIQ to CPU To select between IRQ1 and FIQ please refer to Chapter Interrupt pzs JL Lpeseneg 4 0 LINEGL R W The gain setting of Left Channel Line in 00000 12 dB 00001 10 5 dB 00010 9 dB 00011 7 5 dB 00100 6 dB Generalplus Technology Inc PAGE 231 V1 0 Dec 20 2006 G General
54. Bars Insulating Spacers Bar Sliver In Mylar Sliver Ink dE Connector Transparent Resistive Conductor Indium tin oxide ITO Y Layer Connector In general a touch panel equivalent resistor is less than 1000 Ohms detailed specification of the touch panel transparent ITO conductors Typically please refer to the And some parasitic capacitance exists between two There are two basic modes for touch panel operation one is interrupt mode which has lower power consumption and the other is operatingymode used to probe be touch panel coordinate value x y Note that the time interval in operation mode should be as short as possible since power consumption is very large during operating mode Generalplus Technology Inc PAGE 216 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide The following two diagrams indicate equivalent circuitry of interrupt mode and operating mode Touch Panel Operation Mode TIER SW3 ADC TP Channel X TSPY swe gt P 1 5 ADC TP Channel Y Vtop l A l l SW2 1 NR en TSMX TSPX lt l lt l Vbottom e l A TSMY SW4 Y Vbottom Touch Panel Interrupt Mode VDD TSPY A Touch Panel Interrupt TPINT 50KOhm TSMX Be ISPX i Lo Debounce I SWO Circuit Touch Panel Status chmitt
55. Il 2 8 0 10 o i a VCC MEM AVCCDAC AVSSDAC AVCCADC AVSSADC Y VCC_33 0 3 amp M M Y Y Y Y yY C107 220u i5 L2 R31 L3 R33 R30 Bead T pape E BEAD 0Ohm BEAD 0Ohm BEAD x E 8 E E O Z Ol Z O ol 5 ol x gt gt 9 2 C104 C106 S VCC_50 0 1u au C103 cud e E AVCCSRUSSSPK 9 E C110 AVCCABESSADC 1 220u 220u VCC_18 0 of m R m H e O 1uF x 2 SE 9 nad C109 L4 L6 PW1 PW2 ui pep R38 sv l 3 3V 2204F 8 n x x E al N 8 5 9 2 al LF33 LF18 o 8 gt 7805 Q2 Q3 gt 6 Q1 x gt 1 No H GND H GND Ka gt gt z E E E C102 A d n Olu C101 i t 1693 8 R32 D11 2 2 1 2 2 220u bi dk DIODE e Ay X swe 2 JP64 JP65 JP66 sw 2PpT E gt Y pun SI E DIODE BRIDGE 2 Ay DCJACK Generalplus Technology Inc PAGE 391 V1 0 Dec 20 2006 A Generalplus GPL162002A 162003A Programming Guide M SDC JP67 JP68 IOC 0 15 HEADER 2 HEADER 2 IOC4 VCC_33 SDCWP 3K 10K SDCD1 SDC CMD SDCD3 RIK 20 SDCD2 4 10K R44 33 ou DN DN X VBus 5 R45 33 za C120 JP71 op gt gt DP X 0 1uF VCC_5X i gt oe vec_s ETS 3 C118 C121 HEADER 2 100pF 100pF USB_IN 2 JP70 USBDETECT VBus_5 1 BUSS R46 m PME Dp XN 68K B GAZE 8 5 4 L8 USB_B USBDETECT VBus 5 see OCDE HEADER 2 bead ES 0S 0 1uF KS gt
56. The further write to the full FIFO will overwrite the last written data in the FIFO V1 0 Dec 20 2006 G Generalplus Bit Function Type GPL162002A 162003A Programming Guide Description Condition 9 5 ASFIL R W Auto Sample Mode FIFO Full Interrupt Level The control bits are used to setup FIFO full defines the number of data left in interrupt timing It FIFO to be considered as full by hardware The smaller the value is the more often the FIFO empty interrupt occurs The larger the value is the less frequent the FIFO full Consequently it bandwidth interrupt happens saves CPU FIFO Full Interrupt issue timing 000007 when data no 000017 when data no 000107 when data no 000117 when data no 001007 when data no 001012 when data no 001107 when data no 001112 when data no 010007 when data no 010017 when data no 010102 when data no 010112 when data no 011007 when data no 01101 when data no 011105 when data no 011112 when data no in FIFO gt 0 in FIFO gt 1 in FIFO gt 2 in FIFO gt 3 in FIFO gt 4 in FIFO gt 5 in FIFO gt 6 in FIFO gt 7 in FIFO gt 8 in FIFO gt 9 in FIFO gt 10 in FIFO gt 11 in FIFO gt 12 in FIFO gt 13 in FIFO gt 14 in FIFO gt 15 10000 when data no in FIFO 16 10001 11111 Reserved 00000 0 data is in FIFO 00001 1 data is in FIFO 00010 2 data is in FIFO 00011 3 data is in FIFO 001
57. USB Device Register Summary Table Name Address Description P USBD Config 0x7B30 USB Configuration Register P_USBD_Device 0x7B57 USB Device Register P USBD Function 0x7B31 USB Function Register P_USBD_DMAINT 0x7B59 USB DMA Interrupt Register P_USBD_PMR 0x7B32 USB Power Management Register P USBD EPOData 0x7B33 USB Endpoint0 Data Register P_USBD_BiData USB Bulk In Data Register P_USBD_BOData USB Bulk Out Data Register P_USBD_INTINData USB Interrupt In Data Register P USBD NulPk P USBD EPEvent e USBD GLOINT P USBD INTEN P_USBD ANTE O Generalplus Technology Inc PAGE 344 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Name Address Description P USBD EPOVR 0x7B48 USB EndpointO wValue Register P USBD EPOIR Ox7B49 USB EndpointO windex Register P USBD EPOLR Ox7B4A USB EndpointO wLength Register USB Host Register Summary Table Name Description P USBH Config 0x7B00 USB Host Configuration Register P USBH TimeConfig USB Host Timing Configuration Register P USBH Data USB Host Data Register P USBH Transfer USB Host Transfer Register P USBH DveAddr USB Device Address Register P USBH DveEP USB Device Endpoint Register P USBH TXCount USB Host Transmit Count Register P USBH RXCount USB Receive Count Register P_USBH_FIFOInPointer USB Host FIFO Input Pointer Register P_USBH_FlFOOutPointer 0x7B09 USB Host FIFO Output Pointer Register P USBH AutolnByteCoun
58. Write 0 No Effect mode or NOT write OxAOOA to enter standby Write 1 Clear the flag mode this bit will be set o i by GPL 162002A 162003A and CPU will be reset Pap reserves LVR R W Low Voltage Reset Flag Read 0 Not Occurred If GPL162002 power is below designated Read 1 Occurred threshold voltage this flag will be set to 1 by Write 0 No Effect GPL162002A 162003A and CPU will be reset Write 1 Clear the flag The threshold voltage is defined in P LVR Ctrl Programmers can confirm which type of reset is activated by reading the corresponding bit Write O No Effect Generalplus Technology Inc PAGE 14 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 3 4 Clock Generation There are two crystal circuits built in GPL162002A 162003A which are for 32768Hz and 12MHz When the built in USB device host function GPL162002A 162003A is used it is recommended that a 12MHz crystal should be connected to GPL162002A 162003A to ensure that the error free 48MHz clock is generated If the USB function is not used users can choose to use 32768Hz crystal only The selection between these two configurations is via the IC pin BM2 If users pull high BM2 pin at start up the 12MHz and 32768Hz crystals will be used otherwise only the 32768 Hz crystal will be used The following table shows the difference between these two configurations
59. a o b shift 1 bit mode Right Channel Left Channel c left justified mode V1 0 Dec 20 2006 PAGE 95 Generalplus Technology Inc G Generalplus GPL162002A 162003A Programming Guide 10 6 Control Registers DAC Control Register Summary Table Name Address Description EQ Band Spectrum output P_CHA Ctrl 0x78F0 CHA DAC PWM Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function FEMIF C FEMIEN CHAEN SIGNED SRCEN SRCRST SRCFS Default 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 FEMIF C R W FIFO Empty Interrupt Flag Read 0 Not Occurred Write 1 to clear the flag Read 1 Occurred This bit is set to 1 by hardware if the FIFO Write 0 No effect empty interrupt is asserted CHAFEILV Write 1 Clear the flag defines the level that FIFO is considered as empty Generalplus Technology Inc PAGE 96 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide FEMIEN RW FIFO 14 FEMIEN RW FIFO Empty Interrupt enable Lt Geste Interrupt enable 0 Disable If this bit is set to 1 and FIFO empty interrupt 1 Enable occurs hardware will issue an IRQ0 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked To select between IRQ0
60. 0 this interrupt will be masked Set Configuration Interrupt Enable 07 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked Get Interface Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked Set Interface Interrupt Enable 07 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked Generalplus Technology Inc PAGE 195 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_USBD_SCINTF 0x7B3C USB Standard Command Interrupt Flag Register Bit 1514113 1121111 2 0 9 8 7 6 5 4 3 2 1 0 Function GSTS CFEA SFEA SADD GCON SCON GINT SINT Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 esal Rea NS II Generalplus Technology Inc R W Get Status Interrupt Flag The interrupt is set if the enable bit is 1 and GET_STATUS command happens Clear Feature Interrupt Flag The interrupt is set if the enable bit is 1 CLEAR_FEATURE happens and command Set Feature Interrupt Flag The interrupt is set if the enable bi
61. 1 Enabled overflow or capture or compare event interrupt happens hardware will issue an IRQ4 or FIQ to CPU If this bit is clear to 0 this interrupt will be masked To select between IRQ4 and FIQ please refer to Chapter Interrupt Generalplus Technology Inc PAGE 74 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide It should be noted the TimerE amp TimerF will not issue interrupt to CPU 13 TMXEN R W TimerX Enable 0 Disabled If this bit is set to 1 TimerX will start to 1 Enabled up count its 16 bit timer counter register according the frequency of a selected clock source If this bit is clear to 0 the TimerX will stop counting ml AA ES 11 10 EXTASEL R W External Input A IOD12 pre scalar 00 EXTA every falling 01 EXTA every rising These two bits are used to select the 10 EXTA every 4 risings pre scalar function between external 11 EXTA every 16 risings input signal and timer clock source EXTBSEL R W External Input B IOD13 pre scalar 00 EXTB every falling setup 01 EXTB every rising These two bits are used to select the 40 EXTB every 4 risings pre scalar function between external 11 EXTB every 16 risings input signal and timer clock source z Reserves L 6 4 SRCBSEL R W Clock Source Group B selection 000 2048Hz Note When TimebaseB or TimebaseA is 001 1024Hz SX the corresponding EEE enable 010
62. 1 Occurred interrupt is asserted For details refer to chapter UART IrDA interface SPIIF Serial Peripheral Interface SPI Interrupt status 0 Not Occurred This bit is set to 1 by hardware if the SPI 1 Occurred interrupt is asserted For details refer to chapter Serial Peripheral interface FPIF FP Interrupt status 0 Not Occurred This bit is set to 1 by hardware H the 1 Occurred LCD FP signal rising edge interrupt is asserted For detail refer to chapter LCD interface TPIF Touch Panel Stylus Tapped Interrupt status 0 Not Occurred This bit is set to 1 by hardware if the touch panel 1 Occurred interrupt is asserted For details referyto chapter Analog Input interface ASIF 0 Not Occurred 1 Occurred This bit is set to_ 1 by hardware if the Auto Sample FIFO Full included microphone channel interrupt is asserted For details refer to chapter Analog Input interface Reserved AUDBIF Audio Channel B FIFO Empty Interrupt status 0 Not Occurred This bit is set to 1 by hardware if the audio 1 Occurred channel B FIFO empty interrupt is asserted For details refer to chapter Audio Output interface AUDAIF Audio Channel A FIFO Empty Interrupt status 0 Not Occurred This bit is set to 1 by hardware if the audio 1 Occurred channel A FIFO empty interrupt is asserted For details refer to chapter Audio Output interface Ka Un bi wa NN For details refer
63. 1012 Selects LINEIN4 110 1112 Reserved P MADC Data 0x7962 Manual ADC Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function MADCDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Manual AD Conversion Data After Control bit CNVRDY is set ADC data will be valid on this register P ASADC Ctrl 0x7963 Auto Sample control register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ASIF C ASIEN ASFF ASFOV DMA OVER ASFIL FIFOLEV Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Type Description Condition ASIF C Generalplus Technology Inc Auto Sample Mode FIFO Full interrupt flag This bit is set to 1 by hardware if auto sample mode is enabled and the Auto FIFO Full channel Sample including microphone interrupt is asserted Note that this flag should be clear PAGE 224 Read 0 Not Occurred Read 1 Occurred Write 0 No Effect Write 1 Clear the flag V1 0 Dec 20 2006 G Generalplus Function Type GPL162002A 162003A Programming Guide Description Condition Generalplus Technology Inc after acquiring ADC data from auto sample FIFO Programmers cannot clear this bit BEFORE acquiring ADC data from the FIFO If DMA is set to 1 this bit will be clear as long as the data in the FIFO is lower than the trigger level Auto Sa
64. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PLLN Default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 HE fume Tm ee Reserved PLLN Fast PLL s output control 0000000 000011 reserved This register can be changed only when 0000100 12MHz System is not at FAST state This means 0000101 15MHz programmers need to switch PLL to slow 0000110 18MHz mode then can change PLL clock In other 0000111 21MHz words programmers must disable bit 15 of 0001000 24 MHz P Clock Ctrl 0x7807 first then change PLLN enable bit 15 of P Clock C and polling P State 0x780F for PLL stable 0100000 96MHz The PLL system clock equals to PLLN multiplied by three 3 5 System Reliability Control P LVR Ctrl 0x7808 Low Voltage Reset Control Register Bit 15 14 13 12 11 10 97 8 7 6 5 4 3 2 1 0 Function LVROFF Default 0 0 0 0 04 10 0 0 0 0 0 0 0 0 0 0 RE DE ch LVROFF R W Low Voltage Reset Off Selection 0 Enable This register is used to turn off the LVR reset 1 Disable when users do not wish to use the LVR function The LVR reset flag is still set when LVR is 1 LVR reset voltage 2 47 2 55V Ca Reseed P Watchdog Ctrl 0x780A Watchdog Reset Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 12
65. 2 4 The Differences between GPL162002A and GPL162003A eee 12 3 SYSTEM CONTROL A Wi 13 3 1 e AA E TE MES os E ZE 13 3 2 Device IdentificatiOn immenses SN M po ce 14 3 9 Reset el T N H A ene 14 34 Clock GeneratiO NEE Moo Nuus u tek T 15 3 5 System Reliability Control mm MN AMAR usines 18 3 0 Operation Mode Control NN ii e it 19 3 7 Special e RER Dg eeu cedi o loci 23 4 MEMORY ER CREER e sasssssssasassassssasssasssanassssssssawashassssssse 24 4 1 lite Te In EE WW p a A 24 42 FEATURE unie e Load D BEE 24 4 3 Memory Mappings ZC ASS NN A ie 24 4 4 Memory Access Big Vonfiguratiqfy LZ iii 29 45 Control Reobi e z Xe iii 29 4 6 BanjeabwaiengControl S JN ci cm 38 DNE uc A c EE 40 4 8 Stack Locate FA coccion nic trafic a 40 4 9 Chip Select Project Setting on IDE sise 40 4 10 Prog lu 41 5 befier 42 5 1 J vallable er EE 42 5 2 General Purpose I Os Configuration sise 47 5 3 General Purpose I Os Function Table sse eee sere eee 47 5 4 SAA eaaa e aaen eaaa i aa Eiraan E A E aaas r EE i Eia Eai 48 5 5 O structure diagraMs siennes 53 5 6 Special e 54 Sif Program Examples tn sis coasted eae gue erret o eR e eter dae eH p euet p seu nie line c ea de en ee 54 6 INTERRUP dui a 55 H Generalplus Technology Inc PAGE 3 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Progra
66. 256Hz bit should be set or else the timer will not count 011 TimeBaseB Note When external Input B 111 in binary 100 TimeBaseA is selected PortD13 is configured as counter 101 0 logic low glock source earn be GPIO function that 110 1 logic high IS am GPIO setting on PortD13 will be in vain 111 EXTB with Pre scalar 3 0 SRCASEL R W Clock Source Group A selection 0000 SYSCLK 2 Note Timer X 1 and TimerX form a 32 bit 0001 SYSCLK 256 counter and are configured as a cascada mode 0010 32768Hz when Timer X 1 overflow 0110 in binary is selected 0011 8192Hz Note When external Input A 0111 in 0100 4096Hz binary is selected 10D12 is configured as 0101 1 counter clock source It cannot be GPIO 0110 Timer X 1 Overflow function that is any GPIO setting on IOD12 will b in vain 0111 EXTA with Pre scaler 1000 0 1001 1111 Reserved Generalplus Technology Inc PAGE 75 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TimerA_CCP_Ctrl 0x78C1 TimerA CCP Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CCPAEN CAPASEL CMPASEL PWMASEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TimerB CCP Ctrl 0x78C9 TimerB CCP Control Register Bit 15 14 131 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CCPBEN CAPBSEL CMPBSEL PWMB
67. CS3WAIT 3 0 1 SYSCLK cycle SYSCLK gt memory device access time P MCSA Ctrl 0x7824 CS4 Device Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CS4SIZE CS4MD WARWAT CS4WAIT Default 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Bit Functon Type Description Condition 15 8 CS4SIZE R W Memory Device Size on Chip Select 4 CS4 Range 0 255 unit is 64K words CS4SIZE 7 0 1 defines Size CS4SIZE 7 0 1 64K the number of page for the entire memory word device on CS4 Page size is 64K word SizeRange 64K word 16384K word 7 6 CS4MD R W CS4 Memory Device Access Mode 00 ROM SRAM To define which memory device on CS4 01 ROM SRAM Generalplus Technology Inc PAGE 32 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide such as ROM SRAM NOR or NAND Flash 10 NOR Flash memories If NAND Flash is selected the 11 NAND Flash MCS4 pin will keep low until it is changed to 5 4 WARWAT R W SRAM Write after Read Wait State WARWATT 1 0 SYSCLK When data is written to memory and then read it immediately from the same address CPU will wait WARWAT 1 0 SYSCLK to read it 3 0 CS4WAIT R W CS4 Memory Device Access Wait State Range 0 15 Setup Criterion Tw CSAWAIT 3 0 1 CSAWAIT 3 0 1 SYSCLK cycle SYSCLK gt memory device access time
68. Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 369 V1 0 Dec 20 2006 G Generalplus E Fuse Register Summary Table Name Address GPL162002A 162003A Programming Guide Description P EFuse DO 0x7C30 E Fuse Data Register 0 P EFuse D1 0x7C31 E Fuse Data Register 1 P EFuse D2 0x7C32 E Fuse Data Register 2 P EFuse D3 0x7C33 E Fuse Data Register 3 Generalplus Technology Inc P EFuse DO 0x7C30 E Fuse Data Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function E DATA 15 0 Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P EFuse Di 0x7C31 E Fuse Data Register 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function E DATA 34 16 Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P EFuse D2 0x7C32 E Fuse Data Register 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function E DATA 47 32 Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P_EFuse_D3 0x7C33 E Fuse Data Register 3 Bit 15 14 1 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function E DATA 63 48 Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 L PAGE 370 V1 0 Dec 20 2006 G Generalplus GPL162002A 16200
69. EP1 Type endpoint1 ST This bit is used to indicate the EP4 is in or out Wibal ia This bit is used to indicate the EP3 is in or out This bit is used to indicate the EP2 is in or out Endpoint3 Type These two bits are used to indicate the type of endpoint3 Endpoint2 Type These two bits are used to indicate the type of endpoint2 A E Endpoint1 Type These two bits are used to indicate the type of 7 4 EP1 IO R W Endpoint1 IN OUT This bit is used to indicate the EP1 is in or out jpg Generalplus Technology Inc PAGE 183 00 Reserved 01 Reserved 10 Bulk 11 Interrupt 00 Reserved 01 Reserved 10 Bulk 11 Interrupt 00 Reserved 01 Reserved 10 Bulk 11 Interrupt 00 Reserved 01 Reserved 10 Bulk 11 Interrupt 0 OUT 1 IN 0 OUT 1 IN 0 OUT 1 IN 0 OUT 1 IN Reserved V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition 1 MODE RAW Mode selection 0 Normal mode 1 Debug mode P USBD Function 0x7B31 USB Function Register Bit 151141131121 11 10 9 8 7 615413121110 Function SRST DMA BOEN DMA BIEN Config Value FNC Addr Default 0 0 O0 O 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition rel Reeved NS 11 SRST W Software Reset
70. Function TMAIF C TMAIE TMAEN EXTASEL EXTBSEL SRCBSEL SRCASEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TimerB Ctrl 0x78C8 TimerB Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMBIF C TMBIE TMBEN EXTASEL EXTBSEL SRCBSEL SRCASEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerC_Ctrl 0x78D0 TimerC Control Register Bit 15 14 13 12 11 10 9 8 7 6N 5 4 3 2 1 0 Function TMCIF C TMCIE TMCEN EXTASEL EXTBSEL SRCBSEL SRCASEL Default 0 0 0 0 0 0 0 040 0 A 0 0 0 0 0 P_TimerD_Ctrl 0x78D8 TimerD Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMDIF C TMDIE TMDEN EXTASEL EXTBSEL SRCBSEL SRCASEL Default 0 0 0 Om 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerE_Cirl 0x79C0 TimerE Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMEIF C TMEIE TMEEN EXTASEL EXTBSEL SRCBSEL SRCASEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TimerF Ctrl 0x79C8 TimerF Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMFIF C TMFIE TMFEN EXTASEL EXTBSEL SRCBSEL SRCASEL Default 0 0 0 0 0 0 0 0 00 0 0 0 0 0 O P TimerA CCP Ctrl 0x78C1 TimerA CCP Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CCPAEN CAPASEL CMPASEL PWMASEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TimerB CCP Ctrl 0x78C9 TimerB CCP Control Register Bit 15 14
71. GPL162002A 162003A include three boot modes that described in MEMORY chapter The DIP switch 2 3 on S11 are to select among these three boot modes SW DIP 4 25 4 6 Memory There are six memory footprints on emulation board three for SRAM two for NOR flash memory and one for NAND flash memory Since GPL162002A 162003A has a built in 128KW mask ROM programmers can use external memory devices to simulate internal mask ROM By the switch SW4 users can select SRAM or NOR type flash memory to simulate internal mask ROM GPL162002A 162003Arallows the memory control signals CSO CS4 MA17 MA23 and OEB WEB to be set as GPIO When ProtD isfconfigured as GPIO Jumper J25 J26 J28 J29 J31 J32 J34 J35 J36 J37 J39 and J40 must be properly set up 25 4 7 Audio Output J2 and J3 are single channel phone jacks to external speakers On GPL162002A 162003A EMU board these two audio outputs are amplified by Generalplus OP ampliers known as GPY0030 Users can modify the gain of the amplifiers for CHA and CHB by simply changing the value of corresponding potential resistor R6 and R11 J4 is the stero phone jack for an external headphone In this situation GPL162002A 162003A drives the headphone directly 25 4 8 Analog Input JP2 is the header for touch panel interface with 4 bypass capacitors to ground Note that if touch panel Generalplus Technology Inc PAGE 376 V1 0 Dec 20 2006 G Generalplus GPL162
72. Generalplus Technology Inc PAGE 136 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function type Description Condition TFT_Hsync to last horizontal pixel See the following diagram for details P TFT HSYNC_SETUP 0x7D06 TFT Hsync Setup Register Bit 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 Function HS POL HS WIDTH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bt f uneton Tee HS_POL R W TFT Horizontal Synchronous Polarity 0 Negative Low pulse T Positive C e pulse 14 11 Reserved AND 10 0 HS WIDTH R W TFT Horizontal Pixel Width Horizontal nam width This register is to set the number of HS WIDTH 1 TFT CLK of horizontal pixel See the following diagram for details P TFT V WIDTH 0x7D07 TFT Vertical Width Bit 15 14 13 12 11 40 9 8 T 6 5 4 3 2 1 0 Function V_WIDTH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Le et us CT Reseed V WIDTH R W TFT Vertical Total line Total vertical line This register is to set the total vertical width of V_WIDTH 1 one frame See the following diagram for details P_TFT_V_START 0x7D08 TFT Vertical Start Location Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function gt Z 2 _ _ V_START
73. JAUDBIF AUDAIF USB DMA EXTBIF EXTAIF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition KEYIF RW I 4 i A Description Key change Interrupt status Write 1 to clear thesflag read P MINT Ctrl determine which key is changing Programmers need to to This bit isiset to 1 by hardware if the key change interrupt is asserted AD Conversion Ready Interrupt status This bit is set to 1 by hardware if the AD Conversion interrupt is asserted For details refer to chapter Analog Input interface TFT Under Flow Interrupt status This bit is set to 1 by hardware if the TFT under flow error interrupt is asserted For details refer to chapter TFT LCD interface This bit is invalid on GPL162003 TFT Frame End Interrupt status This bit is set to 1 by hardware if the TFT frame end interrupt is asserted For details refer to chapter TFT LCD interface This bit is invalid on GPL162003 Condition Read 0 Not Occurred Read 1 Occurred Write 0 No Effect Write 1 Clear the flag 0 Not Occurred 1 Occurred 0 Not Occurred 1 Occurred 0 Not Occurred 1 Occurred Generalplus Technology Inc PAGE 60 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide UTIRIF UARTIIrDA Interrupt status 0 Not Occurred This bit is set to 1 by hardware if the UART IrDA
74. JPEG Table in JPEG_Table obj with 0 Locate ICTest in ICTest obj at 27000 GPL162002A 162003A Programming Guide Locate JPEG Table in JPEG Table obt at 9000 Set Manually Align ICTest in ICTest obj with 0 Locate unSP_StartUp in startup all obj at FEOO Align unSP StartUp in startup all obj with O Locate MP3CODE ROM in MP3 ROM of MP3 HW KO0 1 0 2 P0040221 lib at 20000 Align MP3CODE_ROM in MP3 ROM of MP3 HW KO0 1 0 2 20060221 Nb with O sn section RES HAP1 ADP in HAP1 ADPres at 21000 sn section RES HAP1 ADP in HAP1_ADP res with 0 sn section RES HB ADP in HB ADP res after sn section RES HAP12ADP sn section RES HB ADP in HB ADP res with 0 sn section RES HBO ADP in HBQ_ADP res after sn section RES HB ADP sn section RES HBO ADP in HBQ ADP res with O This method is able to avoid the overlap of resources and programs when they are modified Generalplus Technology Inc PAGE 310 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 25 1 25 Appendix Normally used abbreviation list Although all abbreviation indicated here are uppercases lower cases are also accepted for naming flexibility However the first letter should be capitalized For example BUF Buf CHO Ch0 CLK CIK etc Abbreviation Description Address Buffer Character CHA CHB etc CHA CHB etc CLK Clock CMP
75. Option Link Section Redefine BreakPoint PreDownload Be 1 gt Sien Body SPL162002_RAMEMU ChpSelect Advanced J Head Files a E External Depen Probe auto Flash Type Ss 8 Emulator Default Timer B nmn mE Body Property Name Start Address End Address Download Type RAM 0x0 Ox fff Disable HO 0x7800 Ox7FFF Disable ROM 0x8000 Oxffef ROM Interrupt OXFFFO OXPFFFF ROM ROM 0x10000 Ox27FfF ROM Chip SelectO 0x30000 Ox4fFff Disable Chip Select1 0x50000 OxGFFFF ROM Chip Select2 0x70000 Ox FFFF ROM Chip Select3 0x80000 OXx8FFFF ROM Chip Select4 0x90000 Oxaffff ROM M 1 Body Select a body The linker and simulator are based on the body description to link and simulate 2 Emulator Select the external device emulator for selected IC the emulator is a DLL specified at CPT file of a corresponding body 3 Timer Set clock frequency of Simulator and Emulator 4 Configure Set emulator 5 Body property Show the memory mapping Generalplus Technology Inc PAGE 403 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Chip Select S memory files General Option Link Section Redefine Hardware BreakPoint PreDownload Be gt T kel Metier Body SPL162002_RAMEMU Chip Select Advanced memory rc Resource a Setting Chip Select Sy Head Files GPL162002 P_mcso_ctrl Port 0x7820 S memory h meal ie Memory Typ
76. P Hour 0x7922 Hour Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RTCHR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_Alarm_Second 0x7924 Alarm Second Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ALMSEC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_Alarm_Mintue 0x7925 Alarm Minute Register Bit 15 14 13 12 4 114 10 9 8 7 6 5 4 3 2 1 0 Function ALMMIN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_Alarm_Hour 0x7926 Alarm Hour Register Bit 15 14 134 124 11 10 9 8 7 6 5 4 3 2 1 0 Function gt ALMHR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_RTC_Ctrl 0x7934 HMS Alarm Schedule Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RTCEN ALMEN JHMSEN SCHEN SCHSEL Default 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_RTC_INT Status 0x7935 HMS Alarm Schedule Interrupt Flag amp Clear Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ALMIEF C SCHIF C HRIF C MINIF C SECIF C
77. P USBD BlData Ox7B34 USB Bulk In Data Register G Generalplus GPL162002A 162003A Programming Guide Name Address Description P_USBD_GLOINT 0x7B38 USB Global Interrupt Register P_USBD_SCI NTEN USB Host Register Summary Table Name Address Description P_USBH_Config 0x7B00 USB Host Configuration Register Generalplus Technology Inc PAGE 181 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Name Address Description P_USBH_AutolnByteCount Ox7BOA USB Host Automatic In Transaction Byte Count Register P USBH AutoOutByteCount 0x7B0B USB Host Automatic Out Transaction Byte Count Register P USBH AutoTrans Ox7BOC USB Host Auto Transfer Register P USBH Status Ox7BOD USB Host Status Register P USBH StorageRST 0x7B10 USB Storage Reset Register P_USBH_SoftRST 0x7B11 USB Software Reset Register Device Plug Out Register P_USBH_SOFTimer 0x7B12 USB SOF Timer Register P_USBH_FrameNum 0x7B13 USB Frame Number Register P_USBH_INTF 0x7BOE USB Host Interrupt Flag Register P_USBH_INTEN Ox7BOF USB Host Interrupt Enable Register USB D D Readback Register 15 6 USB Device Register Definition P USBD Config 0x7B30 USB Configuration Register Bit 15 141131121110 9181716 5 4 3 2 1 0 Function fe RWUPEN SPWR USBEN TNSPL TNSPH BYPASS Default Ov 0 O 0 0 0 0 0
78. Please refer to Chapter Interrupt Reseved _ O ipo Reserved P_TFT_H_WIDTH 0x7D03 TFT Horizontal Width Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function E H WIDTH Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description gt gt cona tion sra Reseed NSD 11 0 H WIDTH RAW TFT Horizontal Total Clock Width Total horizontal TFT CLK This register is to set the number of H WIDTH 1 TFT CLK of one line See the following diagram for details P TFT H START 0x7D04 TFT Horizontal Start Location Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function B b H_START Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rer OS Eee ooo o 10 0 H_START R W TFT Horizontal Display Start Location Horizontal start location This register is to set the number of H_START 1 TFT_CLK of TFT_Hsync to first horizontal pixel See the following diagram for details P TFT H END 0x7D05 TFT Horizontal End Location Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function H_END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sq Rea 11 0 H END R W TFT Horizontal Display End Location Horizontal end location This register is to set the number of TFT CLK of H_END 1
79. Read 1 Buffer Full bit will be clear after data had been read from the DATARx register or after writing 1 to StpCmd bitin P SD CMD RBufFu Response Buffer Full Head Uc Buffer Not Full Indicate the RESP register is full Reading Read 1 Buffer Full data from RESP register or initiating a new transaction or setting STPCMD in command 6 b111111 in the case of response R3 Write 1 Clear RidxE C R W Gommand Index in Response Error Read 0 Not error Indicate the command index in the response is Read 1 Error failed Write 0 No effect Write 1 Clear DCOMIC R W Data Complete Read 0 Not occurred Indicate data transmitting receiving is complete Read 1 Occurred Write 0 No effect Write 1 Clear CCOMIC R W Command Complete Read 0 Not occurred Indicate corresponding response is received or Read 1 Occurred a timeout happens after sending a command Write 0 No effect Write 1 Clear CBY SD Card Busy 0 Card is not Busy Indicate the SD card is busy drive the DATO 1 Card is Busy low Host needs to poll this bit after a Write dk command is issued Controller busy 0 Controller is idle Indicate the controller is busy 1 Controller is busy Generalplus Technology Inc PAGE 289 V1 0 Dec 20 2006 register will clear this bit M Response CRC Error Read 0 Not error Indicate the CRC bits inthe response are failed Read 1 Error This bi wll be set if the CRC received is not Write 0 No effect i i
80. Slow PLL Fast PLL 32768Hz gt 12MHz 12MHz gt 96MHz l o Not Active Active After enter Fast mode Available when Fast PLL is on Not Active Active After enter Fast mode The 32768Hz crystal must be connected to GPL162002A 162003A when USB device host function is used there will be two crystals connected to GPL162002A 162003A The 12MHz crystal is used to generate Fast PLL from 12MHz to 96MHz and 32768Hz crystal is used to trigger Real Time Clock unit and 32768Hz system clock when bit C32K mb Clock Ctrlis set to 1 After power on the system will run at 12MHz system clock P Clock Ctrl 0x7807 System Clock Control Register Bit 15 14 113 12 11 10 9 8171615 4 3 21110 Function FAST C32K WEAK C32KOFF KCEN DAPLLEN CLK96M CLKDIV Default 0 0 0 0 0 0 0 0000 0 0 000 Bit Function ng Description Condition 15 FAST R W Fast PLL Enable 0 Disabled 12MHz This control bit is used to enable internal 12 Enabled default 48MHz Fast PLL logic circuit 1 When C32K is set to 0 and this bit is set to 1 the Fast PLL will be enabled and generate 48 MHz clock 2 When C32K is set to 0 and this bit is set to 0 the Fast PLL will be disabled and the system clock is coming from external 12MHz Crystal when 12MHz crystal is used or Slow PLL from 32768Hz crystal to 12MHz PLL Generalplus Technology Inc PAGE 15 V
81. String TimerA TimerB etc Temporary Tone Universal Asynchronized Receiver Transmitter Volume Wakeup Watchdog Crystal oscillator 25 2 Control Register Mapping List by function 30KW SRAM System Control Memory Control 1 0 Port Control Interrupt Control Time Base Control Timer Control Audio Output Control UART IrDA Control RTC Control SPI Control Analog Control LCD Control Reserved Reserved Timer Control SD Card Interface Reserved LCD Color Palette USB Host USB Device 12C Interface DMA Control Key Scan Miscellaneous control Reserved Audio Output Control PAGE 312 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 700016 7C2F46 Reserved 703016 7C3F 16 E Fuse Register 7D0016 7D3F 16 TFT Control paie 7FFF y System Control Register Summary Table Name Address Description P BodyID 0x7800 Body Identification Number Register P CLK Chio P CLk Cui P Reset Flag P Clock Cm P LVR Cm P Watchdog Cin P Walchdog Clear P WAIT P Power State P PLN P_PLLWiatGLK P_AD Driving Address Data Driving control Register P_HALT 0x780D Halt Mode Entrance Register P_SLEEP 0x780E Sleep Mode entrance Rgister P BodyID 0x7800 Body ID Number Bit 15 1214 13 12 1 11 10 9 8 7 6 5 4 3 2 1 0 Function 0x8688 Default 1 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 P Reset Flag 0x7806 Re
82. The HQADC needs a 12 288MHz 1 Enable clock for the digital filter Before enabling the HQADC programmers must first enable DAPLL 0x7807 b4 and wait PLL stable and then set this bit to 1 to initiate HQADC clock P HQADC PGAS 0x7971 High Quality ADC MICIN pre gain setting Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PGAS Default 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 Bit Function Type Description Condition 15 5 Reserved 4 0 PGAS R W The gain setting of MICIN PGA 00000 33 dB 00001 31 5 dB 00010 30 dB 00011 28 5 dB 00100 27 dB Generalplus Technology Inc PAGE 229 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Type Description Condition decrease 1 5dB on each level 11101 10 5 dB 11110 12 dB 11111 oo dB mute P_HQADC_RGAIN 0x7972 High Quality ADC LINEINR gain setting Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ADROVP ADROVN ADROV IEN LINEGR Default 0 0 0 00000 0 0 0 0 1 0 0 0 Function Type Description Condition ADROVP RW HQADC Right Channel Line in Top L Read 0 Not Occurred Overflow interrupt flag Read 1 Occurred This bit is set to 1 by hardware if HQADC Write 0 No effect right channel line in top overflow occur
83. before Attribution bit to be 1 produces an unexpected short pulse However setting the Attribution bit to 1 before the Direction bit will not have the additional pulse 5 7 Program Examples R1 OxFOFO Il OA 3 0 are input with pull low resistor IP IOA Data R1 Il OA 7 4 are input with pull high resistor R1 OxFFOO J 10A 15 8 are all floating P IOA Attrib R1 R1 0x0000 P IOA Dir R1 R1 OxFOFO OC 3 0 are output buffer high PMOS driven P IOC Data R1 11 10C 7 4 are output buffer low NMOS driven R1 OxFFOO INOC 11 8 are output buffer low NMOS driven P_lOC_Attrib R1 IOC 15 12 are output buffer high PMOS driven R1 OxFFFF P OC Dir R1 Generalplus Technology Inc PAGE 54 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 6 1 6 Interrupt Introduction GPL 162002A 162003A provides many interrupt sources which can also be wake up sources In other words after system enters wait halt or sleep mode an interrupt event will wake CPU up For interrupt and wake up capability from different modes please refer to following table Interrupt Wakeup Capability Table for each mode PortB 2 0 key change wakeup_ o OY w ExTAwakeup_ o j o IO EXBwaep ON o DMA Transfer Complete Interrupt 0717 USB Imterrupt ef 12C TransmitReceive Interrupt O Y NAND Flash FIFO overlunder flow interrupt o
84. gt gt gt Aen L Lav zi Ger 61v E Ei gt 81v LESA i aly Las av ity PL 8IVW_ 8 PARTIE Av LE ory CZYN s ory CHE LLYN ary CHE LVA sid sty 8 SEI sha pw LE Sen sid stw Er Sen San S piy SRN SION pide ly er Sen SION la piy Lee StvW ELO tv ela ew Z viVIN ELO ela Eu IT vi pion ZE ela ely ZZ iV eLan DEI zua ziv D giya ELQW za dv Sev LOW ziq ziy Z ELVN zion tig i D t cw Pist ua Ww Sen aan iia LL ZW LION 3 Jota oi LS LI LION oa ore LIYN LION ZE log ov LEE LS ON YE e gy 2 OlWW OLAN ed ev LEZEOLYW DON Elea ag DECH SO ZE Z Sun SO Sen SOW E Sen go e sa gw sa gw Ban DE a Jv 8 Ge san 4a Aw Dr BOW 6c 1a Hi SI zan log a EL YW Lan sa aw LY OR loq sv LWW San ZE 6L OVW SOW EI San SL EI sa s sa s sa s SOW vg py LE SYN SON ra Sen san leg ww SYN tan jea gy Z Sei taw ea ev TAIN tan t lea gy TIN ean SE za zy LEE ev EAN za V EVA EAN E zv EVA Om EE La n c ZYN ZAN a LY ZYN ZON 6 ta LY ZYN LOW 316 oq ov 36 Yn LAN oa OV LYN tan Slog ov LY oan 62 SZ OVN DEI OWN oan T OWN V1 0 Dec 20 2006 PAGE 389 Generalplus Technology Inc A Generalplus GPL162002A 162003A Programming Guide K Nand Flash
85. pos Reseed 00 0 84 full range 01 0 71 full range 10 0 60 full range 11 0 50 full range 0 Disable 1 Enable 000 Record in 48KHz sample rate 001 Record in 24KHz sample rate 010 Record in 16KHz sample rate 011 Record in 12KHz sample rate 100 Record in 9 6KHz sample rate 101 Record in 8KHz sample rate 110 Record in 6 9KHz sample rate 111 Record in 6KHz sample rate 0 Stero mode 1 Mono mode only left channel will V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Type Description Condition or stero mode of recording If stero be recorded mode is selected then at each sampling time the left and right channel data will be sent to FIFO If mono mode is selected then at each sampling time only left channel data will be sent to FIFO BOOST R W Internal Boost Amplifier Control 0 Disable boost amplifier 1 Enable boost amplifier 5 4 INMODE RW HQADC Input Source Select 00 MIC in There are three input sources on 01 Line in GPL162002A 162003A MIC LINE 10 FM in and FM These bits are to select the 11 All off input source Control 1 Power down Control 1 Power down 1 MICBIAS R W HQADC Microphone Bias Voltage 0 Bias voltage power on Output Power Control 17 bias voltage power down This bit is usef l only when INMODE is selected to MIC channel ADMCLK R W HQADC Main Clock Enable 0 Disable
86. status register P_UART_RXStatus is updated only when a read operation is performed on P_UARTIrDA_Data control register P_UARTIrDA Ctrl 0x7902 UART IrDA Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RXIE TXIE RTIE JUEN MSIE SLT WLSEL FEN SBSEL PSEL PEN SB Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O Bit Function Type Description Condition 15 RXIE R W Receive Interrupt Enable 0 Disabled For FIFO is enabled 8 depth FEN 1 1 Enabled If this bit is set to 1 and the data number in receiving FIFO is more or equal to 8 hardware will issue an IRQ3 or FIQ to CPU For FIFO is disable 1 depth FEN 0 If this bit is set to T and the receiving buffer is just held one new coming data hardware will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this receiving interrupt will be masked To select between IRQ3 and FIQ please refer to Chapter Interrupt TXIE Transmit Interrupt Enable 0 Disabled For FIFO is enabled 8 depth FEN 1 1 Enabled If this bit is set to 1 and the data number in transmitting FIFO is less or equal to 1 hardware will issue an IRQ3 or FIQ to CPU For FIFO is disable 1 depth FEN 0 If this bit is set to 1 and the transmitting buffer is empty hardware will issue an IRQ3 or FIQ to CPU If this bit is cleared to O this transmittin
87. test r1 C INT TimerD jz L_EndIRQ4 r1 P_TimerD_ Ctrl P TimerD Ctrl r1 ri P KS Ctrl test r1 0x0100 jnz L EndIRQ4 r1 0x0200 Il Write one to start a key scan process P_KS_Ctrl r1 L_EndIRQ4 pop r1 from sp reti L Generalplus Technology Inc PAGE 304 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 22 Miscellaneous 22 1 Introduction For facilitating programming GPL162002A 162003A offers bit nibble and byte swap operations It can save CPU resource on these operations 22 2 Specified Register Miscellaneous Register Summary Table Name Address Description P Byte Swap Ox7BDO Byte Swap P Nibble Swap Ox7BD1 Nibble Swap P TwoBit Swap Ox7BD2 Two Bit Swap P Bit Reverse 0x7BD3 Bit Reverse P_Byte_Swap Ox7BDO Byte Swap Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b4 bO Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 BYTESWAP R W Byte Swap Write B15 BO to this control register and then read this control register to obtain B7 BO B15 B8 P Nibble Swa 0x7BD1 Nibble Swap Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L Bi Function Type Description
88. 0 Bank W Bank Number Register When these bits are set to 0x01 Physical address 0x200000 0x3FFFF will be mapped to 0x20000 0x3FFFFF When these bits are set to 0x02 Physical address 0x400000 0x5FFFF will be mapped to 0x20000 0x3FFFFF And so on When BM 1 0 is set to 2b 00 the external MCSO boot mode is selected The mapping size of external boot area can be changed by setting P MAPSEL register P MAPSEL 0x7816 CS0 boot mapping size select register Bit 15 14 13 12 11 1 30 9 8 1 6 5 4 3 2 1 0 Function MAPSEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Funcion Type Gesopten Condition Ipss Reseved RR Reserved OOOO 2 0 MAPSEL W CSO boot map size register 000 2K 0xF800 0xFFFF is mapping to When programmers use MCSO Ox3F800 0x3FFFF boot mode Generalplus 001 4K 0xF000 0xFFFF is mapping to suggests programmers set this Ox3F000 0x3FFFF register immediately after CPU 6K OxE800 0xFFFF is mapping to starts to run Ox3E800 0x3FFFF 8K OxEO00 0xFFFF is mapping to Ox3E000 0x3FFFF 10K 0xD800 0xFFFF is mapping to Ox3D800 0x3FFFF 12K 0xD000 0xFFFF is mapping to 0x3D000 0x3FFFF 16K 0xC000 0xFFFF is mapping to 0x3C000 0x3FFFF 32K 0x8000 0xFFFF is mapping to 0x38000 0x3FFFF Generalplus Technology Inc PAGE 39 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 4 7 Vectors Interrupt Vector Address Ox00FFF
89. 0 Disable and interrupt occurs hardware will issue an IRQ3 or 1 Enable FIQ to CPU If this bit is cleared to 0 this interrupt will be masked Generalplus Technology Inc PAGE 191 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition BOPS Bulk Out Packet Set Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to O this interrupt will be masked BINA Bulk In NACK Interrupt Enable 0 Disable i i i i EOSC R W to 0 this interrupt will be masked EOINNA R W EPO In NACK Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable Will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to O this interrupt will be masked Bulk In Packet Clear Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bitis cleared to 0 this interrupt will be masked EPO Status NACK Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared
90. 0 0 0 P KS Datai 0x7BC9 Sample Data of Line IOA 1 Bit 15 14 18 42 11 10 9 8 7 6 5 4 3 2 1 0 Function gt Data1 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P KS Data Ox7BCA Sample Data of Line IOA 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data2 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P KS Data3 Ox7BCB Sample Data of Line IOA 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data3 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P KS Data Ox7BCC Sample Data of Line IOA 4 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data4 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 368 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_KS Data5 0x7BCD Sample Data of Line IOA 5 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data5 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P KS Data6 Ox7BCE Sample Data of Line IOA 6 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data6
91. 0 0 0 0 0 P DMA TAR AddrL1 0x7B8A DMA Target Low Address Register 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 271 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_DMA_TAR_AddrL2 0x7B92 DMA Target Low Address Register 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR_Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_TAR_AddrL3 0x7B9A DMA Target Low Address Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Type Description Condition TAR Addr R W DMA Target Low Address 15 0 These P DMA TAR Addrlx registers are low address 15 0 registers of targets The value in these registers will be increased decreased when a word is written and when the DF nP DMA Ctrl 6 is O It should be noted if the TD in P DMA Ctrl 11 10 is set to memory to IO or IO to IO mode only the lower 12 bits will be used to issue a peripheral write P DMA TCountLO 0x7B83 DMA Terminal Count Low Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
92. 0 0 0 0 0 P ECC LPRL LB 0x7858 ECC Low Byte Line parity LSB Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LPRL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P ECC LPRH LB 0x7859 ECC Low Byte Line parity MSB Register Bit 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 Function LPRH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P ECC CPR LB 0x785A ECC Low Byte Column parity Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CPR Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P ECC LPR CKL LB 0x785B ECC Low Byte Line parity Check LSB Register Bit 15 4 14 134 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LPRCKL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P ECC LPR CKH LB 0x785C ECC Low Byte Line parity Check MSB Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LPRCKH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P ECC CPCKR LB 0x785D ECC Low Byte Column parity Check Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CPRCK Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 356 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide
93. 0 0 0 0 0 0 0 P TFT PIP2 STARTAH 0x7D2D TFT PIP2 Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2 SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 STARTAH 0x7D38 TFT PIP3 Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP3 SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 el Reserved e 32 10 0 PIP _SAH R W PIP Frame Buffer Start High Address This register set up TFT PIP LCD buffer address P TFT PIPO STARTAL 0x7D18 TFT PIPO Frame Buffer Start Low Address Bit 15 14 1371 12 1411 10 149 8 7 6 5 4 3 2 1 0 Function PIPO SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP1 STARTAL 0x7D23 TFT PIP1 Frame Buffer Start Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1 SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP2_STARTAL 0x7D2E TFT PIP2 Frame Buffer Start Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2 SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP3_STARTAL 0x7D39 TFT PIP3 Frame Buffer
94. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description condition 15 0 CHECKSUMO LB NAND Flash low byte 0 255 bytes check sum value P P_CHECKSUM1_LB 0x7831 NAND Flash Low Byte Check Sum High Value Bit 15 14 13 122 11 10 9 8 7 6 5 4 3 2 1 0 Function CHECKSUM1_LB Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 CHEGKSUM1_LB NAND Flash low byte 256 511 bytes check sum value EM P CHECKSUMO HB 0x7832 NAND Flash High Byte Check Sum Low Value Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CHECKSUMO HB Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 CHECKSUMO HB R W NAND Flash High byte 0 255 bytes check sum value This register is valid only when NAND flash is set to 16 bit mode Generalplus Technology Inc PAGE 245 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_CHECKSUM1_HB 0x7833 NAND Flash High Byte Check Sum High Value Bit 15 114 113 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CHECKSUM1_HB Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 17 5 15 0 CHECKS R W NAND Flash High byte 256 511 bytes check sum value UM1_HB This register is valid only when NAND flash set to 16 bit mode Special Note
95. 0x1 DAC CHA 0x2 UART TX 0x3 UART RX 0x4 SD MMC 0x5 NAND Flash 0x6 Serial Interface 0x7 DAC CHB 0x8 ADC Auto Sample Full 0x9 SPI TX OxA SPI RX Other Reserved 11 8 DMA SS2 R W DMA Channel 2 Source Select R W 0x0 USB 0x1 DAC CHA 0x2 UART TX 0x3 UART RX 0x4 SD MMC 0x5 NAND Flash 0x6 Serial Interface 0x7 DAC CHB Generalplus Technology Inc PAGE 278 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Description Condition 0x8 ADC Auto Sample Full 0x9 SPI TX OxA SPI RX Other Reserved 7 4 DMA_SS1 R W DMA Channel 1 Source Select R W 0x0 USB 0x1 DAC CHA 0x2 UART TX 0x3 UART RX 0x4 SD MMC 0x5 NAND Flash 0x6 Serial Interface 0x7 DAC CHB 0x8 ADC Auto Sample Full 0x9 SPhTX OxA SPLRX Other Reserved 3 0 DMA SSO R W DMA Channel 0 Source Select R W 0x0 USB 0x1 DAC CHA 0x2 UART TX 0x3 UART RX 0x4 SD MMC 0x5 NAND Flash 0x6 Serial Interface 0x7 DAC CHB 0x8 ADC Auto Sample Full 0x9 SPI TX OxA SPI RX Other Reserved Each DMA channel has its own DMA request and DMA acknowledge signal These signals do not have to be connected to specific peripherals In other words a DMA channel could receive a DMA request signal determined by setting P_DMA_SS register P_DMA_INT Ox7BBF DMA Interrupt Register Bit 1511413112 11 10 9 8 7 6 5 4 3 2 1 0 Function
96. 1 and MONO is set to stero mode sequence of data to CHA FIFO As a the odd data will be sent to and then write a result channelA and the even data will be sent to channelB over and over automatically by hardware Read 0 Not Occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag 0 Disabled 1 Enabled 0 Disabled 1 Enabled 0 Not used 1 The same service frequency with CHA 0 Use CHB s configuration 1 Use CHAS configuration 0 Stereo 1 Monochrome Generalplus Technology Inc PAGE 99 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Cond iton If MONO is set to Monochrome mode the writen voice data head to CHA FIFO and CHB FIFO respectively bog JL reee lo P CHB Data 0x78F9 CHB DAC PWM Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CHBDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description _ _ A gt condition 15 0 CHBDATA Channel B Data Register ki P_CHB_FIFO 0x78FA CHB FIFO Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function FFUL FUDN ARST CHBFEILV CHBFINX Default 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Function Type Description Condition 15 FF
97. 1 start software reset Write 1 to start USB software reset and 10 stop software reset programmer must write O to stop USB software reset 10 DMA BOEN R W DMA Bulk OUT Enable Write 02 Diable DMA Write 1 to this bit to enable the DMA function with bulk out function with bulk out When this bit is Write 12 Enable DMA set to 1 the DMA DIEN must be O It function with bulk out indicates Bulk IN must be disabled when Bulk out is enabled in DMA mode When DMA is finished this bit will be automatically cleared to 0 DMA BIEN RW DMA Bulk IN Enable Write 0 Diable DMA Write 1 to this bit to enable the DMA function with bulk in function with bulk in When this bit is Write 1 Enable DMA set to 1 the DMA_BOEN must be 0 function with bulk in It indicats Bulk OUT must be disabled when Bulk in is enabled in DMA mode When DMA is finished this bit will be automatically cleared 8 7 Config Value Configure Value The USB configuration value of the device can be read from these two bits when receiving a configuration command FNC_Addr Function Address When the device gets Set Address command from the host the address is stored in these bits Generalplus Technology Inc PAGE 184 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_USBD_DMAINT 0x7B59 USB DMA Interrupt Register Bit 15 14 13 12 11 10 9
98. 1 data is in FIFO 0010 2 data is in FIFO 0011 3 data is in FIFO 1110 14 data is in FIFO 1111 15 data is in FIFO P DAC Ctrl 0x78FD DAC Control Register Bit 1511411312 11 10 918 7 6 5 4 3 2 1 0 Function BPFIR AS S SP DLY AS CYCLE AS RANGE PWDAL PWDAR IIS DACLK Default 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 Bit Function Type Description Condition 54 reams VA 0 11 BPFIR R W Bypass DAC Digital Filter 07 Not bypass This control bit is to set whether audio data 1 Bypass bypass lhe internal digital filter 10 AS S R W A to Sleep Function Input Source Select 0 IIS output This control bit is to select input sources of 1 Digital filter output auto sleep function which is either from IIS channel directly or from IIS channel then through digital filter SP DLY RW Time Delay Between DAC and Heapphone 00 1440 DALRC These control bits are to set delay time 01 2880 DALRC between DAC and headphone driver when 10 4320 DALRC DAC is ON OFF This is to avoid bo 11 9 60 DALRC sound when turning ON OFF DAC function Note DAE OE For ON procedure turn on DAC first then headphone driver circuitry for OFF procedure turn off DAC after headphone driver circuitry 7 6 AS CYCLE R W Auto Sleep Start up Time 00 8192 DALRC When auto sleep condition exists hardware 01 16384 DALRC will turn
99. 11 10 9 8 7 6 5 4 3 2 1 0 Function TMAUCR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerB_UpCount 0x78CC TimerB Up Count Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMBUCR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerC_UpCount 0x78D4 TimerC Up Count Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMCUCR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerD_UpCount 0x78DC TimerD Up Count Bit 15 14 134 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMDUCR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TimerE UpCount 0x79C4 TimerE Up Count Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMEUCR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerF_UpCount 0x79CC TimerF Up Count Bit 15 14 M3 12 11 10 8 7 6 5 4 2 1 0 Function TMFUCR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 324 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Timebase Control Register Summary Table P TimeBaseA Ctrl 0x78B0 TimeBaseA Control Register P TimeBaseB Ctrl 0x78B1 TimeBaseB Control Register P_TimeBaseC Ctrl 0x7 8B2 TimeBaseC Control Register P TimeBase Reset 0x78B8 TimeBase Counter Reset Register P TimeBaseA
100. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PLLN Default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 P LVR Ctrl 0x7808 Low Voltage Reset Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LVROFF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P Watchdog Ctrl 0x780A Watchdog Reset Control Register Bit 15 14 134 12 111110 9 8 7 6 5 41 3 2 1 0 Function WDGEN WDGS WDGPD Default 0 0 0 0 0 0 0 0 0 0 0 O 0 0 O 0 P Watchdog Clear 0X780B Watchdog Clear Register Bit 15 14 134 12 11 10 9 8 7 6 5 4 3 2 1 0 Function WDGC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_WAIT 0x780C Wait Mode Entrance Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function WAIT Default 0 0 0 0 0 0 0 0 0 0 0 P_HALT 0x780D Halt Mode Entrance Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function HALT Default Generalplus Technology Inc PAGE 314 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_Sleep 0x780E Sleep Mode Entrance Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SLEEP Default P_State 0x780F Power State Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function State Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
101. 14 13 12 11 10 7 6 5 4 3 2 1 0 Function WEB4NUM Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 316 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_MCS3_RDTimingCirl 0x7829 MCS3 RD timing control register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RDB3NUM Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_MCS4_RDTimingCirl 0x782A MCS4 RD timing control register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RDB4NUM Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P MCS3 TimingCtrl 0x782B MCS3 CS timing control register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CSB3NUM Init 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 P_MCS4_TimingCtrl 0x782C MCSA CS timing control register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CSB4NUM Init 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 P Mem Ctrl 0x7840 Memory Control Register Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function WE RD MCS4 MCS3 MCS2 MCS
102. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function REQF C DMAEN INTEN ADR4EN ADR3EN ADR2EN 1 1 1 Init 0 0 0 1 0 1 1 00000000 0 Function Type Description Condition REQF C RAN 14 DMAEN RW 13 INTEN RW Generalplus Technology Inc NAND FlashAccess Request Flag Write 1 to clear the flag This bit is set to 1 by hardware after the CLE When NAND flash is ready to Read Write the Request flag is asserted Clear it to 0 after Reading Writing NAND Flash memory through port 0x7854 NAND Flash DMA Access Enable If this bit is set to 1 and if NAND Flash Access Request occurs hardware will issue a DMA and ALE commands request to DMA controller If this bit is cleared to 0 this request will be masked When Nand Flash DMA is enabled programmers should set DMA mode as software mode or external demand mode DMA for details NAND Flash Access Interrupt Enable If this bit is set to 1 and if NAND Flash Access Request occurs hardware will issue an IRQ5 or Please refer to Chapter PAGE 238 Read 0 Not Occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag 0 Disable 1 Enable 0 Disable 1 Enable V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 17 4 Function Type Description Condition FIQ to CPU If this bit is cleared to 0 this interrupt will be ma
103. 16 bit type by switching SW5 to select which type is used When Nand Flash interface is used users should turn on the DIP switch S13 which interconnects GPL162002A 162003A and PortB socket referenced as JP9 JP10 JP19 and JP20 labeled with JOB JP73 2 is connected to NAND flash WP pin and JP73 1 is connected to VCC Shorting these two pins will disable NAND flash WP JP62 2 is connected to NAND flash CE pin and JP62 1 is connected to MCS3 Shorting these bins will configure MCS3 as NAND type flash In addition for example if users want to configure MCS2 as NAND type flash JP62 2 and MCS2 pin of GPL162002A 162003A should be physically connected Key Scan Interface When key scan function shares PortA with LCD panel each output must connect a diode serially to the key pads to prevent the LCD glitch caused when multi keys are pressed Users can turn on DIP switches S15 and S10 to achieve this goal On board LED indicator Header Referenced as JP16 This LED array is for general purposed indicator s and connecting any one pin on JP16 to high voltage will turn on corresponding LED NENNEN Generalplus Technology Inc PAGE 379 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 8 7 E LED 10 ZW L D1 5 L 10 9 U L 6 5 3 LED 10 Ww d D1 4 s e O O O O LED10 ve s L D1 6 e 12 11 O I OO Q B OO N co J O O1 R N A Ee LA HEADER 8 On board
104. 162003A Programming Guide 16 4 Step 13 Turn off ADC Step 14 Turn back to touch panel interrupt mode In the application that power consumption is not a big issue programmers might not turn ADC on and off frequently as previous description Instead Programmers can turn on ADC while system powers on and turn off ADC when system goes into standby mode As the programming example provides touch panel Interrupt service routine in this case programmers can hook this ISR on a 128Hz or 256Hz Interrupt vector Voice Recorder HQADC operates mode GPL162002A 162003A provides a high quality ADC for voice recording After ADMCEK EN is 1 and PWADL PWADR is turned on the HQADC will start to record the voice depending on the LINEINS settings The operation current is around 10 15 mA The record sample rate is fixed to 48 KHz If programmers want to decrease the sample rate use DIV REC record register to control the hardware FIFO Monophonic and stero recording functions can be selected on GPL162002A 162003A In monophonic record mode only left channel will be record At each AD sample time one ADC data is generated In stero record mode left and right channels are used At each AD sample time there are two ADC data generated Then programmers need to get P ASADC Data 0x7964 twics the first data is from left channel and second data is from right channel input The procedure o turn on HQADC is enable ADC clock 0x7807 b4
105. 17 17 15 8 2 8 18 JAZZ 18 16 14 1 16 18 17 POP 12 18 4 12 18 12 8 LIVE 10 9 2 3D Control Method Filter Coefficient Register Mapping Address 7 10 14 17 18 10 7 Definition Ox000 0x0FF HRTF Filter Coefficient 0x100 0x1FF 10 10 Program Examples r1 0x8410 P_Clock_Ctrl r1 r1 0x8200 CSS Filter Coefficient JI Setup PLL Frequency as 48MHz enable AD DA clock source Generalplus Technology Inc PAGE 110 V1 0 Dec 20 2006 G Generalplus iS y al _IRQO CHA P_CHA_Ctri r1 r1 0x0120 P_CHA_FIFO r1 r1 0x9000 P_CHB_Ctrl r1 r1 0x0120 P_CHB_FIFO r1 r1 P_CHA_ Ctrl r1 0x03 P CHA Ctrl r1 R1 0x01 P_DAC_Ctrl r1 R1 0x00 P_HPAMP_Ctrl r1 R1 0x01 P_DAC_IIS_Ctrl r1 r1 P CHA Ctrl r1 0x6400 P CHA cimier M LP_CHB Ctrl r1 0x2000 P_CHByCtrl r1 push r1 to sp r1 P_INT_Status1 test r1 INT AudioA jz CHB r1 P_CHA Ctrl P_CHA_Ctrl r1 ReadResourceData_A P_CHA_Data r1 GPL162002A 162003A Programming Guide Clear CHA FIFO interrupt flag reset SRC controller J Set CHA FIFO empty interrupt level Clear CHB FIFO interrupt flag set the same sample rate with CHA Set CHB as Stereo mode Set CHB FIFO empty interrupt level Setup sample rate Overflow Frequency Il as 22 05KHz llenable DAC clock R L channel power
106. 2006 G Generalplus GPL162002A 162003A Programming Guide P CHB Cm 0x78F8 CHB DAC PWM Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function FEMIF C FEMIEN CHBEN SSF CHACFG MONO Default 1 0 0 0 0 0 0000000000 Bit Function Type Description Condition 15 FEMIF C R W FIFO Empty Interrupt Flag Write 1 to clear the flag This bit is set to 1 by hardware if the FIFO empty interrupt is asserted CHBFEILV defines the level that FIFO is considered as empty FEMIEN RW FIFO Empty Interrupt enable If this bit is set to 1 and if FIFO empty interrupt occurs hardware will issue an IRQO or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked To select between IRQO and FIQ please refer to Chapter Interrupt mE e T R W CHB service frequency If users enable channel B this bit must And then the CHB will have the same sample rate with CHA CHACFG R W CHB uses CHAS configuration When CHA and CHB have the same service frequency SSF 1 if CHACFG is set to high the CHB will use CHAS configuration such as CHAEN CHA DATA CHA FEILV CHA FRST and CHA DMA request so CHA and CHB can share the same DMA channel ii be set to 1 Monochrome mode When CHA and CHB have the same service frequency SSF 1 configuration CHACFG
107. 4 bitper phel OXTADO OX7AOF 8 bibper pixel OXTADO OXTAFF BPR control bit bypass Palette table is valid only when 1 bit per pixel and B W mode is selected In most cases of 1 bit per pixel configuration it is mono display mode and Palette table is not used Therefore Palette function can be bypassed by setting BPR to 1 However programmers can still use palette function on 1 bit per pixel mode BPRz 0 In this case GPL162002A 162003A LCD controller will read one index bit from LCD buffer next look up the corresponding first two palette registers and thenfinally send the corresponding gray level or color information to external LCD driver In the case of 12 bit per pixel 4096 colors solution GPL 162002A 162003A does not support Palette function In other words when 12 bit per pixel configuration is selected Palette function would be bypassed by hardware BPR 1 LCDBW and BPP are used to set up the pixel configuration If LCDBW is set to 1 Black amp White mode is enabled In this mode it supports mono 4 gray level and 16 gray level types for each pixel These Generalplus Technology Inc PAGE 125 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide three types are corresponding to 1 bit per pixel 2 bit per pixel and 4 bit per pixel respectively Note that Black amp White mode does not support neither 8 bit per pixel nor 12 bit per pixel configuration Th
108. 5 4 3 2 1 0 Function BLKLEN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 12 Reserved 11 0 BLKLEN R W Data Block Length The data block length to be transferred is in the unit of bytes The valus in this register should be equal to the block length of the SD MMC card Generalplus Technology Inc PAGE 290 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_SD_INT 0x79DA SD MMC Interrupt Enable Register Bit 1511411312 1111019 18 7 6 5 4 3 2 1 0 Function HOINTIINSINTIDBULEPTIDBULFUICBULFUIDCOM CCOM Default 0 0 0 0 0 0000 0 0 0 0 0 0 0 Function Description Condition Reserved IOINT SD 10 Card Interrupt Enable 0 Disable Writing 1 to this bit will enable the SD IO card 1 Enable interrupt INSINT Card Insert Interrupt Enable 0 Disable Writing 1 to this bit will enable the card insert 1 Enable interrupt Writing 1 to the P SDStatus 12 will clear this interrupt DBULEPT Data Buffer Empty Interrupt Enable 0 Disable Writing 1 to this bit will enable the data buffer empty 1 Enable interrupt This interrupt will be cleared after data had been written to the P SD DataTX DBULFU Data Buffer Full Interrupt Enable 07 Disable Writing 1 to his bit will enable the data
109. 8 7 6 5 4 3 2 1 0 Function DMAINTEN_CLR DMAINTEN DMAINTF Default 0 0 0 0 0 0 0 0 0 0 0 0 O 0 0 0 Bit Function Type Description Condition psp JL Reseed 2 DMAINTEN_CLR R W DMA Interrupt Disable Write 1 DMA Interrupt Disable If this bit is set to 1 DMA Interrupt will be disabled 1 DMAINTEN R W DMA Interrupt Enable Write 4 DMA Interrupt Enable If this bit is set to 1 and a DAM interrupt occurs hardware will issue an IRQ3 or FIQ to CPU To select between IRQ3 and FIQ please refer To Chapter Interrupt DMAINTF R W DMA Interrupt Flag Read 1 Occurred This bit is set if one of DMA Read 0 Not occurred interrupts happens The interrupt indicates Bulky Out or Bulk In transaction is finished in DMA mode Writing 1 to clear the specific interrupt would clear this bit P_USBD PMR 0x7B32 USB Power Management Register Bit 1514 13 12 4110 9 8 7 6 5 4 3 2 1 0 Function IRESWKEIRE_WA RE_WAFEA RST SUS_Mod Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition rs E L RESWKE R W Resume Wakeup Enable E Write 1 to enable Resume Wakeup Returning 1 Enable from suspend mode indicates the system or CPU that USB is wakeup now Write 0 to disable this function O Generalplus Tec
110. 8 line key scan process LCD BLANK IOA 0 IOA 1 IOA 2 IOA 3 IOA 4 IOA 5 IOA 6 IOA 7 Fig3 Key Scan Mode 1 Flexible Sampling time depends on the LCD s configuration The other type is the fixed sampling time mode This mode is executed automatically when LCD is off or LCD does not share 10 with key scan controller Writing FIXSTIME in P KS Ctrl to 1 can enter this mode when this controller shares IO with the LCD interface The sampling time can be configured as 8T 16T 32T and 64T When the resistance or the capacitance connected with a key pad is lager using longer sampling time will have a better result Generalplus Technology Inc PAGE 296 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide LCD BLANK IOA 0 IOA 1 IOA 2 IOA 3 IOA 4 IOA 5 IOA 6 IOA 7 Fig4 Key Scan Mode 2 Fixed Sampling time depends on the TSEL in P KS Ctrl the terminated key scan will continue at next LCD blank 21 5 Auto Manual Sample Mode The key scan controller provides auto sample mode and manual mode The auto sample mode is initiated by writing 1 to AUTO in P KS Ctrl Each time the selected timer overflow bit is rising the key scan function will start automatically After the key scan process is complete the INT in P KS Ctrl will be set only when SMART in R KS Cl is 0 o
111. 89 e 3 i vcc 33 Ir a tu aie z m mm mb EES m VCC 33 Wt rene eames JP15 1K MA23D11MA23 MCSODOMCSO MCS1D1MCS1 MCS2D2MCS2 MCS3D3MCS3 6 MCSADAMCSS Y Y Y Y Y Y N m Co o N a NN CH N m UN lt ais N N nD 3 o 2 n A un JP14 JP24 da Oa O Qo Os O Aa gas zag o Y a 9 aya 9 PORTO PORID ETS Eno Fio Eno No Eno ann 10D13 10D12 10D15 JP2g HEADER 3 ppg FADER jpggHEADER 3 pa HEADER jS HEADER 3 p40 Ras JP39 RAA HEADER 3 JP25 HEADER 3 JP28 HEADER 8 JP31 HEADER 3 JPS4HEADER 3 JP36 HEADER 3 HEADER 3 ETS EE EET Me ETS ae able able pe o o a a Da O s gc ahNoea Saad AA un Ka t oo o a zs JP o GER Sae Sas 28 a6 5 PORTD PORTD M M M M M M TS N Ee gD A DN MAD 5 MA17 MA18D6MA 18 MA19D7MA19 MA20D8 MA20 MA21D9MA21 MA22D10 MA22 1OC 0 15 gt x m B UARTIrDATX R20 UARTIrDARX C_33 J EUR 10K eo r co T S16 JPM JP21 J SW DIP 4 PORTC PORTO JP10 JP20 Putas pata elogio See Ojo See JP38 10B 0 15 3 ae m H Q m d MOE AN JP9 JP19 O B4 IOA 0 15 lt o G TANMTHORDHO TAMTNORDHO JP7 JP17 PORTA PORTA L Generalplus Technology Inc PAGE 386 V1 0 Dec 20 2006 A Generalplus GPL162002A 162003A Programming Guide
112. 9 8 7 6 5 4 3 2 1 0 Function ACTHRES 23 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bit Function Type Description Condition 58 Reseves 7 0 ACTHRES AC Threshold Register 23 16 P DAC EQBANDSEL 0x7BF6 EQ Band Index Selection Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EQBAND Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ssi reserves NS PA 2 0 EQBAND R W EQ BandSpectrum Output Selection 000 Select band 0 001 Select band 1 010 Select band 2 011 Select band 3 100 Select band 4 101 Select band 5 110 Select band 6 111 Resreved P_DAC_EQSPEC Ox7BF7 EQ Band Spectrum output Bit 15s 14 13142 11 10 9 8 7 6 5 4 3 2 1 0 Function EQSPEC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 532 Reserve 11 0 EQSPEC EQ Spectrum of Each Band This register represents the spectrum of band set in EQBAND P DAC VOLUME3D Ox7BF8 3D Main Volume Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function VOL 3D Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 106 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit F
113. 9 8 7 6 5 4 3 2 1 0 Function DMA_SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Functon Type Xa Description Condition psp co Reened 10 0 T DMA SAH R W TFT DMA Start Address This register is to set TFT LCD buffer start address high byte P TFT DMASTART AL 0x7D0E TFT DMA Start Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DMA_SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 DMA_SAL R W TFT DMA Start Address This register is to set TFT LCD buffer start address low byte Generalplus Technology Inc PAGE 141 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TFT_DM_OFFSET Ox7DOF TFT DMA Offset Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DMA OFFSET Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit Function Type Description Condition pst Reserves 10 0 DMA_OFFSET TFT DMA Address Offset For Each Line ADA TFT Virtual Frame DMASA DMA START ADDR DMAOFESET DMA OFFSET ADDR P TFT DM OFFSET and P TFT PIXEL NUM control registers set up the horizontal size of virtual page The maximum virtual page is of 1024 pixels To move the actual display area horizontally or vertically users
114. Attribution Register Bit 15 14 13 12 4 11 4410 9 8 7 6 5 4 3 2 1 0 Function IODATT Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Global Interrupt Control Register Summary Table Name Address Description _ P INT Status1 Ox78A0 Interrupt Status Register 1 P INT Status2 0x78A1 Interrupt Status Register 2 P_INT_Priority 0x78A4 Interrupt Priority Register 1 P_INT_Priority2 0x78A5 Interrupt Priority Register 2 P MINT Ctrl 0x78A8 Miscellaneous Interrupt Control Register P INT Status1 0x78A0 Interrupt Status 1 Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function KEYIF ADCRIF TFTUFIF TFTFEIF UTIRIF SPIIF FPIF TPIF ASIF AUDBIF AUDAIF USB DMA EXTBIF EXTAIF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P INT Status2 0x78A1 Interrupt Status 2 Register Bit 15 14 13 12 11 10 9 8 71615 4 3 2 1 0 Function TMDIF TMCIF TMBIF TMAIF KSIF TMBCIF TMBBIF TMBAIF SD I2C NAND SCHIF ALMIF HMSIF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UA n ilu Ln A r o Generalplus Technology Inc PAGE 320 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide EEE MH EE EE P_INT_Priority1 0x78A4 Interrupt Priority 1 Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Func
115. Bit Function Type Description Condition 15 0 LCDBUFAL LCD Buffer Address 15 0 bo P LCD Buffer HighAdr 0x7985 LCD Buffer Address A25 A16 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LCDBUFAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 121 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition mse Resewe LCDBUFAH LCD Buffer Address 25 16 rd LCDBUFAH and LCDBUFAL construct a 26 bit addressing register to define the start address of a LCD buffer P LCD Buffer Offset 0x7986 LCD Offset Size Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LCDOFST Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Descriptions J Condition usaf Reseed NN LCDOFST R W LCD Virtual Page Offset Unit pixel The value given here must be the multiple of 16 that is the bit3 bitO must be all Os Note LCDOFST LCDSEG 1 should smaller than 1024 lt Maximum 1024 Pixel 5 LCDOFST offsetA offsetB OffsetA Actual LCD Display Area Physical Whole Display Area Logical P LCD Buffer Offset and P LCD Buffer Segment control registers set up the horizontal size of a virtual page Note that th
116. CSB3NUM Init 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bit Function Type Description Condition AN CSB3 Program Timing Register Reserved CSB3NUM R Range 0 15 Tw CSB3NUM 3 0 SYSCLK P MCSA TimingCtrl 0x782C MCS4 CS timing control register Bit 151 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function CSBANUM Init 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bit Function Type Description Condition CSBANUM m Program Timing Register PAGE 35 Range 0 15 Tw CSB4NUM 3 0 SYSCLK Generalplus Technology Inc V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Among all the chip select signals CS3 and CS4 access setup time and hold time can be adjusted This makes CS3 and CS4 more flexible for special memory devices such as Compact Flash cards Please refer to the following timing diagrams CS3 CS4 Timing CS3 4 WAIT Addr addregs valid M8 LL WE x em ii Al gt WEBHNUM 4 WEB NUM CSB NUM CSB NUM Following control registers are used to change the memory address signals and memory control signals to GPIO functions After power on reset the default settings of these pins are as memory access signals except CS4 If there is no external memory device or external devices are less than five some of memory addresses or memory control signals can be used as GPIOs To ch
117. Check Reg gt 784D Column Parity F Field 1 Error Line Position 7857 Check Once P ECC Cm 0x7857 ECC Control Register Bit 15 14 LA3N 12 11 104 9 8 7 6 5 4 3 2 1 0 Function s ECCSPT CKP ERST Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 3 Reserved 2 ECCSPT W ECC Stop Calculation 1 Stop calculate Write 1 to this bit will stop ECC and checksum 0 Calculate calculation all parity registers will keep the previous value 1 CKP W Write 1 to check parity Line or Column once The 1 Check once Low Byte Error Flag will be shown on 0x785E and 0 no action 0x785F and the High Byte Error Flag will be shown on 0x784E and Ox784F In checksum function it does not support check function ERST W Reset ECC The reset action must be done before any 1 Reset data is transferred to the ECC and checksum module 0 not Reset Generalplus Technology Inc PAGE 240 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P ECC LPRL LB 0x7858 ECC Low Byte Line parity LSB Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LPRL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 LPRL R The ECC Line parity regis
118. Clear Register Bit 15 14 13 12 11 10 9 8 7 6 J 5 4 3 2 1 0 Function IINBCIBOBC BIBC EPOBC Default 0 0 0 0 0 0 0 0 0 0 0 O 0 0 0 0 Bit Function Type Description Condition ps Reserved 3 IINBC W Interrupte In Buffer Clear Write 1 to clear Interrupte In buffer Write 1 to clear Bulk Out buffer Write 1 to clear Bulk In buffer CRT Write 1 to clear EPO buffer P USBD EPEvntClear 0x7B40 USB Endpoint Event Clear Register Bit 15 14 131121111101 9 8 7 16 5 4 3 2 1 0 Function k IINPCIBOECIBIPCIEPOSCIEPOIPCIEPOOEC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit_ Function Type Description Condition psg Reseed VAO _ _ j j Interruptin Packet Clear EE Write 1 to this bit to clear P USBD EPEvent 14 Bulk Out Enable Clear mE Write 1 to this bit to clear P USBD EPEvent 11 Bulk In Packet Clear Write 1 to this bit to clear P USBD EPEvent 9 EPO Status Clear Write 1 to this bit to clear P USBD EPEvent 6 B mm Write 1 to this bit to clear P USBD EPEvent 4 indi Li RN EPO Out Enable Clear Write 1 to this bit to clear P USBD EPEvent 1 P USBD EPOWrtCount 0x7B41 USB Endpoint0 Write Count Register Bit 151 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function
119. Control Method EQ AC Filter Coefficient Register Mapping Address Suggested Value 0x20 Ox3F2AEC 0x21 Ox80DB59 0x22 Ox3DCDD8 0x23 0x825E4A 0x24 Ox3AA52B 0x25 0x86676F 0x26 0x311BE2 0x27 0x978040 0x28 0x2150F8 0x29 0xC4C1F1 0x2A Ox086CFE 0x2B 0x1BB754 0x2C 0xC0D513 Filter Gain Register Mapping Address Meaning 0x40 Gain of Band 0 GO 0x41 Gain of Band 1 G1 0x42 Gain of Band 2 G2 0x43 Gain of Band 3 G3 O Generalplus Technology Inc PAGE 109 V1 0 Dec 20 2006 G Generalplus Address GPL162002A 162003A Programming Guide Meaning 0x44 0x45 Gain of Band 4 Gain of Band 5 G4 G5 0x46 Gain of Band 6 By adjusting G0 G6 many kinds of effects can be applied to output voice setting gain The following table shows the setting value in each step Value Value G6 There are 25 setps for Value 0x0809BC 0x0904D1 0x196B23 0x1C8520 0x50615F 0x5A3031 Ox0A1E89 0x200000 0x653161 Ox0B5AA1 0x23E793 0x718A50 Ox0CBD4B 0x28491E 0x7F64F0 0x0E4B3B 0x2D3382 0x1009B9 0x32B772 0x11FEB3 0x1430CD Ox38E7AA Ox3FD930 Ox16A77D 0x47A39A The follow effects can be applied by setting different gain in each band Effect G0 G1 G2 G3 g4 G5 G6 DBB 18 18 16 16 12 9 5 ROCK
120. Ctrl 0x78B0 TimeBaseA Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMBAIF C TMBAIE TMBAEN TMBAS Default 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 P_TimeBaseB_Cirl 0x78B1 TimeBaseB Control Register Bit 15 14 13 1211111019 8 PARE 5 1 4y 34 2 1 0 Function TMBBIF C TMBBIE TMBBEN C l Sel TMBBS Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimeBaseC_Cirl 0x78B2 TimeBaseC Conirol Register Bit 15 14 13 12141 110918 716151 41312 1 0 Function TMBCIF C TMBCIE TMBCEN 4 TMBCS Default 0 0 0 0 0 0 0 0 0 0 0 0 O O 0 P_TimeBase_Reset 0x78B8 TimeBase Reset Conirol Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMCCR Default Real Time Clock Control Register Summary Table Mame Address Description Generalplus Technology Inc PAGE 325 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_Second 0x7920 Second Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RTCSEC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_Minute 0x7921 Minute Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RTCMIN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
121. DP x 3 DN_X T Ds D 4 VBus_ 5 o GND VBus 20pF USB_BRec Generalplus Technology Inc PAGE 392 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 25 6 CPU Performance Downgrade Issue 25 6 1 LCD Display and System Performance GPL162002A 162003A can use internal SRAM or external memory as display buffer If LCD buffer is configured as an external memory device the display data should be read from external memory and running program is on the other external memory device these two memory devices will share the same system bus Therefore CPU performance is degraded As depicted in the following table there are three memory access conditions on GPL162002A 162003A When LCD and CPU access the same region of memory the CPU performance of CPU will be downgraded At this situation Generalplus recommends take the following action to improve the CPU performance Copy the instruction into SRAM and execute it in internal SRAM Or define the LCD buffer in the internal SRAM LCD uses internal SRAM LCD uses external memory as data buffer as data buffer Software Program downgrade CPU performance Do not downgrade CPU performance On Internal RAM Software Program downgrade CPU performance Do not downgrade CPU performance On Internal ROM Software Program Do not downgrade CPU downgrade CPU performance On External memory performance If it is difficult to take above actions
122. Device_addr isend device addr P_12C_Data r1 r1 0x0f0 H Write OxOOfO to status register P_I2C_Status r1 waitloop ri P I2C Ctrl test r1 0x010 jz waitloop r1 P_l2C Status r1 amp 0x0f tests 10x01 jz next goto F Error H Did not receive ACK next test r1 0x08 jz next1 goto F_Error II Bus arbitration failed r1 Send Data send data P I2C Data r1 r1 P DC Ctrl clear int flag and send data P_12C_Ctrl r1 waitloop2 ri P I2C Ctrl test r1 0x010 jz waitloop2 r1 P 12 C Status r1 amp 0x0f Generalplus Technology Inc PAGE 261 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide test r1 0x01 jz next4 Goto F_Error next4 test r1 0x08 jz Master_Transmit_Complete r1 0x0d0 P_I2C_Status r1 goto Error Master_Transmit_Complete jmp Generalplus Technology Inc PAGE 262 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 19 DMA and Bridge Controller 19 1 Introduction The DMA controller built in GPL162002A 162003A is a 4 channel DMA controller combined with a host to peripheral bridge Each DMA channel is capable of doing DMA transfer from any memory address to another memory address To minimize the host bus usage the DMA channel is also able to do the DMA transfer from IO to memory or from memory to IO or even from IO to IO During the DMA transfer the DMA controller can do the byte
123. EQEN BPEQ BPAC DEPTH 3D Default 0 0 0 0 0 0 0 0 070 0 0 0 0 0 0 P_DAC_ACTHRESL 0x7BF4 AC anti clip Threshold Low Register Bit 15 14 13 12 4 4410 9 8 7 6 5 4 3 2 1 0 Function ACTHRES 15 0 Default 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DAC_ACTHRESH Ox7BF5 AC anti clip Threshold High Register Bit 154 14 134 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ACTHRES 23 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 P DAC EQBANDSEL 0x7BF6 EQ Band Index Selection Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EQBAND Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DAC_EQSPEC Ox7BF7 EQ Band Spectrum output Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EQSPEC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L Generalplus Technology Inc PAGE 329 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P DAC VOLUME3D Ox7BF8 3D Main Volume Bit 15 14 38 42 0 40 amp 8 716 5 4 3 2 110 VOL 3D Defaut 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O Function P DAC VOLUME3D C 0x7BF9 3D Center Volume Bit 15 14 13 12 11 10 9 8 7 6 5 4
124. Frame Buffer Start Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1 VIR SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H Generalplus Technology Inc PAGE 144 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TFT_PIP2_VIR_SAL 0x7D2A TFT PIP2 Virtual Frame Buffer Start Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2 VIR SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 VIR SAL 0x7D35 TFT PIP3 Virtual Frame Buffer Start Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP3_VIR_SAL Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description gt gt Conditiom 15 0 PIPZ VIR SAL R W PIP Virtual Start Low Address PIP3 VIR SAL This register is valid only when PIPZSCREN is Real data address setto 1 The virtual frame start address means the real address of data not TFT PIPA buffer start address See the following diagram for details P TFT PIPO VIR EAH 0x7D15 TFT PIPO Virtual Frame Buffer End High Address Bit 15 14 13 124 41 10 9 8 7 6 5 4 3 2 1 0 Function PIP0_VIR_EAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP1_VIR_EAH 0x7D20 TFT PIP1 Virtual Frame Buffer E
125. Frame rate is the frequency of frame pulse signal FP In general for mono display frame rate is approximately 60Hz For gray level or color display frame rate might be about 180 90Hz For example In 4096 colors mode with 160X160 resolution and 48MHz of the system clock We obtain 48000000 160 160 180 2 2 8 4 Therefore LCDCLK 9 0 can be set as 8 or 9 in decimal Frame rate 48000000 160 160 B 2 187 5Hz if LCDCLK 9 0 8 Frame rate 480000007160 160 2 170 5Hz if LCDCLK 9 0 9 In mono mode with 320x240 resolution and 24MHz of the system clock We obtain 24000000 320 240 60 2 3 2 Therefore LCDCLK 9 0 can be set as 3 or 4 even 2 in decimal for higher frame rate Frame rate 24000000 320 240 25 2 78 1 Hz if LCDCLK 9 0 2 Frame rate 24000000 320 240 B 2 62 5 Hz if LCDCLK 9 0 3 Frame rate 24000000 320 240 4 2 52 Hz if LCDCLK 9 0 4 Important Note To decrease power consumption and increase CPU performance on external memory device system designers should try to minimize LCD frame rate as short as possible until there is no flicking phenomenon on a LCD panel Generalplus Technology Inc PAGE 120 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P LCD Segment 0x7982 LCD Segment Number Register Bit 15 1
126. Generalplus GPL162002A 162003A Programming Guide P_UARTIrDA Data 0x7900 UART IrDA Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function UARTDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_UART_RXStatus 0x7901 UART Reception Error Flag Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function OE BE PE FE Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P UARTIIDA Ctrl 0x7902 UART IrDA Control Register Bit 15 14 13 12 11 10 1918 7161 5 4 3 2 1 0 Function RXIE TXIE RTIE UEN MSIE SLT WLSEL FEN SBSEESPSEL PEN SB Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_UART_BaudRate 0x7903 UART Baud Rate Setup Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BUAD Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_UARTIrDA Status 0x7904 UART IrDA Status Register Bit 15 14 13 412111 110 R9 8 7 6 5 4 3 2 1 0 Function RXIF TAIE RIE Az N TXEF RXFF TXFF IRXEF BY DCD DSR CTS Default 0 0 0 0 0 0 0 0 1
127. IIS MODE IISEXT IISEN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AAA 7 6 1IS_MCLK 5 4 IIS BITS 3 2 MN a IIS External DAC Main Clock Selection These control bits are to set IIS MCLK clock which is a must for a high level DAC These bits are valid only when IISEN and IISEXT are both set to 1 IIS Data Bits Control Register If internal DAC is selected the IIS_ BITS needs to be set to 00 IIS Output Mode Select If internal DAC is selected IIS output mode should be the P DAC Ctrl 0x78FD b1 IIS mode External DAC Mode Enable This bit is valid only when IISEN is set to 1 same with 00 384 FS 01 256 FS 10 192 FS 11 128 FS Note FS is IIS LRCK clock 00 24 bits internal DAC support only 01 16 bits 10 32 bits 11 Reserved Right justified shift 1 bits Left justified Reserved 0 Disable 1 Enable Generalplus Technology Inc PAGE 103 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide IISEN R W DAC IIS Mode Enable 0 Disable This bit must be set to 1 when the 1 Enable internal DAC is used The Following registers are used to download upload parameter to 3D or EQ AC modules Before enabling these modules the correct registers must be downloaded with corresponding parameters into these modules P_DAC_ACCREQ 0x7BFO 3D EQ AC Parameter A
128. In Out 1 0 l 7 6 5 4 3 2 1 0 Special Nand Flash Interface Memory Signals Timer Specified Output unction Signal NF CLE NF OEB NF WEB CCPC CCPB CCPA In Out O O O O O yo yo yo Special Key Change Function Signal Key Ch2 Key Ch1 Key ChO In Out l l l Generalplus Technology Inc PAGE 43 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide PortC and Special Functions Shared Information 15 14 13 12 11 10 9 8 Special Ens DAC IIS Interface SDC IF UART IrDA Interface SDC IF unction Signal IS MCLK IIS BCLK IIS LRCK IIS SD SD DAT3 UART RX UART TX SD DAT2 In Out O O O O 1 0 l O 1 0 Special IIC Interface Function Signal IC DAT IIC_CLK In Out 1 0 O 7 6 5 4 3 2 1 0 Special SDC Interface LCD Interface Function STN FM In Out ele No la o o PortD and Special Functions Shared Information 15 14 13 12 11 10 9 8 Special General purpose Extnal Input Memory Address Bus Function Signal In Out 1 0 UO I l O O O O Special SPI IF Function Signal SPI DI In Out l 7 6 5 4 3 2 1 0 Special Memory Address Bus Memory Chip Selection Function Signal In Out O O O O O O O O Special SPI IF Function Signal SPI DO In Out O Generalplus
129. Low as the first bit of address there should be arbitration for second address bit and so on This arbitration will continue to the end of last address bit Bus Arbitration Produres If a slave receiver cannot acknowledge the confirmation of the slave address it should hold the level of the SDA line High In this case the master should generate a Stop condition and to abort the transfer If a master receiver is involved in the aborted transfer it should signal at the end of the slave transmitting operation by canceling the generation of an ACK after the last data byte is received from the slave The slave transmitter should then release the SDA to allow a master to generate a Stop condition Generalplus Technology Inc PAGE 252 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 18 3 Firmware Flow Chart 18 3 1 Master Transmit Mode Start v Change to Master Transmit Mode Y Write Slave Address to P DC Data Y Write 0xF0 to P DC Status Y Data in P DC Data is Transmitted Y Interrupt Pending ACK Received Y N S Y Stop y Y Write New Data to P DC Data Write 0xD0 to P DC Status Y Y Clear Pending Interrupt Clear Pending Interrupt lt D y Y Data in P I2C Data is Wait until Controller IDLE Transmitted Y Stop O Generalplu
130. Method sienne 110 10 10 Program EXaMpleS u u 110 11 yn Neo ee 113 11 1 IVE OCU CHOI pem aeeauees 113 11 2 LCD Control Pin Configuration sise 113 11 3 ep 114 11 4 LCD PAS LE acs s l hs u RUE OM es 115 Generalplus Technology Inc PAGE 4 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 11 5 lu ele 117 11 6 Operation during Wait Halt Standby amp Wakeup Procedure a 126 11 7 LCD Image Resource File Tooling sse see eee eee 127 11 8 Program lu 128 12 TFT LCD isso E E E E R E E 131 12 1 vie e Dieu UT 131 12 2 I a Blue E 131 12 3 NOR e KA err ets 132 12 4 sub Frame Display PIER suerge gue hee id dE EE 132 12 5 Control Register uu WE E s 133 12 6 Operation during Wait Halt Standby amp Wakeup Procedure m r M 152 12 7 Programming Example mn M D 152 13 UART IRDA INTERFACE 2 2er ceto ndun et een areas ie Ng ql iecit 154 13 1 INTOdUCION ee A b ud NE 154 13 2 Structure and Block Diagram U tenen is 154 13 3 UART IrDA SIR Frame Schere AN rg ree 155 13 4 UART IrDA Control Pin Configuration deeem enne 156 13 5 Control registers iie e eu 156 13 6 Program Examples A A M Ree Ness
131. Mode Color Mode Control Register Word word Location 15 12 11 8 7 4 3 0 0x7A00 RaR2R1Ro G3G2G Go B3B2B1Bo 0x7A01 RaR2R1Ro G3G2G 1Go B3B2B1Bo 0x7A02 RaR2R1Ro G3G2G Go B3B2B1Bo R3R2R 1Ro G3G2G1Go B3B2B1Bo R3R2R Ro G3G G Go B3B B Bo Invalid Area Reserved Area Therefore if Palette is activated values in a LCD buffer are only indexes of color It does not contain the real display color information On the contrary if Palette is bypassed not activated values in a LCD buffer is the real display color information Generalplus Technology Inc PAGE 116 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide GPL162002A 162003A provides many kind of LCD configuration that varies with n bit per pixel Palette operation and color P LCD Palette Ctrl control register will easily help programmers to set up their own configurations Please refer to the following Section Control Register for details The color index with Palette or real color level without Palette are sequentially distributed In a LCD buffer The following three diagrams depict the detailed layouts for 8 4 2 bit per pixel LCD buffer for bit i 15 0115 0115 0 e fT T T TT T T L o T 7 0 7 0 7 0 7 0 7 0 7 0 1st pixel 2nd pixel 3rdpixel 4th pixel 5th pixel 6th pixel value value value value value value LCD buffer for 4
132. Name Address Description P SD DataTX Ox79DO SD MMC Data Transmit Register P SD DataRX SD MMC Data Receive Register P SD CMD SD MMC Command Register P SD ArgL SD MMC Argument Low Word Register P SD ArgH SD MMC Argument High Word Register P SD RespL Ox79D5 SD MMC Response Low Word Register P SD RespH 0x79D6 SD MMC Response High Word Register P_SD_Status Ox79D7 SD MMC Status Register P SD Ctrl 0x79D8 SD MMC Control Register P_SD_BLKLEN 0x79D9 SD MMC Block Length Register P_SD_INT Ox79DA SD MMC Interrupt Enable Register P SD DataTX Ox79DO SD MMC Data Transmit Register Bit 15 14 13 12 11 10 1 9 8 7 6 5 4 3 2 1 0 Function DataTX Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Description Condition DataTX SD MMC Data Transmit Register Write data to SD card data can be written to this register only when DATBUFEMPTY is 1 Data transmit register host writes 16 bit data to this register and the controller will transmit it to SD card When the data stored in the buffer is transmitted DATBUFEMPTY bit in P SD Status register will be set or the DMA request will be issued It should be noted data could be written to this register only when DATBUFEMPTY is 1 P SD DataRX 0x79D1 SD MMC Data Receive Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DataRX Default 0 0
133. ON eee _ _ L PIP H_STR R W The PIP frame horizontial start location in the main frame See the following diagram for details P TFT PIPO H END Ox7D1A TFT PIPO Horizontal End Location in Each Line Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPO H END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP1 H END 0x7D25 TFT PIP1 Horizontal End Location in Each Line Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1 H END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 148 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TFT_PIP2_H_END 0x7D30 TFT PIP2 Horizontal End Location in Each Line Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function PIP2 H END Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 H END 0x7D3B TFT PIP3 Horizontal End Location in Each Line Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function PIP3 H END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description a Condition ps1 JL Rea S 4 lal The PIP frame horizontial end location in the main frame See the following diagram for details
134. PIP1 VIR SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP2 VIR SAL 0x7D2A TFT PIP2 Virtual Frame Buffer Start Low Address Bit 15 4 14 134 122 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2 VIR SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 VIR SAL 0x7D35 TFT PIP3 Virtual Frame Buffer Start Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP3_VIR_SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIPO_VIR_EAH 0x7D15 TFT PIPO Virtual Frame Buffer End High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPO_VIR_EAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 337 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P TFT PIP1 VIR EAH 0x7D20 TFT PIP1 Virtual Frame Buffer End High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1_VIR_EAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP2_VIR_EAH 0x7D2B TFT PIP2 Virtual Frame Buffer End High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2 VIR EAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
135. R W SOF Timer 0 Disable SOF timer R ee 4 to enable SOF timer a Enable SOF timer Reevd ss ssid HOSTEN R W Host Enable 0 Host is disabled Write 1 to this bit to enable host 1 Host is enabled Device is disabled P_USBH_TimeConfi 0x7B01 USB Host Timing Configuration Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SAU PAC TC IPD Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ET LE Storage 1 2 Auto Mode If this bit is set to 1 setting P USBH StorageRST after each transaction in non DMAymode is not Pointer Auto Clear Always set to 1 If fthe bt is set 1 READ WRITE pointer is automatically reset to O after any transaction However this mode is automatically disabled in DMA mode The ADMA mode is activated by configuring P_USBH_AutoTrans 0 or P USBH AutoTrans 1 TimeOut Criteria Inter Packet Delay P USBH Data 0x7B02 USB Host Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function HDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 204 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition 58 Rend HDATA Host Data Mu P USBH Transfer 0x7B03 USB Host Transfer Regi
136. RGB serial mode only 2 0 dEVEN L TYPE R W 4 Even line Serial RGB Data Arrangement These bits are used for RGB serial mode only 000 RGB 001 RBG 010 GRB 011 GBR 100 BRG 101 BGR 110 111 Reserved 000 RGB 001 RBG 010 GRB 011 GBR 100 BRG 101 BGR 110 111 Reserved P TFT YUV CTRL 0x7D0C TFT YUV Mode Control Register Bit 15 14 13 1211101918 7 6 5 4 3 2 1 0 Function YUV EN YUV MjCCIR656 EN SHARE YUV_TYPE Default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 V1 0 Dec 20 2006 Generalplus Technology Inc PAGE 140 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition _ 1 Enable This bit is valid only when YUV is enabled 1 YUV il Zeg M r bit is valid GE when YUV is enabled RE Enable m sl Reevd SHARE RAW RGB Data Share Enable 0 Not share If this bit is set to 1 then there is one RGB 1 Share data for U Cb YV cr Y Otherwise there are two RGB data for U Cb YV Cr Y This bit is valid only when YUV is enabled pz Rea ON ST t 0 YUV TYPE R W YU Cb V Cr data Arrangement 00 U Cb YV Cr Y These bits are valid only when YUV is 01 V Cr YU Cb Y s 10 YU Cb YV Cr P_TFT_DMASTART_AH 0x7D0D TFT DMA Start High Address Bit 15 14 13 12 ite 10
137. Read 1 Occurred P USBD INTEN is 1 and the status stage is Write 0 No effect finished this bit will be set Write 12 Clear the flag EPO In NACK Interrupt Flag Read 0 Not occurred If the corresponding enable bit of Read 1 Occurred P_USBD INTEN is 1 and an IN request Write 0 No effect happens with rplying a NAK to the host is Write 1 Clear the flag bit will be set EP0 In Packet Clear Interrupt Flag Read 0 Not occurred If the corresponding enable bit of Read 1 Occurred P USBDLINTEN iA and an IN packet is Write 0 No effect EI read from the host this bit will be set Write 1 Clear the flag EOONA EPO Out NACKdnterrupt Flag Read 0 Not occurred If the corresponding enable bit of Read 1 Occurred P USBD INTEN is 1 and an OUT request Write 0 No effect happens with rplying a NAK to the host this Write 1 Clear the flag bit will be set P USBD INTEN is 1 and an OUT packet is Write 0 No effect loaded into the endpointO FIFO this bit will Write 1 Clear the flag be set EOOPS EPO Out Packet Set Interrupt Flag Read 0 Not occurred If the corresponding enable bit of Read 1 Occurred EOSPS Generalplus Technology Inc PAGE 194 V1 0 Dec 20 2006 EPO Setup Packet Set Interrupt Flag Read 0 Not occurred If the corresponding enable bit of Read 1 Occurred P_USBD_INTEN is 1 and a non standard Write 0 No effect setup command or get set descriptor Write 1 Clear the flag command is loaded into t
138. Register Bit 15 14 13 12 11 10 9 x8 1716 5 4 31211110 Function SPIEN LBM a 4 SPIRST MOD SCKPHA SCKPOL SCKSEL Default 0 0 050 0 0 0 0 0 0 0 0 0 0 0 0 P_SPI_TXStatus 0x7941 SPI Transmit Status Register Bit 15 14 137 142 11 10 9 8 7 6 5 4 3 2 1 0 Function SPITXIF SPITXIEN TXFLEV TXFFLAG Default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 P SPI TXData 0x7942 SPI Transmit FIFO Register Bit 154 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SPIDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P SPI RXStatus 0x7943 SPI Transmit Status Register Bit 15 14 13 12 111410 9 8 7 6 5 4 3 2 1 0 Function SPITXIF SPITXIEN JRXFULL RXFOV TXFLEV TXFFLAG Default 0 0 0 0 0 0 0 0 0 0 L Generalplus Technology Inc PAGE 343 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P SPI RXData 0x7944 SPI Receive FIFO Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SPIDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P SPI Misc 0x7945 SPI Misc Control Register Bit 15 14 13 12 11 10 9 8 71615 4 3 2 1 0 Function OVER SMART BSY RFF RNE TNF TFE Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
139. Reserved A S 3 P_MADC Ctrl 0x7961 Manual ModeADC Control Register Bit 15 14 1311211110 19 8 7 6 514 3 2 1 0 Function ADCRIF C ADCRIEN CNVRDY STRONV CHSEL Default 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Function Description Condition ADCRIF C R W AD Conversion Ready Interrupt Flag amp Clear Read 0 Not Occurred This bit is set to 1 by hardware if the AD Read 1 Occurred conversion is ready and ADC data is reliable Write 0 No Effect Write 1 Clear the flag 14 ADCRIEN AD Conversion Ready Interrupt Enable 0 Disabled If this bit is set to 1 and AD conversion is 1 Enabled ready hardware will issue an IRQ1 or FIQ to CPU To select between IRQ1 and FIQ please refer to Chapter Interrupt aal Jo Reseed PE Generalplus Technology Inc PAGE 223 V1 0 Dec 20 2006 G Generalplus Function GPL162002A 162003A Programming Guide Description Condition CNVRDY STRCNV AD Conversion Ready Indicate bit Manual Start AD Conversion AD conversion Writing this bit to 1 will start the operation of 0 Not ready AD data not effect 1 Ready ADC data is effect 0 No Effect 1 START sa Rea 2 0 CHSEL Current ADC Channel Selection 000 Selects TP X axis 001 Selects TP Y axis 010 7 Selects LINEIN1 011 7 Selects LINEIN2 1007 Selects LINEIN3
140. S G Generalplus GPL162002A 162003A Programming Guide P_SD Ctrl 0x79D8 SD MMC Control Register Bit 15 14 13 12 11 10 9 8 T DIB 4 3 2 1 0 Function SDEN IOEN DMAMOD BUSWD CLKDIV Default 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 Bit Function Type Description Condition 15 12 Reserved 11 SDEN R W SD Enablen 0 Disable If this bit is set to 1 SD MMS interface is 1 Enable enabled Or SD MMC interface is disabled 10 IOEN R W SD IO Card Interrupt Enable 0 Disable If this bit is set to 1 SD IO Card interrupt 12 Enable detection is enabled else it is disabled DMAMOD RW DMA Mode Enable 0 Not using DMA mode If this bit is set to 1 it will use DMAvchannel 4 Using DMA mode to transfer data BUSWD R W Bus Width Selection 0 1 bit data bus If this bit is set to 1 the data bus width is 4 1 4 bits data bus bits during a transfer else the bus width is 1 bit 7 0 CLKDIV R W Clock Division The clock speed on the SD bus is calculated from these bits FSDCLK FSYSCLK 2 CLKDIV 1 SD MMC control register is used to control the clock speed of the SD bus and data block length when transmitting or receiving data This register is changeable only when BUSY bit in status register is 0 P SD BLKLEN 0x79D9 SD MMC Block Length Register Bit 15 14 13 12 11 10 9 8 7 6
141. STIME TSEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Type Description Condition Key Scan Interrupt Flag Read 0 Not occurred This bit is set to 1 by hardware if the key Read 1 Occurred scan interrupt happens Write 0 No effect Write 1 Clear the flag Key Scan Interrupt Enable 0 Disable If this bit is set to 1 and key scan interrupt 1 Enable occurs hardware will issue and IRQ6 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked To select between IRQ6 and FIQ please refer to 13 AUTO R W Automatically Sample Mode 0 Manual scan mode only When this bit is set to 1 the key scan 1 Automatical and manual controller will initiate a scan process scan mode are both available automatically when selected timer overflow happens Generalplus Technology Inc PAGE 298 V1 0 Dec 20 2006 G Generalplus Function Type GPL162002A 162003A Programming Guide Description Condition FIXSTIME RW 10 SMART R W STRSCAN W B74OFF R W Generalplus Technology Inc Fix Sample Time When LCD is turned off this bit is useless and the controller will change to fixed sampling time mode automatically When LCD is on and uses IOA as output users can choose either LCD blank time or fixed sampling time as sampling time via this bit Inverted Output Control Th
142. Significant Features Sunplus16 bit CPU j nSP maximum 96MHz 2 7V 3 6V Dual Clocks System Phase Lock Loop and 32768 Crystal e Flexible Operations Wait Halt Sleep for power management Address extensible to 80M words e Built in Internal 30K word SRAM STNLCD controller supporting up to 320x320 dots 16 gray level or 4096 color level display e TET LCD controller supporting up to 640X480 dots 65536 color level display Two Channels 16 bit DAC audio outputs MP3 decoding accelerator band programmable equalizer e 3D Surround processor Six channels 12 bit ADC two channels are dedicated to touch panel e 16 bit ADC for stereo microphone line in FM record One UART amp One IrDA with 8 byte transmit and receive FIFOs queues Five chip select pins to access external ROM SRAM and NOR amp NAND Flash memories e Six 16 bit re loadable timers counters and two of them support capture comparison and PWM functions One SPI Serial Peripheral Interface Generalplus Technology Inc PAGE 11 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Real Time Clock RTC supports auto update to hour and an alarm comparison register Built in 2 5V low voltage reset Embedded In Circuit Emulation More system reliability features watchdog illegal write reset flag mode protection for write error watchdog protection for write error
143. Start Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP3 SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 147 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition 15 0 PIP SAL R W PIP Frame Buffer Start Low Address This register set up TFT PIP LCD buffer address P TFT PIPO H START 0x7D19 TFT PIPO Horizontal Start Location in Each Line Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPO H STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP1 H START 0x7D24 TFT PIP1 Horizontal Start Location in Each Line Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1 H STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP2 H START 0x7D2F TFT PIP2 Horizontal Start Location in Each Line Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2 H STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 H START 0x7D3A TFT PIP3 Horizontal Start Location in Each Line Bit 15 14 13 12 14 10 9 8 7 6 5 4 3 2 1 0 Function PIP3 H STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uso
144. Start a Key Scan process Write 0 No effect Write 1 Stop the controller Write 0 IOA7 IOA4 are used as scan output Write 1 IOA7 IOA4 are used as GPIOs V1 0 Dec 20 2006 G Generalplus Function Type GPL162002A 162003A Programming Guide Description Condition BOOFF 3 2 STIME B310FF 1 0 TSEL Bit 3 1 OFF When this bit is set to 1 IOA3 IOA1 are used as GPIOs and setting the control registers P KS Data3 P KS Data is invalid Bit 0 OFF When this bit is set to 1 IOAO is used as GPIO and setting the control register of P KS Data is invalid Key Scan Sample Timer Selection These bits are valid only when FIXSTIME is set to 1 or LCD is turned off When LCD is using IOA and FIXSTIME is set to 0 these bits is invalid the sampling time in such a case is the length of LCD blank time Key Scan Auto Sample Mode Timer Selection bits auto sample mode is enabled These are valid only when Write 0 IOA3 IOA1 are used as scan output Write 1 IOA3 IOA1 are used as GPIOs Write 0 IOAO is used as scan output Write 1 GPIOs IOAO is used as Key scan sample time 00 8 System Clocks 012 16 System Clocks 107 32 System Clocks 112 64 System Clocks 002 Trigger Source is TimerC 017 Trigger Source is TimerD 107 Trigger Source is TimerE 112 Trigger Source is TimerF P KS DataO 0x7BC8
145. Write 0 to disable that function 1 BI NULLPKT RAW Write 1 to enable USB device to send a null packet to the Bulk IN endpoint Write 0 to disable that function EPO NULLPKT R W Write 1 to enable USB device to send a null packet to the EndpointO Write 0 to disable that function P USBD EPEvent 0x7B37 USB Endpoint Event Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IINNA IINPR BONA BOPR BOPE BINA BIPC BIPR EOSNA EOSEN EOINNA EOINPR EOONA EOOPR EOOPE EOSPR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 187 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Interrupt IN NACK Read 1 Occurred This bit is set to 1 if an IN request happens Read 0 Not occurred and in the meantime the device sends a Write 0 No effect NAK Write 1 to clear the bit Write 1 Clear the flag Interrupt IN Packet Ready Write 1 Packet is ready Set this bit to 1 to indicate an IN packet is ready in the INTERRUPT IN FIFO Its set automatically if there are 8 bytes IN data and P_USBD_EPAutoSet 4 is 1 After this bit is set to 1 the hardware will send the data to the Host This bit is cleared by hardware when the data transaction is finished Bulk Out NACK Read 1 Occurred This bit is set if an OUT packet happens and Read 0 Not occurred
146. allowed 0011 data no in FIFO gt 4 4 read is allowed V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description 1 Condition 0100 data no in FIFO gt 5 5 read is allowed 0101 data no in FIFO gt 6 6 read is allowed 0110 data no in FIFO gt 7 7 read is allowed 0111 data no in FIFO gt 8 8 read is allowed 1000 1111 not valid 3 0 IRXFFLAG Receive FIFO Data Level 0000 No data in FIFO or 8 The register is used to indicate how many bytes in FIFO data are still in the FIFO 0001 1 byte in FIFO 0010 2 bytes in FIFO 0011 3 bytes in FIFO 0100 4 bytes in FIFO 0101 5 bytes in FIFO 0110 6 bytes in FIFO 0111 7 bytes in FIFO P SPI RXData 0x7944 SPI Receive FIFO Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SPIDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition nse gt py reserves 7 0 SPIRXDATA R Read data from SPI Transmit FIFO Po P_SPI_Misc 0x7945 SPI Misc Control Register Bit 15 14 13 12 11 10 9 8 71615 4 3 2 1 0 Function OVER SMART BSY RFF RNE TNF TFE Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 pev eee E OVER R W SPI FIFO
147. and FIQ please refer to Chapter Interrupt CHAEN R W CHA Enable 0 Disable gt a Enable 2 jReewed o 1 Signed data Input 10 SRCEN R W SRC Mode Enable 0 Disable SRC controller Programmer must enable this bit to activate 17 Enable SRC controller DAC sample rate SRCRST R W Reset SRC 07 NG erect If this bit is set to 1 SRC will be reset And it 1 Reset SRC will be cleared to O after the SRC reset is done Before turning op the SRC programmers must write 1 to this bit AAA j C O T SRCFS R W Input Sample Rate Setup 0000 44 1KHz This register is valid only when SRCEN is set 0001 48KHz tom 0010 32KHz 0011 22 05KHz 0100 24KHz 0101 16KHz 0110 11 25KHz 0111 12KHz 1000 8KHz 1001 1111 Reserved P_CHA_Data 0x78F1 CHA DAC PWM Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CHADATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 CHADATA Channel A Data Register Generalplus Technology Inc PAGE 97 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_CHA FIFO 0x78F2 CHA FIFO Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3121110 Function FFUL FUDN FRST CHAFEILV CHAFINX Default 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 15 FFUL CHA FIFO
148. and 9600bps of UART buad rate is desired Then BUAD 48000000 9600 P IrDA Ctrl 0x7908 IRDA Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TXLT TPOL RPOL IEN ILP RXLT Default 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 165 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 15 12 TXLT R W Transmit Latency Time 0 no delay It defines the delay time between the time that 1 15 1 15 bit delay time the transmitter is finished and the time that the receiver starts 0 Positive Polarit 0 Negative Polarity IEN R W IrDA SIR Enable 0 Disabled If this bit is set to 1 the IrDA SIR Endec is 1 Enabled enabled This bit has no effect if the UART is not enabled by setting UEN Control bit as 1 When the IrDA SIR Endec is enabled IrDA data is transmitted and received on PortC9 and PortC10 respectively In other words these two pins cannot be used as GPIO at this time When the IrDA SIR Endec is disabled PortC9 and PortC10 are able to function as GPIO ILP R W IrDA SIR Low Power Mode Selection 0 2 normal mode fixed to If this bit is cleared to 0 low level data bits are 3 16 of corresponding bit transmitted as an active high pulse with 3 16 period of a bit period 1 low power mode fixed If this bit is set to 1 low level data bits are to 1 63
149. and minute interrupt 1 Enabled occurs hardware will issue an HMS IRQ7 to CPU f this bit is cleared to 0 this interrupt will be masked off Generalplus Technology Inc PAGE 89 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Second Interrupt Enable If this bit is set to 1 occurs hardware will issue an HMS IRQ7 to CPU will be masked off and second interrupt If this bit is cleared to 0 this interrupt o Half Second Interrupt Enable If this bit is set to 1 and half second interrupts occurrs hardware will issue an HMS IRQ7 to CPU will be mask If this bit is cleared to 0 this interrupt li B 0 Disabled 1 Enabled 0 Disabled 1 Enabled P_RTC_HMSBusy 0x7937 RTC HMS Busy Register Bit 15 14 13 1211111019 8 716 5 443 211 0 Function SEC BUSY MIN BUSY HR BUSY 94 J 4 4 lo Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O RTC Second Controller Busy Flag When this bit is 1 it means he RTC is busy on writing second to the register Programmers must wait until this bit je O in order to write further data to second register or shut down the system clock RTC Minute Controller Busy Flag When this bit is 1 it means the RTC is busy on writing minute to the register Programmers must wait until this bit is 0 in order to write furth
150. bit is set to 1 by hardware if touch panel interrupt is asserted Touch panel is at interrupt mode and a stylus is tapped on touch screen Touch Panel Interrupt Enable If this bit is set to 1 and at the time when stylus Je tapped on touch screen this hardware will issue an IRQ1 or FIQ to CPU To select between ARQO and FIQ please refer to Chapter Interrupt Touch Panel Interface enable When his bit is set to 1 PortB 15 12 Interface becomes Touch Panel These 1 0 pins cannot be used as GPIO function Touch panel stylus tapped status This bit is valid only when touch panel is at interrupt mode Touch Panel Mode Refer to Section Touch Panel Interface for detailed operation schemes Read 0 Not Occurred Read 1 Occurred Write 0 No Effect Write 1 Clear the flag 0 Disabled 12 Enabled 0 Disabled 1 Enabled 17 touch panel stylus tapped 07 touch panel stylus not tapped 0 Interrupt Mode 1 Operation Mode Note programmers set TSPX to high and Generalplus suggests wait a minute for stable when first time enabling touch panel function and then setting to interrupt mode This method is to avoid dummy TP interrupt occur at first time when touch panel is enabled and set to interrupt mode Generalplus Technology Inc PAGE 227 V1 0 Dec 20 2006 G Generalplus Bit Function Type Description GPL162002A 162003A Programming Guide C
151. change interrupt and external interrupts EXTA and EXTB In addition there are also interrupt flags which have the same function with these read only interrupt flags depicted in this chapter For example Reading from P_TimerA_Ctrl bit15 is the same with reading from P INT Status2 bit12 Generalplus suggests programmers do not use TimbaseA B C and scheduler as halt sleep mode wake up sources because the TimebaseA B C and scheduler interrupts occurs more quickly than the time that CPU wakes up from halt sleep mode As a result the TimebaseA B C and scheduler interrupt flags will not be held from halt sleep wake up Generalplus Technology Inc PAGE 56 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 6 2 Peripheral Interrupt Arrangement As depicted in Section Memory Vectors there are 11 interrupt events on Sunplus 16 bit CPU nSP Software Break Fast Interrupt FIQ Reset and IRQ 7 0 GPL162002A 162003A peripheral interrupts are distributed on nine of above interrupt sources FIQ and IRQ 7 0 The following table depicts the peripheral interrupt arrangement Note that some peripheral interrupts can be configured as FIQ or as one of IRQ refer to P INT Priorityf and P INT Priority2 control registers for details Interrupt Type Possible Peripheral Interrupt Flag Register FIQ Key Change Interrupt P INT Status1 TFT Under Flow Error Interrupt P_INT_Status2 TFT Frame End In
152. count by the sequence OxFFFC OxFFFD OxFFFE OxFEFF OxFFFC OxFFFD etc In other words the timer counter s overflow frequency is Source clock frequency 65536 Preload value Formula Timer Counter Overflow Interrupt Frequency Source clock frequency 65536 Preload Register Value Note that if external Input A EXTA PortD 12 is selected as counter clock source this pin cannot be GPIO function In other words any GPIO setting on PortD12 will be in vain Similarly if external Input B EXTB PortD13 is selected as counter clock source this pin cannot be GPIO function That is any GPIO setting on PortD13 will have no effect In addition TimerA TimerB and TimerC offer Capture Comparison Pulse Width Modulation CCP special functions If one of these three special functions is enabled Control Register 2 and CCP Register of TimerA TimerB and TimerC should be set up appropriately Note that TimerD to TimerF do not support CCP functions The following three sections will depict the detailed operations for CCP function Generalplus Technology Inc PAGE 69 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Capture Mode In capture mode the value in Timer Counter register is latched in Capture Comparison PWM registers CCP Register at the selected edge rising or falling of external I O pin PortB 2 0 The value in Timer Counter Register can be latched every rising
153. enable SAR ADC correspondingly To increase SAR AD conversion efficiency SAR ADC must not be initialized to build up internal reference voltage right before AD conversion operation Instead SAR ADC should be initialized for a Generalplus Technology Inc PAGE 214 V1 0 Dec 20 2006 A Generalplus GPL162002A 162003A Programming Guide 16 3 while before starting ADC data acquirement because of its long setup time In touch panel applications Generalplus recommends initializing SAR ADC right after power on or after sleep halt mode After all system requires SAR ADC to sample the x y coordinate value continuously on this case There is one control bit to turn off SAR ADC internal reference voltage by software set up by initialization operation Programmers should shut down SAR ADC internal reference voltage before GPL162002A 162003A enters sleep mode or halt mode Moreover programmers should re initialize SAR ADC again after power on and after wakeup from sleep halt mode if necessary Middle Power Consumption with uA de ree High Power Consumption with mA degree tl ADC BIAS reference voltage setup time ADC initalization Warm up time CPU Sleep or System Standby Note that while SAR ADC is turned on there will be larger power consumption Therefore the time interval when SAR ADC is enabled should be as short as possible Generalplus recommends enabling SAR ADC rig
154. flag 0 Not time out interrupt This bit will be clear H programmers write 1 1 Time out interrupt to CHOIF to clear interrupt flag d Generalplus Technology Inc PAGE 280 V1 0 Dec 20 2006 G Generalplus 19 7 Program Examples Momery to memory Read Finish r1 0x0200 P_DMA_Ctrl0 r1 r1 0x00 P_DMA_SRC_AddrL0 r1 r1 0x03 P_DMA_SRC_AddrHO r1 r1 0x5000 P_DMA_TAR_AddrLO r1 r1 0x00 P_DMA_TAR_AddrHO r1 r1 0x1902 P_DMA_TCountLO r1 r1 0x00 P_DMA_TCountH0 r1 r1 0x4009 P_DMA_Ctrl0 3r1 r1 P_DMA_INT test r1 0x01 jz Read Finish r1 0x01 P_DMA_INT r1 jmp GPL162002A 162003A Programming Guide DMA channel Reset Set source address to 0x30000 JI Set target address to 0x5000 JI Transfer length 0x1902 Single transfer mode target amp source 16 bit memory to memory disable DMA interrupt source address amp target address increase JI DMA issue interrupt when P DMA TCount reach 0 and don t care the DBF software mode Generalplus Technology Inc PAGE 281 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 20 SD and MMC Memory lO Card Controller 20 1 Introduction Secure Digital SD memory card is a Flash based memory card that is specifically designed to meet the security capacity performance and environment requirements inherent in newly emerging audio and video consumer electro
155. gain 0 or 20dB R On chip programmable gain amplifier for MIC input gain 33 31 5 30 12 dB W On chip volume control for line in amp FM in gain 12 10 5 9 4 33 8 dB W On chip anti aliasing filter W Analog oversampling third order sigma delta modulator for ADC R On chip digital decimation comb filter amp decimation FIR niers e 12 288MHz master clock frequency for ADC SAR ADC Control Six channels of the 12 bit SAR ADC are built in GPL162002A 162003A Two channels are dedicated for touch panel named TP channels other four channels are defined as general purpose line input LINEIN1 LINEIN2 LINEIN3 and LINEIN4 These four channels are very suitable for system voltage detection and other general purpose usage GPL162002A 162003A SAR AD conversion process is done automatically by hardware Initializing and enabling ADC is two necessary steps to make GPL162002A 162003A ADC work properly SAR ADC is Unable to work without being initialized even when ADC is enabled and vice versa JInitialing SAR ADC is to build up internal reference voltage for itself It takes approximate 100 milliseconds ms to complete the initialization After initialization GPL162002A 162003A power consumption will increase several hundreds of micro amp uA On the other hand enabling ADC is to turn the SAR ADC module on It takes only several microseconds us but it will consume more than 2mA There are two control bits to Initialize and
156. in the meantime the device sends a NAK Write 0 No effect Write 1 to clear this bit Write 1 Clear the flag Bulk Out Packet Ready Read 1 Ready This bit is set if an OUT packet is loaded into Read 0 Not ready the bulk out FIFO Write 1 to clearthis bit or Write O No effect its cleared automatically if the OUT packet is Write 1 Clear the flag read from MCU and P USBD EPAutoSet 3 is 1 Bulk Out Packet Enable Write 1 Enable Write Ion this bit to enable receiving incoming packets for BULK OUT data This bit is automatically cleared after the packet is loaded to bulk out FIFO in DMA mode or BOPR is set to 1 Writing 1 to P USBD EPEwvntClear 4 will clear this bit Bulk IN NACK Read 1 2 Occurred This bit is set if an IN request happens but Read 07 Not occurred the device sends a NAK Write 1 to clear Write 0 No effect this bit Write 1 Clear the flag Bulk IN Packet Clear Read 1 Occurred This bit is set if an IN packet is read from the Read 0 Not occurred host Write 1 to clear this bit Write 0 No effect Write 1 Clear the flag Generalplus Technology Inc PAGE 188 V1 0 Dec 20 2006 G Generalplus R W W NW EOSNA EOSEN EOINNA EOINPR EOONA EOOPR Generalplus Technology Inc GPL162002A 162003A Programming Guide Bit Function Type Description Condition Bulk IN Packet Ready Set this bit to indicate BULK IN packet
157. interface TimerC Interrupt Flag 0 Not Occurred This bit is set to 1 by hardware if the TimerC 1 Occurred Up counter overflow or Capture or Comparison event interr pt is asserted For details refer to chapter Timer Counter interface TimerB Interrupt Flag 0 Not Occurred This bit is set to 1 by hardware if the TimerB Up counter 12 Occurred overflow or Capture or Comparison event interrupt is asserted For details refer to chapter Timer Counter interface TimerA Interrupt Flag 0 Not Occurred This bit is set to 1 by hardware if the TimerA Up counter 1 Occurred overflow or Capture or Comparison event interrupt is asserted For details refer to chapter Timer Counter interface Key Scan Interrupt 0 Not Occurred This bit is set to 1 by hardware if the Key Scan is 1 Occurred finished For details refer to chapter Key Scan interface Generalplus Technology Inc PAGE 62 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 10 TMBCIF TimeBaseC Interrupt Flag 0 Not Occurred This bit is set to 1 by hardware if the TimebaseC 1 Occurred interrupt is asserted For details refer to chapter TimeBase interface TMBBIF TimeBaseB Interrupt Flag 0 Not Occurred This bit is set to 1 by hardware if the TimebaseB 1 Occurred interrupt is asserted For details refer to chapter TimeBase interface TMBAIF TimeBaseA Interrupt Flag 0
158. is ready the BULK IN FIFO automatically if MCU writes 64 bytes data and P USBD EPAutoSet 2 is 1 After this bit is set to 1 the hardware will send the data to the Host This bit is cleared by hardware when the in Its set data transaction is finished EPO Status NACK This bit is set if the request of status transaction happens but the device sends a NAK Wirte 1 to clear the bit EPO Status Enable This bit is set to enable the transaction in status stage It s automatically cleared if the status stage is finished Besides it s set automatically if the status stage is finished and P USBD EPAutoSet 5 is 1 EPO IN NACK This bit is set if an IN request happens but the device sends a NAK Wirte 1 to clear the bit EPO IN Packet Ready Set this bit to indicate IN packet is ready in the EndpointO FIFO It s set automatically if bytes IN P USBD EPAutoSet 1 is 1 is set to 1 to the Host This bit is cleared by hardware when the data and After this bit the hardware will send the data there are 8 data transaction is finished EPO Out NACK This bit is set if an OUT packet happens but the device sends a NAK Wirte 1 to clear the bit EPO Out Packet Ready This bit is set if an OUT packet is loaded into the endpointO FIFO Write 1 to clear the bit or its cleared automatically if the OUT packet is read from MCU and P USBD EPAutoSet 0 is 1 PAGE 189 Write 1 Packet is ready Read 1 2 Occ
159. lon enable headphone R L power MS enable lenable CHA enable CHA interrupt lenable CHB D Sound A 1 Clear Channel A FIFO Empty Interrupt Generalplus Technology Inc PAGE 111 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Fetch CHA Data CHB ReadResourceData_B D_Sound_B P_CHB_Data r1 J Fetch CHB Data jmp endirq0 pop r1 from sp endirq0 reti Note ReadResourceData is MACRO NENNEN Generalplus Technology Inc PAGE 112 V1 0 Dec 20 2006 G 11 2 Generalplus GPL162002A 162003A Programming Guide 11 STNLCD 11 1 Introduction The GPL162002A 162003A contains a powerful STN LCD controller and it can support resolution up to 320 H X 320 V and support 16 gray levels for monochrome STN or 4096 colors for color STN The LCD controller also has a built in hardware scroll function to reduce software overhead Moreover the interface supports flexible 1 bit 4 bit or 8 bit data interface to connect with a variety of LCD panels The LCD controller in GPL 162002A 1620034A has the following features Supports standard STN LCD panel driver interface Built in frame rate control for gray and color display Supports standard 1 4 8 bit LCD driver Interface Supports monochrome 4 gray levels and 16 gray levels e Supports 2 4 16 256 and 4096 colors display Supports virtual display screen up to 1024 x 1024 for ha
160. nnt raus ornata ance ka saceecacedsaceesuuessncestecteanie 263 19 1 Insee m denses 263 19 2 silere a BJF To TETTE EE OTT 264 19 3 r 264 19 31 Single emm 264 19 3 2 Demand Mode sien a ns SEENEN dee cis 265 Generalplus Technology Inc PAGE 6 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 19 4 Bele MsiiMu 265 19 5 Byte Mode Op ration e 266 19 6 Control E E EE 267 19 7 Program Tue EE 281 20 SD AND MMC MEMORY IO CARD CONTROLLER U U u rre 282 20 1 INTOdUCION geed Ee sde een annee eee qutu Cs 282 20 2 lole ll Cl 282 20 3 Command Line e lt ne EE 283 20 4 Data Line OT 0 4 1160 m 283 20 5 Card Insertion Detection coccion catre ANN 284 20 6 Multi Block Read Write es e W 284 20 7 SD MMC Control Pin Configuration pnm thee ne MA hs 284 20 8 Control Register cion POS Noi ae EE 285 20 9 Example deel olla cc MMM E 292 21 KEY SCAN CONTROLLER coito Nem AP in E 294 21 1 Jurte e o EE wn Y m 294 21 2 Key Scan FUNCHON issues L aS Qu uuu uu Pe Af eet 294 21 3 Key Scan Application Circuit e uer 294 21 4 Sample Time Configurations Be Masse 290 21 5 Auto Manual SampleMgdeN 3 ANEREN u 297 21 6 Automatically Detect Key bmmcess ie 297 21 7 Key Scan Control Pin Configur tiort
161. no in FIFO gt 4 4 read is allowed 100 data no in FIFO gt 5 5 read is allowed 101 data no in FIFO gt 6 6 read is allowed 110 data no in FIFO gt 7 7 read is allowed V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition 111 data no in FIFO gt 8 8 read is allowed jReeved c RX FLAG Receive FIFO Data Level 000 0 byte in FIFO This register indicates how many data 001 1 byte in FIFO have been received in receive FIFO 010 2 bytes in FIFO 011 3 bytes in FIFO 100 4 bytes in FIFO 101 5 bytes in FIFO 110 6 bytes in FIFO 111 bytes in FIFO P_UART_TXDLY 0x7906 UART TX Delay Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TWT Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 usal Reseed e 0 x o 3 0 TWT R W Transmitter Waiting time It is used to make 0 no delay a delay between two transmitting bits 0001 1111 1 15 bits dela P_IrDA_BaudRate 0x7907 IrDA Baud Rate Setup Register Bit 15 144 13 12 11 510 9 8 7 6 5 4 3 2 1 0 Function BUAD Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 BUAD IrDA Buad Rate control _ The Buad rate system clock BUAD For example system clock is 48MHz
162. noted if the TD in P DMA Ctrl 11 10 is set as lO to memory or IO to IO mode this register is useless Generalplus Technology Inc PAGE 273 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_DMA TAR_AddrH0 0x7B85 DMA Target High Address Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR_AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA TAR_AddrH1 0x7B8D DMA Target High Address Register 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR_AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_TAR_AddrH2 0x7B95 DMA Target High Address Register 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA TAR AddrH3 0x7B9D DMA Target High Address Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 10 Reserved go TAR_AddrH DMA Target High Address 25 16 Po The P DMA TAR AddrHx registers are the destination high address 25 16 registers The value in these registers will be increased decreased when a word is written a
163. of these modes is enabled direction attribution data control bits are forced to The direction corresponding mode contents on attribution data control bits have no effect on this I O pad Key change1 Input pull high or low P_MINT_Ctrl bit 12 1 MEI GPIO All modes pU IOB2 Pin Special Function Shared Information Special Function TimerC Capture Mode 1 0 Mode Supported Floating Output Buffer High or Low Trigger Input TimerC Comparison Mode Event Output TimerC PWM Mode Output Buffer High or Low Signal Output Key change2 Input pull high or low P MINT Ctrl bit 14 1 i GPIO All modes Generalplus Technology Inc P TimerC CCP Ctrl bit 15 14 01 P_TimerC_CCP_Ctrl bit 15 14 10 P TimerC CCP Ctrl bit 15 14 11 PAGE 46 Enable Control bit Description When one of these modes is enabled direction attribution data control bits are forced to The direction corresponding mode contents on attribution data control bits have no effect on this I O pad V1 0 Dec 20 2006 G 5 3 Generalplus GPL162002A 162003A Programming Guide 5 2 General Purpose I Os Configuration GPL162002A 162003A provides a bit to bit I O configuration every I O configuration can be defined individually To set up a bit configuration three control registers must be setup Data Attribution and Direction The following table is a summary of UO configuration
164. off DAC for designated sleep time to 10 32768 DACRC reduce white noise 11 65536 DALRC Generalplus Technology Inc PAGE 101 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide PP note DAL is 48KHz 5 4 AS RANGE R W Auto Sleep code Variation Range These bits are to set auto sleep code level condition When auto sleep function input data matches AS RANGE setup value auto sleep condition exists 1 Power down mode 1 Power down mode 1 IIS R W Internal IIS Format Select 0 right justified mode This control bit is to set internal IIS mode 1 shift 1 bit mode The IIS mode setting must be the same with setting of IIS MODE 0x78FF b gt 3 2 Besides if using internal DAC IS mode the IIS left justified mode 0x78FF b 3 2 710 is not supported DACLK R DAC Main Clock Enable 0 Disable DAC clock The DAC needs an 18 432MHz clock for 1 Enable DAC clock digital filter Before enabling the DAC Programmers must enable the DAPLL 0x7807 b4 and wait it stable and then set this bit to 1 to initialize DAC clock P HPAMP Ctrl 0x78FE Headphone Amplifier Control Register Bit 15 14 13 12 1140 9 8 7 6 5 4 3 2 1 0 Function A v P PWSPVR SPINS PWSPL PWSPR Default 0 0 O70 0 0 0 0 0 0 0 1 0 0 1 1 CEST 7 Reseed PE 4 PWSPVR R W Headphone Direct Dri
165. or falling edge of external I O pin refer to control register 2 for details When a capture occurs the interrupt flag is set and CPU is interrupted via IRQ4 The interrupt flag must be cleared by firmware Note that if another capture occurs before the value in the CCP Register is read the old captured value will be lost That is the clock frequency from external I O pin has to be at least one half of the timer counter s clock source frequency The corresponding GPIO pin PortB 2 0 for the timer counter is configured as INPUT pin automatically when TimerA TimerB or TimerC is set as capture mode Trigger Logic CCPIC A PORTB 2 0 Rising or Falling Timer C A 16 bit Edge Trigger Preload Register V ED E I gt CPU Interrupt Latch In Enable IRQ4 Up Counting start from the value in 16 bit Timer Preload Register Timer C A Enable Control bit Ti C A imer C i Timer C A 16 bit Timer C A 16 bit Up Count CCP Register Clock Source Timer Counter Timer C A Capture Mode Function Diagram When TimerA TimerB or TimerC is configured as capture mode P_TimerX_CCP_Ctrl bit 15 14 01 programmers can enable disable clear and read status of the corresponding capture event interrupt by accessing D TimerX Ctrl bit 15 14 At this time timerA TimerB or timerC up counter overflow interrupt will have no effect on any operation of P TimerX Ctrl bit 15 14 In other words
166. read it CS1 Memory Device Access Wait State 5 4 TT 3 0 UT Setup Criterion CS1WAIT 3 0 1 SYSCLK cycle gt memory device access time 64Kword Size Range 64K word 16384K word 00 ROM SRAM 012 ROM SRAM 102 NOR Flash 117 NAND Flash WARWATT 1 0 SYSCLK Range 0 15 Tw CS1WAIT 3 0 1 SYSCLK P MCS2 Ctrl 0x7822 CS2 Device Control Register Bit 15 14 13 12 11 40 9 8 7 6 5 4 3 2 1 0 Function CS2SIZE CS2MD WARWAT CS2WAIT Default 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Bit Functon Type Description Conaition 15 8 CS2SIZE R W Memory Device Size on Chip Select 2 CS2 unit is 64K words CS2SIZE 7 0 1 defines the number of page for the entire memory device on CS2 Page size is 64K word CS2 Memory Device Access Mode other memory type 5 4 WARWAT RW SRAM Write after Read Wait State When data is written to memory and then read it immediately from the same address CPU will wait WARWAT 1 0 SYSCLK to read it Generalplus Technology Inc To define which memory device on CS2 such as ROM SRAM NOR or NAND Flash memories If NAND Flash is selected the MCS2 pin will keep low until it is changed to CS2 Memory Device Access Wait State Setup Criterion CS2WAIT 3 0 1 SYSCLK cycle PAGE 31 Range 0 255 Size CS2SIZE 7 0 1 64Kword Size Range 64K word 16384K word
167. read the status from I O PortC external pads P IOC Buffer 0x7871 IOC Buffer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOCBUF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 IOCBUF R W Executing the read operation in this IOCBUF R IOCDATA W register will read the setup value from IOCBUF W VO Port data register which is previously latched by IOCDATA writing operation P IOC Dir 0x7872 IOC Direction Register Bit 151 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOCDIR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L Generalplus Technology Inc PAGE 51 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Conaition 15 0 IOCDIR R W This control register sets the direction of UO Refer to the above table PortC In addition the direction setup VO port configuration and value can be read back from the same function control register P IOC Attrib 0x7873 IOC Attribution Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOCATT Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 IOCATT R W This control register defines the attribution Refer to th
168. same time the data is also shifted in through slave device SDI pin When the transmitting FIFO level is lower then the interrupt trigger level the SPITXIF flag bit will be set besides a SPI interrupt will be generated if the SPITXIRQEN bit is set When the receiving FIFO level is higher then the interrupt trigger level the SPIRXIF flag bit will be set besides a SPI interrupt will be generated if the SPIRXIRQEN bit is set Programmers can read SPI data from SPIRXD control register The following diagram depicts the timing scheme on SPI master mode for different operation types polarity control bit equals 1 or 0 phase control bit equals 1 or 0 and sample strobe control bit equals 1 or 0 Slave Mode In slave mode the SPICLK becomes an input pin that receives external clock And all clock and data are valid when SPICSN is at low state In GPL162002A 162003A SPI slave mode only supports polarity 0 and phase 0 mode Each time when starting to transmit data to a slave GPL162002A 162003A the SPICSN needs to switch to low for GPL162002A 162003A SPI clock and data synchronous and needs to switch SPICSN to high when data transmission is finished L Generalplus Technology Inc PAGE 169 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide spiCLK _ LJ LI LE LI LI LI LI LI 1 SPICSN SPITX Fig1 Master Mode POLARITY 0 PHASE 0 At this setting GPL1
169. the specific interrupt would also clear this bit Standard Command Interrupt Read 1 Occurred This bit is set if one of standard command Read 0 Not occurred interrupts happens except GET SET Descriptor Writing 1 to clear the specific interrupt would also clear this bit Power Management Interrupt Read 1 Occurred This bit is set if one of power management Read 0 Not occurred interrupts happens Writing 1 to clear the specific interrupt would also clear this bit Interrupt In interrupt Read 1 Occurred This bit is set if one of INTERRUPT_IN interrupts Read 0 Not occurred happens Writing 1 to clear the specific interrupt would also clear this bit Bulk Out Interrupt Read 1 Occurred This bit is set if one of BULK OUT interrupts Read 0 Not occurred happens Writing 1 to clear the specific interrupt would also clear this bit Generalplus Technology Inc PAGE 190 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition Bulk In Interrupt Read 1 Occurred This bit is set if one of BULK IN interrupts Read 0 Not occurred happens Writing 1 to clear the specific interrupt would also clear this bit EndpointO Interrupt Read 1 Occurred This bit is set if one of endpointO interrupts Read 0 Not occurred happens Writing 1 to clear the specific interrupt would also clear this bit P_USBD_INTEN 0x7B39 USB Interrupt Ena
170. to chapter USB interface 1 Occurred 2 DMA DMA transfer complete interrupt 0 Not Occurred This bit is set to 1 by hardware if the one of the 1 Occurred DMATCR of DMA channels reaches 0 and the Generalplus Technology Inc PAGE 61 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide corresponding DMA interrupt is enabled For details refer to chapter DMA Controller 1 EXTBIF R W External Interrupt B status Read 0 Not Occurred Write 1 to clear the flag Read 1 Occurred This bit is set to 1 by hardware if the external Write O No Effect interrupt B is asserted Write 1 Clear the flag EXTAIF R W External Interrupt A status Read 0 Not Occurred Write 1 to clear the flag Read 1 Occurred This bit is set to 1 by hardware if the external Write O No Effect interrupt A is asserted Write 1 Clear the flag P_INT_Status2 0x78A1 Interrupt Status 2 Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMDIF TMCIF TMBIF TMAIF KSIF TMBCIF TMBBIF TMBAIF SD I2C NAND SCHIF ALMIF HMSIF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TimerD Interrupt Flag 0 7 Not Occurred This bit is set to 1 by hardware if the TimerD 1 Occurred Up counter overflow or Capture or Comparison event interruptis asserted For details refer to chapter Timer Counter
171. users should take care of the bandwith of LCD occupying data bus The factors include the wait cycle for external memory the color gray mode the size of LCD panel and the Frame rate of color gray display in LCD panel The formula of downgrade factors The percentage that STN TFT LCD interface occupies bus bandwidth equals to LCD Segment x LCD Common x LCD BPP x LCD Frame Rate x LCD Wait 16 PLL Clock where LCD BPP display mode 1 2 4 8 12 or 16 bit per pixel LCD Wait 7 extra wait cycle of LCD buffer for enough external memory accessing time This value is the same with the value in P MCSx Ctrl CSx depends on which LCD buffer is located Generalplus Technology Inc PAGE 393 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide If the LCD buffer is located in internal SRAM then LCD Wait 1 PLL clock depending on the value set in P Clock Ctrl LCD Frame Rate the enough frequency for color gray display For example PLL clock 48MHZ LCD Wat 3 It means the LCD Buffer access time is less than 3 PLL clock cycle X size x Y size x Frame rate BPP 1 BPP 2 BPP 4 BPP 12 320 240 156 25 4 6875 9 375 18 75 lt 56 25 7 320 240 125 3 75 45 60 320 240 60 174 21 6 348 160 160 125 1 25 15 20 25 7 Audio Output Components Selection Guide DAC Output RC circuit vs frequency response For DAC audio output the external audio driv
172. will keep low until it is changed to other memory type 5 4 WARWAT RAW SRAM Write after Read Wait State WARWAT 1 0 SYSCLK When data is written to memory and then read it immediately from the same address CPU will wait WARWAT 1 0 SYSCLK to read it 3 0 CSOWAIT R W CSO Memory Device Access Wait State Range 0 15 Setup Criterion Tw CSOWAIT 3 0 1 CSOWAIT 3 0 1 SYSCLK cycle SYSCLK gt memory device access time P MCS1 Ctrl 0x7821 CS1 Device Control Register Bit 15 14 13 12 11 1101 9 8 7 6 5 4 3 2 1 0 Function CS1SIZE CS1MD WARWAT CS1WAIT Default 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 15 8 CS1SIZE R W Memory Device Size on Chip Select 1 CS1 Range 0 255 unit is 64K words CS1SIZE 7 0 1 defines Size CS1SIZE 7 0 1 Generalplus Technology Inc PAGE 30 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide the number of page for the entire memory device on CS1 Page size is 64K word 7 6 CS1MD CS1 Memory Device Access Mode To define which memory device on CSO such as ROM SRAM NOR or NAND Flash If NAND Flash is selected the MCS1 pin will keep low until it is changed to memories other memory type SRAM Write after Read Wait State When data is written to memory and then read it immediately from the same address CPU will wait WARWAT 1 0 SYSCLK to
173. 0 15 0 IOBATT This control register defines the attribution of I O Refer to the above table PortB In addition the attribution setup value VO port configuration can be read back from the same control and function register P IOB Latch 0x786C IOB Latch for Key Change Wakeup Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOBLHW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 50 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide usaf Rea 2 0 IOBLHW This control register latches the I O PortB status for key changed wake up purpose Wake up is triggered if any I O state of PortB is different from at the time latched This latch operation must be done before entering sleep mode for more information refer to Chapter System Control P IOC Data 0x7870 IOC Data Register Bit 151 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOCDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Descriptin C nditiom 15 0 IOCDATA R W Executing the writing operation Ins Refer to the above table register will latch setup value into 1 0 PortC I O port configuration and qata register Similarly executing the read function operation in this register will
174. 0 Address Value Write 3 cycle and 4 cycle of Address value to the register and then NAND FLASH interface will write this Address value to NAND FLASH memory Some of Nand Flash commands only take two address cycle such as Block erase however programmers still need to write dummy values to P_NF_AddrH register Otherwise the address will not be sent to the Nand Flash L Generalplus Technology Inc PAGE 237 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_NF Data 0x7854 NAND Flash Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function NFDATA Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Description Condition NFDATA Read Write Data instruction Write Data value to the register and NAND FLASH interface will write this Data NAND Flash automatically A Read operation will read value to memory Data value from NAND Flash memory 15 0 Data Value 16 bit type Nand Flash 7 0 Data Value 8 bit type Nand Flash When the Nand Flash is 8 bit type the data in P NF Data 15 8 register is invalide The data value written to read from the Nand Flash is effective only in the lower byte of the P NF Data register When the Nand Flash is 16 bit type the data in P NF Data is all valid P NF INT Ctrl 0x7855 DMA INT Control Register Bit 15
175. 0 RX Data is not Ready 1 and the data number in receiving Read 1 RX Data is Ready Generalplus Technology Inc PAGE 160 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide FIFO is more or equal to eight This bit is cleared to 0 by hardware if data number in receiving FIFO is less than eight In other word receive interrupt is cleared by reading data from the receive FIFO until it becomes less than eight data For FIFO is disabled 1 depth FEN 0 This bit is set to 1 by hardware if the receiving interrupt enable bit is set to 1 and the data is received completely The receive interrupt is cleared by performing a single read of receive data register P_UARTIrDA_Data Transmit Interrupt Flag If FIFO is enabled For FIFO is enabled 8 depth Read 0 no in TX FIFO gt 8 FEN 1 Read 1 no in TX FIFO lt 8 This bit is set to 1 by hardware if the If FIFO is disabled transmitting interrupt enable bit is set to Read 0 TX Buffer is not Ready 4 andithe data number in transmitting Read 1 TX Buffer is Ready FIFO is less or equal to one This bit is cleared to 0 by hardware if data number in transmitting FIFO is more than one In other word transmitting interrupt is cleared by filling data to transmitting FIFO until it becomes more than one data For FIFO is disabled 1 depth FEN 0 This bit is set to 1 by hardwa
176. 0 0 Generalplus Technology Inc PAGE 268 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P DMA Ctrl3 0x7B98 DMA Channel Control Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function WriteReq TM TARByte SRCByte TD RS CIE SF DF SD DD DB NOR Mod BS CE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Type Description Condition WRITEREQ R W Pheripheral Write Request Byte Mode Indicate that the request from a peripheral needs to be written or read This bit is only valid when SRCBYTE or TARBYTE is 1 and MODE is 1 External Mode R W Transfer Mode Field This bit is used to indicate single transfer mode or demand transfer mode Note that this bit is only valid when MODE is set to 1 external mode Indicate if the target is in byte mode or not 12 SRCBYTE R W Source Byte Selection Indicate if the source is in byte mode or not R W Transfer direction field These two bits are used to select DMA transfer direction Software reset If this bit is set to 1 the values of control register in this channel will be reset to RS W default 4 R W Channel Interrupt Enable is set to P DMA TCount reaches 0 hardware will issue an IRQ3 or FIQ to CPU If this bit is 0 this be masked To select between IRQ3 or FIQ cleared to interrupt will please refer to Chapter Inter
177. 0 0 0 0 0 Bit Function Type Description Condition 15 8 BIBWP Bulk IN Buffer Write Pointer These bits are used as the write pointer of Bulk IN FIFO 7 0 BIBRP Bulk IN Buffer Read Pointer These bits are used as the read pointer of Bulk IN FIFO Generalplus Technology Inc PAGE 199 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_USBD_BOBufPointer 0x7B45 USB Bulk OUT Buffer Pointer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BOBWP BOBRP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 BOBWP Bulk OUT Buffer Write Pointer These bits are used as the write pointer of Bulk OUT FIFO 7 0 BOBRP Bulk OUT Buffer Read Pointer These bits are used as the read pointer of Bulk OUT FIFO P USBD EPORTR 0x7B46 USB Endpoint0 bmRequestType Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EPORTR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description gt Condition neg Reewd KT 7 0 EPORTR EPO bmRequestType These bits are used as the Request Type of setup commands P USBD EPORR 0x7B47 USB Endpoint0 bRequest Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EPORR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fet ne pss 10 Reserved 0 EPORR EPO bRequest These bits ar
178. 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 6 Reserved 5 RWIPEN R W Remote Wakeup Enable 0 Remote Wakeup is not If this bit is set to 1 the remote wakeup supported is supported Or itis not supported 1 Remote Wakeup is supported SPWR RW Self Power of Device 0 USB device is bus powered This bit is used to indicate if USB device 1 USB device is self powered is self powered or not USBEN R W USB Transceiver Enable Write 1 to this bit to enable the USB transceiver Generalplus Technology Inc PAGE 182 V1 0 Dec 20 2006 G Generalplus Function Description Condition GPL162002A 162003A Programming Guide TNSPL TNSPH BYPASS USB Transceiver Pull Low Write 1 to this bit D and D are pulled down with 15K Ohm USB Transceiver Pull High Write 1 to this bit D is pulled high with 1 5K ohm USB Bypass Mode transceiver 0 Bypass disable is disabled 1 Bypass enable the inner USB P_USBD_Device 0x7B57 USB Device Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 81211 0 Function EP4 Type EP3 Type EP2 Type EP1 Type EP4 lO EP3_lO EP2 IO EP1 1O MOD Default 0 1 1 1 1 0 1 0 0 1 0 1 000 0 Bit Function Type Description 7 Condition Endpoint4 Type These two bits are used to indicate the type of endpoint4
179. 0 0 0 0 0 0 0 0 0 P TFT PIP1 V END 0x7D27 TFT PIP1 Vertical End Location in Each Frame Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1_V_END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP2_V_END 0x7D32 TFT PIP2 Vertical End Location in Each Frame Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2 V END Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP3_V_END 0x7D3D TFT PIP3 Vertical End Location in Each Frame Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP3 V END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 psp 700000000000 PIPZ V END R W The PIP frame vertical end location in the main frame See the following diagram for details H Generalplus Technology Inc PAGE 150 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide PIP Position diagram PIX NUM DMA SA ain Frame WIS A did PIP H STR WAN ANTI Ee d ID I PIP Scrolling Duagram PIP Virtual Start Address PIP Virtual Start Address Loop PIP Virtual End Address PIP Virtual End Address Generalplus Technology Inc PAGE 151 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 12 6
180. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Description Condition DataRX SD MMC Data Receive Register Read data from SD card read data from this register will only valid when the DATBUFFULL is set otherwise it will return zeros Generalplus Technology Inc PAGE 285 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Data receive register This register is used to store the data read from the SD card When 16 bit data is received DATBUFFULL bit in status register will be set or the DMA request will be issued It should be noted data could be read from this register only when DATBUFFULL is 1 P_SD CMD 0x79D2 SD MMC Command Regisiter Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 21 110 Function RespType IniCard MulBIk TranData CmdWD RunCmd StpCmd CmdCode Default 0 0 0 0 0 0 0 0 0 0 0000 04 0 Bit Function Type Description Condition 15 Reserved 14 12 RespType R W Response Type Selection 000 Norresponse Indicate the response type of this command 001 Response type R1 Currently only the response type R2 has 010 2 Response type R2 response length 128 bits all other response 0117 Response type R3 will have 32 bits in length Response type 110 Response type R6 R1b will keep the controller to wait for busy 111 2 Response type R1b signal on the SD bus 11 IniCard Initial Card Write This Bit to
181. 0 0 1 0 0 0 0 P UARTIrDA FIFO 0x7905 UART IrDA FIFO Control Register Bit 15 14 134 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TX LEVEL TX_FLAG RX_LEVEL RX_FLAG Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_UART_TXDLY 0x7906 UART TX Delay Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TWT Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_IrDA_BaudRate 0x7907 IrDA Baud Rate Setup Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BUAD Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 342 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P IrDA Ctrl 0x7908 IRDA Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TXLT TPOL RPOL IEN ILP RXLT Default 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 P IrDALP 0x7909 IrDA Low Power Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IrDALP Default 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 SPI Control Register Summary Table Name Address Description 2 P SPI Ctrl 0x7940 SPI Control Register P SPI TXStatus 0x7941 SPI Transmit Status Register P SPI Ctrl 0x7940 SPI Control
182. 00 0x0000_77FF 0x0000_8000 0x0002_7FFF Reserved Memory 0 0x0003_0000 Memory 1 Memory 2 H Generalplus Technology Inc PAGE 25 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 2 EMU mode When BM 1 0 01 or 11 GPL162002A 162003A boot from external memory instead internal ROM In this mode IC pin BKCSB5 EMUCE will change to low when CPU access address from 0x8000 to Ox27FFF The memory mapping of EMU mode is shown below BOOT EMU ROM 0x0000_0000 0x0000_77FF 0x0000_8000 m d EMU memory 0x0002 7FFF Reserved 0x0003 0000 Memory 2 Generalplus Technology Inc PAGE 26 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 3 MCSO boot mode When BM 1 0 00 GPL162002 will boot from external MCS0 memory In this mode default internal rom area OXF800 0xFFFF are mapped to 0x3F800 0x3FFFF We call these areas as CPU boot code area And the area size can be adjusted dynamically by setting control register P_MAPSEL 0x7816 The memory mapping of MCS0 boot mode is shown below BOOT MCS0 ROM 0x0000_0000 RAM 30KW 0x0000_77FF 0x0000_8000 Peripheral System Control Embadded ROM 30KW The same mapping 0x0000_F800 0x0001_0000 Embadded ROM 96KW 0x0000_F800 0x0002_7FFF Reserved 0x0003_0000 0x0003_F800 0x0003_FFFF Memory 3 Memory 4 For
183. 00 4 data is in FIFO 00101 5 data is in FIFO 00110 6 data is in FIFO 00111 7 data is in FIFO 01000 8 data is in FIFO 01001 9 data is in FIFO 01010 10 data is in FIFO 01011 11 data is in FIFO 01100 12 data is in FIFO 01101 13 data is in FIFO 01110 14 data is in FIFO 01111 15 data is in FIFO 10000 16 data is in FIFO 10001 11111 Reserved 3 0 FIFOLEV Auto Sample Mode FIFO Full Interrupt Level This number of ADC sampled data in the 16X16 bit ring type FIFO read only flag reports the P_ASADC Data 0x7964 Auto Sample Data register Bit 15 11 10 9 8 7 6 5 4 3 2 1 0 Function ASADC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 Generalplus Technology Inc PAGE 226 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Condition ASADC Description Auto Sample Mode FIFO Data If auto sample mode FIFO is not empty programmers can obtain ADC data from this control register P_TP_Ctrl 0x7965 Touch Panel Control Register Bit 15 14 13 12 11 101918171615 4 3 2 1 0 Function TPIF C TPIEN TPEN TPST TMOD DBEN DBTSEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Type Description Condition TPIF C RW R W R W TMOD R W Touch panel interrupt flag This
184. 002A 162003A Programming Guide 25 4 1 Power Adjustment amp Selection There are three ways to supply DC power for GPL162002A 162003A EMU Board If the board is powered LED indicated as D11 will be turn on e PW1 Direct power input bypass 5V regulator e PW2 Direct power input bypass 3 3V regulator and 5V regulator When this mode is used the USB power 5V is not provided e J5 Adapter DC input on board regulators 5V and 3 3V are activated Input voltage should higher than 6V 25 4 2 Reset The switch S12 labeled with RESET resets the system manually and initializes GPL162002A 162003A emulation board 25 4 3 ICE JP51 JP52 labeled with ICE are the connectors for attaching ICE Probe 25 4 4 12MHz Crystal In GPL162002A 1620034 users can select to use external 12MHz crystal or not When the external 12MHz crystal is used users should turn on the DIP switch 1 on S11and switch SW2 to 12M side When the external 12MHz crystal is not used users should turn off the DIP switch 1 on S11 and switch SW2 to None side Generalplus suggests that when the built in USB function GPL162002A 162003A is used users should enable the external 12MHz crystal 12M SW 2P2T None S R17 C31 C32 7 5K 33pF 33pF C35 3 3nF C36 47nF Generalplus Technology Inc PAGE 375 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 25 4 5 CPU Boot mode
185. 002A 162003A Programming Guide interface is used turn on corresponding switches on S1 which interconnect GPL162002A 162003A and PortB socket Referenced as JP19 and JP20 labeled with IOB JP1 is the header for 2 general purposed analog inputs line1 and Line2 and users can connect external device to internal ADC via this header Note that Line1 and Line2 are dedicated pins of GPL162002A 162003A and Line3 Line4 are shared with GPIO S1 JP2 TSPX TSPY TSMX HEADER 4 TSMY SW DIP 4 SW8 is used to select microphone bias voltage provided Tram VDD power or from GPL162002A 162003A MIC bias output If GPL162002A 162003A MIC bias voltage is used the MIC bias control bit 0x7970 b1 should be enabled AVGCADC SW 2P2T C9 10uF R2 2 2K MICROPHONE MICIN 1uF SW1 is used to select AD recording input source The selection should correspond to bit 5 4 of control register for HQADC input source selection Generalplus Technology Inc PAGE 377 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 25 4 9 Others Input and Output UO Ports PortA Referenced as JP7 JP8 JP17 and JP18 labeled with IOA PortB Referenced as JP9 JP10 JP19 and JP20 labeled with JOB PortC Referenced as JP11 JP12 JP21 and JP22 labeled with IOC PortD Referenced as JP13 JP14 JP23 and JP24 labeled with IOD LCD Driver Interface Header Referenced as JP55 and JP
186. 006 G Generalplus 4 10 Program Examples R1 0x0041 P MCSO Ctrl R1 R1 0x0142 P MCS1 Ctr R1 R1 0x0383 P MCS2 Ctri R1 R1 Ox00CF P_MCS3_Ctri R1 GPL162002A 162003A Programming Guide SRAM 64KW 35ns access time 1 External CSO memory wait state 1 system cycle JI CPU memory mapping is 0x003_0000 0x003_FFFF SRAM 128KW 50ns access time JI External C81 memory wait state 2 system cycle JI CPU memory mapping is 0x0004_0000 0x0005_FFFF J FLASH 256KW 7Ons access time JI External CS2 memory wait state 3 system cycle JI CPU memory mapping is 0x006_0000 0x009 FFFF I NAND Flash O Generalplus Technology Inc PAGE 41 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 5 1 0 Ports 5 1 Available Ports The purpose of General Purpose Input Output GPIO is to communicate with other devices Four programmable UO ports are available in GPL162002A 162003A PortA PortB PortC and PortD Each I O pin on these 4 ports can be bit by bit configured by software Almost every I O pin on these 4 ports can be programmed as special function In other words many special function control signals share with I O ports Besides the PortB 2 0 provide wake up capability To change these 4 ports from GPIO functions to special functions programmers need to enable the corresponding special functions This is because special functions have hig
187. 0x7980 LCD Setup Register Bit 15 14 13 12 11 1019181 17 1619544131 ZA 0 Function FPIF C FPIEN LCDEN SELF PSEL BUSW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P LCD Clock 0x7981 LCD Clock Generation Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LCDCLK Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P LCD Segment 0x7982 LCD Segment Number Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LCDSEG Default 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 P LCD Common 0x7983 LCD Common Number Register Bit 15 414 13 142 11 10 9 8 7 6 5 4 3 2 1 0 Function LCDCOM Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P LCD Buffer LowAdr 0x7984 LCD Buffer Address A15 AO Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LCDBUFAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P LCD Buffer HighAdr 0x7985 LCD Buffer Address A25 A16 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LCDBUFAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NENNEN Generalplus Technology Inc PAGE 331 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P LCD Buffer Offset 0x7986 LCD Offset Size Bit 15
188. 0x7BOA USB Host Automatic In Transaction Byte Count Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function HAIBC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBH_AutoOutByteCount 0x7B0B USB Host Automatic Out Transaction Byte Count Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function HAOBC Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 351 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_USBH_AutoTrans 0x7B0C USB Host Auto Transfer Register Bit 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Function CAO CAI AOX AIX Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P USBH Status Ox7BOD USB Host Status Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TO CRC DE BS UP SH NH AH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P USBH INTF Ox7BOE USB Host Interrupt Flag Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Functio
189. 1 0 Dec 20 2006 A Generalplus GPL162002A 162003A Programming Guide B Audio output J2 PHONEJACK PHONEJACK E 0 JPG El ae HEADER 2 ovn io ddd aloo d aloo HEADER 2 en u2 al gt GPY0030 u1 7 6 A 8 E GPY 0030 AVCCDAC lt EA 7 6 AVCCDAC lt El N J TE RI w C20 J t di 1 R8 100 R3 Rh a 100 aw 100 1M em c22 c16 Gf c19 H e H 224 4 E 100u 100 224 u C23 ei a 1 3 c15 F 1 3 ed R11 R6 LG 10u 104 G8 C28 10u C21 H 0 01u 0 01u R o R5 1K 1K x zi o o L lt a a AVCCDAC PAMSSBAC DAC_RDAC_L ke kb o o lt lt a D AVCCDAC Y J3 Kei PHONEJACK STEREO o VL C29 ML C30 100u 100u x a lt Generalplus Technology Inc PAGE 383 V1 0 Dec 20 2006 G Generalplus C Clock X32KO asa ye X32KO X32KO gt gt X12MO x12M0 gt gt X12MI xM gt gt p gene PE X32KI PLLC C34 22pF C38 33nF GPL162002A 162003A Programming Guide 12M 1 Y 43 D OR 4 X12MI 55 P 6 fo t C SW2P2T None Y1 4 12M R17 631 C32 7 5K 33pF 33pF C35 3 3nF T N36 AZnF AN O Generalplus Technology Inc PAGE 384 V1 0 Dec 20 2006 A Generalplus GPL162002A 1
190. 1 0 Dec 20 2006 G Generalplus Bit Function type Description Condition GPL162002A 162003A Programming Guide This control bit is used to select CPU clock between 32768Hz and PLL clock When this bit is set to 1 the CPU clock will run at 32768Hz and PLL will be turned off no matter FAST bit is 1 or 0 TE C32K R W CPU Clock Selection 0 High speed clock PLLCLK 1 Low Speed clock 32768Hz aaf ea _ j R W 32768 Hz Crystal Weak Mode Enable This bit is used to control the strong weak mode of 32768Hz crystal pad After reset the 32768Hz crystal pad will be set to strong mode to ensure that 32768Hz Users can clock will start correctly choose to change the pad to weak mode l to save power after power on 0 32768 Hz Crystal Pad Operate in Strong Mode 1 32768 Hz Crystal Pad Operate in Weak Mode m Resna NT A IOBO 32768Hz Output Disable There will be a 32768 Hz output on IOBO write 1 to this bit will turn off this output IOBO 2 Key Change Interrupt Enable To turn op the key change wake up P function of these GPIO pins programmers I i FEN MN Reserved HRedowed Ly TN DAPLLEN RAN DA AD PLL Enable Before turning on the DA or AD programmers must set this bit to 1 and wait around 1ms until the PLL output is stable CLK96M R W Current Clock Setting Register This bit is for USB function The USB function n
191. 1 Ctrl 0x7821 P MCS2 Ctrl 0x7822 P MCSS3 Ctrl 0x7823 P MCS4 Ctrl 0x7824 and P EMUCS Ctrl 0x7825 When external memory devices are used users must check the datasheet of memory to make sure the Generalplus Technology Inc PAGE 396 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide enough access time The loading effect on PCB and operation voltage must be seriously considered 25 11 Project Setting on IDE For most projects options are set at project level Options can be setup for different objects that are created by either the system or a user Project can display the structure of options for every object The options given for the project level also apply to all files in the project Set Option for Project 1 Open a project or create a project 2 Click Project Setting to display Setting dialog box 3 Click on each label for further setting Generalplus Technology Inc PAGE 397 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide General EZ memory files li Option Link Section Redefine Hardware BreakPoint PreDownload Be gt J Source Files 13 Head Files G3 External Depen Set Project Configuration Reset C Simulator e ICE Output directories Intermediate ADebug Output ADebug Cancel 1 If simulator is chosen all data will be stored into buffers 2 SetPr
192. 1 MCSO Default 0 0 O 0 0 0 A O 1 1 0 0 1 1 1 1 P Addr Ctrl 0x7841 Memory Address A17 A25 Control Register Bit 15 4 14 13 112 11 10 7 6 5 4 3 2 1 0 Function MA23 MA22 MA21 MA20 MA19 MA18 MA17 Default 0 0 0 0 0 0 0 1 1 1 1 1 1 1 P BankSwitch Ctrl 0x7810 Bank Switch Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Bank Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 P_MAPSEL 0x7816 CS0 boot mapping size select register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function MAPSEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L Generalplus Technology Inc PAGE 317 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 1 0 Port Control Register Summary Table Name Address Description P IOA Data 0x7860 IOA Data Register Bit 15 14 13 KL 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOADATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P IOA Buffer 0x7861 IOA Buffer Register Bit 15 14 13 4712 7 11 10 9 8 7 6 5 4 3 2 1 0 Function IOABUF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P IOA Dir 0x7862 IOA Direction Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOADIR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
193. 1 will initiate 74 clock cycles on the clock line 10 MulBlk Multi Block transfer bit 0 Single block transfer If this bit is set to 1 it will initiate a multiple 1 Multiple block transfer block transfer TranData Transmit Receive Data 0 Receive data Read Indicate if this command transmits or receives 1 Transfer data Write data Command With Data 0 Command without data Indicate if this command is with or without 1 Command with data data RunCmd Run Command Write 1 to this register will initiate the SD command on the SD bus according to current configuration of the controller This bit will be cleared to 0 after the transaction starts You can start a new transaction only when BUSY bit is 0 StpCmd R W Stop Command Write 1 to this bit will force the controller back to IDLE state This bit will be clear to 0 after the controller is back to IDLE state Generalplus Technology Inc PAGE 286 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Type Description Condition CmdCode R W Command Code The command code is that host wishes to transfer P_SD_ArgL 0x79D3 SD MMC Argument Low Word Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ArguMentL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condi
194. 10 Reserved po SPRISIZE Sprite Size of DMA Channel 00 Close sprite mdoe This register is used to determine the sprite size in X axis The sprite size must be smaller than LINELENGTH 0x7BBD b 9 0 When DMA has transferred data amount equal to SPRISIZE the target address will increase automatically by LINELENGTH SPRISIZE This function is useful by moving Generalplus Technology Inc PAGE 276 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide data into LCD frame buffer When SPRUSIZE is set to 0 the sprite mode will be closed Only 16 bit transfer mode is supported in sprite mode and the DF DD must equal to 0 in this mode P_DMA TRANSPATO 0x7BB8 DMA Transparent Pattern Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TRANSPAT Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_TRANSPAT1 0x7BB9 DMA Transparent Pattern Register 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TRANSPAT Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_TRANSPAT2 0x7BBA DMA Transparent Pattern Register 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TRANSPAT Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA TRANSPAT3 0x7BBB DMA Transpa
195. 1024Hz frequency programmable for TimebaseC 8 2 Timebase structure and clock source Reserved 00 8Hz 00 128Hz 00 1Hz imeBa 16Hz i 256Hz i bz M eese A Le ieu Sint el me CHU en 4Hz 11 64Hz 11 1024Hz 11 8 3 Control Registers Timebase Control Register Summary Table P TimeBaseA Ctrl 0x78B0 TimeBaseA Control Register P_TimeBaseB_Ctrl 0x78B1 TimeBaseB Control Register P TimeBaseC Ctrl 0x78B2 TimeBaseC Control Register P TimeBase Reset 0x78B8 TimeBase Counter Reset Register P_TimeBaseA_Cirl 0x78B0 TimeBaseA Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 11 0 Function TMBAIF C TMBAIE TMBAEN TMBAS Default 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 O Bit Function Type Description Condition 15 TMBAIF C R W TimebaseA interrupt Flag Read 0 Not Occurred Write 1 to clear the flag Read 1 Occurred If TimebaseA interrupt occurs this flag is Write 0 No Effect set to 1 by hardware Write 1 Clear the flag Generalplus Technology Inc PAGE 80 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide S tacion O co TMBAIE TimebaseA Interrupt Enable 0 Disabled If this bit is set to 1 and TimeBaseA 1 Enabled interrupt occurs hardware will issue an IRQ7 to CPU If this bit is cl
196. 1110 Function WDGEN WDGS WDGPD Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 18 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 3 6 Bit Function Type Description Condition 15 WDGEN RW Write once to enable Watchdog reset 0 Disabled 1 Enabled 14 WDGS W Write once to select Reset Target 0 Reset System included For more information about system reset CPU and CPU reset refer to Appendix 1 Reset CPU AAA 2 07 WDGPD R W Watchdog period 000 2 seconds 001 1 second 010 0 5 seconds 011 0 25 seconds 1X0 0 125 seconds 1X1 62 5 seconds P_Watchdog_Clear 0X780B Watchdog Clear Register Bit 151 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function WDGC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 WDGC W Watchdog Clear Register Write A005 to clear watchdog timer only when watchdog is enabled i e OX780A 15 1 Writing other value will reset CPU Operation Mode Control GPL162002A 162003A has three operation modes Wait Halt and Sleep mode Please refer to the following table Note that these three modes will all yield CPU to be powered down CPU PLL System Clock 32768Hz Clock After wakeup Wait Mode O Next Instruction FF ON ON Halt Mode ON RTC Re
197. 12K word flash CS3 gt 256K word flash To follow the limitation mentioned in the programming guide Set CS0 size to 4 start address 0x30000 Set CS1 size to 8 start address 0x70000 Set CS2 size to 8 start address 0xF0000 Set CS3 size to 4 start address 0x130000 b Wait cycle The ICE downloading speed is 10MHz i e CPU cycle 100nsf If programmers use lower access speed memory it will have additional wait cycles to prevent download failure In general the extra wait cycle can be set as 0 This is because memory access time is seldom larger than 200ns based on CPU cycle 4 InternalMemory Setting Set the extra wait cycles for downloading into a memory device that tries to emulate internal mask ROM Generalplus Technology Inc PAGE 405 V1 0 Dec 20 2006
198. 13 12 11 10 9 8 716 5 4 3 2 1 0 Function CCPBEN CAPBSEL CMPBSEL PWMBSEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 322 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TimerC_CCP_Ctrl 0x78D1 TimerC CCP Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CCPCEN CAPCSEL CMPCSEL PWMCSEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerA_Preload 0x78C2 TimerA Preload Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMAPLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerB_Preload 0x78CA TimerB Preload Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMBPLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerC_Preload 0x78D2 TimerC Preload Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMCPLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerD_Preload 0x78DA TimerD Preload Register Bit 15 14 13 12 11 T 10 9 8 7 6 5 4 3 2 1 0 Funct
199. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IARST OARST Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 usaf Reseed gt 00 117 0000 0 Write 1 to resetP USBH INAckCount CR ES TT Write 1 10 reset P USBH OUTAckCount P_USBH_Dreadback 0x7B1B USB D D Readback Register Bit 15 44 13 12211 10 9 8 7 6 5 4 3 2 1 0 Function DM DP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 psz reserves Ci DM R PIN imputsigna L Co oe n jwMNipesgnal 3 3 3 Y O Generalplus Technology Inc PAGE 213 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 16 1 16 2 16 Analog Input Touch Panel Voice Recorder Introduction There are two ADC modules on GPL162002A 162003A One is a 12 bit SAR ADC for touch panel and voltage detection and the other one is a 16 bit voice ADC so called HQADO for voice recording The SAR ADC only supports manual sampling mode whereas the HQADC only supports auto sampling mode e 6 Channels 12 bit resolution 11 bit no missing code ADC for touch panel and voltage detection e 80GB delta sigma ADC for voice recording and microphone input W 16 bit stero ADC of 48 KHz sampling rate for audio band signal processing applications W On chip microphone bias voltage output m On chip microphone boost amplifier
200. 141 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function H_END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_HSYNC_SETUP 0x7D06 TFT Hsync Setup Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function HS POL HS WIDTH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 334 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TFT V_WIDTH 0x7D07 TFT Vertical Width Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function V_WIDTH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_V_START 0x7D08 TFT Vertical Start Location Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function z d 2 V START Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT V END 0x7D09 TFT Vertical End Location Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function V_END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_VSYNC_SETUP 0x7D0A TFT Vsyne Setup Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function
201. 162002A 162003A Programming Guide Table 2 Behavior of DMA controller when WRITEREQ 1 19 6 Condition Read Start P_DMA_SRC_Addr Change Write Start P_DMA_TAR_Add P_DMA_TCount Decrease SRCBYTE 1 TARBYTE 0 SRCBYTE 0 TARBYTE 1 SRCBYTE 1 TARBYTE 1 Request Come Each request results in two read Request Come Each request results in two read Control Register Read Complete 2 Reads Complete Read Complete 2 Reads Complete DMA Control Register Summary Table Name Address Read Complete Write Complete 2 Reads Complete or Write Complete P DMA TCount is zero Read Complete Each 2 Writes Complete 1 Write Complete request results in one write Data will be hold until another request come 2 Reads P DMA TCount is Complete or 2 Writes Completes 1 Write Complete zero Each request results in one write Data will be hold until another request come Description P DMA CtrlO P DMA SRC Addio P DMA TAR AGdrkO P DMA TCountLO P DMA SRC AddrHO P DMA TAR AddrHO P DMA TCountHO P DMA MISCO P DMA Cl P_DMA_SRC_AddrL1 P DMA TAR AddrL1 P DMA TCountL1 P DMA SRC AddrH1 P DMA TAR AddrH1 P DMA TCountH1 P DMA MISC1 P DMA Ctrl2 P DMA SRC AddrL2 P DMA TAR AddrL2 Generalplus Technology Inc 0x7B80 PAGE 267 DMA Channel Control Register 0 DMA Source Low Address 15 0 Register 0 DMA Target Low Address 15 0 Regis
202. 2 3 Applications Advanced educational toys High end general STN TFT LCD controller Kid storybook E book Hand held Multimedia LCD game Educational Learning Assistant Handheld organizer Data bank Multi Media Dictionary PDA 2 4 The Differences between GPL162002A and GPL162003A GPL162003A does not have TFT LCD feature Other functions and pins are compatible with GPL162002A Generalplus Technology Inc PAGE 12 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 3 1 3 System Control Introduction This chapter describes the body information reset option system clock system reliability and operation mode The features are depicted as follows Body Information e Built in 32768Hz 6MHz crystal circuit Built in 2 Phase Lock Loop PLL one pumps from 32768Hz up to 12MHz and the other pumps from 12MHz to 96MHz Support clock driver in each mode which can generate different kinds of speed in wild range Level Low Voltage Reset LVR e Build in Watchdog Timer e Support wait mode halt mode and sleep mode for power management The clock of each device can be turned on off individually to reduce the operating power System Control Register Summary Table Name Address Description P BodyID 0x7800 Body Identification Number Register P CLK Gu P_CLK Cui P Reset Flag P Clock Ct P_LVR Cin P Watchdeg OH P Watchdog Clear P WAIT P HALT
203. 2002A 162003A Programming Guide P_TFT_PIP3_STARTAH 0x7D38 TFT PIP3 Frame Buffer Start High Address P_TFT_PIP3_STARTAL 0X7D39 TFT PIP3 Frame Buffer Start Low Address P_TFT_CTRL 0x7D00 TFT Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 41 3 211 0 Function TFTEN VS TYPE Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_DCLK_CTRL 0x7D01 TET Data Clock Control Register Bit 15 14 13 12 11 10 9 8 LD B 44 3 2 1 0 Function DCLK_INV _ AJ DCLK_SEL Default 0 0 0 0 0 0 0 0 o 0 0 0 0 0 0 1 P TFT INT CTRL 0x7D02 TFT Interrupt Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function UF_F C UE EN ha FE F C FEEN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_H_WIDTH 0x7D03 TFT Horizontal Width Bit 15 14 1413 12 11 140 9 8 7 6 5 4 3 2 1 0 Function H_WIDTH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_H_START 0x7D04 TFT Horizontal Start Location Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function E x H_START Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_H_END 0x7D05 TFT Horizontal End Location Bit 15
204. 2006 G Generalplus r2 r1 P_TFT_DMAStart_AH r2 r1 SEGMENT 1 P_TFT_Pixel_Num r1 r1 COMMON 1 P_TFT_Line_Num r1 r1 T_DIP r2 r1 P_TFT_PIPO_STR_AL r2 r1 r1 P_TFT_PIPO_STR_AH r1 r1 PIPO_H_Start P_TFT_PIPO_H_Start r1 r1 PIPO_H_End P_TFT_PIPO_H_End r1 r1 PIPO_V_Start P_TFT_PIPO_V_Start r1 r1 PIPO_V_End P_TFT_PIPO_V_End r1 r1 0x8000 P_TFT_PIPO Ctrl r1 r12 P TFT Ctrl rt 0x8000 P_TFT_ Ctrl J r1 GPL162002A 162003A Programming Guide Iset X pixel Iset Y pixel PIP setup get PIP pic address J set PIP X axis position set PIP Y axis position enable PIP controller lenable TFT controller Generalplus Technology Inc PAGE 153 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 13 UART IrDA Interface 13 1 Introduction The UART IrDA module built in GPL162002A 162003A performs serial to parallel conversion on data received from an external device and it also performs parallel to serial conversion on data transmitted to the external device The transmission and reception paths are individually buffered with internal 8 bytes FIFO memories This module provides the following features Programmable using of UART or IrDA SIR input output e Data width can be 5 6 7 or 8 bits Parity can be even odd or disabled for generation and detection Stop bit width can be 1 or 2 bits Separate 8 by
205. 3 2 1 0 Function VOL 3D C Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DAC VOLUMESD S 0x7BFA 3D Surround Volume Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function VOL_3D_S Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DAC VOLUMESD R 0x7BFB 3D Right Channel Volume Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function VOL 3D R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DAC VOLUME3D L 0x7BFC 3D Left Channel Volume Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function VOL 3D L Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DAC ACCDOUTL Ox7BFE 3D EQ AC Parameter Data Output Low Register Bit 151114 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DATAOUT 15 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DAC ACCDOUTH Ox7BFF 3D EQ AC Parameter Data Output High Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DATAOUT 23 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STN LCD Control Register Summary Table fame Address Description P LCD Setup 0x7980 LCD setup register P LCD Clock 0x7981 LCD clock register P LCD Segment 0x7982 LCD segment number register P LCD Common 0x7983 LCD common number register PAGE 330 Generalplus Technology Inc V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Name Address Description P_LCD Setup
206. 38 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide TFT Timing TFT V WIDTH TFT V END TFT V STR TT RES BLANK ACTIVE BLANK TFT H WIDT TETCH EN TFT H ST A HS WIDT BLANK x ACTIVE BLANK DATA DO DI Dn Generalplus Technology Inc PAGE 139 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TFT_RGB_CTRL 0x7D0B TFT RGB Mode Conirol Register Bit 15 14 1312111110 19 8 7 6 5 4 3 2 1 0 Function RGB_M RGB_DMEN ODD_L_TYPE EVEN L TYPE Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition ESEER s I RGB_DMEN R W RGB Parallel Serial Mode Selection In parallel mode IOA 15 0 is used as TFT data bus In this mode the keyscan In serial mode IOA 7 0 is used as TFT data function is invalid In this mode the keyscan function can be active with TFT at the same time R W RGB With Dummy Data Enable This bit is used for RGB serial mode only If this bit is set to 1 a pixel takes A TFT CLK which includes R G B clocks and a dummy data clock 0 Parallel 16 bit 1 Serial 8 bit 0 Disable 1 Enable am Reseed q O e 4 ODD_L_TYPE CAS vwReevd R W Odd line SeriaLRGB Data Arrangement These bits are used for
207. 3A Programming Guide 25 3 Crystal Usage Guide The following components must be placed as closed as possible to the GPL162002A 162003A while designing layout and the value of components should not be changed X32KO X32KI 32768 C33 C34 22pF 22pF X12MO SW 2P2T None C32 33pF C35 3 3nF C36 47nF Generalplus Technology Inc PAGE 371 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 25 4 Development Emulation Board Configuration This appendix gives a brief overview on GPL162002A 162003A development emulation board and gives details on how to use this board to emulate varied products L Connection L Generalplus Technology Inc PAGE 372 V1 0 Dec 20 2006 G Generalplus Emulation Board lt 02 EMU BOARD V2 0 GPL162002A 162003A Programming Guide DE d 6000000608 00000000050 Generalplus Technology Inc PAGE 373 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Ill Emulation Board Top View WK e ME AE use Re d Hi E 1L AC lx dd Ga Wu LIIRREL a e irren eT e ee ee e Rs L ma EA FT oo M es ba ee m ee e D n ma s es es HH ip paasiki METER ogpeseheeee aseelee HT as PAFF SPC 050J8 L Generalplus Technology Inc PAGE 374 V1 0 Dec 20 2006 G Generalplus GPL162
208. 4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LCDSEG Default 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bit Function Type Description Condition ms Resne LCDSEG R W LCD Panel Segment Number Register Range 15 319 LCDSEG 3 0 is fixed to 1111 in binary LCDSEG 3 0 should be 1111 This register defines the segment number of LCD panel that equals to LCDSEG 8 0 1 Itumust be the multiple of 16 The maximum segment number is 320 and minimum segment number is 16 Therefore LCDSEG 3 0 should be equal to 1111 in binary Attempt to write 0 to any of LCDSEG 3 0 will be in vain In other words LCDSEG 3 0 is read only P_LCD_Common 0x7983 LCD Common Number Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LCDCOM Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fs Lesen 80 LCDCOM LCD Panel Common Number Register Range 0 319 LCDCOM 8 0 control register defines the vertical size of aLCD panel The actual size number of common is LCDCOM 8 07 1 The maximum common number is 320 and minimum common number is 1 P LCD Buffer LowAdr 0x7984 LCD Buffer Address A15 AO Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LCDBUFAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
209. 4 3 2 1 0 E DATA 31 16 Function Default lt 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LE Bit Function type Description Condition 15 0 E DATA e E fuse data out 31 16 n P EFuse_D2 0x7C32 E Fuse Data Register 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E DATA 47 32 Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Function PAGE 307 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition 15 0 E DATA R E fuse data out 47 32 Ui P EFuse D3 0x7C33 E Fuse Data Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function E DATA 63 48 Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit Function Type Description Condition so E DATA R K fuse data out 63 48 LC Y Generalplus Technology Inc PAGE 308 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 24 Link your program 24 1 Resource File Alignment by Link Script File u nSP IDE allocates programs and resources in two ways fixing sections for resources and programs and modifying through the linking file lik The ways to set up a start address are as follows project gt setting gt secti
210. 5 Ox00FFF6 OxOOFFF7 Ox00FFF8 Ox00FFF9 Ox00FFFA Ox00FFFB OxOOFFFC Ox00FFFD OxOOFFFE OxOOFFFF Software Break Fast IRQ RESET IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ7 4 8 Stack Location Generalplus recommends that stack starts at the end of Internal SRAM that is stack pointer is set to 0x0077FF Stack area will grow from bottom to top 4 9 Chip Select Project Setting on IDE SUNPLUS u nSP IDE provides a setting dialog box to set up external CS 4 0 configuration In this way programmers can set up the size mode and wait state of CS 4 0 easily and quickly Moreover programmers can review start and end addresses of CS 4 0 memory on other dialog boxes after settings Note that the setting on dialogue box is only for downloading procedure not for the normal operation of GPL162002A 162003A while it is running Therefore programmers should give appropriate software codes to set P MCSO Ctrl P MCS1 Ctrl P MCS2 Ctrl P MCS3 Ctrl and P MCS4 Ctrl registers in a project Generalplus recommends programmers should set this dialog box before downloading programs otherwise ICE download function is possiblely failed Furthermore the dialogue box mentioned above can also determine which memory device CSO CS1 CS2 CS3 and CS4 will be downloaded in order to save downloading time For Detail user manual on IDE refer to appendix Project Setting on IDE Generalplus Technology Inc PAGE 40 V1 0 Dec 20 2
211. 62002A 162003A will sample data at rising edge of SPICLK sack LJ LJ LS LILI LIL LE SPICSN SPIRX SPITX Fig2 Master Mode POLARITY 0 PHASE 1 At this setting GPL162002A 162003A will sample data at falling edge of SPICLK Generalplus Technology Inc PAGE 170 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide sik LJ LJ LI LI LILI LI l SPICSN SPIRX SPITX Fig3 Master Mode POLARITY 1 PHASE 0 At this setting GPL162002A 162003A will sample data at falling edge of SPICLK spoue LILI UU UU UU SPICSN SPIRX SPITX SPIOE Fig4 Master Mode POLARITY 1 PHASE 1 At this setting GPL162002A 162003A will sample data at rising edge of SPICLK Generalplus Technology Inc PAGE 171 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 14 6 Consecutive Bytes Transfer Consecutive byte transfers are available in the master mode In transmission software is able to send the data consecutively as long as the SPITXBF flag is not set In reception software should check for overrun error to monitor if there is any missing data in case the polling rate is too low 14 7 Control Registers SPI Control Register Summary Table Name Address Description P SPI Ctrl 0x7940 SPI Control Register P SPI TXStatus 0x7941 SPI Transmit Status Register
212. 62003A Programming Guide D GPL162002A 162003A VCC_33 0 DVCC18S1 DVCC18C1 DVCC33101 DVCC33R IOA 0 15 1OC 15 VDACRI VSS_DAC VADCREE VSS_ADC HEADER 2 A AVCCDA VSSDAC R25 C39 1OB O 15 JL l I I m Am E SBauF 9 i em RESET a 9 2 v n 3 JP48 RESETB C E p HEADER 2 A C43 AVCCADGVS ADC1 a NEE C51 E 8 m Sl tour al I o o 9 c42 8 9 SF JP41 Hi JP45 27 E 2 2 M P 0 tuF 25 10uF a 2 9 HEADER 2 9 HEADER 2 E 8 o 9 En JP50 A C49 2 VCC_33 o IL 1 eo if 5 HEADER 2 S 6848F s JP44 MD O 15 MA 0 16 22 our vccas M Sp S E a HEADER 20 3 eo H o JP49 S A a On je NN WA 1 ININ HEADER 2 ko Isle VCC 180 CS g PE lolo u3 BBE GPL162002_COB Brogan awn co o x c lt O d 2 COBOS ER RS aiia KE 38 x o z aa X12MI E gt gt x12MI PUE CIS TS 8L99ATId PLLC HE SSATId gt pic PLLVCC33 HE FSOURCE DVCC33IO2 H4 eR DVCC18C2 77 UR DVSS2 4 IOB11 70 1801 RESETB 10810 ISSN 132 089 LINEIN2 PE 189 INEIN2 801 133 1086 LINEINT L LINEIN1 S 1087 VSS ADCA TEA 4801133 1088 10815 L Et SSA _ sgor 136 CBS EI 65 gigot L7 mum 1083 10813 9 EE 0EB4 39 1084 10812 62 ZL8OI gigs lE GAS CARO DER 8199A i41 6 amp 0
213. 62003A Programming Guide This register stores the scan data read from IOA 15 8 when the IOA 7 0 is set as 0500010000 KSINV 0 or 0b11101111 KSINV 1 The data will be preserved until the next scan process happens P KS Data5 Ox7BCD Sample Data of Line IOA 5 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data5 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 Reserved 7 0 peas R Scan data is read from IOA 15 8 when IOA 5 is active NN This register stores the scan data read from IOA 15 8 when the IOAT 7 0 is set as 0600100000 KSINV 0 or 0b11011111 KSINV 1 The data will be preserved until the next scan process happens P KS Data6 Ox7BCE Sample Data of Line IOA 6 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data6 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 Reserved 7 0 Data R Scan data is read from IOA 15 8 when IOA 6 is active This register storesithe scan data read from IOA 15 8 when the IOA 7 0 is set as 0b01000000 KSINV 0 or 0b10111111 KSINV 1 The data will be preserved until the next scan process happens P KS Data7 Ox7BCF Sample Data of
214. 62003A Programming Guide To make it work IOC9 and 10C10 should be For System clock 48MHz Baud Rate 115 200 bps UART Enable N 8 1 FIFO Enable IA TX FIFO data 0x50 1120 gr A eh eh 7 gi TX FIFO data II 0x51 0X52 0x53 0x54 0x55 0x56 0x57 Il If data number of RX FIFO is more than or equalto 8 RX interrupt flag will be set to 1 JI Verify all RX FIFO data Generalplus Technology Inc PAGE 167 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 14 Serial Peripheral Interface SPI 14 1 Introduction A Serial Peripheral Interface SPI controller is built in GPL 162002A 1620034A to facilitate communicating with other devices and components The built in SPI controller GPL162002A 162003A includes four master mode and one slave mode There are four control signals on SPI SPICSN SPICLK SCK SPIDI SDI SPIDO SDO these signals are shared with PortB10 Portb11 PortD11 and PortD4 and SPICSN is valid only on slave mode While SPI module is enabled by setting corresponding control bit these four pins cannot be GPIOs In other words any setting on corresponding GPIO control register will have no effect The SPI provides following features Selectable single byte or consecutive byte transfers Overrun error indication Transmitting receiving interrupt requests Programmable phase and polarity of master clock Selectable
215. 72 JP57 connected to LCDEN DISPOFF pin of external LCM is used to enable the LCM Shorting JP57 1 and JP57 2 will enable LCM all the time In addition users can connect one designated GPIO pin to JP57 to turn the LCM on or off Refer to the LCD schematic diagram for detail pin assignment VCC 33 O HEADER 16X2 UART IrDA Interface Header Referenced as JP69 Note that if UART or IrDA interface is enabled both TX 3 and RX 4 DIP switches on S16 should be turned on Besides GPL162002A 162003A emulation board also probides a RS232 level shifter IC HIN232 with female output header referenced as P1 for UART GPL162002A 162003A emulation board also reserves a footprint of an IrDA transceiver module HP3201 This IC is optional and not soldered on the PCB SD Card Interface Header Referenced as U10 Note that if SD Card interface is used turn on corresponding switches on S14 which interconnect GPL162002A 162003A and PortC socket referenced as JP21 and JP22 labeled with OCH Generalplus Technology Inc PAGE 378 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide JP67 and JP68 are connected to SDC socket 11 and 10 pins respectively so that users can perform SDC writing protection and detecting insertion JP67 JP68 HEADER 2 HEADER 2 U10 SDCON NAND Flash Interface Header Referenced as U9 The built in NAND Flash controller on GPL162002A 162003A supports 8 bit and
216. 7925 Alarm Minute Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ALMMIN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition _ use Reseneg y ALMMIN Alarm Minute Setup Register Only 0x00 0x3B Valid 0 59 P Alarm Hour 0x7926 Alarm Hour Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ALMHR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition pss Rested A 3 gt O 4 0 ALMHR Alarm Hour Setup Register Only 0x00 0x17 Valid 0 23 P RTC Ctrl 0x7934 HMS Alarm Schedule Control Register Bit 15 144 13 12 11 10 9 8 7 6 5 4 3 21110 Function RTCENY amp ALMEN HMSEN SCHEN SCHSEL Default 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Conaition 15 RTCEN RAW RTC Module Enable 0 Disabled If this bit is set to 1 this RTC module and 1 Enabled Alarm Module will be enabled f this bit is cleared to 0 RTC module is disabled to save power A AAA PE 10 ALMEN R W Alarm Function Enable 0 Disabled If this bit is set to 1 this alarm function will 12 Enabled be enabled and vice versa HMSEN RAW
217. A 162003A Programming Guide byte data is effective and high byte data will be filled all zeros P_MCS_Byte_Sel 0x7826 MCS Word Byte Data Select register Bit 151141131121 11110 9 8 7 6 5 4 3 2 1 0 Function EMU S4 S3 S2 S1 SO Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition Reserved If This bit is set 1 then EMUCS accesses data in 8 bit mode Only low byte available High byte will be filled zero If This bit is set 1 then CS4 accesses data in 8 bit mode Only low byte available High byte will be filled zero If This bit is set 1 then CS3 accesses data in 8 bit mode Only low byte available High byte wilhbe filled zero If This bit is set 1 then CS2 accesses data in 8 bit mode Only low byte available High byte will be filled zero If This bit is set 1 then CS1 accesses data in 8 bit mode Only low byte available High byte will be filled zero If This bit is set 1 then CSO accesses data in 8 bit mode O lh ich O la o a o Only low byte available High byte will be filled zero P_MCS3_WETimingCtrl 0x7827 MCS3 WE timing control register Bit 15 14 130 12 1101410 9 8 7 6 5 4 3 2 1 0 Function WEB3NUM Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 4 3 0 WEB3NUM R W CSB3 and WEB3 Program Timing Register R
218. A Transfer Interrupt USB Interrupt TimerA Up Counter Overflow or Capture or Comparison event P INT Status2 Interrupt TimerB Up Counter Overflow or Capture or Comparison event Interrupt TimerC Up Counter Overflow or Capture or Comparison event Interrupt TimerD Up Counter Overflow Key Change Interrupt P INT Status1 LCD Frame Pulse Rising Edge FP Interrupt TFT Under Flow Error Interrupt TFT Frame End Interrupt SP Serial Bus Interrupt SD Controller Interrupt P_INT_Status2 DC Transmit Receive Interrupt NAND Flash FIFO over under flow interrupt Key Scan Interrupt P_INT_Status2 TimeBaseC Interrupt Scheduler Interrupt TimeBaseA Interrupt P_INT_Status2 TimeBaseB Interrupt Alarm Interrupt Hour Minute Second Half Second Interrupt There are three interrupt events in UART IrDA module reception transmission and reception timeout interrupts Any one of these three interrupt sources can trigger FIQ or IRQ3 Therefore in FIQ or IRQ3 _interrupt service routine programmers should read P_UARTIrDA_Ctrl bit 15 13 to distinguish which interrupt event happens Note that 3 bit content reading from P_UARTIrDA_Ctrl bit 15 13 sometimes have more than one 1 That means more than one interrupt event occur Please refer to chapter UART IrDA Interface There are three interrupt events in TimerA TimerB and TimerC module up counter overflow event capture event and comparison event One of above interr
219. AK to the host this enable of enable of d bit will be set PAGE 193 Read 0 Not occurred Read 1 2 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 7 BIPC R W Bulk In Packet Clear Interrupt Flag Read 0 Not occurred If the corresponding enable bit of Read 1 Occurred P_USBD_INTEN is 1 and an IN packet is Write 0 No effect read from the host this bit will be set Write 17 Clear the flag EOSNA EPO Status NACK Interrupt Flag Read 0 Not occurred If the corresponding enable bit of Read 1 Occurred P_USBD_INTEN is 1 and the request of Write 0 No effect status transaction happens with rplying a Write 1 Clear the flag NAK to the host this bit will be set EPO Status Clear Interrupt Flag Read 0 Not occurred If the corresponding enable bit of
220. AWCL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description condition 15 0 DMAWCL R W DMA Write Count Low The register is used in DMA mode Set this register to indicate how many data is transferred It s must be done after setting P USBD DMAWrtCountH 0x7B51 USB DMA Byte Count High Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DMAWCH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition use jReevwd 7 0 DMAWCH R W DMA Write Count High The register is used in DMA mode Set this register to indicate how many data is transferred Generalplus Technology Inc PAGE 201 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_USBD_DMAACK 0x7B52 USB DMA ACK Count Low Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DMAACKL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 DMAACKL R W DMAACK Count Low Write this port to reset The register is used in DMA mode DMAWC and DMAACK It indicates how many transactions each transaction is a 64 byte packet are not finished yet P_USBD_DMAACK 0x7B53 USB DMA ACK Count High Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Funct
221. B data for each odd and even line in RGB mode Support YUV or YCbCr mode Support the adjustable order of YUV YCbCr data for each line in YUV mode e Support CCIR656 mode e Supportfour sub frame buffers reading by PIP DMA The scrolling function is supported for each PIP module TFT Interface Signal Signal Description TFT Vsync TFT vertical synchronous signal shared with GPIO portC3 TFT Hsync TFT horizontal synchronous signal shared with GPIO portC2 TFT DE TFT data enable shared with GPIO portC1 TFT CLK TFT data clock shared with GPIO portCO TFT DATA TFT data bus 8 bit for serial 16 bit for parallel shared with GPIO portA 15 0 Generalplus Technology Inc PAGE 131 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 1233 TFT LCD Butfer 12 4 In GPL162002A the control registers P TFT DMAStart AH 0x7DOD and P_TFT_DMAStart_AL 0x7 DOE are to define TFT LCD buffer start address withit the 80M word addressing field as a LCD buffer Certainly the area defined as a LCD buffer can be SRAM ROM or Flash LCD buffer can also be internal RAM LCD buffer size definition is implied in two control registers P TFT Pixel Num and P TFT Line Num The maximum number of common lines horizontal line to be supported is 640 pixels and the maximum segment line vertical line is 480 pixels GPL162002A TFT LCD can support up to 65536 color display w
222. CD Display and System Performance esee teh nennen 393 Audio Output Components Selection Guide 5 5 eee IIR 394 32768 Crystal and PLL Power on Stable Time sm eene 395 Reset Typa IUE zn O E Ea E A aa AT 395 Important Note for the Setup of Memory Access Time ln 396 Project Setting On IDE T EE A e 397 Generalplus Technology Inc PAGE 8 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Revision History Revision Date By Remark 1 0 12 20 2006 Jacky Lin 1 Add GPL162003 body Correct relationship table between BM2 and USB function Please see section 3 4 for detail and see Revision table1 Correct 0x7815 congtrol register description For detail please see system control chapter Correct 0x7D14 0x7D1F Ox7D2A 0x7D35 control register description For detail please see TFT LCD chapter 06 15 2006 Jacky Lin First edition Revision 1 0 Revision table1 Slow PLL Fast PLL USB Function 32768Hz gt 12MHz 12MHz gt 96MHz o Not Active Active After enter Fast mode Available when Fast PLL is on Not Active Active After enter Fast mode NENNEN Generalplus Technology Inc PAGE 9 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 1 Confirmation sheet The confirmation sheet as a requisite document before placing orders contains useful information and checklist that help to avoid m
223. CNT Compare Counter COM Common starts with 0 e g COMO COM1 DACA DACB etc DACA DACB etc DEC Decrease DISP ECLK ERR Display External clock Error O FLOAT FUNC NC NT DEFAULT LVD Low Voltage Detection LVPD LVR Float state Function Increase Interrupt Initialization Low Voltage Power Down Low Voltage Reset Maximum MIN Minimum MUTE Mute NMI Non masked interrupt DN Open drain NMOS sink Open drain PMOS send I O PortA IO PortB etc Pull high resistor Q PortA PortB TU Pull low resistor Pulse Width Modulation Readable writable U DH I 5 O g R oscillator Real time clock Generalplus Technology Inc PAGE 311 V1 0 Dec 20 2006 G Generalplus Abbreviation GPL162002A 162003A Programming Guide Description TMA TMB etc X TAL or XTAL 000016 77FF46 780016 781F 16 782016 785F 16 786016 788F 16 78A016 78AF 46 78B046 78BF46 78C016 78DF e 78F04e 78FF46 790046 791F 16 792016 793F 16 794016 795F 16 796016 797F8 798016 799F8 79A016 79AF 46 79B016 79BF 16 79C016 79CF 16 79D0 6 79EF 16 79F0 6 79FF 16 7A0016 7AFF46 7B001e 7B2F 16 7B301e 7B5F 16 7B60 6 7B7F46 7B8016 7BBFi6 7BCO0 4e 7BCF46 7BD0 6 7BDF 16 7BEO 1e 7BEF46 7BFO16 7BFF16 Generalplus Technology Inc Segment starts with 0 e g SEGO SEG1 Sleep Speech
224. Compiler location AS Specify the Assembler location LD Specify the linker location 2 3 4 CFLAG Specify the C Compiler Operation FLAGS 5 ASFLAG Specify the assembler Operation FLAGS 6 LDFLAG Specify the linker Operation FLAGS 7 Optimizations Select the Optimization Type you want the optimization flags will be changed automatically 8 ISA Selector Select different instruction set of unSP ISA1 0 ISA1 1 ISA1 2 etc 9 Makefile Check if auto updating the makefile 10 Ary file Check if auto updating the array file 11 Additional include dir Set include file directory 12 Additional library dir Set library file directory Generalplus Technology Inc PAGE 399 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Link 488 memory files General Option E Section Redefine Hardware BreakPoint PreDownload Be gt J Source Files J Head Files Output J External Depen Output file name memory 537 C TSK e 537 V Include Start Up C Iw Generate Interrupt Vector Table E Align all resources with n Iw Generate Initial Table Allow non page 0 IRAM External Symbol Files Library modules CMacro1216 lib Cancel Output file name Specify the output file s name TSK S37 Types of object file binary ASCII Motorola S37 Before users define the type of output file users should check both Makefile and Ary file a
225. Ctrl r1 r1 0x9000 P_NF_INT_Ctrl r1 r1 0x00 R_DMAFlag r1 irq on r1 0x0200 P_DMA_Ctrl0 r1 ri Data Addr Low P_DMA_SRC_AddrL0 r1 ri Data Addr High P DMA SRC AddrHO r1 r1 P NF Data ID DMA TAR AddrLO r1 r1 0x00 IP DMA TAR_AddrHO r1 r1 512 P_DMA_TCountL0 r1 ri 0 P_DMA_TCountHO r1 ri P_DMA SS r1 amp 0x0f r1 0x05 P_DMA_SS r1 r1 0xa148 P DMA Ctrl0 r1 r1 Oxd400 P NF INT Ctrl r1 nand flash initial byte mode lldma Channel 0 control reset Source DataAddr low Source DataAddr high Destination address nand flash data port JI Write 512 bytes consecutively Data will first be written to A area and then B area set dma0 source 5 nand flash nand flash DMA enable addr3 Generalplus Technology Inc PAGE 247 V1 0 Dec 20 2006 G Generalplus _Write_Not_Finish IRQ3 End_IRQ3 GPL162002A 162003A Programming Guide r3 0x00 enable P_NF_CMD r3 r3 0x80 read block A area 00H command P_NF_CMD r3 r1 0x00 P_NF_AddrL r1 send 80H command r1 0x00 IP NF AddrH r1 Iwrite PageAddr low r1 0x0001 P ECC Ctrl r1 Iwrite PageAddr high r1 P_DMA_Ctrl0 Il reset ECC r1 0x0001 P DMA Ctrl0 r1 enable channel r1 R_DMAFlag cmp r1 1 jne Write Not Finish r1 0x0010 IR NF CMD lt r call F CheckNANDBusy call F Read
226. D25 TFT PIP1 Horizontal End Location in Each Line Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function PIP1 H END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP2_H_END 0x7D30 TET PIP2 Horizontal End Location in Each Line Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function PIP2_H_END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 H END Ox7D3B TFT PIP3 Horizontal End Location in Each Line Bit 154 14 134 12 11 10 8 7 6 5 4 3 2 1 0 Function PIP3 H END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIPO V START 0x7D1B TFT PIPO Vertical Start Location in Each Frame Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function PIPO V STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP1 V START 0x7D26 TFT PIP1 Vertical Start Location in Each Frame Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function PIP1 V STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 340 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TFT_PIP2_V_START 0x7D31 TFT PIP2 Vertical Start Location in Each Frame Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2 V STR
227. Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_SD_ArgL 0x79D3 SD MMC Argument Low Word Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ArguMentL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_SD_ArgH 0x79D4 SD MMC Argument High Word Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ArguMentH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_SD_RespL 0x79D5 SD MMC Response Low Word Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RespL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_SD_RespH 0x79D6 SD MMC Response High Word Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RespH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_SD_Status 0x79D7 SD MMC Status Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 110 Function CINT CPRE C CWP DCRCE C TO C DBufEpt DBufFu RBufFu RCRCE C RidxE C DCOM C CCOM C CBY BY Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_SD Ctrl 0x79D8 SD MMC Control Register Bit 151 14 13 12 11 10 9 8 7 6 5 4131 21 110 Function jSDEN IOEN DMAMOD BUSWD CL
228. Dec 20 2006 G 12 2 Generalplus GPL162002A 162003A Programming Guide 12 TFT LCD 12 1 Introduction GPL162003A does not have TFT LCD feature so GPL162003A programmer can ignore this chapter GPL162002A provides a TFT LCD controller supporting data types of parallelRGB 5 6 5 serial delta RGB serial stripe RGB serial YUV serial YCbCr and CCIR656 The maximum horizontal resolution of TFT controller reaches 640 pixels and the maximum vertical resolution of TFT controller reaches 480 pixels For the resolution setting it could be programmed by giving designated values To internal registers The TFT controller mainly provides four timing signals and an 8 16 bit data signal fo control external TFT module These are VSYNC HSYNC DE DCLK and DATA Besides GPL162002A provides a special function PIP which can overlap the main display window to create up to 4 sub display windows Fearure Maximum horizontal and vertical pixels are 640 X 480 The FT clock is divided from the system clock 1 1 2 1 4 1 8 of SYSCLK The width and polarity of HSYNG and VSYNC can be programmed Active region and blank region clock and the TFT clock of the horizontal pixels are programmable Active region and blank region clock andthe TFT clock of the vertical line are programmable Support parallel RGB mode R 5 bit G 6 bit B 5 bit Support delta RGB stripe RGB mode Support the adjustable order of RG
229. Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 V START 0x7D3C TFT PIP3 Vertical Start Location in Each Frame Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP3 V STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIPO V END Ox7D1C TFT PIPO Vertical End Location in Each Frame Bit 151 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPO V END Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP1 V END 0x7D27 TFT PIP1 Vertical End Location in Each Frame Bit 151 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1 V END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP2 V END 0x7D32 TET PIP2 Vertical End Location in Each Frame Bit 15 14 13 12 4 14 1410 9 8 7 6 5 4 3 2 1 0 Function PIP2 V END Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 V END Ox7D3D TFT PIP3 Vertical End Location in Each Frame Bit 151114 134 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP3 V END Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART IrDA Control Register Summary Table ly Name Address Description Generalplus Technology Inc PAGE 341 V1 0 Dec 20 2006 G
230. ERR FAILBIT FAILLINE Init 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 Bit Function Type Description Condition 15 13 Reserved ESO z 1 error PER dn NUN NN 1 error ce E E others m error on bit m Pp E others n error on line n P_ECC_ERR1_HB 0x784F ECC High Byte Field 1 Error Flag Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function 2ERR 1ERR FAILBIT FAILLINE Init 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 Bit Function Type Description Condition 15 13 Reserved Generalplus Technology Inc PAGE 244 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Description Condition 2ERR There are two error bits 0 error free 1 error 11 1ERR There is one error bit 0 error free 1 error bed iini Re RIA others m error on bit m others n error on line n The control register P ECC ERRO HB stores the error information of 0 255 high bytes of Nand Flash Moreover P ECC ERR1 HB stores the error information of 256 511 high bytes of Nand Flash For more information about ECC check error registers please refer to NAND Flash ECC amp CheckSum special note P CHECKSUMO LB 0x7830 NAND Flash Low Byte Check Sum Low Value Bit 15 14 13 12 11 30 9 8 7 6 5 4 3 2 1 0 Function CHECKSUMO 1B Init 0
231. ESTN Test mode negative input or output Generalplus Technology Inc PAGE 221 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 16 6 Control Registers ADC control register summary table Address 0x7960 Name P ADC Setup Description ADC Setup Register P_MADC Ctrl 0x7961 Manual Mode ADC Control Register P MADC Data 0x7962 Manual Mode ADC Data Register P ASADC Ctrl 0x7963 Auto Sample Mode ADC Control Register P HQADC RGAIN 0x7972 High Quality ADC LINEINR gain setting P HQADC LGAIN 0x7973 High Quality ADC LINEINL gain setting P ADC Setup 0x7960 ADC Setup Register Bit 15 14 13 12 11 110 918 7 6151413 2 110 Function ADBEN ADCEN CLKSEL jASEN ASMEN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description R W SAR AD Bias Reference Voltage Enable This bit is for SAR ADC only 14 ADCEN R W consumption Enables SAR ADC for SAR ADC only p51 Reese CT Condition 0 Disabled 1 Enabled 0 ADCADE will be turned on only when the increase rapidly therefore turn ADC on only and turn off ADC immediately after ADC data is successfully manual or auto sample when it is necessary ADC operation 1 ADCADE will turned on all the time be obtained If programmers write 1 to this bit the ADCADE will turn on all the time If this bit is set to 0
232. EXTASEL EXTBSEL SRCBSEL SRCASEL Default 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 P TimerD Ctrl 0x78D8 TimerD Control Register Bit 15 14 13 12 11 10 9 8171615141 13 2 11 0 Function TMDIF C TMDIE TMDEN EXTASEL EXTBSEL SRCBSEL SRCASEL Default 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 P_TimerE_Cirl 0x79CO TimerE Control Register Bit 15 14 13 12 11 10 9 8 7 IBB M4 3 42 1 0 Function TMEIF C TMEIE TMEEN EXTASEL EXTBSEL SRCBSEL SRCASEL Default 0 0 0 0 0 0 0 0 0 0 OF 40 0 0 0 O P TimerF Ctrl 0x79C8 TimerF Control Register Bit 15 14 13 12 11 10 9 8 Tal 5 4 3 2 1 O Function TMFIF C TMFIE TMFEN EXTASEL EXTBSEL SRCBSEL SRCASEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Functon Type Description Condition 15 TMXIF C R W TimerX Interrupt Flag Read 0 2 Not Occurred Write 1 to dear tbe flag Read 1 Occurred In_timer counter mode this bit is set Write 0 No effect when TimerX rolls over from FFFF and is Write 1 Clear the flag cleared by writing this bit to 1 In capture mode This bit is set when the external signal is driven and timer counter value is latched into TimerX CCP register In comparison mode this bit is set when the timer counter value is the same as the value stored in TimerX CCP register In PWM mode reading or writing this bit has no effect TMXIE R W TimerX Interrupt Enable 0 Disabled If this bit is set to 1 and TimeX Timer
233. F INT Ctrl P ECC Ctrl P ECC LPRL LB P ECC LPRH LB P ECC CPR LB P ECC LPR CKL LB P ECC LPR CKH LB P ECC CPCKR LB P ECC ERRO LB Generalplus Technology Inc 0x7850 NAND Flash Control Register NAND Flash Command Register NAND Flash Low Address Register NAND Flash High Address Register NAND Flash Data Register NAND Flash DMA INT Control Register ECC Control Register ECC Low Byte Line Parity LSB Register ECC Low Byte Line Parity MSB Register ECC Low Byte Column Parity Check LSB Register ECC Low Byte Line Parity Check LSB Register ECC Low Byte Line Parity Check MSB Register ECC Low Byte Column Parity Check Register ECC Low Byte Error FlagO PAGE 354 V1 0 Dec 20 2006 G Generalplus Name GPL162002A 162003A Programming Guide Address Description P ECC ERR1 LB P ECC LPRL HB P ECC LPRH HB P ECC CPR HB P ECC LPR CKL HB P ECC LPR CKH HB P ECC CPCKR HB P ECC ERRO HB P ECC ERR1 HB P CHECKSUMO LB P CHECKSUM1 LB P CHECKSUMO HB P CHECKSUM1 HB 0x785F ECC Low Byte Error Flag1 P NF Ctrl 0x7850 NAND Flash Control Register Bit 15 14 19 12111 10 9 8 7 6 5 4 3 2 1 0 Func
234. Frame Buffer End Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1 MIR EAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP2_VIR_EAL 0x7D2C TFT PIP2 Virtual Frame Buffer End Low Address Bit 15 14 13 124 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2 VIR EAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 VIR EAL 0x7D37 TFT PIP3 Virtual Frame Buffer End Low Address Bit 158 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP3 VIR EAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e e Desorption OOOO f conation 15 0 PIP 4VIR_EAL PIP Virtual End Low Address This register is valid only when PIPZSCREN is set to 1 The virtual frame End address means the real address of data See the following diagram for details P TFT PIPO STARTAH 0x7D17 TFT PIPO Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPO_SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 146 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TFT_PIP1_STARTAH 0x7D22 TFT PIP1 Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1 SAH Default 0 0 0 0 0 0 0 0 0
235. GPL162002A 162003A each page size is 64K word GPL162002A 162003A can access up to 256 pages 16384KW of each memory controller There are total five memory controllers on GPL162002A 162003A so that it can totally access up to 81920KW in CPU view however it can only address up to 4MW To access whole 81920KW programmers need to use one control register to switch bank Besides GPL162002A 162003A supports five chip select signals to enable five external memory devices Some of these chip select pins are shared with other special functions For detail please refer to I O Port The 30K word Internal SRAM including stack area is located in 0x000000 0x0077FF and system Generalplus Technology Inc PAGE 27 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide control registers and peripheral control registers reside in the 2K word area from 0x007800 to 0x007FFF Internal SRAM system control register and peripheral control registers are positioned in the lower 32K word of Page0 The layout of internal ROM starts from the upper 32K word in page0 and ends up the upper 32K word of Page2 from 0x008000 to 0x027FFF Therefore internal resources will be stored in Page0 Page1 and Page2 Note that the higher 32K word of Page2 is reserved 0x028000 0x02FFFF The address of the five external memory devices starts at 0x0003_0000 total 81920K word In other words the size of five devices is programmable
236. HB 0x784C ECC High Byte Line parity Check MSB Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LPRCKH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P ECC CPCKR HB 0x784D ECC High Byte Column parity Check Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CPRCK Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L PAGE 357 V1 0 Dec 20 2006 Generalplus Technology Inc G Generalplus GPL162002A 162003A Programming Guide P_ECC_ERRO HB 0x784E ECC High Byte Field 0 Error Flag Bit 45 44 48 42 i 30 9 8 7 S 5 4 3 2 1 90 Function 2ERRMERR FAILBIT FAILLINE Init 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 P_ECC_ERR1_HB 0x784F ECC High Byte Field 1 Error Flag Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function 2ERR 1ERR FAILBIT FAILLINE Init 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 P CHECKSUMO LB 0x7830 NAND Flash Low Byte Check Sum Low Value Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CHECKSUMO LB Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_CHECKSUM1_LB 0x7831 NAND Flash Low Byte Check Sum High Value Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CHECKSUM1_LB Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P CHECKSUMO HB 0
237. HSECIF C Default 0 0 0 0 0 0 0 0 0000 0 0 0 0 Generalplus Technology Inc PAGE 326 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_RTC_INT Ctrl 0x7936 HMS Alarm Schedule Interrupt Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ALMIEN SCHIEN HRIEN MINIEN SECIEN HSECIEN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P RTC HMSBusy 0x7937 RTC HMS Busy Register Bit 15 14 13 12 111 1100 9 8 7 6 5 4 3 2 1 0 Function SEC BUSY MIN BUSY HR BUSY Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC Control Register Summary Table Name Address Description P_CHA Ctrl 0x78F0 CHA DAC PWM Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function FEMIF C FEMIEN CHAEN SIGNED SRCEN SRCRST SRCFS Default 1 0 0 0 0 0 0 000000000 O Generalplus Technology Inc PAGE 327 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_CHA_Data 0x78F1 CHA DAC PWM Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CHADATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
238. High 25 16 Register 3 P DMA MISC3 DMA miscellaneous Control Registers P DMA SPRISIZEO DMA Sprite Size 9 0 Register 0 P DMA SPRISIZE1 DMA Sprite Size 9 0 Register 1 P DMA SPRISIZE2 DMA Sprite Size 9 0 Register 2 P DMA SPRISIZE3 DMA Sprite Size 9 0 Register 3 P DMA TRANSPATO DMA Transparent Pattern Register 0 P_DMA_TRANSPAT1 DMA Transparent Pattern Register 1 P DMA TRANSPAT2 DMA Transparent Pattern Register 2 P DMA TRANSPAT3 DMA Transparent Pattern Register 3 P DMA LINELENGTH DMA Line Length Control Register P DMA SS Ox7BBE DMA Soruce Select Register P DMA INT 0x7BBF DMA Interrupt Status Register P DMA CtriO 0x7B80 DMA Channel Control Register 0 Bit 15 14 13 12 1111019 8 7 6 5 14 3 21110 Function WriteReq TM TARByte SRCByte TD RS CIE SF DF SD DD DB NOR Mod BS CE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA Ctrl1 0x7B88 DMA Channel Control Register 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 21110 Function WriteReq TM TARByte SRCByte TD RS CIE SF DF SD DD DB NOR Mod BS CE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA Ctrl2 0x7B90 DMA Channel Control Register 2 Bit 15 14 13 12 1110191 8 7 6 5 4 3 21110 Function WriteReq TM TARByte SRCByte TD RS CIE SF DF SD DD DB NOR Mod BS CE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0
239. Hour Minute Second Function Enable 07 Disabled If this bit is set to 1 this hour minute second 1 Enabled automatic updating function will be enabled and vice versa Generalplus Technology Inc PAGE 87 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Gergen SCHEN RAW Scheduler Function Enable 07 Disabled If this bit is set to 1 this scheduler module 1 Enabled will be enabled If this bit is cleared to O scheduler module is disabled to save 3 Rene 2 0 SCHSEL R W Schedule Time Period Selection 000 16Hz These 3 control bits are valid only when 001 32Hz SCHEN control bit is set to 1 010 64Hz 011 128Hz 100 256Hz 101 512Hz 110 1024Hz 111 2 2048Hz P RTC INT Status 0x7935 HMS Alarm Schedule Interrupt Flag amp Clear Register Bit 15 14 13 12 11 10 9 8 7161514 3 2 1 0 Function ALMIEF C SCHIF C ja HRIF C MINIF C SECIF C HSECIF C Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e Peron condon el Reevwed 10 ALMIF C R W Alarm Interrupt Flag Clear Read 0 Not Occurred Write 1 to clear the flag Read 1 Occurred This bit is set to 1 by hardware if the Write O No Effect alarm interrupt is asserted Write 1 Clear the flag L9 ROS s Reeved 000 0 0 SCHIF C RA
240. If this bit is set to 1 and I2C interrupt is 1 Enable generated hardware will issue an IRQ5 or FIQ to CPU If this bit is cleard to 0 the interrupt will be masked off To select between IRQ5 and FIQ please refer to Chapter Interrupt 4 INTPend R W I2C Bus TX RX Interrupt Pending Flag Read No interrupt C A I2C bus interrupt occurs pending 1 When a 1 byte transmitting or Read 1 Interrupt is pending receiving operation is terminated Write 0 No effect When a general call or slave address Write 1 Clear the flag match occurs If bus arbitration fails Generalplus Technology Inc PAGE 257 V1 0 Dec 20 2006 G Generalplus Function Type GPL162002A 162003A Programming Guide Description Condition TXCLK R W DC Bus Transmit Clock Pre scaler Transmitting clock frequency is determined by these 4 bits pre scaler value according to the following formula Tx clock I2CCLK P_I2C_Ctrl 3 0 1 Where 1 I2CCLK is determined by P I2C Ctrl 6 2 When P DC Ctrl 6 20 P I2C Ctrl 3 0 20x00 or 0x01 is not available P I2C Status 0x7B61 12C Status Register Bit 15 14 13 112111 11 0 9 1 8 7 6 5 4 3 2 1 0 Function Mod BY DataEN ArbSI SS AddrS LS Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 Reserved DC Bus Ma
241. Inc PAGE 65 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Interrupt happens Write 0 No Effect Write 1 Clear the flag 10 KCOEN R W Key change 0 Interrupt Enable 0 Disabled If this bit is set to 1 and bit9 KCEN in 1 Enabled P Clock Ctrl is set to 1 IOBO key change Interrupt is enabled eaf JL resevwa 5 EXTBIS R W EXTB Interrupt Edge Selection 0 Falling edge triggered This bit is valid only when EXTBIEN control 1 Rising edge triggered bit is set to 1 If this bit is set to 1 the EXTB is triggered on rising edge Otherwise itis triggered on falling edge 4 EXTAIS R W EXTA Interrupt Edge Selection 0 Falling edge triggered This bit is valid only when EXTAIEN control 1 Rising edge triggered bit is set to 1 If this bit is set to 1 the EXTA is triggered on rising edge Otherwise itis triggered on falling edge al resewes eD 2 1 EXTBIEN R W EXTB interrupt enable 0 Disabled If this bit is set as 1 PortD13 will be 1 Enabled configured as external interrupt B input pin If this bit is cleared to 0 PortD13 remains as GPIO EXTAIEN R W EXTA interrupt enable 07 Disabled If this bit is set as 1 PortD12 will be 1 Enabled configured as external interrupt A input pin If this bit is cleared to 0 PortD12 remains as GPIO Generalplus Technology Inc PAGE 66 V1 0 Dec 20 2006
242. KDIV Default 0 0 0 O 0 0 0 0 0 1 0 1 0 1 0 0 P SD BLKLEN 0x79D9 SD MMC Block Length Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BLKLEN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_SD_INT 0x79DA SD MMC Interrupt Enable Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOINT INSINT DBULEPT DBULFU CBULFU DCOM CCOM Default 0 0 0 0 0 0000 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 367 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Key Scan Register Summary Table Name Address Description P KS Ctrl 0x7BC0 Key Scan Control Register P KS Data 0x7BC8 Sample Data of Line IOA 0 P KS Data Ox7BC9 Sample Data of Line IOA 1 P KS Data2 Ox7BCA Sample Data of Line IOA 2 P KS Data3 P KS Data P KS Data5 P KS Data6 P KS Data7 P_KS Ctrl 0x7BCO Key Scan Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 2121110 Function INT C IEN AUTO FIXSTIME INV SMART STRSCAN BY ISTOPIB74OFF B31OFF B0OFF STIME TSEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0000 P KS DataO 0x7BC8 Sample Data of Line IOA 0 Bit 15 14 13 12 11 10 N9 8 1 6 5 4 3 2 1 0 Function Data Default 0 0 0 0 0 0 0 0 0 0 0 0 0
243. Key Array Header Referenced as JP30 This key array is for general purposed input s Each pin on JP30 connects to each corresponding key individually and then to the one common pin in the middle of JP27 This common pin can be easily shorted to high voltage or low voltage via a single jumper HEADER 3 GO O OI Q N c NENNEN Generalplus Technology Inc PAGE 380 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 25 5 Development Emulation Board Schematic Analog Input Audio Output Clock GPL162002A 162003A GPIO ICE UART IrDA 0 mm oo p gt Key Scan LCD Memory Nand Flash Power SDC USB z z r x lt Generalplus Technology Inc PAGE 381 V1 0 Dec 20 2006 A Generalplus GPL162002A 162003A Programming Guide A Analog input J6 ES PHONEJACK STEREO p X E n E 24 Du We E HEADE gt 2 E R 4 C6 ord P HD 1nF 1nF SW1 P de NA SW 2P2T AD_LFLT AD_RFLT IOB O 15 SW DIP 4 JP HEADER 2 G gt GE CS 1uF 1uF 1uF eN 9 u OO Es o 9 lt Y Y AA EIN INEIN_R AVCOMSSADC Si F E E A d ul ed INN LIN ENIS EN 2 C9 E u JP4 10uF C8 HEADER 2 0 1uF x o MICROPHONE A SW8 TESIP 3 ei 6 o S oc 5 z 4 R1 i R2 3 H a i 12 2 H E 2 2K 2 2K E SW 2P2T H m Cio 1uF Y MICBIAS NA MICIN Generalplus Technology Inc PAGE 382 V
244. L162002A 162003A Programming Guide P_TP_Ctrl 0x7965 Touch Panel Control Register Bit 15 14 13 12 11 101918171615 4 3 2 1 0 Function TPIF C TPIEN TPEN TPST TMOD DBEN DBTSEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_HQADC Ctrl 0x7970 High Quality ADC control Bit 1511411312 1110 9 8 7 6 5 4 3 2 1 0 Function DIV REC MONO BOOST INMODE PWADL PWADR MICBIAS ADMCLK Default 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 P_HQADC_PGAS 0x7971 High Quality ADC MICIN pre gain setting Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PGAS Default 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 P_HQADC_RGAIN 0x7972 High Quality ADC LINEINR gain settin Bit 15 14 1311211110 9 8 Fer 6 5 4 3 2 1 0 Function ADROV ADROV IEN LINEGR Default 0 0 0 0 0 0 00 0 0 0 0 1 0 0 0 P_HQADC_LGAIN 0x7973 High Quality ADC LINEINL gain setting Bit 15 14 13 12417101 918 716 5 4 3 2 1 0 Function ADLOV ADLOV IEN LINEGL Default 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Nand Flash Control Register Summary Table Name Address Description P NF Ctrl P NF CMD P NF AddrE P NF AddrH P NF Data P N
245. LL clock activating On the other hand the PLL clock is shut down in both halt and standby modes that will cause LCD unable to display in such modes Therefore Generalplus Technology Inc PAGE 126 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Generalplus recommends set the LCDEN control bit to 0 before entering halt mode and standby mode After GPL162002A 162003A wakes up from those modes set the LCDEN control bit to 1 again Simply programmers are able to turn on off LCD panel via the configuration of LCDEN control bit The GPL162002A 162003A will automatically perform the LCD power on off procedures in order to avoid unexpected lines occurring on the LCD panel 11 7 LCD Image Resource File Tooling Generalplus offers some PC tools to transfer BMP file to the LCD buffer format Tools are as follows PO4COLOR EXE SWAPWORD EXE BMP2GIM EXE and POBMP EXE KK KKK dee ee KKK kok e de e kok e e he kok kok k e e kok e hehe ee e e he e de kok e hehe ee e ee e e ehe e ehe ee e ehe de e he ee kok ee e ehe ee he ee de RIE RRR kok kok ERR kk kkk kk ER k kkk 256 Color BMP File to 1 Bit Per Pixel Format of LCD Buffer gt 2 Mono kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Conversion Batch File pobmp f2 1 bmp d o swapword 1 put raw o b4 Note there is no header in front of the raw file ee KK e ee
246. LOW state 12 SELF R W Self Refresh mode 0 Disabled If the external LCD driver s involves the 1 Enabled built in memory and supports the self refresh mode the LCD interface can be configured to self refresh mode The LCD driver shows the last display data and GPL162002A 162003A outputs FM FP LP signals only and be CP and LCD Data signal will remain at ground state D Reseed AO BUSW RAN LCD hardware data bus width configuration 007 1 bit LCDDO Valid 1 4 8 bit width is supported in 01 7 4 bit LCDD 3 0 Valid GPL 162002A 162003A 10 8 bit LCDD 7 0 Valid 112 Reserved lalo ne Bus Width configuration BUSW 1 0 00 1 bit LDO 01 4 bit LD3 0 10 8 bit LD7 0 11 Reserved The V represents support and X means not support owes oz Pez me mr Kaz filalelilalelilalelilalelilals Generalplus Technology Inc PAGE 119 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P LCD Clock 0x7981 LCD Clock Generation Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LCDCLK Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition pst Res po LCDCLK Pixel Clock Divider Range 0 1023 LCDCLK 9 0 SYSCLK LCDCOM 1 LCDSEG 1 Frame rate 2 where LCDCOM is number of common 1 LCDSEG is number of segment 1
247. Line IOA 7 Bit 154 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 Reserved 7 0 Date R Scan data is read from IOA 15 8 when IOA 7 is active This register store the scan data read from IOA 15 8 when the IOA 7 0 is set as 0b10000000 KSINV 0 or 0b01111111 KSINV 1 The data will be preserved until the next scan process happens Generalplus Technology Inc PAGE 302 V1 0 Dec 20 2006 G Generalplus 21 9 Example Program Manual FixSample keyloop loop keynum keysend r1 0x10000 32768 60 P_TimerD_Preload r1 r1 0xe062 P_TimerD_Ctrl r1 r1 0x9000 P_KS_Ctrl r1 r1 P_KS_ Ctrl jp keyloop ri P KS Ctrl P_KS_Ctrl r1 ri P IOB Buffer r1 0x0001 P_IOB_Buffer r1 r4 8 r1 0 r2 P_KS_Data0 r3 r2 jnz _keynum jnz loop jmp keyloop r3 r3 Isr 1 jz keysend r1 1 jmp keynum cmp r1 R_PreKey je keyloop _R_PreKey r1 _R_Press r1 jmp keyloop GPL162002A 162003A Programming Guide H TimerD 60Hz Enable TimerD Manual scan mode Fix sample time clear flag Generalplus Technology Inc PAGE 303 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide _IRQ4 push r1 to sp r1 P_INT_Status2
248. Line Parity LSB Register P ECC LPRH HB 0x7849 ECC High Byte Line Parity MSB Register P ECC CPR HB 0x784A ECC High Byte Column Parity Register P_ECC_LPR_CKL_HB ECC High Byte Line Parity Check LSB Register P_ECC_LPR_CKH_HB ECC High Byte Line Parity Check MSB Register P_ECC_CPCKR_HB ECC High Byte Column Parity Check Register P_ECC_ERRO_HB ECC High Byte Error FlagO P_ECC_ERR1_HB ECC High Byte Error Flag1 P CHECKSUMO LB NAND Flash Low Byte Check Sum Low Value P CHECKSUM 1 LB NAND Flash Low Byte Check Sum High Value P CHECKSUMO HB NAND Flash High Byte Check Sum Low Value P CHECKSUM1 HB NAND Flash High Byte Check Sum High Value P NF Ctrl 0x7850 NAND Flash Control Register Bit 15 14 1312 11 10 9 b8 7 6 5 4 3 2 1 0 Function NFBF 80r16 4 NFC7 NEC6 NFC5 NFC4 NFC3 NFC2 NFC1 NFCO Init 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Description Condition Read back busy status RB n 1 ready 0 busy 14 NF8or16 R W 8 bitor 16 bit Nand flash memory data access Ls E Reserved 7 0 NFCTRL RR W Adjustable setup hold time 7 6 tREH RE n high pulse tREH NFCTRL 7 6 1 x CPUCLK 5 4 tREA Access time tREA NFCTRL 5 4 1 x CPUCLK 3 2 tWH WE n high pulse tWH NFCTRL 3 2 1 x CPUCLK 1 0 WP WE n low pulse tWP NFCTRL 1 0 1 x CPUCLK P NF CMD 0x7851 NAND Flash Command Register B
249. MARQ ERRW TRANS EN DMATO STATE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_MISC1 0x7B8F DMA miscellaneous Conirol Register 1 Bit 15 14 13 12 1171019 8 7 6 5 41 3 2 1 0 Function DMARQ ERRW A IRANS EN DMATO STATE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_MISC2 0x7B97 DMA miscellaneous Conirol Register 2 Bit 15 14 13 12 1 t0op9 8 7 6 5 4 3 2 1 0 Function DMARQ ERRW1 TRANS EN DMATO STATE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_MISC3 0x7B9F DMA miscellaneous Control Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DMARQ ERRW TRANS EN DMATO STATE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA SPRISIZEO 0x7BBO DMA Sprite Size 9 0 Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SPRISIZE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L Generalplus Technology Inc PAGE 364 V1 0 Dec 20 2006 G Generalplus P DMA SPRISIZE1 GPL162002A 162003A Programming Guide P DMA SPRISIZE2 P DMA SPRISIZE3 P DMA TRANSPATO Function P DMA TRANSPAT1 Function Function Function
250. MBCCR W Writing 0x5555 to this control register will reset the internal timebase counter for precise timing correction control Generalplus Technology Inc PAGE 83 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 8 4 Program Examples L_PollingTimeBase r1 0x0007 IP IOA Attrib r1 P IOA Dir r1 Setup IOA 2 0 as output buffer low r1 0xA001 IP TimeBaseA Ctrl r1 H Setup TimeBaseA Frequency as 1Hz IP TimeBaseB Ctrl r1 J Setup TimeBaseB Frequency as 16Hz P TimeBaseC Ctrl r1 H Setup TimeBaseC Frequency as 256Hz L CheckTimeBaseOverflow ri P TimeBaseC Ctrl jp L EndCheckTimeBaseC P_TimeBaseC_Ctrl r1 Clear TimeBaseC Flag ri P IOA Buffer r1 r1 xor 0x0004 P IOA Data r1 H Toggle IOA2 frequency 0 5Hz 1Hz 2 L EndCheckTimeBaseC r1 P_TimeBaseB_ Ctrl jp L EndCheckTimeBaseB P_TimeBaseB_Ctrl r1 Clear TimeBaseB Flag r1 P IOX Buffer r1 T1 xor 0x0002 ID IOA Data r1 H Toggle IOA1 frequency 8Hz 16Hz 2 L EndCheckTimeBaseB r1 P_TimeBaseA_ Ctrl jp A CheckTimeBaseOverflow P_TimeBaseA_Ctrl r1 Clear TimeBaseA Flag ri P IOA Buffer r1 r1 xor 0x0001 IP IOA Data r1 H Toggle IOA0 frequency 128Hz 256Hz 2 jmp L CheckTimeBaseOverflow Generalplus Technology Inc PAGE 84 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 9 Real Time Clock RTC 9 1 In
251. N Schedule Interrupt Flag Clear Read 0 Not Occurred Write 1 to clear the flag Read 1 2 Occurred This bit is set to 1 by hardware if the Write 0 No Effect scheduler interrupt is asserted Write 1 Clear the flag ga 7 Rea 000000 Le 3 HRIF C R W Hour Interrupt Flag Clear Read 0 Not Occurred Write 1 to clear the flag Read 1 Occurred This bit is set to 1 by hardware if the Write 0 No Effect hour interrupt is asserted Write 1 Clear the flag MINIF C R W Minute Interrupt Flag Clear Read 0 Not Occurred Write 1 to clear the flag Read 1 Occurred This bit is set to 1 by hardware if the Write 0 No Effect minute interrupt is asserted Write 1 Clear the flag SECIF C R W Second Interrupt Flag Clear Read 0 Not Occurred Write 1 to clear the flag Read 1 Occurred This bit is set to 1 by hardware if the Write 0 No Effect Generalplus Technology Inc PAGE 88 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Conaition _ second interrupt is asserted Write 1 Clear the flag HSECIF C R W Half Second Interrupt Flag Clear Read 0 Not Occurred Write 1 to clear the flag Read 1 Occurred This bit is set to 1 by hardware if the Write 0 No Effect half second interrupt is asserted Write 1 Clear the flag
252. NANDStatus Byte push r1 to sp ri P INT Status1 test r1 C INT DMA jz End IRQ3 r1 P_DMA INT P_DMA_INT r1 test r1 DMA CHO INT jz End IRQ3 r1 1 R_DMAFlag r1 pop r1 from sp reti Generalplus Technology Inc PAGE 248 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 18 I2C Controller 18 1 Introduction The multi master I2C bus controller provides a mechanism to communicate between bus masters and peripheral devices by using two signals a serial data line SDA and a serial clock line SCL To avoid all possibilities of confusion data loss and blockage of information the master and slave devices must have a well defined protocol In multi master I2C bus mode multiple microprocessors can receive or transmit serial data to or from slave devices The master that initiates a data transfer over the I2C bus is responsible for terminating the transfer It is possible to combine several masters with several slaves onto an I2C bus to form a multi master system If more than one master simultaneously tries to control the bus an arbitration procedure decides which master gets priority The maximum number of devices connected to the bus is dictated by the maximum allowable capacitance on the lines 400 pF Master transmitting and receiving mode Slave transmitting and receiving mode Detection of bus arbitration failure e Interrupt generation Programmable ACK g
253. Not Occurred This bit is set to 1 by hardware if the TimebaseA 1 Occurred interrupt is asserted For details refer to chapter TimeBase interface Reserved eo SD Controller Interrupt 0 Not Occurred This bit is set to 1 by hardware if one of the events of 1 Occurred SD controller occurrs For details refer to chapter SD MMC interface I2C Controller Interrupt 0 Not Occurred This bit is set to II by hardware if one byte is 1 Occurred transmitted received on the DC bus or when address matches In DC Slave mode For details refer to chapter DC interface Mali 7 c ss For details referto chapter NAND Flash interface ERE Occurred EHE ASA Reserved SCHIF Schedule Interrupt Flag 0 Not Occurred This bit is set to 1 by hardware if the scheduler interrupt 1 Occurred is asserted For details refer to chapter Real Time Clock 1 ALMIF Alarm Interrupt Flag 0 Not Occurred This bit is set to 1 by hardware if the alarm interrupt is 1 Occurred asserted For details refer to chapter Real Time Clock HMSIF HMS Interrupt Flag 0 Not Occurred This bit is set to 1 by hardware if the hour or minute or 1 Occurred second or half second interrupt is asserted For details refer to chapter Real Time Clock P_INT_Priority1 0x78A4 Interrupt Priority 1 Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function KEYIP
254. OV the power on reset occurs It has some probability that the power on reset does not occur due to unstable operation voltage The Super reset mechanism is necessary to avoid this condition Super reset circuitry The application circuit is shown below It detects the variance of operating voltage and keeps the RESET signal as low state when operating voltage is charging from ground to stable state When the operating voltage is in stable state the Reset signal releases from 0 to 1 1N4148 Note When the reset circuit applied to the application is more sensitive to generate the reset signal user can add the resistor R1 and capacitor C1 to reduce the sensitivity of the reset signal 25 10 Important Note for the Setup of Memory Access Time GPL162002A 162003A provides flexible adjustment of external memory access time Through the adjustment of memory access time and flexible clock selection users can fine tune the system performance For example when PLL clock is 48MHZ it means it has 20 8ns per clock cycle In this case when accessing the external memory which has minimum access time 55ns it takes 3 clock cycles to supply enough time to memory accessing When PLL clock is 24MHZ it means 41 7ns per clock cycle So it needs 2 clock cycles to supply enough accessing time There are six independent control registers to set the memory accessing time on GPL162002A 162003A which are P MCSO Ctrl 0x7820 P MCS
255. Over Write Mode 0 The further write to the full This register is used to control the data FIFO will be skipped which will be overwrite or skipped when 1 The further write to the full TX RX FIFO is full FIFO wil overwrite the last written data in the FIFO 8 SMART SPI FIFO SMART Mode Register 0 Normal Interrupt Clear Generalplus Technology Inc PAGE 176 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide A Desorption L o cenawon When this bit is set to 1 programmers 1 Smart Interrupt Clear do no need to clear the Note Generalplus suggest transmitting receiving interrupt flag when programmer enable this bit for the FIFO status is reached SPI function work correctly programmers only need to write to read from transmitting receiving FIFO and keep the FIFO level lower higher than the interrupt level and the interrupt flag will be cleared automatically wst f frese M M SPI Controller Busy Flag This bit is used to indicate if the SPI controller is busy or not Receive FIFO Full Flag 0 Receive FIFO not full This bit is used to indicate if the SPI 1 Receive FIFO full not empty controller is real full or not f the slot receive FIFO is full any data read from SPI bus cannot be written into the FIFO and the RFOV bit will be set Im this situation Receive FIFO Not Empty Flag 0 Receive FIFO is empty This bitis used to indicate if ther
256. P SLEEP P Power State P PLLN P_PLLWiatCLK P_AD_Driving Generalplus Technology Inc PAGE 13 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 3 2 Device Identification P BodyID 0x7800 Body ID Number Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function 0x8688 Default 1 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 Bit Function Type Description Condition 15 0 BODYID Body Identification Register 0x8688 for For GPL162002 and GPL162003 the ID number is GPL162002 and fixed to 0x8688 GPL 162003 3 3 Reset Control P_Reset_Flag 0x7806 Reset Event Flag Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function A NDG WDE MPE LVR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 naal Reseved Le O 4 WDG R W Watchdog Timeout Reset Flag Read 0 Not Occurred Read 1 Occurred Write 1 Clear the flag 3 WDE RAW Watchdog Error Write Flag Read 0 Not Occurred If programmers do NOT write OxA005 to clear Read 1 Occurred watchdog timer this bit will be set to 1 by Write 0 No Effect GPL 162002A 162003A and CPU will be reset Write 17 Clear the flag 2 MPE R W Mode Protect Error Write Flag Read 0 Not Occurred If programmers do NOT write 0x5005 to enter Read 1 Occurred wait mode or NOT write 0x500A to enter halt
257. PIPO Virtual Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPO VIR SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 336 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TFT_PIP1_VIR_SAH 0x7D1E TFT PIP1 Virtual Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1_VIR_SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP2_VIR_SAH 0x7D29 TFT PIP2 Virtual Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2 VIR SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 VIR SAH 0x7D34 TFT PIP3 Virtual Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP3_VIR SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIPO_VIR_SAL 0x7D14 TFT PIPO Virtual Frame Buffer Start Low Address Bit 151 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPO_VIR_SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP1_VIR_SAL Ox7D1F TFT PIP1 Virtual Frame Buffer Start Low Address Bit 15 14 13 12 14 410 9 8 7 6 5 4 3 2 1 0 Function
258. PY0030 Generalplus Technology Inc PAGE 93 V1 0 Dec 20 2006 G Generalplus 10 3 B Int 10 4 GPL162002A 162003A Programming Guide lock Diagram EEN I A I I DAC Channel A f EN ata erface FIFO See data me m vE vu1e6e YE V ier m 8 d I I I CHA Ihterrupt r O CHA DMA Reguest IIS signal i g Controller 3D EQ AC HS DAC HeadPhone I controller controller controller d aS mia ap i I I z DAC Channel B L N FIFO oi data I z 16X16 i Ed gt g 8 I CHB Interrupt E HA DMA Res Esc i Controller gt I I Speech Mode In GPL162002A 162003A data written to data control register P CHA Data or P CHB Data will be saved in FIFO buffer d rate such as 8 KHz F To playback voice or audio sound programmers need to obtain appropriate PCM ata and then write them to corresponding data control register with certain frequency known as sample When the corresponding timer overflows the audio controller will send the data in IFO to audio output In GPL162002A 162003A SRC controls the sample rate for CHA and CHB respectively To obtain appropriate PCM data depends on the decompression algorithm programmer C hosen GPL162002A 162003A has a built in 7 band EQ These 7 band center fr
259. Palette is a table with the depth equal to the number of index For example palette depth of 4 bit per pixel configuration is 16 palette depth of 8 bit per pixel configuration is 256 Table value for each index is the real display color information 12 bit range form 0 4095 According the mapping information in the palette GPL162002A 162003A can automatically and easily convert the index value in LCD buffer to the real display color Following diagram depicts the relationship between LCD buffer palette and a real display image Note that if palette is activated maximum number of display colors is the depth of Palette at one time Certainly programmers can change display color level in color index pixel value dynamically by modifying corresponding Palette registers NENNEN Generalplus Technology Inc PAGE 115 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide pixel value Real Display color index RGB information 01 lt E ss bit 15 141312 210 First Word of LCD buffer Palette LCD butter LCD Diaply Screen Video Memory GPL162002A 162003A Palette location starts with 0x7A00 of CPU view For color configuration the valid bit in each word of Palette is 12 bits On the other hand for gray level configuration the valid bit in each word of Palette is only 4 bits Please refer to the following table Gray Level
260. Pointer 0x7B43 USB Endpoint0 Buffer Pointer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EPOWBP EPORBP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O Generalplus Technology Inc PAGE 348 V1 0 Dec 20 2006 GPL162002A 162003A Programming Guide G USB Bulk IN Buffer Pointer Register 0 Generalplus P_USBD_BIBufPointer 0x7B44 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Function BIBWP BIBRP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_BOBufPointer 0x7B45 USB Bulk OUT Buffer Pointer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BOBWP BOBRP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_EPORTR 0x7B46 USB Endpoint0 bmRequestType Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EPORTR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_EPORR 0x7B47 USB Endpoint0 bRequest Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EPORR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_EPOVR 0x7B48 USB Endpoin
261. RWUPEN SPWR USBEN TNSPL TNSPH BYPASS Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD Device 0x7B57 USB Device Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 31211 0 Function EPA Type EP3 Type EP2 Type EP1 Type EP4 IO EP3 IOERZ IO EP1 IO MOD Default 0 1 1 1 1 0 1 0 0 1 0 1 000 0 P_USBD_Function 0x7B31 USB Function Register Bit 1511413 112 11 10 9 8 7 615413121110 Function _ SRST DMA_BOEN DMA BIEN Config_Value FNC_Addr Default 0 0 O O 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD DMAINT 0x7B59 USB DMA Interrupt Register Bit 15114113 12 11 1019 8 7 6 5 14 3 2 1 0 Function AP ate IDMAINTEN_CLR IDMAINTENIDMAINTF Default 0 0 0 0 0 0 0 0 0 0 0 0 O 0 0 0 P_USBD_PMR 0x7B32 USB Power Management Register Bit 154 14 43 12 111110 9 18171615 4 3 2 1 0 Function lt 4 JRESWKERE WARE WAFEA RST SUS Mod Default 0 0 0 0 0 0 0 0 0 0 O 0 0 0 0 0 P_USBD_EP0Data 0x7B33 USB Endpoint0 Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EPODATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P USBD BliData 0x7B34 USB Bulk IN Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BIDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 346 V1 0 Dec 20 2006 G General
262. Read 1 no in RX FIFO 8 For FIFO is enabled 8 depth If FIFO is disabled FEN 1 Read 0 RX buffer is not full This bit is set to 1 when the receive Read 1 RX buffer is full FIFO is full For FIFO is disabled 1 depth FEN 0 This bit is set to 1 when the receiving hold register is full Note that this flag is read only hardware will set or clear this flag automatically 5 TXFF Transmit FIFO Full Flag If FIFO is enabled The meaning of this bit depends on the Read 0 no in TX FIFO lt 8 state of the FEN control bit Read 1 no in TX FIFO 8 For FIFO is enabled 8 depth If FIFO is disabled FEN 1 Read 0 TX buffer is not full This bit is set to 1 when the Read 1 TX buffer is full transmitting FIFO is full For FIFO is disabled 1 depth FEN 0 This bit is set to 1 when the transmitting hold register is full Generalplus Technology Inc PAGE 162 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Note that this flag is read only hardware will set or clear this flag automatically Receive FIFO Empty Flag If FIFO is enabled The meaning of this bit depends on the Read 0 no in RX FIFO gt 0 state of the FEN control bit Read 1 no in RX FIFO 0 For FIFO is enabled 8 depth If FIFO is disabled FEN 1 Read 0 RX buffer is not empty This bit is set to 1 when the receiving Read 1 RX buffer is empty FIFO is empty For FIFO is disa
263. S BINA BIPC EOSNA E0SC EOINNA EOINPC EOONA EOOPS EOSPS Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition Reset Interrupt Flag If the corresponding bit P_USBD_INTEN is 1 and the USB device is reset the interrupt flag will be set enable of Resume Interrupt Flag If the corresponding bit P_USBD_INTEN is 1 and the USB device resumes in SUSPEND state the interrupt enable of flag will be set Suspend Interrupt Flag If the corresponding enable bit P USBD INTEN is 1 and the USB device is suspended the interrupt flag will be set of IINNA Interrupt In NACKAnterrupt Flag If the corresponding enable bit P USBD INTEN is Tand an IN request happens with rplying a NAK to the host this of bit will be set Interrupt In Packet Clear Interrupt Flag H the corresponding bit P_USBD_INTEN is 1 and an IN packet is read from the host this bit will be set Bulk Out NACK Interrupt Flag If the corresponding bit P USBD INTEN is 1 and an OUT packet happens but the device sends a NAK this enable of enable of BONA BOPS BINA Generalplus Technology Inc bit will be set Bulk Out Packet Set Interrupt Flag If the corresponding bit P USBD INTEN is 1 and an OUT packet is loaded into the endpointO FIFO this bit will be set Bulk In NACK Interrupt Flag If the corresponding bit P USBD INTEN is 1 and an IN request happens with rplying a N
264. S PWSPL IPWSPR Default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 P DAC IIS Ctrl 0x78FF DAC IIS Mode Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function 1S_MCLK IIS BITS IIS MODE IISEXT IISEN Default 0 0 0 0 0 0 0 O 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 328 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_DAC_ACCREQ 0x7BF0 3D EQ AC Parameter AccessRequesr Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RDY WRITE 3D ADDR Default 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DAC_ACCDINL 0x7BF1 3D EQ AC Parameter Data Input Low Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DATAIN 15 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DAC_ACCDINH Ox7BF2 3D EQ AC Parameter Data Input High Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DATAIN 23 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DAC EFF Ctrl Ox7BF3 3D EQ AC Control register Bit 15 14 13 12 11 10 F9 h8 7 65 4 3 2 140 Function 3DEN 2CH HP
265. S10 D3 ik 1 2 DIODE D4 1 2 DIODE JP54 SW DIP 8 D5 1 a LK on 1 DIODE E 5 12 TOM ER E D6 H E 3 14 1 2 7 T 2 15 o TOA7 1 16 DIODE Bm HEADER 8 D7 1 2 DIODE D8 1 2 DIODE D9 1 2 DIODE VCC 33 LCDD8 LCDD9 LCDDT0 LCDDTT TCDDTZ LCDDT3 DISOER Cem ECDEP vec_33 ICDFE Kw o LCDDO LCDDT ECDDZ LCDD3 LCDD4 TCDD5 EDD LCDD7 C83 1 x 4 0 1uF LCDDi4 LCDD15 CMT TMZ TMS CME HEADER 16X2 1OC 0 15 VCC_33 JP57 1 DISOFF 2 LCDEN HEADER 2 LCDD0 LCDD1 LCDDZ d LCDD3 LCDD4 o LCDD5 LCDD6 LCDD7 LCDD8 o LCDDS LCDD10 o LCDD11 JP56 LCDD12 a LCDD13 CM1 LCDD14 o LCDD15 1 TCDFM o LCDFP z LCDLP LCDCP 3 Oo N HEADER 10X2 HEADER 4 Generalplus Technology Inc PAGE 388 V1 0 Dec 20 2006 GPL162002A 162003A Programming Guide Generalplus J Memory MCS4 MCS3 WE MCS1 MOE RESETB ICECKICEDA MCSO MA23 MA22 MCS2 MA21 X lM4222 22222Z22 MA20 MA19 JP59 HSVTA HSV14 39nW3 AVES 3903 Wvus MA 0 16 ae C124 SOL Ken 10uF Lh 0 1uF C423 swa VCC_MEM gt SW 2P2T VC MEM A EMUCE H gt MD O 15
266. SEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TimerC CCP Ctrl 0x78D1 TimerC CCP Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 13 2 1 0 Function CCPCEN CAPCSEL CMPCSEL PWMCSEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 14 CCPXEN R W Operation Mode Selection 002 CCP Mode Disabled Default is timer counter mode 01 2 Capture Enabled When capture mode is selected PortBX 10 Comparison Enabled becomes INPUT automatically and any 11 PWM Enabled GPIO setting will have no effect When comparison and PWM mode is selected PortBX becomes OUTPUT automatically any GPIO setting will have no effect lt should be noted TimerD TimerE amp TimerF do not have their specified output pin so capture and PWM mode is not valid for these four timer ppp O Reseed 000 d CAPXSEL R W Capture Operation mode Selection 00 every falling These 2 bits are valid only when 01 every rising CCPXEN is set to 01 in binary 107 reserved 112 reserved TS Reseed po 5 4 CMPXSEL R W Comparison Operation Mode Selection 00 high pulse on CCP X These 2 bits are valid only when 01 low pulse on CCP X CCPXEN is set to 10 in binary 10 unaffected on CCP X 11 reserved iz JL Reese 1 0 PWMXSEL RW PWM Operation Mode Sel
267. SVIS IN A15 y WE 59 33HOQVA EMUCE ONS FAL EMUCE EE MCS4D4 345 10D4 LINEIN_R 755 Y NINO MCS3D3 140 lOD3 FMIN_L sg MCS2D2 347 OD2 FMIN R 54 M NIA MCS1D4 1487 OD1 AD_LFLT 53 1131 Qv MS lt gt jag OD0 AD REUT 52 IOA0 VSS_ADC L 51 IOA1 VCC_ADC e IOA2 TESTP a n TESTP 1OA3 TESTN HS TESTN e DAC L 47 DAC L eg VSS_SPK s 1OAG VSS DAC IQA7 DAC_R 45 QVO SSA DAC R 1OAB VCC SPK His 1948 VCC DAC 10A10 VDACREF LZ SE NC BM2 2222 ous E Oo ol gt JP47 H 2 1 HEADER 2 A AVCCAD VSSADC C53 i E ES D SI 9 och C52 al SI JP46 H Hi Out HEADER 2 A AVCCSPIAVSSSPK C77 to 0 tUF C71 10uF C76 El d cu TH 0 1uF Q 1uF C67 VCC18 an 10uF 0 1uF C64 ES Gr H DA EN H O 10F C60 HH ey d DAN He E VCC33 Generalplus Technology Inc PAGE 385 V1 0 Dec 20 2006 A Generalplus GPL162002A 162003A Programming Guide E GPIO JP16 S1 S2 S3 S4 ER 56 s7 S8 ENTORNO 2324 LOROKOK A o d a SF Y 2 9 sj an sr sp sp sf a so DiH ob ob ok ok ok ok os o WEI WEI WEI TERY 15 Y WEI REZ dn Bie Mi i Dl E SN IS SW DIP 4 al de d d d e a sz e al ei e
268. Sample Data of Line IOA 0 Bit 15 14 135112 h11 10 9 8 7 6 5 4 3 2 1 0 Function E Data0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 7 0 past Scan data is read from IOA 15 8 when IOA 0 is active Reserved This register stores the scan data read from IOA 15 8 when the IOA 7 0 is set as 0500000001 KSINV 0 or 0b11111110 KSINV 1 The data will be preserved until the next scan process happens P_KS Datal 0x7BC9 Sample Data of Line IOA 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 Reserved Generalplus Technology Inc PAGE 300 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Type Description Condition Scan data is read from IOA 15 8 when IOA 1 is active This register stores the scan data read from IOA 15 8 when the IOA 7 0 is set as 0000000010 KSINV 0 or 0611111101 KSINV 1 The data will be preserved until the next scan process happens P KS Data2 0x7BCA Sample Data of Line IOA 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data2 Defaul
269. Set 0x7B3D USB Endpoint Auto Set Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EPOASE IAINPR BAOPE BAIPR EOAIPR EOAOPE Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition reg Reseed po O EPO Auto Status Enable Set aE Please refer to P USBD EPEvent 6 He EN Please refer to P USBD EPEvent 14 EN l GE Please refer to P USBD EPEvent 11 or 12 APA Please refer to P USBD EPEvent 8 KE odka Please refer to P USBD EPEvent 4 pera Please referntoP USBD EPEvent 1 or 2 P USBD EPSetStall Ox7B3E USB Endpoint Set Stall Register Bit 15 14 13 122 11 10 97 8 7 6 5 4 3 2 1 0 Function TINS BOS BIS EPOS Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sa EN EP L 0 disable STALL response M deen H 0 disable STALL response 1 BIS R W Bulk In Set Stall 1 enable STALL response 0 disable STALL response EPOS R W EPO Set Stall 1 enable STALL response Write 1 to this bit to generate a STALL 0 disable STALL response signal if a host request happens This bit is automatically cleared if one of SETUP commands is loaded into endpointO FIFO Generalplus Technology Inc PAGE 197 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P USBD EPBufClear 0x7B3F USB Endpoint Buffer
270. TPST 7165 12 l Trigger x Failing Edge Triger Ee l N7 VSS Generalplus Technology Inc PAGE 217 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide The area in dash line is the touch panel equivalent circuit outside of GPL162002A 162003A The TSPX and TSMX are connecting pins to touch panel X Layer equivalent horizontal resistor Similarly TSP Y and TSMY are connecting pins to touch panel Y Layer equivalent vertical resistor When stylus taps on touch panel X Layer and Y Layer are inter connected In other word horizontal resistor and vertical resistor can be considered as electrical contact The following table depicts switches status in different modes Interrupt Mode s W0 X axis measurement Y axis measurement During touch panel interrupt mode and stylus tapping on touch panel there will be a falling edge signal after Schmitt trigger This signal informs GPL162002A 162003A that the touch panel is tapped During touch panel operation mode and stylus tapping on touch panel X coordinate value can be determined by measuring the Y layer from TSPY pin according to voltage dividing principle Similarly Y coordinate value can be determined by probing the X layer from TSPX Pin Note that if stylus does not tap on touch panel the x or y coordinate value obtained from operation mode will be invalid Therefore software must ensure that stylus is tapping wh
271. Technology Inc PAGE 44 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide IOD12 Pin Special Function Shared Information Special Function External Interrupt A TimerX Clock Source 1 0 Mode Supported Floating With pull low resistor With pull high resistor Floating With pull low resistor With pull high resistor Enable Control bit P_MINT_Ctrl bitO 1 P TimerX Ctrl bit 3 0 7 10D13 Pin Special Function Shared Information Special Function 1 0 Mode Supported External Interrupt B Floating TimerX Clock Source With pull low resistor With pull high resistor Floating With pull low resistor With pull high resistor Enable Control bit P_MINT_Ctrl bit1 1 P_TimerX_Ctrl bit 6 4 7 Description When one of these modes is enabled direction control bit P_IOD_Dir bit12 is forced to 0 That is original content of direction control bit will be ignored Programmers can configure 3 input modes by modifying corresponding data and attribution control bit directly P_IOD_Data bit12 P_10D Attrib bit12 00 with pull low resistor 01 with pull high resistor 1X floating GPIO All modes AI pa Description When one of these modes is enabled direction control bit P IOD Dir bit13 is forced to 0 That is original content of bit will be Programmers can direction control ignored configure 3 input modes by modifying correspo
272. UL 1 Enable MA21 is shared with DIL 1 Enable MA20 is shared with IOD 8 1 Enable Generalplus Technology Inc PAGE 37 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 2 MA19 R W Address bus MA19 enable pin 0 Disable MA19 is shared with IOD 7 1 Enable MA18 is shared with IOD 6 1 Enable MA17 is shared with IOD 5 17 Enable 4 6 Bank Switch Control As mentioned in the previous sections GPL162002A 162003A is able to access totally 81920KW However in CPU view it can only address up to 4MW 0x000000 Ox3FFFFF To use the address space larger than Ox3FFFFF programmers need to set bank switch control register before accessing the space The address from 0x0020 0000 to 0x003F_FFFF is the memory space used to switch bank and each bank size is 2MW 0x0000 0000 RAM 30KW 0x0000 7800 Peripheral System Control CSO 0x0000 8000 0x0002 8000 0x0003 0000 0x0020 0000 0x0040 0000 0x0060 0000 0x0020 0000 Ox0040 0000 0x0080 0000 Ox00AO 0000 Generalplus Technology Inc PAGE 38 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_BankSwitch_Ctrl 0x7810 Bank Switch Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Bank Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit Function Type Description Condition _ nse Reserved R Reewed 363 5
273. UL CHB EIFO full flag 0 FIFO is not full This flag is set to 1 by hardware if 1 FIFO is full the FIFO is full If the flag is 1 any data written via P CHB Data is invalid FFUNRN CHB FIFO under run flag 07 FIFO is not under running ET This flag is set to 1 by hardware if 1 FIFO is under running the FIFO is under running If the flag is 1 the output of DAC is keep last output value mal gt A Reseed le FRST W FIFO reset Write 0 No effect Write 1 FIFO reset 7 4 CHBFEILV RW CHB FIFO Empty Interrupt Level FIFO Empty Interrupt issue timing These control bits are used to set 0000 Reserved FIFO empty interrupt timing that is 0001 when of data in FIFO lt 1 enabled on FEMIEN of P CHB Ctrl 0010 when of data in FIFO lt 2 register It defines the number of 0011 when of data in FIFO lt 3 data left in FIFO to be considered as empty by hardware The larger the value is the higher frequency of the FIFO empty interrupt happens The 1110 when of data in FIFO lt 14 wee waa Space Technology Inc PAGE 100 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide smaller the value is the less 1111 when of data in FIFO lt 15 frequency of the FIFO empty interrupt occurs Consequently it saves the CPU bandwidth 3 0 CHBFINX CHB FIFO used Default 0000 0000 0 data is in FIFO FIFO is a 16X16 bit ring buffer 0001
274. VS_POL VS_WIDTH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_RGB_CTRL 0x7D0B TFT RGB Mode Conirol Register Bit 15 14 1312111110 9 8 7 6 5 4 3 2 1 0 Function RGB M RGB DMEN Ap MN ODD_L_TYPE EVEN L TYPE Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_YUV_CTRL 0x7D0C TFT YUV Mode Control Register Bit 15 14 13 12111110 91 8171615 4 212 1 0 Function YUV EN YUV_M CCIR656_EN ISHARE YUV_TYPE Default 0 0 0 00000 0 0 0 1 0 0 0 0 P_TFT_DMASTART_AH 0x7D0D TFT DMA Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DMA_SAH Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_DMASTART_AL Ox7DOE TFT DMA Start Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DMA SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 335 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TFT_DM_OFFSET 0x7D0F TFT DMA Offset Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DMA_OFFSET Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 P_TFT_PIXEL_NUM 0x7D10 TFT Pixel Numbers in Each Line Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIXEL NUM
275. W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P IOC Data 0x7870 IOC Data Register Bit 15 114 13 12N 11 10 9 8 7 6 5 4 3 2 1 0 Function IOCDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P IOC Buffer 0x7871 IOC Buffer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOCBUF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P IOC Dir 0x7872 IOC Direction Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOCDIR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 319 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_IOC_Attrib 0x7873 IOC Attribution Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOCATT Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_IOD Data 0x7878 IOD Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IODDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P IOD Buffer 0x7879 IOD Buffer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IODBUF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_IOD Dir 0x787A IOD Direction Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IODDIR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P IOD Attrib 0x787B IOD
276. W Word Length Definition 00 5 bits Indicate number of data bits transmitted or 01 6 bits receivediin a frame 107 7 bits 117 8 bits 4 FEN R W FIFO Buffer Enable Disable 07 Disabled Setting this bit to 1 will enable 16 depth FIFO 1 Enabled buffer on receiving operation and 2 depth FIFO buffer on transmitting operation When clearing this bit to 0 the FIFO becomes 1 byte deep hold registers 3 SBSEL R W Stop Bit Size Selection 0 1 Stop Bit When this bit is set to 1 two stop bits are 1 2 Stop Bit transmitted at the end of the frame The receiving logic cannot check for data with two received stop bits 2 PSEL R W Parity Selection 0 Odd Parity if PEN 1 If this bit is set to 1 even parity generation and n Even Parity if PEN 1 checking are performed during transmission and reception which checks for an even number of 1s in data and parity bits When cleared to 0 Generalplus Technology Inc PAGE 159 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide the odd parity is performed to check for an odd number of 1s This bit has no effect until parity is enabled by setting PEN Control bit to 1 Parity Enable 0 Disabled If this bit is set to 1 parity checking and 1 Enabled generation is enabled or else parity is disabled and no parity bit is added to the data frame Send Break 0 Normal Operation If this bit is set to 1
277. Wait Card Busy Write SD Sector IP SD ArgL r3 P SD ArgH r4 r2 0x1398 J Send SDC Command 24 Response R1 P SD CMD 12 J SDC Command Run SDC Command call Wait CMD Complete with Data SDC Transmit Data r1 Response Receive response r2 P_SD_RespL r1 r2 r2 P_SD_RespH r1 r2 O Generalplus Technology Inc PAGE 292 V1 0 Dec 20 2006 G Generalplus Write Finish GPL162002A 162003A Programming Guide r1 Load_High_Addr r2 Load_Low_Addr ds r1 r4 256 Write 256 words H Load High word Load Low word call Wait Data Empty r3 ds r2 P_SDC_DataTx r3 r4 1 jnz Write_Finish call Wait Controller Busy call Wait Data Complete call Wait Card Busy Generalplus Technology Inc PAGE 293 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 21 1 21 2 21 3 21 Key Scan Controller Introduction The key scan controller of GPL 162002A 162003A provides the hardware key scan function which shares IO with LCD interface without affecting the LCD display When LCD is not turned on the key scan controller can still work The key scan controller supports up to 64 keypads when using IOA 15 0 Hardware interrupt and auto detect function are also provided Support up to 64 keypads Share IO with LCD interface Key scan function still works when LCD is off or IOA is not shared Interrupt generation Automatic detection of key be
278. _DMA Ctrl 15 is set to 0 only the reading operation will decrease the counter This is only valid when SRCBYTE in P_DMA Ctrl 12 or TARBYTE in P DMA Ctrl 13 is set to 1 P DMA SRC AddrHO 0x7B84 DMA Source High Address Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 443 2 1 0 Function SRC AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA SRC AddrH1 0x7B8C DMA Source High Address Register 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SRC AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 O 0 0 0 P_DMA_SRC_AddrH2 0x7B94 DMA Source High Address Register 2 Bit 15 14 13 12 41 10 9 8 7 6 5 413 2 1 0 Function E SRC AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 O 0 0 0 P_DMA SRC_AddrH3 0x7B9C DMA Source High Address Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function 4 SRC_AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 O 0 0 0 Bit Function Type Description Condition 15 10 Reservede 90 SRC AddrH DMA Source High Address 25 16 J The P DMA SRC AddrHx registers are the source high address 25 16 registers The value in these registers will be increased decreased when a word is read and the SF in P DMA Ctrl 7 is O It should be
279. _Stage obj ISA ORAM Sertinn LISA TniFial nhi SDCDriv lt USB RA Ser USED F vfs h 01 External Dei Y gt Cancel 1 Obj amp Lib modules Show all object and library modules in current project 2 Merged section List the merged segments in current project 3 Non merged section List the non merged sections in current project You can change the address or align base of these sections by double click on the ROM field and the specified sections will be located at proper aligned addresses after re linking this project Generalplus Technology Inc PAGE 401 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Redefine Setting ES Pl memory files General Option Link Section 3 Hardware BreakPoint PreDownload Be_4 J Source Files e i Alias 3 Head Files TM Alas 3 External Depen CMacro1216 lib Redefine table Edit Delete Redefine N Module or Obj en 1 Alias Select an section from the list Window oflibraries and rename it 2 Edit Edit the selected item in the Redefine table list window It is the same with double clicking on the item in the Redefine table list 3 Delete Delete a selected item in the Redefine table list window Generalplus Technology Inc PAGE 402 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Hardware 2 EI memory files General
280. ag Register Bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Function GSTS CFEA SFEA SADD GCON SCON GINT SINT Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_EPAutoSet 0x7B3D USB Endpoint Auto Set Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EPOASE IAINPR BAOPE BAIPR EOAIPR EOQAOPE Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_EPSetStall 0x7B3E USB Endpoint Set Stall Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function E IINS BOS BIS EPOS Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P USBD EPBufClear Ox7B3F USB Endpoint Buffer Clear Register Bit 15 14 13 12 11 10 9 817416 5 4 3 2 1 0 Function JINBCI IBOBC BIBC EPOBC Default 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 P USBD EPEvntClear 0x7B40 USB Endpoint Event Clear Register Bit 15 14 13 12 11 10 9 8 7 1 6 5 4 3 2 1 0 Function A IINPC BOEC BIPC EPOSC EPOIPC EPOOEC Default 0 0 O 0 0 On 0 0 0 O 0 0 0 0 0 0 P_USBD_EPOWrtCount 0x7B41 USB Endpoint0 Write Count Register Bit 154 14 134 12 11 10 9 8 7 6 5 4 3 2 1 0 Function E EPOWC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_BOWrtCount 0x7B42 USB Bulk OUT Write Count Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BOWC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_EPOBuf
281. al Please refer to the EE diagram 1 C ria Reseed m MVAL R W Define the frequency of frame modulation when 0 255 C type is active For B Type Frame Modulation Mode BCMOD 0 FM changes its state for each FP signal Generalplus Technology Inc PAGE 123 V1 0 Dec 20 2006 G FM NE FP BE 9 po LP Linel Line2 mu LineN T 1 x Frame Interval For C type frame modulation mode BCDMOD 1 FM changes its state for each MAL 7 0 1 LP signal For example if MVAL 7 0 2 FM signals changes its state each three LP signals See the following diagram for reference If MVAL 7 0 1 equals the number of common the C type FM signal is the same as B type FM signal me C e CT MS LP Linel Line Line j Line4 LineN T 3 x Line Interval P LCD Palette Ctrl 0x7989 LCD Palette Control Register Bit 15 14 13 M2 11 10 9 8 7 615114131211 0 Function OVIF C C BPR BPP LCDBW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 OVIF G LCD DMA operations overflow Read 0 Not Occurs This bit is set to 1 by hardware if the Read 1 Happened LCD DMA operation overflow is Write 0 No effect asserted Write 1 Clear the flag pes Reserved 7 BPR R W Bypass Palette Register Setup 0 Not Bypass Pale
282. ange 0 15 Tw WEB3NUN 3 0 SYSCLK P MCSA4 WETimingCtrl 0x7828 MCS4 WE timing control register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function WEB4NUM Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition Reserved WEBANUM R W ICSB4 and WEB4 Program Timing Range 0 15 Register Tw WEB4NUM 3 0 SYSCLK Generalplus Technology Inc PAGE 34 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_MCS3_RDTimingCirl 0x7829 MCS3 RD timing control register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RDB3NUM Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function type Description Condition RDB3NUM R W CSB3 and RDB3 Program Timing Range 0 15 Tw RDB3NUN 3 0 SYSCLK P_MCS4_RDTimingCirl 0x782A MCS4 RD timing control register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RDB4NUM Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ES OO O a TW LPP Da mea Reserved 22 1 e 0 RDBANUM R W CSB4 and RDBA Program Timing 0 15 Register Tw RDBANUN 3 0 SYSCLK P MCS3 TimingCtrl 0x782B MCS3 CS timing control register Bit 15 14 13142 11 10 1 9 8 7 6 5 4 3 2 1 0 Function
283. ange these pins to GPIOs programmers must write certain word to a corresponding control register Generalplus Technology Inc PAGE 36 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P Mem Ctrl 0x7840 Memory Control Register Bit 15 14 13 12 11 10 918 7 6 5 4 3 2 1 0 Function IWE RD MCS4 MCS3 MCS2 MCS1 MCSO Default 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 KEE DA O p peee a nem _ Tnesebishavetobe setas o fo o n R W Memory Write Enable Signal WEB 0 Disable When write 0 to this bit PortB 3 becomes GPIO 1 Enable Otherwise PortB 3 remains Write Enable Signal Memory Read Enable Signal OEB 0 Disable When write 0 to this bit PortB 4 becomes GPIO 1 Enable Otherwise PortB 4 remains Read Enable Signal s Resne A lt j MCS4 is shared with IOD 4 1 Enable MCS3 is shared with IOD 3 1 Enable MCS2 is shared with IOD 2 1 Enable MCS1 is shared with IOD 1 1 Enable MK L ES MCS0 is shared with IOD 0 1 Enable P Addr Ctrl 0x7841 Memory Address A17 A25 Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function aM MA23 MA22 MA21 MA20 MA19 MA18 MA17 Default 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 von Ree MA23 is shared with HI 1 Enable Teee S MA22 is shared with YO
284. are available and it supports H W ECC Error Correction Code FEATURE Support ROM SRAM NOR type flash memory Five banks 5 chips select are available for the supported memories Each bank size is up to 256 pages and each page is 64K words the controller can totally support up to 80M words for NOR type flash memories e Supply the interface to access 8 bit or 16 bit NAND Flash memory e Support flexible Command Address mode Support Auto page Program Read e Support single Program Read by Firmware Provide DMA interrupt request e Support NAND hardware ECC Each memory can be configured as 8 bit mode access Memory Mappings GPL162002A 162003A has a built in 30K word SRAM and a 128K word internal ROM Associated with external memory devices GPL162002A 162003A is able to address up to 81920K word locations GPL162002A 162003A supports three boot modes Boot from internal ROM Boot from external ROM and boot EMU mode The memory mappings of these three modes are as follows 1 Internal ROM mode When BM 1 0 10 GPL162002A 162003A will boot from internal embedded ROM This mode is active at end product stage The memory mapping of the internal ROM mode is shown below Generalplus Technology Inc PAGE 24 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide BOOT FROM INTERNAL ROM RAM 30KW Peripheral System Control mbadded ROM 128KW 0x0000_00
285. at is BPP cannot be set to neither 011 nor 100 if LCDBW is equal to 1 Following diagram depicts the configuration that GPL162002A 162003A supports and not supports Bypass Palette Palette Valid Bypass Palette Palette Valid B W Mode B W Mode Color Mode Color Mode LCDBW 1 LCDBW 1 LCDBW lt 01 Ke E 1 bit per pixel 2 bit per pixel 4 bit per pixel 8 bit per pixel O Supported X Not supported Note that BPR control bit is used to determine whether to bypass palette or not ONLY when 1 bit per pixel mode is selected Note If LCDBW is cleared to 0 color mode is enabled Color mode can only support 4 bit and 8 bit data buses Simply if color mode is enabled LCDBW 0 BUSW cannot be 00 P LCD Attri Ctrl 0x798A LCD Attribute Control Register Bit 151141113112 M 10 91817 6 5 4 3 2 1 0 Function b hd VerINV HORINV DATAINV NEGFILE Default 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 Bit A Function Type Description Condition naal A Rea 3 VERINV R W Vertical Invert in LCD Display 0 Disable 1 Enable 1 Enable LCD Display Data Order Reversed D 7 0 gt D 0 7 1 Enable A O 0x55 gt OxAA 17 Enable 11 6 Operation during Wait Halt Standby amp Wakeup Procedure In wait mode the LCD is able to remain functioning even if CPU is turned off because GPL162002A 162003A keeps P
286. ble Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RST RME SUS IINNA IINPC BONA BOPS BINA BIPC EOSNA JEOSC EOINNA EOINPC EOONA EOOPS EOSPS Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Type Description Condition Rest Interrupt Enable 0 Disable If this bit is set to 1 and an interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU Af this bit is cleared to 0 this interrupt will be masked Resume Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked Suspend Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked Interrupt In NACK Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU Ifthis bit is cleared to 0 this interrupt will be masked Interrupt In Packet Clear Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked Bulk Out NACK Interrupt Enable If this bit is set to 1
287. bled 1 depth FEN 0 This bit is set to 1 when the receiving hold register is empty Note that this flag is read only hardware will set or clear this flag automatically When this bit is read as 1 theeUART or IrDA module is busy in transmitting This bit remains set until the complete byte including all the stop bits has been sent from the shift register Note at this flag is read only hardware will set or clear this flag automatically MA el nUARTDCD modem status input 12 nUARTDCD is 0 EA de Td nUARTDSR modem status input 1 nUARTDSR is 0 ld NN nUARTCTS modem status input 1 nUARTCTS is 0 The above three interrupt flag are combined into a single interrupt flag on P INT Status1 bit11 by an OR logic Programmers should determine which interrupt occurs from this control register P UARTIrDA Status bit 15 13 P UARTIrDA FIFO 0x7905 UART IrDA FIFO Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TX LEVEL TX FLAG RX LEVEL RX FLAG Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NENNEN Generalplus Technology Inc PAGE 163 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition 05 AA 14 12 TX LEVEL FIFO interrupt level register This register is used to indicate how many empt
288. buffer full 12 Enable interrupt his interrupt will be cleared after data had been read from the P SD DataTR CBULFU Command Buffer Full Interrupt Enable 0 Disable Writing 1 to this bit will enable the command buffer 1 Enable full interrupt This interrupt will be cleared when read from P_SD Resp register or start a new transaction or Set STPCMD in command register DCOM Data Complete Interrupt Enable 0 Disable Write 1 to this bit will enable the data complete 1 Enable interrupt Writing 1 to P SD Status 3 will clear this interrupt CCOM Command Complete Interrupt Enable 0 Disable Write 1 to this bit will enable the command complete 1 Enable interrupt Writing 1 to P SD Status 2 will clear this interrupt Generalplus Technology Inc PAGE 291 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 20 9 Example Program Read_SD Sector P_SD_ArgL r3 P_SD_ArgH r4 r2 0x1191 Send SDC Command17 Response R1 P_SD_CMD r2 J SDC Command Run SDC Command with data call Wait_CMD_Complete r1 Response receive command response r2 P SD Respl r1 r2 r2 P_SD_RespH r1 r2 r1 Store_High_Addr store High word r2 Store Low Addr I store Low word ds r1 r4 256 1 Read 256 words Read_Finish call Wait Data Full r32 P GD DataRx ds r2 r3 r4 1 jnz Read Finish call Wait Controller Busy call Wait Data Complete call
289. bulk out and interrupt in furthermore as a USB mini host basic transaction and function are supported There is only a FIFO implemented by 128X8 bits single port SRAM To enhance the speed of bulk transfers DMA function is supported and then FIFO seems to become dual FIFOs each one is 64 bytes In addition it is permissible that bulk in happens simultaneously with bulk out when DMA is disabled this situation however is not allowed when DMA is enabled Conforms to USB Version 1 1 specification e USB device controller is supported USB mini host controller is supported e Built in USB transceiver There are 4 endpoints when USB device is enabled m Control pipe for standard commande W Bulk IN for a large number of data transfers m Bulk OUT for a large number of data transfers B Interrupt in Tor data transfer seldom happens A8 byte DEE FIFO for a control pipe in USB device only e For USB device a 128x8bits single port SRAM is used only in Bulk IN and Bulk OUT and for USB host all types of transmission use this single port SRAM A2 byte DFF FIFO for Interrupt IN in USB device only Functionsyare supported when USB mini host is enabled W Setup command or data transaction B IN transaction OUT transaction B Programmable packet delay time or timeout latency W SOF timer frame number generator W Reset signal Interrupt mode or polling mode for driver Generalplus Technology Inc PAGE 179 V1 0 Dec 20 2006
290. by software but the addressing space ofthese five devices cannot be overlapped Besides if the system has to connect a NAND Flash it wil use one of these five chip select pins It is recommanded to use the system s last chip select pin See the following formula Size of External DeviceO External Device External Device2 External Device3 External Device4 lt 81920K words The method to define the address mapping of five external memory devices is to set up the size of each memory device In GPL162002A 162003A the start address of CSO is 0x0003 0000 After the size of CS0 is given the CS1 address is defined impliedly That is 0x0003 0000 size of CSO the unit is based on each 64K word or saying 0x010000 After the CS1 is settled the start address of CS2 is automatically defined similar for CS3 CS4 Example Suppose we have two 256K Word SRAMs for CSO and CS1 and A 512K Word Flash memory and a 512K Word ROM for CS2 and CS3 respectively Arrangement the following CS0 0x0003 0000 0x006 FFFF as 256KW SRAM CS1 0x0007 0000 0x000A FFFF as 256KW SRAM CS2 0x000B 0000 0x0013 FFFF as 512KW Flash CS3 0x0014 0000 0x001B FFFF as 512KW ROM In most cases not all five external device will be used nor all 24 address lines Therefore GPL 162002A 162003A allows system designers to convert unused CSO CS4 Address signal A17 A23 or even read write signal WE RE to general purpose I O Theses signals are memory con
291. can just modify P TFT DMASTART AH and b TFT DMASTART AL control registers P TFT PIXEL NUM 0x7D10 TFT Pixel Numbers in Each Line Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIXEL_NUM Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition _ msi JL Reseed po PIXEL_NUM The number of pixel in each line TFT line pixel Generalplus Technology Inc PAGE 142 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide The maximum horizontal pixel number on PIXEL_NUM 1 GPL162002A is 640 P_TFT_LINE NUM 0x7D11 TFT Line Numbers in Each Line Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LINE NUM Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition msi Reseed N LINE NUM R W The number of line in each frame TFT frame line The maximum vertical line number on LINE NUM 1 GPL12002A is 480 PIP Special Function Display Priority PIP3 gt PIP2 gt PIP1 gt PIPO gt Main P TFT PIPO CTRL 0
292. ccessRequesr Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RDY WRITE 3D ADDR Default 1 0 o 0 0 0 0 0 0 0 0 0 0 0 0 0 R W Access Ready Register 0 Not ready Any request must berissued when 1 Ready for read write parameter RDY is 1 When RDY is 0 all requests will be discarded WRITE RW Read or Write Access Register 0 Read parameter 1 Write parameter 13 10 ns O R W 3D or EQ AC Selection 0 Download EQ AC parameter 1 Download 3D E ADDR Parameter Download Address P_DAC_ACCDINL Ox7BF1 3D EQ AC Parameter Data Input Low Register Bit 15 21444713 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DATAIN 15 0 Default lt 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sit Function type Description Condition 15 0 DATAIN R W Programmers must fill a designated parameter in this register before writing to P DAC ACCREQ register P DAC ACCDINH Ox7BF2 3D EQ AC Parameter Data Input High Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DATAIN 23 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 104 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition Reserved DATAIN R W Programmers must fil a de
293. completed Write 1 to clear the interrupt PAGE 210 Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide SOF R W SOF Interrupt Read 0 Not occurred This interrupt is periodically generated for every Read 1 Occurred ims frame time Write 1 to clear the interrupt Write O No effect Write 1 Clear the flag DSC DP DM Status Change Interrupt Read 0 Not occurred This interrupt is used to detect the device Read 1 Occurred connection when the host controller is in the Write 0 No effect idle state Once the device is plug in this Write 1 Clear the flag interrupt must b
294. d to select the automatic pull enter HALT STANDBY mode high low function of data bus when entering 1 Pull high bus when enter HALT mode or STANDBY mode This bit is HALT STANDBY mode Generalplus Technology Inc PAGE 21 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Pagonywenpporso j 13 D_SR R W Slew Rate control of data bus 0 High slew rate of data bus This bit is used to control the slew rate of 1 Low slew rate of data bus 12 D SMT R W Schimit trigger of data bus 0 Turn off the Schimit trigger This bit is used to control the Schimit trigger of data bus of data bus 1 Turn on the Schimit trigger of data bus m Reseved R Resemed O 10 8 D DRIVE R W Driving Strength of data Bus 000 2 4 mA This register is used to control the driving 001 AmA capability of data bus 010 8 mA 011 8 mA 100 12 mA 101 12 mA 110 16 mA 111 16 mA rg Reseved R Reserved eD a j 5 A SR R W Slew Rate control of address bus 0 High slew rate of address This bit is used to control the slew rate of bus address bus 1 Low slew rate of address bus 4 A SMT RW Schimit trigger of address bus 0 Turn off the Schimit trigger This bit is used to control the Schimit trigger of address bus of address bus 1 Turn on the Schimit trigger of address bus pg Resewed R Reseved ooo j 2 0 A DRIVE R W_ Driving Strength of Add
295. data sampling time at he end or middle of clock period Programmable master SCK clock frequency System Clock 2 4 8 16 32 64 128 Built in 8 depth 8 bits FIFOs in both transmitting and receiving direction with programmable interrupt level 14 2 Structure Following je a function diagram of SPI module Clock Generation SCK GPL162002A Control Register SPITXD SPI Master TX Shift Control SDO Register CSN GPL162002A Control Register SPIRXD SDI RX Shift Register Generalplus Technology Inc PAGE 168 V1 0 Dec 20 2006 G 14 4 14 5 Generalplus GPL162002A 162003A Programming Guide 14 3 SPI Control Pin Configuration SPICK o Serial Peripheral Interface Clock Pin Shared with PortB11 SPICSN o Serial Peripheral Interface Chip Select Low Active Shared with PortB10 SPIDO e Serial Peripheral Interface Data Out Pin Shared with PortD4 SPIDI ME Serial Peripheral Interface Data In Pin Shared with PortD11 Master Mode In master mode the shifting clock SPICLK is generated by GPL162002A 162003A There are two control bits to control the clock phase and polarity The transmission starts immediately from writing SPIBUF control register As long as there is a data in the FIFO the transmision will start automatically The SPI shifts the data from MSB to LSB through the SDO pin The 8 bit data is shifted out after 8 SCK cycles At the
296. ddress Note that this bit will be valid only when DF is 0 DMA Double Buffer Full When DMA is active and programmers write the P_DMA_TCountL H again this bit will P DMA SRC AddrL H P DMA TAR AddrL H can be updated before writing ato P DMA TCountl H When the DMA action is completed it will automatically reload the be set to 1 The value of and current value in these three registers and perform the next DMA transfer DMA Normalinterrupt Mode This bit is used to set up the interrupt mode MODE R W DMA mode selection This bit is used to select DMA operation mode In Software mode DMA transfer will start automatically until P DMA TCount reaches 0 In External mode DMA controller will not initialize a DMA transfer until acquiring a DMA request from a peripheral pes CE R W Channel Enable 0 Channel is disabled 1 Channel is enabled PAGE 270 Generalplus Technology Inc Status of DMA Channel 1 Fix destination address 0 Increase address 1 Decrease address 0 Increase address 1 Decrease address 1 Occur 0 Not occur 0x07 DMA issue interrupt only when P DMA TCount reach 0 and DBF is 0 0x17 DMA issue interrupt every time when DMATCR reach 0 and don t care the DBF 0 2 Software mode 17 External mode 0 Idle 1 Bus V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_DMA SRC_AddrL0 0x7B81 DMA Source Low Address Regis
297. ddress is OxO I2C Bus Last Received Bit Status Flag 0 Last received bit is 0 ACK was received 12 Lastreceived bit is 1 ACK was not received P I2C Addr 0x7B62 I2C Address Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Addr Init 0 0 0 0 0 0 0 O 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 Reserved 7 1 Addr R W I2C Bus Address 7 1 Slave Address T bit slave address latched from the DC bus When data output enable bit 0 in the P_I2C Status 4 it is able to write P 2C Adar It is allowable to read this register at any time regardless of the current serial output enable bit P I2C Status 4 Lo lr nese s ll P I2C Data 0x7B63 DC Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 Reserved 7 0 Data R W 12C Data Register 8 bit data shift register for 12C bus TX RX operation Generalplus Technology Inc PAGE 259 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Type Description Condition When serial output enable 1 in the P I2C Status it is able to write this register It is allowable to read t
298. e Programmers should set a specific response type via 0x79D2 to inform CPU how long the controller will receive the response Following is the description of each kind of responses Response type 3 b000 R0 No response Response type 3 b001 R1 Normal 6 byte long response Response type 3 b010 R2 17 byte response type Response type 3 b011 R3 6 byte response with command index and 6 b111111 of CRC7sfield Response type 3 b111 R1b Normal 6 byte response with a busy signal on the DATO Controller keeps the clock running until the busy signal is cleared The value of these response types may not totally appear in the response control register For Response type R1 only 4 bytes of bit 39 8 card status can be read from response control register it has to read P SD RespL and P SD RespH for one time to get the 32 bit response For Response type R2 only 16 bytes of bit 127 0 CID or CSD can be read from response control register it has to read P SD RespL and P SD RespH for four times to get the 128 bit response For Response type R3 only 4 bytes of bit 39 8 OCR can be read from response control register it has to read P SD RespL and P SD RespH for one time do get the 32 bits response For Response type R6 only 4 bytes of bit 39 8 RCA and Card Status can be read from response control register it has to read P SD RespL and P SD RespH for one time to get the 32 bits response In order to receive all 16 bytes
299. e Value 0x014F External Depen RAM Select value S Reset A Size 2 D 64K Word Reset N E Mode System Cycle 15 Cancel Chip Select is the setting of downloading a program and resources onto four external memories CSO CS1 CS2 CS3 and CS4 on EMU board through ICE Programmers must set it up before downloading a program onto EMU board Note This setting is only a reference for downloading a program from ICE to EMU board Programmers must set Chip Select properly based on their needs 1 Memory Chip Select Select which chip to be set up 2 MemoryType Which type of memory is used e g RAM ROM Flash in download box check is disabled if this chip is not used IDE therefore will not download a program into these memory devices while re downloading The disable sequence must be CS4 CS3 CS2 CS1 then CSO can be disabled indivisually 3 Select value a Size setup size of the chip The starting address of the GPL162002 CS is determined by the previous memory size CSO is fixed in 0x30000 Therefore the starting address of next memory must be appointed The starting address of memory must be corresponding to the one given in the programming guide Generalplus Technology Inc PAGE 404 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Some memory limitation may be applied for example to configure CSO 256K word ROM CS1 gt 512K word flash CS2 gt 5
300. e Select Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DMA_SS3 DMA_SS2 DMA_SS1 DMA SSO Init 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 P DMA INT Ox7BBF DMA Interrupt Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CH3BY CH2BY CH1BY CHOBY CH3TOIF CH2TOIF CH1TOIF CHOTOIF CHSIF CH2IF CH1IF CHOIF Init 0000 0 0 0 0 0 0 0 0 0 0 0 0 SD MMC Register Summary Table Name Address Description P SD DataTX Ox79DO SD MMC Data Transmit Register P SD DataRX P SD CMD P SD ArgL P SD ArgH 0x79D4 ooa P_SD_Respl P_SD_RespH P SD Status P SD Cm P SD BLKLEN P SD INT P SD DataTX 0x79D0 SD MMC Data Transmit Register Bit 15 14 13 12 411 10 9 8 7 6 5 4 3 2 1 0 Function DataTX Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_SD_DataRX 0x79D1 SD MMC Data Receive Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DataRX Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_SD CMD 0x79D2 SD MMC Command Register Bit 15 14 13 12 11 10 9 8 7 6 514 3 2 1 0 Function RespType IniCard MulBIk TranData CmdWD RunCmd StpCmd CmdCode Default 0 0 0 0 0 0 0 0 0 0 000000 Generalplus Technology Inc PAGE 366 V1 0
301. e above table I O of I O PortC In addition the attribution port configuration and setup value can be read back from the function same control register P_IOD Data 0x7878 IOD Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IODDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 IODDATA R W Executing the writing operation in this register will Refer to the above latchsetup value into I O PortD data register table NO port Similarly executing the read operation in this configuration and register will read the status from I O PortD function external pads P IOD Buffer 0x7879 IOD Buffer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IODBUF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 IODBUF R W Executing the read operation in this register IODBUF R will read the setup value from I O PortD data IODDATA W register which is previously latched by IODBUF W IODDATA writing operation Generalplus Technology Inc PAGE 52 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_IOD_Dir 0x787A IOD Direction Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IODDIR 5 5 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condit
302. e bounce while obtaining touch panel x and y coordinate values The time interval between operating mode start and AD conversion start should not be too short It may take some time to wait that voltage level is stable RC effect because a parasitic capacitance may exist on touch panel The timing scheme for touch panel coordinate value acquisition is depicted in the following diagram ADBEN Input Signals tl ADC BIAS voltage setup time ADC initalization warm up time t2 X measurement switches and input select Setup time t3 X coordinate value aquisistion time ADC conversion time t4 Y measurement switches and input select setup time t5 Y coordinate value aquisistion time ADC conversion time Following are pseudo codes about touch panel coordinate value acquirement process Step 0 Touch panel is in interrupt mode Step 1 Touch panel tapped interrupt event occurs Step 2 Turn on ADC Step 3 Switch to operation mode measurement X Step 4 Delay for waiting signal stable Step 5 Start AD conversion Step 6 Poll AD conversion ready Step 7 Obtain X coordinate value by acquiring AD data Step 8 Switch to operation mode measurement Y Step 9 Delay for waiting signal stable Step 10 Start AD conversion Step 11 Poll AD conversion ready Step 12 Obtain Y coordinate value by acquiring AD data Generalplus Technology Inc PAGE 219 V1 0 Dec 20 2006 G Generalplus GPL162002A
303. e clock selection of each timer Generalplus Technology Inc PAGE 68 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide System Clock 2 0000 System Clock 256 0001 32768 Hz 0010 meme en d 4096 Hz 0100 Selection Prescaler 1 gt 0101 00 1 falling Next Timer Over Flow 110 EXTA PORT IOD12 01 1 rising 0111 10 1 4 risings Se 1000 11 1 1 A6 rising 8 Synchronization Clock Source N Circuit of Timer y gt with rising edge zd of CPU clock 2048 Hz gt gt 000 1024 Hz 001 256 Hz 010 TimeBase B Clock TimeBase A S da 100 Selection 0 101 1 110 111 EXTB Prescaler 00 1 falling cP 01 1 rising SI 10 1 4 risings 11 1 16 rising PORT 10D13 Each of these 16 bit timers counters has an up counter and increment on the rising edge of internal clock Source or increment either on the rising or falling edge of external Clock source Initial value of the up counter is stored in the pre load register preload register When the timer counter is enabled and overflow occurs the initial value is loaded into counter on the next increment clock edge synchronous load At the same time corresponding interrupt flag is set If corresponding interrupt is enabled it will issue an interrupt to CPU For example if the initial value is OXFFFC the timer counter will
304. e disabled Write 1 to clear the interrupt P_USBH_INTEN Ox7BOF USB Host Interrupt Enable Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 gt 1 0 Function DPO TRST TSOFI ITOK TXO VSC AOX AIX RX TX SOF DSC Default 0 0 O 0 0 0 0 0 0 0 0 0 0 0 0 0 IST A A IA EE 1 Enable 1 Enable 1 Enable 1 Enable 1 Enable ha E 1 Enable 1 Enable 1 Enable AA 1 Enable C ES 1 Enable 1 Enable Generalplus Technology Inc PAGE 211 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide DSC R W DP DM Status Change Interrupt Enable 0 Disable 1 Enable P_USBH_StorageRST 0x7B10 USB Storage Reset Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function StorageRST Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 StorageRST W Reset Bulk In Out Buffer Write any value to Write any value to this register will clear bulk in out reset bulk in out buffer We suggest programmer write this register buffer at starting data transmission with USB device P USBH SoftRST 0x7B11 USB Software Reset Register Device Plug Out Register Bit 15 14 13 12 11 10 F9 8 7 6 5 4 3 2 1 0 Function IDPOE DPOTV SRST
305. e error bit 0 error free 1 error 10 8 FAILBIT Generalplus Technology Inc PAGE 242 V1 0 Dec 20 2006 others m error on bit m G Generalplus Function GPL162002A 162003A Programming Guide Description Condition FAILLINE The error line position 255 error free others n error on line n The control register P_ECC_ERRO_LB stores the error information of 0 255 bytes of Nand Flash Moreover P_ECC_ERR1_LB stores the error information of 256 511 bytes of Nand Flash P_ECC_LPRL_HB 0x7848 ECC High Byte Line parity LSB Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LPRL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Condition Description 15 0 LPRL R The ECC Line parity register LSB P_ECC_LPRH_HB 0x7849 ECC High Byte Line parity MSB Register Bit 15 14 13 12 11 10 1 9 8 7 6 5 4 3 2 1 0 Function LPRH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 LPRH R The ECC Line parity register MSB P ECC CPR HB 0x784A ECC High Byte Column parity Register Bit 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Function v CPR Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function
306. e host will start to wait for data after the final bit of a command is sent This wait will be timeout after 150ms TIMEOUT bit will be set in such a condition If the card transmits the data and CRC16 correctly the transaction completes smoothly or else the P_SD_Status bit10 Data CRC Error will be set 20 5 Card Insertion Detection When both the CMD and DAT State machine are idle and DAT3 on the bus is pulled high the P SD Status bit12 Card Present will be set Otherwise if the DAT3 is pulled low the P SD Status bit12 Card Present bit will be cleared A de bounce circuit is used here to prevent the noise on the bus 20 6 Multi Block Read Write The multi block read write mode is enabled by setting P SD CMD bit10 Multi Block Transfer to 1 In this mode host can read write multi block in one command The read write method is the same as single block mode The only difference is that the host needs to stop controller manually by setting STPCMD to 1 when all data are received transmitted Host also should initiate CMD12 on the bus to stop the card 20 7 SD MMC Control Pin Configuration Name yo Description SDCMD SDData0 Command Response transfer on this pin Shared with PortC5 1 0 soc lo L Pin Shared with reg Generalplus Technology Inc PAGE 284 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 20 8 Control Register SD MMC Register Summary Table
307. e is any 1 Receive FIFO is not empty data currently in the receive FIFO Transmit FIFO Not Full Flag 0 Transmit FIFO is full you This bit is Used to indicate if there is any can t write any more data into it empty slot in the transmitting FIFO 1 Transmit FIFO is not full Transmit FIFO Empty Flag 0 Transmit FIFO is not empty This bit is used to indicate if the 1 Transmit FIFO is empty transmitting FIFO is empty or not L Generalplus Technology Inc PAGE 177 V1 0 Dec 20 2006 G Generalplus 14 8 Program Examples GPL162002A 162003A Programming Guide SPI self loop test the SPIDI SPIDO need be connected F SPISelfLoopTest Int off r1 0xa100 P_SPI_Ctrl r1 r1 0x0050 P_SPI_TXData r1 RX_Ready r2 P_SPI_RXStatus test r2 0x01 jz RX_Ready r2 P SPI RXData cmp r1 r2 jne L Error DisplayResultCode retf L Error DisplayResultCode retf Enable SPI Master mode self loop test Iphase 0 polarity O H Output 0x50 to SPI D OK D NG Note that DisplayResultCode is MACRO Generalplus Technology Inc PAGE 178 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 15 USB Interface 15 1 Introduction The built in USB controller in GPL 162002A 162003A can be configured either as a USB device controller or USB mini host controller AS a USB device there are 4 endpoints control pipe bulk in
308. e key scan controller supports pull up circuit or pull down circuit for external keypads Automatically Detect Key Press Mode The key scan controller can detect if any key is pressed in a scan Manual Start a Key Scan When users wish to initiate a key scan manually writing 1 to this bit will generate But if the controller is busy when users write 1 to this the be Programmers sure a key scan procedure register request will ignored the controller is not busy before writing 1 to must make this register Key Scan Controller Busy Status This bit indicates if the key scan controller is idle or busy Force to Stop the Key Scan Controller When key scan contrller works incorrectly programmers can write 1 to this bit to force the key scan controller to stop This will make the key scan controller back to idle state Bit 7 4 OFF When this bit is set to 1 IOA7 IOA4 are used as GPIOs and setting the control registers P KS Data7 P KS Data4 is invalid PAGE 299 0 Use LCD blank time as sample time 1 Use fixed sampling time set in STIME as sampling time 0z pull down circuit with The scan External keypads output is high active 1 With pull up circuit The scan output External keypads is low active O Interrupt is asserted each time when keyscan is complete 1 Interrupt is asserted each time when keyscan is complete and a key is pressed Write 0 No effect Write 1
309. e maximum virtual page is 1024 pixels To move the actual display area horizontally or vertically programmers should modify P LCD Buffer HighAdr and P LCD Buffer LowAdr control registers NENNEN Generalplus Technology Inc PAGE 122 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P LCD Timing Ctrl 0x7987 LCD Control Signal Timing Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LBVL LPW LPCPD Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition sag JL Reseed 11 8 LBVL R W Line Blank Width T LBVL 1 x CLCPCLK Please refer to following timing diagram Range 0 15 Please refer to following timing diagram Range 0 15 Please refer to following timing diagram Range 0 15 Note Generally this register does not need to be changed The purpose of this register is to adjust the LCD control signals for special LCD drivers CLCPCLK LCDCLK 9 0 2 Width LP L Line Blank LPloCP Delay P LCD Frame Ctrl 0x7988 LCD Frame Modulation Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BCMOD MVAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p aas ere BCMOD RAW LCD Frame Modulation Type 0 B type Typic
310. e used as the Request of setup commands P USBD EPOVR 0x7B48 USB Endpoint0 wValue Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EPOVR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 EPOVR EPO wValue These bits are used as the Value of setup commands PAGE 200 Description V1 0 Dec 20 2006 Generalplus Technology Inc G Generalplus GPL162002A 162003A Programming Guide P USBD EPOIR 0x7B49 USB windex Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EPOIR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 EPOIR EPO windex These bits are used as the windex of setup commands P USBD EPOLR 0x7B4A USB Endpoint0 wLength Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EPOLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description L condition 15 0 EPOLR EPO wLength These bits are used as the wLength of setup commands P USBD DMAWrtCountL 0x7B50 USB DMA Byte Count Low Register Bit 15 14 13 12 114 10 9 8 7 6 5 4 3 2 1 0 Function DM
311. e valid in calculating ECC and only 0x7830 0x7831 are valid in calculating checksum When the NAND flash connected to GPL162002A 162003A is 16 bit type all the ECC and checksum registers are valid In checksum function GPL162002A 162003A does not support the compare function but it does have that in ECC function NENNEN Generalplus Technology Inc PAGE 239 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 7858 Line Parity LSB ield 0 One Error ield 0 Two Error 7857 ECC RST Low Byte 7859 Line Parity MSB EE i ECC NEDataln 7 0 785E Field O Error Bit Position 785A Column Parity 785E Field O Error Line position Compare 785B Line Parity LSB 9785F Field 1 One Error gt ield 1 Two Error Low Byte 785C Line Parity MSB gt ield 1 Error Bit Position Check Reg gt 785D Column Parity 785F Field 1 Error Line Position 7857 Check Once 7848 Line Parity LSB 784E Field 0 One Error L 7857 ECC RST 784E Field 0 Lwo Error High Byte 7849 Line Parity MSB ECC d NFDataIn 15 8 d 0 Error Bit Position 784A Column Parity VD Error Line Position Compare AF Fi ror 74B Line Parity LSB 784F Field 1 One Error a 784F Field 1 Two Error gt High Byte 784C Line FE MSB 784F Field 1 Error Bit Position
312. eal image raw data re Generalplus Technology Inc PAGE 127 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide kk e ee ee k ee kok k kok kok kok he kok kok he kok kok e hehe ee je e kok kok e hehe ee k ehe ee hehe e hehe ee je ehe ee he ee KKK ehe ee k kk kk k ehe kk kk k kk kk k kk kk k kk kk kk kkk k High Color 24 bit BMP File to lt 12 Bit Per Pixel Format of LCD Buffer gt 4096 Color ee KK e ee ee KKK kok e e e kok ee he ee kok he ee hehe e hehe ee je he e e e hehe e hehe ee e ehe ee hehe e hehe ee k ee e e he ee hehe ee k ehe ee he ee hehe k kk ehe ee k ee kk k kk kk k kk kk kk kkk k Conversion Batch File po4color e 1 bmp 1 bin o b 4 tO swapword 1 bin 1 raw o b4 Note The first word of raw represents the number of picture width and second word of raw represents the number of picture height 11 8 Program Examples The image raw data starts from third word 160 Segment x 160 Common 256 color 4 bit interface LCD buffer start address 0x004 0000 DEFINE DEFINE F Fill256CPalette SEGMENT COMMON 160 160 r1 48000000 SEGMENT COMMON 180 2 IP LCD Clock 7 r1 ri 4 P LCD Buffer HighAdr 7 r1 ri 0 PL LCD Buffer LowAdr r1 Pa LCD Butter Offset r1 P LCD Timing Ctrl r1 P LCD Frame Ctrl r1 r1 SEGMENT 1 P LCD Segment r1 r1 COMMON 1 P LCD Common r1 r1 0x0006 II 8 bit per pixel 256 Color
313. eared to 0 this interrupt will be masked Generalplus suggests programmers do not use TimbaseA as halt sleep mode wake up source because the TimebaseA interrupt occurs more quickly than the time CPU wakes up from halt sleep mode As a result the TimebaseA interrupt flag will not be held from halt sleep wake up TMBAEN TimeBaseA Module Enable 07 Disabled If this bit is set to 1 TimeBaseA module 1 Enabled will be enabled on the contrary it will be disabled for power consumption consideration maj Resemes K a IV 1 0 TMBAS R W TimebaseA frequency selection 00 reserved There are three frequency sources on 01 1Hz TimebaseA 1Hz 2HzZ and 4Hz These 10 2Hz two control bits are to select one of three 112 4Hz frequencies P TimeBaseB Ctrl 0x78B1 TimeBaseB Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 11 0 Function TMBBIF C TMBBIE TMBBEN TMBBS Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 TMBBIF C R W TimebaseB interrupt Flag Read 0 Not Occurred Write 1 to clear the flag Read 1 Occurred If TimebaseB interrupt occurs this flag is set Write 0 No Effect to 1 by hardware Write 1 Clear the flag TMBBIE TimebaseB Interrupt enable 0 Disabled If this bit is set to 1 and TimeBaseB 1 Enabled interrupt
314. ection 00 PWM mode NRO output These 2 bits are valid only when 01 PWM mode NRZ output CCPXEN is set to 11 in binary 10 reserved Generalplus Technology Inc PAGE 76 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Conaition S l O i mes P_TimerA_Preload 0x78C2 TimerA Preload Register Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 Function TMAPLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerB_Preload 0x78CA TimerB Preload Register Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 Function TMBPLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerC_Preload 0x78D2 TimerC Preload Register Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 Function TMCPLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerD_Preload 0x78DA TimerD Preload Register Bit 15 14 13 12 11 40 8 U D 5 4 3 2 1 Function TMDPLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerE_Preload 0x79C2 TimerE Preload Register Bit 154 14 13 12 11 10 8 7 6 5 4 3 2 1 Function TMEPLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerF_Preload 0x79CA TimerF Preload Register Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 Function TMFPLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0
315. ecu cronaca nae ca uec a ses ERR nOD R ERROR RR RR Sam Ra sand RNRE Rara RR RR RR anses 235 17 1 Jurte e le e a u O 235 17 2 NAND Flash Control Pin Configuration rennen tete 235 17 3 Control Register O eee gf 235 17 4 NAND Flash ECC amp Checksum m Ne eee Nf eene 239 17 5 Special Note M MEE EO We am 246 17 6 Program Example B NN ees 247 18 I2C CONTROLLER GEET ususqa d MN E 249 18 1 Introductions treated en h TEE 249 18 2 I2G Bus ase RER QE rr lA RP re 249 18 2 1 Start Stop Generation ANNE coe asees eser seer eenn rr 249 18 2 2 Data Transfer Format a MW Meee ee cece nnne nennen 250 18 2 3 Acknowledgement Signal Transmission 1 251 18 2 4 Read Write Operation 252 18 2 5 Bus ArptsaNon Produr LA y iii 252 18 2 6 Bus Arbitration Produres sin 252 18 3 Ui ouis A AR VOR DNS NS 253 18 1 AO E gt y EEN 253 18 3 2 Masi it ceive Mode ii iiuiiuiisissilseitusneseuanrtenius 254 18 3 3 Z Glave Fransmit Mode ie 255 18 3 4 Ave RECEIVE MOde EE 256 18 4 I2C Bus Control Pin Configuration 257 18 5 I2C Bus eege Re E sxc ceased Die 257 18 6 Example esl s eere Re eter ote tarta AE MER Rue tra REN use ERE errada cias 261 19 DMA AND BRIDGE CONTROLLER 2 0 niece necatur ue side
316. ee k ee kok e e e kok ee he ee je je e ee hehe ehe he Kok kok e e e hehe e hehe ee he ehe e e hehe e hehe ee e ehe e e he ee hehe ee k ehe ee he ee hehe k ee kk ee k ee kk e kk k kk ee kk kkk k 256 Color BMP Files to lt 4 Bit Per Pixel Format of LCD Buffer gt 16 Gray ke hee he hee hee k KK KK k kok kok ee K he ehe e he ee kok k ehe ehe ok he e ee he he e he hee he kok kok KK e kok kok e dee ee e ee ee ehe e ehe ehe e ehe kok k ehe hehe hehe he hehe KK he hehe kok e hehe dece dece RER Conversion Batch File po4color b 1 bmp 1 bin o b 4 x swapword 961 bin 1 raw o b4 Note The first word of raw represents the number of picture width and the second word of raw means the number of picture height The image raw data starts from third word RER RE e dee kok k fee kok e e e kok ee he ee je je he ee hehe e hehe ee je je he ee hehe e hehe ee k ehe ee hehe e hehe ee k ehe e e he ee hehe ee k ehe ee he ee hehe k ehe kk ee k ee kk k kk kk k kk kk kk kkk k 256 Color BMP File to lt 8 Bit Per Pixel Format of LCD Buffer gt 256 Color KKK e dee ee eee e je e e de kok ee he ee e e e ee ehe e hehe ee e e he e e hehe e hehe ee e ee e e ehe e ehe ee e ehe e e he ee hehe ee je ehe e e he ee de hee ee ehe e e he ee eee ee kk e dee ee kkk kkk Conversion Batch File bmp2gim bmp GIM Note The first eight words of gim are reserved for header signature The following 256 words are the information for LCD Palette and the rest of data are the r
317. eeds 48MHz clock When system clock is setting to 96MHz this bit must be set to 1 2 0 CLKDIV needs to write this bit foi Clock Divide Selection The clock divider operates under any kinds of configurations t will divide the clock source selected by users and then output quotient as system clock So the slowest clock in GPL162002 is 32768 128 256Hz Generalplus Technology Inc PAGE 16 IOB0 output 32768 Hz 17 IOBO behaves as GPIO or other Special function IOBO 2 key change function interrupt disable 1 IOBO 2 key change function interrupt enable 0 Disable DA AD PLL 1 Enable DA AD PLL 0 Current clock is not 96MHz 1 Current clock is 96MHz 0007 SYSCLK Clock Source 0012 SYSCLK Clock Source 2 0102 SYSCLK Clock Source 4 0112 SYSCLK Clock Source 8 1002 SYSCLK Clock Source 16 1012 SYSCLK Clock Source 32 110 SYSCLK Clock Source 64 111 SYSCLK Clock Source 128 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide The clock of each module can be turned on off individually This is done by writing the corresponding bits of the P_CLK_Ctri0 and P CLK Ctrl1 If programmers write 1 to the corresponding bit of P_CLK_Ctrl0 and P_CLK_Ctrl1 the clock of the corresponding device will be turned on If programmers write 0 to the corresponding bit of P CLK Cl and P CLK Ctrl1 the clock of the corresponding device will be turned off Some i
318. egister 2 P DMA TAR Addi 2 DMA Target Low Address 15 0 Register 2 P DMA TCountL2 DMA Terminal Counter Low 15 0 Register 2 P DMA SRC AddrH2 DMA Source High Address 25 16 Register 2 P DMA TAR AddrH2 DMA Target High Address 25 16 Register 2 P DMA TCountH2 DMA Terminal Counter High 25 16 Register 2 P DMA MISC2 0x7B97 DMA miscellaneous Control Register 2 P DMA Ctrl3 0x7B98 DMA Channel Control Register 3 P DMA SRC Addrt 3 DMA Source Low Address 15 0 Register 3 P DMA TAR Addi 3 DMA Target Low Address 15 0 Register 3 P DMA TCountL3 DMA Terminal Counter Low 15 0 Register 3 P DMA SRC AddrH3 DMA Source High Address 25 16 Register 3 P DMA TAR AddrH3 DMA Target High Address 25 16 Register 3 P DMA TCountH3 DMA Terminal Counter High 25 16 Register 3 P DMA MISC3 Ox7B9F DMA miscellaneous Control Register 3 P DMA SPRISIZEO Ox7BBO DMA Sprite Size 9 0 Register 0 P DMA SPRISIZE1 Ox7BB1 DMA Sprite Size 9 0 Register 1 P DMA SPRISIZE2 DMA Sprite Size 9 0 Register 2 P DMA SPRISIZE3 DMA Sprite Size 9 0 Register 3 P DMA TRANSPATO DMA Transparent Pattern Register 0 P_DMA_TRANSPAT1 DMA Transparent Pattern Register 1 P_DMA_TRANSPAT2 DMA Transparent Pattern Register 2 P_DMA_TRANSPAT3 DMA Transparent Pattern Register 3 P_DMA_LINELENGTH DMA Line Length Control Register P_DMA_SS 0x7BBE DMA Soruce Select Register P_DMA_INT Ox7BBF DMA Interrupt Status Register P DMA Ctr
319. eneration Programmable clock speed in master mode Input de bounce circuit 18 2 12C Bus Protocol 18 2 1 Start Stop Generation A Start condition means transfering a one byte serial data over the SDA line and a Stop condition means terminating the data transfer A Start condition is a high to low transition of the SDA line while SCL is high A Stop condition is a low to high transition of the SDA line while SCL is high Start and Stop conditions are always generated by the master The I2C bus is busy when a Start condition is generated A few clocks after a Stop condition the I2C bus will be free again Generalplus Technology Inc PAGE 249 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide SDA SDA SCL SCL Start Stop Condition Condition When a master initiates a Start condition it should send a slave address to notify the slave device The one byte of address field consists of a 7 bit address and a 1 bit transfer direction indicator that is to write or to read If 8 bit is O it indicates a write operation transmitting operation if 8 bit is 1 it indicates a request for reading data receiving operation The master will finish a transfer operation by transmitting a Stop condition If the master wants to continue the data transmission to the bus it should generate another Start condition as well as a slave address In this way the read write operation can be pe
320. enne ener enne 167 14 SERIAL PERIPHERAL INTERFACE YSPIl 5 X Lees U uuu uu uuu uu uu u 168 14 1 Introduction NN A e 168 14 2 SU OUR nnn EN LT Nr 168 14 3 SPI Control Pin Confouraton sise 169 14 4 AS A SORT D Y EE 169 14 5 i S APO dn EE 169 14 6 CONSECULING lt u CR Transfer cindecs inscrita cajita rre es lacada etica qapas awas as s 172 14 7 Contes E 172 14 8 Nuslie lgl u at una umasha dew fn te t 178 15 CAT ee 179 15 1 ie e Sere EE 179 15 2 IS nett ttttttttttt tast AntE ASEA AAE EAN EENE EASEESSEESEEEEEEEEEEE EENE EA AEEA EEn Ene naene 180 15 3 USB MiNi 2 iii Stage Ie 180 15 4 Serial Interface Control Pin Configuration si 180 15 5 Control R60ISerSu a z u u ul 180 15 6 USB Device Register Definition 182 15 7 USB Host Register DeflnitiOn coacto neue da ie er ud eae coe aaa asua a eroe tne tun ein nn 203 16 ANALOG INPUT TOUCH PANEL VOICE RECORDER u uuu uu u u 214 Generalplus Technology Inc PAGE 5 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 16 1 Ji e Tes 214 16 2 SAR ADC A R 214 16 3 Touch Mu E 215 16 4 Voice Recorder HQADC operates mode 220 16 5 Analog Input Control Pin Configuration sis 221 16 6 Grenier Mm 222 16 7 Program Example u uD S La aan siat erit erret E in etes deteste 232 17 NAND FLASH INTERFACE U n
321. equencies are 100 150 400 1 EQ Generalplus also provides some EQ designated value for reference K 3K 7K and 15K Programmers can define music style by themselves through setting this 7 band Please refer to the following descriptions for details GPL162002A 162003A also has a built in 3D surround effector to increase sound stero quality It is easy to set up the 3D effector in GPL162002A 162003A by just configuring 5 corresponding control registers 10 5 IIS Mode GPL 162002A 162003A supports IIS interface of 4 physical signal lines to connect other DAC devices B BCLK bit clock output shared with IOC14 W LRCK left right select output shared with IOC13 W DA data output shared with IOC12 H MCLK main clock share wtih 10C15 General plus Technology Inc PAGE 94 V1 0 Dec 20 2006 A Generalplus GPL162002A 162003A Programming Guide There are three types of IIS transmission format on GPL162002A 162003A These transmission The formats are selected by given designated value to P DAC IIS Mode 0x78FF b 3 2 register details of setting transmission modes and timing diagram are as below Right Channel Left Channel 24 bit default a Right justified mode Right Channel Left Channel IT IS SS OS SS a IS II RQ ag SSNNN SS S SS RQ aq RQ qa SS TMK XXE IS IS BCLK LRCK IS
322. er 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SRO Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA SRC AddrL1 0x7B89 DMA Source Low Address Register 1 Bit 15 14 13 12 114 10 9 8 7 6 5 4 3 2 1 0 Function SRC_Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_SRC_AddrL2 0x7B91 DMA Source Low Address Register 2 Bit 154 14 134 1224 41 10 9 8 7 6 5 4 3 2 1 0 Function SRC_Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_SRC_AddrL3 0x7B99 DMA Source Low Address Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SRC_Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA TAR AddrLO 0x7B82 DMA Target Low Address Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NENNEN Generalplus Technology Inc PAGE 361 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_DMA_TAR_AddrL1 0x7B8A DMA Target Low Address Register 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR_Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_TAR_AddrL2 0x7B92 DMA Target Low Address Register 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR_Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_TAR_AddrL3 0x7B9A DMA Target Low Address Register 3 B
323. er circuit is required The bandwidth of the audio driver circuit can affect the perceived audio performance User can adjust the bandwidth according to the reference table below R is the effective resistance of the circuit and C is the effective capacitance Please refer to GPL162002A 162003A application circuit Faag 3dB frequency o vs az oan an oss iz ane nz non oss our el ru The frequency range 5K 4 KHz is for speech application and marked in yellow cells The frequency range 15K 25K Hz is for Audio application and marked in blue cells Generalplus Technology Inc PAGE 394 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 25 8 25 9 32768 Crystal and PLL Power on Stable Time When in power on GPL162002A 162003A will operate in 12MHz system clock And it takes 2048 cycle of 32768Hz crystal to make slow PLL clock stable After the bit Fast PLL Enable in P Clock Ctrl is set to 1 the system clock will change to 48MHz And it takes 2048 cycle of 12MHz crystal to make fast PLL clock stable Reset Type CPU reset When watchdog timeout reset watchdog mode protect reset or power saving mode protect reset occurs it just resets CPU The peripherals are not affected by the above reset mechanism and keep in its original state The corresponding reset flag can be read out to judge which reset happens System reset When Power on reset Low Vol
324. er data to minute register or shut down the system clock RTC Hour Controller Busy Flag When this bit is 1 it means the RTC is busy on writing hour to the register Programmers must wait until this bit is 0 in order to write further data to hour register or shut down the system clock Reserved Generalplus Technology Inc PAGE 90 V1 0 Dec 20 2006 G Generalplus 9 4 Program Examples _RESET secondwait r1 P_RTC_Busy test r1 0x8000 jnz secondwait r1 59 P_Second r1 minutewait hourwait r1 P_RTC_Busy test r1 0x4000 jnz minutewait r1 59 P_Minute r1 r1 P_RTC_Busy test r1 0x2000 jnz hourwait r1 7 P_Hour r1 r1 0 P_Alarm Second r1 P Alarm Minute r1 ri 8 P_Alarm_Hour r1 r1 0x0400 P RTC INT Ctrl r1 r1 0x8700 P_RTC_Ctrl r1 int irq jmp l je ee e e e ee kok k kok kok ke dee ee eee kek kk k kk k _IRQ7 push r1 r2 to sp r2 P_INT_Status2 ri r2 amp C_INT Alarm jz L_End_Alarm_ISR ri P_RTC_INT_Status GPL162002A 162003A Programming Guide J Setup Current Clock as 07 59 59 H M S II After writing new value to P Second it must wait RTC second idle state to make sure the new value write valid II After writing new value to P Minute it must wait RTC minute idle state to make sure the new value is written valid After writing new value to P Hour it must wait RTC ho
325. er should generate the clock pulse required to transmit the ACK bit The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received T hereceiver should also drive the SDA line Low during the ACK clock pulse so that the SDA is Low during the High period of the 9 SCL pulse The ACK bit transmit function can be enabled or disabled by software P_I2C_Ctrl However the ACK pulse on the 9 clock of SCL is required to complete a one byte data transfer operation Clock to Output I K Ia K d 1 1 EE can GE Cmm EE Data Output by Transmitter Data Output by 1 D T 1 1 1 1 1 H 1 1 1 Receiver Ny Master ar Goer ae Le Master s ce bemoaned I I Start Condition i f I 1 Clock Pulse for Acknowledgment Generalplus Technology Inc PAGE 251 V1 0 Dec 20 2006 G 18 2 5 18 2 6 Generalplus GPL162002A 162003A Programming Guide 18 2 4 Read Write Operation In the transmitter mode after the data is transferred the I2C bus interface will wait and the SCL line will be low until pending interrupt is cleared After the interrupt is cleared the SCL line will be released After the CPU receives the interrupt request it should write a new data into P DC Data before clearing the pending interrupt In the receiving mode after a data is received the I2C bus interface will wait and the SCL line will be low until pending
326. erflow r1 P TimerC Ctrl jp L_CheckTimerCOverflow P TimerC Ctrl r1 r1 IP IOC Buffer r1 r1 xor0x0001 P_IOC Data ri jmp L CheckTimerCOverflow l kc eee de e K Rk K K kok kk e kk kk kk k kk kk k kk kk L TimerAPWMPolling r1 0x1000 ID TimerA CCP Reg r1 r1 0x0000 IP TimerA Preload r1 r1 0xC000 TimerA CCP Ctrl 7 r1 r1 0xA060 IP TimerA Ctrl r1 jmp 48000000 Setup IOCO as output buffer low Setup TimerC preload value Iso that up counter overflow frequency 8000Hz Enable TimerC Clear TimerC up counter overflow interrupt flag Read Previous PortC Setup Toggle PortCO for 50 duty square wave ll and frequency is 4000 Hz 8000 2 NOBO will output a square wave with 1 16 duty icycle and frequency is CPUCLK 2 65536 Generalplus Technology Inc PAGE 79 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 8 Timebase 8 1 Introduction A timebsae generated from 32768Hz source is a combination of frequency selections GPL162002A 162003A supports three timebases accompanied with their interrupt mechanism these facilitate timing control for most of projects In additions a timebase also provides variety of frequency selections to clock source of Timer These three timebases are e 1Hz 2Hz 4Hz frequency programmable for TimebaseA e 8Hz 16Hz 32Hz 64Hz frequency programmable for TimebaseB e 128Hz 256Hz 512Hz
327. es in FIFO 0011 3 bytes in FIFO 0100 4 bytes in FIFO 0101 5 bytes in FIFO 0110 6 bytes in FIFO 0111 7 bytes in FIFO P_SPI_TXData 0x7942 SPI Transmit FIFO Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SPIDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition pss Reseed 7 0 SPITXDATA Write data to SPI Transmit FIFO Generalplus Technology Inc PAGE 174 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_SPI_RXStatus 0x7943 SPI Transmit Status Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SPITXIF SPITXIEN RXFULL RXFOV TXFLEV TXFFLAG Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 SPIRXIF R W SPI Transmit Interrupt flag This bit is set to 1 by hardware when the receiving FIFO level is higher then the value set by users When SMART is set in P_SPI_Misc register the bit will be cleared as long as the receiving FIFO level is lower than interrupt level else users should write 1 to clear this flag SPIRXIEN R W SPI Receive Interrupt Enable If this bit is set to 1 and SPI interrupt when 8 bit RX FIFO level in higher then interrupt level occurs hardware will iss
328. except the first byte response via the response register a host needs to poll the CMDBUFFULL register and read 4 bytes one by one There are two 32 bit buffers P SD RespL and P SD Reen to facilitate receiving responses The CMDBUFFULL will be set when one of two buffers is full If both of them are full the controller will stop the clock then wait until the host read the response register Responses will time out after 64 clocks cycle when the host transfer the last bit of a command If the card do not response in this period TIMEOUT bit will be set Data Line Control If a command will have data transferred on the data line the host needs to set the P SD CMD bit8 to 1 and set P SD CMD bit9 to indicate the data direction The BLKLEN is also necessary for the controller to determine how many bytes need to be transferred Another thing need to note is setting the data length The data length can be given by byte but it is necessary to align data length in word to prevent data from losing Generalplus Technology Inc PAGE 283 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide In transmitting mode the host will start to transmit extra 2 clocks after the final bit of the response After all bits and CRC16 are transmitted the host will wait for 2 clocks and start to receive the CRC status from the card If the CRC status indicates the CRC fails DATCRCERR bit will be set In receiving mode th
329. f data that host receives is stored in these bits P_USBH_FIFOInPointer 0x7B08 USB Host FIFO Input Pointer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function 2 HFIP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 206 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition pss Reserved prop ere Rw Host FiFo input Pointer P USBH FIFOOutPointer 0x7B09 USB Host FIFO Output Pointer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function HFOP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Ganda ro HFoP RW Joes FIFO Output Pointer ele P USBH AutolnByteCount 0x7B0A USB Host Automatic In Transaction Byte Count Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function HAIBC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Inge Description Condition _ 15 0 HAIBC R W Host Automatic IN Transaction Byte Count When using DMA in USB Write the number of IN transaction that is to be host the transmitting initated in these bits For example if the hostis receiving data must be going Io receive 512 bytes from the device it mult
330. fer The DMA channel will begin the next DMA transfer immediately after current DMA transfer is completed This is very useful in playing music and recording voice But if programmers write new address count when there is already a queue in the DMA channel the old one will be overwritten so cares must be taken to ensure the DBF bit in P DMA Ctrlis O when writing the new address count The sequence of writing a new address count is P DMA SRC AddrL gt P_DMA_SRC_AddrH gt P_DMA_TAR_AddrL gt P_DMA_TAR_AddrH gt P_DMA_TCountL gt P_DMA_TCountH Programmers must write P_DMA_TCountL P_DMA_TCountH at the end of the updating sequence The P_DMA Ctrl does not need to be updated since only the DMA transfer with the same configuration can use the double buffer mode L Generalplus Technology Inc PAGE 265 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 19 5 Byte Mode Operation When SRCBYTE in P_DMA_Ctrl is set to 1 the DMA channel will treat the data read from a source in byte If SF in P DMA Ctrl is O the P DMA SRC Addr will increase decrease after every two readings from a source When TARBYTE in P DMA Ctrl is set to 1 the DMA channel will write data to a peripheral in byte If DF in P DMA Ctrl is 0 the P_LDMA_SRC_Addr will increase decrease after every two writings to destination If WRITEREQ in P DMA Ctrl is 0 this means that the request from a peripheral needs to be read so
331. full flag 0 FIFO is not full This flag is set to 1 by hardware if the 1 FIFO is full FIFO is full If the flag is 1 any data written via P CHA Data is invalid 14 FFUNRN CHA FIFO under run flag 07 FIFO is not under running This flag is set to 1 by hardware if the 12 FIFO is under running FIFO is under running If the flag is 1 the output of DAC is keep last output value Pone roe pe per FIFO Reset Write O No effect Write 1 FIFO reset S nad CHAFEILV R W CHA FIFO Empty Interrupt Level FIFO Empty Interrupt issue timing These control bits are used to set FIFO 00007 Reserved empty interrupt timing that is enabled 0001 2 when of data in FIFO lt 1 on FEMIEN of P CHA Ctrl register It 00102 when of data in FIFO lt 2 defines the number of data left in FIFO 00112 when of data in FIFO lt 3 to be considered as empty by hardware The larger the value is the higher frequency of FIFO empty interrupt occurs The smaller the value 1110 2 when of data in FIFO lt 14 is the less frequency of the FIFO 11112 when of data in FIFO 15 empty interrupt happens Consequently it saves the CPU bandwidth 3 0 CHAFINX CHA FIFO used Default 0000 0000 0 data is in FIFO FIFO is a 16X16 bit ring buffer 0001 2 1 data is in FIFO 0010 2 data is in FIFO 11107 14 data is in FIFO 1111 2 15 data is in FIFO NENNEN Generalplus Technology Inc PAGE 98 V1 0 Dec 20
332. g interrupt will be masked To select between IRQ3 and FIQ please refer to Chapter Interrupt 13 RTIE R W Receive Timeout Interrupt Enable 07 Disabled If this bit is set to 1 and when the receiving 1 Enabled FIFO is not empty and no further data is Generalplus Technology Inc PAGE 158 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide received over a 32 bit period hardware will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this receiving interrupt will be masked To select between IRQ3 and FIQ please refer to Chapter Interrupt 12 UEN R W UART Enable 0 Disabled If this bit is set to 1 the UART Interface is 1 Enabled enabled Data transmission and reception occur as either UART signals UTX URX PortD5 PortD6 or IrDA SIR signals IRTX IRRX PortD5 PortD7 based on the setting of Control bit IEN P_IrDA_Ctrl bit9 For example to enable IrDA control module both UEN and IEN bits should be set to 1 to enable UART control module UEN should be set to 1 but IEN should clear to 0 11 MSIE Modem Status Interrupt Enable 0 Disable If this bit is set to 1 the modem status interrupt 1 Enable is enabled 10 SLT R W Self Loop Test Enable 0 Disabled This bit is used for IrDA mode If this bit is set 1 Enabled to 1 IrDA device is seems as full duplex Reserved IAN sl _ Reserved 6 5 WLSEL R
333. gister summary table Name Address Description P ADC Setup 0x7960 ADC Setup Register P TP Ct 0x7965 Touch Panel Control Register P ADC Setup 0x7960 ADC Setup Register Bit 15 14 13 12 11 10 9 8 7 6151413 2 110 Function ADBEN ADCEN CLKSEL ASEN ASMEN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P MADC Ctrl 0x7961 Manual ModeADC Control Register Bit 15 14 13112 11 1101918 7 6 5 4 3 121110 Function ADCRIF C ADCRIENK lt gt CNVRDY STRCNV CHSEL Default 0 0 0 0 0 000 1 0 0 0 0 0 0 0 P MADC Data 0x7962 Manual ADC Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function MADCDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P ASADC Ctrl 0x7963 Auto Sample control register Bit 15 14 13 12 11 10 91817165 4 3 2 1 0 Function ASIF C ASIEN ASFF ASFOV DMA OVER ASFIL FIFOLEV Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_ASADC Data 0x7964 Auto Sample Data register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ASADC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 353 V1 0 Dec 20 2006 G Generalplus GP
334. gt enable HQADC clock 0x7970 b0 gt setup HQADC control register 0x7970 0x7973 gt enable auto sample mode 0x7960 b7 gt start HQADC auto sample Generalplus Technology Inc PAGE 220 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 16 5 Analog Input Control Pin Configuration SAR ADC interface signals Description Touch Panel Y axis Bottom pin shared with GPIO PortB15 Touch Panel X axis Bottom pin shared with GPIO PortB14 mE F F l asw i spy 1 Touch Panel Y axis Top pin shared with GPIO Porsa TSPX JL 1 Touch Panel X axis Top pin shared wih GPIO PortB12 a VADREF O La Reference Voltage supported by GPL162002A 162003A built in logit uneni 1 SaRADCInputChannta O A r uwEN2 1 sar AD Input Channels NO nena 1 SARADC Input Channel C shared with GPIO Porto CA LINEIN4 SAR ADC Input Channel D shared with GPIO PortB11 HQADC interface signals Name Description MICBIAS Buffered voltage output suitable for electret microphone capsule biasing Voltage level is 3 4 VCCADC MICIN Micriphone input LINEINR Right channel line input LINEINL Left channel line input FMINR Right channel EM input FMINL Left channel FM input ADRFLT Right channel anti aliasing filter capacitor For ADC ADLFLT Left channel anti sliasing filter capacitor For ADC TESTP Test mode positive input or output T
335. have wake up capability ODP output configuration can be done in the way of changing between float state 011 in binary and output high state 111 in binary by only modifying the direction bit from 0 to 1 Similarly ODN output configuration can be done in the way of changing between float state 010 in binary and output low state 110 in binary by only modifying the direction bit from 0 to 1 Generalplus Technology Inc PAGE 47 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 5 4 Control Register 1 0 Port Control Register Summary Table Name Address Description P IOA Data 0x7860 IOA Data Register Bit 15 14 43 12 11 1 10 9 8 7 6 5 4 3 2 1 0 Function IOADATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 IOADATA R W Executing the writing operation in this Refer to the above table register will latch setup value into I O PortA VO port configuration data register Similarly executing the read and function operation in this register will read the status from I O PortA external pads P IOA Buffer 0x7861 IOA Buffer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOABUF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 48 V1 0 Dec 20 2006
336. he endpointO FIFO this bit will be set G Generalplus GPL162002A 162003A Programming Guide P_USBD_SCINTEN 0x7B3B USB Standard Command Interrupt Enable Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function GSTS CFEA SFEA SADD GCON SCON GINT SINT Default 0 0 0 0 0 0 0 O 0 0 0 0 0 0 0 0 ru I GSTS Get Status Interrupt Enable 0 7 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked CFEA Clear Feature Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked 5 SFEA Set Feature Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked 4 SADD Set Address Interrupt Enable 0 7 Disable If this bit is set to TU and interrupt occurs hardware 1 Enable Will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked Get Configuration Interrupt Enable 0 7 Disable If this bitis set to 1 and interrupt occurs hardware 1 Enable Will iss e an IRQ3 or FIQ to CPU If this bit is cleared to
337. her priority than GPIO does When special functions are activated GPIO function will be disabled and any setting on GPIO will become invalid To change each memory control signal to GPIO function programmers have to set its corresponding write once register for each I O pin Write once mechanism on these registers is for system reliability purpose Following table depicts shared information about I O ports and their special functions Note The PortA TFT D 15 0 and PortC 3 0 TFT control signals are invalid on GPL162003 body Generalplus Technology Inc PAGE 42 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide PortA and Special Functions Shared Information 15 14 13 12 11 10 9 8 Special Key Scan Function In Out Special LCD TFT interface D 15 8 Function 7 6 5 4 3 2 1 0 Special Key Scan Function Signal KEYOUT7 KEYOUT6 KEYOUTS5 KEYOUTA KEYOUT3 KEYOUT2 KEYOUT1 KE In Out O O O O O O O O Special LCD TFT STN Interface D 7 0 Function Signal LCD D7 LCD D6 LCD D5 LCD D4 LCD D3 LCD D2 LCD Di In Out O O O O Q O O O PortB and Special Functions Shared Information 15 14 13 12 11 10 9 8 Special Nand Flash Touch Panel Interface Analog Input Function Interface Signal In Out Special SPI Interface Function Signal SPI CLK SPI CS
338. his register value at any time regardless of the current serial output enable bit P I2C Status 4 P I2C DeCLK 0x7B64 DC De bounce Clock Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DEBCLK Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 Reserved 7 0 DEBCLK R W De bounce Clock 0 255 0 255 cycles of Since rising time of 12C bus IS very slow system clock this register is used to de bounce the input signal on DC bus I2C intput signal will be latched every DEBCLK cycles of system clock P I2C En 0x7B65 I2C Enable Register Bit 15 14 13 12 11 4 10 9 8 7 6 5 4 3 2 1 0 Function I2CEN Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 1 Reserved I2CEN R W I2C Bus Enable 0 Disable If this bit is set to 1 I2C interface is enabled 1 Enable And IOC 13 12 cannot be used as GPIOs Generalplus Technology Inc PAGE 260 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 18 6 Example Program R1 0x01 Enable DC interface P_I2C_En rl r1 0x09a clock is 75kHz enable ACK P_12C_Ctrl r1 r1 0x0dO master tx enable rx tx P_I2C_Status r1 r1 0x010 P_12C_DeCLK r1 r1
339. his bit after DATA register is read Parity Error This bit is set to 1 received data does not match the parity selected in PSEL Control bit This bit is refreshing in every read So it if the parity of the is necessary to check this bit after DATA register is read Frame Error This bit is set to 1 if a received character does not have a valid stop bit a valid stop bit is 1 bit This bit is refreshing in every read So it is necessary to check this bit after DATA register is read Read 0 Not Occurred Read Occurred Write 0 No Effect Write 1 Clear this Error Flag Read 0 Not Occurred Read 1 Occurred Write 0 No Effect Write 1 Clear this Error Flag Read 0 Not Occurred Read 1 Occurred Write 0 No Effect Write 1 Clear this Error Flag Read 0 Not Occurred Read 1 Occurred Write 0 No Effect Write 1 Clear this Error Flag The status information corresponds to the data read from P_UARTIrDA_Data control register prior to reading P_UART_RXStatus control Generalplus Technology Inc PAGE 157 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide register Write 1 to corresponding register bit will clear the frame parity break and overrun error Note that the received data byte must be read first from P_UARTIrDA_Data before reading the corresponding error status from P UART RXStatus This read sequence cannot be reversed since the
340. hit i a st Word w nd Word 115 0 15 0 L T TT T T T T j 3 0 3 03 03 _ 02 1st 2nd 3rd Ah pixel pixel pixel pixel o o o value valueval e value LOD buffer Layout for ZES a Zet Mord gt lt 2na Word gt 115 115 0 0 10 LO 010 LD 0 Sy th pixel d pixel value e o o o 9 o value Se value value 11 5 Control Registers STN LCD Control Register Summary Table P LCD Setup 0x7980 LCD setup register P LCD Clock 0x7981 LCD clock register Generalplus Technology Inc PAGE 117 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Name Address Description There are eleven control registers residing from 0x7980 through 0x798A to control the LCD Interface in GPL162002A 162003A If color mode or gray level mode is enabled LCD palette locating in Ox7A00 Ox7 AFF is activated The following sections give detailed descriptions of these control registers Note that Palette registers can be modified only when LCDEN control bit is cleared to 0 Besides delay with one frame rate interval is necessary before starting to modify Palette registers Step 1 Clear LCDEN bit to 0 I P LCD Ctrl bit13 0 Step 2 Delay with one LCD frame rate interval Step 3 Start to modify Palette register s Step 4 Set LCDEN bitto 1 J Re enable LCDEN P LCD Setup 0x7980 LCD Set
341. hnology Inc PAGE 185 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide ET RE_WA R W Remote Wakeup The USB will generate a resume signal of a duration of 0 24 micro second when this bit is set in suspend mode and the USB device has already received the SET_FEATURE command of REMOTE_WAKEUP This bit must be cleared manually after SUSPEND MODE is cleared Remote Wakeup Feature When the device gets SET FEATURE command of REMOTE WAKEUP this bit will set to 1 by hardware When the device gets CLEAR FEATURE command of REMOTE WAKEUP this bit will clear to O by hardware Reset This bit is assigned to reset USB BUS Logic 0 of this bit means there is a USB reset on the contrary logic 1 means no reset Suspend Mode This bit is set by hardware when it enters suspend mode This bit is cleared by hardware when it returns from suspend mode or the USB reset signal is generated P USBD EPOData 0x7B33 USB Endpoint0 Data Register Bit 15 144 13 12 11 510 9 8 7 6 5 4 3 2 1 0 Function E EPODATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition _ usay gt gReewed Ca LEPODATA ew Endpointo Data P USBD_BilData 0x7B34 USB Bulk IN Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BIDATA
342. ht before SAR ADC channel sample operation and turn off SAR ADC immediately after ADC data acquirement However in order to ease the software effect and decrease the CPU bandwidth programmers might always turn on ADC during voice recording Note that AD Conversion time is programmable and can be set as SYSCLK 2048 SYSCLK 1024 SYSCLK 512 SYSCLK 256 SYSCLK 128 and SYSCLK 64 for using ADC under different kind of SYSCLK frequency Touch Panel Interface GPL162002A 162003A supports analog touch panel interface It includes two dedicated SAR ADC channels some built in switches and de bounces circuit In addition GPL162002A 162003A has interrupt and wakeup mechanisms while a stylus taps on the touch panel It also allows programmers to poll the touch panel status for checking the stylus tapping There are only four pins for the touch panel interface TSPX TSMX TSPY and TSMY A touch panel is composed of two transparent resistive layers separated by insulating spacers We can consider touch panel as two normally disconnected resistors a horizontal resistor and a vertical resistor Following diagram indicates physical view and equivalent circuit of touch panel Generalplus Technology Inc PAGE 215 V1 0 Dec 20 2006 G Generalplus Resistive Touch Panel GPL162002A 162003A Programming Guide Equivalent Circuit Connector Transparent Resistive Conductor Connector Indium tin oxide ITO X Layer
343. ile measuring x and y coordinate value Typically a tap on the touch panel lasts about several tens of micro seconds us During touch panel interrupt mode no matter stylus is tapping on the touch panel or not the system will not consume a huge amount of power because a 50K Ohms pull high resistor exists on TSPX As a result programmers should make touch panel in interrupt mode at most of time even when stylus is tapping on H the touch panel is tapped and x y coordinate values are required turn to the operating mode and get ADC values Finally after acquiring ADC values turn back to interrupt mode immediately To check the touch panel tapped or untouched GPL162002A 162003A provides interrupt and polling mechanisms After CPU registers are set properly stylus tap operation can trigger INT and wake GPL 162002A 162003A up from halt mode or sleep mode just like other interrupt or key wakeup events On the other hand users can also monitor the stylus tap status by polling The polling is very important because it is the only way to determine if x and y coordinated values are corrected The interrupt setup and usage and wakeup event setup are the same as other interrupt and wakeup events Generalplus Technology Inc PAGE 218 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Note that there is a de bounce circuit on stylus tap signal Therefore it is not necessary to perform software d
344. ing pressed Support inverted output Automatic sample mode Manual sample mode Programmable sampling time Key Scan Function The key scan function of GPL162002A 162003A configures IOA as output state at IOA 7 0 and input state at IOA 15 8 The IOA 7 0 can be shared with LCD data 7 0 which means the key scan function can still work even when LCD data is used on IOA 7 0 It should be noted that when key scan function shares IOA with LCD panel each output must connect a diode serially to the key pad to prevent the LCD glitch caused by contention when multi keys are pressed The following diagram shows an example of the connection If users use TET LCD as parallel mode 16 bit data transmission IOA 15 0 are all at output state So the keyscan function on this mode is invalid Key Scan Application Circuit Before using the key scan function users must set IOA 15 8 to input mode If not all of input pins are used set necessary pins of IOA to input mode is still acceptable But the auto detect interrupt may work incorrectly if the unused IOA is toggled when the scan is processing Figure 1 and 2 shows the application circuit for key scan function L Generalplus Technology Inc PAGE 294 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide IOA 0 IOA 1 IOA 2 IOA 3 IOA 4 IOA S IOA 6 IOA 7 CLD 0 CLD 1 CLD 2 CLD 3 CLD 4 CLD 5 CLD 6 CLD 7
345. internal clock sources timer mode or from external I O pin counter mode TimerE and TimerF do not support Interrupt function Main features Variance clock source selection for each timer source Support two external clock sources One external clock source provides 1 4 1 16 pre scalar Each programmable clock source can be synchronous with CPU clock as for each timer source Three timers support Capture function Three timers support Comparison function Three timers support Pulse Width Modulation PWM function Timer Structure and Clock Source There are two basic operation modes on GPL162002A 162003A timer counter module timer mode and counter mode In timer mode the clock source is generated by internal clock sources such as CPUCLK 256 CPUCLK 2 32768Hz 8192Hz 4096Hz 1024Hz 4Hz 2Hz 1Hz or combinations for detail refer to clock source block diagram Besides each clock source can be synchronized with CPU clock in the way of setting the corresponding control bits In counter mode the clock source is supported by external clock source pin EXTA or EXTB Additionally signal from external clock source can be divided by 4 or 16 pre scalar and will be capable of selecting trigger edge rising or falling To ensure the CPU clock synchronization procedure is completed this external clock frequency has to be less than or equal to a half of CPUCLK Following are function diagrams of sourc
346. interrupt is cleared After the pending interrupt is cleared the SCL line will be released After the CPU receives the interrupt request it should read the data from P DC Data before clear the pending interrupt Bus Arbitration Produres Arbitration takes place on the SDA line to prevent the contention on the bus between two masters Ifa master with a SDA high level detects another master with aS DA active Low level it will not initiate a data transfer because the current level on the bus does not correspond to its own The arbitration procedure will be extended until the SDA line turns high However when the masters simultaneously lower the SDA line each master should evaluate whether or not the mastership is allocated to itself Eor the purpose of evaluation each master should detect the address bits While each master generates the slaver address it should also detect the address bit on the SDA line because the lowering of SDA line is stronger than maintaining high on the line For example one master generates a low as first address bit while the other master is maintaining high In this case both masters will detect low on the bus because Low is stronger than High even if first master is trying to maintain high op the line When this happens low generating as the first bit of address master will get the mastership and high generating as the first bit of address master should withdraw the mastership Jf both masters generate
347. ion DMAACKH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition al Rea amp a Y 2 0 DMAACKH DMA ACK Count High The register is used in DMA mode It indicates how many transactions each transaction is packet are not finished yet P USBD EPStall 0x7B54 USB Endpoint Stall Bit Register Bit 154144 13 12 11 10 9 8 71615141 3 2 1 0 Function Af 4 11SS BOSS BISS EPOSS 1ISB BOSB BISB EPOSB Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 stg meses 11 IISS R W Interrupt IN Write 1 to clear this bit It indicates that USB device has replied the request by sending STALL 10 BOSS R W Bulk OUT Write 1 to clear this bit It indicates that USB device has replied the request by sending STALL BISS R W Bulk IN Write 1 to clear this bit It indicates that USB device has replied the request by sending STALL Generalplus Technology Inc PAGE 202 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 15 7 EP0SS R W Endpoint0 Write 1 to clear this bit It indicates that USB device has replied the request by sending STALL Ta Reserved 3 IISB Interrupt IN If STALL happens the bit will be set The bit is for debugging only 2 BOSB Bu
348. ion 15 0 IODDIR R W This control register sets the direction of I O Refer to the above table PortD In addition the direction setup VO port configuration value can be read back from the same and function control register P IOD Attrib 0x787B IOD Attribution Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IODATT Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 IODATT R W This control register defines the attribution Refer to the above table of I O PortD In addition the attribution VO port configuration setup value Can be read back from the and function same control register UO structure diagrams I O BUFFER R I O DATA W I O BUFFER W Data Registers UO DIRECTION R W amp Control Logic UO ATTRIBUTION R W gt I O DATA R lt Generalplus Technology Inc PAGE 53 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 5 6 Special Notes Suppose a programmer intends to change the I O configuration and finds out that two control registers need to be set up the various setup sequence may have different outcomes For example changing the I O mode from input with pull low resistors to output with buffers requires changing both Direction and Attribution registers Setting the Direction bit to 1
349. ion TMDPLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerE_Preload 0x79C2 TimerE Preload Register Bit 15 114 13 124 11 10 9 8 7 6 5 4 3 2 1 0 Function TMEPLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TimerF Preload 0x79CA TimerF Preload Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMFPLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerA_CCP_Reg 0x78C3 TimerA Capture Comparison PWM Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMACCPR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 323 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TimerB_CCP_Reg 0x78CB TimerB Capture Comparison PWM Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMBCCPR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerC_CCP_Reg 0x78D3 TimerC Capture Comparison PWM Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMCCCPR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TimerA_UpCount 0x78C4 TimerA Up Count Bit 15 14 13 12
350. iple of 64 bytes has to generate 512 64 8 IN transactions and write 8 to this register This register is used only in DMA mode P USBH AutoOutByteCount 0x7B0B USB Host Automatic Out Transaction Byte Count Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function HAOBC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function type Description Condition 15 0 HAOBC R W Host Automatic OUT Transaction Byte Count When using DMA in Write the number of OUT transaction in these USB host the transmit bits that is to be initiated For example if the receive byte must be host is going to transmit 512 bytes to the multiple of 64 bytes device it has to generate 512 64 8 OUT Generalplus Technology Inc PAGE 207 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition transactions and write 8 to this register This register is used only in DMA mode P_USBH_AutoTrans 0x7B0C USB Host Auto Transfer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CAO CAI AOX AIX Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 psa jew NN Clear Auto Out Transfer Write 1 to this bit to c
351. istakes during development Due to the updates of the confirmation sheet please download a newest confirmation sheet from http www generalplus com H Generalplus Technology Inc PAGE 10 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 2 1 2 2 2 Introduction General Description The GPL162002A 162003A a 16 bit architecture LCD controller product carries the Sunplus newest 16 bit microprocessor called nSP pronounced as micro n SP This high processing speed assures the w nSP is capable of handling complex digital signal processes easily and rapidly Therefore the GPL 162002A 162003A is applicable to the areas of digital sound process voice recognition and learning auxiliary product The memory capacity includes a 30K word working SRAM and 128K word ROM The LCD controller is able to support maximum 320x320 dots 16 gray level or 4096 CSTN or 640X480 dots 65536 color TFT displays Other features include 64 programmable multi functional Os MP3 decode accelerator six 16 bit timers counters 32768Hz Real Time Clock Low Voltage Reset 12 bit ADC for touch panel and general purpose application 16 bit ADC DAC for voice playling recording supports SD memory card USB 1 1version and plus many others The control registers of MP3 decode accelerator wll not be described in this programming guide Please contact Generalplus for details of MP3 decoding accelerator and decoding process
352. it 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR_Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA TCountLO 0x7B83 DMA Terminal Count Low Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA TCountL1 0x7B8B DMA Terminal Count Low Register 1 Bit 15 14 13 12 4 14 4 10 9 8 7 6 5 4 3 2 1 0 Function TCountL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_TCountL2 0x7B93 DMA Terminal Count Low Register 2 Bit 154 14 134 12 1 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA TCountL3 0x7B9B DMA Terminal Count Low Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA SRC AddrHO 0x7B84 DMA Source High Address Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SRC_AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 O 0 0 0 H Generalplus Technology Inc PAGE 362 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_DMA SRC_AddrH1 0x7B8C DMA Source High Address Register 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Functi
353. it 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function NFCMD Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 236 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Type Description Condition Write Command instruction 15 0 Command value Write Command value to the register and For example NAND FLASH interface will write this 00H Read A area Command value to NAND FLASH 01H Read B area memory automatically 50H Read C area 80H 10H Page program 70H read Status 90H read ID FFH reset 60H DOH Block erase P_NF_AddrL 0x7852 NAND Flash ADDR Low Word Regisiter Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function 2 Cycle 1 Cycle Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Type Description Condition NFADDRL W Write Low Word Address instruction 15 0 Address Value Write 1 cycle and 2 cycle Address value to the register and then NAND FLASH interface will write this Address value to NAND FLASH memory automatically P_NF_AddrH 0x7853 NAND Flash ADDR High Word Register Bit 151 14 13 42411 10 9 8 7 6 5 4 3 2 1 0 Function 4 Cycle 3 Cycle Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Eunction Description Condition NFADDRH Write High Word Address instruction 15
354. ith16 bits representing a pixel This 16 bit per pixel configuration is composed of R 5 bit G 6 bit and B 5 bit In most cases the size of LCD buffer equals to P TFT Pixel Num 1 x P TFT Line Num 1 x 16 bits First word second Third eise LCD buffer TFT LCD Diaply Screen Video Memory Sub Frame Display PIP GPL162002A support four sub frame display function The main display frame can be covered with sub frames of their own data buffer without changing original main fram data in LCD buffer This is a very useful function for game or animation display If these four sub frames overlap with each other simultaneously the priority is as PIP3 gt PIP2 gt PIP1 gt PIPO Each PIP control supports scrolling function this means the sub frame buffer data are larger than data of sub frame display screen size By this scrolling method it is easy to review all sub frame buffer data for each PIP Generalplus Technology Inc PAGE 132 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 12 5 Control Register TFT LCD Control Register Summary Table Generalplus Technology Inc PAGE 133 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P TFT CTRL 0x7D00 TFT Control Register Bit 15 14 43 12 11 109 8 7 6 5 4 3 2 1 0 Func
355. lO 0x7B80 DMA Channel Control Register 0 Bit 15 14 13 12 11110019 81716 51 4 3 2 1 0 Function WriteReq TM TARByte SRCByte TD RS CIE SF DF SD DD DB NOR Mod BS CE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 360 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P DMA Ctrl1 0x7B88 DMA Channel Control Register 1 Bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Function WriteReq TM TARByte SRCByte TD RS CIE SF DF SD IDD DB NOR Mod BS CE Init 0 0 0 0 0 0 0 0 0 0 0 O 0 0 0 0 P_DMA Ctrl2 0x7B90 DMA Channel Control Register 2 Bit 15 14 13 12 1110191 8 71 6 54 3 2 110 Function WriteReq TM TARByte SRCByte TD RS CIE SF DF SD IDD IDB NOR Mod BS CE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA Ctrl3 0x7B98 DMA Channel Control Register 3 Bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Function WriteReq TM TARByte SRCByte TD _ RS CIE SF DF SD DD DB NOR Mod BS CE Init 0 0 0 0 0 0 0 0 0 0 0 O 0 0 0 0 P DMA SRC AddrLO 0x7B81 DMA Source Low Address Regist
356. lear P USBH AutorTrans 1 Write 1 clear Clear Auto IN Transfer Write 1 to this bit to clear P USBH AutoTrans 0 Write 1 7 clear 1 AOX R W Auto Out Transfer 0 Disable This bit is set 1 for entering DMA mode Tor Bulk out 1 Enable When transaction is surely finished this bit must be cleared Note After DMA is finished DMA counter reaches 0 the transaction may not be finished yet Enabling this bit programming the UHAOBCR and then triggering the OUT transfer will Start the OUT transaction This bit is cleared by software AIX R W Auto In Transfer 0 Disable This bit is set 1 for entering DMA mode for Bulk in 1 Enable When transaction is surely finished this bit must be cleared Enabling this bit programming the UHAIBCR and then triggering the IN transfer will start the IN transaction This bit is cleared by software P USBH Status 0x7B0D USB Host Status Register Bit 15 14 131 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TO CRC DE BS UP SH NH AH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function type Description Condition Generalplus Technology Inc PAGE 208 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide ENEE TimeOut No Response This flag is set when timeout or no response occurs from the device CRC16 Error Packet Received This flag is set
357. lk OUT If STALL happens the bit will be set The bit is for debugging only 1 BISB Bulk IN If STALL happens the bit will be set The bit is for debugging only EPOSB EndpointO If STALL happens the bit will be set The bit is for debugging only PS In CPU mode BULK_IN and BULK_OUT can work simultaneously BULK_IN will occupy the USB buffer 0x00 0x3F of SRAM and BULK OUT will occupy the USB buffer 0x40 0x7F of SRAM USB Host Register Definition Bit 0 in P USBH Config must be set to 1 when accessing the USB Host functions P USBH Config 0x7B00 USB Host Configuration Register Bit 15 14 N13 1224117 10 9 8 7 6 5 4 3 2 1 0 Function SUS ASOF SOFTR HOSTEN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C 2s meme i R W Host Suspend 0 HOST SUSPEND is disable Write 1 to this bit will enable host 1 HOST SUSPEND is enable suspend USB Transceiver is in SUSPEND mode The SUSPEND mode is controlled by software when HOST is enable A L NE ASOF R W Auto Generate SOF 0 Generate SOF by software Setting this bit to 1 will generate SOF 1 Generate SOF by hardware timer by hardware If this bit is 0 write 1 to P_USBH_Transfer 0 to generate Generalplus Technology Inc PAGE 203 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide serene EE SOFTR
358. me Clock Second Setup Register Only 0x00 0x3B Valid 0 59 P_Minute 0x7921 Minute Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RTCMIN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition usel l Respet 5 0 RTCMIN Real Time Clock Minute Setup Register Only 0x00 0x3B Valid 0 59 P Hour 0x7922 Hour Register Bit 15 14 13 142 11 10 9 8 7 6 5 4 3 2 1 0 Function z RTCHR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mesi lt Reserved 4 0 RTCCHR Real Time Clock Hour Setup Register Only 0x00 0x17 Valid 0 23 When updating above registers programmers should check P RTC HMsSBusy 0x7937 for keeping hour minute second setup stable P Alarm Second 0x7924 Alarm Second Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ALMSEC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 86 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition nse JI Reang ALMSEC Alarm Second Setup Register Only 0x00 0x3B Valid 0 59 P_Alarm_Mintue 0x
359. mming Guide 6 1 pigeelifeio EE 55 6 2 Peripheral Interrupt Arrangement iii 57 6 9 Control RegISters iodo israel iepientesaitverssacdicnsteianssacesest 60 6 4 Program Examples u iii A aida cea 67 7 TIMER COUNTER c M M 68 7 1 Timer WOM UCU s EE mt 68 7 2 Timer Structure and Clock Source sise 68 T3 Control Registers 73 LA SAA 79 8 UI ET r E 80 8 1 ai siege 110 WEEN Ad 80 8 2 Timebase structure and clock source Mb teaa ALl Anne 80 8 3 Control Registers eoe teet es Nef rie 80 8 4 Program Exvamples sees sees ee eee ereenn Ni 84 9 REAL TIME CLOCK RIC S l u aR A Nee A a meme 85 9 1 INTO UC it iii mm We EE 85 9 2 RTC Structure and clock source 4 JL is 85 9 3 Control Reglsters uu uuu sul EE Geen 85 9 4 Program Examples sa MAL erre Acedera RAR ERRE 91 10 AUDIO OUTPU T WT ns D Ten 93 10 1 DAC uo O NN An nn E Lui 93 10 2 DAG Operation EE a A ie 93 10 3 Block Diag arNh e A 94 10 4 SDS CIE ERE TN Nc 94 10 5 NERA A m 94 10 6 Control ROUSE EE 96 10 7 A einer 108 10 8 Ramp Sand Ramp Down ect iine erectae te e in fit natale EAR 108 10 9 3D EQ AC parameter reference setup 109 80 9 1 EQ AC Control Method u u LL LU nan rari renean ke rana RTL cdi 109 10 9 2 3D Control
360. mple Mode FIFO Full Interrupt Enable This bit is used to enable FIFO full interrupt when Auto Sample mode is activated If this bit is set to 1 and the FIFO is full definition of full is depending on ASFIL control bits P_ASADC_Ctrl bit 9 5 hardware will issue an IRQ1 or FIQ to CPU To select between IRQ1 and FIQ please refer to Chapter Interrupt Auto Sample Mode FIFO Full Flag This read only flag is set to 1 by hardware when auto sample FIFO is full Auto Sample Mode FIFO Overflow Flag This read only flag is set to 1 by hardware if auto sample FIFO has been full and last data has been replaced by the latest sampled ADC data DMA mode The ADC auto sample mode is connected to the DMA channel source 8 the DMA transfer will not clear ASIF After DMA mode is enabled ASIF will be cleared automatically when FIFO level is lower than designated level Auto Sample FIFO Over Write Mode This overwrite or to skip incoming data register is to decide to right after auto sample FIFO is full PAGE 225 0 Disabled 1 Enabled 0 Not Full 1 Full 0 Auto Sample FIFO is not overflow 1 Auto Sample FIFO is overflow 0 needs to write 1 to ASIF to clear the ASIF 1 DMA mode programmer do not need to write 1 to ASIF the ASIF will be clear automatically when FIFO Interrupt mode programmer level is lower than trigger level 0 The further write to the full FIFO will be skipped 1
361. mportant facts should be noted 1 To turn off the clock of system bus and system control module is not allowed This will cause unexpected results and cause the system crashed 2 Before turning off the memory controller s clock be sure you are not using the external bus for a program or placing data in the external bus 3 Besure the corresponding device is not active before turning off its clock P CLK Cd 0x7804 Peripheral Clock Control RegisterO Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Clock Source 15 0 Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P CLK CtrH 0x7805 Peripheral Clock Control Register1 Bit 15 14 13 12 11 104 9 8 7 6 5 4 3 2 1 0 Function Clock Source 31 16 Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Please refer to the follow table for the device of each source Clock Source DeWte po A A o Sysmiss x CA A Go s sevice dir e E x a EY mms o m x 87 timer rR EE 7 me Analog SP Bus Timer E F SD MMC Note On GPL162003 this bit is invalidly System Control System Control SECH ETC EC 2 j a Generalplus Technology Inc PAGE 17 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_PLLN 0x7817 Fast PLL output divider register Bit 15
362. n DPO TRST TSOFI ITOK TXO VSC AOX AIX RX TX SOF DSC Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBH_INTEN Ox7BOF USB Host Interrupt Enable Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DPO TRST TSOFI ITOK TXO VSC AOX AIX RX TX SOF DSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P USBH SoftRST 0x7B11 USB Software Reset Register Device Plug Out Register Bit 15 14 13 12 d 11 10 9 8 7 6 5 4 3 2 1 0 Function DPOE DPOTV SRST Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBH_INAckCount 0x7B17 USB IN ACK Count Register Bit 154 14 134 122k 11 10 9 8 7 6 5 4 3 2 1 0 Function INACK Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBH_OutAckCount 0x7B18 USB OUT ACK Count Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function OUTACK Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P USBH RSTAckCount 0x7B19 USB Reset ACK Count Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IARSTJOARST Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 352 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_USBH_Dreadback 0x7B1B USB D D Readback Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DM DP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC control re
363. nc PAGE 338 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Function Function Function P TFT PIP2 STARTAH 0x7D2D TFT PIP2 Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2 SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP3_STARTAH 0x7D38 TFT PIP3 Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP3 SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIPO_STARTAL 0x7D18 TFT PIPO Frame Buffer Start Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIPO_SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP1_STARTAL 0x7D23 TFT PIP Frame Buffer Start Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIP1 SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP2 STARTAL 0x7D2E TFT PIP2 Frame Buffer Start Low Address Bit 15 14 13 12 4 11 4410 9 8 7 6 5 4 3 2 1 0 PIP2 SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 STARTAL 0x7D39 TFT PIP3 Frame Buffer Start Low Address Bi
364. nce There are two modes in detecting the external request signal Single mode and Demand mode respectively Single Mode The single mode means only the rising edge of the external request will be detected Each rising edge of the request signal will result in a single DMA transfer Fig1 External Single mode Generalplus Technology Inc PAGE 264 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 19 3 2 Demand Mode 19 4 The demand mode means the DMA request become level sensitive If the DMA request is detected high at the beginning the DMA controller will start a DMA transfer At the end of the DMA transfer DMA controller will detect the level of the DMA request signal if the DMA request signal is still high another burst read write will start Other DMA channel could not get the bus grant if the DMA request is kept low during a demand transfer mode but if the P_DMA_TCount reach 0 the bus grant could be released even the DMA request is still low The peripheral built in GPL162002A 162003A such as SD Card UART etc are all using this mode DMARQ DM DMACK Fig2 External Demand Mode Double Buffer Mode In order to prevent the gap between a DMA transfer and another DMA transfer the DMA controller provides the double buffer mode With the double buffer mode programmers can write the new address count of next DMA transfer before the end of current DMA trans
365. nd High Address Bit 15 44 13 127 11 10 9 8 7 6 5 4 3 2 1 0 Function a PIP1 VIR EAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP2 MIR EAH 0x7D2B TFT PIP2 Virtual Frame Buffer End High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP2 VIR EAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 VIR EAH 0x7D36 TFT PIP3 Virtual Frame Buffer End High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP3_VIR_EAH Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H Generalplus Technology Inc PAGE 145 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition rel Reserved 10 0 PIP _VIR_EAH RW PIP Virtual End High Address This register is valid only when PIP SCREN is set to 1 The virtual frame End address means the real address of data See the following diagram for details P_TFT_PIPO_VIR_EAL 0x7D16 TFT PIPO Virtual Frame Buffer End Low Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPO_VIR_EAL Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP1_VIR_EAL 0x7D21 TFT PIP1 Virtual
366. nd blue Each element which is connected to a single LCD segment line can be divided into 16 levels Maximum level of display color will be 16 red x 16 green x 16 blue or says 4096 Therefore one pixel takes 12 bits LCD buffer to represent a color level We call this configuration as 12 bit per pixel LCD buffer layout for each pixel is depicted as following diagram Please note that 3 word contents 4 pixel color information LCD buffer Layout for 12 bit per pbel 15 0 15 0 15 mgr gees art mu gggg bbbb mr eses NT nm ve wd 1st pixel color 2nd pixel color 3rd pixel color 4th pixel color The larger the LCD resolution is number of common X numberof segment the larger the size of LCD buffer is In most cases 12 bit per pixel configuration is not popular because it requires larger size of a LCD buffer and it is too costly As a result the concept of the palette is derived from these drawbacks mentioned above Take 4 bit per pixel configuration as an example in LCD buffer each pixel takes 4 bits that is each pixel can display 16 colors However GPL162002A 162003A can display 4096 colors now the problem becomes how we can map a 4 bit pixel value to a real display value The solution is Palette the translation table If the palette is enabled 4 bit value range form 0 to 15 does not represent the real display information Instead this 4 bit value represents an index to the palette mapping table
367. nd the DF in P DMA Ctrl 6 is O It should be noted if the TD in P_DMA_ Ctrl 11 10 is set to memory to IO or IO to IO mode this register is useless P DMA TCountHO 0x7B86 DMA Terminal Count High Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA TCountH1 0x7B8E DMA Terminal Count High Register 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 274 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_DMA_TCountH2 0x7B96 DMA Terminal Count High Register 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_TCountH3 0x7B9E DMA Terminal Count High Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TCountH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 10 Reserved p TCountH DMA Terminal Count High 25 16 O
368. nding data attribution bit directly P_IOD_Data bit13 P IOA Attrib bit13 00 with pull low resistor and control 01 7 with pull high resistor 1X floating GPlo All modes A O Generalplus Technology Inc PAGE 45 V1 0 Dec 20 2006 G Generalplus IOB0 Pin Special Function Shared Information Special Function UO Mode Supported Floating Output Buffer High or Low TimerA Capture Mode Trigger Input TimerA Comparison Mode Event Output TimerA PWM Mode Signal Output Output Buffer High or Low GPL162002A 162003A Programming Guide Enable Control bit P TimerA CCP Ctrl bit 15 14 01 Description When one of these modes is enabled direction attribution data control bits are forced to P TimerA CCP Ctrl bit 15 14 10 corresponding mode The contents on direction P_TimerA_CCP_Ctrl attribution data control bits bit 15 14 11 have no effect on this I O pad Input pull high or low P_MINT_Ctri bit 10 1 D GPIO All modes IA Q en O 10B1 Pin Special Function Shared Information Special Function 1 0 Mode Supported Floating Output Buffer Comparison Mode High or Low Event Output TimerB Capture Mode Trigger Input TimerB TimerB PWM Mode Signal Output Output Buffer High or Low P TimerB CCP Ctrl bit 15 14 01 P TimerB CCP Ctrl bit 15 14 10 P TimerB CCP Ctr bit 15 14 11 Enable Control bit Description When one
369. ng data from this register will be valid only if the CMDBUFFULL is set This register is used to store the response from the SD card Commands with response R1 R1b R3 or R6 have 6 bit command index and 32 bit response length The response will be stored in this register Commands with response R2 have response length in 128 bits Host needs to poll the CMDBUFFULL bit in the status register to determine when to read this register when CMDBUFFULL bit is 1 The data in this register is valid only Host must read P SD RespL first and then read P_DS_RespH next to ensure every 32 bit response is received correctly For response R2 it has to read P DS RespL and P DS RespH for four times to get the 128 bit reponse P SD Status 0x79D7 SD MMC Status Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 110 Function CINT CPRE C CWP DCRCE C TO C DBufEpt DBufFu RBufEu RCRCE C RidxE C DCOM C CCOM C CBY BY Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 14 13 CINT 12 CPRE C R W 10 DCRCE C RW Generalplus Technology Inc Reserved Card Interrupt Indicate a SD lO card interrupt is pending This Di will be set only when IOEN in control register is KHostineeds to clear the interrupt by using device specific command Write 1 to this register will have no effect Card Present This bit is only t
370. ngs And SPICSN does not become SPI interface Lra Reserved _ 5 SCKPHA R W SPI clock phase Refer to timing scheme This bit should not be changed after SPIEN is 1 on previous section SCKPOL R W SPI clock polarity Refer to timing scheme imu bit should not be GE after SPIEN is 1 on O section Reeved eA I SCKSEL R W Master mode clock selection 000 SYSCLK 2 0012 SYSCLK 4 010 SYSCLK 8 011 SYSCLK 16 100 SYSCLK 32 101 SYSCLK 64 110 SYSCLK 128 111 Reserved P_SPI_TXStatus 0x7941 SPI Transmit Status Register Bit 15 14 13 42 11 10 9 8 17 6 5 4 3 2 1 0 Function SPITXIE SPITXIEN TXFLEV TXFFLAG Default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Bit F ncton Type Description 1 Condition 15 SPITXIF R W SPI Transmit Interrupt flag Read 0 Not Occurred This bit is set to 1 by hardware when the Read 1 Occurred transmitting FIFO level is lower then the Write 0 No effect value setting by users When SMART is Write 1 Clear the flag set in P SPI Misc register the bit will be cleared as long as the transmitting FIFO level is higher than interrupt level else users should write 1 to clear this flag SPITXIEN R W SPI Transmit Interrupt Enable 0 Disabled If this bit is set to 1 and SPI interrupt 1 Enabled when 8 bit TX FIFO level in lower then Note If enable SPI TX interrupt in
371. nic devices The SD Memory Card communication is based on an advanced 9 pin interface Clock Command 4xData and 3xPower lines designed to operate in a low voltage range SD IO card controller is based on and is compatible with the SD memory card The intent of the SD IO card controller is to provide high speed data I O with low power consumption for mobile electronic devices The SD MMC card controller built in GPL162002A 162003A is designed to have high performance transfer rate by using DMA access which can achieve the best performance cost ratio Fully compatible with SD MMC Memory card specification Accept SD commands directly to improve the compatibility Programmable clock speed on the SD bus SD bus clock control while the buffersis full Interrupt generation e DMA R W operation e Both 1 bit and Abu SD modes are supported e SD 10 card interrupt detection 20 2 Block Diagram Peripheral BUS Bus Interface and Register Command State Machine Data State Machine FIFO and CRC check ke CMD CLK TI DAT 3 0 SD BUS Generalplus Technology Inc PAGE 282 V1 0 Dec 20 2006 G 20 4 Generalplus GPL162002A 162003A Programming Guide 20 3 Command Line Control There are three major types of responses SD card will send They are no response 6 byte response and 17 byte respons
372. nterrupt event is generated Please refer to chapter DMA AND BRIDGE Controller There are several interrupt events in USB function for details please refer to chapter USB Controller There are three interrupt events in AD Conversion Ready Interrupt These are manual mode AD convert ready line in right channel overflow and line in left channel or mic in overflow Any one of these interrupt sources can trigger IRQ1 Therefore in IRQ1 AD Conversion Ready interrupt service routine programmers should read P MADC Ctr P HQADC R Gain and P HQADC L Gain to distinguish which interrupt event is generated Please refer to chapter Analog Input On GPL162003 body the FIQ and IRQ TFT interrupt vector are invalidly Generalplus Technology Inc PAGE 59 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 63 Control Registers Global Interrupt Control Register Summary Table Name Address Description P INT Status1 0x78A0 Interrupt Status Register 1 P_INT_Status2 0x78A1 Interrupt Status Register 2 P_INT_Priority1 0x78A4 Interrupt Priority Register 1 P_INT_Priority2 0x78A5 Interrupt Priority Register 2 P MINT Ctrl 0x78A8 Miscellaneous Interrupt Control Register P INT Status1 0x78A0 Interrupt Status 1 Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 e 1 0 Function KEYIF ADCRIF TFTUFIF TFTFEIF UTIRIF SPIIF FPIF TPIF ASIF
373. o detect the DAT3 on the SD interface when the controller is idle Controller s Host can initiate a transaction no matter what this bit behavior will not be affected by this bit is Writing 1 to this register will clear the pending interrupt of card present Card Write Protect Indicate the card is writing protect This bit is only to detect the writing protect pin on the interface Controllers behavior will not be affected by this bit protecting the card Data CRC Error Indicate read data CRC error or write data with Host is responsible for CRC error response PAGE 288 Read 0 Not occurred Read 1 Occurred Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear Read 0 Not protect Read 1 Protect Read 0 Not error Read 1 Error Write 0 No effect Write 1 Clear V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Type Description Condition data response time out Write 0 No effect Write 1 Clear Data Buffer Empty Read 0 Buffer Not This bit will be set when data buffer is empty Empty This bit will be cleared after data had been Read 1 Buffer Empty written to the DATATX register or after writing 1 R W Time Out Read 0 Not timeout Indicate command response time out or read Read 1 Timeout T to StpCmd bit in P SD CMD DBufFu Data Buffer Full Read 0 Buffer Not ull This bit will be set when data buffer is full This
374. o effect on any operation of P TimerX Ctrl bit 15 14 In other words only one interrupt event is valid on the control bits P_TimerX Ctri bit 15 14 at one time either up counter overflow interrupt or comparison event interrupt Pulse Width Modulation Mode When a timer counteris set as in Pulse Width Modulation PWM mode the PortB 2 0 pin is configured as OUTPUT pin automatically When the timer counter is enabled the PWM output will toggle at the overflow of timer counter and at the end of CCP cycle There are two output signal polarities on PWM output pin positive and negative Generalplus Technology Inc PAGE 71 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Positive Polarity Non Return One NRO Non Return Zero NRZ Negative Polarity ss AA X t source clock period x CCP Register value Preload Register value 1 Also known as CCP cycle T source clock period x 65536 Preload Register value Timer C A 16 bit CCP Register PWM Daty Cycle Control CCP C A PWM C A X PORTBD2 0 Control Logic PWM Frequency Control Timer CA 16 bit Timer C A Preload Register 16 bit Up Count Register In Pulse Width Modulation PWM normal mode PWM frequency is set by the preloaded register value See the formula below PWM Output Frequency Source Clock Frequency 65536 Preload Register Value PWM du
375. occurs hardware will issue an IRQ7 to CPU If this bit is cleared to 0 this interrupt will be masked Generalplus suggests programmers do not use TimbaseB as halt sleep mode wake up Generalplus Technology Inc PAGE 81 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function type Description Condition source because the TimebaseB interrupt occurs more quickly than the time CPU wakes up from halt sleep mode As a result the TimebaseB interrupt flag will not be held from halt sleep wake up 13 TMBBEN R W TimeBaseB Module Enable 0 Disabled If this bit is set to 1 TimeBaseB module will 1 Enabled be enabled on the contrary it will be disabled for power consumption consideration ma Reseed NS 1 0 TMBBS R W TimebaseB Frequency Selection 00 8Hz There are four frequency sources on 01 16Hz TimebaseB 8Hz 16Hz 32Hz and 64Hz 10 32Hz These two control bits are to select one of 112 64Hz four frequencies P TimeBaseC Ctrl 0x78B2 TimeBaseC Control Register Bit 15 14 13 12 4110 9 8 6 5 41 3 2 10 Function TMBCIF C TMBCIE TMBCEN 29 1 TMBCS Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 TMBCIF C R W TimebaseC Interrupt Flag Read 0 Not Occurred Write 1 to clear the flag Read 1 occurred If TimebaseC interrupt occur
376. oject Configuration Select which version of the project is used debug or release 3 Simulator ICE select u nSP amp IDE running mode If ICE mode is selected you should connect an emulation board to your computer through a parallel port or a USB port 4 PC track enable enable PC Trace function make sure the ICE board has PC trace capability during ICE mode 5 Save instruction only If checked only instruction fetch will be saved in PC trace buffer else it will save all memory read write in PC trace buffer 6 Tracer buffer size Specify the number of bytes to store operation records 7 Intermediate Specify directory for intermediate files Intermediate files normally are generated during compilation 8 Output Display the terminal file s directory Normally it is the same as the intermediate directory 9 Reset Reset default configuration Generalplus Technology Inc PAGE 398 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Option fl memory files General E Link Section Redefine Hardware BreakPoint PreDownload Be gt J Source Files J Head Files Category General D LC External Depen CC CRIRE APPDIR xasm16 APPDIR dink16 i Cfla ISA Selector sa d Pointer g Near Pointer C Far Pointer M all Warnings On r Optimizations Disable Debug DI CFLAG 5 gstabs Wall ASFLAG Lidd Las TI 1 CC Specify the C
377. on SRC_AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_SRC_AddrH2 0x7B94 DMA Source High Address Register 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SRC_AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_SRC_AddrH3 0x7B9C DMA Source High Address Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 4 3 2 1 0 Function SRG_AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 P DMA TAR AddrHO 0x7B85 DMA Target High Address Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR_AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_TAR_AddrH1 0x7B8D DMA Target High Address Register 1 Bit 15 14 13 12 4 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA TAR AddrH2 0x7B95 DMA Target High Address Register 2 Bit 154 14 134 124 11 10 9 8 7 6 5 4 3 2 1 0 Function 3 TAR_AddrH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA TAR AddrH3 0x7B9D DMA Target High Address Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR AddrH
378. on S USBD_FAR files A General Option Link Redefine Hardware BreakPoint PreDownload Be_4 2 rig Obj amp Lib modules merged section ier sim C Program Files Sunplus unSP ID SectionName RoM RAM C Program Files Sunplus unSP IDI 0 DE D spl162002 FPGA testcode USB 9AAG 222 Resourc D spl162002 FPGA testcode USB System D spl162002 FPGA testcode USB USED F D spl162002 FPGA testcode USB a USB D spl162002 FPGA testcode USB ze SDC lt gt Sy Head Files Non merged section diverh Esectionneme rom ram Parent F5_Conl USB_Descriptor_ORAM_Sect 1000 USB Initial obj GPL162 USB Descriptor ORAM Sect 0 USB Initial obj GPL162 ISR_TEXT 8009 isr obj Nand h Ip TEXT 0 ist obj NandCo EPO Data Stage RAM Sect 220 EPO Data Stage obj Resourc EPO Data Stage RAM Sect EPO Data Stage obj SDCDriv MISA ARAM Section 1 LISA Initial ahi lt USB_RA USBD_F vfs h 01 External Dei Y lt gt Note Since this is a forced setting programmers must avoid the location overlap of programs and resources After a program is compiled and linked a lik file is produced The lik file includes the following information obj resource and the definition of section link We can allocate all resource and section location in the lik fie manually See the following example for details Generalplus Technology Inc PAGE 309 V1 0 Dec 20 2006 G Generalplus Align
379. ondition 10 5 I Reserved R W De bounce enable Note Before CPU goes to wait halt or sleep mode this control bit must be always set to 1 once the touch panel interface is enabled TPEN 1 Otherwise touch panel operation might be failed sometime 0 Disabled 1 Enabled pz Reeva NS 1 0 DBTSEL De bounce timing select default 00 00 de bounce by SYSCLK 1024 01 de bounce by SYSCLK 2048 10 de bounce by SYSCLK 4096 11 de bounce by SYSCLK 8192 P HQADC Ctrl 0x7970 High Quality ADC control Bit 15114113112 11 10 9 8 7 6 5 4 3 2 1 0 Function ADVOR ENHP DIV REC MONO BOOST INMODE PWADL PWADR MICBIAS ADMCLK Default 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 0 15 14 Reserved 13 12 ADVOR HQADG input limitrange select ENHP R W HQADC High Pass filter enable register When HQADC recording is used this bit need be set to 1 Record Sample Rate Control Register After the initialization of the HQADC the HQADC will output recorded data When users do not need to sample data in in 48KHz sampling rate such high sampling rate this register can be used for reducing the sample rate of recording This is done by skipping the recorded data we dont 10 8 DIVSREC 7 MONO RW Mono Record Control Register This bit is to choose the monophonic PAGE 228 need Generalplus Technology Inc
380. only one interrupt event is valid on the control bits P TimerX Ctrl bit 15 14 at one time either up counter overflow interrupt or capture event interrupt Comparison mode In comparison mode the value to be compared with the 16 bit timer counter registers is stored in CCP Register The preloaded value is reloaded to a 16 bit timer counter as well as the interrupt flag is set if they are matched The corresponding PortB 2 0 I O pin is configured as an OUTPUT pin automatically when comparison mode is set Note that in this mode the overflow of 16 bit timer counter will reload the preloaded value Generalplus Technology Inc PAGE 70 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide CCP C A h Xp RTB 2 Timer C A 16 bit FORTRON Preload Register Re CPU Interrupt IRQ4 Timer C A Enable Control bit f Timer C A Timer C A 16 bit Up Count Comparison amp Timer C A 16 bti Clock Source Register Trigger Logic CCP Register Up Counting start from the value in 16 bit Timer Preload Register Timer C A Comparison Mode Function Diagram When TimerA or TimerB is configured as comparison mode P TimerX CCP Ctrl bit 15 14 10 programmers can enable disable clear and read status of the corresponding comparison event interrupt by accessing P TimerX Ctrl bit 15 14 At this time timerA TimerB or timerC up counter overflow interrupt will have n
381. ould be set to power down mode 10 8 Ramp Up and Ramp Down As we know middle value of speech file is 0x8000 first PCM data of speech file usually starts with middle level 0x8000 The mute level on DAC mode is 0x0000 Therefore in order to avoid unexpected sound caused by changing audio output value rapidly from 0x0000 to 0x8000 some smooth methods as known as ramp up and ramp down should be involved NENNEN Generalplus Technology Inc PAGE 108 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 10 9 10 9 1 Ramp up is the operation that changes from mute level to middle level 0x8000 while Ramp down is the operation that changes from middle level 0x8000 to mute level The implementation of ramp up and ramp down is to achieve the target value by gradually adding subtracting with a constant slope from the start value For GPL162002A 162003A the ramp up and ramp down procedure is done by hardware For power on ramp up procedure programmers should turn on DAC power 0x78FD b 3 2 control first and wait it stable and then turn on headphone power 0x78FE b 1 0 For power down ramp down procedure programmers should turn off headphone power 0x78FE b 1 0 and wait it power down and then turn off DAC power 0x78FD b 3 2 3D EQ AC parameter reference setup Generalplus provides some 3D and EQ AC parameters for reference Please refer to the tables below for details EQ AC
382. pe Description Condition Generalplus Technology Inc PAGE 205 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition Daddr RAW Device Address Write the device address to these bits that host wants to access P_USBH_DveEP 0x7B05 USB Device Endpoint Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DEP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function type Description Condition is Reseed 3 0 DEP R W Device Endpoint Write the device endpoint to these bits that host wants to access P_USBH_TXCount 0x7B06 USB Host Transmit Count Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function gt TXC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition psr Resne VO TXC R W Host Transmitting Count Write the number of data to these bits that host wants to transmit P USBH RXCount 0x7B07 USB Host Receive Count Register Bit 15 14 113 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RXC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 un Reserved R W Host Receiving Count The number o
383. plus Function Description GPL162002A 162003A Programming Guide Condition 16 7 Program Example Voice Record on Microphone channel amp Touch panel Int off r1 0x0dc1 P_HQADC_ Ctrl r1 R1 0xc100 P_ASADC_Ctri r1 R1 D ADC Setup R1 0xc080 P_ADC_Setup r1 r1 0xc000 P_MADC_Ctrl r1 r1 0x2810 P_TP_Ctrl r1 r1 0x0080 P_INT_Priority1 r1 r2 5 ds r2 r3 0x0000 call F_DelayADCStable fiq on irq on ri P ADC Setup r1 r1 Ox0004 P ADC Setup r1 r1 P MADC Ctrl r1 0x040 P_MADC_Ctri r1 Call K_WaitKeyTrigger decrease 1 5dB on each 11101 31 5 dB 11110 33 dB 11111 oo dB mute J Set 8KHz sampling rate enable AD clock Istero mode RL channel power on enable auto sample intrrupt FIFO level 8 llenable HQADC enable SAR ADC llenable SAR AD vonversion ready interrupt enable touch panel interface operation mode X channel J Wait for ADC bias voltage stable H Start Auto Sample Operation start SAR AD converter H Wait for key trigger to stop voice recoding Generalplus Technology Inc PAGE 232 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide _FIQ push r1 to sp r1 P_INT_Status1 r1 r1 amp 0x0080 jz L_EndAutoSample ri P_ASADC_ Data J Get 8 ADC acquired data from FIFO D r3 r1 r1 P_ASADC_Data D r3 r1 r1 P_ASADC Data D r3 r1 r1
384. plus GPL162002A 162003A Programming Guide P_USBD_BOData 0x7B35 USB Bulk OUT Data Register Bit 151 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function BODATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_INTINData 0x7B36 USB Interrupt IN Data Register Bit 151 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function INTINDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P USBD NullPkt 0x7358 USB Null Packet Register Bit 15114113112111110191 8171615141 3 2 1 0 Function 1 HJIN_NULLPKTIBI NULLPKTJEPO NULLPKT Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_EPEvent 0x7B37 USB Endpoint Event Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IINNA INPR BONA BOPR BOPE BINA BIPC BIPR EOSNA EOSENJEOINNA EOINPR EOONA EOOPR EOOPE EOSPR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_GLOINT 0x7B38 USB Global Interrupt Register Bit 15 14 13 12 111 14104 9 8 7 6 5 4 3 2 1 0 Function IDMA STANDARD POWER INT BO BI EPO Default O 0 0 0 0 0400 0 0 0 0 0 0 0 0 P_USBD_INTEN 0x7B39 USB Interrupt Enable Register Bit 15 44 13 12 11 10 9 8 7 6 5 4 3 2 1 0
385. r to the above table register will latch setup value into I O PortB VO port configuration data register Similarly executing the read and function operation in this register will read the status from I O PortB external pad Generalplus Technology Inc PAGE 49 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P IOB Buffer 0x7869 IOB Buffer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOBBUF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 IOBBUF R W Executing the read operation in this IOBBUF R register will read the setup value from I O IOBDATA W PortB data register which is previously IOBBUF W latched by IOBDATA writing operation P IOB Dir 0x786A IOB Direction Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IOBDIR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description condition 15 0 IOBDIR R W This control register sets the direction of I O Refer to the above table PortB In addition the direction setup value VO port configuration can be read back from the same control and function register P IOB Attrib 0x786B IOB Attribution Register Bit 15 14 113 12 41 510 9 8 7 6 5 4 3 2 1 0 Function IOBATT Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
386. r when SMART is 1 and a key is pressed If IEN in P KS Ctrl is 1 IRQ6 or FIQ will be triggered depending on the setting of P INT Priority2 The manual mode is similar to auto mode except the trigger source needs to write 1 to STRSCAN in P KS Ctrl register The scan process is the the same as the auto mode It should be noted when the BY in P KS Ctrl is 1 any trigger event including the manual trigger or the auto trigger is invalid and will be ignored 21 6 Automatically Detect Key Process The key scan controller can automatically detect if any key is pressed after a key scan process is complete To enable this function programmers should write 1 to SMART in P KS Ctrl After the function is enabled the INT in P KS Ctrl will be set only when a key is pressed This will reduce the firmware loading for key scan function Generalplus Technology Inc PAGE 297 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 21 7 Key Scan Control Pin Configuration Name 1 0 Description Keyout 7 0 O The keyout is through IOA 7 0 Keyin 7 0 The keyin is through IOA 15 8 21 8 Control Register Key Scan Register Summary Table Name Address Description P KS Ctrl 0x7BC0 Key Scan Control Register P_KS Ctrl 0x7BCO Key Scan Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3121110 Function INT C IEN AUTO FIXSTIME INV SMART STRSCAN BY STOP B74OFF B310FF BOOFF
387. ramming Guide Bit Function Type Description Condition 15 0 VOL_3D_L R W The volume control register of left channel in 0000h Mute 3D module FFFFh maximum P DAC ACCDOUTL Ox7BFE 3D EQ AC Parameter Data Output Low Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DATAOUT 15 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TE 15 0 DATAOUT This is to read the 3D or EQ AC parameter This data will be valid after RDY of Ox7BFO is 1 P_DAC_ACCDOUTH 0x7BFF 3D EQ AC Parameter Data Output High Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DATAOUT 23 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 use Rested Aa i 7 0 DATAOUT This data will be valid after RDY of Ox7BFO becomes 1 In 3D mode programmers do not need to fill any value in this register since the parameter is 16 bit 10 7 Mute level In DAC mode the mute level is Ox0000 In order to make sound complete silence Generalplus recommends programmers should make both channelA and channelB audio output value to mute level In addition to completely shut down audio output module on GPL162002A 162003A very low power consumption both channelA and channelB enable control bits P CHA Ctrl bit3 and P CHB Ctrl bit13 should be clear to 0 and DAC power and headphone power sh
388. rdware horizontal and vertical scrolling capability LCD Control Pin Configuration Description O Frame modulation signal shared with GPIO PortCO Frame Rate signal shared with GPIO PortC1 Line Scan signal shared with GPIO PortC2 Shifting clock signal shared with GPIO PortC3 LCD Data 0 shared with PortAO LCD Data 1 shared with PortA1 LCD Data 2 shared with PortA2 LCD Data 3 shared with PortA3 LCD Data 4 shared with PortA4 LCD Data 5 shared with PortA5 LCD Data 6 shared with PortA6 LCD Data 7 shared with PortA7 The LCDFM LCDFP LCDLP and LCDCP are synchronous signals used to transfer LCD display data from GPL162002A 162003A to GPLDs or SPLCs The LCDD 7 0 is a data port and responsible for carrying transferred LCD data Generalplus Technology Inc PAGE 113 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 11 3 LCD Buffer GPL162002A 162003A allows programmers to locate a LCD buffer inside entire 64M word addressing range of u nSP CPU n other words programmers are able to define any area within 64M word addressing field as a LCD buffer Certainly the area defined as a LCD buffer can be SRAM ROM or Flash or can also be internal RAM The control registers P LCD Buffer HighAdr and P LCD Buffer LowAdr define the start address of LCD buffer In addition different LCD pages LCD buffer can be easily switched by programming the LCD sta
389. re if the transmitting interrupt enable bit is set to 1 and there is no data in the transmitter This flag is cleared to 0 by performing a single write to the transmit data register P_UARTIrDA_Data Receive Timeout Interrupt Flag Read 0 Not Occurred This bit is set to 1 by hardware if the Read 1 Occurred receiving timeout interrupt is asserted When receiving FIFO is not empty and no further data is received over a 32 bit Generalplus Technology Inc PAGE 161 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide period This interrupt flag is cleared to 0 by hardware when the FIFO becomes empty by reading all data or by reading the holding register ize Reseed 7 TXEF Transmit FIFO Empty Flag If FIFO is enabled The meaning of this bit depends on the Read 0 no in TX FIFO gt 0 state of the FEN control bit Read 1 no in TX FIFO 0 For FIFO is enabled 2 depth FEN 1 If FIFO is disabled This bit is set to 1 when the Read 0 TX buffer is not empty transmitting FIFO is empty Read 1 TX buffer is empty For FIFO is disabled 1 depth FEN 0 This bit is set to 1 when the transmitting hold register is empty Note that this flag is read only hardware will set or clear this flag automatically RXFF Receive FIFO Full Flag If FIFO is enabled The meaning of this bit depends on the Read 0 no in RX FIFO lt 8 state ofthe FEN control bit
390. re or comparison event 0 IRQ4 overflow interrupt priority 1 FIQ KSIP Key Scan Interrupt Priority 0 IRQ6 1 N ol Reseed 0000000 pee l1 1 FIQ q et 1 FIQ NAND R W NAND Flash Controller Interruptypriority IRQ5 1 FIQ ie pe IR P_MINT_Ctrl 0x78A8 Miscellaneous Interrupt Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 312 1 0 Function KC2IF KC2EN KC1IF KC1EN KCOIF KCOEN EXTBIS EXTAIS EXTBEN EXTAEN Default 0 0 0 0 0 0 0000 0 0 1 0 0 0 15 KC2IF R W Key change 2 Interrupt Flag Read 0 Not Occurred If this bit is set to 1 IOB2 key change Read 1 Occurred Interrupt happens Write 0 No Effect Write 1 Clear the flag KC2EN R W Key change 2 Interrupt Enable 07 Disabled If this bit is set to 1 and bit9 KCEN in 1 Enabled P Clock Ctrl is set to 1 IOB2 key change Interrupt is enabled KC1IF R W Key change 1 Interrupt Flag Read 0 Not Occurred If this bit is set to 1 IOB1 key change Read 1 Occurred Interrupt happens Write 0 No Effect Write 17 Clear the flag KC1EN R W Key change 1 Interrupt Enable 07 Disabled If this bit is set to 1 and bit9 KCEN in 1 Enabled P Clock Ctrl is set to 1 IOB1 key change Interrupt is enabled KCOIF R W Key change O0 Interrupt Flag Read 0 Not Occurred If this bit is set to 1 IOBO key change Read 1 Occurred Generalplus Technology
391. rent Pattern Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TRANSPAT Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 TRANSPAT R W Transparent Pattern of DMA Channel This register is used to determine the transparent pattern in DMA transfer When TRANSPEN 0x7B87 b12 set to 1 and DMA read date matched the value stored in this register the read data will not be written to the destination address P_DMA_LINELENGTH 0x7BBD DMA Line Length Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LINELENGTH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 10 Reserved bo LINELENGTH Line Length of DMA Sprite ll Generalplus Technology Inc PAGE 277 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide The following diagram show the memory mapping when sprite mode is turned on LCD Frame Buffer DMASAR DMASAR LINELENGTH Transfer DMASAR DMASAR SPRISIZE DMASAR DMATCR P_DMA_SS 0x7BBE DMA Source Select Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DMA_SS3 DMA SS2 DMA SS1 DMA_SSO Init 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Bit Function Description Condition 15 12 DMA SS3 R W DMA Channel 3 Source Select R W 0x0 USB
392. ress Bus 000 4 mA This register is used to control the driving 001 4 mA capability of address bus 010 8 mA 011 8 mA 100 12 mA 101 12 mA 110 16 mA 111 16 mA Generalplus Technology Inc PAGE 22 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 3 7 Special Note GPL162002A 162003A supports three boot modes for details please refer to Memory Chapter To select which boot mode is used GPL162002A 162003A will detect pins BMO and BM1 at power on or hardware reset cycle When BM 1 0 00 the system will boot from external MCSO memory When BM 1 0 10 the system will boot from internal ROM When BM 1 0 11 or 01 the system will boot form external EMUCE Memory instead of internal ROM Generalplus Technology Inc PAGE 23 V1 0 Dec 20 2006 G 4 2 4 3 Generalplus GPL162002A 162003A Programming Guide 4 Memory 4 1 Introduction GPL 162002A 162003A has a built in internal ROM SRAM and a NOR type flash memory controller with AMBA like interface There are five chip select pins and one chip select pin for emulation each memory device has 256 pages and each page is 64K words So the controller can totally support up to 80M words for NOR type flash memories In addition to the ROM SRAM NOR type flash memory controller the NAND type flash memory controller for 8 bits or 16 bits NAND type flash memories and SM Smart Media flash memories
393. rformed in various formats 18 2 2 Data Transfer Format Every byte placed on the SDA line should be eight bits in length The number of bytes which can be transmitted per transfer is unlimited The first byte following a Start condition should have the address field The address field can be transmitted by the master when the I2C bus is operating in master mode Each byte should be followed by an acknowledgement ACK bit The MSB bit of the serial data and addresses are always sent first Write mode with 7 bits address Slave Address 7bits DATA 1Byte ale s Write Data Transferred Data Acknowledge Generalplus Technology Inc PAGE 250 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Read mode with 7 bits address Slave Address 7 bits DATA ATP S Read Data Transferred Data Acknowledge Data transfer on the I2C bus w E eee UA Le MSB Acknowledgement Acknowledgement I Signal from Receiver Signal from Receiver H c BAE L PUR T m i x aech T basses Byte Complete Intern Clock Line Held Low While within Receiver Interrupts are Serviced 18 2 3 Acknowledgement Signal Transmission To finish a one byte transfer operation successfully the receiver should send an ACK bit to the transmitter The ACK pulse should occur at the 9 Clock of the SCL line Eight clocks are required for the one byte data transfer The mast
394. rite signals to access NAND flash In addition a DMA channel is also provided to speed up NAND Flash data access GPL162002A 162003A supports 8 bit or 16 bit NAND type flash data access along with hardware ECC Error Correction Code and checksum Support the an interface to access 8 bit or 16 bit NAND flash memory Support hardware ECC amp checksum Programmable setup hold timing for accessing NAND Flash Control Pin Configuration Name UO Description NFWEB NFOEB Write Enable shared with GPIO PortB5 O O Reag Enable shatedwith GPIO Ponse NrcLE o N command Lac Enable shared with GPIOPortB7 NrALE 9 Addreaa Latch Enable shared with GPIO Porse MES Zi R adyBusyOugut shared with GPIO Porto U UU U Control Register Nand Flash Control Register Summary Table Name Address Description P NF Ctrl 0x7850 NAND Flash Control Register P NF CMD P NF Add P NF AddrH P NF Data P NF INT Ch P ECC Ctr P ECC LPRL LB P ECC LPRH LB P ECC CPR LB P ECC LPR CKL LB P ECC LPR CKH LB Generalplus Technology Inc PAGE 235 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Name Address Description P ECC CPCKR LB 0x785D ECC Low Byte Column Parity Check Register P ECC ERRO LB 0x785E ECC Low Byte Error FlagO P ECC ERR1 LB 0x785F ECC Low Byte Error Flag1 P ECC LPRL HB 0x7848 ECC High Byte
395. rt address register Programmers can define more than one LCD buffer in the system In this case the switch operation between different LCD pages can accelerate frames updating The definition of LCD buffer size is implied in two control registers P LCD Common and P LCD Segment The maximum number of common lines horizontal line to be supported is 320 pixels and the maximum number of segment lines vertical line is also 320 pixels as well In most cases the size of LCD buffer equals to P LCD Common 1 x P LCD Segment 1 x bpp bits where bpp represents bit per pixel GPL162002A 162003A also supports virtual page function that allows programmers to define a virtual LCD buffer larger than actual viewable size actual LCD size In this case programmers can easily scroll actual LCD display screen horizontally and vertically on the full virtual page by simply defining P LCD Buffer Offset control register and modifying the following two control registers P LCD Buffer HighAdr and P LCD Buffer LowAdr The maximum width in a virtual page is 1024 pixels as being indicated in the following diagram Maximum 1024 Pixel gt Actual LCD Display Area Phyical Whole Display Area Logical Generalplus Technology Inc PAGE 114 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 11 4 LCD Palette Any color on a pixel can be combined from three elements red green a
396. rupt R W Source Fixing Address If this bit is set to 1 the source address will be fixed when data is read from the 0x07 Request coming from a peripheral whose data need to be read 0x12 Request coming from a peripheral whose data need tobe written 0x02 Single transfer mode 0x1 Demand transfer mode 0x07 Target is 16 bits mode 0x1 Target is 8 bits mode 0x07 Source is 16 bits mode 0x17 Source is 8 bits mode 00 2 Memory to Memory 012 Memory to IO 107 IO to Memory 112 IO to lO Write 1 Reset control register 0 Disable DMA interrupt 1 Enable DMA interrupt 0 Increase decrease source address 1 Fix source address If this bit 1 and if source address DF R W Destination Fixing Address 0 7 Increase decrease If this bit is set to 1 the destination destination address Generalplus Technology Inc PAGE 269 V1 0 Dec 20 2006 G Generalplus Function Type Description GPL162002A 162003A Programming Guide Condition address will be fixed when data is written to the destination address R W Source Address Direction If this bit is set to 1 the source address will be decreased when data is read from Note that this bit will be valid only when SF is 0 R W Destination Address Direction If this bit is set to 1 the destination the source address address will be decreased when data is written to the destination a
397. s P LCD Palette Ctrl r1 r1 0x2100 P LCD Ctrl r1 Data width 4 bit call F_Fill256CPalette O Generalplus Technology Inc PAGE 128 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide r1 P LCD Ctri r1 r1 8 0x2000 1 Clear LCDEN bit to O P_LCD_Ctrl r1 call F DelayOneFramelnterval JI Delay one frame interval m Fill palette from Ox7A00 to Ox7AFF r1 P LCD Ctrl r1 r1 0x2000 Set LCDEN bit to 1 P LCD Ctrl r1 retf Note that palette can be modified ONLY when LCDEN control bit is cleared to 0 P LCD Ctrl bit13 0 Generalplus Technology Inc PAGE 129 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Copy 320x240 256 Color Information to both LCD Palette and LCD Buffer IIIIIIIIIIII IIIIIIIIIIIIIIIII FG_Putlmage320x240x256C IIIIIIIIIIIIIIIIIIIIIIII IIIIII L_FillPalette L FillLCDBuffer r1 IR Bitmaplndex r2 T BMPStartAddressTable r2 r1 r2 r2 r1 r2 r2 r2 r2 r2 Isl 4 r2 r2 Isl 4 r2 r2 Isl 2 ds r2 H Setup Data Segment ri r1 8 r4 P_LCD Palette Fill LCD Palette r3 DS r1 r4 r3 cmp 14 P_LCD_Palette 256 jne L FillPalette r2 0x0000 r4 ds II Fill LCD Buffer at Ox3 0000 ds r4 r3 DS r1 r4 ds ds 3 DS r2 r3 cmp r2 320 240 8 16 jne L_FillLCDBuffer retf Generalplus Technology Inc PAGE 130 V1 0
398. s Write 1 Clear the flag Programmers can use this register to determine the setting of LINEGR When top overflow occurs programmers need to reduce LINEGR 14 ADROVN RW HQADC Right Channel Line in Bottom Read 0 Not Occurred Overflow interrupt flag Read 1 Occurred This bit is set to 1 by hardware if HQADC Write 0 No effect right channel _ line in bottom overflow Write 1 Clear the flag occurs Programmers can use this register to determine the setting of LINEGR When bottom overflow occurs programmers need to reduce LINEGR 13 JADROV_I R W HQADC Right Channel Overflow Interrup 0 Disable Enable 1 Enable If this bit is set to 1 and at the time when ADROVP or ADVRON is set to 1 hardware will issue an IRQ1 or FIQ to CPU To select between IRQ1 and FIQ please refer to Chapter Interrupt 126 Reeea j Ces LINEGR R W The gain setting of Right Channel Line in 00000 12 dB 00001 10 5 dB 00010 9 dB 00011 7 5 dB 00100 6 dB decrease 1 5dB on each Generalplus Technology Inc PAGE 230 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Type Description Condition level 11101 31 5 dB 11110 33 dB 11111 oo dB mute P_HQADC_LGAIN 0x7973 High Quality ADC LINEINL gain setting Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ADLOVP ADLOVN
399. s this flag is set Write O No Effect to 1 by hardware Write 17 Clear the flag 14 TMBCIE R W TimebaseC Interrupt enable 0 Disabled If this bit is set to 1 and TimeBaseC 1 Enabled interrupt occurs hardware will issue an IRQ6 to CPU If this bit is cleared to 0 this interrupt will be masked Generalplus suggests programmers do not use TimbaseC as halt sleep mode wake up source because the TimebaseC interrupt occur occurs more quickly than the time that CPU wakes up from halt sleep mode As a result the TimebaseC interrupt flag will not be held from halt sleep wake up 13 TMBCEN R W TimeBaseC Module Enable 07 Disabled If this bit is set to 1 TimeBaseC module will 12 Enabled be enabled on the contrary it will be disabled for consumption Generalplus Technology Inc PAGE 82 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide L consideration j 122 Reseed PE 1 0 TMBCS R W TimebaseC Frequency Selection 00 128Hz There are four frequency sources on 01 256Hz TimebaseC 128Hz 256Hz 512Hz and 10 512Hz 1024Hz These two control bits are to 11 1024Hz select one of four frequencies P TimeBase Reset 0x78B8 TimeBase Reset Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMCCR Default Bit Function Type Description D Condition 15 0 T
400. s Technology Inc PAGE 253 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 18 3 2 Master Receive Mode Start Change to Master Receive Mode Write Slave Address to P I2C Data Write 0xB0 to P I2C Status Data in P I2C Data is Transmitted Interrupt Pending ACK Received N Y ead Data from P DC Data Write 0x90 to P DC Status Meer BE sae Clear Pending Interrupt Clear Pending Interrupt lt q _ SDA Shift to P DC Data Wait until Controller IDLE l Stop Generalplus Technology Inc PAGE 254 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 18 3 3 Slave Transmit Mode Start we Write Slave Address to P_I2C_Addr v Change to Slave Transmit Mode N Detect Start Signal w LY SDA shift P DC Data N Y IAR match with P DC Data Y _ Interrupt Pending Y Write Data to P DC Data lt Y Clear Pending Interrupt 4 Y Data in P_I2C_Data is Transmitted Y Interrupt Pending ACK Received N Stop H Generalplus Technology Inc PAGE 255 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 18 3 4 Slave Receive Mode Start Wri
401. s clock sorce this state very short and halt or sleep state will entered 110 halt state Use 32768Hz as clock Source only a little logic is active 111 sleep state No clock source Wake up by key change Address Data Bus Driving Strength Control To meet the various requirements of external memory in GPL162002A 162003A it is capable of adjusting the driving ability of address and data bus When external memory bus loading is small reducing the driving ability will reduce the bouncing time of signals When external memory loading is large increasing the driving ability willreduce the signal delay P_AD Driving 0x781F Address Data Driving Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3121110 Function D POEF D PH D SR D SMT D DRIVE A SR A SMT A DRIVE Default 0 0 0 0 0 0 0 100 0 0 0 0 0 1 Bit Function Type Description Condition 15 D POFF R W Data Bus Automatic Pull High Low Turn Off O Automatic function is on This bit is used to control the automatic pull Address bus will be tied to high high low function of data bus when entering lat the same time HALT mode or STANDBY mode This bit 1 Automatic function is off also controls the state of address bus when Address bus will not be tied to entering HALT mode or STANDBY mode high E Data Bus Automatic Pull High Low Selection 0 Pull low data bus when This bit is use
402. set CPU OFF Sleep Mode OFF System reset When entering the halt mode the system will disable PLL automatically so that it doesn t need to change system clock to 32768 Hz And the system will run at the clock that set before entering halt mode when waking up from halt mode If the system enters halt mode programmers can disable RTC to save more power To determine CPU is whether power on reset or wakeup from halt mode refer to chapter Interrupt Generalplus Technology Inc PAGE 19 V1 0 Dec 20 2006 G Generalplus P WAIT Bit Function Default GPL162002A 162003A Programming Guide 0x780C Wait Mode Entrance Register 151 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WAIT 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition _ 15 0 WAIT W Wait Mode Entrance Register Write 0x5005 to enter wait mode stop CPUCLK source only but SYSCLK and 32768Hz are still valid When writing 0x5005 to control register 0x780C to enter wait mode programmers have to add at least 6 nop instructions to make sure the GPL162002A 162003A enter wait mode successfully P_HALT Bit Function Default 0x780D Halt Mode Entrance Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HALT Bit Functon Type Description Condition _ 15 0 HALT W Halt Mode Entrance Register Write Ox500A to enter halt mode s
403. set Event Flag Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function WDG WDE MPE LVR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P Clock Ctrl 0x7807 System Clock Control Register Bit 15 14 13 12 11 10 9 8171615 4 3 21110 Function FAST C32K IWEAK C32KOFF KCEN DAPLLEN CLK96M CLKDIV Default 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 313 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_CLK_CtrlO 0x7804 Peripheral Clock Control RegisterO Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Clock Source 15 0 Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P CLK CtrH 0x7805 Peripheral Clock Control Register1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Clock Source 31 16 Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P PLLN 0x7817 Fast PLL output divider register Bit 15 14
404. setting Each corresponding bit in these three control registers should be given a value to set one bit configuration For example suppose PortA 0 is used as an input port with internal pull low resistors The bitO in PortA DIRECTION ATTRIBUTION and DATA control registers should be given 000 in binary If PortA 1 is used as a floating input port with wake up functions the bit1 in PortA DIRECTION ATTRIBUTION and DATA control registers should be given 010 in binary Reading operation on I O DATA control registers will read status from external UO pads On the other hand GPL162002A 162003A also provides a control register UO BUFFER This control register holds the setting data value that is previously written into I O DATA control register Therefore programmers do not need an extra variable 1 word SRAM to store hold the previous setting on DATA control register General Purpose I Os Function Table Direction Attribution Data n E e 5 Description Register Register Register o o o 4 FPulow Input with pull low lo o 1 Purin Input with pull high m Ir Float EDI Impendence 0 F L Float High Impendence RSS content of buffer register SR content of buffer register OutputLow Low Outputwithbuffer With buffer j Output High Output with buffer Default is input mode with pull low state Only PortA and PortB in the state of 000 001 and 010
405. signated parameter in this register before writing to P DAC ACCREQ register In 3D mode programmers do not need to fill any value in this register since the parameter is 16 bit P DAC EFF Ctrl Ox7BF3 3D EQ AC Control register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 140 Function 3DEN 2CH HP EQEN BPEQ BPAC DEPTH_3D Default 0 0 0 0 0 0 0 0 000 00 O 0 0 0 Function Type Description Condition 3D Module Enable Control 0 Disable Before enabling 3D module 2CH HP DEPTH 3D 1 Enable and 3D filter parameter must be set correctly 1 2 channel mode 1 Headphone output 12 EQEN R W EQ AC Module Enable Control 0 Disable Before enabling 1 EQ AC module the EQ AC 1 Enable parameter must be set correctly 1 Bypass EE Pi 1 Bypass p pu 18 0 DEPTH 3D RAW aD Surround Depth Control _ P_DAC_ACTHRESL 0x7BF4 AC anti clip Threshold Low Register Bit 15 14 13 12 11 1100 9 81 7 6 5 4 3 2 110 Function ACTHRES 15 0 Default 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition Deg ACTHRES RW AC Threshold Register 15 0 A O Generalplus Technology Inc PAGE 105 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_DAC_ACTHRESH 0x7BF5 AC anti clip Threshold High Register Bit 151 14 13 12 11 10
406. sked To select between IRQ5 and FIQ please refer to Chapter Interrupt 12 _ Reserved s 11 ADRAEN RW INAND Flash memory fourth cycle A25 A32 address 0 disable enable 1 enable If NAND Flash uses 32 bit address The ADR4EN and ADR3EN both need to be set to 1 a NAND Flash memory third cycle A17 A24 address enable 1 enable AAA enable NS LS enable leal Reserved _____ e NAND Flash ECC amp Checksum GPL162002A 162003A internal ECC 8 ckecksum calculation logic can be controlled by software via P_ECC_Ctrl bit2 When it is set to 0 it will calculate read write data appears on the NAND flash data bus The value after ECC will be output to the ECC logic P ECC LPRL LB P ECC LPRH LB P ECC CPR LB P ECC LPRL HB P ECC LPRH HB and P ECC CPR HB in every calculation And value after checksum calculation will be output to P CHECKSUMO LB P CHECKSUM 1 LB P CHECKSUMO HB and P CHECKSUM HB in every calculation In addition because of the nature of ECC and checksum logic only after exactly 512 bytes 256 words in 8 bit type Nand flash and 256 words 512 bytes in 16 bit type Nand flash of data are given to the ECC and check sum logic the calculation result is valid To guarantee a correct ECC result users must reset P ECC Ctrl bitO by filling 1 at the beginning of reading writing a page When the NAND flash connected to GPL162002A 162003A is 8 bit type only the registers 0x7858 0x785F ar
407. ster Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RST OD1 ODO ID1 IDO Setup SOF Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REESEN R W Reset Signal 1 Generate reset signal The RESET signaling is not terminated by O Stop reset signal hardware automatically CPU must explicitly write 0 to this bit to stop signaling RESET instead Out Data1 Transfer Write 1 to initiate OUT DATA transfer This bit is cleared automatically if the transfer is completed Out DataO Transfer Write 1 to initiate OUT DATAO transfer This bit is cleared automatically if the transfer is completed In Data1 Transfer Write 1 to initiate IN DATA1 transfer This bit is cleared automatically if the transfer is completed In DataO Transfer Write 1 to initiate IN DATAO transfer This bit is cleared automatically if the transfer is completed Setup Transfer Write 1 to initiate SETUP transfer This bit is cleared automatically if the transfer is completed SOF Transfer Write 1 to initiate SOF transfer SOF is generated by software This bit is cleared automatically if the transfer is completed P_USBH_DveAddr 0x7B04 USB Device Address Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DAddr Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Ty
408. ster Slave TX RX Mode Selection These two bits are used to select the master or slave transmit or receive mode of the I2C bus Note Under following 2 kinds of situations the DC bus will change to slave receive mode automatically 1 In slave mode receive slave address is 0x00 In master mode detects bus arbitration fail I2C Bus Busy Signal Status This bit is used to indicate if the 12C bus is busy or not I2C Bus Data Output Enable If this bit is set to 1 I2C data output is enabled Or the data output is disabled I2C Bus Arbitration Procedure Status Flag This bit is used to indicate if the arbitration procedure is okay or not 00 Slave Receive Mode 012 Slave Transmit Mode 10 7 Master Receive Mode 117 Master Transmit Mode Read 0 Not Busy Read 1 Busy Write O DC Bus interface STOP signal generation Write 1 I2C Bus interface START signal generation 0 Disable RX TX 1 Enable RX TX 0 okay Bus arbitration status 1 Bus arbitration failed gt ss R I2C Bus Address as Slave Status Flag 0 START STOP condition Generalplus Technology Inc PAGE 258 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Type Description Condition was generated 1 Received slave address matches the address value in the P I2C Addr I2C Bus Address Zero Status Flag 0 START STOP condition was generated 1 Received slave a
409. t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 Reserved 7 0 Data R Scan data is read from IOA 15 8 when IOA 2 is active This register stores the scan data read from IOA 15 8 when the IOA 7 0 is set as 0500000100 KSINV 0 or 0b11111011 KSINV 1 The data will be preserved until the next scan process happens P_KS Data3 0x7BCB Sample Data of Line IOA 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data3 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 Reserved 7 0 Data 2 Scan data is read from IOA 15 8 when IOA 3 is active fF This register stores the scan data read from IOA 15 8 when the IOA 7 0 is set as 0500001000 KSINV 0 or 0611170111 KSINV 1 The data will be preserved until the next scan process happens P KS Data4 Ox7BCC Sample Data of Line IOA 4 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Data4 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 Reserved 7 0 Daa4 R Scan data is read from IOA 15 8 when IOA 4 is active _ Generalplus Technology Inc PAGE 301 V1 0 Dec 20 2006 G Generalplus GPL162002A 1
410. t 0x7BOA USB Host Automatic In Transaction Byte Count Register P USBH AutoOutByteCount USB Host Automatic Out Transaction Byte Count Register P USBH AutoTrans USB Host Auto Transfer Register P USBH Status USB Host Status Register P USBH INTF USB Host Interrupt Flag Register P USBH ANTEN USB Host Interrupt Enable Register P USBH StorageRST USB Storage Reset Register P USBH SoftRST USB Software Reset Register Device Plug Out Register P USBH SOFTimer USB SOF Timer Register P USBH FrameNum USB Frame Number Register P USBH OTGConfig USB OTG Configuration Register P USBH VBusSet USB VBUS Set Register P USBH VbusStatus USB VBUS Status Register P USBH INAckCount USB IN ACK Count Register P USBH OutAckCount USB OUT ACK Count Register P USBH RSTAckCount USB Reset ACK Count Register Generalplus Technology Inc PAGE 345 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Name Description P_USBH_Storage1 2 0x7B1A For Debugging P USBD Config 0x7B30 USB Configuration Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function
411. t 154 14 134 122 11 10 9 8 7 6 5 4 3 2 1 0 PIP3_SAL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIPO H START 0x7D19 TFT PIPO Horizontal Start Location in Each Line Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPO H STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP1 H START 0x7D24 TFT PIP1 Horizontal Start Location in Each Line Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIP1 H STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L PAGE 339 V1 0 Dec 20 2006 Generalplus Technology Inc G Generalplus P TFT PIP2 H START 0x7D2F GPL162002A 162003A Programming Guide TFT PIP2 Horizontal Start Location in Each Line Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function PIP2 H STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP3 H START 0x7D3A TFT PIP3 Horizontal Start Location in Each Line Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function PIP3 H STR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIPO_H_END Ox7D1A TFT PIPO Horizontal End Location in Each Line Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Function PIPO H END Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP1 H END 0x7
412. t Option TAB Generate Interrupt Vector Table Uncheck it if users don t want to produce Interrupt Vector Table in the project output Incl de Start Up Code Uncheck it if users don t want to produce the default start up code in the project output Align all resource with Checkitand input the align base if users want to align all resources with a specified align base Generate Initial Table Uncheck it if users don t need an initial table in the project output External Symbol Files Input the other symbol files sym needed for reference link in the current project Library modules Specify and show all library modules included in the current project Generalplus Technology Inc PAGE 400 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Section fl USBD_FAR files General Option Link m a Source Files Obj amp Lib modules C Program Files Sunplus unSP IDI C Program Files Sunplus unSP IDI D ispli620021FPGAltestcodelUSB D ispl162002 FPG ltestcode USE D ispl162002 FPGA testcode USB D ispl162002 FPGA testcode USB D spl162002 FPGA testcode USB lt gt Head Files Non E section 222 ID s lt USB Descriptor ORAM Sect USB_Initial obj GPL1621 USB_Descriptor_ORAM_Sect USB_Initial obj GPL1621 ISR_TEXT isr obj Nand h ISR_TEXT ist obj NandCo EPO Data Stage RAM Sect EPO Data Stage ob Resourc EPO_Data_Stage_RAM_Sect EPO_Data
413. t is 1 and SET_FEATURE command happens Set Address Interrupt Flag The interrupt is set H the enable bit is 1 and SET_ADDRESS command happens Get Configuration Interrupt Flag The interrupt is set if the enable bit is 1 and GET_ CONFIGURATION command happens Set Configuration Interrupt Flag The interrupt is set if the enable bit is 1 and SET_ CONFIGURATION command happens Get Interface Interrupt Flag The interrupt is set if the enable bit is 1 GET_INTERFACE happens and command Set Interface Interrupt Flag The interrupt is set if the enable bit is 1 SET_INTERFACE happens and command PAGE 196 Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_USBD_EPAuto
414. t0 wValue Register Bit 15 14 13 12 4 14 410 9 8 7 6 5 4 3 2 1 0 Function EPOVR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P USBD EPOIR 0x7B49 USB windex Register Bit 154 14 134 122 11 10 9 8 7 6 5 4 3 2 1 0 Function EPOIR Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_EPOLR 0x7B4A USB Endpoint0 wLength Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function EPOLR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_DMAWrtCountL 0x7B50 USB DMA Byte Count Low Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DMAWCL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 349 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_USBD_DMAWrtCountH 0x7B51 USB DMA Byte Count High Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DMAWCH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD DMAACK 0x7B52 USB DMA ACK Count Low Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DMAACKL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_USBD_DMAACK 0x7B53 USB DMA ACK Count High Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function lt DMAACKH Default O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
415. t_Swap r1 r1 P_Byte_Swap cmp r1 0x50FA II Verify Byte Swap jne L_OtherTestError r2 P_Nibble Swap cmp r2 0xAFO5 II Verify Nibble Swap jne L OtherTestError r3 P Bit Reverse cmp r3 0x0A5F II Verify Bit Reverse jne L OtherTestError rA P TwoBit Swap cmp r4 0x9669 J Very 2 bit Reverse jne L OtherTestError L OtherTestError Generalplus Technology Inc PAGE 306 V1 0 Dec 20 2006 G Generalplus 23 1 23 2 Generalplus Technology Inc GPL162002A 162003A Programming Guide 23 E Fuse Option Introduction There are four E Fuse registers in GPL162002A 162003A The value of these four registers can be decided by customers on IC mass production procedure so that users can protect the program by configuring these four registers Specified Register E Fuse Register Summary Table Name address Deserption gt P EFuse DO 0x7C30 E Fuse Data Register 0 P EFuse D1 0x7C31 E Fuse Data Register 1 P EFuse D2 0x7C32 E Fuse Data Register 2 P EFuse D3 0x7C33 E Fuse Data Register 3 P EFuse DO 0x7C30 E Fuse Data Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E DATA 15 0 Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bi Function ype Description Condition Function 15 0 E DATA Kk E fuse data out 15 0 P _ P EFuse_D1 0x7C31 E Fuse Data Register 1 Bit 15 44 143 12 11 10 9 8 7 6 5
416. tage reset or watchdog timeout reset occurs GPL162002 including CPU and all peripheral is reset to initial state excluding SRAM and Palette RAM All the flags return to initial state including reset flag So the resetflags must be recorded to SRAM to avoid disappearance In other words CPU reset is the subset of system reset Watchdog timeout reset When Watchdog timeout reset is activated the value of Axx5 must be written to Watchdog clear register within the period of users definition Otherwise CPU reset occurs Also note that reset target of watchdog timeout can be selected between CPU and system by software 1 bit control register Watchdog mode protection reset When Watchdog timeout reset is activated if the wrong value not Axx5 is written to Watchdog clear register CPU reset will occur Power saving mode protection reset GPL162002A 162003A define three power saving modes Wait Halt and Standby mode When entering power saving mode the Wait Halt or Standby mode control register must be written the corresponding value If the wrong value is written into the control register CPU reset occurs Low voltage reset When the operation voltage is lower than 2 5V the Low voltage reset mechanism will reset system Generalplus Technology Inc PAGE 395 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Power on reset When power is supplied to GPL162002A 162003A from
417. te Slave Address to P_I2C_Addr Change to Slave Receive Mode N Detect Start Signal 3 Y SDA shift P I2C Data N IAR match with P_I2C_Data A Interrupt Pending Read Data From P_I2C_Data Clear Pending Interrupt Y SDA Shift to P_I2C_Data Interrupt Pending Continuous IrI ESA Stop Generalplus Technology Inc PAGE 256 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 18 4 12C Bus Control Pin Configuration UO Description 1 0 I2C Bus SCL input output shared with GPIO PortC12 12C Bus SDA input output shared with GPIO PortC 13 18 5 12C Bus Control Register 12C Register Summary Table Name Address Description P_12C Ctrl 0x7B60 I2C Control Register P_I2C Ctrl 0x7B60 DC Control Register Bit 1511413 12111 1 10 1 9 8 7 6 5 4 3121110 Function ACKEN CLKSEL INTEN INTPEND C TXCLK Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 8 Reserved 7 ACKEN R W DC Bus Acknowledge Enable Bit 0 Disable ACK generation 1 Enable ACK generation CLKSEL R W Source Clock of DC Bus Transmit Clock 0 I2CCLK SysCLK 16 Prescaler Selection Bit 1 I2CCLK SysCLK 512 INTEN 5 R W 12C Bus TX RX Interrupt Enable 0 Disable
418. te transmitting and 8 byte receiving FIFOs Programmable baud rate generator e Independent masking of transmitting FIFO receiving FIFO and receive timeout interrupts False start bit detection e Link break generation and detection e Support normal 3 16 and low power 1 63us bit duration Programmable IrDA TX and RX latency Programmable IrDA TX and RX signal polarity Support Loop Back Testing for system diagnosis or mass production testing 13 2 Structure and Block Diagram Interrupt Control Tx Shift Register Rx Shift Register Tx Controller Rx Controller Baud rate Generator UART IrDA interface Generalplus Technology Inc PAGE 154 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide GPL162002A 162003A contains a module that manipulates both UART and IrDA signals It is impossible to operate transmitting and receiving functions with UART and IrDA at the same time IrDA interface compatible with SIR Serial Infrared level IrDA accompanied with UART Interface is built in GPL162002A 162003A This interface and an external IrDA transceiver module connected via PortC9 and PortC10 implement IrDA physical layer In addition this built in half duplex IrDA interface also provides programmable latency and programmable signal pulse duration 13 3 UART IrDA SIR Frame Scheme UART characteristic frame is depicted in the following diagram o
419. ter LSB P_ECC_LPRH_LB 0x7859 ECC Low Byte Line parity MSB Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LPRH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 LPRH R The ECC Line parity register MSB P ECC CPR LB 0x785A ECC Low Byte Column parity Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function CPR Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 12 Reserved pro cer Le TheEGO Column parity register All 16 bit value of P ECC LPRL LR and P_ECC_LPRH_LB and all 12 bit value of P ECC CPR LB are valid As result when the Nand Flash is chosen as 8 bit type it needs to write low byte and high byte to P NE Data respectively P ECC LPR CKL LB 0x785B ECC Low Byte Line parity Check LSB Register Bit 154 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LPRCKL Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 LPRCKL R W The ECC Line parity Check register LSB P ECC LPR CKH LB 0x785C ECC Low Byte Line parity Check MSB Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function LPRCKH Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
420. ter 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SRC_Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA SRC AddrL1 0x7B89 DMA Source Low Address Register 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SRC Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P DMA SRC AddrL2 0x7B91 DMA Source Low Address Register 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SRC_Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_SRC_AddrL3 0x7B99 DMA Source Low Address Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SRC_Addr Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Description Condition SRC_Addr DMA Source Low Address 15 0 These P_DMA_SRC_AddrLx registers are low address 15 0 registers of sources The value in these registers will be increased decreased when a word is read and when the SF in P DMA Ctrl 7 is O It should be noted if the TD nR DMA Ctrl 11 10 is set as IO to memory or IO to IO mode only the lower 12 bits will be used to issue a peripheral read P DMA TAR AddrLO 0x7B82 DMA Target Low Address Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TAR Addr Init 0 0 0 0 0 0 0 0 0 0 0
421. ter 0 DMA Terminal Counter Low 15 0 Register 0 DMA Source High Address 25 16 Register 0 DMA Target High Address 25 16 Register 0 DMA Terminal Counter High 25 16 Register 0 DMA miscellaneous Control Register 0 DMA Channel Control Register 1 DMA Source Low Address 15 0 Register 1 DMA Target Low Address 15 0 Register 1 DMA Terminal Counter Low 15 0 Register 1 DMA Source High Address 25 16 Register 1 DMA Target High Address 25 16 Register 1 DMA Terminal Counter High 25 16 Register 1 DMA miscellaneous Control Register 1 DMA Channel Control Register 2 DMA Source Low Address 15 0 Register 2 DMA Target Low Address 15 0 Register 2 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Name Address Description P_DMA_TCountL2 0x7B93 DMA Terminal Counter Low 15 0 Register 2 P_DMA_SRC_AddrH2 DMA Source High Address 25 16 Register 2 P_DMA_TAR_AddrH2 DMA Target High Address 25 16 Register 2 P_DMA_TCountH2 DMA Terminal Counter High 25 16 Register 2 P DMA MISC2 0x7B97 DMA miscellaneous Control Register 2 P DMA Ctrl3 0x7B98 DMA Channel Control Register 3 P_DMA_SRC_AddrL3 DMA Source Low Address 15 0 Register 3 P DMA TAR AddrL3 DMA Target Low Address 15 0 Register 3 P DMA TCountL3 DMA Terminal Counter Low 15 0 Register 3 P DMA SRC AddrH3 DMA Source High Address 25 16 Register 3 P DMA TAR AddrH3 DMA Target High Address 25 16 Register 3 P DMA TCountH3 DMA Terminal Counter
422. terrupt UART IrDA Interrupt Serial Peripheral Interface SPI Interrupt LCD Frame Pulse Rising Edge FP Interrupt Touch Panel Interrupt Stylus Tapped Interrupt ADC Auto Sampling FIFO Full Interrupt AD Conversion Ready Interrupt Audio Channel A FIFO Empty Interrupt Audio Channel B FIFO Empty Interrupt External A Interrupt seing or falling edge of IOD12 External B Interrupt rising or falling edge of IOD13 TimerA Up Counter Overflow or Capture or Comparison event Interrupt TimerB Up Counter Overflow or Capture or Comparison event Interrupt TimerC Up Counter Overflow or Capture or Comparison event Interrupt TimerD Up Counter Overflow DMA Transfer Interrupt USB Interrupt I2C Transmit Receive Interrupt NAND Flash FIFO over under flow interrupt SD Controller Interrupt Key Scan Interrupt Audio Channel A FIFO Empty Interrupt P INT Status1 Audio Channel B FIFO Empty Interrupt IRQ1 ADC Auto Sampling FIFO Full Interrupt P INT Status1 AD Conversion Ready Interrupt Touch Panel Interrupt Stylus Tapped Interrupt IRQ2 External A Interrupt rising or falling edge of IOD12 P_INT_Status1 External B Interrupt rising or falling edge of IOD13 Generalplus Technology Inc PAGE 57 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Interrupt Type Possible Peripheral Interrupt Flag Register UART IrDA Interrupt P_INT_Status1 Serial Peripheral Interface SPI Interrupt DM
423. terrupt level occurs hardware will issue Generalplus suggest programmer enable an IRQ3 or FIQ to CPU If this bit is smart interrupt clear function cleared to 0 this interrupt will be masked P SPI Misc b8 Generalplus Technology Inc PAGE 173 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description 1 Condition To select between IRQ3 and FIQ please refer to Chapter Interrupt ise Reserves 7 4 TXFLEV R W Transmit FIFO interrupt level register FIFO Full Interrupt issue timing This register is used to indicate how many 0000 data no in FIFO lt 1 8 empty slots are required when issuing an write is allowed interrupt The larger the value is set the 0001 data no in FIFO lt 7 2 lower the interrupt penalty users have write is allowed since users can write more data in one 0010 data no in FIFO lt 6 3 interrupt write is allowed 0011 data no in FIFO lt 5 4 write is allowed 0100 data no in FIFO lt 4 5 write is allowed 0101 data no in FIFO lt 3 6 write is allowed 0110 data no in FIFO lt 2 7 write is allowed 0111 data no in FIFO lt 1 8 write is allowed 1000 1111 not valid 3 0 TXFFLAG Transmit FIFO Data Level 0000 No data in FIFO or 8 The register is used to indicate how many bytes in FIFO data are still in the FIFO 0001 1 byte in FIFO 0010 2 byt
424. the ADCADE will be turn on only when the manual or auto sample ADC operation is active for reducing the power system clock is slow Change this register will reduce the clock cycles needed for an ADC conversion These bits are for ASR ADC only When ADC is enabled power consumption will 10 8 CLKSEL SAR ADC Conversion Time Select 000 ADC Conversion In order to increase the sampling speed when Generalplus Technology Inc PAGE 222 use 512 SYSCLK 001 ADC Conversion use 256 SYSCLK 010 ADC Conversion use 128 SYSCLK V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Function Type Description Condition 011 ADC Conversion use 64 SYSCLK 100 ADC Conversion use 1024 SYSCLK 101 ADC Conversion use 2048 SYSCLK 110 111 Reserved ASEN R W Auto Sampling Mode Enable for HQADC only 0 Disable If this bit is set to 1 ADC auto sample 1 Enable operation can be applied on HQADC ADC auto sample rate can be selected from overflow frequency of divided from 48KHz 0x7970 b 10 8 sat Reserved D ASMEN ADC Auto Sampling Mode Enable for HQADC 0 STOP Disabled only 1 START Enabled When this bit is set to 1 ADC auto sample mode start AD conversion will start automatically Then hardware will store the fetched ADC data into 16X16 depth FIFO On the other hand If this bit is cleared to 0 ADC auto sample mode stops malo
425. the P_DMA_TCount will decrease at every reading to a peripheral If WRITEREQ in P DMA Ctrl is 1 this means that the request from a peripheral needs to be written so the P DMA TCount will decrease at every writing to peripheral For example the DMA needs to read from SPI and write to a memory device for 512 bytes IO to memory With SRCBYTE 1 TARBYTE 0 WRITEREQ 0 andyP_DMA_TCountL 512 The DMA will read one byte from SPI while every request comes and P DMA TCount will be decreased by one While every two readings complete the DMA will cascade these two bytes in one word and write to a memory device For other conditions please refer to the following two tables Table 1 Behavior of DMA controller when WRITEREQ 0 Condition Read Start P DMA SRC Add Write Start P DMA TAR Addr P DMA TCount r Change Change Decrease SRCBYTE Read Complete Read Complete Write Complete Read Complete TARBYTE SRCBYTE 1 Each request 2 Reads Complete 12 Reads Complete or Write Complete TARBYTE 0 results in one P DMA TCount is zero read SRCBYTE 0 Request Read Complete Read Complete Two 12 Writes Complete Read Complete TARBYTE 1 Come writes are continues SRCBYTE 1 Each request 2 Reads Complete 2 Reads Complete or 2 Writes Complete TARBYTE 1 result in one P_DMA_TCount is zero Two writes are continues Generalplus Technology Inc PAGE 266 V1 0 Dec 20 2006 G Generalplus GPL
426. this GPL162002A 162003A Integrated Development Environment IDE The GPL162002A 162003A has a 16 bit stereo D A converter with headphone amplifier circuitry which can drive16Q headphone directly All voice data will be converted to data of 48K Hz sample rate by the embedded Sample Rate Controller SRC Programmers can use the internal EQ and 3D effector to increase sound quality GPL162002A 162003A provides two 16 bit DAC drivers for two channel audio outputs The audio driver can be amplified by a bipolar junction transistor or by an amplifier to drive a set of speaker or buzzer GPL162002A 162003A also supports IIS interface for connecting other AC device Two 16 bit DAC channels Each channel has a 16 X 16 bit ring buffer FIFO e FIFO empty interrupt e FIFO full indication flag Support IIS mode e Sample rate converter which can convert voice to data of 48K Hz sample rate Embedded digital 7 band equalizer EQ e Embedded a 3D surround effector DAC Operation In DAC mode DACA signal is outputted through DAC_L pin and the DACB signal is through DAC_R pin The data of DACA and DACB should be delivered to P CHA Data 0x78F1 and P CHB Data 0x78F9 registers respectively In the DAC mode external components some amplification circuit are necessary to drive a speaker There are several solutions for these external components for example simple transistors 8050BJT or standard OPs LM324 or GENERALPLUS amplifier G
427. tion 15 0 ArguMentL R W Argument 15 0 transfer to SD card P_SD_ArgH 0x79D4 SD MMC Argument High Word Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ArguMentH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 0 ArguMentH R W_ Argument 31 16 transfer to SD card Host writes the argument to be transferred to The card in this register The SD command needs a 32 bit command Host must fill ARGUMENTE first and then fill ARGUMENTH next to ensure a 32 bit command is transmit correctly P SD RespL 0x79D5 SD MMC Response Low Word Register Bit 15 14 134 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RespL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Description Condition RespL Response Data from SD card Reading data from this register will be valid only if the CMDBUFFULL is set P_SD_RespH 0x79D6 SD MMC Response High Word Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RespH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 287 V1 0 Dec 20 2006 G Generalplus Function Type GPL162002A 162003A Programming Guide Description Condition Response Data from SD card Readi
428. tion TFTEN lt VS TYPE Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function type Description Condition 15 TFTEN R W TFT Controller Enable 0 Disable Set this bit to 1 to enable TFT interface Clear to 0 1 Enable then TFT interface pin will reinstate as GOIP rai Reserved 11 VS_TYPE R W Vertical Synchronous Type Control 0 Not add If this bit set to 1 the odd field and even filed of 1 add half line vertical will add half line additionally Lmmg Reserves O Generalplus Technology Inc PAGE 134 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P TFT DCLK_CTRL 0x7D01 TFT Data Clock Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function DCLK INV DCLK SEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 sq ea DCLK INV R W TFT data Clock Inverse 0 Not inverse positive edge If this bit is set to 1 it will latch data by 1 Inverse negative edge negative TFT CLK edge otherwise it will latch data by positive TFT CLK edge al Reeva KN 4 0 DOLK SEL R W TFT Clock Selection If these bits set to all 0 s then the System Clock DCLK_SEL 1 TFT CLK is equal to system clock If these are set to all 1 s then TET CLK is equal to system clock 2 and so on
429. tion NFBF 8or16 NFC7 NFC6 NFC5 NFC4 NFC3 NFC2 NFC1 NFCO Init 0 0 0 0 0 0 00 1 1 1 1 1 1 1 1 P_NF_CMD 0x7851 NAND Flash Command Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function NFCMD Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P NF AddrL 0x7852 NAND Flash ADDR Low Word Register Bit 15 1 44 13 N1221311 10 9 8 7 6 5 4 3 2 1 0 Function 2 Cycle 1 Cycle Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_NF_AddrH 0x7853 NAND Flash ADDR High Word Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function 4 Cycle 3 Cycle Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_NF_Data 0x7854 NAND Flash Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function NFDATA Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 355 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P NF_INT Ctrl 0x7855 DMA INT Control Register Bit 15 14 13 112 11 10 9 8 7 6 5 4 3 2 1 0 Function REQF C DMAEN INTEN ADR4EN ADR3EN ADR2EN Init 0 0 0 1 0 1 1 000000000 P ECC Ctrl 0x7857 ECC Control Register Bit 151 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function ECCSPT CKP ERST Init 0 0 0 0 0 0 0 0 0 0 0
430. tion KEYIP ADCRIP TFTUFIP TFTFEIP UTIRIP SPIIP FPIP TPIP ASPIP AUDBIP AUDAIP USBIP DMAIP EXTBIP EXTAIP Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P INT Priority2 0x78A5 Interrupt Priority 2 Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 312 1 0 Function TMDIP TMCIP TMBIP TMAIP KSIP SD DC NAND Default 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 P MINT Ctrl 0x78A8 Miscellaneous Interrupt Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function KC2IF KC2EN KC1IF KC1EN KCOIF KCOEN EXTBIS EXTAIS gt EXTBEN EXTAEN Default 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Timer Control Register Summary Table Name Adres lt Description Generalplus Technology Inc PAGE 321 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P TimerA Ctrl 0x78C0 TimerA Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
431. to 0 this interrupt will be masked EPO Status Clear Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared EOINPC EPO In Packet Clear Interrupt Enable 0 Disable H this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked EOONA EOOPS EOSPS Generalplus Technology Inc PAGE 192 V1 0 Dec 20 2006 EPO Out NACK Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU Ifthis bit is cleared to 0 this interrupt will be masked EPO Out Packet Set Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to O this interrupt will be masked EPO Setup Packet Set Interrupt Enable 0 Disable If this bit is set to 1 and interrupt occurs hardware 1 Enable will issue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked li li G Generalplus GPL162002A 162003A Programming Guide P_USBD_INTF 0x7B3A USB Interrupt Flag Register Bit 15 14 13 42 11 10 9 8 7 6 5 4 3 2 1 0 Function RST RME SUS IINNA IINPC BONA BOP
432. to word or word to byte conversion for the simplification of software coding 4 independent DMA channels Both host bus master and peripheral bus master are integrated Memory to memory memory to IlO IO to memory and 10 to 10 modes are available Both external request and software request modes are available 26 bit addressing 8 bit and 16 bit peripheral supported Support double buffer mode Support pattern match transparent function Support sprite auto move function Spport DMA time out interrupt Integrate Host to peripheral bridge Generalplus Technology Inc PAGE 263 V1 0 Dec 20 2006 G 19 3 19 3 1 Generalplus GPL162002A 162003A Programming Guide 19 2 Block Diagram HOST BUS HOST MASTER CH0 HOST TO CHI PERIPHERAL CH2 j DMA ARBITER BRIDGE CH3 PERIPHERAL BUS PERIPHERAL lt SLAVE MASTER Peripheral BUS Operation Mode There two operation modes when accessing DMA Software mode and External mode When DMA channel is operating in software mode the DMA will start immediately as soon as the CE in P DMA Ctrl 0 is 1 and P DMA TCount gt 0 It will continue moving the data until the P DMA TCount count to O When DMA channel is operates in external mode the DMA channel will wait for the external request signal to initial a read write seque
433. top CPUCLK and SYSCLK but 32768Hz remains working The RTC is still capable of running in this mode P_Sleep Bit Function Default 0x780E Sleep Mode Entrance Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLEEP Bit Function Type Description Condition 15 0 SLEEP W Halt Mode Entrance Register Write OxA00A to enter standby mode stop all clock source CPUCLK SYSCLK and 32768Hz Once waking up from sleep mode the system will be reset P State Bit Function Default Generalplus Technology Inc 0x780F Power State Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 PAGE 20 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide usa Reserved R reseve j 2 0 State Current Power State Register 000 Clock Change State Programmers can appreciate 001 Slow State Use Slow PLL clock the current power state of or external 12MHz clock as clock GPL162002A 162003A by source reading this register 010 Fast State Use Fast PLL as Programmers cannot change clock source system clock in changing state 011 32768 State Use 32768 Hz as clock source 100 wait state Use the previous setting before ebter this state 101 before stop state Use 32768Hz a
434. troduction GPL 162002A 162003A provides a real time clock RTC module which offers Auto update up to hour clock register One alarm comparison registers Hour Minute Second Half second interrupts Alarm Interrupt Scheduler interrupt 16Hz 32Hz 64Hz 128Hz 256Hz 512Hz 1024Hz 2048Hz 9 2 RTC Structure and clock source RTC timer clock 3 0 5 32768 X TA e y Second Minute Hour O gt Second Kat Le Clock Source Ko G Counter Counter Counter D ounter e 1dnueju 91607 jon nuoo Y Y Y Alarm INT J Alarm and Comparator 9 3 Control Registers Real Time Clock Control Register Summary Table Name Address Description Generalplus Technology Inc PAGE 85 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_RTC INT Status 0x7935 HMS Alarm Scheduler Interrupt Flag amp Clear Register P_RTC_INT Ctrl 0x7936 HMS Alarm Scheduler Interrupt Control Register P RTC HMSBusy 0x7937 RTC HMS controller busy register P_Second 0x7920 Second Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function RTCSEC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function type Description Condition gt ail Resev 7 5 0 RTCSEC Real Ti
435. trol signals in default after CPU resets After configuring the control registers these signals can be one of GPIOs For details please refer to Chapter I O Ports Generalplus Technology Inc PAGE 28 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 44 Memory Access Pin Configuration Name VO Description MD 15 0 Memory 16 bit data bus Dedicated MA 16 0 o Memory address bus 16 0 Dedicated waan o Memory address bus 23 17 shared with GPIO PortD 11 5 osjo o Memory chip selection signal shared with GPIO Eet we o Memory write enable control signal shared with GPIO Panpa RE o Memory read enable control signal shared with GPIO Ports 7 4 5 Control Registers Memory Control Register Summary Table Name Address Description P_MCSO Ctrl 0x7820 Chip Selection 0 Memory Device Control Register EMU Chip Selection Memory Device Control Register CS0 boot mapping size select register The P MCSO Ctrl P MCS1 Ctrl P MCS2 Ctrl P MCS3 Ctrl and P MCS4 Ctrl are control registers for memory devices on chip select O 1 2 3 and 4 To make system operation more reliable programmers should set appropriate wait cycles for each external device on these five control registers The longer the wait period is the more reliable a system is The shorter the wait period is the higher the performance is but the less reliable a system is
436. tte is This control bit can be set to 1 only active when 1 bit per pixel or 12 bit per pixel 12 Bypass Palette is not configuration is selected BPP 000 active Generalplus Technology Inc PAGE 124 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide waj Rea PE 3 1 BPP R W Bit Per Pixel Configuration on LCD 000 1 bit pixel Buffer 001 2 bits pixel 010 4 bits pixel 011 8 bits pixel 100 12 bits pixel 101 111 Reserved LCDBW R W B W mode and color mode 0 Color Mode 1 B W Mode including gray mode Palette is a look up table defining the relationship between data in LCD buffer and data to be displayed Using 2 bit per pixel configuration as an example the 2 bit per pixel means one pixel requires two bits memory in a LCD buffer therefore there are up to 4 colors or 4 gray levels in each display frame However the two bits data cannot define the actual pattern to be displayed Instead the 2 bit data is just an index to the palette Palette registers define the actual display pattern corresponding to 2 bit index 00 01 10 and 11 In other words for 2 bit per pixel configuration it takes 4 palette registers meaning look up table depth is 4 The LED controller will perform this look up table operation by hardware automatically Valid Palette Depth Palette Register Address 1 bitper pixel 0x7A00 0x7A01 2 bitper pixel OXTADO Ox7A03
437. ty cycle is set by the CCP register value See the formula below PWM Output Duty Cycle CCP Register Preload_Register 1 65536 Preload Register PWM period 7 1 PWM Frequency Generalplus Technology Inc PAGE 72 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 73 Control Registers Timer Control Register Summary Table Name T address Description TimerD Preload Register P TimerA Ctrl 0x78C0 TimerA Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function TMAIF C TMAIE TMAEN EXTASEL EXTBSEL SRCBSEL SRCASEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TimerB Ctrl 0x78C8 TimerB Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 21 1 0 Function TMBIF C TMBIE TMBEN EXTASEL EXTBSEL SRCBSEL SRCASEL Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 73 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_TimerC_Ctrl 0x78D0 TimerC Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 41 3 2 1 0 Function TMCIF C TMCIE TMCEN
438. ue an IRQ3 or FIQ to CPU If this bit is cleared to 0 this interrupt will be masked To select between IRQ3 and FIQ please refer to Chapter Interrupt Read 0 Not Occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag 0 Disabled 1 Enabled Note SPI RX interrupt Generalplus suggest If enable programmer enable smart interrupt clear function P SPI Misc b8 320 AAA Receive FIFO full register This bit will be set by hardware when the In addition this bit the receiving FIFO is full will be clear by hardware when ii RXFOV R W Receive FIFO over run register If the RX FIFO is full and a data is coming in immediately this flag will be set The new coming data will overwrite the last input data or be skipped please refer to P SPI Misc 7 4 RXFLEV RW Receive FIFO interrupt level register This register is used to indicate how many bytes are stored in receiving FIFO when issuing an interrupt The larger the value is set the lower the interrupt penalty users have since users can read more data in one interrupt receiving FIFO is not full Generalplus Technology Inc PAGE 175 0 Not Full 1 Full Read 0 Not occured Read 1 Occurs Write 0 No effect Write 1 Clear the flag FIFO Full Interrupt issue timing 0000 data no in FIFO gt 1 1 read is allowed 0001 data no in FIFO gt 2 2 read is allowed 0010 data no in FIFO gt 3 3 read is
439. unction type Description 1 Condition 15 0 VOL_3D The volume control register of all 3D module 0000h Mute P DAC VOLUME3D C 0x7BF9 3D Center Volume Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function VOL 3D C Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The volume control register of center channel in 3D module P DAC VOLUME3D S 0x7BFA 3D Surround Volume Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function VOL 3D S Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description 15 0 VOL 3D S R W The volume controls register of surround channel in 3D module P DAC VOLUME3D R 0x7BFB 3D Right Channel Volume Bit 15 14 13 412 11 10 9 8 7 6 5 4 3 2 1 0 Function VOL 3D R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description 1 Condition 15 0 VOL_3D_R R W The volume controls register of right channel in 3D module P DAC VOLUME3D L 0x7BFC 3D Left Channel Volume Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function VOL 3D L Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 107 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Prog
440. up Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function FPIF C FPIEN LCDEN SELF BUSW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15 FPIF C R W LCD FP Signal Interrupt Flag Read 0 Not Occurred This bit is set to 1 by hardware if the FP Read 1 Occurred interrupt is asserted Write 0 No Effect When FP signal is at rising edge and FPIEN Write 1 Clear the flag is set to 1 the FP interrupt is issued FPIF 1 It informs CPU that a new frame is beginning And CPU may update some display data to a new frame FPIEN R W LCD FP Signal Interrupt Enable 0 Disabled If this bit is set to 1 and if FP interrupt is 1 Enabled Generalplus Technology Inc PAGE 118 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide generated hardware will issue an IRQ5 or FIQ to CPU If this bit is cleared to 0 the interrupt will be masked off To select between IRQ5 and FIQ please refer to Chapter Interrupt 13 LCDEN R W LOD Interface Enable 0 Disabled If this bit is set to 1 LCD interface is 1 Enabled enabled Or LCD interface is disabled Setting LCDEN control bit to 1 will enable LCD controller This control bit should be remained as 1 whenever the LCD interface is active When this control bit is cleared to 0 all output signals will stay in
441. upt sources can trigger FIQ or IRQ4 Therefore in FIQ or IRQ4_ interrupt service routine programmers should read P TimerA CCP Ctrl bit 15 14 P_TimerB_CCP_Ctrl bit 15 14 P TimerC CCP Ctrl bit 15 14 to distinguish which interrupt event takes place Note that unlike UART IrDA interrupt only one of above three events will occur at one time Please refer to chapter Timer Counter NENNEN Generalplus Technology Inc PAGE 58 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide There are four interrupt events in Hour Minute Second Half Second Interrupt Hour Minute Second and Half Second Interrupt Any one of these four interrupt sources can trigger IRQ7 Therefore in IRQ7 interrupt service routine programmers should read P RTC INT Status 3 0 to distinguish which interrupt event is generated Note that 4 bit content reading from P_RTC_INT_Status 3 0 sometimes shows more than one interrupt event happening For example reading from P_RTC_INT_Status 3 0 will be 1111 when clock register is from 15 59 59 to 16 0 0 Please refer to chapter Real Time Clock There are four interrupt sources DMA1 DMA3 in DMA Transfer Interrupt Each DMA source includes two interrupt events that a transfer is finished and timeout Any one of these interrupt sources can trigger IRQ3 Therefore in IRQ3 DMA interrupt service routine programmers should read P DMA INT to distinguish which i
442. ur idle state to make sure the new value write valid J Setup Alarm Clock as 08 00 00 H M S Enable Alarm Interrupt only Enable Alarm Scheduler and H Hour Minute Second Half Second Module H Enable CPU IRQ function H Dead Loop J Note that even though that scheduler and H Hour Minute Second Half Second interrupt Il are not enabled their interrupt flags can still H be polled if interrupt event occurs Generalplus Technology Inc PAGE 91 V1 0 Dec 20 2006 G Generalplus cmp r1 0x050F jne L_RTCTestError DisplayResultCode D OK jmp L End Alarm ISR L RTCTestError DisplayResultCode D NG L End Alarm ISR pop r1 r2 from sp reti GPL162002A 162003A Programming Guide H corresponding flag is read as 1 Note that DisplayResultCode is a MACRO H and Delay Loop is a two 32768Hz clock Il cycles Generalplus Technology Inc PAGE 92 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide 10 1 10 2 10 Audio Output DAC GPL 162002A 162003A supports the function for speech and melody synthesis The sound data can be played back in the sequence of the control functions as designed by users program Several algorithms are recommended for sound compression PCM LOG PCM DM and ADPCM In addition Generalplus provides SUBBAND CLEP LPC HASC LRC Wavetable and FM low bit rate high compression rate software algorithm on
443. urred Read 0 Not occurred Write 0 No effect Write 1 Clear the flag Write 1 Enable Read 1 2 Occurred Read 0 Not occurred Write 0 No effect Write 1 Clear the flag Write 1 to indicate IN packet is ready in EndpointO FIFO Read 1 Occurred Read 0 Not occurred Write 0 No effect Write 1 Clear the flag Read 1 Ready Read 0 Not ready Write 0 No effect Write 1 Clear the flag V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide PAIE EOOPE R W EPO Out Packet Enable Write 1 Enable Writing 1 to this bit will enable the incoming packet for OUT data This bit is automatically cleared after the packet is loaded to endpointO FIFO EOOPR is set to 1 Write 1 to P USBD EPEvntClear 0 will clear this bit EOSPR R W EPO Setup Packet Ready Read 1 2 Occurred This bit is set if a non standard setup Read 07 Not occurred command or a get set descriptor command is Write 1 Clear loaded into the endpointO FIFO Write 1 to Write 0 No effect clear the bit P USBD GLOINT 0x7B38 USB Global Interrupt Register Bit 15 14 13 12111 7 10 19 8 7 6 5 4 3 2 1 0 Function BMA STANDARD POWER INT BO BI EPO Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GE CET SAS __ DMA nterrupt Read 1 Occurred This bit is set T one of DMA interrupts happens Read 0 Not occurred Writing 1 to clear
444. us transmitted with a pulse width which is 3 times of the period of an input signal Note thatisetting this bit consumes less power but the transmission distance may become shorter 7 0 I DAPD R W IrDA SIR Receive Latency Setup 07 no delay It defines the delay time between the time that 1 255 1 255 bits delay the receiver is finished and the time that the time transmitter starts P IrDALP 0x7909 IrDA Low Power Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function IrDALP Default 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ges Reseme 7 0 IrDALP IrDA Low Power Divisor EE Generalplus Technology Inc PAGE 166 V1 0 Dec 20 2006 G Generalplus 13 6 Program Examples This sample code is self loop test of UART module interconnected r1 48000000 115200 P UARTIrDA BaudRate r1 r1 0x9070 P UARTIrDA Ctrl r1 r4 0x0050 P UARTIrDA Data r4 r4 1 r1 7 L FillRXFIFO P UARTIrDA Data r4 ri 2ri 1 r4 r1 1 jnz L FillRXFIFO L WaitRX FIFO Empty INT r1 P UARTIrDA Status jl L WaitRX FIFO Empty INT r4 0x50 L Wait RX FIFO Empty r1 P UARTIrDA Status r1 7 r1 amp 0x0010 jnz L UARTSelfLoopTestOK r3 P UARTIrDA Data cmp r3 r4 jne L_UARTSelfLoopTestError r4 r4 1 Jmp L Wait RX FIFO Empty L_UARTSelfkoopTestOK GPL162002A 1
445. ut count of the disable DMA When P DMA _Ctrl b0 is set to 1 the timer 01 DMA will time out starts to count And If the DMA controller does lin 1 256 sec not complete data transmission at duration of 02 DMA will time out designated time out count then hardwre will issue lin 2 256 sec a DMA interrupt to CUP 03 DMA will time out in 3 256 sec FF DMA will time out in 255 256 sec 3 Resne o STATE R Lous Controllers State register 2 17 P DMA SPRISIZEO Ox7BBO DMA Sprite Size 9 0 Register 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SPRISIZE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_SPRISIZE1 0x7BB1 DMA Sprite Size 9 0 Register 1 Bit 15 14 13 12 41 10 9 8 7 6 5 4 3 2 1 0 Function SPRISIZE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_SPRISIZE2 Ox7BB2 DMA Sprite Size 9 0 Register 2 Bit 15 14 13 1 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SPRISIZE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DMA_SPRISIZE3 0x7BB3 DMA Sprite Size 9 0 Register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function SPRISIZE Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 15
446. ver Control 0 Headphone power on This bit set to O will enable headphone 4 Power down mode power driver The hardware can drive a set of headphone directly but needs external audio amplifier circuitry to drive a set of speaker 3 2 SPINS R W Audio Driver Input source select 00 DAC output If SPINS 00 then audio driver output data 01 Line in volume output are from DAC If SPINS 01 audio driver 10 MIC output is internally connected to ADC line in 11 Reserved channel so that hardware can output Generalplus Technology Inc PAGE 102 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide recorded data directly from line in channel If SPINS 10 audio driver is connected to ADC MIC channel so that hardware can output recorded data directly internally from MIC channel Headphone Left Channel Power Control 07 Left channel power on Register This bit availd only when 1 Power down SPINS 11b If SPINS 00 the left channel power controlled by P DAC Ctrl b3 Headphone Right Channel Power Control 0 Right channel power on Register This bit availd only when 1 Power down SPINS 11b If SPINS 00 the channel power controlled by P DAC Ctrl right b2 P DAC IIS Ctrl 0x78FF DAC IIS Mode Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function lt IIS MCL IIS BITS
447. when the CRC16 error occurs in received data packet Data Sequence Error Packet Received This flag is set when the data sequence error occurs in received data packet Bit Stuffing Error Packet Received This flag is set when the bit stuffing error occurs in received data packet Unkonwn PID Packet Received This flag is set when receiving a packet with unknown PID Stall Handshake Received This flag handshake is set when receiving a stall NACK Handshake Received This flag is set when receiving a NACK handshake ACK Handshake Received This flag is set when receiving an ACK handshake Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag Read 0 Not occurred Read 1 Occurred Write 0 No effect Write 1 Clear the flag P USBH INTF Ox7BOE USB Host Interrupt Flag Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function
448. withPoncg RR 1 IDASIR Reception Pin shared with Pong Rrx o IDASIR Transmission Pin shated with Ponco U U U 13 5 Control registers UART IrDA Control Register Summary Table Name Address Description P_UARTIrDA_Data 0x7900 UART IrDA Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function UARTDATA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Generalplus Technology Inc PAGE 156 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide Bit Function Type Description Condition pss jReewd 0 0 0 0 UARTDATA UART IrDA Data Read Write Register BEEN P UART RXsStatus 0x7901 UART Reception Error Flag Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Default 0 0 OE BE PE FE sql Resme T R W Overrun Error Receiving status is read from P UART RXStatus control register This bit is set to 1 if data is received and the FIFO is full Break Error This bit is set to 1 if a break condition is detected Indicate that the received data input is held LOW for more hana full word transmission time defined as start data parity and stop bits This bit is refreshing nevery read So it is necessary Io check t
449. x7832 NAND Flash High Byte Check Sum Low Value Bit 15 14 13 124 11 4 10 9 8 7 6 5 4 3 2 1 0 Function CHECKSUMO HB Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P CHECKSUM1 HB 0x7833 NAND Flash High Byte Check Sum High Value Bit 15 14 13 4 12 211 10 9 8 7 6 5 4 3 2 1 0 Function CHECKSUM1 HB Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C Register Summary Table Name Address Description P GC Ctrl 0x7B60 I2C Control Register P DC Status 0x7B61 I2C Status Register P DC Adar 0x7B62 I2C Address Register P_I2C Data 0x7B63 DC Data Register P_I2C_DeCLK 0x7B64 DC De Bounce Clock Register P_I2C En 0x7B65 12C Interface Enable Register O Generalplus Technology Inc PAGE 358 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P_I2C_Ctrl 0x7B60 DC Control Register Bit 1514113112 111110 9 8 7 6 5 4 3121110 Function JACKEN CLKSEL INTEN INTPEND C TXCLK Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_I2C Status 0x7B61 12C Status Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Mod BY DataEN ArbS SS Addr LS Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_I2C_Addr 0x7B62 DC Address Register Bit 15114113112111110 9 8 7 6 5 4 3 2 1 0 Function Addr
450. x7D12 TFT PIPO Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPOEN PIPOSCREN Default 0 0 0 0 0 0 0 10 O 0 0 0 0 0 0 0 P_TFT_PIP1_CTRL 0x7D1D TFT PIP1 Control Register Bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Function PIP1EN PIPISCREN P J T Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P TFT PIP2 CTRL 0x7D28 TFT PIP2 Control Register Bit 15 14 1312111110 9 8 7 6 _514 312 1 1 0 Function PIP2EN PIP2SCREN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_TFT_PIP3_CTRL 0x7D33 TFT PIP3 Control Register Bit 15 14 1312111110 1 9 8 7 16 15 14 1312 1 1 0 Function PIPSEN PIPSSCREN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Function type Description Condition 15 PIPZEN RAW The PIPZ Frame Enable 0 Disable 1 Enable PIPZSCREN R W The PIP Scrolling Function Enable 0 Disable See the following diagram for details uM Enable pao Reseed Generalplus Technology Inc PAGE 143 V1 0 Dec 20 2006 G Generalplus GPL162002A 162003A Programming Guide P TFT PIPO VIR SAH 0x7D13 TFT PIPO Virtual Frame Buffer Start High Address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function PIPO VIR SAH Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
451. y slots are required when issuing an interrupt The larger the value is set the lower the interrupt penalty you have since you can write more data in one interrupt FIFO Full Interrupt issue timing 000 data no in FIFO lt 1 8 write is allowed 001 data no in FIFO 2 7 write is allowed 010 data no in FIFO 3 6 write is allowed 011 data no in FIFO lt 4 5 write is allowed 100 data no in FIFO 5 4 write is allowed 101 data no in FIFO lt 6 3 write is allowed 110 data no in FIFO lt 7 2 write is allowed 111 2 data no in FIFO 8 1 write is allowed reserves VK AY 10 8 TX_FLAG I T gt A Reserved Pp 6 4 RX_ ss i see EE Technology Inc Transmit FIFO Data Level This register indicates how many data remain in transmit FIFO This register is used to indicate how many bytes are stored in receiving FIFO when issuing an interrupt The larger the value is set the lower the interrupt penalty you have since you can read more data in one interrupt PAGE 164 000 0 byte in FIFO 001 1 byte in FIFO 010 2 bytes in FIFO 011 3 bytes in FIFO 100 4 bytes in FIFO 101 5 bytes in FIFO 110 6 bytes in FIFO 111 7 bytes in FIFO FIFO Full Interrupt issue timing 000 data no in FIFO gt 1 1 read is allowed 001 data no in FIFO gt 2 2 read is allowed 010 data no in FIFO gt 3 3 read is allowed 011 data

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