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S1D13706 TECHNICAL MANUAL

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1. 170 165 160 155 150 145 140 135 130 125 120 E 175 SK a DIE No X5534D Pa Unusable Pad 180 9 185 vo 190 105 Y 195 100 A 200 95 205 90 gt X 210 85 0 0 215 80 220 75 225 70 230 65 235 60 Unusable Pad E 1 5 10 15 20 25 30 35 40 45 50 55 Figure 4 3 Pinout Diagram Die Form SID13706D00A Chip Size 5 88 x 6 55 mm PAD size 68 x 68 um S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 21 Vancouver Design Center Table 4 2 Pi
2. VDP VNDP la ple FPFRAME zE FPLINE fl f l 1 I I DRDY MOD ne X FPDAT 15 0 Invalid LINE X LINE2 X LINES X LINE4 XLINE479 XLINE480 Invalid LINE1 X LINE2 a FPLINE l DRDY MOD oh I HDP pig NDP y FPSHIFT 3Ts 2Ts 3Ts 3Ts 2Ts 3Ts 3Ts 3Ts 3Ts 2Ts 3Ts y 3Ts 3Ts 2Ts 3Ts 3Ts 2 s L 2Ts 3Ts 3Ts E FPDAT15 Invalid 1 R1 X 1 G6 X1 B11 X Y E ES X 1 G635X Invalid FPDAT14 Invalid XIB XR XIGX X X lb X Krees invalid XX FPDAT13 Invalid X 1 G2 X 1 B7 X 1 R13 X RE X X1 R637 Invalid X FPDAT12 invalid 1a 1 08 X1 B13 X he Se Xx XBoX Invalid XX FPDAT7 Invalid 1 B3 X 1 9 X1 G14 X a X X1 G638X Invalid X FPDAT6 Invalid G4 Y 1 B9 X 1 R15X X X E X X1 R639 Invalid X X FPDAT5 Invalid R5 X1 G10 X1 B15 Y X X1 B639 Invalid X FPDAT4 Invalid 1 B5 X 1 R11 1 G16 Y y MU 1 G640X Invalid FPDAT11 Invalid 1 61 X 1 B6 X 1 R12X X E X1 R636 Invalid X X FPDAT10 Invalid 12 X 1 67 Y 1812 X SS aS X X1B636X Invalid XX FPDAT9 Invalid 1 82 X 1 R8 X 1 G13 X E X1 G637X Invalid Y FPDAT8 Invalid XT 188 X 1 R14X Y Y a EE y YTR638X invalid X FPDAT3 Invalid TRA Y 1 G9 X 1 B14Y YX Y A E E Y 1 B638X Inv
3. T 1 a 3 p o Peo 80 UPN Aepseupe vL lt oog gt g n saqwny w wn og 215 Siopeuuoo sng ISOH 0 4 MBH QOOBSOLEHNSS y Z utd Idd 03 35019 Z9ePAI9 UT dIDd 07 SSOTO PAF utd grog 03 SO ja a 2 a a AOL ng9 L noz nee le normes L mob nga L 1e9 F 960 FJ seo T veo FT n nae Ag ne ake 10d W10d a n ASt T J 2X 1 U3OV3H pm a pe siow wrod Bae 3 Ti SBE ONAF O A E 9 408 nosna 9Z t ee Lav oav fee 91 59 Way S i 4 z 039 0 9 ja 1 38 9 lt uva 9 UuaS y Huuad 91law ot dOLS 9 PI 138430 gt A KGACHL 9 yaw 9 2739 9 Moz ngg la eeg 39 9 amp yasal 9 Alt 2X 1 U3OV3H 1am 9 KES 91 HUING SO git gt LSH 9 91 LIVM gt aM 91 03183538 as34 9 03183538 O A 0383538 ja 9 o Lelay 9 T T a Figure 10 5 SIDI3706B00C Schematics 5 of 6 S5U13706B00C Rev 1 0 Evaluation Board User Manual S1D13706 Issue Date 01 02 23 X31B G 004 04 Page 33 PSUS W00e BO Ye epsa lt oog gt g Jequiny juauinoog azis 9109 WOd4 0 4 19 DOOEIOZELNSS on DISNOOU a gt 38 o Lelav nezo nezo nezo nezo F 9
4. 6 bit Red Data 6 bit Green Data Blue Look Up Table 256x6 00 0000 01 0001 02 0010 03 0011 04 0100 05 0101 A 06 0110 6 bit Blue Data da 1398 08 09 1001 0A 1010 0B 1011 1100 06 1101 0E 1110 OF 1111 Kc FD FE FF unused Look Up Table entries S1D13706 X31B A 001 08 Figure 11 7 4 Bit Per Pixel Color Mode Data Output Path Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Vancouver Design Center 8 Bit per pixel Color Mode Page 137 Red Look Up Table 256x6 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 6 bit Red Data 6 bit Green Data 00 0000 0000 01 0000 0001 02 0000 0010 03 0000 0011 04 0000 0100 05 0000 0101 06 0000 0110 07 0000 0111 F8 1111 1000 F9 1111 1001 FA 1111 1010 FB 1111 1011 FC 1111 1100 FD 1111 1101 FE 1111 1110 FF 1111 1111
5. Figure 3 4 Configuration Jumper JP3 Location S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center JP4 GPO Polarity on H1 Page 13 JP4 selects the polarity of the GPO signal available on the LCD Connector H1 Position 1 2 sends the GPO signal directly to H1 default setting Position 2 3 inverts the GPO signal before sending it to H1 E rnd os Orr P me i E JP4 E fe o0 en REPETE Normal f f XX Inverted Figure 3 5 Configuration Jumper JP4 Location JP5 Contrast adjust for ve LCD bias VDDH JP5 selects the type of control used for contrast adjustment of the ve LCD bias VDDH Position 1 2 selects software control of the contrast adjustment Position 2 3 selects manual control of the contrast adjustment using potentiometer R24 default setting i e a O7 sm a a HEE Software 7 0 Control Manual Control Figure 3 6 Configuration Jumper JP5 Location S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 S1D13706 X31B G 004 04 Page 14 Epson Research and Development
6. Figure 2 1 REDCAP2 Memory Read Cycle Figure 2 2 REDCAP2 Memory Write Cycle on page 9 illustrates a typical memory write cycle on the REDCAP2 bus Figure 2 2 REDCAP2 Memory Write Cycle Interfacing to the Motorola RedCap2 DSP With Integrated MCU S1D13706 Issue Date 01 02 23 X31B G 014 02 Page 10 Epson Research and Development Vancouver Design Center 3 S1D13706 Host Bus Interface The S1D13706 implements a 16 bit native REDCAP2 host bus interface which is used to interface to the REDCAP2 processor The REDCAP2 host bus interface is selected by the S1D13706 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configu ration For details on S1D13706 configuration see Section 4 3 S1D13706 Hardware Configuration on page 15 3 1 Host Bus Interface Pin Mapping S1D13706 X31B G 014 02 The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping 1D13706 Pin Names REDCAP2 AB 16 0 A 16 0 DB 15 0 D 15 0 WE1 EBO M R A17 CS REDCAP2 Internal Chip Select CLKI CKO BS Connected to HIO Vpp RD WR RW RD OE WEO EB1 WAIT N A RESET RST_OUT Interfacing to the Motorola RedCap2 DSP With Integrated MCU Issue Date 01 02 23 Epson Research and
7. LCD Pin LCD Pin S1D13706 Description Ritak No Name Pin Name P meer 1 VDD Power supply of gate driver high level ana ee Rower 2 VCC Power supply of gate driver logic high EE A ae ioe power 3 MOD Control signal of gate driver eee Section 2 2 MR TEMO Signal on page 11 4 MOD Control signal of gate driver 36e Section ee MR TETEMOD Signal on page 11 5 U L Selection for vertical scanning direction Connect to VSHD top bottom scanning 6 SPS FPFRAME Start signal of gate driver 7 CLS GPIO1 Clock signal of gate driver 8 VSS Power supply of gate driver logic low a a toma Power 9 VEE 5 Power supply of gate driver low level oda oa ae RONEL 10 VEE a Power supply of gate driver low level a T Power 11 VCOM Common electrode driving signal See Section 2 1 External Power Supplies on page 8 12 VCOM Common electrode driving signal oe Selle fee Supplies on page 8 13 SPL GPIO3 Sampling start signal for left right scanning 14 RO FPDAT11 Red data signal LSB 15 R1 FPDAT10 Red data signal 16 R2 FPDAT9 Red data signal 17 R3 FPDAT2 Red data signal 18 R4 FPDAT1 Red data signal 19 R5 FPDATO Red data signal MSB 20 GO FPDAT14 Green data signal LSB 21 G1 FPDAT13 Green data signal 22 G2 FPDAT12 Green data signal 23 G3 FPDAT5 Green data signal 24 G4 FPDAT4 Green data signal 25 G5 FPDAT3 Green data signal MSB 1D13706 Connecting to the Sharp HR TF
8. Page 102 Vancouver Design Center bits 5 4 Panel Data Width Bits 1 0 These bits select the data width size of the LCD panel Table 8 5 Panel Data Width Selection Panel Data Width Bits 1 0 P2 ssive dora Width Active Panel Data Width Size 00 4 bit 9 bit 01 8 bit 12 bit 10 16 bit 18 bit 11 Reserved Reserved bit 3 Active Panel Resolution Select This bit selects one of two panel resolutions when an HR TFT or D TFD panel is selected This bit has no effect for other panel types Table 8 6 Active Panel Resolution Selection pa OS HR TFT Resolution D TFD Resolution Select Bit 0 160x160 160x240 1 320x240 320x240 Note This bit sets some internal non configurable timing values for the selected panel How ever all panel configuration registers REG 12h REG 27h still require program ming with the appropriate values for the selected panel For panel AC timing see Section 6 4 Display Interface on page 56 bits 1 0 Panel Type Bits 1 0 These bits select the panel type Table 8 7 LCD Panel Type Selection REG 10h Bits 1 0 Panel Type 00 STN 01 TFT 10 HR TFT 11 D TFD 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 103 Vancouver Design Center MOD Rate Register REG 11h Read Write n a MOD Rate Bits 5 0 7 6 5 4 3 2 1 0 bits 5 0 MOD Rate Bits 5 0 These bits are for passive LCD pane
9. Color Depth Look Up Table Indices Used Effective Gray RED GREEN BLUE Shades Colors 1 bpp gray 2 2 gray shades 2 bpp gray 4 4 gray shades 4 bpp gray 16 16 gray shades 8 bpp gray 16 64 gray shades 16 bpp gray 64 gray shades 1 bpp color 2 2 2 2 colors 2 bpp color 4 4 4 4 colors 4 bpp color 16 16 16 16 colors 8 bpp color 256 256 256 256 colors 16 bpp color 65536 colors SF Indicates the Look Up Table is not used for that display mode Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 20 Epson Research and Development Vancouver Design Center 4 2 1 Gray Shade Modes Gray shade monochrome modes are defined by the Color Mono Panel Select bit REG 10h bit 6 When this bit is set to 0 the value output to the panel is derived solely from the green component of the LUT 1 bpp gray shade The 1 bpp gray shade mode uses the green component of the first 2 LUT entries The remaining indices of the LUT are unused Table 4 2 Suggested LUT Values for 1 Bpp Gray Shade Unused entries 2 bpp gray shade The 2 bpp gray shade mode uses the green component of the first 4 LUT entries The remaining indices of the LUT are unused Table 4 3 Suggested LUT Values for 4 Bpp Gray Shade Unused entries S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 21 Vancouver D
10. Byte 2 Host Address 2 bpp Byte 0 Byte 1 Byte 2 Host Address 4 bpp Byte 0 Byte 1 Byte 2 Host Address Byte 0 Byte 1 Byte 2 Host Address Display Memory 16 bpp 5 6 5 RGB Byte 0 Bo Byte 1 Ro Ph RGB value from LUT Index A Panel Display PoP P2 P3P4P5PsP7 P RGB value from LUT Index A Bn Panel Display PoP PoP3P4P5P P7 P RGB value from LUT Index An Bn Cn Dn Panel Display PoP4 P2 P3P4P5 Pe P7 P RGB value from LUT Index An Bn Cr Dp En Fm Gn Hn Panel Display PoP4 Po P3P4Ps P P7 Bypasses LUT Byte 2 B4 Byte 3 RO Host Address Display Buffer Ph z R Gn 5 0 B Panel Display Figure 10 1 4 8 16 Bit Per Pixel Display Data Memory Organization Note 1 The Host to Display mapping shown here is for a little endian system 2 For 16 bpp format R Gn Bp represent the red green and blue color components Hardware Functional Specification Issue Date 01 11 13 1D13706 X31B A 001 08 Page 132 Epson Research and Development Vancouver Design Center 11 Look Up Table Architecture The following figures are intended to show
11. 00 0000 0000 01 0000 0001 02 0000 0010 03 0000 0011 04 0000 0100 05 0000 0101 06 0000 0110 07 0000 0111 F8 1111 1000 F9 1111 1001 F 1111 1010 FB 1111 1011 FC 1111 1100 ED 1111 1101 EE 1111 1110 FF 11111111 8 bit per pixel data from Display Buffer 6 bit Blue Data Figure 11 8 8 Bit per pixel Color Mode Data Output Path 16 Bit Per Pixel Color Mode The LUT is bypassed and the color data is directly mapped for this color depth See Display Data Formats on page 131 Hardware Functional Specification Issue Date 01 11 13 S1D13706 X31B A 001 08 Page 138 Epson Research and Development Vancouver Design Center 12 SwivelView 12 1 Concept Most computer displays are refreshed in landscape orientation from left to right and top to bottom Computer images are stored in the same manner Swivel View is designed to rotate the displayed image on an LCD by 90 180 or 270 in an counter clockwise direction The rotation is done in hardware and is transparent to the user for all display buffer reads and writes By processing the rotation in hardware SwivelView offers a performance advantage over software rotation of the displayed image The image is not actually rotated in the display buffer since there is no address translation during CPU read write The image is rotated during display refresh 12 2 90 SwivelView 90 Swivel
12. o o 96 S1D13706 Programming Notes and Examples Issue Date 01 02 23 X31B G 003 03 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 9 Vancouver Design Center 1 Introduction This guide provides information on programming the S1D13706 Embedded Memory LCD Controller Included are algorithms which demonstrate how to program the 1D13706 This guide discusses Power on Initialization Panning and Scrolling LUT initialization LCD Power Sequencing Swivel View Picture In Picture Plus etc The example source code referenced in this guide is available on the web at www eea epson com or www erd epson com This guide also introduces the Hardware Abstraction Layer HAL which is designed to simplify the programming of the S1D13706 Most SED135x and SED137x products have HAL support thus allowing OEMs to do multiple designs with a common code base This document will be updated as appropriate Please check the Epson Electronics America Website at www eea epson com for the latest revision of this document and source before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 10 Epson Research and
13. SIZ 1 0 TT 1 0 X X D 31 0 XXXXXX valid Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 MCF5307 Memory Write Cycle 2 1 3 Burst Cycles Burst cycles are very similar to normal cycles except that they occur as a series of four back to back 32 bit memory reads or writes The TIP Transfer In Progress output is asserted continuously through the burst Burst memory cycles are mainly intended to fill Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13706 Issue Date 01 02 23 X31B G 010 02 Page 10 Epson Research and Development Vancouver Design Center caches from program or data memory They are typically not used for transfers to or from IO peripheral devices such as the S1D13706 The MCF5307 chip selects provide a mechanism to disable burst accesses for peripheral devices which are not burst capable 2 2 Chip Select Module In addition to generating eight independent chip select outputs the MCF5307 Chip Select Module can generate active low Output Enable OE and Write Enable BWE signals compatible with most memory and x86 style peripherals The MCF5307 bus controller also provides a Read Write R W signal which is compatible with most 68K peripherals Chip selects O and 1 can be programmed independently to respond to any base address and block size Chip select 0 can be active immediately after reset and is typically used to control a boot ROM Chip select 1 is
14. Programming Notes and Examples Issue Date 01 02 23 1D13706 X31B G 003 03 Page 14 Epson Research and Development Vancouver Design Center 3 Memory Models The S1D13706 contains a display buffer of 80K bytes and supports color depths of 1 2 4 8 and 16 bit per pixel For each color depth the data format is packed pixel Packed pixel data may be envisioned as a stream of pixels In this stream pixels are packed adjacent to each other If a pixel requires four bits then it is located in the four most signif icant bits of a byte The pixel to the immediate right on the display occupies the lower four bits of the same byte The next two pixels to the immediate right are located in the following byte etc 3 1 Display Buffer Location The S1D13706 display buffer is 80K bytes of embedded SRAM The display buffer is memory mapped and is accessible directly by software The memory block location assigned to the 1D13706 display buffer varies with each individual hardware platform For further information on the display buffer see the 7D 13706 Hardware Functional Specification document number X31B A 001 xx For further information on the S1D13706 Evaluation Board see the S5U13706B00C Evaluation Board Rev 1 0 User Manual document number X31B G 004 xx 3 2 Memory Organization for One Bit per pixel 2 Colors Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 1 Pixel 2 P
15. REG 14h HORIZONTAL D ISPLAY PERIOD REGISTER Bit 4 Bit 3 Horizontal Display Period Bit 2 RW Page 1 n a n a n a Bit 4 Bit 3 TFD GCP Ind Bit 2 lex Bit 1 Bit 0 REG 2Ch D TFD GCP DATA REGISTER Bit 7 Bit 6 Bit 5 D TFD GCP Data Bit 4 Bit 3 Bit 2 RW Bit 1 Bit 0 Bit 7 Bit 6 REG 81h SuB WINDOW LINE ADDRESS Bit 5 Bit 4 Bit 3 OFFSET REGISTER 1 RW n a n a n a n a n a Sub Window Line Address Offset Bit 9 Bit 8 REG 84h Su WiNDOw X START POSITION REGISTER 0 RW Sub Window X Start Position Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 85h Sus WinDow X START POSITION REGISTER 1 RW Sub Window X Start n a n a n a n a n a n a Position Bit 9 Bit8 REG 88h SUB WINDOW Y START POSITION REGISTER 0 RW Bit 7 Bit 6 Sub Window Y Start Position Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 01 02 26 S1D13706 Register Summary REG 89h SuB WINDOW Y START POSITION REGISTER 1 RW REG B2h CV PULSE BURST LENGTH REGISTER Sub Window Y Start n a n a n a n a n a n a Position Bit 9 Bit 8 REG 8Ch SuB WiNDOW X END POSITION REGISTER 0 RW Sub Window X End Position Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 8Dh SuB WINDOW X END POSITION REGISTER 1 RW Sub Window X End n a n a n a n a n a n a Position Bit 9 Bit 8 REG 9
16. 17 0 TFT CSnit gt CS FPFRAME FPFRAME Display A 16 1 AB 16 1 FPLINE gt FPLINE 3 D 15 0 la gt DB 15 0 3 FPSHIFT gt FPSHIFT WEO gt WEO 2 WE1 WEI DRDY DRDY ha BS gt BS S1 D1 3706 RD WR gt RD WR GPO RD gt RD WAITH La WAIT CKIO gt CLKI RESET gt RESET ABO VSS V Figure 3 4 Typical System Diagram Hitachi SH 3 Bus Hardware Functional Specification 1D13706 X31B A 001 08 Page 16 Epson Research and Development Vancouver Design Center Oscillator MC68K 1 BUS y HIOVDD A A RD x FPDAT 17 0 gt D 17 0 18 bit WEO 2 FPFRAME SPS HR TFT A 23 17 gt BA E Decoder M R FRENE ER Display FPSHIFT gt CLK Decoder p CS GPIOO PS L GPIO1 CLS 2 A 16 1 AB 16 1 3 q pilo2 p REV D 15 0 gt DB 15 0 GPIO3 sPL S p m LDS ABO S1 D1 3706 UDS gt WE1 GPO ASH gt BS R W RD WR DTACK WAIT CLK gt CLK RESET gt RESET Figure 3 5 Typical System Diagram MC68K 1 Motorola 16 Bit 68000 Oscillator MC68K 2 BUS y a A 31 17 caus gt wre Y FPDAT 17 0 D 17 0 1g bit FCO FC1 o FPFRAME DY D TFD LP FPLINE yy Displa Decoder CS splay FPSH
17. CNF7 CNF6 CLKI to BCLK Divide 0 2 1 1 0 3 1 1 1 4 1 recommended setting for generic 8 bit processor 4 3 Register Memory Mapping The S1D13706 is a memory mapped device The S1D13706 uses two 128K byte blocks which are selected using A17 from the 8 bit processor A17 is connected to the S1D13706 M R pin The internal registers occupy the first 128K byte block and the 80K byte display buffer occupies the second 128K byte block An external decoder can be used to decode the address lines and generate a chip select for the S1D13706 whenever the selected 128k byte memory block is accessed If the processor supports a general chip select module its internal registers can be programmed to generate a chip select for the S1D13706 whenever the 1D13706 memory block is accessed Interfacing to 8 bit Processors Issue Date 01 02 23 Epson Research and Development Page 13 Vancouver Design Center 5 Software Test utilities and Windows CE v2 11 2 12 display drivers are available for the S1D 13706 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display driver
18. Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 01 02 23 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface requires the following signals CLKI is a clock input required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For example DCLKOUT from the Toshiba TMPR3905 12 The address inputs AB 12 0 are connected directly to the TMPR3905 12 address bus Since the TMPR3905 12 has a multiplexed address bus the other address inputs A 16 13 must be generated using an external latch controlled by the address latch enable signal ALE The low data byte on the TMPR3905 12 data bus for 16 bit ports is D 31 24 and connects to the 1D 13706 low data byte D 7 0 The high data byte on the TMPR3905 12 data bus for 16 bit ports is D 23 16 and connects to the S1D13706 high data byte D 15 0 The hardware engineer must ensure that CNF4 selects the proper endian mode upon reset Chip Select CS is driven by external decoding circuitry to select the S1D13706 M R memory register selects between memory or register accesses This signal may be connected to an address line allowing system address A17 to be connected to the M R line This address line must be generated from the external latch used to provide the upper addresses to the S1D13706 WE1F is
19. MEMCS 16 of the NEC VR4181A is connected to LCDCS to signal that the S1D13706 is capable of 16 bit transfers BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO Vpp The diagram below shows a typical implementation of the VR4181A to S1D13706 interface NEC VR4181A 1D13706 MEMWR gt WEO UBE gt WE1 MEMRD RD A17 M R LCDCS e gt CSH Pull up IORDY 4 WAIT MEMCS16 System RESET __ RESET A 16 0 gt AB 16 0 D 15 0 4 gt DB 15 0 SYSCLK gt CLKI HIO Vop a BS RD WR Note When connecting the S1D13706 RESET pin the system designer should be aware of all conditions that may reset the S1D13706 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of VR4181A to SIDI3706 Interface S1D13706 Interfacing to the NEC VR4181A Microprocessor X31B G 008 02 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 4 2 S1D13706 Hardware Configuration Page 13 The S1D13706 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13706 Hardware Functional Specification document number X31B A 001 xx The follow
20. Writes one RGB element to the lookup table Programming Notes and Examples Issue Date 01 02 23 S1D13706 X31B G 003 03 Page 64 Epson Research and Development Vancouver Design Center Table 10 1 HAL Functions Continued seSubWinVirtInit seMainAndSubWinVirtInit Function Description seReadLutEntry Reads one RGB element from the lookup table seWriteLut Write the entire lookup table seReadLut Read the entire lookup table seSetMode Sets the color depth of the display and updates the LUT seUseMainWinlmageForSubWin Sets the sub window image to use the same image as the main window seGetBitsPerPixel Gets the current color depth AA gt AAA seVirtlnit seMainWinVirtlnit Initialize a surface to hold an image larger than the physical display size Also required for SwivelView 90 and 270 seVirtPanScroll seMainWinVirtPanScroll seSubWinVirtPanScroll seMainAndSubWinVirtPanScroll seSetPixel seSetMainWinPixel seSetSubWinPixel Pan right left and Scroll up down the display device over the indicated virtual surface Set one pixel at the specified x y co ordinate and color seGetPixel seGetMainWinPixel seGetSubWinPixel Returns the color of the pixel at the specified x y co ordinate seDrawLine seDrawMainWinLine seDrawSubWinLine Draws a line between two endpoints in the specified color seDrawRect seDrawMainWinRect seDrawSubWinRect Draws a rectangle The rect
21. YSCL VCC 3 3V VCC 3 3V VDDH VDD 4 5V VCC 3 3V D1 158388 28J285 3 Ci 1uF 16V 1 25K1848 C4 0 1uF 16V C2 1uF 16V S1D13706 X31B G 012 03 Figure 2 1 VDDH and VDD Voltage Generation The circuit in Figure 2 1 VDDH and VDD Voltage Generation uses the Vertical Shift Clock control signal YSCL to control a pair of ultrahigh speed P and N channel MOSFET transistors These transistors are used to generate a 3 3V square wave which is passed through C1 This blocks any DC component in the signal The 3 3V square wave is then added to 3 0V from diode D1 VF 0 3V and passed through diode D2 VF 0 3V to produce a 6 0V DC input voltage to the linear regulator Toko part TK11245BM This regulator provides the high precision output of 4 5V required for VDDH and VDD An alternative method would be to use a switching regulator IC to generate 4 5V from 3 3V If 5 0V is available a low dropout linear regulator may also be used Connecting to the Epson D TFD Panels Issue Date 01 02 23 Epson Research and Development Page 9 Vancouver Design Center 2 2 VEEY LCD Panel Drive Voltage for Vertical Power Supplies Brightness Reference A negative voltage potential VEEY must be provided as a brightness reference and a temperature compensator to the vertical logic and vertical liquid crystal driving power supplies The recommended voltage is 32 0V with a minimum allowabl
22. 1D13706 X31B B 002 03 1 To show color patterns which must be manually stepped through type the following 13706SHOW The program displays the default color depth as selected by 13706CFG Press any key to go to the next screen Once all screens are shown the program exits To exit the pro gram immediately press the Esc key To show color patterns which automatically step through type the following 13706SHOW a The program displays the default color depth as selected by 13706CFG Each screen is shown for approximately 1 second before the next screen is automatically shown The program exits after the last screen is shown To exit the program immediately press CTRL BREAK To show a color pattern for a specific color depth type the following 13706SHOW b mode where mode 1 2 4 8 or 16 The program displays the requested color depth and then exits Note If a monochrome LCD panel is used the image is formed using only the green component of the Look Up Table for 1 2 4 and 8 bpp color depths For 16 bpp color depths the green component of the pixel value is used 4 To show the color patterns in Swivel View 90 mode type the following 13706SHOW r90 The program displays the default color depth as selected by 13706CFG Press any key to go to the next screen To exit the program immediately press the Esc key The r90 r180 and 1270 switches can be used in combination with other com mand
23. 1D13706 X31B B 003 02 Epson Research and Development Vancouver Design Center F addr1 addr2 data Fills a specified address range with 8 bit data bytes Where addr1 Start address of the range to be filled hex addr2 End address of the range to be filled hex data Data to be written hex Data can be a list of bytes to be repeated for the duration of the fill To use decimal values attach a t suffix to the value e g 100t is 100 decimal FD addr1 addr2 data Fills a specified address range with 32 bit data dwords Where addrl Start address of the range to be filled hex addr2 End address of the range to be filled hex data Data to be written hex Data can be a list of dwords to be repeated for the duration of the fill To use decimal values attach a t suffix to the value e g 100t is 100 decimal FW addr1 addr2 data Fills a specified address range with 16 bit data words Where addrl Start address of the range to be filled hex addr2 End address of the range to be filled hex data Data to be written hex Data can be a list of words to be repeated for the duration of the fill To use decimal values attach a t suffix to the value e g 100t is 100 decimal H lines Sets the number of lines of data that are displayed at a time The display is halted after the specified number of lines Setting the number of lines to O disables the halt function and allows the data to continue di
24. 1D13706 13706BMP Demonstration Program X31B B 004 02 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center 13706BMP 13706BMP is a demonstration utility used to show the S1D13706 display capabilities by rendering bitmap images on the display device The program displays any bitmap stored in Windows BMP file format and then exits 13706BMP supports SviwelView 90 180 and 270 hardware rotation of the display image 13706BMP is designed to operate on a personal computer PC within a 32 bit environment only Windows 9x NT Other embedded platforms are not supported due to the possible lack of system memory or structured file system The 13706BMP demonstration utility must be configured and or compiled to work with your hardware configuration The program 13706CFG EXE can be used to configure 13706BMP For further information on 13706CFG refer to the 13706CFG Users Manual document number X31B B 001 xx S1D13706 Supported Evaluation Platforms 13706BMP supports the following S1D13706 evaluation platforms e PC with an Intel 80x86 processor running Windows 9x NT Note The 13706BMP source code may be modified by the OEM to support other evaluation platforms Installation Copy the file 13706bmp exe to a directory in the path e g PATH C S1D13706 13706BMP Demonstration Program 1D13706 Issue Date 01 02 23 X31B B 004 02 Page 4 Epson Research and Development Vancouver Design Cent
25. 2 Windows will detect the new hardware as a new PCI Device and bring up the ADD NEW HARDWARE dialog box 3 Click NEXT 4 Windows will look for the driver When Windows does not find the driver it will al low you to specify the location of it Type the driver location or select BROWSE to find it 5 Click NEXT 6 Windows will open the installation file and show the option EPSON PCI Bridge Card 7 Click FINISH All ISA Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Goto the CONTROL PANEL and double click on ADD NEW HARDWARE to launch the ADD NEW HARDWARE WIZARD Click NEXT 3 Windows will attempt to detect any new plug and play device and fail Click NEXT 4 Windows will ask you to let it detect the hardware or allow you to select from a list Select NO I WANT TO SELECT THE HARDWARE FROM A LIST and click NEXT 5 From the list select OTHER DEVICES and click NEXT 6 Click HAVE DISK and type the path to the driver files or select browse to find the driver 7 Click OK 8 The driver will be identified as EPSON PCI Bridge Card Click NEXT 9 Click FINISH S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 X00A E 003 04 Page 6 Windows 95 OSR2 Epson Research and Development Vancouver Design Center All PCI Bus Evaluation Cards X00A E 003 04 1 2 Install the evaluation board in the computer and boot the computer Wi
26. 6 5 Manual Software Adjustable LCD Panel Negative Power Supply VLCD 6 6 Software Adjustable LCD Backlight Intensity Support Using PWM 6 7 Passive Active LCD Panel Support 6 7 1 Buffered LCD Connector 00000004 6 7 2 Extended LCD Connector 0 0 0 0 0 2 000 Clock Synthesizer and Clock Options lt lt 7 1 Clock Programming References aira a aa ad bed a ae o 8 1 Documents 8 2 Document Sources Parts List ca ew as A ee ea ee eee a Schematic S de sr a as ta a ds oe a ie la Board Layout si caw ee e o al e A A ee e e dE Technical Support ori aa a a Bes 12 1 EPSON LCD Controllers S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 Page 3 S1D13706 X31B G 004 04 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center Table 3 1 Table 3 2 Table 4 1 Table 4 2 Table 4 3 Table 5 1 Table 5 2 Table 6 1 Table 6 2 Table 9 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 7 1 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Figure 10 6 Figure 11 1 List of Tables Configuration DIP Switch Settings 00 Jumper Summary 2 00000
27. Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 01 02 26 Epson Research and Development Vancouver Design Center 3 S1D13706 Host Bus Interface The S1D13706 directly supports multiple processors The S1D13706 implements a Dragonball Host Bus Interface which directly supports the Motorola MC68VZ328 micro processor Page 9 The Dragonball Host Bus Interface is selected by the S1D 13706 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 12 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping eee Motorola MC68VZ328 AB 16 0 A 16 0 DB 15 0 D 15 0 WE1 UWE CS CSx M R External Decode CLKI CLKO BS Connect E ee from the RD WR Connect a ee from the RD OE WEO LWE WAIT DTACK RESET System RESET Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 01 02 26 1D13706 X31B G 016 02 Page 10 Epson Research and Development Vancouver Design Center 3 2 Host Bus Interface Signals 1D13706 X31B G 016 02 The Host Bus Interface requires the following signals CLKI is a clock input required by the S1D13706 Host Bus Interface as a source fo
28. RD connects to MEMRD the read enable signal from the NEC VR4181A and must be driven low when the NEC VR4181A is reading data from the S1D13706 WAIT connects to IORDY and is a signal which is output from the S1D13706 which indicates the NEC VR4181A must wait until data is ready read cycle or accepted write cycle on the host bus Since VR4181A accesses to the S1D13706 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13706 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS and Read Write RD WR signals are not used in this implemen tation of the NEC VR4181A interface using the Generic 2 Host Bus Interface These pins must be tied high connected to HIO Vpp Interfacing to the NEC VR4181A Microprocessor 1D13706 Issue Date 01 02 23 X31B G 008 02 Page 12 Epson Research and Development Vancouver Design Center 4 VR4181A to S1D13706 Interface 4 1 Hardware Description The NEC VR4181A microprocessor is specifically designed to support an external LCD controller by providing the internal address decoding and control signals necessary By using the Generic 2 Host Bus Interface no glue logic is required to interface the S1D13706 to the NEC VR4181A A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle
29. The 256 bit GCP data is organized into 32 8 bit data registers each addressable by the D TFD GCP Index register REG 28h GCP index 00h GCP index 01h GCP index 1Fh GCP data register window GCP data register window GCP data register window je7 pefbs Sf bofe7 o 0 1 2 e 7 8 GCP bit chain 256 falling edge of RES Figure 5 1 GCP Data Connecting to the Epson D TFD Panels 1D13706 Issue Date 01 02 23 X31B G 012 03 Page 20 5 2 Programming GCP Data 1D13706 X31B G 012 03 To program the GCP Data bit chain the following procedure must be followed 1 ZA 3 4 Epson Research and Development Vancouver Design Center Program the D TFD GCP Index Register REG 28h Program the D TFD GCP Data Register REG 2Ch Increment the D TFD GCP Index Register REG 28h Return to step 2 and repeat until all 32 8 bit segments are programmed The following values must be programmed into the GCP data bit chain for the LF37SQT and LF26SCT D TED panels Table 5 1 GCP Data Bit Chain Values for LF37SQT and LF26SCT Index Value Index Value Index Value Index Value 00h 52h 08h 49h 10h 2Ah 18h 00h 01h 2Ah 09h 24h 11h 52h 19h 00h 02h 92h OAh 92h 12h 49h 1Ah 00h 03h 22h OBh 49h 13h 24h 1Bh 00h 04h 48h OCh 49h 14h 48h 1Ch 00h 05h 88h ODh 4Ah 15h 84h 1Dh 00h 06h 91h OEh 52h 16h 00h 1Eh 00h 07h 22h OFh A5h 17h 00h 1Fh 00h Connect
30. The following table shows the configuration required for this implementation of a S1D13706 to Motorola MC68030 microprocessor Table 4 1 Summary of Power On Reset Configuration Options S1D13706 Pin value on this pin at the rising edge of RESET is used to configure 1 0 Name 1 0 CNF 2 0 CNF3 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs CNF4 Little Endian bus interface CNF5 Active low WAIT CNF 7 6 see Table for recommended settings configuration for MC68030 microprocessor Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 recommended setting for MC68030 microprocessor 4 3 Register Memory Mapping The MC68030 IDP board uses the first 256M bytes of address space therefore the S1D13706 can be mapped anywhere beyond this boundary The S1D13706 uses two 128K byte blocks which are selected using M R from the address decoder The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block Registers were located at memory location 10A0 0000h and the display buffer at memory location 10E0 0000h The address space for the S1D13706 is user dependent Interfacing to the Motorola MC68030 Microprocessor S1D13706 Issue Date 01 02 23 X31B G 013 02 Page 14 5 Software 1D13706 X31B G 013 02 Epson Research and Development
31. VT 1 Frame gt PS yy VPW E FPFRAME VDPS VDP FPLINE di L DRDY FPDAT 17 0 A UR HT 1 Line 4 gt ee PW FPLINE FPSHIFT DRDY HDPS HDP 4 pie gt FPDAT 17 0 invalid E CENK invalid Figure 6 27 Generic TFT Panel Timing VT Vertical Total REG 19h bits 1 0 REG 18h bits 7 0 1 lines VPS FPFRAME Pulse Start Position REG 27h bits 1 0 REG 26h bits 7 0 lines VPW FPFRAME Pulse Width REG 24h bits 2 0 1 lines VDPS Vertical Display Period Start Position REG 1Fh bits 1 0 REG 1Eh bits 7 0 lines VDP Vertical Display Period REG 1Dh bits 1 0 REG 1Ch bits 7 0 1 lines HT Horizontal Total REG 12h bits 6 0 1 x 8 pixels HPS FPLINE Pulse Start Position REG 23h bits 1 0 REG 22h bits 7 0 1 pixels HPW FPLINE Pulse Width REG 20h bits 6 0 1 pixels HDPS Horizontal Display Period Start Position REG 17h bits 1 0 REG 16h bits 7 0 5 pixels HDP Horizontal Display Period REG 14h bits 6 0 1 x 8 pixels For TFT panels the HDP must be a minimum of 8 pixels and must be increased by multiples of 8 Panel Type Bits REG 10h bits 1 0 01 TFT FPLINE Pulse Polarity Bit REG 24h bit 7 O active low FPFRAME Polarity Bit REG 20h bit 7 O active low S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Vancouver Design Center 6 4 9 9 12 18 Bit TFT Panel Timi
32. Y JA 1 Figure 6 14 Generic STN Panel Timing 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 59 Vancouver Design Center VT Vertical Total REG 19h bits 1 0 REG 18h bits 7 0 1 lines VPS FPFRAME Pulse Start Position 0 lines because REG 27h bits 1 0 REG 26h bits 7 0 0 VPW FPFRAME Pulse Width REG 24h bits 2 0 1 lines VDPS Vertical Display Period Start Position 0 lines because REG 1 Fh bits 1 0 REG 1Eh bits 7 0 0 VDP Vertical Display Period REG 1Dh bits 1 0 REG 1Ch bits 7 0 1 lines HT Horizontal Total REG 1 2h bits 6 0 1 x 8 pixels HPS FPLINE Pulse Start Position REG 23h bits 1 0 REG 22h bits 7 0 1 pixels HPW FPLINE Pulse Width REG 20h bits 6 0 1 pixels HDPS Horizontal Display Period Start Position 22 pixels because REG 17h bits 1 0 REG 16h bits 7 0 0 HDP Horizontal Display Period REG 14h bits 6 0 1 x 8 pixels For passive panels the HDP must be a minimum of 32 pixels and must be increased by multiples of 16 HPS must comply with the following formula HPS gt HDP 22 HPS HPW lt HT Panel Type Bits REG 10h bits 1 0 00b STN FPFRAME Pulse Polarity Bit REG 24h bit 7 1 active high FPLINE Polarity Bit REG 20h bit 7 1 active high MOD is the MOD signal when REG 11h bits 5 0 0 MOD toggles every
33. 12 Table 4 1 Summary of Power On Reset Configuration Options 12 List of Figures Figure 4 1 Typical Implementation of 8 bit Processor to S1D13706 Interface 11 Interfacing to 8 bit Processors S1D13706 Issue Date 01 02 23 X31B G 015 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to 8 bit Processors X31B G 015 02 Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction Interfacing to 8 bit Processors Issue Date 01 02 23 This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and 8 bit processors This document is not intended to cover all possible implementation but provides a generic example of how such an interface can be accomplished The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com 1D13706 X31B G 015 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to an 8 bit Processor 2 1 The Generic 8
34. 2 ee ee 40 Hitachi SH 3 Interface Timing 2 2 ee ee 42 Motorola MC68K 1 Interface Timing 2 2 0 00 00008 44 Motorola MC68K 2 Interface Timing 2 20 00 0 0000087 46 Motorola REDCAP2 Interface TiMid8 o 0020000000 48 Motorola DragonBall Interface with DTACK TiMid8 50 Motorola DragonBall Interface without DTACK Timing 52 Passive TFT Power On Sequence Timing o 54 Passive TFT Power Off Sequence TiMiN8 55 Panel Timing Parameters ssri at t arani a we he ee ee en 56 Generic STN Panel Timing 58 Single Monochrome 4 Bit Panel Timing o 60 Single Monochrome 4 Bit Panel A C Timing 0 0 61 Single Monochrome 8 Bit Panel Timing o 62 Single Monochrome 8 Bit Panel A C TiMid8 o o 63 Single Color 4 Bit Panel Timing e 64 Single Color 4 Bit Panel A C Timing 65 Single Color 8 Bit Panel Timing Format l o o 66 Single Color 8 Bit Panel A C Timing Formatl o oo 67 Single Color 8 Bit Panel Timing Format 2 o e 68 Single Color 8 Bit Panel A C Timing Format2 o oo 69 Single Color 16 Bit Panel Timing e 70 Single Color 16 Bit Panel A C Timing e 71 Specifica
35. 270 SwivelView i main window sub window y end position REG 91h REG 90h og A sub window y start position y REG 89h REG 88h sub window sub window x start position Ea REGIS5h REG S4n a sub window x end position REG 8Dh REG 8Ch panel s origin Figure 8 5 Picture in Picture Plus with SwivelView 270 enabled SwivelView 270 is a mode in which both the main and sub windows are rotated 270 counter clockwise when shown on the panel The images for each window are typically placed consecutively with the main window image starting at address 0 and followed by the sub window image In addition both images must start at addresses which are dword aligned the last two bits of the starting address must be 0 Note It is possible to use the same image for both the main window and sub window To do so set the sub window line address offset registers to the same value as the main win dow line address offset registers Note The Sub Window X Start Position registers Sub Window Y Start Position registers Sub Window X End Position registers and Sub Window Y End Position registers are named according to the SwivelView 0 orientation In Swivel View 270 these registers switch their functionality as described in Section 8 2 Registers Example 8 In SwivelView 270 program the main window and sub window regis ters for a 320x240 panel at 4 bpp with the sub w
36. Q Quits the program P on off Controls the power on off state of the S1D13706 Where on Powers on the chip off Powers off the chip R addr count Reads a certain number of bytes from the specified address If no value is provided for count it defaults to 10h Where addr Address from which byte s are read hex count Number of bytes to be read hex RD addr count Reads a certain number of dwords from the specified address If no value is provided for count it defaults to 10h Where addr Address from which dword s are read hex count Number of dwords to be read hex 13706PLAY Diagnostic Utility 1D13706 Issue Date 01 02 23 X31B B 003 02 Page 8 1D13706 X31B B 003 02 Epson Research and Development Vancouver Design Center RW addr count Reads a certain number of words from the specified address If no value is provided for count it defaults to 10h Where addr Address from which word s are read hex count Number of words to be read hex Txx Tests VNDP read for xx seconds This option was developed for testing purposes only and is not supported Where XX The number of seconds VNDP is tested decimal V Calculates the current frame rate from the VNDP count W addr data Writes byte s of data to specified memory address Where addr Address data is written to data Data to be written hex Data can be a list of bytes to be repeated for the duration of the write To use d
37. Table 4 1 List of Connections from REDCAP2 ADM to S5U13706B00C REDCAP2 Signal Name REDCAP2ADS Connector and Pin Name S1D13706 Signal Name A17 P9 34 M R A16 P9 33 AB20 A15 P9 32 AB19 A14 P9 31 AB18 A13 P9 30 AB17 A12 P9 29 AB16 A11 P9 28 AB15 A10 P9 27 AB14 AQ P9 26 AB13 A8 P9 25 AB12 A7 P9 24 AB11 A6 P9 23 AB10 A5 P9 22 AB9 A4 P9 21 AB8 A3 P9 20 AB7 A2 P9 19 AB6 Al P9 18 AB5 AO P9 17 AB4 D15 P9 16 DB15 D14 P9 15 DB14 D13 P9 14 DB13 D12 P9 13 DB12 D11 P9 12 DB11 D10 P9 11 DB10 D9 P9 10 DB9 D8 P9 9 DB8 D7 P9 8 DB7 D6 P9 7 DB6 D5 P9 6 DB5 D4 P9 5 DB4 D3 P9 4 DB3 D2 P9 3 DB2 D1 P9 2 DB1 DO P9 1 DBO RES_OUT P24 6 RESET Interfacing to the Motorola RedCap2 DSP With Integrated MCU Issue Date 01 02 23 1D13706 X31B G 014 02 Page 14 1D13706 X31B G 014 02 Epson Research and Development Vancouver Design Center Table 4 1 List of Connections from REDCAP2 ADM to S5U13706B00C Continued REDCAP2 Signal Name REDCAP2ADS Connector and Pin Name S1D13706 Signal Name CLKO P24 3 BUSCLK CST P9 40 CS R W P9 47 RD WR OE P9 48 RD EBT P9 46 WEO EBO P9 45 WE1 Gnd P24 20 P9 50 Vss Note In order for the S5U13706B00C evaluation board to work with the ADM pin 5 and pin 13 of U28 on the ADM must be connected to Vpp This ensures that the DIR signa
38. e Epson Electronics America Website http www eea epson com S1D13706 Interfacing to the Intel StrongARM SA 1110 Microprocessor X31B G 019 02 Issue Date 02 06 26 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epson electronics de 7 2 Intel StrongARM SA 1110 Processor INTEL Intel Customer Support ICS for StrongARM 800 628 8686 Website for StrongARM Processor http developer intel com design strong Interfacing to the Intel StrongARM SA 1110 Microprocessor Issue Date 02 06 26 Page 19 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue
39. gt o ty Tosc Figure 6 1 Clock Input Requirements Table 6 1 Clock Input Requirements for CLKI when CLKI to BCLK divide gt 1 2 0V 3 3V Symbol Parameter Units Min Max Min Max fosc Input Clock Frequency CLKI 40 100 MHz Tosc Input Clock period CLKI fosc Tfosc ns towy INput Clock Pulse Width High CLKI 4 5 4 5 ns tow Input Clock Pulse Width Low CLKI 45 4 5 ns t Input Clock Fall Time 10 90 5 5 ns t Input Clock Rise Time 10 90 5 5 ns Note Maximum internal requirements for clocks derived from CLKI must be considered when determining the frequency of CLKI See Section 6 1 2 Internal Clocks on page 35 for internal clock requirements Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 34 Epson Research and Development Vancouver Design Center Table 6 2 Clock Input Requirements for CLKI when CLKI to BCLK divide 1 2 0V 3 3V Symbol Parameter Units Min Max Min Max fosc _ nput Clock Frequency CLKI 20 66 MHz Toso Input Clock period CLKI Tose Wosc ns town Input Clock Pulse Width High CLKI 3 3 ns tow Input Clock Pulse Width Low CLKI 3 3 ns t Input Clock Fall Time 10 90 5 5 ns t Input Clock Rise Time 10 90 5 5 ns Note Maximum internal requirements for clocks derived from CLKI mu
40. set high for read cycles and low for write cycles e AT 0 3 Address Type Signals provides more detail on the type of transfer being attempted When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MPC821 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks Figure 2 1 Power PC Memory Read Cycle illustrates a typical memory read cycle on the Power PC system bus SYSOLK f A 0 31 X X TSIZ 0 1 AT O 3 ne x ooon ITLL EEO Same wen To Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 1 Power PC Memory Read Cycle Interfacing to the Motorola MPC821 Microprocessor 1D13706 Issue Date 01 02 23 X31B G 009 02 Page 10 Epson Research and Development Vancouver Design Center Figure 2 2 Power PC Memory Write Cycle illustrates a typical memory write cycle on the Power PC system bus A 0 31 X RD WR TSIZ 0 1 AT O 3 T D 0 31 Valid Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 Power PC Memory Write Cycle If an error occurs TEA Transfer Error Acknowl
41. 11 1D13706 X31B G 005 02 Interfacing to the PC Card Bus Issue Date 01 02 23 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The S1D13706 Generic 2 Host Bus Interface requires the following signals from the PC Card bus CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock Since the PC Card signalling is independent of any clock CLKI can come from any oscillator already implemented For example the source for the CLKI2 input of the S1D13706 may be used The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the PC Card address A 16 0 and data bus D 15 0 respectively CNF4 must be set to select little endian mode Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space M R memory register selects between memory or register accesses This signal may be connected to an address line allowing system address A17 to be connected to the M R line WE1F is the high byte enable for both read and write cycles and connects to the PC Card high byte chip select signal CE2 WEO connects to WE the write enable signal form the PC Card bus and must be driven low when the PC Card bus is writing data to the S1D13706 RD connects to OE the read enable
42. 3 1 Host Bus Interface Pin Mapping 1D13706 X31B G 007 02 The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping ene NEC VR4102 4111 AB 16 0 ADD 16 0 DB 15 0 DAT 15 0 WE1 SHB CS LCDCS M R ADD17 CLKI BUSCLK BS connect to HIO Vpp RD WR connect to HIO Vpp RD RD WEO WR LCDRDY WAIT RESET system RESET Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 01 02 23 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface requires the following signals CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example BUSCLK from the NEC VR4102 4111 is used for CLKI The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the NEC VR4102 4111 address bus ADD 16 0 and data bus DAT 15 0 respectively CNF4 must be set to select little endian mode Chip Select CS must be driven low by LCDCS whenever the S1D 13706 is accessed by the VR4102 4111 M R memory register selects between memory or register accesses This signal may be connected to an address line allowing system address ADD17 to be connected to the M R line WE1 connects to SHB the
43. 6 2 7 Motorola REDCAP2 Interface Timing Epson Research and Development Vancouver Design Center CKO M R A 16 1 RW CSn EBO EB1 write D 15 0 write OE ti t2 lt f Teko Hi Z t6 t7 t8 q Hi Z VALID t10 EBO EB1 read D 15 0 read Hi Z t11 t gt t13 t12 VALID Note CSn may be any of CS0 CS4 1D13706 X31B A 001 08 Note Figure 6 8 Motorola REDCAP2 Interface Timing For further information on implementing the REDCAP2 microprocessor see Interfac ing to the Motorola REDCAP2 DSP with Integrated MCU document number X31B G 013 xx Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 49 Vancouver Design Center Table 6 11 Motorola REDCAP2 Interface Timing Symbol Parameter MiB od Max Win 3V Max Units fcko Bus Clock frequency 17 17 MHz Tcko Bus Clock period 1 fcko 1 fcko ns ti Bus Clock pulse width low 26 26 ns t2 Bus Clock pulse width high 26 26 ns t3 A 16 1 M R R W CSn setup to CKO rising edge 1 1 ns t4 A 16 1 M R RAW CSn hold from CKO rising edge 0 0 ns t5a CSn asserted for MCLK BCLK 8 8 Toko t5b CSn asserted for MCLK BCLK 2 10 10 Toko t5c CSn asserted for MCLK BCLK 3 13 13 Toko t5d
44. DEnablePreferVmem to CDEFINES CDEFINES DEnablePreferVmem This step causes the system to redraw the main display upon power on This step is only required if display memory loses power when Windows CE is shut down If dis play memory is kept powered up set the S1D13706 in powersave mode then the dis play data will be maintained and this step can be skipped Search for the file PROJECT REG in your Windows CE directories and inside PROJECT REG find the key PORepaint Change PORepaint as follows PORepaint dword 2 S1D13706 X31B E 006 01 Page 16 Comments 1D13706 X31B E 006 01 Epson Research and Development Vancouver Design Center The display driver is CPU independent allowing use of the driver for several Windows CE Platform Builder supported platforms By default the 13706CFG program assumes PCI addressing for the S5U13706B00C evaluation board This means that the display driver will automatically locate the S1D13706 by scanning the PCI bus currently only supported for the CEPC platform If you select the address option Other and fill in your own custom addresses for the registers and video memory then the display driver will not scan the PCI bus and will use the specific addresses you have chosen If you are running 13706CFG EXE to produce multiple MODE tables make sure you change the Mode Number in the WinCE tab for each mode table you generate The display driver supports multiple mode tables
45. HPS HDP HDPS 4 if negative add t3 min 8 t14 ni HDPS HPS 14 nin if negative add t3min Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 64 6 4 4 Single Color 4 Bit Panel Timing Epson Research and Development Vancouver Design Center VDP VNDP FPFRAME FPLINE I fl f fl fl fl LJ fl fl fl f fl fl DRDY MOD FPDAT 7 4 X Invalid LINE1 X LINE2 X LINES X LINE4 XLINE239XLINE240X Invalid LINE1 X LINE2 FPLINE i DRDY MOD HDP HNDP lt gt lt gt 5Ts 5Ts 5Ts 5Ts 5Is 5Ts Ts 5Ts 5Ts 5Ts SIS FPSHIFT AAA I EA ase l STs STs 5Ts Ts 5Ts 2 5Ts Ts Ts EPDAT7 nas XA R1X 1 62 X 1 83 X X Y 1 8319 pee X FPDATS RA SSS e FPDAT5 rala 4 B1 X 1 R3 Y 1 G4X Y Y Y Xx 1 6320 Invalid X FPDAT4 Invalid X1 R2X_1 G3X_1 B4 X YX Y 1 B320X Invalid x X Notes FPSHIFT uses extended low states in order to process 8 pixels in 6 FPSHIFT clocks Ts Pixel clock period PCLK Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 6 19 Single Color 4 Bit Panel Timing REG 19h bits 1 0 REG 18h bits 7 0 REG 1Dh bits 1 0 REG 1Ch bits 7 0 Lines VDP Vertical Display Period REG 1 Dh bits 1 0 REG 1Ch bits 7 0 1 Lines VNDP Vertical Non Display Period VT VDP HDP Horizontal Dis
46. REG 84h PIP Window X Start Position Register 0 Read Write 7 6 PIP Window X Start Position Bits 7 0 5 4 3 2 1 0 REG 85h PIP Window X Start Position Register 1 Read Write T PIP Window X Start Position Bits 9 8 5 4 8 2 1 0 n a bits 9 0 1D13706 X31B A 001 08 PIP Window X Start Position Bits 9 0 These bits determine the X start position of the PIP window in relation to the origin of the panel Due to the S1D13706 SwivelView feature the X start position may not be a horizontal position value only true in 0 and 180 SwivelView For further information on defining the value of the X Start Position register see Section 13 Picture in Picture Plus PIP on page 143 The register is also incremented differently based on the Swivel View orientation For 0 and 180 SwivelView the X start position is incremented by x pixels where x is relative to the current color depth Table 8 11 32 bit Address Increments for Color Depth Color Depth Pixel Increment x 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 For 90 and 270 SwivelView the X start position is incremented in 1 line increments Depending on the color depth some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels Note These bits have no effect unless the PIP Window Enable bit is set to 1
47. The S1D13706 Generic 2 Host Bus Interface has a maximum BCLK of 50MHz Therefore if the processor clock is higher than 100MHz either divide the BCLK input using the S1D13706 configuration pins CNF 7 6 see Table 4 2 CLKI to BCLK Divide Selec tion or set SDCLK1 SDCLK2 to CPU clock divided by four using the DRAM Refresh Control Register MDREFR bit 26 1 for SDCLK2 MDREFR bit 22 1 for SDCLK1 Interfacing to the Intel StrongARM SA 1110 Microprocessor 1D13706 Issue Date 02 06 26 X31B G 019 02 Page 16 Epson Research and Development Vancouver Design Center 4 4 Register Memory Mapping The S1D13706 is a memory mapped device The SA 1110 uses the memory assigned to a chip select nCS4 in this example to map the 1D13706 internal registers and display buffer The S1D13706 uses two 128K byte blocks which are selected using A17 from the SA 1110 A17 is connected to the S1D13706 M R pin The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block Each variable latency IO chip select is assigned 128M Bytes of address space Therefore if nCS4 is used the S1D13706 registers will be located at 4000 0000h and the display buffer will be located at 4002 0000h These blocks are aliased over the entire 128M byte address space Note If aliasing is not desirable the upper addresses must be fully decoded 1D13706 Interfacing to the Intel StrongARM SA 1110 Microproc
48. next to it The expanded view will contain the item default Right click on default and select Properties A properties win dow will appear c Select the C C compiler tab to display the command switches used in the build Remove the ansi switch from the line that con tains g mpentium ansi nostdinc DRW_MULTI_THREAD Refer to GNU ToolKit user s guide for details 8 Compile the VxWorks image Select the Files tab in the Tornado Workspace window Right click on Sbpp files or 16bpp files and select Dependencies Click on OK to regenerate project file dependencies for All Project files Right click on Sbpp files or 16bpp files and select ReBuild All vxWorks to build VxWorks 9 Copy the VxWorks file to the diskette From a command prompt or through the Windows interface copy the file x 13706 8bpp default vxW orks or x 13706 1 6bpp default vx Works to the bootable disk created in step 4 10 Start the VxWorks demo Boot the target PC with the VxWorks bootable diskette to run the UGL demo program automatically Wind River UGL v1 2 Display Drivers 1D13706 Issue Date 01 02 23 X31B E 003 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Wind River UGL v1 2 Display Drivers X31B E 003 02 Issue Date 01 02 23 EPSON 1D13706 Embedded Memory L
49. o ee a E e a 92 S1D13706 Internal Clock Requirements o o e o 94 SID13706 Register Setir ia a a aa 95 MCLK Divide Selecti0d o 97 PCEK Divide Selection seco eto whe Pa ed be Fee de oe Old See 98 PEER Source Selection bl 4 34 vad tse de ed e bl ney eek ee ah ee 98 Panel Data Width Selection 2 2 2 o o e 102 Active Panel Resolution Selection o ee 102 ECDPanel Type Selection a bee la 102 Inverse Video Mode Select Options o o e 110 LCD Bit per pixel Selection 2 eop a o 111 SwivelView M Mode Select Opuons 4 8 a Me ai a Sch Y 112 32 bit Address Increments for Color Depth o o o 116 32 bit Address Increments for Color Depth o o o 117 32 bit Address Increments for Color Depth o o o 118 32 bit Address Increments for Color Depth o o o 119 PWM Clock Control woo pd dl ll oe ad ee 126 EN Pulse Controls ke dh dd e a a id e e aE da 127 PWM Clock Divide Select Options o o e e e 128 CV Pulse Divide Select Options o 128 PWMOUT Duty Cycle Select Options o o o 129 Power Save Mode Function Summary 20 0000002 149 Hardware Functional Specification Issue Date 01 11 13 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 4 1
50. on page 143 The register is also incremented differently based on the Swivel View orientation For 0 and 180 SwivelView the Y end position is incremented in 1 line increments For 90 and 270 SwivelView the Y end position is incremented by y pixels where y is relative to the current color depth Table 8 14 32 bit Address Increments for Color Depth Color Depth Pixel Increment y 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 Depending on the color depth some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels Note These bits have no effect unless the PIP Window Enable bit is set to 1 REG 71h bit 4 2 The effect of REG 84h through REG 91h takes place only after REG 91h is written and at the next vertical non display period Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 120 Epson Research and Development Vancouver Design Center 8 3 7 Miscellaneous Registers Power Save Configuration Register REG AOh Read Write Vertical Non Memory Display n a Controller nla Power Save Period Status Power Save Mode Enable RO Status RO 7 5 4 3 2 1 0 bit 7 Vertical Non Display Period Status This is a read only status bit When this bit 0 the LCD panel output is in a Vertical Display Period When this bit 1 the LCD panel output is in a Vertical
51. return the same value Parameters None Return Value The return value is the size of the available amount of display buffer memory directly accessible to an application int seEnableHardwareDisplaySwapping int Enable Description The S1D13706 requires 16 bits per pixel data to be in little endian format On big endian systems the software or hardware needs to swap this data seEnableHardwareDisplay Swapping is intended to be used on big endian systems where system performance can be improved by utilizing hardware swapping of display memory bytes in 16 bits per pixel If the system is not big endian or if the bits per pixel is not 16 this function will not enable hardware display swapping However a flag is set in the HAL and if seSetMode is later called to set the bits per pixel to 16 in a big endian system hardware display swap ping is enabled Also if seSetMode is called to set the bits per pixel to a value other than 16 then hardware display swapping is disabled Parameters Enable Call with Enable set to TRUE to enable hardware display swapping Call with Enable set to FALSE to disable hardware display swapping Return Value ERR_OK Function completed successfully ERR_FAILED Returned when caller requested that hardware display swapping be enabled but system not in 16 bits per pixel or system is not big endian S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Developmen
52. tm t10 t12 t13 Spt gies gt Hi Z Hi Z I t14 P t15 Hi Z Hi Z t1 t17 d gt gt e Hi Z VALID Hi Z S1D13706 X31B A 001 08 Figure 6 5 Hitachi SH 3 Interface Timing Hardware Functional Specification Issue Date 01 11 13 Issue Date 01 11 13 Epson Research and Development Page 43 Vancouver Design Center Table 6 8 Hitachi SH 3 Interface Timing Symbol Parameter MIE omy Max MIR 2 Max Unit fckio Bus Clock frequency 20 66 MHz Texio Bus Clock period W cxio 1 fckio ns t1 Bus Clock pulse width low 22 5 6 8 ns t2 Bus Clock pulse width high 22 5 6 8 ns t3 A 16 1 M R RD WR setup to CKIO 0 1 ns t4 CSni high setup to CKIO 0 1 ns t5 BS setup 3 1 ns t6 BS hold 7 2 ns t7 CSn setup 0 1 ns t8 A 16 1 M R RD WR hold from CS 0 0 ns t9a RD or WEn asserted for MCLK BCLK max MCLK 50MHz 8 5 8 5 Tckio t96 RD or WEn asserted for MCLK BCLK 2 11 5 11 5 Toxo t9c RD or WEn asserted for MCLK BCLK 3 13 5 13 5 Tekio t9d RD or WEn asserted for MCLK BCLK 4 18 5 18 5 Tokio t10 Falling edge RD to D 15 0 driven read cycle 5 24 3 12 ns t11 Rising edge CSn to WAIT high impedance 4 24 2 10 ns t12 Falling edge CSn to WAIT driven low 3 24 2 12 ns t13 CKIO to WAIT delay 6 45 4 18 ns t14 D 15 0 setup to 2 CKIO after BS write c
53. www mot com e Epson Electronics America website http www eea epson com Interfacing to the Motorola MC68030 Microprocessor 1D13706 Issue Date 01 02 23 X31B G 013 02 Page 16 7 Technical Support 7 1 EPSON LCD CRT Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MC68030 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor S1D13706 X31B G 013 02 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Motorola MC68030 Microprocessor Issue Date 01 02 23 EPSON 1D13706 Embedded M
54. 16 4 Look Up Table LUT 0 ee ee es id a e a oe ae ee 17 4 1 Registers tO es A a a RA a e ls OT 4 1 1 Look Up Table Write sevice PR hg Bid wah OA 6 ae 17 4 1 2 Look Up Table Read Registers o o o 18 4 2 Look Up Table Organization 2 2 22 19 4 2 1 Gray Shade Modes 0s ecr ee ee ee eee 20 4 222 Color Modes 2 acs 6 ke a RU wed MO tak tyke blag Pa ted ne Ge nae 22 5 Power Save Mode gioi ige i ahin e ah ke hese sat Se ec ame eS se ies ae 26 Dil OVERVIEW y de oe ee oe Be ee a Gee Gm oe me oon amp 2 26 5 2 Registers Ds o as ga at o Des dt Hane ode ae 5 2 1 Power Save Mode Enable o o e e 27 5 2 2 Memory Controller Power Save Status o e 27 5 3 Enabling Power Save Mode 2 ee ee ee 28 5 4 Disabling Power Save Mode 2 a o e 28 6 LCD Power Sequencing eee ee 4 29 6 1 Enabling the LCD Panel 30 6 2 Disabling the LCD Panel aaa 30 T SWivelVi W s soser as AA A A AR A ee 31 PAS RCSISIEDS aar rain a oo shoes A A a A o a a a R Examples lt p oY o ge ok es Bo Ge Ee a ee ee etd Ge O 7 3 Limitations de pate By ee od ae coe te GS inte ite ay ee I a ee 0 TIT CS Mivel Vie WO and 180 o sls el Sw bee ES EG doe eB as 8 36 7 3 2 SwivelView 90 and 270 36 8 Picture In Picture PluS 0 ects ee b
55. 1D13706 Issue Date 01 02 23 X31B G 010 02 Page 16 5 Software 1D13706 X31B G 010 02 Epson Research and Development Vancouver Design Center Test utilities and Windows CE v2 11 2 12 display drivers are available for the S1D13706 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 23 Epson Research and Development Page 17 Vancouver Design Center 6 References 6 1 Documents Motorola Inc MCF5307 ColdFire Integrated Microprocessor User s Manual Motorola Publication no MCF5307UM available on the Internet at http www mot com SPS HPESD prod coldfire 5307UM html Epson Research and Development Inc 1D 3706 Hardware Functional Specification document number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx Epson Research and Development Inc 1D 3706 Programming Notes and Examp
56. 2 1 0 bits 7 0 CV Pulse Burst Length Bits 7 0 The value of this register determines the number of pulses generated in a single CV Pulse burst Number of pulses in a burst ContentsOfThisRegister 1 PWMOUT Duty Cycle Register REG B3h Read Write PWMOUT Duty Cycle Bits 7 0 7 6 5 4 3 2 1 0 bits 7 0 PWMOUT Duty Cycle Bits 7 0 This register determines the duty cycle of the PWMOUT output Table 8 19 PWMOUT Duty Cycle Select Options PWMOUT Duty Cycle 7 0 PWMOUT Duty Cycle 00h Always Low 01h High for 1 out of 256 clock periods 02h High for 2 out of 256 clock periods FFh High for 255 out of 256 clock periods Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 130 Epson Research and Development Vancouver Design Center 9 Frame Rate Calculation The following formula is used to calculate the display frame rate f FrameRate ed lt Soares HT x VT Where fpc g PClk frequency Hz HT Horizontal Total REG 12h bits 6 0 1 x 8 Pixels VT Vertical Total REG 19h bits 1 0 REG 18h bits 7 0 1 Lines 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Vancouver Design Center 10 Display Data Formats Page 131 The following diagrams show the display mode data formats for a little endian system 1 bpp Byte 0 Byte 1
57. 2 11 5 11 5 ToLk t7c RDO RD1 WEO WE1 asserted for MCLK BCLK 3 13 5 13 5 ToLk t7d RDO RD1 WEO WE1 asserted for MCLK BCLK 4 17 5 17 5 ToLk t8 RDO RD1 WEO WE1 setup to CLK rising edge 2 1 ns 19 Falling edge of either RDO RD1 or WEO WE1 to WAIT 5 31 3 15 he driven low t10 Rising edge of either RDO RD1 or WEO WE1 to WAIT 5 34 3 13 ee high impedance 11 D 15 0 setup to third CLK rising edge where CS 0 and 4 0 is WEO WE1 0 write cycle see note 1 t12 D 15 0 hold from WAIT rising edge write cycle 1 0 ns t13 RDO RD1 falling edge to D 15 0 driven read cycle 4 27 3 14 ns t14 WAIT rising edge to D 15 0 valid read cycle 0 2 ns t15 RDO RD1 rising edge to D 15 0 high impedance read cycle 3 29 3 11 ns 1 t11 is the delay from when data is placed on the bus until the data is latched into the write buffer Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 38 6 2 2 Generic 2 Interface Timing e g ISA Epson Research and Development Vancouver Design Center SA 16 0 M R SBHE CS MEMR MEMW IOCHRDY SD 15 0 write SD 15 0 read ti t2 TBUSCLK r BUSCLK j a t3 t4 t5 a 1 4 t7 gt t8 t9 t10 N 811 t12 t14 t13 gt gt gt a VALID S1D13706 X31B A 001 08 Figure
58. 2 2 Overview REDCAP 2 uses a 22 bit address bus A 21 0 and 16 bit data bus D 15 0 All IO is synchronous to a square wave reference clock called CKO The CKO source can be the DSP clock or the MCU clock and is selected disabled in the Clock Control Register CKCTL REDCAP2 can generate up to 6 independent chip select outputs Each chip select has a memory range of 16M bytes and can be independently programmed for wait states and port size Note REDCAP2 does not provide a wait or termination acknowledge signal to external devic es Therefore all external devices must guarantee a fixed cycle length 2 3 Bus Transactions The chip initiates a data transfer by placing the memory address on address lines AO through A21 Several control signals are provided with the memory address e R W set high for read cycles and low for write cycles e EBO active low signal indicates access to data byte 0 D 15 8 during read or write cycles e EB1 active low signal indicates access to data byte 1 D 7 0 during read or write cycles e OE active low signal indicates read accesses and enables slave devices to drive the data bus 1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 02 Issue Date 01 02 23 Epson Research and Development Page 9 Vancouver Design Center Figure 2 1 REDCAP2 Memory Read Cycle on page 9 illustrates a typical memory read cycle on the REDCAP2 bus
59. 89 Clock Selection sj2 pach A Be A A Pe A ES 93 Display Data Byte Word Swap o oo 112 PWM Clock CV Pulse Block Diagram o o 126 4 8 16 Bit Per Pixel Display Data Memory Organization 131 1 Bit per pixel Monochrome Mode Data Output Path 132 2 Bit per pixel Monochrome Mode Data Output Path 132 4 Bit per pixel Monochrome Mode Data Output Path 133 8 Bit per pixel Monochrome Mode Data Output Path 133 1 Bit Per Pixel Color Mode Data Output Path o 134 2 Bit Per Pixel Color Mode Data Output Path o 135 4 Bit Per Pixel Color Mode Data Output Path o 136 8 Bit per pixel Color Mode Data Output Path o oo 137 Relationship Between The Screen Image and the Image Refreshed in 90 SwivelView 138 Relationship Between The Screen Image and the Image Refreshed in 180 SwivelView 140 Relationship Between The Screen Image and the Image Refreshed in 270 SwivelView 141 Picture in Picture Plus with SwivelView disabled 143 Picture in Picture Plus with SwivelView 90 enabled 144 Picture in Picture Plus with SwivelView 180 enabled 144 Picture in Picture Plus with SwivelView 270 enabled 145 Byte swapping for 16 Bpp e 147 Byte swapping for 1 2 4 8 BPP o
60. CLK t5 t6 FPDAT 17 0 bik p2k o3k X X XD160 4 GPIO3 SPL GPIO1 CLS t12 OoOo GPIOO PS t13 GPIO2 REV Figure 6 30 160x160 Sharp Direct HR TFT Panel Horizontal Timing S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 77 Vancouver Design Center Table 6 24 160x160 Sharp Direct HR TFT Horizontal Timing Symbol Parameter Min Typ Max Units t1 FPLINE start position 13 Ts note 1 t2 Horizontal total period 180 220 Ts 13 FPLINE width 2 Ts t4 FPSHIFT period 1 Ts t5 Data setup to FPSHIFT rising edge 0 5 Ts t6 Data hold from FPSHIFT rising edge 0 5 Ts t7 Horizontal display start position 5 Ts t8 Horizontal display period 160 Ts t9 FPLINE rising edge to GPIO3 rising edge 4 Ts t10 GPIO3 pulse width 1 Ts t11 GPIO1 GPIO0 pulse width 136 Ts t12 GPIO1 rising edge GPIOO falling edge to FPLINE rise edge 4 Ts t13 GPIO2 toggle edge to FPLINE rise edge 10 Ts 1 Ts pixel clock period 2 tityp REG 22h bits 7 0 1 3 t2typ REG 12h bits 6 0 1 x8 4 tStyp REG 20h bits 6 0 1 5 t7typ REG 16h bits 7 0 5 REG 22h bits 7 0 1 6 t8typ REG 14h bits 6 0 1 x8 Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 78 Epson Research and Dev
61. Epson Research and Development Page 13 Vancouver Design Center The Generic 2 Host Bus Interface control signals of the S1D13706 are asynchronous with respect to the S1D13706 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and CLKI2 The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum S1D13706 clock frequencies The S1D13706 also has internal clock dividers providing additional flexibility Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors S1D13706 Issue Date 01 02 23 X31B G 002 02 Page 14 4 2 S1D13706 Hardware Configuration 4 3 Memory Mapping and Aliasing 1D13706 X31B G 002 02 Epson Research and Development Vancouver Design Center The S1D13706 latches CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13706 Hardware Functional Specification document number X31B A 001 xx The table below shows the configuration settings important to the Generic 2 host bus interface used by the Toshiba TMPR3905 12 Table 4 1 Summary of Power On Reset Configuration Options S1D13706 value on this pin at the rising edge of RESET is used to configure 1 0 Pin Name 1 CNF 2 0 CNF3
62. For Generic 2 these pins are connected to D 15 0 e For SH 3 SH 4 these pins are connected to D 15 0 e For MC68K 1 these pins are connected to D 15 0 For MC68K 2 these pins are connected to D 31 16 for a 32 bit device e g MC68030 or D 15 0 for a 16 bit device e g MC68340 For REDCAP2 these pins are connected to D 15 0 For DragonBall these pins are connected to D 15 0 See Table 4 9 Host Bus Interface Pin Mapping on page 30 for summary WEO0 10 LIS HIOVDD This input pin has multiple functions For Generic 1 this pin inputs the write enable signal for the lower data byte WEO e For Generic 2 this pin inputs the write enable signal WE e For SH 3 SH 4 this pin inputs the write enable signal for data byte O WEO e For MC68K 1 this pin must be tied to HIO Vpp For MC68K 2 this pin inputs the bus size bit O SIZO For REDCAP2 this pin inputs the byte enable signal for the D 7 0 data byte EB1 For DragonBall this pin inputs the byte enable signal for the D 7 0 data byte LWE See Table 4 9 Host Bus Interface Pin Mapping on page 30 for summary WE1 11 LIS HIOVDD This input pin has multiple functions For Generic 1 this pin inputs the write enable signal for the upper data byte WE1 e For Generic 2 this pin inputs the byte enable signal for the high data byte BHE For SH 3 SH 4 this pin inputs the write en
63. Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 NEC Electronics Inc NEC Electronics Inc U S A Corporate Headquarters 2880 Scott Blvd Santa Clara CA 95050 8062 USA Tel 800 366 9782 Fax 800 729 9288 http www necel com Interfacing to the NEC VR4181A Microprocessor Issue Date 01 02 23 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Page 17 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13706 X31B G 008 02 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the NEC VR4181A Microprocessor X31 B G 008 02 Issue Date 01 02 23 EPSON 1D13706 Embedded Memory LCD Controller Interfacing to the Motorola MPC821 Microprocessor Document Number X31B G 009 02 Copyright 2001 Epson Research and Development Inc
64. PIP window x end position hone B REG 8Dh REG 8Ch PIP window x start position REG 85h REG 84h PIP window xt main window PIP window y end position f a del REG 91h REG 90h IP window y start position panel s origin REG 89h REG 88h Figure 13 3 Picture in Picture Plus with SwivelView 180 enabled 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 145 Vancouver Design Center 13 2 3 SwivelView 270 270 SwivelView M aa main window PIP window y end position REG 91h REG 90h i y A PIP window y start position Pas REG 89h REG 88h PIP window PIP window x start position a a o REG 85h REG 84h PIP window x end position REG 8Dh REG 8Ch panel s origin Figure 13 4 Picture in Picture Plus with SwivelView 270 enabled Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 146 Epson Research and Development Vancouver Design Center 14 Big Endian Bus Interface 14 1 Byte Swapping Bus Data The display buffer and register architecture of the S1D13706 is inherently little endian If a host bus interface is configured as big endian CNF4 1 at reset bus accesses are automatically handled by byte swapping all read write data to from the internal display buffer and registers Bus data byte swapping
65. R2 R3 R5 R5 R5 FPDAT1 3 D1 R3 D1 G5 Ri R2 R4 R4 R4 FPDAT2 5 D2 B2 D2 B4 RO R1 R3 R3 R3 FPDAT3 7 D3 G2 D3 RA G2 G3 G5 G5 G5 FPDAT4 9 DO D4 Do R2 D4 R3 D4 R2 Da B5 G1 G2 G4 G4 G4 FPDAT5 11 D1 D5 D1 B1 D5 G2 D5 B1 D9 RS Go G1 G3 G3 G3 FPDAT6 13 D2 D6 D2 G1 D6 B1 D6 G1 D10 G4 B2 B3 B5 B5 B5 FPDAT7 15 D3 D7 D3 R1 D7 R1 D7 R1 D11 B3 B1 B2 B4 B4 B4 FPDAT8 17 D4 G3 BO B1 B3 B3 B3 FPDAT9 19 D5 B2 RO R2 R2 R2 FPDAT10 21 D6 R2 R1 R1 Ri FPDAT11 23 D7 G1 RO RO RO FPDAT12 25 D12 R3 GO G2 G2 G2 FPDAT13 27 D13 G2 G1 G1 G1 FPDAT14 29 D14 B1 Go GO Go FPDAT15 31 D15 R1 BO B2 B2 B2 FPDAT16 4 B1 B1 B1 FPDAT17 BO BO BO FPSHIFT 33 FPSHIFT CLK XSCL DRDY 35 amp 38 MOD FPSHIFT2 MOD DRDY GCP FPLINE 37 FPLINE LP LP FPFRAME 39 FPFRAME SPS DY anp gt 8 15 20 GND PWMOUT 28 PWMOUT VLCD 30 Adjustable 24V to 8V negative LCD bias VGC 32 LCDVCC 3 3V 5 0V 12V 34 12V VDDH 36 Adjustable 20V to 40V positive LCD bias GPO 40 GPO for controlling on board LCD bias power supply on off MOD GPO Note These pin mappings use signal names commonly used for each panel type however signal names may differ between panel manufacturers The values shown in brackets represent the color components as mapped to the corresponding FPDATxx signals at the first valid edge of FPSHIFT For further FPDATxx to LCD interface mapping see S1D13706 Hardware Func
66. S9 elf The configuration values can be saved to a specific EXE file for Intel platforms or to a specific S9 or ELF file for non Intel platforms The file must have been compiled using the 13706 HAL library Checking Preserve Physical Addresses instructs 13706CFG to use the register and display buffer address values the files were previously configured with Addresses specified in the General Tab are discarded This is useful when configuring several programs for various hardware platforms at the same time For example if configuring PCI MPC and IDP based programs at the same time for a new panel type the physical addresses for each are retained This feature is primarily intended for the test lab where multiple hardware configurations exist and are being tested 13706CFG Configuration Program Issue Date 01 03 29 Epson Research and Development Page 23 Vancouver Design Center Export After determining the desired configuration Export permits the user to save the register information as a variety of ASCII text file formats The following is a list and description of the currently supported output formats a C header file for use in writing HAL library based applications a C header file which lists each register and the value it should be set to a C header file for use in developing Window CE display drivers a C header file for use in developing display drivers for other operating systems such as Linux QNX and
67. Selects the panel data width Panel data width is the number of bits of data transferred to the LCD panel on each clock cycle and shouldn t be confused with color depth which determines the number of displayed colors When the panel type is STN the available options are 4 8 and 16 bit When an active panel type is selected the available options are 9 12 and 18 bit 13706CFG Configuration Program Issue Date 01 03 29 Epson Research and Development Page 15 Vancouver Design Center Mono Color Format 2 FPLINE Polarity FPFRAME Polarity Panel Dimensions Display Total Display Start Selects between a monochrome or color panel Selects color STN panel format 2 This option is specif ically for configuring 8 bit color STN panels See the D13706 Hardware Functional Specification document number X31B A 001 xx for description of format 1 format 2 data formats Most new panels use the format 2 data format Selects the polarity of the FPLINE pulse Refer to the panel specification for the correct polarity of the FPLINE pulse Selects the polarity of the FPFRAME pulse Refer to the panel specification for the correct polarity of the FPFRAME pulse These fields specify the panel width and height A number of common widths and height are available in the selection boxes If the width height of your panel is not listed enter the actual panel dimensions into the edit field For passive panels manual
68. This design allows for easy customization of display type clocks decode addresses rotation etc by OEMs For further information on 13706CFG see the 3706CFG Configuration Program User Manual document number X31B B 001 xx Note The Linux console driver is provided as reference source code only The driver is in tended to provide a basis for OEMs to develop their own drivers for Linux This document and the source code for the Linux console drivers are updated as appro priate Please check the Epson Research and Development website at http www erd epson com for the latest revisions or before beginning any development We appreciate your comments on our documentation Please contact us via e mail at documentation erd epson com 1D13706 X31B E 004 02 Page 4 Epson Research and Development Vancouver Design Center Building the Console Driver for Linux Kernel 2 2 x 1D13706 X31B E 004 02 Follow the steps below to construct a copy of the Linux operating system using the S1D13706 as the console display device These instructions assume that the GNU devel opment environment is installed and the user is familiar with GNU and the Linux operating system 1 Acquire the Linux kernel source code You can obtain the Linux kernel source code from your Linux supplier or download the source from ftp ftp kernel org The S1D13706 reference driver requires Linux kernel 2 2 x The example S1D13706 reference driver availa
69. Vancouver Design Center Test utilities and Windows CE v2 11 2 12 display drivers are available for the S1D13706 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the Motorola MC68030 Microprocessor Issue Date 01 02 23 Epson Research and Development Page 15 Vancouver Design Center 6 References 6 1 Documents Motorola Inc MC68030 32 bit Enhanced Microprocessor User s Manual Motorola Publication no MC68030UM available on the Internet at http www mot com SPS ADC pps _subpgs _documentation Epson Research and Development Inc 1D 3706 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual Document Number X31B G 004 xx Epson Research and Development Inc Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources e Motorola Inc Literature Distribution Center 800 441 2447 e Motorola Inc Website http
70. X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 105 Vancouver Design Center Vertical Total Register 0 REG 18h Read Write Vertical Total Bits 7 0 7 6 5 4 3 2 1 0 Vertical Total Register 1 REG 19h Read Write n a Vertical Total Bits 9 8 7 6 5 4 3 2 1 0 bits 9 0 Vertical Total Bits 9 0 These bits specify the LCD panel Vertical Total period in 1 line resolution The Vertical Total is the sum of the Vertical Display Period and the Vertical Non Display Period The maximum Vertical Total is 1024 lines Vertical Total in number of lines REG 18h bits 7 0 REG 19h bits 1 0 1 Note 1 This register must be programmed such that the following formula is valid VDPS VDP lt VT 2 For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 56 Vertical Display Period Register 0 REG 1Ch Read Write Vertical Display Period Bits 7 0 7 6 5 4 3 2 1 0 Vertical Display Period Register 1 REG 1Dh Read Write Vertical Display Period na Bits 9 8 7 6 5 4 3 2 1 0 bits 9 0 Vertical Display Period Bits 9 0 These bits specify the LCD panel Vertical Display period in 1 line resolution The Vertical Display period should be less than the Vertical Total to allow for a sufficient Vertical Non Display period Vertical Display Period in number of lines REG 1Ch
71. configured as an output writing a 1 to this bit drives GPIO2 high and writing a 0 to this bit drives GPIO2 low When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIO2 is configured as an input a read from this bit returns the status of GPIO2 When a D TFD panel is enabled REG 10h bits 1 0 11 GPIO2 outputs the FR signal automatically and writing to this bit has no effect When a HR TFT panel is enabled REG 10h bits 1 0 10 GPIO2 outputs the REV sig nal automatically and writing to this bit has no effect GPIO1 Pin IO Status When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIO1 is configured as an output writing a 1 to this bit drives GPIO1 high and writing a 0 to this bit drives GPIO1 low When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIO1 is configured as an input a read from this bit returns the status of GPIO1 When a D TFD panel is enabled REG 10h bits 1 0 11 GPIO1 outputs the YSCL sig nal automatically and writing to this bit has no effect When a HR TFT panel is enabled REG 10h bits 1 0 10 GPIO1 outputs the CLS sig nal automatically and writing to this bit has no effect Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 125 Vancouver Design Center bit 0 GPIOO Pin IO Status When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIOO is configure
72. however signal names may differ between panel manufacturers The values shown in brackets represent the color components as mapped to the corresponding FPDATxx signals at the first valid edge of FPSHIFT For further FRDATxx to LCD interface mapping see Section 6 4 Display Interface on page 56 3 When the HR TFT interface is selected REG 10h bits 1 0 10 this GPO can be used to control the HR TFT MOD signal Note this is not the same signal as the S1D13706 DRDY MOD signal used for passive panels Hardware Functional Specification Issue Date 01 11 13 1D13706 X31B A 001 08 Page 32 5 D C Characteristics Table 5 1 Absolute Maximum Ratings Epson Research and Development Vancouver Design Center Symbol Parameter Rating Units Core Vpp Supply Voltage Vss 0 3 to 4 0 V IO Vpp Supply Voltage Vss 0 3 to 4 0 V VIN Input Voltage Vss 0 3 to IO Vpp 0 5 V Vout Output Voltage Vss 0 3 to IO Vpp 0 5 V TsTG Storage Temperature 65 to 150 C TsoL Solder Temperature Time 260 for 10 sec max at lead C Table 5 2 Recommended Operating Conditions Symbol Parameter Condition Min Typ Max Units 1 8 2 0 2 2 V Core Vpp Supply Voltage Vss 0V 0 33 36 7 1 8 2 0 2 2 V HIO Vpp Supply Voltage Vss 0V 30 33 36 y NIO Vpp Supply Voltage Vss 0V 3 0 3 3 3 6 V Vin Input Volt
73. input of the S1D13706 may be connected to the system RESET Interfacing to the Intel StrongARM SA 1110 Microprocessor Issue Date 02 06 26 Epson Research and Development Page 13 Vancouver Design Center 4 StrongARM SA 1110 to S1D13706 Interface 4 1 Hardware Description The SA 1110 microprocessor provides a variable latency I O interface that can be used to support an external LCD controller By using the Generic 2 Host Bus Interface no glue logic is required to interface the S1D13706 and the SA 1110 A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO Vpp The following diagram shows a typical implementation of the SA 1110 to S1D13706 interface S1D13706 HIO V SA 1110 5 BS RD WR nWE gt WEO nCAS1 gt WE1 nOE gt RD nCS4 gt CSH Pull up Too RDY WAIT A17 gt M R nCASO gt ABO A 16 1 gt AB 16 1 D 15 0 gt DB 15 0 SDCLK2 gt CLKI System RESET RESET Note When connecting the S1D13706 RESET pin the system designer should be aware of all conditions that may reset the S1D13706 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of SA 1110 to SID13706 Interface Interfac
74. is not used in this implementation and should be tied high connected to HIO Vpp The following diagram shows a typical implementation of the MPC821 to S1D13706 interface MPC821 1D13706 A 15 31 AB 16 0 D 0 15 ly gt DB 15 0 CS4 gt CS A14 gt M R HIO Vpp A BS TA WAIT WEO gt WE1 WET gt WEO OE gt RD WR gt RD SYSCLK gt CLKI System RESET Wp RESET Note When connecting the S1D13706 RESET pin the system designer should be aware of all conditions that may reset the S1D13706 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MPC821 to SID13706 Interface Table 4 1 List of Connections from MPC821ADS to S1D13706 on page 16 shows the connections between the pins and signals of the MPC821 and the 1D13706 Interfacing to the Motorola MPC821 Microprocessor 1D13706 Issue Date 01 02 23 X31B G 009 02 Page 16 4 2 MPC821ADS Evaluation Board Hardware Connections 1D13706 X31B G 009 02 Note Epson Research and Development Vancouver Design Center The interface was designed using a Motorola MPC821 Application Development System ADS The ADS board has 5 volt logic connected to the data bus so the interface included two 74F245 octal buffers on D 0 15 between the ADS and the S1D13706 In a true 3 volt system no buffering is necess
75. 0 REG A4h Read Write Scratch Pad Bits 7 0 7 6 5 4 3 2 1 0 Scratch Pad Register 1 REG A5h Read Write Scratch Pad Bits 15 8 7 6 5 4 3 2 1 0 bits 15 0 Scratch Pad Bits 15 0 This register contains general purpose read write bits These bits have no effect on hardware Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 122 Epson Research and Development Vancouver Design Center 8 3 8 General lO Pins Registers General Purpose lO Pins Configuration Register 0 REG ASh Read Write n a Y GPIO6 Pin IO Configuration 6 GPIO5 Pin lO Configuration 5 GPIO4 Pin lO Configuration 4 GPIO3 Pin IO Configuration 3 GPIO2 Pin lO Configuration 2 GPIO1 Pin lO Configuration 1 GPIOO Pin IO Configuration 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note If CNF3 0 at RESET then all GPIO pins are configured as outputs only and this register has no effect This case allows the GPIO pins to be used by the HR TFT D TFD panel interfaces For a summary of GPIO usage for HR TFT D TED see Table 4 10 LCD Interface Pin Mapping on page 31 2 The input functions of the GPIO pins are not enabled until REG A9h bit 7 is set to 1 GPIO6 Pin IO Configuration When this bit 0 default GPIO6 is configured as an input pin When this bit 1 GPIO6 is configure
76. 0 Evaluation Board User Manual Document Number X31B G 004 xx Epson Research and Development Inc S D13706 Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources e Motorola Literature Distribution Center 800 441 2447 e Epson Electronics America Website www eea epson com 1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 02 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD CRT Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola REDCAP2 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor Interfacing to the Motorola RedCap2 DSP With Integrated MCU Issue Date 01 02 23 Page 19 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec
77. 0 PCLK Source Select Bits 1 0 These bits determine the source of the Pixel Clock PCLK Table 8 4 PCLK Source Selection PCLK Source Select Bits PCLK Source 00 MCLK 01 BCLK 10 CLKI 11 CLKI2 S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 99 Vancouver Design Center 8 3 3 Look Up Table Registers Note The S1D13706 has three 256 position 6 bit wide LUTs one for each of red green and blue see Section 11 Look Up Table Architecture on page 132 Look Up Table Blue Write Data Register REG 08h Write Only LUT Blue Write Data Bits 5 0 n a 7 6 5 4 3 2 1 0 bits 7 2 LUT Blue Write Data Bits 5 0 This register contains the data to be written to the blue component of the Look Up Table The data is stored in this register until a write to the LUT Write Address register REG OBh moves the data into the Look Up Table Note The LUT entry is updated only when the LUT Write Address Register REG OBh is written to Look Up Table Green Write Data Register REG 09h Write Only LUT Green Write Data Bits 5 0 n a 7 5 4 3 2 1 0 bits 7 2 LUT Green Write Data Bits 5 0 This register contains the data to be written to the green component of the Look Up Table The data is stored in this register until a write to the LUT Write Address register REG OBh moves the data into the Look Up Tab
78. 001 04 Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds The following sections describe how to build the Windows CE display driver for 1 Windows CE 2 0 using a command line interface 2 Windows CE Platform Builder 2 1x using a command line interface In all examples x refers to the drive letter where Platform Builder is installed Build for CEPC X86 on Windows CE 2 0 using a Command Line Interface 1D13706 X31B E 001 04 To build a Windows CE v2 0 display driver for the CEPC X86 platform using a S5U13706B00C evaluation board follow the instructions below 1 Install Microsoft Windows NT v4 0 or 2000 2 Install Microsoft Visual C C version 5 0 or 6 0 3 Install the Microsoft Windows CE Embedded Toolkit ETK by running SETUP EXE from the ETK compact disc 1 4 Create a new project by following the procedure documented in Creating a New Project Directory from the Windows CE ETK v2 0 Alternately use the current DEMO project included with the ETK v2 0 Follow the steps below to create a X86 DEMO7 shortcut on the Windows NT v4 0 desktop which uses the current DEMO project a Right click on the Start menu on the taskbar b Click on the item Open All Users and the Start Menu window will come up c Click on the icon Programs d Click on the icon Windows CE Embedded Development Kit e Drag the icon X86 DEMO1
79. 01 02 23 Epson Research and Development Vancouver Design Center Page 11 The following table represents the sequence and values written to the S1D13706 registers to control a configuration with these specifications e 320x240 color single passive LCD 70Hz e 8 bit data interface format 2 e 8 bit per pixel bpp color depth 256 colors e 50MHz input clock for CLKI e MCLK BCLK CLKI 50MHz e PCLK CLKI 8 6 25MHz Note On the S5U13706BO0C evaluation board CNF 7 6 must be set to 00 Table 2 1 Example Register Values Register 04h 05h 10h 1th 12h 14h 16h 17h 18h 19h 1Ch 1Dh 1Eh 1Fh 20h 22h 23h 24h 26h 27h Value Hex 00 43 Value Binary 0000 0000 0100 0011 1101 0000 0000 0000 0010 1011 0010 0111 0000 0000 0000 0000 1111 1010 0000 0000 11101111 0000 0000 0000 0000 0000 0000 1000 0111 0000 0000 0000 0000 1000 0000 0000 0001 0000 0000 Description Sets BCLK to MCLK divide to 1 1 Sets PCLK PCLK source 8 and the PCLK source CLKI2 Selects the following panel data format 2 color mono panel color panel data width 8 bit active panel resolution don t care panel type STN MOD rate don t care Sets the horizontal total Sets the horizontal display period Sets the horizontal display period start position Sets the vertical total Sets the vertical display period Sets
80. 01 02 23 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD CRT Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MPC821 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 23 Page 23 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13706 X31B G 009 02 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 02 Issue Date 01 02 23 EPSON 1D
81. 1 0 1 1 REGIECHI bit7 bito bit7 bit7 Index 00h Index 01h Index 00h Figure 6 35 160x240 Epson D TFD Panel GCP Horizontal Timing Table 6 29 160x240 Epson D TFD Panel GCP Horizontal Timing Symbol Parameter Min Typ Max Units t1 Half of the horizontal total period 200 Ts note 1 t2 GOP clock period 1 Ts 1 Ts pixel clock period S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 85 Vancouver Design Center Vertical Total 250HT g FPFRAME DY t2 wey SOE A er Se Ae ee a a E E a ey t3 E FPDAT 17 0 R G B linet i line2 A x ae GPIO2 FR l l l i i odd frame i GPIO2 FR even frame ON i i i E A E ee ee Figure 6 36 160x240 Epson D TFD Panel Vertical Timing Table 6 30 160x240 Epson D TFD Panel Vertical Timing Symbol Parameter Min Typ Max Units t1 FPFRAME pulse width 200 Ts note 1 t2 Horizontal total period 400 Ts t3 Vertical display start 400 Ts 1 Ts pixel clock period Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 86 Epson Research and Development Vancouver Design Center 6 4 13 320x240 Epson D TFD Panel Timing e g LF37SQR t1
82. 10 LCD Interface Pin Mapping on page 31 for summary This pin has multiple functions e CLS for Sharp HR TFT e YSCL for Epson D TFD GPIO1 IO 44 LB3M NIOVDD 0 General purpose lO pin 1 GPIO1 See Table 4 10 LCD Interface Pin Mapping on page 31 for summary S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Vancouver Design Center Page 27 Table 4 4 LCD Interface Pin Descriptions Pin Name Type Pin Cell 10 RESET Description Voltage State escriptio GPIO2 43 LB3M This pin has multiple functions REV for Sharp HR TFT FR for Epson D TFD General purpose IO pin 2 GPIO2 See Table 4 10 LCD Interface Pin Mapping on page 31 for summary NIOVDD 0 GPIO3 42 LB3M This pin has multiple functions e SPL for Sharp HR TFT FRS for Epson D TFD e General purpose IO pin 3 GPIO3 See Table 4 10 LCD Interface Pin Mapping on page 31 for summary NIOVDD 0 GPIO4 41 LB3M This pin has multiple functions RES for Epson D TFD NIOVDD 0 General purpose IO pin 4 GPIO4 See Table 4 10 LCD Interface Pin Mapping on page 31 for summary GPIO5 40 LB3M This pin has multiple functions DD_P1 for Epson D TFD NIOVDD 0 e General purpose IO pin 5 GPIO5 See Table 4 10 LCD Interface Pin Mapping on page 31 for summary G
83. 13706PLA Y to start the program Type for help Type i to initialize the registers Type xa to display the contents of the registers Type x 34 to read register 34h Type x 34 10 to write 10h to register 34h Type f 0 ffff aa to fill the first FFFFh bytes of the display buffer with AAh Type r 0 100 to read the first 100h bytes of the display buffer 10 Type q to exit the program 13706PLAY Diagnostic Utility Issue Date 01 02 23 Epson Research and Development Page 11 Vancouver Design Center Scripting Comments 13706PLAY Diagnostic Utility Issue Date 01 02 23 13706PLAY can be driven by a script file This is useful when e there is no display output and a current register status is required e various registers must be quickly changed to view results A script file is an ASCII text file with one 13706PLAY command per line All scripts must end with a q quit command On a PC platform a typical script command line might be 13706PLAY lt dumpregs scr gt results This causes the file dumpregs scr to be interpreted as commands by 13706PLAY and the results to be sent to the file results Example 1 Create a script file that reads all registers and then exits This file initializes the S1D13706 and reads the registers Note after a semicolon all characters on a line are ignored 6699 Note all script files must end with the q command Initialize the S1D13706 i Read all re
84. 26 X31B G 016 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B G 016 02 Issue Date 01 02 26 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 2 000000020 ee eee 9 Table 4 1 Summary of Power On Reset Configuration Options 12 Table 4 2 CLKI to BCLK Divide Selection o o e 12 Table 4 3 WS Bit Programming 0 0 000 a 13 List of Figures Figure 4 1 Typical Implementation of MC68VZ328 to S1D13706 Interface 11 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor S1D13706 Issue Date 01 02 26 X31B G 016 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B G 016 02 Issue Date 01 02 26 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and the Motorola MC68VZ328 Dragonball VZ microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electro
85. 3 and CV Pulse Enable bit 0 These bits control the CVOUT pin and CV Pulse circuitry as follows Table 8 16 CV Pulse Control Bit 3 Bit 0 Result 0 1 CV Pulse circuitry enabled controlled by REG B1h and REG B2h 0 0 CVOUT forced low 1 x CVOUT forced high x don t care When CVOUT is forced low or forced high it can be used as a general purpose output Note Bit 3 must be set to 0 and bit O must be set to 1 before initiating a new burst using the CV Pulse Burst Start bit 2 The CV Pulse circuitry is disabled when Power Save Mode is enabled bit 2 CV Pulse Burst Status This is a read only bit A 1 indicates a CV pulse burst is occurring A 0 indicates no CV pulse burst is occurring Software should wait for this bit to clear before starting another burst bit 1 CV Pulse Burst Start A 1 in this bit initiates a single CVOUT pulse burst The number of clock pulses generated is programmable from 1 to 256 The frequency of the pulses is the divided CV Pulse source divided by 2 with 50 50 duty cycle This bit should be cleared to 0 by software before initiating a new burst Note This bit has effect only if the CV Pulse Enable bit is 1 bit 0 CV Pulse Enable See description for bit 3 Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 128 Epson Research and Development Vancouver Design Center PWM
86. 30 70 50 D2 40 30 20 13 20 20 20 53 EO BO FO 93 30 70 60 D3 40 30 20 14 30 30 30 54 FO BO FO 94 30 70 70 D4 40 40 20 15 40 40 40 55 FO BO EO 95 30 60 70 D5 30 40 20 16 50 50 50 56 FO BO DO 96 30 50 70 D6 30 40 20 17 60 60 60 57 FO BO CO 97 30 40 70 D7 20 40 20 18 70 70 70 58 FO BO BO 98 50 50 70 D8 20 40 20 19 80 80 80 59 FO CO BO 99 50 50 70 D9 20 40 20 1A 90 90 90 5A FO DO BO 9A 60 50 70 DA 20 40 30 1B AO AO AO 5B FO EO BO 9B 60 50 70 DB 20 40 30 1C BO BO BO 5C FO FO BO 9C 70 50 70 DC 20 40 40 1D Co CO CO 5D EO FO BO 9D 70 50 60 DD 20 30 40 1E EO EO EO 5E DO FO BO 9E 70 50 60 DE 20 30 40 1F FO FO FO 5F CO FO BO 9F 70 50 50 DF 20 20 40 20 00 00 FO 60 BO FO BO AO 70 50 50 EO 20 20 40 21 40 00 FO 61 BO FO CO Al 70 50 50 El 30 20 40 22 70 00 FO 62 BO FO DO A2 70 60 50 E2 30 20 40 S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 25 Vancouver Design Center Table 4 8 Suggested LUT Values to Simulate VGA Default 256 Color Palette Continued Index R G B Index R G B Index R G B Index R G B 23 BO 00 FO 63 BO FO EO A3 70 60 50 E3 30 20 40 24 FO 00 FO 64 BO FO FO A4 70 70 50 E4 40 20 40 25 FO 00 BO 65 BO E0 FO A5 60 70 50 ES 40 20 30 26 FO 00 70 66 BO DO FO A6 60 70 50 E6 40 20 30 27 FO 00 40 67 BO CO FO A7 50 70 50 E7 40 20 30 28 FO 00
87. 320 x 240 x 4 8 4 1 9599 257Fh Program the Main Window Display Start Address registers REG 74h is set to 7Fh REG 75h is set to 25h and REG 76h is set to 00h 4 Determine the main window line address offset number of dwords per line image width 32 bpp 320 32 4 40 28h Program the Main Window Line Address Offset registers REG 78h is set to 28h and REG 79h is set to 00h 5 Determine the sub window display start address The main window image must take up 320 x 240 pixels 2 pixels per byte 9600h bytes If the main window starts at address Oh then the sub window can start at 9600h sub window display start address desired byte address sub window width x sub window height x bpp 8 4 1 9600h 160 x 120 x 4 8 4 1 11999 2EDFh Program the Sub window Display Start Address registers REG 7Ch is set to DFh REG 7Dh is set to 2Eh and REG 7Eh is set to 00h Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 56 1D13706 X31B G 003 03 Epson Research and Development Vancouver Design Center 6 Determine the sub window line address offset number of dwords per line image width 32 bpp 160 32 4 20 14h Program the Sub window Line Address Offset registers REG 80h is set to 14h and REG 81h is set to 00h Determine the value for the sub window X and Y start and end position registers Let the top lef
88. 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg S1D13706 X31B G 019 02 Page 20 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Intel StrongARM SA 1110 Microprocessor X31B G 019 02 Issue Date 02 06 26
89. 4 1 Summary of Power On Reset Configuration Options 14 List of Figures Figure 2 1 MCF5307 Memory Read Cycle 2 2 0 0 0 ee 9 Figure 2 2 MCF5307 Memory Write Cycle 2 2 0 2 02 0000000002 eee 9 Figure 2 3 Chip Select Module Outputs Timing e 10 Figure 4 1 Typical Implementation of MCF5307 to S1D13706 Interface 13 Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13706 Issue Date 01 02 23 X31B G 010 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X31B G 010 02 Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and the Motorola MCF5307 Processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor S1D13706 Issue Date 01 0
90. 48 The register is also incremented differently based on the SwivelView orientation For 0 and 180 SwivelView the Y end position is incremented in 1 line increments For 90 and 270 SwivelView the Y end position is incremented by Y pixels where Y is relative to the current color depth Table 8 4 32 bit Address Increments for Color Depth Bits Per Pixel Color Depth Pixel Increment Y 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 In Swivel View 0 these registers set the vertical coordinates y of the sub windows s bottom right corner Increasing values of y move the bottom right corner downwards in steps of 1 line Program the Sub Window Y End Position registers so that sub window Y end position registers y 1 In Swivel View 90 these registers set the horizontal coordinates x of the sub window s bottom left corner Increasing values of x move the top right corner towards the right in steps of 32 bits per pixel see Table 8 4 Program the Sub Window Y End Position registers so that sub window Y end position registers panel height x 32 bits per pixel 1 Note panel height x must be a multiple of 32 bits per pixel In Swivel View 180 these registers set the vertical coordinates y of the sub window s top left corner Increasing values of y move the top left corner downwards in steps of 1 line Programming Notes and Examples Issue Date 01 02 23 Epson R
91. 5 4 Disabling Power Save Mode Power Save Mode must be disabled using the following steps 1 Ifthe Memory Clock source is shut down it must be started and the Memory Control ler Power Save Status bit must return a 0 Note if the pixel clock source is disabled it must be started before step 2 2 Disable Power Save Mode set REG AOh bit 0 to 0 3 Wait for the LCD bias power supply to charge The charge time must be based on the time specified in the LCD panel specification 4 Enable the LCD bias power using GPO Note 1D13706 X31B G 003 03 The S5U13706B00C uses GPO to control the LCD bias power supplies Your system design may vary Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 29 Vancouver Design Center 6 LCD Power Sequencing The S1D13706 requires LCD power sequencing the process of powering on and powering off the LCD panel LCD power sequencing allows the LCD bias voltage to discharge prior to shutting down the LCD signals preventing long term damage to the panel and avoiding unsightly lines at power on power off Proper LCD power sequencing for power off requires a delay from the time the LCD power is disabled to the time the LCD signals are shut down Power on requires the LCD signals to be active prior to applying power to the LCD This time interval depends on the LCD bias power supply design For example the LCD bias power supply on the S5U13706 Evaluation boa
92. 6 3 Generic 2 Interface Timing Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 39 Vancouver Design Center Table 6 6 Generic 2 Interface Timing 2 0V 3 3V Symbol Parameter Min Max Min Max Unit fgusc_k Bus Clock frequency 20 50 MHz TBUSCLK Bus Clock period 1ABuscLk 1 ABuscLk ns ti Clock pulse width high 22 5 9 ns t2 Clock pulse width low 22 5 9 ns 3 SA 16 0 M R SBHE setup to first BUSCLK rising edge 4 4 Ae where CS 0 and either MEMR 0 or MEMW 0 t4 SA 16 0 M R SBHE hold from either MEMR or MEMW 0 0 He rising edge t5 CS setup to BUSCLK rising edge 0 1 ns t6 CS hold from either MEMR or MEMW rising edge 0 0 ns t a MEMR MEMW asserted for MCLK BCLK 8 5 8 TBUSCLK t7b MEMR MEMW asserted for MCLK BCLK 2 11 5 11 TBUSCLK tze MEMR MEMW asserted for MCLK BCLK 3 13 5 13 TBUSCLK t7d MEMR MEMW asserted for MCLK BCLK 4 17 5 17 TBUSCLK t8 MEMR or MEMW setup to BUSCLK rising edge 2 1 ns 19 fra edge of either MEMR or MEMW to IOCHRDY driven 5 3 15 Re HO pedo of either MEMR or MEMW to IOCHRDY high 5 3 13 AS 11 SD 15 0 setup to third BUSCLK rising edge where CS 0 and 4 0 s MEMW 0 write cycle see note 1 t12 SD 15 0 hold from IOCHRDY rising edge write cycle 1 0 ns t13 MEMR falling edge to SD 15 0 driven read cycle 4 26 3 13 ns t14 IOCHRDY rising edge
93. Bee Seen A E ena Owe Supplies on page 8 45 V5 Standard gray scale voltage See Seon 231 External Rower Supplies on page 8 46 V6 Standard gray scale voltage Soe Sarton E Na owe Supplies on page 8 47 V7 Standard gray scale voltage eee Facon li ORET Supplies on page 8 48 V8 5 Standard gray scale voltage pee Sen Peta aenal ROWE Supplies on page 8 49 v9 Standard gray scale voltage white Haa Section ee External Rower Supplies on page 8 50 AGND Vss Analog ground Ground pin of S1D13706 Connecting to the Sharp HR TFT Panels Issue Date 01 02 23 S1D13706 X31B G 011 04 Page 14 Epson Research and Development Vancouver Design Center 3 Connecting to the Sharp LQ031B1DDxx HR TFT 3 1 External Power Supplies The S1D13706 provides all necessary data and control signals to connect to the Sharp LQ031B1DDxx 160x160 HR TFT panel s However it does not provide any of the voltages required for the backlight gray scaling gate driving or for the digital and analog supplies Therefore external supplies must be designed for any device utilizing the LQ031B1DDxx The LQ031B1DDxx 160x160 has the same voltage requirements as the LQ039Q2DS01 320x240 All the circuits used to generate the various voltages for the LQ039Q2DS01 panel also apply to the LQ031B1DDxx panel This section provides additional circuits for generating some of these voltages 3 1 1 Gray Scale Voltages for Gamma Correction The standard gray
94. CLKI2 frequency will be displayed in blue in the Auto section If the system design requires the CLKI2 frequency to be fixed at a particular rate set this value by selecting a preset frequency from the drop down list or entering the desired frequency in MHz These settings select the clock signal source and divisor for the pixel clock PCLK Selects the PCLK source Possible sources include CLKI CLKI2 BCLK or MCLK Specifies the divide ratio for the clock source signal The divide ratio is applied to the PCLK source to derive PCLK Selecting Auto for the divisor allows the configu ration program to calculate the best clock divisor Unless a very specific clocking is being specified it is best to leave this setting on Auto This field shows the actual PCLK used by the configu ration process 1D13706 X31B B 001 03 Page 12 BCLK Source Divide Timing MCLK Source Divide Timing 1D13706 X31B B 001 03 Epson Research and Development Vancouver Design Center These settings select the clock signal source and divisor for the bus interface clock BCLK The BCLK source is CLKI Specifies the divide ratio for the clock source signal The divide ratio is applied to the BCLK source to derive BCLK This field shows the actual BCLK frequency used by the configuration process These settings select the clock signal source and input clock divisor for the memory clock MCLK MCLK should
95. CLKI2 of the 1D 13706 and VCLKOUT from the clock synthesizer is connected to CLKI of the S1D13706 A 14 31818MHz crystal Y1 is connected to XTALIN and XTALOUT of the clock synthe sizer ICD2061A Synthesizer reference 14 31818 MHz gt P gt XTALIN MCLKOUT gt CLKI2 VCLKOUT gt CLKI Figure 7 1 Symbolic Clock Synthesizer Connections At power on CLKI2 MCLKOUT is configured to be 40MHz and CLKI VCLKOUT is configured at 25 175MHz Note If an Epson D TFD panel is selected the clock synthesizer cannot be programmed and external oscillators must provide the clock signals to CLKI and CLKI2 Jumpers JP2 and JP3 allow selection of external oscillators U5 and U6 as the clock source for both CLKI and CLKI2 For further information see Table 3 2 Jumper Summary on page 11 7 1 Clock Programming The 1D13706 utilities automatically program the clock generator If manual programming of the clock generator is required refer to the source code for the S1D13706 utilities available on the internet at www eea epson com For further information on programming the clock generator refer to the Cypress ICD2061A specification Note When CLKI and CLKI2 are programmed to multiples of each other e g CLKI 20MHz CLKI2 40MHz the clock output signals from the Cypress clock generator may jitter Refer to the Cypress ICD2061A specification for details To avoid this problem set CLKI
96. CV Pulse settings The CV Pulse is provided for panels which support the contrast voltage function When this box is checked the CV Pulse circuitry is enabled The signal CVOUT is forced high when this box is checked CVOUT is forced low when this box is not checked and CVOUT is not enabled The CV Pulse uses the same source clock as the PWMCLK Specifies the divide ratio for the clock source signal The divide ratio is applied to the CVOUT Pulse clock source to derive the CV Pulse clock frequency This field shows the actual CV Pulse frequency used by the configuration process The number of pulses generated in a single CV Pulse burst S1D13706 X31B B 001 03 Page 14 Panel Tab Panel Data Width Mono Color Format 2 Panel Type Display Total TET FPLINE 51D13706 Configuration Utility 607160 fe S20 7240 1D13706 X31B B 001 03 Display Start Epson Research and Development Vancouver Design Center FPLINE FPFRAME Polarity Polarit Predefined fea Panels The S1D13706 supports many panel types This tab allows configuration of most panel settings such as panel dimensions type and timings Panel Type Panel Data Width Selects between passive STN and active TFT D TFD HR TFT panel types Several options may change or become unavailable when the STN TFT setting is switched Therefore confirm all settings on this tab after the Panel Type is changed
97. Clock CV Pulse Configuration Register REG B1h Read Write PWM Clock Divide Select Bits 3 0 CV Pulse Divide Select Bits 2 0 NM AS Source Select 7 6 5 4 3 2 1 0 bits 7 4 PWM Clock Divide Select Bits 3 0 The value of these bits represents the power of 2 by which the selected PWM clock source is divided Table 8 17 PWM Clock Divide Select Options PWM Clock Divide Select Bits 3 0 PWM Clock Divide Amount Oh 1 th 2 2h 4 3h 8 Ch 4096 Dh Fh Reserved Note This divided clock is further divided by 256 before it is output at PWMOUT bits 3 1 CV Pulse Divide Select Bits 2 0 The value of these bits represents the power of 2 by which the selected CV Pulse source is divided Table 8 18 CV Pulse Divide Select Options CV Pulse Divide Select Bits 2 0 CV Pulse Divide Amount Oh 1 th 2 2h 4 3h 8 7h 128 Note This divided clock is further divided by 2 before it is output at the CVOUT bit 0 PWMCLK Source Select When this bit 0 the clock source for PWMCLK is CLKI When this bit 1 the clock source for PWMCLK is CLKI2 Note For further information on the PWMCLK source select see Section 7 2 Clock Selec tion on page 93 S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 129 Vancouver Design Center CV Pulse Burst Length Register REG B2h Read Write CV Pulse Burst Length Bits 7 0 7 6 5 4 3
98. Comments 1 Connected to DBO of the S1D13706 2 Connected to DB1 of the S1D13706 3 Connected to DB2 of the S1D13706 4 Connected to DB3 of the S1D13706 5 Ground 6 Ground 7 Connected to DB4 of the S1D13706 8 Connected to DB5 of the S1D13706 9 Connected to DB6 of the S1D13706 10 Connected to DB7 of the S1D13706 11 Ground 12 Ground 13 Connected to DB8 of the S1D13706 14 Connected to DB9 of the S1D13706 15 Connected to DB10 of the S1D13706 16 Connected to DB11 of the S1D13706 17 Ground 18 Ground 19 Connected to DB12 of the S1D13706 20 Connected to DB13 of the S1D13706 21 Connected to DB14 of the S1D13706 22 Connected to DB15 of the S1D13706 23 Connected to RESETH of the S1D13706 24 Ground 25 Ground 26 Ground 27 12 volt supply 28 12 volt supply 29 Connected to WEO of the S1D13706 30 Connected to WAIT of the S1D13706 31 Connected to CS of the S1D13706 32 Connected to MR of the S1D13706 33 Connected to WE1 of the S1D13706 34 Connected to TXVDD1 S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 Epson Research and Development Vancouver Design Center Table 4 3 CPU Bus Connector H4 Pinout Sonetos Comments Pin No 1 Connected to AO of the S1D13706 2 Connected to A1 of the S1D13706 3 Connected to A2 of the S1D13706 4 Connected to A3 of the S1D13706 5 Connected to A4 of the S1D13706 6
99. Date 01 02 23 X31B G 014 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 02 Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13706 Embedded Memory LCD Controller and the Motorola REDCAP 2 processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America Website at www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Motorola RedCap2 DSP With Integrated MCU S1D13706 Issue Date 01 02 23 X31B G 014 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the REDCAP2 2 1 The REDCAP2 System Bus REDCAP2 integrates a RISC microprocessor MCU and a general purpose digital signal processor DSP on a single chip The External Interface Module EIM handles the interface to external devices This section provides an overview of the operation of the REDCAP2 bus in order to establish interface requirements
100. Development Vancouver Design Center 2 Initialization 1D13706 X31B G 003 03 This section describes how to initialize the S1D13706 Sample code for performing initial ization of the S1D13706 is provided in the file init13706 c which is available on the internet at www eea epson com or www erd epson com S1D13706 initialization can be broken into the following steps 1 Disable the display using the Display Blank bit set REG 70h bit 7 1 2 Ifthe system implementation uses a clock chip instead of a fixed oscillator program the clock chip For example the S5U13706 Evaluation Board uses a Cypress clock chip 3 Set all registers to initial values Table 2 1 Example Register Values contains the correct values for an example panel discussed below 4 Program the Look Up Table LUT with color values For details on programming the LUT see Section 4 Look Up Table LUT on page 17 5 Power up the LCD panel For details on powering up the LCD panel see Section 5 4 Disabling Power Save Mode on page 28 6 Enable the display using the Display Blank bit set REG 70h bit 7 0 7 Clear the display buffer if required Note The simplest way to generate initialization tables for the S1D13706 is to use the utility program 13706CFG EXE which generates a header file that can be used by the operat ing system or the HAL Otherwise modify the init13706 c file directly Programming Notes and Examples Issue Date
101. Driver Power Supplies See Section 2 1 4 AC Gate Driver Power Supplies on page 10 and Figure 2 3 Panel Gate Driver AC Power Supplies on page 10 for details on generating Veg and Vcom If the Sharp IR3E203 is used to generate the gray scale voltages the COM signal can be connected to the input of the F2C02E MOSFET instead of the buffered REV signal 3 2 HR TFT MOD Signal See Section 2 2 HR TFT MOD Signal on page 11 for details on controlling the MOD signal through software Connecting to the Sharp HR TFT Panels 1D13706 Issue Date 01 02 23 X31B G 011 04 Page 16 3 3 S1D13706 to LQ031B1DDxx Pin Mapping Epson Research and Development Vancouver Design Center Table 3 1 S1D13706 to LOO3IBIDDxx Pin Mapping LCD Pin LCD Pin S1D13706 Description prado No Name Pin Name P een 1 VDD Power supply of gate driver high level Sco oe noes 2 VCC Power supply of gate driver logic high o os rower 3 MOD Control signal of gate driver pee POOS EE TET MOR Sna on page 15 4 MOD Control signal of gate driver pea PONE E MOR Signal on page 15 5 U L E Selection for vertical scanning direction Connect to VSHD top bottom scanning 6 SPS FPFRAME Start signal of gate driver 7 CLS GPIO1 Clock signal of gate driver 8 VSS Power supply of gate driver logic low on Ar Power 9 VEE Power supply of gate driver low level ea
102. EDC 1 an idle cycle is inserted after a read cycle for back to back external trans fers unless the next cycle is a read cycle to the same CS bank e WWS 0 same length for reads and writes Interfacing to the Motorola RedCap2 DSP With Integrated MCU Issue Date 01 02 23 Epson Research and Development Page 17 Vancouver Design Center 5 Software Test utilities and Windows CE v2 11 2 12 display drivers are available for the S1D13706 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at www eea epson com Interfacing to the Motorola RedCap2 DSP With Integrated MCU 1D13706 Issue Date 01 02 23 X31B G 014 02 Page 18 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e Motorola Inc REDCAP2 Digital Signal Processor Integrated With MCU Product Specifications Rev 1 2ext Epson Research and Development Inc 1D13706 Hardware Functional Specification Document Number X31B A 001 xx e Epson Research and Development Inc S5UI13706B00C Rev 1
103. FPFRAME MOD is the MOD signal when REG 11h bits 5 0 n MOD toggles every n FPLINE Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 60 Epson Research and Development Vancouver Design Center 6 4 2 Single Monochrome 4 Bit Panel Timing VDP VNDP j i FPFRAME FT o FPLINE l J is 2 Nl l Il j Il DRDY MOD at X FPDAT 7 4 y Invalid LINE1 X LINE2 X LINES X LINE4 XLINE239XLINE240X Invalid X LINE X LINE2 Y FPLINE C DRDY MOD X 3 k HDP re HNDP x Beet 2 ESE AE A Oe EOE oes a FPDAT7 invalid 1X 15 XX EL XX 4317X Invalid X FPDAT6 invalid X12 X16 Y X Ss Y Y 1 318 Invalid Y FPDAT5 Invalid 13 X 17 Y YX AR Y YX X 1 319X Invalid X FPDAT4 Invalid 14 Y 18 Y X io As Y YX X 1320X invalid X YX Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 6 15 Single Monochrome 4 Bit Panel Timing VDP Vertical Display Period REG 1 Dh bits 1 0 REG 1Ch bits 7 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 19h bits 1 0 REG 18h bits 7 0 REG 1Dh bits 1 0 REG 1 Ch bits 7 0 Lines HDP Horizontal Display Period REG 14h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts 1D13706 Ha
104. FPLINE NA LP t2 t3 ke gt FPSHIFT eels Vopr a ee NN NE 14 t5 t6 pe a 1 2V3Va 320 t7 t8 gt lt gt lt t9 ple t9 fl t10 t10 GPIO4 RES t11 t12 t11 t12 pi pi Pid gt GPIO1 rm YSCL t13 gt GPIOO XINH t14 t15 lt f gt GPIO6 YSCLD GPIO2 Y FR t16 GPIO3 FRS t17 t17 GRIDS NO DD_P1 Figure 6 37 320x240 Epson D TFD Panel Horizontal Timing S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Vancouver Design Center Table 6 31 320x240 Epson D TFD Panel Horizontal Timing Page 87 Symbol Parameter Min Typ Max Units t1 FPLINE pulse width 9 Ts note 1 t2 FPLINE falling edge to FPSHIFT start position 8 5 Ts t3 FPSHIFT active period 331 Ts t4 FPSHIFT start to first data 6 Ts t5 Horizontal display period 320 Ts t6 Last data to FPSHIFT inactive 5 Ts t7 FPLINE falling edge to GPIO4 first pulse falling edge 1 Ts t8 Horizontal total period 400 Ts t9 GPIO4 first pulse falling edge to second pulse falling edge 200 Ts t10 GPIO4 pulse width 11 Ts t11 GPIO1 pulse width 100 Ts t12 GPIO1 low period 100 Ts t13 GPIOO pulse width 200 Ts t14 GPIO6 low pulse width 90 Ts t15 GPIO6 rising edge to GPIOO falling edge 10 Ts t16 GPIO2 toggle to GPIO3 toggle 1 Ts t17 GPIO5 low pulse width 7 Ts 1 Ts pixel clock period Ha
105. Figure 4 2 Figure 4 3 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 6 10 Figure 6 11 Figure 6 12 Figure 6 13 Figure 6 14 Figure 6 15 Figure 6 16 Figure 6 17 Figure 6 18 Figure 6 19 Figure 6 20 Figure 6 21 Figure 6 22 Figure 6 23 Figure 6 24 Figure 6 25 Figure 6 26 Hardware Functional Issue Date 01 11 13 Epson Research and Development Vancouver Design Center Page 9 List of Figures Typical System Diagram Generic 1 Bus o o 14 Typical System Diagram Generic 2 Bus o o 14 Typical System Diagram Hitachi SH 4 Bus o o e 15 Typical System Diagram Hitachi SH 3 Bus o e 15 Typical System Diagram MC68K 1 Motorola 16 Bit 68000 16 Typical System Diagram MC68K 2 Motorola 32 Bit 68030 16 Typical System Diagram Motorola REDCAP2 Bus 17 Typical System Diagram Motorola MC68EZ328 MC68VZ328 DragonBall Bus 17 Pinout Diagram TQFP15 100pin SID13706FOOA 18 Pinout Diagram CFLGA 104pin S1D13706B00A 00 19 Pinout Diagram Die Form SID13706DODA o o o oo 20 Clock Input Requirements o 33 Generic 1 Interface Timing 2 2 e 36 Generic 2 Interface TiMing ee ee 38 Hitachi SH 4 Interface Timing 2
106. Figures Figure 2 1 Toshiba 3905 12 PC Card Memory Attribute Cycle o oo 9 Figure 2 2 Toshiba 3905 12 PC Card IO Cycle o o o o o 9 Figure 4 1 S1D13706 to TMPR3905 12 Direct Connection o o o 12 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors S1D13706 Issue Date 01 02 23 X31B G 002 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 02 Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13706 Embedded Memory LCD Controller and the Toshiba MIPS TMPR3905 3912 processors The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors S1D13706 Issue Date 01 02 23 X31B G 002 02 Page 8 Epson Research and Development Vancouver Design Center 2 Int
107. Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 NEC Electronics Inc NEC Electronics Inc U S A Corporate Headquarters 2880 Scott Blvd Santa Clara CA 95050 8062 USA Tel 800 366 9782 Fax 800 729 9288 http www necel com North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 01 02 23 Page 17 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13706 X31B G 007 02 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 02 Issue Date 01 02 23 EPSON 1D13706 Embedded Memory LCD Controller Interfacing to the NEC VR4181A Microprocessor Document Number X31B G 008 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without
108. In this case the user is notified Note Manual changes to the registers may have unpredictable results if incorrect values are entered 13706CFG Configuration Program S1D13706 Issue Date 01 03 29 X31B B 001 03 Page 20 Epson Research and Development Vancouver Design Center 13706CFG Menus The following sections describe each of the options in the File and Help menus Open From the Menu Bar select File then Open to display the Open File Dialog Box aj al lla El Look in EME 13706bmp exe 13706cfg exe 13706play exe 13706show exe Files of type fan Configurable Executable Files y Cancel Z The Open option allows 13706CFG to open files containing HAL configuration infor mation When 13706CFG opens a file it scans the file for an identification string and if found reads the configuration information This may be used to quickly arrive at a starting point for register configuration The only requirement is that the file being opened must contain a valid S1D13706 HAL library information block 13706CFG supports a variety of executable file formats Select the file type s 13706CFG should display in the Files of Type drop down list and then select the filename from the list and click on the Open button Note 13706CFG is designed to work with utilities programmed using a given version of the HAL If the configuration structure contained in the executable file differs from the ver sion
109. Invert Bit 2 Bit 1 Bit 0 REG 71h SPECIAL EFFECTS REGISTER RW Display Data Display Data n a Sub Window Wa ia SwivelView Mode Select Word Swap Byte Swap Enable Bit 1 Bit 0 REG 74h MAIN WINDOW DISPLAY START ADDRESS REGISTER 0 RW Main Window Display Start Address Bit 5 Bit 4 Bit 3 Bit 2 REG 75h MAIN WINDOW DISPLAY START ADDRESS REGISTER 1 RW Main Window Display Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 76h Main WINDOW DISPLAY START ADDRESS REGISTER 2 RW n a n a n a n a n a Main Window Display Start Address Bit 16 REG 78h MAIN WINDOW LINE ADDRESS OFFSET REGISTER 0 RW Main Window Line Address Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 1Eh VERTICAL DISPLAY PERIOD START POSITION REGISTER 0 RW Vertical Display Period Start Position REG 79h Main WINDOW LINE ADDRESS OFFSET REGISTER 1 RW Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Main Window Line n a n a n a n a n a n a Address Offset REG 1Fh VERTICAL DISPLAY PERIOD START POSITION REGISTER 1 RW Bit 9 Bit 8 Vertical Display Period n a n a n a n a n a n a Start Position REG 7Ch SuB WinDOw DISPLAY START ADDRESS REGISTER 0 RW bit 9 bit 8 Sub Window Display Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 20h FPLINE PuLse WIDTH REGISTER RW E FPLINE Pulse Width REG 7Dh SUB WINDOW DISPLAY START ADDRESS REGISTER 1 R
110. Mode Enable REG AOh bit 0 18 t7 LCD Signals X ache It is recommended to use one of the general purpose IO pins GPIO 6 4 to control the digital power supply VSHD It is recommended to use one of the general purpose IO pins GPIO 6 4 to control the other power supplies required by the HR TFT panel The S1D13706 LCD power on off sequence is activated by programming the Power Save Mode Enable bit REG AOh bit LCD Signals include FPDAT 17 0 FPSHIFT FPLINE FPFRAME and GPIO 3 0 Figure 2 4 HR TFT Power On Off Sequence Timing Table 2 1 HR TFT Power On Off Sequence Timing Symbol Parameter Min Max Units t1 LCD Power VSHD active to Power Save Mode disabled 0 ns t2 LCD signals low to LCD Power VSHD inactive 0 ns t3 Power Save Mode disabled to LCD Power other active 0 ns t4 LCD Power other inactive to Power Save Mode enabled 0 ns t5 LCD Power other active to MOD active 2 FRAME t6 MOD inactive to LCD Power other inactive 0 ns t7 Power Save Mode disabled to LCD signals active 20 ns t8 Power Save Mode enabled to LCD signals low 20 ns Connecting to the Sharp HR TFT Panels 1D13706 Issue Date 01 02 23 X31B G 011 04 Page 12 2 3 S1D13706 to LQ039Q2DS01 Pin Mapping Epson Research and Development Vancouver Design Center Table 2 2 SIDI3706 to LOO3902D5801 Pin Mapping
111. Note For the example steps where the drive letter is given as x Substitute x with the drive letter that your development environment is on 1 Create a working directory and unzip the UGL display driver into it Using a command prompt or GUI interface create a new directory e g x 13706 Unzip the file 13706ugl zip to the newly created working directory The files will be unzipped to the directories x 13706 8bpp and x 1137061 6bpp 2 Configure for the target execution model This example build creates a VxWorks image that fits onto and boots from a single floppy diskette In order for the VxWorks image to fit on the disk certain modifica tions are required Replace the file x Tornado target config pcPentium config h with the file x 13706 8bpp File config h or x 13706 1 6bpp File config h The new config h file removes networking components and configures the build image for booting from a floppy disk Note Rather than simply replacing the original config h file rename it so the file can be kept for reference purposes 3 Build a boot ROM image From the Tornado tool bar select Build gt Build Boot ROM Select pcPentium as the BSP and bootrom_uncmp as the image 4 Create a bootable disk in drive A From a command prompt in the directory x Tornado target config pcPentium type mkboot a bootrom_uncmp 5 Ifnecessary generate a new mode0 h configurat
112. Page 19 gt uU O om 7n O I S 7A FE O 000000 eeeee 6000000000860 600000000008 0000000000 4640000000006 06000000000 EE EEEE EEE 06000000000 O is 6 6000000 Do O O O O O O 1 2 3 4 5 6 7 8 9 BOTTOM VIEW 10 11 Figure 4 2 Pinout Diagram CFLGA 104pin SIDI3706B00A Table 4 1 CFLGA Pin Mapping L NIOVDD GPIOO GPIO4 COREVDD DBO DB4 DB6 K ido GPO GPIO2 GPIO6 GPIO5 DB2 DB8 DB9 ie J NIOVDD FPFRAME FPLINE CVOUT GPIO3 PWMOUT DB1 DB5 DB7 DB11 HIOVDD H FPDAT1 FPDATO FPSHIFT FPDAT2 DRDY GPIO1 DB3 DB10 DB13 DB14 DB12 G FPDAT5 FPDAT4 FPDAT3 FPDAT6 vss NC vss WE1 CLKI DB15 WAIT F FPDAT10 FPDAT7 FPDAT8 vss vss NC NC vss BS RD WR RESET E FPDAT11 FPDAT9 FPDAT13 FPDAT16 vss NC vss AB1 M R WEO RD D NIOVDD FPDAT12 FPDAT14 CNF7 CNF3 AB13 AB11 AB7 AB3 CS ABO Cc NC FPDAT15 FPDAT17 CNF5 CNF1 TESTEN AB14 AB9 AB5 AB2 HIOVDD B CLKI2 CNF6 CNFO AB15 AB16 AB8 AB4 NC NC A NIOVDD CNF4 CNF2 COREVDD AB12 AB10 AB6 1 2 3 4 5 6 7 8 9 10 11 Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 20 Epson Research and Development Vancouver Design Center 4 3 Pinout Diagram Die Form
113. REG 71h bit 4 2 The effect of REG 84h through REG 9 1h takes place only after REG 9 1h is written and at the next vertical non display period Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 117 Vancouver Design Center PIP Window Y Start Position Register 0 REG 88h Read Write PIP Window Y Start Position Bits 7 0 7 6 5 4 3 2 1 0 PIP Window Y Start Position Register 1 REG 89h Read Write HA PIP Window Y Start Position Bits 9 8 7 6 5 4 3 2 1 0 bits 9 0 PIP Window Y Start Position Bits 9 0 These bits determine the Y start position of the PIP window in relation to the origin of the panel Due to the S1D13706 SwivelView feature the Y start position may not be a vertical position value only true in 0 and 180 SwivelView For further information on defining the value of the Y Start Position register see Section 13 Picture in Picture Plus PIP on page 143 The register is also incremented differently based on the Swivel View orientation For 0 and 180 SwivelView the Y start position is incremented in 1 line increments For 90 and 270 SwivelView the Y start position is incremented by y pixels where y is relative to the current color depth Table 8 12 32 bit Address Increments for Color Depth Color Depth Pixel Increment y 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 Depe
114. Ra 22 EXPORTA LA td o fora hn Bah ere Cheers Fe oat Oe 23 Enable Tooltips 0 dit Boe bi ee ee ok raid ie ee dd 24 ERD on the Web a ii irk Se ite Be Aw oar ba he ar a Re Ass 24 About T3706CFG e i e eles oe he he ee ee ee ee ee ae 24 Comments 8 o a a an he es ee ee nd oe ee a ee ne Be cel ie ee DA 13706CFG Configuration Program 1D13706 Issue Date 01 03 29 X31B B 001 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 13706CFG Configuration Program X31B B 001 03 Issue Date 01 03 29 Epson Research and Development Page 5 Vancouver Design Center 13706CFG 13706CFG is an interactive Windows 9x ME NT 2000 program that calculates register values for a user defined S1D13706 configuration The configuration information can be used to directly alter the operating characteristics of the S1D13706 utilities or any program built with the Hardware Abstraction Layer HAL library Alternatively the configuration information can be saved in a variety of text file formats for use in other applications 1D13706 Supported Evaluation Platforms 13706CFG runs on PC system running Windows 9x ME NT 2000 and can modify the executable files for the following evaluation platforms PC system with an Intel 80x86 processor M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor MC68030IDP Integrated Development Platform board revision 3 0 with a Motor
115. Research and Development Vancouver Design Center 3 3 LCD Pin Mapping for Y Connector LF26SCT Page 17 Table 3 3 LCD Pin Mapping for Y Connector Pins for Y Driver LF26SCT LCD Pin No LCD Pin Name 1D13706 Pin Name Description Remarks Y 1 DYIO1 No Connect Start pulse signal Forward scanning Open Reverse scanning Active low pulse using VCCY and V5Y for logic level Y 2 DYIO2 FPFRAME Start pulse signal Forward scanning Active low pulse using VCCY and V5Y for logic level Reverse scanning Open See Section 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals on page 13 VDD Power supply for liquid crystal drive See Section 2 4 Swing Power Supply for the Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 Y 4 VOY Power supply for liquid crystal drive See Section 2 4 Swing Power Supply for the Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 Y 5 NC No Connect No Connect Y 6 V5Y Power supply for logic low and liquid crystal drive See Section 2 4 Swing Power Supply for the Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 Y 7 VCCY Power supply for logic high See Section 2 4 Swing Power Supply for the Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 Y 8 FRY GPIO2 AC signal for output See Se
116. S1D13706 X31B G 004 04 Figure 10 2 SIDI3706B00C Schematics 2 of 6 S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 1 a 1 4 PSUS 00072 80 IEP epsa lt oog gt g Jequiny juauinoog azis Vancouver Design Center S10 98uu09 497 01 APH D00890LELNSS h Epson Research and Development POOHE UF TE Meer 7i zen 2 ras zi i i i f YIQV3H Odd nro Te PyZLOHbL 029 olano oz 90000104 E590 or paz pve Ly Elexg eve LP NOWMd ZAZ ve FEF Wud Eraz rve Fe 3NMd3 At pvt Agud FeAl evi y 214 IHSd3 Livddig Y FA Rt Livdds otivadsa er LAL Wl Pe gtivada peeLOHbL lan Dz IODA ol Az pve EAZ eve ZAZ eve tke Nid AL pvt _ 2x0z U3OV3H EAI E TAL vi ee v HAGA gt 99918 y agas vbrZLOHbZ lano gz pIYAd4g lYdd4g vad lt 1vYdd48 VT EN ey Y sad LI Vdd 46 Lvdd48 FF YY lyi Z hHYdd4 0lYdd38 01vd438 BT OLWads TT 0 21 wads T T T T Page 30 Issue Date 01 02 23 S5U13706B00C Rev 1 0 Evaluation Board User Manual Figure 10 3 SIDI3706B00C Schematics 3 of 6 1D13706 X31B G 004 04 Page 31
117. S1D13706 output signal REV accomplishes this function and generates the alternating Vcom signal which is superimposed onto Vpr Figure 2 3 Panel Gate Driver AC Power Supplies on page 10 shows the schematic for generating Vcom and VEE ct 22uF 16V 7 NS NDI rev gt 2e 2 jne noz E AN a z ates por HZ 225 180 N7 Tancmos PG Po vss gt gt vee 2 R2 15K 5 R4 27K 5 AT 22uF 16V Y gt gt vcom 100K Re 225 1D13706 X31B G 011 04 Figure 2 3 Panel Gate Driver AC Power Supplies Connecting to the Sharp HR TFT Panels Issue Date 01 02 23 Epson Research and Development Page 11 Vancouver Design Center 2 2 HR TFT MOD Signal The HR TFT panel uses an input signal MOD to control the power on sequencing of the panel This HR TFT signal should not be confused with the S1D13706 signal DRDY referred to as MOD for passive panels To power on the HR TFT panel MOD must be held low until the power supply has been turned on for more than two FRAMES To power off the HR TFT panel MOD must be forced low before the power supply is turned off This sequencing requires two software controlled GPIO pins from the S1D13706 see Figure 2 4 HR TFT Power On Off Sequence Timing t1 t2 lt _ gt gt e GPIOx VSHD power 13 4 lt gt GPIOy other power t5 t6 GPO MOD Power Save
118. Select External decode required M R Memory Register Select External decode required CLKI BUSCLK BS connect to HIO Vpp RD WR connect to HIO Vpp RD RD WEO WE WAIT WAIT RESET Inverted RESET a Interfacing to 8 bit Processors 1D13706 Issue Date 01 02 23 X31B G 015 02 Page 10 Epson Research and Development Vancouver Design Center 3 2 Host Bus Interface Signals 1D13706 X31B G 015 02 The S1D13706 Generic 2 Host Bus Interface requires the following signals from an 8 bit processor CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock The address inputs AB 16 0 connect directly to the 8 bit processor address lines A 16 0 If the specific 8 bit processor cannot implement all 17 address lines required by the S1D13706 only a portion of the 80K byte S1D13706 display buffer is accessible For example if only AB 15 0 are supported only the first 64K byte of the display buffer is available The data bus DB 15 0 must be connected so that the 8 bit processor data lines D 7 0 are connected to both DB 15 8 and DB 7 0 of the S1D13706 CNF4 must be set to select little endian mode Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space M R memory register selects between memory
119. VR4111 Microprocessors S1D13706 Issue Date 01 02 23 X31B G 007 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 02 Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and the NEC VR4102 4111 microprocessor The NEC VR4102 and VR4111 microprocessors are specifically designed to support an external LCD controller The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the NEC VR4102 VR4111 Microprocessors S1D13706 Issue Date 01 02 23 X31B G 007 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4102 VR4111 2 1 The NEC VR41XX System Bus 2 1 1 Overview 1D13706 X31B G 007 02 The VR Series family of microprocessors features a high speed synchronous system bus typical of modern microprocessors Desig
120. Vancouver Design Center JP6 LCD Panel Voltage JP6 selects voltage level to the LCD panel Position 1 2 sets the voltage level to 5 0V default setting Position 2 3 sets the voltage level to 3 3V Note When configured for Sharp HR TFT or Epson D TFD panels JP1 must be set to no jumper and JP6 must be set to position 2 3 JP6 Oee e 0 5 0V 3 3V Figure 3 7 Configuration Jumper JP6 Location JP7 Contrast adjust for ve LCD bias VLCD JP7 selects the type of control used for contrast adjustment of the ve LCD bias VLCD Position 1 2 selects software control of the contrast adjustment Position 2 3 selects manual control of the contrast adjustment using potentiometer R31 default setting a NMI pee z w E E ES L g a ERRERRARRA APRA PEEP REET E Software eee Control Control Figure 3 8 Configuration Jumper JP7 Location S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 4 CPU Interface 4 1 CPU Interface Pin Mapping Table 4 1 CPU Interface Pin Mapping Page 15 1 AO for these busses is not used inte
121. View mode For example co ordinate 0 0 is always the top left corner of the image but this is physically in different corners of the panel depending on what SwivelView mode is selected void seSetPixel long x long y DWORD Color void seSetMainWinPixel long x long y DWORD Color void seSetSubWinPixel long x long y DWORD Color Description Parameters Return Value These routines set a pixel at the location x y with the specified color Use seSetPixel to set one pixel on the current active surface See seSetMainWinAsAc tiveSurface and seSetSubWinAsActiveSurface for information about changing the active surface Use seSetMainWinPixel and seSetSubWinPixel to set one pixel on the surface indi cated in the function name If no memory was allocated to the surface these functions return without writing to dis play memory x The X co ordinate in pixels of the pixel to set y The Y co ordinate in pixels of the pixel to set Color Specifies the color to draw the pixel with Color is interpreted differently at different color depths At 1 2 4 and 8 bpp display colors are derived from the lookup table values The least significant byte of Color forms an index into the lookup table At 16 bpp the lookup table is bypassed and each word of display memory forms the color to display In this mode the least significant word describes the color to draw the pixel with in 5 6 5 RGB format None Programm
122. VxWorks UGL or WindML a comma delimited text file containing an offset a value and a description for each S1D13706 register C Header File for 51013706 HAL Based Applications appetg h Exports C Header File Defining a Map of 51013706 Registers chip C Header File for 51013706 WinCE Drivers mode h Cancel C Header File for 51013706 Generic Drivers s1d13706 h Comma Delimited File Containing Current Configuration 13706regs csv After selecting the file format click the Export As button to display the file dialog box which allows the user to enter a filename before saving Before saving the configuration file clicking the Preview button starts Notepad with a copy of the configuration file about to be saved When the C Header File for S1D13706 WinCE Drivers option is selected as the export type additional options are available and can be selected by clicking on the Options button The options dialog appears as Export Options Mode Number gt sf selects the mode number for f use in the header file Mode number 0 uN Cursor Cursor Support Cancel C Software Cursor selects the type of cursor support enabled in the header file No Cursor SW Blit Emulation ___ L Software Blt Emulation enables software BitBLT emulation in the header file 13706CFG Configuration Program 1D13706 Issue Date 01 03 29 X31B B 001 03 Page 24 Enable Tooltips ERD on the Web Abou
123. WinCE for version 2 12 or later If the environment variable WINCEOSVER is not defined then WINCEVER will default 2 11 The S1D display driver may test against this option to support different WinCE version specific features EnablePreferVvmem This option enables the use of off screen video memory When this option is enabled WinCE can optimize some BLT operations by using off screen video memory to store images You may need to disable this option for systems with limited off screen memory ENABLE_CLOCK_CHIP This option is used to enable support for the ICD2061A clock generator This clock chip is used on the S5U13706B00C evaluation board The S1D13706 display drivers can program the clock chip to support the frequencies required in the MODE tables If you are not using the S5U13706B00C evaluation adapter you should disable this option ENABLE_ANTIALIASED_FONTS This option enables the display driver support of antialiased fonts in WinCE Fonts created with the ANTIALIASED_QUALITY attribute will be drawn with font smoothing If you want all fonts to be antialiased by default add the following line to PLATFORM REG HKEY_LOCAL_MACHINE SYSTEM GDI Fontsmoothing This registry option causes WinCE to draw all fonts with smoothing Font smoothing is only applicable to 16bpp mode Windows CE 3 x Display Drivers 1D13706 Issue Date 01 05 25 X31B E 006 01 Page 12 Epson Research and Development Vancouver Design Center
124. X31B B 003 xx 13706BMP Demonstration Program Users Manual X31B B 004 xx S1D13706 Product Brief X31B C 001 xx S1D13706 Windows CE Display Drivers X31B E 001 xx Interfacing to the Toshiba TMPR3905 3912 Microprocessor X31B G 002 xx S1D13706 Programming Notes And Examples X31B G 003 xx S5U13706BO0C Rev 1 0 Evaluation Board User Manual X31B G 004 xx Interfacing to the PC Card Bus X31B G 005 xx S1D13706 Power Consumption X31B G 006 xx Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 xx Interfacing to the NEC VR4181 Microprocessor X31B G 008 xx Interfacing to the Motorola MPC821 Microprocessor X31B G 009 xx Interfacing to the Motorola MCF5307 Coldfire Microprocessors X31B G 010 xx Connecting to the Sharp HR TFT Panels X31B G 011 xx Connecting to the Epson D TFD Panels X31B G 012 xx Interfacing to the Motorola MC68030 Microprocessor X31B G 013 xx Interfacing to the Motorola RedCap2 DSP with Integrated MCU X31B G 014 xx Interfacing to 8 Bit Processors X31B G 015 xx Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B G 016 xx Integrating the CFLGA 104 pin Chip Scale Package X31B G 018 xx Interfacing to the Intel StrongARM SA 1110 Microprocessor X31B G 019 xx S1D13706 Register Summary X31B R 001 xx Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 153 Vancouver Design Center 18 Sales and Technical Support Japan Seik
125. an index value into the LUT Epson Research and Development Vancouver Design Center The S1D13706 LUT has six bits 64 intensities of intensity control per primary color which is the same as a standard VGA RAMDAC The following table shows LUT values that simulate the VGA default color palette Table 4 8 Suggested LUT Values to Simulate VGA Default 256 Color Palette Index R G B Index R G B jIndex R G B Index R G B 00 00 00 00 40 FO 70 70 80 30 30 70 CO 00 40 00 01 00 00 AO 41 FO 90 70 81 40 30 70 C1 00 40 10 02 00 AO 00 42 FO BO 70 82 50 30 70 C2 00 40 20 03 00 AO AO 43 FO DO 70 83 60 30 70 C3 00 40 30 04 AO 00 00 44 FO FO 70 84 70 30 70 C4 00 40 40 05 AO 00 AO 45 DO FO 70 85 70 30 60 C5 00 30 40 06 AO 50 00 46 BO FO 70 86 70 30 50 C6 00 20 40 07 AO AO AO 47 90 FO 70 87 70 30 40 C7 00 10 40 08 50 50 50 48 70 FO 70 88 70 30 30 C8 20 20 40 09 50 50 FO 49 70 FO 90 89 70 40 30 C9 20 20 40 OA 50 FO 50 4A 70 FO BO 8A 70 50 30 CA 30 20 40 0B 50 FO FO 4B 70 FO DO 8B 70 60 30 CB 30 20 40 0C FO 50 50 4C 70 FO FO 8C 70 70 30 CC 40 20 40 oD FO 50 FO 4D 70 DO FO 8D 60 70 30 CD 40 20 30 0E FO FO 50 4E 70 BO FO 8E 50 70 30 CE 40 20 30 OF FO FO FO 4F 70 90 FO 8F 40 70 30 CF 40 20 20 10 00 00 00 50 BO BO FO 90 30 70 30 DO 40 20 20 11 10 10 10 51 CO BO FO 91 30 70 40 D1 40 20 20 12 20 20 20 52 DO BO FO 92
126. and CLKI2 to different frequencies use the S1D13706 internal clock divides to obtain the lower frequencies S5U13706B00C Rev 1 0 Evaluation Board User Manual S1D13706 Issue Date 01 02 23 X31B G 004 04 Page 24 Epson Research and Development Vancouver Design Center 8 References 8 1 Documents Epson Research and Development Inc 1D13706 Hardware Functional Specification document number X31B A 001 xx Epson Research and Development Inc 1D13806 Programming Notes and Examples document number X31B G 003 xx e Cypress Semiconductor Corporation ICD2061A Data Sheet 8 2 Document Sources e Epson Electronics America Website http www eea epson com e Cypress Semiconductor Corporation Website http www cypress com S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 9 Parts List Table 9 1 Parts List Page 25 rer Manufacturer Part No Item Qty Designation Part Value Description Assembly Instructions C1 C11 C13 C16 Fo 1 21 021 025 027 029 0 1u 50V X7R 5 1206 pckg 2 2 C26 C12 10u 10V 10u 10V Tantalum C Size 10V 10 3 2 C15 014 n p 1206 pckg Do not populate 4 2 C22 C28 22u 10V Tantalum C Size 10V 10 C23 C38 C39 C40 C41 C4 x 2E h 5 10 2 C43 C44 C45 C46 0 22u 50V X7R 5 1206 pckg e f NIPP
127. and byte 2 and byte 3 to be swapped before sending them to the LCD display If the Display Data Word Swap bit is also enabled then the byte order of the fetched 32 bit data is reversed 32 bit display data from display buffer byte 0 gt byte 1 gt Data To LUT byte 2 gt Serialization gt gt byte 3 y y gt Byte Swap Word Swap bit 4 bit 1 0 1D13706 X31B A 001 08 Figure 8 1 Display Data Byte Word Swap Note For further information on byte swapping for Big Endian mode see Section 14 Big Endian Bus Interface on page 146 Picture in Picture Plus PIP Window Enable This bit enables the PIP window within the main window used for the Picture in Picture Plus feature The location of the PIP window within the landscape window is determined by the PIP Window X Position registers REG 84h REG 85h REG 8Ch REG 8Dh and PIP Window Y Position registers REG 88h REG 89h REG 90h REG 91h The PIP window has its own Display Start Address register REG 7Ch REG 7Dh REG 7Eh and Memory Address Offset register REG 80h REG 81h The PIP win dow shares the same color depth and SwivelView orientation as the main window SwivelView Mode Select Bits 1 0 These bits select different Swivel View orientations Table 8 10 SwivelView Mode Select Options SwivelView Mode Sel
128. are dword aligned the last two bits of the starting address must be 0 Note It is possible to use the same image for both the main window and sub window To do so set the sub window line address offset registers to the same value as the main win dow line address offset registers Example 5 Program the main window and sub window registers for a 320x240 pan el at 4 bpp with the sub window positioned at 80 60 with a width of 160 and a height of 120 1 Confirm the main window coordinates are valid The horizontal coordinates must be a multiple of 32 bpp 320 32 4 40 Main window horizontal coordinate is valid 2 Confirm the sub window coordinates are valid The horizontal coordinates and horizontal width must be a multiple of 32 bpp 80 32 4 10 1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 49 Vancouver Design Center Programming Notes and Examples Issue Date 01 02 23 160 32 4 20 Sub window horizontal coordinates and horizontal width are valid Determine the main window display start address The main window is typically placed at the start of display memory which is at display address 0 main window display start address register desired byte address 4 0 Program the Main Window Display Start Address registers REG 74h is set to 00h REG 75h is set to 00h and REG 76h is set to 00h Determine the main window li
129. as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Connecting to the Sharp HR TFT Panels 1D13706 Issue Date 01 02 23 X31B G 011 04 Page 8 Epson Research and Development Vancouver Design Center 2 Connecting to the Sharp LQ039Q2DS01 HR TFT 2 1 External Power Supplies The S1D13706 provides all necessary data and control signals to connect to the Sharp LQ039Q2DS01 320 x 240 HR TFT panel However it does not provide any of the voltages required for gray scaling gate driving or for the digital and analog supplies Therefore external supplies must be designed for any device utilizing the LQ039Q2DS01 2 1 1 Gray Scale Voltages for Gamma Correction The standard gray scale voltages can be generated using a precise resistor divider network that supplies two sets A and B of nine reference voltages to a National Semiconductor 9 Channel Buffer Amplifier LMC6009 The LMC6009 buffers these nine reference voltages and outputs them to the panel column drivers The A B inputs allow the two sets of reference voltages to be alternated compensating for asymmetrical gamma character istics during row inversion This input is controlled b
130. assumes PCI addressing for the S5U13706B00C evaluation board This means that the display driver will automatically locate the S1D13706 by scanning the PCI bus currently only supported for the CEPC platform If you select the address option Other and fill in your own custom addresses for the registers and video memory then the display driver will not scan the PCI bus and will use the specific addresses you have chosen When using 13706CFG EXE to produce multiple MODE tables make sure you change the Mode Number in the WinCE tab for each mode table you generate The display driver supports multiple mode tables but only if each mode table has a unique mode number At this time the drivers have been tested on the x86 CPUs and have been run with version 2 0 of the ETK Platform Builder v2 1x Windows CE 2 x Display Drivers 1D13706 Issue Date 01 05 25 X31B E 001 04 Page 14 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Windows CE 2 x Display Drivers X31B E 001 04 Issue Date 01 05 25 EPSON 1D13706 Embedded Memory LCD Controller Wind River WindML v2 0 Display Drivers Document Number X31B E 002 03 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the
131. available on the internet at www eea epson com 6 2 Disabling the LCD Panel S1D13706 X31B G 003 03 The HAL function seDisplayEnable FALSE can be used to disable the LCD panel The function disables the LCD panel using the following steps 1 Disable the LCD power using GPO 2 Wait for the LCD bias power supply to discharge based on the delay time as specified in the LCD panel specification 3 Disable the LCD signals Set Display Blank bit REG 70h bit 7 to 1 4 At this time the LCD pixel clock source may be disabled Optional Note the LUT must not be accessed if the pixel clock is not active Note seLcdDisplayEnable is included in the C source file hal_misc c available on the internet at www eea epson com Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 31 Vancouver Design Center 7 SwivelView Most computer displays operate in landscape mode In landscape mode the display is wider than it is high For example a standard display size of 320x240 is 320 pixels wide and 240 pixels wide SwivelView rotates the display image counter clockwise in ninety degree increments possibly resulting in a display that is higher than it is wide Rotating the image on a 320x240 display by 90 or 270 degrees yields a display that is now 240 pixels wide and 320 pixels high SwivelView also works with panels that are designed with a portrait orientation In this case when Swivel
132. bit Processor System Bus 1D13706 X31B G 015 02 Although the S1D13706 does not directly support an 8 bit CPU an 8 bit interface can be achieved with minimal external logic Typically the bus of an 8 bit microprocessor is straight forward with minimal CPU and system control signals To connect a memory mapped device such as the S1D13706 only the write read and wait control signals plus the data and address lines need to be inter faced Since the 1D13706 is a 16 bit device some external logic is required Interfacing to 8 bit Processors Issue Date 01 02 23 Epson Research and Development Page 9 Vancouver Design Center 3 S1D13706 Host Bus Interface The S1D13706 directly supports multiple processors The S1D13706 implements a 16 bit Generic 2 Host Bus Interface which can be adapted for use with an 8 bit processor The Generic 2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 12 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping areca Generic 2 Comments AB 16 0 A 16 0 DB 15 0 D 15 0 WE1 Byte High Enable BHE External decode required CS Chip
133. built At the root of the Project source tree type make Note To build drivers for X86 NTO type OSLIST nto CPULIST x86 make Further builds do not require all libraries to be re built To build only the S1D13706 display driver change to the directory gddk_1 0 devg S1D13706 and type make QNX Photon v2 0 Display Driver Issue Date 01 09 10 Epson Research and Development Page 5 Vancouver Design Center Installing the Driver The build step produces two library images e lib disputil nto x86 libdisputil so e lib disputil nto x86 libffb so For the loader to locate them the files need to be renamed and copied to the lib directory 1 Rename libdisputil so to libdisputil so 1 and libffb so to libffb so 1 2 Copy the files new files libdisputil so 1 and libffb so 1 to the directory usr lib 3 Copy the file devg S1D13706 so to the lib dll directory Note To locate the file devg S1D13706 so watch the output of the true command during the makefile build 4 Modify the trap file graphics modes in the etc system config directory by inserting the following lines at the top of the file io graphics dldevg S 1D 13506 so g640x480x8 I0 d0x0 0x0 640 480 8 Epson io graphics dldevg S 1D 13506 so g640x480x16 I0 d0x0 0x0 640 480 16 Epson Run the Driver Note For the remaining steps the S5U13706B00C evaluation board must be installed on the test platform It is recommended that the driver be verified before sta
134. but only if each mode table has a unique mode number At this time the drivers have been tested on the x86 CPUs and have been built with Plat form Builder v3 00 Windows CE 3 x Display Drivers Issue Date 01 05 25 EPSON S1D13XXX 32 Bit Windows Device Driver Installation Guide Document No X00A E 003 04 Copyright O 1999 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13XXX 32 Bit Windows Device Driver Installation Guide X00A E 003 04 Issue Date 01 04 17 Epson Research and Development Page 3 Vancouver Design Center S1D13XXX 32 Bit Windows Device Driver Installation Guide This manual describes the installation of the Windows 9x ME NT 4 0 2000 device drivers for the S5U13xxxB00x series of Epson Evaluation Boards The file S1D13XXX VXD is requir
135. configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the Motorola MPC821 Microprocessor 1D13706 Issue Date 01 02 23 X31B G 009 02 Page 22 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e Motorola Inc Power PC MPC821 Portable Systems Microprocessor User s Manual Motorola Publication no MPC821UM available on the Internet at http www mot com SPS ADC pps _subpgs _documentation 821 821UM html e Epson Research and Development Inc S1D 3706 Hardware Functional Specification Document Number X31B A 001 xx e Epson Research and Development Inc SSUI3706BO0C Rev 1 0 Evaluation Board User Manual Document Number X31B G 004 xx e Epson Research and Development Inc Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources e Motorola Inc Literature Distribution Center 800 441 2447 e Motorola Inc Website http www mot com e Epson Electronics America website http www eea epson com 1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 02 Issue Date
136. connected to CARD1CSH and is the high byte enable for both read and write cycles WEO is connected to CARDIOWR the write enable signal and must be driven low when the Toshiba TMPR3905 12 is writing data to the S1D13706 RD is connected to CARDIORD the read enable signal and must be driven low when the Toshiba TMPR3905 12 is reading data from the S1D13706 WAIT connects to CARDIWAIT and is a signal which is output from the S1D13706 to the TMPR3905 12 that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13706 may occur asynchro nously to the display update it is possible that contention may occur in accessing the S1D13706 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS and Read Write RD WR signals are not used in this implemen tation of the Toshiba TMPR3905 12 using the Generic 2 Host Bus Interface These pins must be tied high connected to HIO Vpp Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors 1D13706 Issue Date 01 02 23 X31B G 002 02 Page 12 Epson Research and Development Vancouver Design Center 4 Toshiba TMPR3905 12 to S1D13706 Interface 4 1 Hardware Description In this implementation the S1D13706 occupies the TMPR3905 12 PC Card slot 1 IO address space IO address space closely matches th
137. depth bpp display type rotation etc The mode0 h file included with the drivers may not contain applicable values and must be regenerated The configuration pro gram 13706CFG can be used to build a new mode0 h file If building for 8 bpp place the new mode0 h file in the directory x 13706 8bpp File If building for 16 bpp place the new mode0 h file in x 13706 16bpp File Wind River WindML v2 0 Display Drivers Issue Date 01 04 06 Epson Research and Development Page 5 Vancouver Design Center Note Mode0 h should be created using the configuration utility 13706CFG For more infor mation on 13706CFG see the 13706CFG Configuration Program User Manual docu ment number X31B B 001 xx available at www erd epson com 6 Build the WindML v2 0 library From a command prompt change to the directory x Tornado host x86 win32 bin and run the batch file torvars bat Next change to the directory x Tornado tar get src ugl and type the command make CPU PENTIUM ugl 7 Open the 1D13706 workspace From the Tornado tool bar select File gt Open Workspace gt Existing gt Browse and select the file x 13706 8bpp 13706 wsp or x113706116bpp113706 wsp 8 Add support for single line comments The WindML v2 0 display driver source code uses single line comment notation rather than the ANSI conventional comments To add support for single line comments follow thes
138. document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Wind River WindML v2 0 Display Drivers X31B E 002 03 Issue Date 01 04 06 Epson Research and Development Page 3 Vancouver Design Center Wind River WindML v2 0 DISPLAY DRIVERS The Wind River WindML v2 0 display drivers for the S1D13706 Embedded Memory LCD Controller are intended as reference source code for OEMs developing for Wind River s WindML v2 0 The driver package provides support for both 8 and 16 bit per pixel color depths The source code is written for portability and contains functionality for most features of the S1D13706 Source code modification is required to provide a smaller more efficient driver for mass production The WindML display drivers are designed around a common configuration include file called mode0 h which is generated by the configuration utility 13706CFG This design allows for easy customization of display type clocks decode addresses rotation etc by OEMs For further information on 13706CFG see the 3706CFG Configu
139. e 148 Mechanical Data 100pin TQFP15 S1D13706F00A o o o o 150 Mechanical Data 104pin CFLGA SID13706BOOA 151 Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 11 Vancouver Design Center 1 Introduction 1 1 Scope This is the Hardware Functional Specification for the S1D13706 Embedded Memory LCD Controller Included in this document are timing diagrams AC and DC characteristics register descriptions and power management descriptions This document is intended for two audiences Video Subsystem Designers and Software Developers For additional documentation related to the S1D13706 see Section 17 References on page 152 This document is updated as appropriate Please check the Epson Research and Devel opment Website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com 1 2 Overview Description The S1D13706 is a color monochrome LCD graphics controller with an embedded 80K byte SRAM display buffer While supporting all other panel types the S1D13706 is the only LCD controller to directly interface to both the Epson D TFD and the Sharp HR TFT family of products thus removing the requirement of an external Timing Control IC This high level of integration provides a low cost low power single chi
140. e areor ans aoira ee ee 11 4 VR4102 VR4111 to S1D13706 Interface es 12 4 1 Hardware Description o esi goias eoa man ee ee 1 4 2 S1D13706 Hardware Configuration 2 2 ee eee ee ee 13 4 3 NEC VR4102 VR4111 Configuration 2 2 eee 14 5 DONWAIG oe ELE ee ARS aa oe hee ee 15 ROTerences ao e as eae da a ee we oe de 16 GL DOCUMEN S ura a a a aa A A rd a a ar I 6 2 DocumentSources 1 ee ee 16 Technical S pport e ogee hoe ele Rog E we Sk ale eae ed eens 17 7 1 Epson LCD Controllers SI1D13706 o eee ee eT Ta NEC Electronics Mc cie el ok Be ae a Re ee ee a ee TF Interfacing to the NEC VR4102 VR4111 Microprocessors 1D13706 Issue Date 01 02 23 X31B G 007 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 02 Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 2 000000 eee 10 Table 4 2 CLKI to BCLK Divide Selection o o e e 13 Table 4 1 Summary of Power On Reset Configuration Options o 13 List of Figures Figure 2 1 NEC VR4102 VR4111 Read Write Cycles o o o 9 Figure 4 1 Typical Implementation of VR4102 VR4111 to S1D13706 Interface 12 Interfacing to the NEC VR4102
141. ee ee a Pe TS Typical System Implementation Diagrams 088082 eae 14 PINS era See and Gene eo ve tat ea a ae E le AA a ee a a 18 4 1 Pinout Diagram TQFP15 100pin 2 2 18 4 2 Pinout Diagram CFLGA 104pin 2 ee 19 4 3 Pinout Diagram Die Form 2 2 2 2 20 4 4 PinDescriptions z o os sanno aua ee 22 dakie Host Iinteriace a eee eS aes Gee bd a ea hls eb de fe 22 44 2 LODiInterfaces o tua bd ene Bcd ea Se hae A de edt beh dh aed a eal be as 26 4 4 3 gt Clock Input tuo ape eid we Beg he a A ek Be titi 28 ALA Miscellaneous iS fy a et E ee eR Ae OE 28 4 4 5 Power AndGround aa p aa a E a Ge k e ee 28 4 5 Summary of Configuration Options a a a a a a a 29 4 6 Host Bus Interface Pin Mapping 30 4 7 LCD Interface Pin Mapping 2 2 2 31 D C Characteristics aiii is a O ee as VA 32 AC Characteristics ic oe ag ee a a a A 33 6 1 Clock Timmg 2005026404 Bode ce RO BE a ee eo a ee 33 GLE Input Clocks sy ica ad Moe A a ble oii a ead 33 6 1 2 Internal Clocks wir nf as ak Se When SA Aa Sr kM a 35 6 2 CPU Interface Timing S 6 2 1 Generic 1 Interface Timing 0 200 000 0000 000 4 36 6 2 2 Generic 2 Interface Timing e g ISA o oo 0 000 38 6 2 3 Hitachi SH 4 Interface Timing e 40 6 2 4 Hitachi SH 3 Interface Timing e 42 6 2 5 Motorola M
142. environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system The two methods are described below 1 To start CEPC after booting from a floppy drive a Create a bootable floppy disk b Edit CONFIG SYS on the floppy disk to contain only the following line device a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy LOADCEPC EXE and HIMEM SYS to the bootable floppy disk Search for the loadCEPC utility in your Windows CE directories e Copy NK BIN to c f Boot the system from the bootable floppy disk 2 To start CEPC after booting from a hard drive a Copy LOADCEPC EXE to CA Search for the loadCEPC utility in your Windows CE directories b Edit CONFIG SYS on the hard drive to contain only the following line device c himem sys c Edit AUTOEXEC BAT on the hard drive to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy NK BIN and HIMEM SYS to c e Boot the system S1D13706 Windows CE 2 x Display Drivers X31B E 001 04 Issue Date 01 05 25 Epson Research and Development Page 11 Vancouver Design Center Configuration There are several issues to consider when configuring the display driver The issues cover debugging support register initialization values and memory allocation Each of these issues is discussed in the
143. first pixel Figure 6 29 TFT A C Timing S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 75 Vancouver Design Center Table 6 23 TFT A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME cycle time VT Lines t2 FPFRAME pulse width low VPW Lines t3 FPFRAME falling edge to FPLINE falling edge phase difference HPS Ts note 1 t4 FPLINE cycle time HT Ts t5 FPLINE pulse width low HPW Ts t6 FPLINE Falling edge to DRDY active note 2 250 Ts t7 DRDY pulse width HDP Ts t8 DRDY falling edge to FPLINE falling edge note 3 Ts t9 FPSHIFT period 1 Ts t10 FPSHIFT pulse width high 0 5 Ts t11 FPSHIFT pulse width low 0 5 Ts t12 FPLINE setup to FPSHIFT falling edge 0 5 Ts t13 DRDY to FPSHIFT falling edge setup time 0 5 Ts t14 DRDY hold from FPSHIFT falling edge 0 5 Ts t15 Data setup to FPSHIFT falling edge 0 5 Ts t16 Data hold from FPSHIFT falling edge 0 5 Ts 1 Ts pixel clock period 2 t6min HDPS HPS if negative add HT 3 t8min HPS HDP HDPS if negative add HT Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 76 Epson Research and Development Vancouver Design Center 6 4 10 160x160 Sharp Direct HR TFT Panel Timing e g LQ031B1DDxx FPFRAME i SPS e a FA z ae LP gt FPLINE LP 14 Sac RUIN
144. from being allocated in display memory it MUST be allocated from system mem ory Since the main display data is copied to system memory on suspend and then simply copied back on resume this mode is FAST but not as fast as mode 0 Windows CE 3 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 15 Vancouver Design Center c PORepaint 2 e This mode tells WinCE to not save the main display data on suspend and causes WinCE to REPAINT the main display on resume e This mode is used if display memory power is going to be turned off when the system is suspended and there is not enough system memory to save the im age e Any off screen data in display memory is LOST and since there is insuffi cient system memory to save display data off screen memory usage MUST be disabled e When the system is resumed WinCE instructs all running applications to re paint themselves This is the SLOWEST of the three modes Simple Display Driver Configuration The following display driver configuration should work with most platforms running Windows CE This configuration disables the use of off screen display memory and forces the system to redraw the main display upon power on 1 Windows CE 3 x Display Drivers Issue Date 01 05 25 This step disables the use of off screen display memory Edit the file x wince300 platform cepc drivers display S 1D13706 sources and change the line CDEFINES CDEFINES
145. geometry of the S1D13706 display memory Most HAL functions either allocate surface memory or manip ulate a surface that has been allocated Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 77 Vancouver Design Center The functions in this section allow the application programmer a little greater control over surfaces int seGetSurfaceDisplayMode void Description Parameters Return Value This function determines the type of display associated with the current active surface None The return value indicates the active surface display type Return values will be one of MAIN_WIN The main window is the active surface SUB_WIN The sub window is the active surface DWORD seGetSurfaceSize void Description Parameters Return Value This function returns the number of display memory bytes allocated to the current active surface None The return value is the number of bytes allocated to the current active surface The return value will be O if this function is called before initializing the registers DWORD seGetSurfaceLinearAddress void Description Parameters Return Value This function returns the linear address of the start of memory for the active surface None The return value is the linear address to the start of memory for the active surface A linear address is a 32 bit offset in CPU address space The return value will be NULL if this function is
146. in 0 and 180 SwivelView For further information on defining the value of the Y Start Position registers see Section 8 3 Picture In Picture Plus Examples on page 48 The registers is also incremented differently based on the SwivelView orientation For 0 and 180 SwivelView the Y start position is incremented in 1 line increments For 90 and 270 SwivelView the Y start position is incremented by Y pixels where Y is relative to the current color depth Table 8 2 32 bit Address Increments for Color Depth Bits Per Pixel Color Depth Pixel Increment Y 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 43 Vancouver Design Center In SwivelView 0 these registers set the vertical coordinates y of the sub windows s top left corner Increasing values of y move the top left corner downwards in steps of 1 line Program the Sub Window Y Start Position registers so that sub window Y start position registers y In Swivel View 90 these registers set the horizontal coordinates x of the sub window s top right corner Increasing values of x move the top right corner towards the right in steps of 32 bits per pixel see Table 8 2 Program the Sub Window Y Start Position registers so that sub window Y start position registers panel height x 32 bits per pixel Note panel height x must
147. it From a command prompt or GUI interface create a new directory e g x 13706 Unzip the file 13706windml zip to the newly created working directory The files will be unzipped to the directories x 13706 8bpp and x 13706 16bpp 2 Configure for the target execution model This example build creates a VxWorks image that fits onto and boots from a single floppy diskette In order for the VxWorks image to fit on the disk certain modifica tions are required Replace the file x Tornado target config pcPentium config h with the file x 13706 8bpp File config h or x 13706 1 6bpp File config h The new config h file removes networking components and configures the build image for booting from a floppy disk Note Rather than simply replacing the original config h file rename it so the file can be kept for reference purposes 3 Build a boot ROM image From the Tornado tool bar select Build gt Build Boot ROM Select pcPentium as the BSP and bootrom_uncmp as the image 4 Create a bootable disk in drive A From a command prompt change to the directory x Tornado host x86 win32 bin and run the batch file torvars bat Next change to the directory x Tornado tar get config pcPentium and type mkboot a bootrom_uncmp 5 Ifnecessary generate a new mode0 h configuration file The file mode0 h contains the register values required to set the screen resolution col or
148. likewise typically used to control a large static or dynamic RAM block Chip selects 2 through 7 have fixed block sizes of 2M bytes each Each has a unique fixed offset from a common programmable starting address These chip selects are well suited to typical IO addressing requirements Each chip select may be individually programmed for e port size 8 16 32 bit e up to 15 wait states or external acknowledge e address space type e burst or non burst cycle support e write protect Figure 2 3 Chip Select Module Outputs Timing illustrates a typical cycle for a memory mapped device using the GPCM of the Power PC ax d Lara CS 7 0 BE BWE 3 0 OE Figure 2 3 Chip Select Module Outputs Timing 1D13706 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X31B G 010 02 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center Page 11 3 S1D13706 Host Bus Interface The S1D13706 directly supports multiple processors The S1D13706 implements a 16 bit Generic 1 Host Bus Interface which is most suitable for direct connection to the Motorola MFC5307 microprocessor Generic 1 supports a Chip Select and an individual Read Enable Write Enable for each byte The Generic 1 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config urati
149. n a n a n a n a n a n a n a Bit 16 These registers represent a dword address which points to the start of the main window image in the display buffer An address of 0 is the start of the display buffer For the following SwivelView mode descriptions the desired byte address is the starting display address for the main window image and panel width and panel height refer to the physical panel dimensions Note Truncate all fractional values before writing to the address registers In SwivelView 0 program the start address desired byte address 4 In SwivelView 90 program the start address desired byte address panel height x bpp 8 4 1 1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 33 Vancouver Design Center In SwivelView 180 program the start address desired byte address panel width x panel height x bpp 8 4 1 In Swivel View 270 program the start address desired byte address panel width 1 x panel height x bpp 8 4 Note SwivelView 0 and 180 require the panel width to be a multiple of 32 bits per pixel SwivelView 90 and 270 require the panel height to be a multiple of 32 bits per pix el If this is not possible a virtual display one larger than the physical panel size is re quired which does satisfy the above requirements To create a virtual display program the main window line address offset
150. occupies the second 128K byte block In this example the S1D13706 internal registers are accessed starting at address 4100 0000h and the display buffer is accessed starting at address 4102 0000h Each Chip Select on the REDCAP is allocated a 16M byte block However the S1D13706 only needs a 256K byte block of memory to accommodate its register set and 80K byte display buffer For this reason only address bits A 17 0 are used while A 21 18 are ignored The 1D13706 s memory and register are aliased every 256K bytes in the 16M byte CS1 address space Note If aliasing is not desirable the upper addresses must be fully decoded 1D13706 X31B G 014 02 Interfacing to the Motorola RedCap2 DSP With Integrated MCU Issue Date 01 02 23 Page 16 Epson Research and Development Vancouver Design Center 4 5 REDCAP2 Chip Select Configuration 1D13706 X31B G 014 02 In this example Chip Select 1 controls the S1D13706 The following options are selected in the CS1 Control Register e CSEN 1 Chip Select function enabled e WP 0 writes allowed e SP 0 user mode access allowed e DSZ 10 16 bit Port e EBC 0 assert EBO 1 for both reads and writes e WEN 1 EBO I negated half a clock earlier during write cycle e OEA 1 OE asserted half a clock later during a read cycle e CSA 0 Chip Select asserted as early as possible No idle cycle inserted between back to back external transfers e
151. of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Connecting to the Epson D TFD Panels 1D13706 Issue Date 01 02 23 X31B G 012 03 Page 8 Epson Research and Development Vancouver Design Center 2 External Power Supplies The S1D13706 provides all necessary data and control signals to connect to the Epson LF37SQT and LF26SCT D TFD panels However it does not provide any of the vertical and horizontal logic voltages contrast or brightness voltages or the horizontal and vertical liquid crystal driving voltages Therefore external supplies must be designed for any device utilizing these D TFD panels 2 1 VDDH and VDD Horizontal and Vertical Analog Voltages VDDH and VDD control the horizontal and vertical drivers that activate the liquid crystals in the D TFD display The range of VDDH is from 4 5V to 5 5V and VDD is from 4 0V to 5 0V These voltages should be set to 4 5V VDDH and VDD must be activated after all D TFD control signals are active and should be deactivated after the control signals are inactive Figure 2 1 VDDH and VDD Voltage Generation shows an example implementation which generates VDDH and VDD from 3 3V
152. of the LCD seGetBytesPerScanline returns the number of bytes per scanline for the current active surface seGetMainWinBytesPerScanline and seGetSubWinBytesPerScanline return the num ber of bytes per scanline for the surface indicated in the function name To work correctly these routines require the S1D13706 registers to be initialized prior to being called None The return value is the stride or number of bytes from the first byte of one scanline to the first byte of the next scanline This value includes both the displayed and the non dis played bytes on each logical scanline void seSetPowerSaveMode BOOL Enable Description 1D13706 X31B G 003 03 This function enables or disables the power save mode When power save mode is enabled the S1D13706 reduces power consumption by making the displays inactive and ignoring memory accesses Disabling power save mode re enables the video system to full functionality When powering down the following steps are implemented 1 Disable LCD power 2 Delay for LCD power down time interval see seSetPowerDownDelay 3 Enable power save mode Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 71 Vancouver Design Center When powering up the following steps are implemented 1 Disable power save mode 2 Delay for LCD power up time interval see seSetPowerUpDelay 3 Enable LCD power Note seSetPowerSaveMode waits on
153. on the Toshiba 3905 12 PC Card bus A 25 0 x ALE IN D 31 16 x CARD1CSL CARD1CSH CARDIORD CARDIOWR CARD1WAIT CARDREG Figure 2 2 Toshiba 3905 12 PC Card IO Cycle Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors S1D13706 X31B G 002 02 Issue Date 01 02 23 Page 10 Epson Research and Development Vancouver Design Center 3 S1D13706 Host Bus Interface The S1D13706 directly supports multiple processors The S1D13706 implements a 16 bit Generic 2 Host Bus Interface which is most suitable for connection to the Toshiba 3 1 Host Bus Interface Pin Mapping 1D13706 X31B G 002 02 TMPR3905 12 microprocessor The Generic 2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Config uration on page 14 The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping es Toshiba TMPR3905 12 AB 16 0 External Decode DB 15 8 D 23 16 DB 7 0 D 31 24 WE1 External Decode CS External Decode M R External Decode CLKI DCLKOUT BS connect to HIO Vpp RD WR connect to HIO Vpp RD CARDIORD WEO CARDIOWR WAIT CARD1WAIT RESET system RESET
154. onto the desktop using the right mouse button f Click on Copy Here g Rename the icon X86 DEMO1 on the desktop to X86 DEMO by right click ing on the icon and choosing rename h Right click on the icon X86 DEMO7 and click on Properties to bring up the X86 DEMO7 Properties window i Click on Shortcut and replace the string DEMO1 under the entry Target with DEMO7 j Click on OK to finish 5 Create a sub directory named S1D13706 under x wince platform cepc drivers dis play 6 Copy the source code to the S1D13706 subdirectory Windows CE 2 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 5 Vancouver Design Center 7 10 Windows CE 2 x Display Drivers Issue Date 01 05 25 Edit the file x wince platform cepc drivers display dirs and add S1D13706 into the list of directories Edit the file PLATFORM BIB located in x wince platform cepc files to set the de fault display driver to the file EPSON DLL EPSON DLL will be created during the build in step 13 Replace or comment out the following lines in PLATFORM BIB IF CEPC_DDI_VGA2BPP ddi dll _FLATRELEASEDIR ddi_vga2 dll NK SH ENDIF IF CEPC_DDI_VGA8BPP ddi dll _FLATRELEASEDIR ddi_vga8 dll NK SH ENDIF IF CEPC_DDI_VGA2BPP IF CEPC_DDI_VGASBPP ddi dll _FLATRELEASEDIR ddi_s364 dll NK SH ENDIF ENDIF with this line ddi dll FLATRELEASEDIRANEP
155. outputs Little Endian bus interface Active low WAIT configuration for MC68VZ328 microprocessor S1D13706 X31B G 016 02 Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 N recommended setting for MC68VZ328 microprocessor Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 01 02 26 Epson Research and Development Page 13 Vancouver Design Center 4 2 1 Register Memory Mapping The S1D13706 requires two 128K byte segments in memory for the display buffer and its internal registers To accommodate this block size it is preferable but not required to use one of the chip selects from groups A or B Groups A and B can have a size range of 128K bytes to 16M bytes and groups C and D have a size range of 32K bytes to 16M bytes Therefore any chip select other than CSAO would be suitable for the S1D13706 interface In the example interface chip select CSB1 controls the S1ID13706 A 256K byte address space is used with the S1D13706 internal registers occupying the first 128K byte block and the 80K byte display buffer located in the second 128K byte block A17 from the MC68VZ328 is used to select between these two 128K byte blocks 4 2 2 MC68VZ328 Chip Select and Pin Configuration The chip select used to map the S1D13706 in this example CSB1 must have its RO Read Only bit set to 0 its BSW Bus Data Width set
156. passive LCD panel support 4 8 16 bit 3 3V or 5V single color passive LCD panel support 9 12 18 bit 3 3V or 5V active matrix TFT LCD panel support Direct interface for 18 bit Epson D TFD LCD panel support Direct interface for 18 bit Sharp HR TFT LCD panel support Programmable clock synthesizer to CLKI and CLKI2 for maximum clock flexibility Software initiated power save mode Hardware or software Video Invert support Selectable clock source for CLKI and CLKI2 External oscillator for CLKI and CLKI 2 S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 Epson Research and Development Page 9 Vancouver Design Center 3 Installation and Configuration The S5U13706B00C is designed to support as many platforms as possible The S5U13706B00C incorporates a DIP switch and seven jumpers which allow both evaluation board and S1D13706 LCD controller to be configured for a specified evaluation platform 3 1 Configuration DIP Switches The S1D13706 has configuration inputs CNF 7 0 which are read on the rising edge of RESET In order to configure the 1D13706 for multiple Host Bus Interfaces a ten position DIP switch S1 is required The following figure shows the location of DIP switch SW1 on the S5U13706B00C DIP Switch SW1 Figure 3 1 Configuration DIP Switch SW1 Location S5U13706B00C Rev
157. pulse decrements VDDH one step towards 20V When decremented beyond 20V VDDH resets to 40V again In other words 63 pulses equal incrementing 1 step After the MAX754 is reset see Controlling the MAX754 on page 21 VDDH is set at 30V S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 Epson Research and Development Page 21 Vancouver Design Center The S5U13706B00C uses GPO and CVOUT to control the MAX754 as shown in the following table Table 6 1 Controlling the MAX754 Signal Turn MAX754 On Turn MAX754 Off Reset MAX754 GPO high low low CVOUT X low high X don t care When JP5 is set to position 2 3 VDDH is adjustable using R24 200Q potentiometer to provide an output voltage from 24V to 40V Note When manually adjusting the voltage set the potentiometer according to the panel s specific power requirements before connecting the panel 6 5 Manual Software Adjustable LCD Panel Negative Power Supply VLCD Most passive monochrome LCD panels require a negative bias voltage between 14V and 24V The S5U13706B00C uses a Maxim MAX749 Digitally Adjustable LCD Bias Supply to provide this voltage range The signal VLCD can be adjusted manually using a potenti ometer or controlled through software When JP7 is set to position 1 2 VLCD can be controlled through software to provide an output voltage from 8V to 24V CVOUT and GPO of the 1D
158. remain disabled unless you are performing specific debugging tasks that require the debug monitor Windows CE 2 x Display Drivers 1D13706 Issue Date 01 05 25 X31B E 001 04 Page 12 MonoPanel Mode File 1D13706 X31B E 001 04 Epson Research and Development Vancouver Design Center This option is intended for the support of monochrome panels only The option causes palette colors to be grayscaled for correct display on a mono panel For use with color panels this option should not be enabled A second variable which will affect the finished display driver is the register configurations contained in the mode file The MODE tables contained in files MODE0 H MODE1 H MODE2 H contain register information to control the desired display mode The MODE tables must be generated by the configuration program 13706CFG EXE The display driver comes with example MODE tables By default only MODEO H is used by the display driver New mode tables can be created using the 13706CFG program Edit the include section of MODE H to add the new mode table If you only support a single display mode you do not need to add any information to the WinCE registry If however you support more that one display mode you should create registry values see below that will establish the initial display mode If your display driver contains multiple mode tables and if you do not add any registry values the display driver will default to the fi
159. requires the following signals CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example CLK from the Motorola MC68030 is used for CLKI The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the MC68030 address A 16 0 and data bus D 31 16 respectively CNF4 must be set to select big endian mode Chip Select CS must be driven low by the external address decode circuitry whenever the S1D13706 is accessed by the Motorola MC68030 M R memory register selects between memory or register accesses This signal is generated by the external address decode circuitry WEO connects to SIZO one of the transfer size signals of the MC68030 Along with SIZ1 this signal indicates how many bytes are to be transferred during the current cycle WE1 connects to DS the data strobe signal from the MC68030 and must be driven low when valid data has been placed on the bus RD connects to external decode circuitry of SIZ1 one of the transfer size signals of the MC68030 Along with SIZO this signal indicates how many bytes are to be transferred during the current cycle RD WRH is the read or write enable signal and connects to R W of the MC68030 This signal drives low when the MC68030 is writing to the S1D13706 and drives high when the MC68030 is reading from the S1D13706 WAI
160. respective function ar gument This is to ensure that the value programmed into the address offset registers is a multiple of 4 bytes For example suppose seVirtInit 240 320 is called in Swivel View 90 and at 1 bits per pixel Since four bytes corresponds to 32 pixels in 1 bits per pixel mode the width must be a multiple of 32 Since 240 is not a multiple of 32 the width is automatically changed to the next available multiple which in this case is 256 Width The desired virtual width of the display in pixels Width must be a multiple of the number of pixels contained in one dword of display memory In other words Width must be a multiple of 32 bits per pixel Height The desired virtual height of the display in pixels The HAL performs internal memory management to ensure that all display surfaces have sufficient memory for operation The Height parameter is required so the HAL can determine the amount of memory the application requires for the virtual image ERR_OK The function completed successfully ERR_HAL_BAD_ARG The requested virtual dimensions are smaller than the physical display size Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 88 Epson Research and Development Vancouver Design Center ERR_NOT_ENOUGH_MEMORY There is insufficient free display memory to set the requested virtual display size void seVirtPanScroll DWORD x DWORD y void seMainWinVirtPanScroll DWORD x DWORD
161. set according to the horizontal sync signal of the panel typically FPLINE or LP When this bit 0 the horizontal sync signal is active low When this bit 1 the horizontal sync signal is active high bits 6 0 FPLINE Pulse Width Bits 6 0 These bits specify the width of the panel horizontal sync signal in 1 pixel resolution The horizontal sync signal is typically FPLINE or LP depending on the panel type FPLINE Pulse Width in number of pixels REG 20h bits 6 0 1 Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 56 S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 107 Vancouver Design Center FPLINE Pulse Start Position Register 0 REG 22h Read Write FPLINE Pulse Start Position Bits 7 0 7 6 5 4 3 2 1 0 FPLINE Pulse Start Position Register 1 REG 23h Read Write mA FPLINE Pulse Start Position Bits 9 8 7 6 5 4 3 2 1 0 bits 9 0 FPLINE Pulse Start Position Bits 9 0 These bits specify the start position of the horizontal sync signal in 1 pixel resolution FPLINE Pulse Start Position in pixels REG 23h bits 1 0 REG 22h bits 7 0 1 Note For passive panels these bits must be programmed such that the following formula is valid HPW HPS lt HT Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inte
162. shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Connecting to the Epson D TFD Panels Issue Date 01 02 23 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Page 23 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13706 X31B G 012 03 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Connecting to the Epson D TFD Panels X31B G 012 03 Issue Date 01 02 23 EPSON 1D13706 Embedded Memory LCD Controller Interfacing to the Motorola RedCap2 DSP With Integrated MCU Document Number X31B G 014 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the do
163. signal from the PC Card bus and must be driven low when the PC Card bus is reading data from the S1D13706 WAIT is a signal output from the S1D13706 that indicates the PC Card bus must wait until data is ready read cycle or accepted write cycle on the host bus Since PC Card bus accesses to the S1D13706 may occur asynchronously to the display update it is possible that contention may occur in accessing the 13706 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS and Read Write RD WR signals are not used in this implemen tation of the PC Card bus using the Generic 2 Host Bus Interface These pins must be tied high connected to HIO Vpp The RESET active low input of the S1D13706 may be connected to the PC Card RESET active high using an inverter Interfacing to the PC Card Bus 1D13706 Issue Date 01 02 23 X31B G 005 02 Page 12 Epson Research and Development Vancouver Design Center 4 PC Card to S1D13706 Interface 4 1 Hardware Connections The S1D13706 is interfaced to the PC Card bus with a minimal amount of glue logic In this implementation the address inputs AB 16 0 and data bus DB 15 0 connect directly to the CPU address A 16 0 and data bus D 15 0 The PC Card interface does not provide a bus clock so one must be supplied for the S1D13706 Since the bus clock frequency is n
164. te at are la a at SR ed ara ato a Oe ee Bere cat wa 18 Osh Doctments si sye afk ee A oP a a a A oh ee Bw Ce ht at ee te a ES 6 2 Document Sources hegi a A ee ee 18 7 Technical Support to ee oe at ee Se ee ee ae a A 19 7 1 EPSON LCD Controllers S1D13706 2 2 ee 19 7 2 Intel StrongARM SA 1110 Processor 2 ee ee 19 Interfacing to the Intel StrongARM SA 1110 Microprocessor S1D13706 Issue Date 02 06 26 X31B G 019 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Intel StrongARM SA 1110 Microprocessor X31B G 019 02 Issue Date 02 06 26 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 2 0 0 0 002 ee eee 11 Table 4 1 Summary of Power On Reset Configuration Options 14 Table 4 2 CLKI to BCLK Divide Selection o o e 14 Table 4 3 RDFx Parameter Value versus CPU Maximum Frequency 15 List of Figures Figure 2 1 SA 1110 Variable Latency IO Read Cycle ooo o 9 Figure 2 2 SA 1110 Variable Latency IO Write Cycle 2 2 2 oo o 10 Figure 4 1 Typical Implementation of SA 1110 to S1D13706 Interface 13 Interfacing to the Intel StrongARM SA 1110 Microprocessor 1D13706 Issue Date 02 06 26 X31B G 019 02 Page 6 Epson Research a
165. the TFT frame pulse parameters and are only available when the selected panel type is TFT D TFD HR TFT Refer to S1D 3706 Hardware Functional Specification document number X31B A 001 xx for a complete description of the FPFRAME pulse settings Start pos Specify the delay in lines from the start of the vertical non display period to the leading edge of the FPFRAME pulse Pulse width Specifies the pulse width in lines of the FPFRAME output signal Predefined Panels 13706CFG uses a file panels def which lists various panel manufacturers recommended settings If the file panels def is present in the same directory as 13706cfg exe the settings for a number of predefined panels are available in the drop down list If a panel is selected from the list 13706CFG loads the predefined settings contained in the file 13706CFG Configuration Program 1D13706 Issue Date 01 03 29 X31B B 001 03 Page 18 Panel Power Tab 51D13706 Configuration Utility Epson Research and Development Vancouver Design Center Power Down Time Dela Power Up Time Dela The S5U13706B00C evaluation board is designed to use the GPO signal to control the LCD bias power The following settings allow configuration of the necessary delays Power Down Time Delay Power Up Time Delay S1D13706 X31B B 001 03 This setting controls the time delay between when the LCD panel is powered off and when the S1D13706 control signals are turned off This
166. the least significant word of the return value describes the color as a 5 6 5 RGB value Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 91 Vancouver Design Center void seDrawLine long x1 long y1 long x2 long y2 DWORD Color void seDrawMainWinLine long x1 long y1 long x2 long y2 DWORD Color void seDrawSubWinLine long x1 long y1 long x2 long y2 DWORD Color Description These functions draw a line between two points in the specified color Use seDrawLine to draw a line on the current active surface See seSetMainWinAsAc tiveSurface and seSetSubWinAsActiveSurface for information about changing the active surface Use seDrawMainWinLine and seDrawSubWinLine to draw a line on the surface refer enced by the function name If no memory was allocated to the surface these functions return without writing to dis play memory Parameters xl The X co ordinate in pixels of the first endpoint of the line to be drawn yl The Y co ordinate in pixels of the first endpoint of the line to be drawn x2 The X co ordinate in pixels of the second endpoint of the line to be drawn y2 The Y co ordinate in pixels of the second endpoint of the line to be drawn Color Specifies the color to draw the line with Color is interpreted differently at different color depths At 1 2 4 and 8 bpp display colors are derived from the lookup table values The least significant byte of
167. the vertical display period start position Sets the FPLINE pulse polarity and FPLINE pulse width Sets the FPLINE pulse start position Sets the FPFRAME pulse polarity and FPFRAME pulse width Sets the FPFRAME pulse start position Notes Programming Notes and Examples Issue Date 01 02 23 S1D13706 X31B G 003 03 Page 12 Epson Research and Development Vancouver Design Center Table 2 1 Example Register Values Continued Value Value ipti N Register Hex Binary Description otes Selects the following display blank screen is blanked e dithering enabled 70h 83 1000 0011 hardware video invert disabled software video invert video data is not inverted color depth 8 bpp Selects the following display data word swap disabled 71h 00 0000 0000 display data byte swap disabled sub window enable disabled e SwivelView Mode not rotated 74h 00 0000 0000 75h 00 0000 0000 Sets the main window display start address 76h 00 0000 0000 78h 50 0101 0000 ee 79h 00 0000 0000 Sets the main window line address offset 7Ch 00 0000 0000 7Dh 00 0000 0000 Sets the sub window display start address 7Eh 00 0000 0000 80h 50 0101 0000 81h 00 0000 0000 Sets the sub window line address offset 84h 00 0000 0000 Li 85h 00 0000 0000 Sets the sub window X start position 88h 00 0000 0000 ee 89h 00 0000 0000 Sets the sub window Y start position 8Ch 4F 0100 1111 m 8
168. to interface the S1D13706 Embedded Memory LCD Controller and the Motorola MC68030 microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Motorola MC68030 Microprocessor S1D13706 Issue Date 01 02 23 X31B G 013 02 Page 8 Epson Research and Development Vancouver Design Center 2 Motorola MC68030 Bus Interface 2 1 Overview The MC68030 is a second generation enhanced microprocessor from the Motorola M68000 family of devices The MC68030 is a 32 bit microprocessor with a 32 bit address bus and a 32 bit data bus The microprocessor supports both asynchronous and synchronous bus cycles and burst data transfers The bus also supports dynamic bus sizing which automati cally determines device port size on a cycle by cycle basis 2 2 Dynamic Bus Sizing The MC68030 supports dynamic bus sizing using the following signals e SIZ1 and SIZO indicate the number of bytes remaining to be transfered for the current bus cycle Table 2 1 SIZ Signal Encoding SIZ1 SIZO Bytes Remaining 0 1 1 Byte 1 0 2 Bytes Word 1 1 3 Bytes 0 0
169. to 1 for a 16 bit bus and the WS Wait states bits should be set to 111b to allow the S1D13706 to terminate bus cycles externally with DTACK The DTACK pin function must be enabled with Register FFFFF433 Port G Select Register bit 0 If DTACK is not used then the the WS bits should be set to either 4 6 10 or 12 software wait states depending on the divide ratio between the S1D13706 MCLK and BCLK The WS bits should be set as follows Table 4 3 WS Bit Programming S1D13706 MCLK to BCLK Divide Ratio WS Bits wait states MCLK BCLK 4 MCLK BCLK 2 6 MCLK BCLK 3 10 MCLK BCLK 4 12 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor 1D13706 Issue Date 01 02 26 X31B G 016 02 Page 14 Epson Research and Development Vancouver Design Center 5 Software 1D13706 Test utilities and Windows CE display drivers are available for the S1D13706 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CEG or by directly modifying the source The Windows CE display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the Motorola MC68VZ32
170. to SD 15 0 valid read cycle 0 2 ns 15 Rising edge of MEMR to SD 15 0 high impedance read 5 33 3 12 ne cycle 1 t11 is the delay from when data is placed on the bus until the data is latched into the write buffer Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 40 6 2 3 Hitachi SH 4 Interface Timing Epson Research and Development Vancouver Design Center CKIO A 16 1 M R RD WR CSn WEn RD RDY D 15 0 write D 15 0 read Teko t t2 gt i gt 4 gt t3 t4 7 15 16 BS t7 gt t8 ll 4 t9 t10 t11 t12 tig t14 gt le gt le o Hi Z H Hi Z t15 t16 gt Hi Z Hi Z t17 t18 t gt t gt Hi Z VALID Hi Z S1D13706 X31B A 001 08 Figure 6 4 Hitachi SH 4 Interface Timing Hardware Functional Specification Issue Date 01 11 13 Issue Date 01 11 13 Epson Research and Development Page 41 Vancouver Design Center Table 6 7 Hitachi SH 4 Interface Timing Symbol Parameter nin any Max MIR sed Max Unit fckio Clock frequency 20 66 MHz Tckio Clock period W cxio 1 fckio ns t1 Clock pulse width low 22 5 6 8 ns t2 Clock pulse width high 22 5 6 8 ns t3 A 16 1 M R RD WR setup to CKIO 0 1 ns t4
171. to VCCY See Section 2 5 Level Shift and Clamp Y 3 XINH GPIOO Thinning control signal Circuit for Vertical Logic Control Signals on page 13 See Section 2 5 Level Shift and Clamp Y 4 YSCL GPIO1 Shift clock signal Circuit for Vertical Logic Control Signals on page 13 See Section 2 5 Level Shift and Clamp Y 5 FRY GPIO2 AC signal for output Circuit for Vertical Logic Control Signals on page 13 See Section 2 4 Swing Power Supply for Y 6 VCCY E Power supply for logic high the Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 bo See Section 2 4 Swing Power Supply for Y 7 V5Y r fg supply for logic low and liquid crystal line Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 Y 8 NC No Connect See Section 2 4 Swing Power Supply for Y 9 VOY E Power supply for liquid crystal drive the Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 See Section 2 1 VDDH and VDD Y 10 VDD Power supply for liquid crystal drive Horizontal and Vertical Analog Voltages on page 8 Forward scanning Active low pulse Y 11 DYIO2 No Connect Start pulse signal f Reverse scanning Open Forward scanning Open Reverse scanning Active low pulse Noles EDHON WEE EDOM E gt Startpulse signal See Section 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals on page 13 1D13706 Connecting to the Epson D TFD Panels X31B G 012 03 Issue Date 01 02 23 Epson
172. to the Sharp HR TFT Panels X31B G 01 1 04 Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2 1 HR TFT Power On Off Sequence Timing 0000 11 Table 2 2 S1D13706 to LQ039Q2DS01 Pin Mapping e e 12 Table 3 1 S1D13706 to LQ031B1DDxx Pin Mapping o e e 16 List of Figures Figure 2 1 Sharp LQ039Q2DS01 Gray Scale Voltage VO V9 Generation 8 Figure 2 2 Panel Gate Driver DC Power SupplieS o e 9 Figure 2 3 Panel Gate Driver AC Power Supplies o e 10 Figure 2 4 HR TFT Power On Off Sequence Timing 2 004 11 Figure 3 1 Sharp LQ031B1DDxx Gray Scale Voltage VO V9 Generation 14 Connecting to the Sharp HR TFT Panels S1D13706 Issue Date 01 02 23 X31B G 011 04 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Connecting to the Sharp HR TFT Panels X31B G 01 1 04 Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to connect to the Sharp HR TFT panels directly supported by the S1D13706 These panels are e Sharp LQ031B1DDXX 160 x 160 HR TFT panel e Sharp LQ039Q2DS01 320 x 240 HR TFT panel The designs described in this document are presented only
173. values prior to calling seRegisterDevice ERR_OK operation completed with no problems ERR_UNKNOWN_DEVICE The HAL was unable to locate the S1D13706 ERR_FAILED The HAL was unable to map S1D13706 display memory to the host platform In addition on Win32 platforms the following two error values may be returned ERR_PCI_DRIVER_ The HAL was unable to locate file SED13XX VXD NOT_FOUND ERR_PCI_BRIDGE_ The driver file SED13XX VXD was unable to locate the ADAPTER_NOT_FOUND PCI bridge adapter board attached to the evaluation board Note seRegisterDevice MUST be called before any other HAL functions Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 66 Epson Research and Development Vancouver Design Center int selnitReg unsigned Flags Description Parameters Return Value This function initializes the S1D13706 registers the LUT assigns default surfaces and allocates memory accordingly Flags Provides additional information about how to perform the initialization Valid values for Flags are CLEAR_MEM Zero display memory as part of the initialization DISP_BLANK Blank the display for aesthetics during initialization ERR_OK The initialization completed with no problems ERR_NOT_ENOUGH_MEMORY Insufficient display buffer ERR_CLKI_NOT_IN_TABLE Could not program CLKI in clock synthesizer because selected frequency not in table ERR_CLKI2_NOT_IN_TABLE Could not program CLKI2
174. vertical non display VNDP cycles for delays If there is no VNDP cycle this function will freeze the system To ensure VNDP cycles are being generated ensure that there is a clock available for PCLK Alternatively set the power up and power down times to 0 Parameters Enable Call with Enable set to TRUE to set power save mode Call with Enable set to FALSE to disable power save mode Return Value None BOOL seGetPowerSaveMode void Description seGetPowerSaveMode returns the current state of power save mode Parameters None Return Value The return value is TRUE if power save mode is enabled The return value is FALSE if power save mode is not enabled void seSetPowerUpDelay WORD PowerupTime Description seSetPowerUpDelay sets the power up delay for seSetPowerSaveMode Parameters PowerupTime Power up time in milliseconds Return Value None void seSetPowerDownDelay WORD PowerdownTime Description seSetPowerDownDelay sets the power down delay for seSetPowerSaveMode Parameters PowerdownTime Power down time in milliseconds Return Value None void seCheckEndian BOOL ReverseBytes Description This function returns the endian ness of the CPU the application is running on Parameters ReverseBytes A pointer to boolean value to receive the endian ness of the system On return from this function ReverseBytes is FALSE if the CPU is little endian i e Intel ReverseBytes will be TRUE if the CPU i
175. voltage changes according to the characteristics of the diodes The base voltage at Q1A also appears at the base of Q1B which along with potentiometers R1 and R2 determine the current flowing into resistor R7 The current flowing into R7 sets the output voltage VEEY Therefore any change in temperature results in a corresponding change in the output of VEEY Connecting to the Epson D TFD Panels Issue Date 01 02 23 Epson Research and Development Page 11 Vancouver Design Center 2 3 VCC Horizontal Logic Power Supply The power supply for the horizontal logic circuitry must be set at 3 3V The panel must be ready for use before this supply is turned on A general purpose output pin may be used to control VCC GPO on the S1D13706 Figure 2 4 VCC Power Supply shows an example of this power supply The control signal GPO in this implementation activates VCC when it is low Q1 NDS9400A SO GPO O VCC 3 3V C1 10uF 16V 8 16 Figure 2 4 VCC Power Supply Connecting to the Epson D TFD Panels S1D13706 Issue Date 01 02 23 X31B G 012 03 Page 12 Epson Research and Development Vancouver Design Center 2 4 Swing Power Supply for the Vertical Drive VOY and Logic VCCY V5Y Voltages The vertical drive voltage VOY and vertical logic voltages VCCY and V5Y require a swing power supply To obtain the required voltage range VEEY is used to swing the vertical system voltages through the recommended 32
176. www eea epson com Interfacing to the PC Card Bus S1D13706 Issue Date 01 02 23 X31B G 005 02 Page 16 7 Technical Support 7 1 EPSON LCD Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 PC Card Standard PCMCIA North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Personal Computer Memory Card International Association 2635 North First Street Suite 209 San Jose CA 95134 Tel 408 433 2273 Fax 408 433 9558 http www pc card com S1D13706 X31B G 005 02 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the PC Card Bus Issue Date 01 02 23 EPSON 1D13706 Embedded Memory LCD Controller
177. y void seSubWinVirtPanScroll DWORD x DWORD y void seMainAndSubWinVirtPanScroll DWORD x DWORD y Description When displaying a virtual image the physical display is smaller than the virtual image contained in display memory In order to view the entire image the display is treated as a window into the virtual image These functions allow an application to pan right and left and scroll up and down the display over the virtual image seVirtPanScroll will pan and scroll the current active surface seMainWinVirtPanScroll and seSubWinVirtPanScroll will pan and scroll the surface indicated in the function name seMainAndSubWinVirtPanScroll will pan and scroll the surface which is used by both the main and sub windows Note Panning operations are limited to 32 bit boundaries x must be a multiple of 32 bits per pixel Parameters x The new x offset in pixels of the upper left corner of the display x must be a multiple of 32 bits per pixel y The new y offset in pixels of the upper left corner of the display Return Value None S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 89 Vancouver Design Center 10 2 8 Drawing Functions in this category perform primitive drawing on the specified display surface Supported drawing primitive include pixels lines rectangles ellipses and circles All drawing functions are in relation to the given Swivel
178. 0 D 15 0 D 15 0 D 15 0 CSH External Decode CSn External Decode CSn CSX M R External Decode CLKI BUSCLK BUSCLK CKIO CLK CLK CLK CLKO BS Connected to Vpp BS AS AS Connected to Vpp RD WR Rpig Connectedto po wry R W R W R W Connected Vop VDD RD RDO RD RD eae lo SIZA OE OE DD WEO WEO WE WEO E to SIZO EBT WE DD WE1 WE1 BHE WE1 UDS DS EBO UWE WAIT Hi 7 WAIT WAIT WAIT RDY DTACK DSACK1 N A DTACK RESET RESET RESET RESET RESET RESET RESET OUT RESET Note 1 A0 for these busses is not used internally by the 1D13706 and should be connected to Vss 2 If the target MC68K bus is 32 bit then these signals should be connected to D 31 16 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Vancouver Design Center 4 7 LCD Interface Pin Mapping Table 4 10 LCD Interface Pin Mapping Page 31 al Passive Color Passive Panel Color TFT Panel Pin Name Single Single Others Sharp Hn Fpson 4 bit Format 1 Format 2 16 Bit TFT D TFD 4 bit 8 bit 8 bit 8 bit 9 bit 12 bit 18 bit 18 bit 18 bit FPFRAME FPFRAME SPS DY FPLINE FPLINE LP LP FPSHIFT FPSHIFT DCLK XSCL DRDY MOD FPSHIFT2 MOD DRDY GCP FPDATO DO DO B5 Do G3 Do R6 R2 R3 R5 R5 R5 FPD
179. 0 254mm 0 010 in diameter and are fanned out with 0 005 traces with 0 005 spaces at the passage between pads All the Vss pins are inner pins and require connection with the microvia specific layer On this layer all the Vss pads are connected together and are fanned out with multiple traces All the traces on the microvia specific layer must be terminated to a standard through hole via for connection to the rest of the board i e bottom layer power and ground planes The following diagram shows an example for inner pad routing Figure 3 2 Example Inner Pad Routing S1D13706 Integrating the CFLGA 104 pin Chip Scale Package X31B G 018 02 Issue Date 01 02 26 Epson Research and Development Page 9 Vancouver Design Center 4 References 4 1 Documents Epson Research and Development Inc 1D13706 Hardware Functional Specification Document Number X31B A 001 xx 4 2 Document Sources e Epson Electronics America website http www eea epson com e Epson Research and Development website http www erd epson com Integrating the CFLGA 104 pin Chip Scale Package 1D13706 Issue Date 01 02 26 X31B G 018 02 Page 10 Epson Research and Development Vancouver Design Center 5 Technical Support 5 1 EPSON LCD Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp
180. 00 68 00 00 70 A8 50 70 50 E8 40 20 20 29 FO 40 00 69 10 00 70 A9 50 70 50 E9 40 30 20 2A FO 70 00 6A 30 00 70 AA 50 70 60 EA 40 30 20 2B FO BO 00 6B 50 00 70 AB 50 70 60 EB 40 30 20 2C FO FO 00 6C 70 00 70 AC 50 70 70 EC 40 40 20 2D BO FO 00 6D 70 00 50 AD 50 60 70 ED 30 40 20 2E 70 FO 00 6E 70 00 30 AE 50 60 70 EE 30 40 20 2F 40 FO 00 6F 70 00 10 AF 50 50 70 EF 30 40 20 30 00 FO 00 70 70 00 00 BO 00 00 40 FO 20 40 20 31 00 FO 40 71 70 10 00 B1 10 00 40 F1 20 40 30 32 00 FO 70 72 70 30 00 B2 20 00 40 F2 20 40 30 33 00 FO BO 73 70 50 00 B3 30 00 40 F3 20 40 30 34 00 FO FO 74 70 70 00 B4 40 00 40 F4 20 40 40 35 00 BO FO 75 50 70 00 B5 40 00 30 F5 20 30 40 36 00 70 FO 76 30 70 00 B6 40 00 20 F6 20 30 40 37 00 40 FO 77 10 70 00 B7 40 00 10 F7 20 30 40 38 70 70 FO 78 00 70 00 B8 40 00 00 F8 00 00 00 39 90 70 FO 79 00 70 10 B9 40 10 00 F9 00 00 00 3A BO 70 FO 7A 00 70 30 BA 40 20 00 FA 00 00 00 3B DO 70 FO 7B 00 70 50 BB 40 30 00 FB 00 00 00 3C FO 70 FO 7C 00 70 70 BC 40 40 00 FC 00 00 00 3D FO 70 DO 7D 00 50 70 BD 30 40 00 FD 00 00 00 3E FO 70 BO 7E 00 30 70 BE 20 40 00 FE 00 00 00 3F FO 70 90 7F 00 10 70 BF 10 40 00 FF 00 00 00 16 bpp color Programming Notes and Examples Issue Date 01 02 23 The Look Up Table is bypassed at this color depth therefore programming the LUT is not required S1D13706 X31B G 003 03 Page 26 Epson Research and Development Vancouver Design Center 5 Power Save Mode The S1D13706 is designed for very low pow
181. 022 eee CPU Interface Pin Mapping o o e CPU Bus Connector H3 Pinout CPU Bus Connector H4 Pinout LCD Signal Connector H1 2 2200 4 Extended LCD Signal Connector H2 Controlling the MAX754 saaa o o o 0000 Controlling the MAX749 oo o ee ee Parts ista 4 ick hon Sts ak wedges oli Ste ee A List of Figures Configuration DIP Switch SW1 Location Configuration Jumper JP1 Location o oo Configuration Jumper JP2 Location o Configuration Jumper JP3 Location oo Configuration Jumper JP4 Location o o Configuration Jumper JP5 Location o o o Configuration Jumper JP6 Location o o o Configuration Jumper JP7 Location o oo Symbolic Clock Synthesizer Connections S1D13706B00C Schematics 1 of 6 S1D13706B00C Schematics 2 of 6 S1D13706B00C Schematics 3 of 6 S1D13706B00C Schematics 40f6 S1D13706B00C Schematics 50f 6 S1D13706B00C Schematics 60f6 S1U13706B00C Board Layout o o S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 Page 5 S1D13706 X31B G 004 04 Page 6 Epson Research and Development Vancouver Design Center T
182. 06 Interface ee 12 4 1 Hardware Connections 2 a 1 4 2 S1D13706 Hardware Configuration 2 2 2 13 4 3 Register Memory Mapping 2 13 5 SoftWare na e eir A ea Be oe aS o ee hee es 14 ROTerences ia a A eg Eee Aa la d 15 GL DOCUMENTS Uso a a at A a O 6 2 Document Sources 2 ee ee ee ee 1 Technical S pport lt s a eg A Sk ale a id eA 16 7 1 EPSON LCD Controllers S1D13706 2 2 2 2 2 2 2 42 2 2 16 7 2 PC Card Standard 2 a 16 Interfacing to the PC Card Bus S1D13706 Issue Date 01 02 23 X31B G 005 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the PC Card Bus X31B G 005 02 Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 2 0 0 0022 eee eee 10 Table 4 2 CLKI to BCLK Divide Selection o o e 13 Table 4 1 Summary of Power On Reset Configuration Options 13 List of Figures Figure 2 1s PC Gard Read Cycl ns sus deni Bag eee es A A Ee 9 Figure 2 2 PC Card Write Cycle 2 ee 9 Figure 4 1 Typical Implementation of PC Card to S1D13706 Interface 12 Interfacing to the PC Card Bus 1D13706 Issue Date 01 02 23 X31B G 005 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE
183. 06CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at http www eea epson com S1D13706 Interfacing to the NEC VR4181A Microprocessor 1D13706 Issue Date 01 02 23 X31B G 008 02 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e NEC Electronics Inc NEC VR4181A Target Specification Revision 0 5 9 11 98 e Epson Research and Development Inc S1D 3706 Hardware Functional Specification document number X31B A 001 xx e Epson Research and Development Inc SSUI3706BO0C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples document number X31B G 003 xx 6 2 Document Sources e NEC Electronics Inc website http www necel com e Epson Electronics America website http www eea epson com S1D13706 Interfacing to the NEC VR4181A Microprocessor X31B G 008 02 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 Epson LCD Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501
184. 0h SuB WinDow Y END POSITION REGISTER 0 RW Sub Window Y End Position Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 91h SuB WinDow Y END POSITION REGISTER 1 n a n a n a n a n a n a Sub Wind Bit 9 RW low Y End Position Bit 8 CV Pulse Burst Length X31B R 001 02 9 REG B1h PWM Clock CV Pulse Configuration Register PWM Clock Divide Select Bits 3 0 PWM Clock Divide Amount REG B3h PWMOUT Dury CyCLe REGISTER 1 RW PWMOUT Duty Cycle Bit7 Bite Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 1 REG 00h These bits are used to identify the S1D13706 For the S1D13706 the product code should be 10 2 REG 04h Memory Clock Configuration Register MCLK Divide Select Bits BCLK to MCLK Frequency Ratio 00 EI 01 2 1 3 REG 05h Pixel Clock Configuration Register PCLK Divide Select Bits PCLK Source to PCLK Frequency Ratio N REGISTER REG AOh Power SAVE CONFIGURATIO Memory RW 011 4 1 1XX 8 1 VNDP p f i Controller y Power Sava 4 REG 05h Pixel Clock Configuration Register Status RO wa ma ma Power Save ma ma acia Status RO Enable PCLK Source Select Bits PCLK Source 00 MCLK REG A1h RESERVED RW 01 e 10 n a n a n a n a n a n a n a Reserved 1 CURIE REG A2h SOFTWARE RESET REGISTER
185. 1 0 PIP Window Display Start Address Register 2 REG 7Eh Read Write PIP Window Display Start me Address Bit 16 7 6 5 4 3 2 1 0 bits 16 0 PIP Window Display Start Address Bits 16 0 These bits form the 17 bit address for the starting double word of the PIP window Note that this is a double word 32 bit address An entry of 00000h into these registers represents the first double word of display memory an entry of 00001h represents the sec ond double word of the display memory and so on Note These bits have no effect unless the PIP Window Enable bit is set to 1 REG 71h bit 4 PIP Window Line Address Offset Register 0 REG 80h Read Write PIP Window Line Address Offset Bits 7 0 7 6 5 4 3 2 1 0 PIP Window Line Address Offset Register 1 REG 81h Read Write PIP Window Line Address Offset Bits 9 8 7 6 5 4 3 2 1 0 bits 9 0 PIP Window Line Address Offset Bits 9 0 These bits are the LCD display s 10 bit address offset from the starting double word of line n to the starting double word of line n 1 for the PIP window Note that this is a 32 bit address increment n a Note These bits have no effect unless the PIP Window Enable bit is set to 1 REG 71h bit 4 Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 116 Epson Research and Development Vancouver Design Center
186. 1 0 Evaluation Board User Manual 1D13706 Issue Date 01 02 23 X31B G 004 04 Page 10 Epson Research and Development Vancouver Design Center The S1D13706 has 8 configuration inputs CONF 7 0 which are read on the rising edge of RESET All S1D13706 configuration inputs are fully configurable using a ten position DIP switch as described below Table 3 1 Configuration DIP Switch Settings Switch S1D13706 Value on this pin at rising edge of RESET is used to configure Signal Closed On 1 Open Off 0 Select host bus interface as follows CNF2 CNF1 CNFO Host Bus Interface 0 0 0 SH 4 SH 3 0 0 1 MC68K 1 0 1 0 MC68K 2 SW1 3 1 CNF 2 0 1 0 0 Generic 2 1 0 1 RedCap 2 1 0 DragonBall 1 1 1 Reserved Note The host bus interface is 16 bit SW1 4 CNF3 Enable GPIO pins Enable additional pins for D TFD HR TFT SW1 5 CNF4 Big Endian bus interface SW1 6 CNF5 WAIT is active high CLKI to BCIk divide select CNF7 CNF6 CLKI to BCIk Divide Ratio SW1 8 7 CNF 7 6 0 1 oe 1 0 3 1 1 1 4 1 SW1 9 Hardware Video Invert invert video data Hardware Video Invert normal video data SW1 10 Disable FPGA for non PCI host Enable FPGA for PCI host Required settings when used with PCI Bridge FPGA S1D13706 X31B G 004 04 Note 1 To enable the Hardware Video Invert function the following are required e GPIO pins must be enabled S1 4 closed e GPIOO must be connected to S1 9 Jumper JP1 set to 1
187. 11 320x240 Sharp Direct HR TFT Panel Timing e g LQ039Q2DS01 80 6 4 12 160x240 Epson D TFD Panel Timing e g LF26SCR 0 82 6 4 13 320x240 Epson D TFD Panel Timing e g LFITSQR o o 86 E COCKS d E hak 3 ale Seas Ae A A ESAS A 90 7 1 Clock Descriptions O Hallo BEEK aia ias a A a a oO gine de ia 90 TZ MEL ete ae a et a ate cele a le e E ile ae tae 90 LES PCE Ke aerator Atk ah rd Bia ee taeda iy dd Gee Rah IR Seg 91 TAA PWMCEK r i e Sd o da a Se ee ee Pee ee hae eed 92 12 Clock Selection eta tes a GS BOR A AE A ae UD ge te ae OS 7 3 Clocks versus Functions as osons irate ane am ee eee 94 O REGISTERS oon ce oe on sais net Soy dl Be Se ce a a Ge na 95 8 1 Resister Mapping ssa aast Se io Bean cen FA aio Gb BO lp aie ee de ae Gee eects oad oe WS 8 2 Register Set ms bo ceca ta Re eh ee BB eee A nt ae bd ee da AS ta O 8 3 Register Descriptions sr e acs a A a ea A ey 298 8 3 1 Read Only Configuration Registers 2 0 0 2 2 o e e 96 8 3 2 Clock Configuration Registers 2 0 2 0 000000 0002 ee eee 97 8 3 3 Look Up Table Registers o e e 99 8 3 4 Panel Configuration Registers o e ee ee 101 8 3 5 Display Mode Registers e 109 S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Vancouver Design Center 10 11 12 13 14 15 16 1
188. 110 Overview The SA 1110 system bus can access both variable latency IO and memory devices The SA 1110 uses a 26 bit address bus and a 32 bit data bus which can be used to access 16 bit devices A chip select module with six chip select signals each accessing 64M bytes of memory allows selection of external devices Only chip selects 3 through 5 nCS 5 3 may be used to select variable latency devices which use RDY to extend access cycles These chip selects are individually programmed in the SA 1110 memory configuration registers and can be configured for either a 16 or 32 bit data bus Byte steering is implemented using the four signals nCAS 3 0 Each signal selects a byte on the 32 bit data bus For example nCASO selects bits D 7 0 and nCAS3 selects bits D 31 24 For a 16 bit data bus only nCAS 1 0 are used with nCASO selecting the low byte and nCAS1 selecting the high byte The SA 1110 can be configured to support little or big endian mode 2 1 2 Variable Latency lO Access Overview A data transfer is initiated when a memory address is placed on the SA 1110 system bus and a chip select signal nCS 5 3 is driven low If all byte enable signals nCAS 3 0 are driven low then a 32 bit transfer takes place If only nCAS 1 0 are driven low then a word transfer takes place through a 16 bit bus interface If only one byte enable is driven low then a byte transfer takes place on the respective data lines During a read cycle the outpu
189. 13 1722 30 70 DB5 2813 1470 80 189 CNF5 2813 1470 31 72 DB4 2813 1302 81 191 CNF4 2813 1302 32 74 DB3 2813 1134 82 193 CNF3 2813 1134 33 77 DB2 2813 882 83 196 CNF2 2813 882 34 79 DBI 2813 714 84 198 CNF1 2813 714 35 81 DBO 2813 546 85 200 CNFO 2813 546 36 84 VSS 2813 294 86 203 TESTEN 2813 294 37 86 HVDD 2813 126 87 205 AB16 2813 126 38 89 PWMOUT 2813 126 88 208 AB15 2813 126 39 91 GPIO6 2813 294 89 210 AB14 2813 294 40 93 GPIO5 2813 462 90 212 ABT3 2813 462 41 96 GPIO4 2813 714 91 215 ABT12 2813 714 42 98 GPIO3 2813 882 92 217 AB11 2813 882 43 100 GPIO2 2813 1050 93 219 AB10 2813 1050 44 103 GPIO1 2813 1302 94 222 AB9 2813 1302 45 105 GPIOO 2813 1470 95 224 AB8 2813 1470 46 108 CVOUT 2813 1722 96 227 AB7 2813 1722 47 110 GPO 2813 1890 97 229 AB6 2813 1890 48 112 DRDY 2813 2058 98 231 AB5 2813 2058 49 115 HVDD 2813 2310 99 234 AB4 2813 2310 50 117 VSS 2813 2478 100 236 VSS 2813 2478 Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 22 Epson Research and Development Vancouver Design Center 4 4 Pin Descriptions Key Input Output Bi Directional Input Output Power pin LVTTL Schmitt input LVTTL input LVTTL IO buffer 6mA 6mA 3 3V Low noise LVTTL IO buffer 12mA 12mMA 3 3V Low noise LVTTL Output buffer 12mA 12mA03 3V Low noise LVTTL IO buffer with input mask 12mA 12mMA 3 3V Test mode contro
190. 13706 Embedded Memory LCD Controller Interfacing to the Motorola MCF5307 ColdFire Microprocessor Document Number X31B G 010 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X31B G 010 02 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 INt FOdUCTION s sa sey sid oe as AR we SE A A A 7 2 Interfacing to the MCF5307 2 2 8 2 1 The MCF5307 System Bus 2 e 2 ee ee ee 8 Dal SOVERVICW oil dl Buel eh aa cate eo hate ee ans Bee amp Gos 8 2 1 2 Normal Non Burst Bus Transactions e ee 8 21 37 BurstE yc eva to a A eit EAs add DAS ts deena a 9 2 2 Chip Select Mod
191. 13706 are connected to ADJ and CTRL of MAX749 The output voltage VLCD can be adjusted from 8V to 24V in 64 steps by sending pulses to CVOUT Each CVOUT pulse increments VLCD one step towards 24V When decremented beyond 24V VLCD resets to 8V again In other words 63 pulses equal incrementing 1 step After the MAX749 is reset see Controlling the MAX749 on page 21 VLCD is set at 16V The S5U13706B00C uses GPO and CVOUT to control the MAX749 as shown in the following table Table 6 2 Controlling the MAX749 Signal Turn MAX749 On Turn MAX749 Off Reset MAX749 GPO high low low CVOUT X low high X don t care When jumper JP7 is set to position 2 3 VLCD can be adjusted by R41 500K potenti ometer to provide an output voltage from 16V to 23V Note When using manual adjust set the potentiometer according to the panel s specific power requirements before connecting the panel 1D13706 X31B G 004 04 S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 Page 22 Epson Research and Development Vancouver Design Center 6 6 Software Adjustable LCD Backlight Intensity Support Using PWM The S1D13706 provides Pulse Width Modulation output on PWMOUT PWMOUT can be used to control LCD panels which support PWM control of the backlight inverter The PWMOUT signal is provided on the buffered LCD connector H1 6 7 Passive Active LCD Panel Support The S1D13706 directly suppo
192. 13706CFG expects the Open will fail and an error message is displayed This may happen if the version of 13706CFG is substantially older or newer than the file being opened S1D13706 13706CFG Configuration Program X31B B 001 03 Issue Date 01 03 29 Epson Research and Development Page 21 Vancouver Design Center Save From the Menu Bar select File then Save to initiate the save action The Save menu option allows a fast save of the configuration information to a file that was opened with the Open menu option Note This option is only available once a file has been opened Note 13706cfg exe can be configured by making a copy of the file 13706cfg exe and config uring the copy It is not possible to configure the original while it is running Save As From the Menu Bar select File then Save As to display the Save As Dialog Box Save As AES Save in Y 51013706 z e gal ex 13706bmp exe 13706cfg exe 13706play exe 413706show exe a PANELS DEF File name 13706BMP EXE Save as type y Cancel Z Save as is very similar to Save except a dialog box is displayed allowing the user to name the file before saving Using this technique a tester can configure a number of files differing only in configuration information and name e g BMP60Hz EXE BMP72Hz EXE BMP75Hz EXE where only the frame rate changes in each of these files Note When Save As is selected then an exact duplicate of th
193. 2 e GPIO Pin Input Enable REG A9h bit 7 must be set to 1 e GPIOO Pin IO Configuration REG A8h bit 0 must be set to 0 e Hardware Video Invert Enable bit REG 70h bit 5 must be set to 1 S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 3 2 Configuration Jumpers Page 11 The S5U13706B00C has seven jumper blocks which configure various setting on the board The jumper positions for each function are shown below Table 3 2 Jumper Summary Function Position 1 2 Jumper JP1 GPIOO Connection JP2 CLKI2 Source JP3 CLKI Source JP4 GPO Polarity on H1 JP5 Contrast adjust for ve LCD bias VDDH Software controlled JP6 LCD Panel Voltage JP7 Contrast adjust for ve LCD bias VLCD Software controlled Position 2 3 No Jumper GPIOO disconnected from SW1 9 for direct HR TFT D TFD or GPIO testing External oscillator U5 External oscillator U6 Inverted Active Low 3 3V LCDVCC recommended settings JP1 GPIOO Connection JP1 selects whether GPIOO is connected to SW1 9 SW1 9 is used to enable hardware video invert on the S1D13706 When the jumper is on position 1 2 SW1 9 controls the hardware video invert feature default setting When the jumper is off the hardware video invert feature is disabled This setting must be used for HR TFT an
194. 2 23 X31B G 010 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MCF5307 2 1 The MCF5307 System Bus 2 1 1 Overview The MCF5200 5300 family of processors feature a high speed synchronous system bus typical of modern microprocessors This section is an overview of the operation of the CPU bus in order to establish interface requirements The MCF5307 microprocessor family uses a synchronous address and data bus very similar in architecture to the MC68040 and MPC8xx All outputs and inputs are timed with respect to a square wave reference clock called BCLKO Master Clock This clock runs at a software selectable divisor rate from the machine cycle speed of the CPU core typically 20 to 33 MHz Both the address and the data bus are 32 bits in width All IO accesses are memory mapped there is no separate IO space in the Coldfire architecture The bus can support two types of cycles normal and burst Burst memory cycles are used to fill on chip cache memories and for certain on chip DMA operations Normal cycles are used for all other data transfers 2 1 2 Normal Non Burst Bus Transactions 1D13706 X31B G 010 02 A data transfer is initiated by the bus master by placing the memory address on address lines A31 through AO and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e SIZ 1 0 Transfer Size indicates whethe
195. 2 B4 Vss P12 A5 P12 B5 P12 A6 P12 B6 P12 A7 Note The bit numbering of the Motorola MPC821 bus signals is reversed from the normal convention e g the most significant address bit is AO the next is Al A2 etc Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 23 S1D13706 X31B G 009 02 Page 18 4 3 S1D13706 Hardware Configuration Epson Research and Development Vancouver Design Center The S1D13706 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13706 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a S1D13706 to Motorola MPC821 microprocessor Table 4 2 Summary of Power On Reset Configuration Options 1D13706 Pin Name CNF 2 0 CNF3 value on this pin at the rising edge of RESET is used to configure 1 0 1 CNF4 CNF5 CNF 7 6 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs 0 Little Endian bus interface Active low WAIT see Table 4 3 CLKI to BCLK Divide Selection for recommended settings configuration for MPC821 microprocessor Table 4 3 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 recommended setting for MPC821 mi
196. 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13706 X31B G 014 02 Page 20 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 02 Issue Date 01 02 23 EPSON 1D13706 Embedded Memory LCD Controller Interfacing to 8 bit Processors Document Number X31B G 015 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to 8 bit Processors X31B G 015 02 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center Table of Contents VA introducti
197. 3706 Source code modification is required to provide a smaller driver for mass production The current revision of the driver is designed for use with either QNX RTP or QNX4 from the latest product CD Dec 99 The Photon v2 0 display driver is designed around a common configuration include file called S1D13706 h which is generated by the configuration utility 13706CFG This design allows for easy customization of display type clocks decode addresses rotation etc by OEMs For further information on 13706CFG see the 13706CFG Configuration Program User Manual document number X31B B 001 xx Note The QNX display drivers are provided as reference source code only They are intend ed to provide a basis for OEMs to develop their own drivers for QNX Photon v2 0 This document and the source code for the QNX display drivers are updated as appropriate Please check the Epson Electronics America website at http www eea epson com or the Epson Research and Development website at http www erd epson com for the latest revisions before beginning any development We appreciate your comments on our documentation Please contact us via e mail at documentation erd epson com QNX Photon v2 0 Display Driver 1D13706 Issue Date 01 09 10 X31B E 005 02 Page 4 Epson Research and Development Vancouver Design Center Building the Photon v2 0 Display Driver 1D13706 X31B E 005 02 The following steps build the Photon v2 0 display d
198. 4 Bytes Double Word e DSACK1 and DSACKO the data transfer size acknowledge signals indicate the size of the external port and acknowledge the end of the cycle Table 2 2 DSACK Decoding DSACK1 DSACKO Result Insert Wait States in the Current Bus Cycle Complete Cycle Data Bus Port Size is 8 bits Complete Cycle Data Bus Port Size is 16 bits olo _ Oo j o Complete Cycle Data Bus Port Size is 32 bits e AO and Al determine which portion of the data bus the data is transferred on and whether the address is misaligned 2 3 Asynchronous Synchronous Bus Operation The MC68030 bus can operate asynchronously or synchronously Asynchronous operation requires DSACKO DSACKI AS and DS to control transfers The DSACK signals specify the port width and insert wait states in the current bus cycle AS the address strobe 1D13706 Interfacing to the Motorola MC68030 Microprocessor X31B G 013 02 Issue Date 01 02 23 Epson Research and Development Page 9 Vancouver Design Center signals the start of a bus cycle by indicating a valid address has been placed on the bus DS the data strobe is used as a condition for valid data on the data bus SIZ selects the active portions of the data bus R W indicates a read or write operation Synchronous bus cycles operate much like asynchronous cycles except only 32 bit port sizes are allowed In this mode the DSACK signals are no
199. 4 Issue Date 01 02 23 EPSON 1D13706 Embedded Memory LCD Controller Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Document Number X31B G 002 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 02 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introductions a e ec eee ee ee als ee ee we a a we ke a 7 2 Interfacing to the TMPR3905 12 2 1 ee ee 8 2 1 The Toshiba TMPR3905 12 System Bus 2 2 ee ee ee ee 8 Dal SONCRVICW ecc a a eek ae no ead Ba amp oe 8 2 1 2 Card Access Cycles 5 2 at it ee Bk Be ee eh dk ee aes 8 3 S1D13706 Host Bus Interfa
200. 4 PS GPIOO Power save signal 35 LP FPLINE Data latch signal of source driver 36 DCLK FPSHIFT Data sampling clock signal 37 LBR Selection for horizontal scanning direction Connect to VSHD left right scanning 38 SPR Sampling start signal for right left scanning Right to left scanning not supported See Section 3 1 External Power 39 VSHA Analog power supply Supplies on page 14 40 VO Standard gray scale voltage black e cad SA Extemal Power Supplies on page 14 41 vi Standard gray scale voltage sd Section Seles ra Supplies on page 14 42 V2 Standard gray scale voltage H Seelion e Supplies on page 14 43 V3 s Standard gray scale voltage Aa Poean Sele Mare Supplies on page 14 44 V4 3 Standard gray scale voltage See relia Se Ra ONE Supplies on page 14 45 V5 Standard gray scale voltage opa Section le ARIEL ROWS Supplies on page 14 46 V6 Standard gray scale voltage ore Sc A K OMARONG Supplies on page 14 47 V7 Standard gray scale voltage oe cuen SO Supplies on page 14 48 V8 Standard gray scale voltage ore Section e lA Supplies on page 14 49 v9 Standard gray scale voltage white see pectin She omerowe Supplies on page 14 50 AGND Vss Analog ground Ground pin of S1D13706 Connecting to the Sharp HR TFT Panels Issue Date 01 02 23 S1D13706 X31B G 011 04 Page 18 Epson Research and Development Vancouver Design Center 4 Test Software Test utilities an
201. 4h REG 85h REG 8Ch REG 8Dh and Sub Window Y Position registers REG 88h REG 89h REG 90h REG 9 1h The sub window has its own Display Start Address register REG 7Ch REG 7Dh REG 7Eh and Memory Address Offset register REG 80h REG 8 1h The sub window shares the same color depth and Swivel View orientation as the main window Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 38 Epson Research and Development Vancouver Design Center REG 74h Main Window Display Start Address Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 75h Main Window Display Start Address Register 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 76h Main Window Display Start Address Register 2 n a n a n a n a n a n a n a Bit 16 1D13706 X31B G 003 03 These registers represent a dword address which points to the start of the main window image in the display buffer An address of 0 is the start of the display buffer For the following SwivelView mode descriptions the desired byte address is the starting display address for the main window image and panel width and panel height refer to the physical panel dimensions Note Truncate all fractional values before writing to the address registers In SwivelView 0 program the start address desired byte address 4 In SwivelView 90 program the
202. 5 9 ns t2 Clock pulse width low 22 5 9 ns 3 A 16 1 M R setup to first CLK rising edge where CS 0 4 A is AS 0 UDS 0 and LDS 0 t4 A 16 1 M R hold from AS rising edge 0 ns t5 CS setup to CLK rising edge while CS AS UDS LDS 0 1 ns t6 CS hold from AS rising edge 0 ns t a AS asserted for MCLK BCLK 8 8 Telk t7b ASH asserted for MCLK BCLK 2 11 11 ToLk t7c AS asserted for MCLK BCLK 3 13 13 Telk t7d AS asserted for MCLK BCLK 4 18 18 Tok t8 AS setup to CLK rising edge while CS AS UDS LDS 0 1 1 ns t9 AS setup to CLK rising edge 1 2 ns 10 UDS LDS setup to CLK rising edge while CS ASH 3 4 n UDS LDS 0 t11 UDS LDS high setup to CLK rising edge 3 2 ns t12 First CLK rising edge where AS 1 to DTACK high impedance 5 40 3 14 ns 113 R W setup to CLK rising edge before all CS AS UDS and or 0 4 AS LDS 0 t14 R W hold from AS rising edge 0 0 ns t15 AS 0 and CS 0 to DTACK driven high 4 23 3 13 ns t16 AS rising edge to DTACK rising edge 6 39 4 16 ns 117 DI 5 0 valid to third CLK rising edge where CS 0 ASH 0 and 4 0 ee either UDS 0 or LDS 0 write cycle see note 1 t18 D 15 0 hold from DTACK falling edge write cycle 0 0 ns t19 UDS 0 and or LDS 0 to D 15 0 driven read cycle 4 27 3 13 ns t20 DTACK falling edge to D 15 0 valid read cycle 0 2 ns 121 UDS LDS rising edge to D 15 0 high impedance read cycle 5 33 3 13 ns 1 t17 is the delay fro
203. 6 d Drag the icon Build Minshell for x86 onto the desktop using the right mouse button e Choose Copy Here Windows CE 2 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 7 Vancouver Design Center f Rename the icon Build Minshell for x86 to Build Epson for x86 by right clicking on the icon and choosing rename g Right click on the icon Build Epson for x86 and click on Properties to bring up the Build Epson for x86 Properties window h Click on Shortcut and replace the string Minshell under the entry Target with Epson i Click on OK to finish 5 Create an EPSON project a Make an Epson directory under x wince public b Copy MAXALL and its sub directories x wince public maxall to the Epson di rectory xcopy s e x wince public maxall wince public epson c Rename x wince public epson maxall bat to epson bat d Edit EPSON BAT to add the following lines to the end of the file echo on set CEPC_DDI_S1D13706 1 echo off 6 Make an S1D13706 directory under x wince platform cepc drivers display and copy the S1D13706 driver source code into x wince platform cepc drivers dis play S1D13706 7 Edit the file x wince platform cepc drivers display dirs and add S1D13706 into the list of directories 8 Edit the file x wince platform cepc files platform bib and make the following two changes a Ins
204. 7 18 8 3 6 Picture in Picture Plus PIP Registers 0 4 8 3 7 Miscellaneous Registers 2 2 0 0 a 8 3 8 General IO Pins Registers o o e e o 8 3 9 Pulse Width Modulation PWM Clock and Contrast Voltage CV Pulse Configuration Registers ooa ee ee Frame Rate Calculation ee Display Data Formats 2 4m ac a be eee ae ere APS Ge Look Up Table Architecture 2 2 eee ee 11 1 Monochrome Modes 11 2 Color Modes SwivelView ou nien aa iad er a a ee a ee a a a 12 1 Concept 12 2 90 SwivelView 12 2 1 Register Programming 12 3 180 SwivelView 12 3 1 Register Programming 12 4 270 SwivelView 12 4 1 Register Programming Picture in Picture Plus PIP 0 lt lt ee es 13 1 Concept 13 2 With SwivelView Enabled 13 21 Swivel View 90 tia Secs te bi ts oy Gk 13 2 2 SwivelView 180 o 132233 S WiVel VIE W 2 10 s a ce ri o a Se a a Big Endian Bus Interface o 14 1 Byte Swapping Bus Data 14 1 1 16 Bpp Color Depths s s na no ct are tee ose Wm ae AR a 14 1 2 1 2 4 8 Bpp Color Depth o o Power Save Mode ico e O GE dE AAA Mechanical Data lt 020000 ii ci a Ee es References uti a a A Ge a ee a ws GE ee ES Sales and Technical Support 2 2 2 2 ee eee ee ee es Hardware Functional Spe
205. 8 Dragonball Microprocessor X31B G 016 02 Issue Date 01 02 26 Epson Research and Development Page 15 Vancouver Design Center 6 References 6 1 Documents Motorola Inc MC68VZ328 DragonBall VZ Integrated Processor User s Manual Motorola Publication no MC683VZ28UM available on the Internet at http www mot com SPS WIRELESS products MC68VZ328 html Epson Research and Development Inc D13706 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual Document Number X31B G 004 xx Epson Research and Development Inc Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources e Motorola Inc Literature Distribution Center 800 441 2447 e Motorola Inc Website http www mot com e Epson Electronics America website http www eea epson com Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor 1D13706 Issue Date 01 02 26 X31B G 016 02 Page 16 7 Technical Support 7 1 EPSON LCD CRT Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks P
206. A 16 1 M R RD WR hold from CSn 0 0 ns t5 BS setup 3 1 ns t6 BS hold 7 2 ns t7 CSn setup 0 1 ns t8 CSn high setup to CKIO 0 2 ns t9a RD or WEn asserted for MCLK BCLK max MCLK 50MHz 8 5 8 5 Texto t96 RD or WEn asserted for MCLK BCLK 2 11 5 11 5 Toxo t9c RD or WEn asserted for MCLK BCLK 3 13 5 13 5 Tekio t9d RD or WEn asserted for MCLK BCLK 4 18 5 18 5 Teko t10 Falling edge RD to D 15 0 driven read cycle 5 24 3 12 ns t11 Falling edge CSn to RDY driven high 3 19 3 12 ns t12 CKIO to RDY low 5 42 4 18 ns t13 CSn high to RDY high 5 35 4 14 ns t14 Falling edge CKIO to RDY high impedance 5 38 4 14 ns t15 D 15 0 setup to 2 CKIO after BS write cycle see note 1 1 0 ns t16 D 15 0 hold write cycle 0 0 ns t17 RDY falling edge to D 15 0 valid read cycle 0 ns t18 Rising edge RD to D 15 0 high impedance read cycle 5 31 3 12 ns 1 t15 is the delay from when data is placed on the bus until the data is latched into the write buffer Note Minimum one software WAIT state is required Hardware Functional Specification S1D13706 X31B A 001 08 Page 42 6 2 4 Hitachi SH 3 Interface Timing Epson Research and Development Vancouver Design Center CKIO A 16 1 M R RD WR BS CSn WEn RD WAIT D 15 0 write D 15 0 read Teko t t2 gt pit gt t3 pas 283 A Sy t7 18 1 9 gt
207. A 30 pin connector is used for the horizontal drivers and a 12 pin connector for the vertical drivers Both D TFD panels use the same horizontal 30 pin connector but their vertical driver connectors are different The 320x240 LF37SQT connector pins are swapped compared to the 160x240 LF26SCT panel connector The following tables provide pin mapping for the various connectors Connecting to the Epson D TFD Panels Issue Date 01 02 23 Epson Research and Development Vancouver Design Center Page 15 3 1 LCD Pin Mapping for Horizontal Connector LF37SQT and LF26SCT Table 3 1 LCD Pin Mapping for Horizontal Connector Pins for Horizontal Driver LCD Pin LCD Pin S1 D13706 Description Remarks No Name Pin Name X 1 ElO2 No Connect I O enable signal a F oe X 2 VCC NIOVDD Power supply for logic High a ata roge See Section 2 1 VDDH and VDD X 3 VDDH E Power supply for liquid crystal drive Horizontal and Vertical Analog Voltages on page 8 X 4 D25 FPDAT6 Blue digital data signal MSB X 5 D24 FPDAT7 Blue digital data signal X 6 D23 FPDAT8 _ Blue digital data signal X 7 D22 FPDAT15 Blue digital data signal X 8 D21 FPDAT16 Blue digital data signal X 9 D20 FPDAT17 Blue digital data signal LSB X 10 GCP DRDY PWM output pulse width setting signal X 11 FR GPIO2 AC signal for output X 12 LP FPLINE Data load and
208. ASCII text file formats are supported Most are formatted C header files used to build display drivers or standalone applications Utility files based on the Hardware Abstraction Layer HAL can be modified directly by 13706CFG 13706CFG Configuration Program Issue Date 01 03 29 Epson Research and Development Page 7 Vancouver Design Center 13706CFG Configuration Tabs 13706CFG provides a series of tabs which can be selected at the top of the main window Each tab allows the configuration of a specific aspect of S1D13706 operation The tabs are labeled General Preference Clocks Panel Panel Power and Registers The following sections describe the purpose and use of each of the tabs General Tab 51D13706 Configuration Utility a The General tab contains S1D13706 evaluation board specific information The values presented are used for configuring HAL based executable utilities The settings on this tab specify where in CPU address space the registers and display buffer are located Decode Addresses Selecting one of the listed evaluation platforms changes the values for the Register address and Display buffer address fields The values used for each evalu ation platform are examples of possible implementa tions as used by the Epson S1D13706 evaluation board If your hardware implementation differs from the addresses used select the User Defined option and enter the correct add
209. AT1 D1 D1 R5 D1 R3 D1 G5 R1 R2 R4 R4 R4 FPDAT2 D2 D2 G4 D2 B2 D2 B4 RO R1 R3 R3 R3 FPDAT3 D3 D3 B3 D3 G2 D3 R4 G2 G3 G5 G5 G5 FPDAT4 DO D4 Do R2 D4 R3 D4 R2 D8 B5 G1 G2 G4 G4 G4 FPDAT5 D1 D5 D1 B1 D5 G2 D5 B1 D9 R5 GO G1 G3 G3 G3 FPDAT6 D2 D6 D2 G1 D6 B1 D6 G1 D10 G4 B2 B3 B5 B5 B5 FPDAT7 D3 D7 D3 R1 D7 R1 D7 R1 D11 B3 B1 B2 B4 B4 B4 FPDAT8 D4 G3 BO B1 B3 B3 B3 FPDAT9 D5 B2 RO R2 R2 R2 FPDAT10 D6 R2 R1 R1 R1 FPDAT11 D7 G1 RO RO RO FPDAT12 D12 R3 GO G2 G2 G2 FPDAT13 D13 G2y G1 G1 G1 FPDAT14 D14 B1 GO GO GO FPDAT15 D15 R1 BO B2 B2 B2 FPDAT16 B1 B1 B1 FPDAT17 BO BO BO GPIOO GPIOO GPIOO GPIOO GPIOO GPIOO GPIOO GPIOO GPIOO GPIOO PS XINH GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 CLS YSCL GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 REV FR GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 SPL FRS GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 apioa GPIO4 GPIO4 GPIO4 ea aa RES GPIO5 GPIO5 GPios GPIO5 GPIO5 GPIOS GPIOS GPIOS GPIOS GPIOS a w DDPt GPIO6 GPIO6 GPlos GPIO6 GPIO6 GPios GPios GPios GPios GPio6 f Eint YSCLD GPO GPO General Purpose Output MOD GPO CVOUT CVOUT PWMOUT PWMOUT Note 1 GPIO pins must be configured as outputs CNF3 0 at RESET when the HR TFT or D TFD interface is selected 2 These pin mappings use signal names commonly used for each panel type
210. All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 02 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center Table of Contents E gt INGFODUCTION s oar e sik oe as AR AA AR A A 7 2 Interfacing to the MPC821 40 oo ai A E eee a aS 8 2 1 The MPC8XX System Bus 2 2 2 0 8 2 2 MPC8XX Bus Overview 8 2 2 1 Normal Non Burst Bus Transactions o 9 2 22 Burst yc airis al A A ewe Ae ade BS ae AA 10 2 3 Memory Controller Module e a A leo Yo 2 3 1 General Purpose Chip Select Module le GPCM O eerie se 11 2 3 2 User Programmable Machine UPM o o 0020005 12 3 S1D13706 Host Bus Interface 13 3 1 Host Bus Interfac
211. C Card Bus Issue Date 01 02 23 S1D13706 X31B G 005 02 Page 10 3 S1D13706 Host Bus Interface The S1D13706 directly supports multiple processors The S1D13706 implements a 16 bit Generic 2 Host Bus Interface which is most suitable for direct connection to the PC Card bus Generic 2 supports an external Chip Select shared Read Write Enable for high byte and individual Read Write Enable for low byte Epson Research and Development Vancouver Design Center The Generic 2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 13 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping Fereg PC Card PCMCIA AB 16 0 A 16 0 DB 15 0 D 15 0 WE1 CE2 CS External Decode M R A17 CLKI see note BS connect to HIO Vpp RD WR connect to HIO Vpp RD OE WEO WE WAIT WAIT RESET Inverted RESET Note Although a clock is not directly supplied by the PC Card interface one is required by the S1D13706 Generic 2 Host Bus Interface For an example of how this can be accom plished see the discussion on CLKI in Section 3 2 Host Bus Interface Signals on page
212. C68K 1 Interface Timing e g MC68000 44 Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 4 Epson Research and Development Vancouver Design Center 6 2 6 Motorola MC68K 2 Interface Timing e g MC68030 46 6 2 7 Motorola REDCAP2 Interface Timing o 48 6 2 8 Motorola DragonBall Interface Timing with DTACK e g MC68EZ328 MC68VZ328 o o oo 50 6 2 9 Motorola DragonBall Interface Timing w o DTACK e g MC68EZ328 MC68VZ328 o ee 52 6 3 LCD Power Sequencing DA 6 3 1 Passive TFT Power On Sequence e 54 6 3 2 Passive TFT Power Off Sequence o e 55 6 4 Display Interface o o m e osos e 56 6 4 1 Generic STN Panel Timing a a e e e a A a ATA 58 6 4 2 Single Monochrome 4 Bit Panel Timing 60 6 4 3 Single Monochrome 8 Bit Panel Timing 62 6 4 4 Single Color 4 Bit Panel Timing 64 6 4 5 Single Color 8 Bit Panel Timing Format 1 0 66 6 4 6 Single Color 8 Bit Panel Timing Format 2 68 6 4 7 Single Color 16 Bit Panel Timing a 70 6 4 8 Generic TFT Panel Timing e 72 6 4 9 9 12 18 Bit TFT Panel Timing 2 0 200004 73 6 4 10 160x160 Sharp Direct HR TFT Panel Timing e g LQ031B1DDxx 76 6 4
213. CD Controller Linux Console Driver Document Number X31B E 004 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Linux Console Driver X31B E 004 02 Issue Date 01 09 19 Epson Research and Development Page 3 Vancouver Design Center Linux Console Driver Linux Console Driver Issue Date 01 09 19 The Linux console driver for the S1D13706 Embedded Memory LCD Controller is intended as reference source code for OEMs developing for Linux and supports 4 8 and 16 bit per pixel color depths A Graphical User Interface GUI such as Gnome can obtain the frame buffer address from this driver allowing the Linux GUI the ability to update the display The console driver is designed around a common configuration include file called s1d13706 h which is generated by the configuration utility 13706CFG
214. CF5307 To S1D13706 Interface 4 1 Hardware Description Page 13 The interface between the S1D13706 and the MCF5307 requires no external glue logic The polarity of the WAIT signal must be selected as active high by connecting CNF5 to NIO Vpp see Table 4 1 Summary of Power On Reset Configuration Options on page 14 The following diagram shows a typical implementation of the MCF5307 to S1D13706 interface MCF5307 1D13706 A 16 0 gt AB 16 0 D 23 16 gt DB 7 0 D 31 24 gt DB 15 8 A17 gt M R CS4 CS HIO Vp A L__ BSH TA WAIT BWE1 gt WE1 BWEO WEO OE p RD WR LT RD BCLKO gt CLKI System RESET gt RESET Note When connecting the S1D13706 RESET pin the system designer should be aware of all conditions that may reset the S1D13706 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MCF3307 to S1D13706 Interface Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 23 S1D13706 X31B G 010 02 Page 14 Epson Research and Development Vancouver Design Center 4 2 S1D13706 Hardware Configuration 1D13706 X31B G 010 02 The S1D13706 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13706 Hardwar
215. CLKI 6 MHz CLKI2 6 MHz 1 2 8 bpp 9 43 3 02 0 00 LCD Panel 60Hz 320x240 18 bit TFT CLKI 6 MHz CLKI2 6 MHz 1 2 8 bpp 8 84 3 02 0 00 LCD Panel 60Hz 320x240 18 bit HR TFT CLKI 6 MHz CLKI2 6 MHz 1 2 8 bpp 9 26 3 02 0 00 LCD Panel 60Hz 320x240 18 bit D TFD GLKI 6 MHz CLKI2 6 MHz 1 2 8 bpp 9 78 3 02 0 00 LCD Panel 60Hz 160x240 18 bit D TFD 1 2 8 bpp 6 45 3 02 0 00 CLKI 6 MHz CLKI2 6 MHz 1 1 16 bpp 8 12 3 02 0 00 Note l CLKI and CLKI2 are stopped for this condition 1D13706 X31B G 006 02 Power Consumption Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center 2 Summary Power Consumption Issue Date 01 02 23 The system design variables in Section 1 S1D13706 Power Consumption and in Table 1 1 S1D13706 Total Power Consumption in mW show that S1D13706 power consumption depends on the specific implementation Active Mode power consumption depends on the desired CPU performance and LCD frame rate whereas power save mode consumption depends on the CPU Interface and Input Clock state In a typical design environment the 1D13706 can be configured to be an extremely power efficient LCD Controller with high performance and flexibility 1D13706 X31B G 006 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Power Consumption X31B G 006 02 Issue Date 01 02 23 EPSON 1D13706 Embedded Mem
216. CPU access times e Registers are memory mapped M R input selects between memory and register address space e The complete 80K byte display buffer is directly and contiguously available through the 17 bit address bus Single level CPU write buffer 2 3 Display Support e Single panel single drive passive displays e 4 8 bit monochrome LCD interface e 4 8 16 bit color LCD interface e Active Matrix TFT interface e 9 12 18 bit interface Direct support for 18 bit Epson D TFD interface Direct support for 18 bit Sharp HR TFT interface 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 13 Vancouver Design Center 2 4 Display Modes e 1 2 4 8 16 bit per pixel bpp color depths e Up to 64 gray shades using Frame Rate Modulation FRM and dithering on mono chrome passive LCD panels e Up to 64K colors on passive STN panels e Up to 64K colors on active matrix LCD panels e Example resolutions 320x240 at a color depth of 8 bpp 160x160 at a color depth of 16 bpp 160x240 at a color depth of 16 bpp 2 5 Display Features SwivelView 90 180 270 counter clockwise hardware rotation of display image Picture in Picture Plus displays a variable size window overlaid over background image Double Buffering Multi pages provides smooth animation and instantaneous screen updates 2 6 Clock Source e Two clock inputs CLKI an
217. CSn asserted for MCLK BCLK 4 15 15 Toxo t6 EBO EBT asserted to CKO rising edge write cycle 1 1 ns t7 EBO EB1 de asserted to CKO rising edge write cycle 1 4 ns ig P 15 0 input setup to 3rd CKO rising edge after EBO or EBT 4 0 de asserted low write cycle see note 1 to D 15 0 input hold from 3rd CKO rising edge after EBO or EBT 23 8 Be asserted low write cycle t10 OE EBO EB1 setup to CKO rising edge read cycle 1 0 ns t11 OE EBO EBT hold to CKO rising edge read cycle 1 0 ns t12 DI15 0 output delay from OE EBO EB1 falling edge 4 29 3 10 n read cycle t13a 1St CKO rising edge after EBO or EB1 asserted low to D 15 0 4 5CKO 4 5CKO a valid for MCLK BCLK read cycle 7 20 t13b 1st CKO rising edge after EBO or EB asserted low to D 15 0 7CKO 6 5CKO valid for MCLK BCLK 2 read cycle 10 20 130 1st CKO rising edge after EBO or EB1 asserted low to D 15 0 8 5CKO 9 5CKO 1 valid for MCLK BCLK 3 read cycle 8 20 t13q_ 1st CKO rising edge after EBO or EB asserted low to D 15 0 9CKO 11 5CKO a valid for MCLK BCLK 4 read cycle 11 20 t14 CKO rising edge to D 15 0 output in Hi Z read cycle 4 31 1 11 ns 1 t8is the delay from when data is placed on the bus until the data is latched into the write buffer Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 50 Epson Research and Development Vancouver Design Center 6 2 8 Motorola DragonBall Interf
218. Color is an index into the lookup table At 16 bpp the lookup table is bypassed and each word of display memory forms the color to display In this mode the least significant word describes the color to draw the line with in 5 6 5 RGB format Return Value None Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 92 Epson Research and Development Vancouver Design Center void seDrawRect long x1 long y1 long x2 long y2 DWORD Color BOOL Solid Fill void seDrawMainWinRect long x1 long y1 long x2 long y2 DWORD Color BOOL SolidFill void seDrawSubWinRect long x1 long y1 long x2 long y2 DWORD Color BOOL SolidFill Description Parameters Return Value 1D13706 X31B G 003 03 These routines draw a rectangle on the screen in the specified color The rectangle is bounded on the upper left by the co ordinate x1 y1 and on the lower right by the co ordinate x2 y2 The SolidFill parameter allows the programmer to select whether to fill the interior of the rectangle or to only draw the border Use seDrawRect to draw a rectangle on the current active display surface See seSet MainWinAsActiveSurface and seSetSubWinAsActiveSurface for information about changing the active surface Use seDrawMainWinRect and seDrawSubWinRect to draw a rectangle on the display surface indicated by the function name If no memory was allocated to the surface these functions return without writin
219. Connected to A5 of the S1D13706 7 Connected to A6 of the S1D13706 8 Connected to A7 of the S1D13706 9 Ground 10 Ground 11 Connected to A8 of the S1D13706 12 Connected to A9 of the S1D13706 13 Connected to A10 of the S1D13706 14 Connected to A11 of the S1D13706 15 Connected to A12 of the S1D13706 16 Connected to A13 of the S1D13706 17 Ground 18 Ground 19 Connected to A14 of the S1D13706 20 Connected to A15 of the S1D13706 21 Connected to A16 of the S1D13706 22 Not connected 23 Not connected 24 Not connected 25 Ground 26 Ground 27 5 volt supply 28 5 volt supply 29 Connected to RD WRH of the S1D13706 30 Connected to BS of the S1D13706 31 Connected to BUSCLK of the S1D13706 32 Connected to RD of the S1D13706 33 Not connected 34 Not connected S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 Page 17 S1D13706 X31B G 004 04 Page 18 5 LCD Interface Pin Mapping Table 5 1 LCD Signal Connector H1 Epson Research and Development Vancouver Design Center Monochrome Color Passive Panel Color TFT Panel Passive Pin Connector Single Sharp Epson Name Pin No Single Fomai Format Others HR TFT D TFD 8 bit 16 Bit 9 bit 12 bit 18 bit 18 bit 18 bit FPDATO 1 DO G3 DO R6
220. Date 01 02 23 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 Toshiba MIPS TMPR3905 12 Processor http www toshiba com taec nonflash indexproducts html Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 01 02 23 Page 17 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13706 X31B G 002 02 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 02 Issue Date 01 02 23 EPSON 1D13706 Embedded Memory LCD Contro
221. Design Center Mechanical Layer 1 27 Mar 2000 SEKO EPSON CORP SDU1376B0C REV 1 0 EVALUATION BOARD S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 12 Technical Support 12 1 EPSON LCD Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 Page 35 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13706 X31B G 004 04 Page 36 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 0
222. Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface requires the following signals CLKI is a clock input which is required by the S1D13706 host bus interface and connects to CKO of the REDCAP2 The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the REDCAP2 bus address A 16 0 and data bus D 15 0 respectively CNF 2 0 and CNF4 must be set to select the REDCAP2 host bus interface with big endian mode M R memory register selects between memory or register access It may be connected to an address line allowing REDCAP2 bus address A17 to be connected to the M R line CS Chip Select must be driven low whenever the S1D13706 is accessed by the REDCAP2 bus RD WR connects to R W which indicates whether a read or a write access is being performed on the S1D13706 WE1 and WEO connect to EBO and EB1 Enable Byte 0 and 1 for byte steering RD connects to OE Output Enable This signal must be driven by the REDCAP2 bus to indicate the bus access is a read and enables slave devices to drive the data bus with read data The BS and WAIT signals are not needed for this bus interface they should be connected to HIO Vpp Interfacing to the Motorola RedCap2 DSP With Integrated MCU 1D13706 Issue Date 01 02 23 X31B G 014 02 Page 12 Epson Research and Development Vancouver Design Center 4 REDCAP2 to S1D13706 Interface 4 1 Hardware Descri
223. Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 6 2 Sharp HR TFT Panel North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www sharpsma com S1D13706 X31B G 01 1 04 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Connecting to the Sharp HR TFT Panels Issue Date 01 02 23 EPSON 1D13706 Embedded Memory LCD Controller Interfacing to the Motorola MC68030 Microprocessor Document Number X31B G 013 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents o
224. Dh 00 0000 0000 Sets the sub window X end position 90h EF 1110 1111 a 91h 00 0000 0000 Sets the sub window Y end position AOh 00 0000 0000 Disables power save mode Ath 00 0000 0000 Reserved register Must be written OOh A2h 00 0000 0000 Set reserved bit 7 to 0 A3h 00 0000 0000 Reserved register Must be written OOh A4h 00 0000 0000 gt A5h 00 0000 0000 Clears the scratch pad registers A8h 00 0000 0000 GPIO 6 0 pins are configured as input pins A9h 80 1000 0000 Bit 7 set to 1 to enable GPIO pin inputs S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center Table 2 1 Example Register Values Continued Page 13 BOh Bih B2h B3h 00 00 00 00 0000 0000 0000 0000 0000 0000 0000 0000 Value Value i N Register Hex Binary Description otes ACh 00 0000 0000 GPIO 6 0 pins are driven low Bit 7 controls the LCD bias ADh 00 0000 0000 Set the GPO control bit to low power for the panel on the S5U13706B00C Selects the following PWMOUT pin is software controlled PWM Clock circuitry is disabled CVOUT pin is software controlled CV Pulse circuitry is disabled Sets the PWM Clock and CV Pulse divides Sets the CV Pulse Burst Length Sets the PWMOUT signal to always low For this example the divides are not required For this example the burst length is not required
225. Diagram Generic 1 Bus Oscillator Generic 2 BUS VDD t BS x Ji O bit RD WR FPDAT 8 0 gt D 8 0 TFT A 27 17 _______ Decoder M R FPFRAME FPFRAME Display CSn CS gt FPLINE gt FPLINE 5 A 16 0 AB 16 0 FPSHIFT gt gt FPSHIFT D 15 0 4 gt DB 15 0 DRDY DRDY a WE WEO S1 D1 3 06 BHE gt WE1 GPO f RD gt RD WAITH a WAIT BUSCLK gt CLKI RESET gt RESET Figure 3 2 Typical System Diagram Generic 2 Bus S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 15 Vancouver Design Center Issue Date 01 11 13 Oscillator SH 4 BUS y a S A 25 17 Decoder M R a FPDAT15 Dii 12 bit FPDAT12 D10 Display CSn gt CS FPDAT 9 0 D 9 0 A 16 1 gt AB 16 1 FPFRAME FPFRAME FPLINE FPLINE gt D 15 0 gt DB 15 0 3 WED weds FPSHIFT FPSHIFT 5 DRDY 2 WE1 gt WE1 DRDY k BS gt BS S1 D1 3706 i RD WR gt RD WR GPO RD gt RD RDY e WAIT CKIO gt CLKI RESET gt RESET ABO VSS Figure 3 3 Typical System Diagram Hitachi SH 4 Bus Oscillator SH 3 BUS y a A 25 17 Decoder L y M R A 18 bit FPDAT 17 0
226. Display Start Address registers REG 74h is set to 00h REG 75h is set to 00h and REG 76h is set to 00h 3 Determine the main window line address offset number of dwords per line image width 32 bpp 320 32 4 40 28h Program the Main Window Line Address Offset registers REG 78h is set to 28h and REG 79h is set to 00h Example 2 In SwivelView 90 mode program the main window registers for a 320x240 panel at a color depth of 4 bpp 1 Confirm the main window coordinates are valid The vertical coordinates must be a multiple of 32 bpp 240 32 4 30 Main window vertical coordinate is valid 2 Determine the main window display start address The main window is typically placed at the start of display memory which is at dis play address 0 main window display start address register desired byte address panel height x bpp 8 4 1 0 240 x 4 8 4 1 29 1Dh Program the Main Window Display Start Address registers REG 74h is set to 1Dh REG 75h is set to 00h and REG 76h is set to 00h 3 Determine the main window line address offset number of dwords per line image width 32 bpp 240 32 4 30 1Eh Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 35 Vancouver Design Center Program the Main Window Line Address Offset register REG 78h is set to 1Eh and REG 79h is set to 00h Example 3 In SwivelVie
227. EG 05h 21h BCLK 4 REG 05h 31h BCLK 8 REG 05h 41h CLKI REG 05h 02h CLKI 2 REG 05h 12h CLKI 3 REG 05h 22h CLKI 4 REG 05h 32h CLKI 8 REG 05h 42h CLKI2 REG 05h 03h CLKI2 2 REG 05h 13h CLKI2 3 REG 05h 23h CLKI2 4 REG 05h 33h CLKI2 8 REG 05h 43h Hardware Functional Specification Issue Date 01 11 13 1D13706 X31B A 001 08 Page 92 Epson Research and Development Vancouver Design Center There is a relationship between the frequency of MCLK and PCLK that must be maintained Table 7 4 Relationship between MCLK and PCLK SwivelView Orientation Color Depth bpp MCLK to PCLK Relationship 16 fuck 2 fpcLk 8 fucLk 2 fpcLk 2 SwivelView 0 and 180 4 mcLk 2 TrcLk 4 2 fuck 2 feck 8 1 fuck 2 fpcik 16 SwivelView 90 and 270 16 8 4 2 1 mcLk 2 1 25tpcLk 7 1 4 PWMCLK PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel The source clock options for PWMCLK may be selected as in the following table Table 7 5 PWMCLK Clock Selection Source Clock Options PWMCLK Selection CLKI REG B1h bit 0 0 CLKI2 REG B1h bit 0 1 For further information on controlling PWMCLK see Section 8 3 9 Pulse Width Modulation PWM Clock and Contrast Voltage CV Pulse Configuration Registers on page 126 Note The S1D13706 provides Pulse Width Modulation output on t
228. EG OFh Write Only LUT Read Address Bits 7 0 7 6 5 4 3 2 1 0 bits 7 0 LUT Read Address Bits 7 0 This register forms a pointer into the Look Up Table LUT which is used to read LUT blue green and red data Blue data is read from REG OCh green data from REG ODh and red data from REG OEh This is a write only register and returns 00h if read Note If a write to the LUT Write Address register REG OBh is made the LUT Read Ad dress register is automatically updated with the same value 8 3 4 Panel Configuration Registers Panel Type Register REG 10h Read Write Active Panel Panel Data Color Mono panel Data Width Bits 1 0 Resolution n a Panel Type Bits 1 0 Format Select Panel Select Select 7 6 5 4 3 2 1 0 bit 7 Panel Data Format Select When this bit 0 8 bit single color passive LCD panel data format 1 is selected For AC timing see Section 6 4 5 Single Color 8 Bit Panel Timing Format 1 on page 66 When this bit 1 8 bit single color passive LCD panel data format 2 is selected For AC timing see Section 6 4 6 Single Color 8 Bit Panel Timing Format 2 on page 68 bit 6 Color Mono Panel Select When this bit 0 a monochrome LCD panel is selected When this bit 1 a color LCD panel is selected Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Epson Research and Development
229. EPSON 1D13706 Embedded Memory LCD Controller S1D13706 TECHNICAL MANUAL Document Number X31B Q 001 06 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 TECHNICAL MANUAL X31B Q 001 06 Issue Date 01 04 17 Epson Research and Development Vancouver Design Center COMPREHENSIVE SUPPORT TOOLS Page 3 EPSON provides the designer and manufacturer a complete set of resources and tools for the development of LCD Graphics Systems Documentation Technical manuals Evaluation Demonstration board manual Evaluation Demonstration Board e Assembled and fully tested Graphics Evaluation Demonstration board e Schematic of Evaluation Demonstration board e Parts List e Installation Guide CPU Independent Software Utilities e
230. ESA 46 1 U14 ad 144 pin QFP Altera EPF6016TC144 2 8 pin DIP 7 inn 47 1 U15 socket 8 pin DIP socket Machined socket 8 pin Altera EPC1441PC8 48 1 U15 EPC1441PC8 8 pin DIP pokg programmed socketed 1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 Epson Research and Development Page 27 Vancouver Design Center Table 9 1 Parts List Manufacturer Part No Item Designation Part Val D ription te Qty esignatio art Value escriptio Assembly Instructions Fundamental Mode Parallel 49 1 Y1 14 31818MHz Resonant Crystal HC49 Low FOXS 143 20 or equivalent Profile pckg 50 7 JP1 JP7 Micro Shunt Computer Bracket Blank 51 1 Bracket PCI Keystone Cat No 9203 Screw pan head 4 40 x 1 4 52 2 Screw Pan head 4 40 x 1 4 please assemble bracket onto board S5U13706B00C Rev 1 0 Evaluation Board User Manual S1D13706 Issue Date 01 02 23 X31B G 004 04 T 19 3 ra 0002 80 INAP psSUups Vancouver Design Center lt 300 gt Jaquinyy yu un20g Z MS dIG VO0S90ZELCIS O L 49H D00890ZE LNSS k Epson Research and Development 9 BIINODUG rr 2 yaa vaH bar _ V00490 8101S HA tlw 13534 O MONSMA je cL Gi ma 90149 SOldD aW Hdd loiz iydd K OEE LAOEE QA0EE
231. Epson Research and Development Vancouver Design Center 1D13706 X31B G 004 04 Figure 10 4 SIDI3706B00C Schematics 4 of 6 T Y T T P r oo oe epsa m lt 209 gt Na J9qUINN wewinoog saiddng amod 0 A9 DOOE90ZE INSS a Z 430Y3H Lar an neono li 008 veeez LENIN zo HS 10d 1085 nzi vO e 00m HRW osy peqetndog 30N ool ji Ji 4 a Sh See sen ses y 160 o iu H e a ozv 6pLXYN MAS 92 LEER T TE E sued QOTAOS Z I OL ngg gt npo J Ha ray 09 5 620 0 ep ro 2 vZ6LIZ3 ba n P 99A007 MYIL ZZO monz St Sed ica net Ino 830Y3H Sar la 104 002 es ves AL ve si 108 2 Lzoy pes eeu zu mino Se ED U3QIH Zo F are ie PSLXVN Ged Be Wk veezc Lent Tygo ano Es si TASSOE LINW TANGY NOS Es bed 30 AI E XA NOI el 08 vr e 2198 zHiiva ravi l PERM een El Cas aa FS reo 6i 2 6189n Tn HOGA 4 rt Jo06e LEW k ja 10 nornez Luny as T nee I 1 1 S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 Epson Research and Development Page 32 Vancouver Design Center
232. EpsonMessages This debugging option enables the display of EPSON specific debug messages These debug message are sent to the serial debugging port This option should be disabled unless you are debugging the display driver as they will significantly impact the performance of the display driver DEBUG_MONITOR GrayPalette Mode File 1D13706 X31B E 006 01 This option enables the use of the debug monitor The debug monitor can be invoked when the display driver is first loaded and can be used to view registers and perform a few debugging tasks The debug monitor is still under development and is UNTESTED This option should remain disabled unless you are performing specific debugging tasks that require the debug monitor This option is intended for the support of monochrome panels only The option causes palette colors to be grayscaled for correct display on a mono panel For use with color panels this option should not be enabled The MODE tables contained in files MODE0 H MODE1 H MODE2 H contain register information to control the desired display mode The MODE tables must be generated by the configuration program 13706CFG EXE The display driver comes with example MODE tables By default only MODEO H is used by the display driver New mode tables can be created using the 13706CFG program Edit the include section of MODE H to add the new mode table If you only support a single display mode you do not need to add
233. Evaluation Software e Display Drivers Application Engineering Support EPSON offers the following services through their Sales and Marketing Network e Sales Technical Support e Customer Training e Design Assistance Application Engineering Support Engineering and Sales Support is provided by Japan North America Seiko Epson Corporation Epson Electronics America Inc Electronic Devices Marketing Division 150 River Oaks Parkway 421 8 Hino Hino shi San Jose CA 95134 USA Tokyo 191 8501 Japan Tel 408 922 0200 Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Fax 408 922 0238 http www eea epson com Hong Kong Europe Epson Hong Kong Ltd Epson Europe Electronics GmbH 20 F Harbour Centre Riesstrasse 15 25 Harbour Road 80992 Munich Germany Wanchai Hong Kong Tel 089 14005 0 Tel 2585 4600 Fax 089 14005 110 Fax 2827 4346 TECHNICAL MANUAL Issue Date 01 04 17 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13706 X31B Q 001 06 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 TECHNICAL MANUAL X31B Q 001 06 Issue Date 01 04 17 EPSON amp GRAPHICS March 2001 1D13706 Embedded Me
234. FF Blue Look Up Table 256x6 a p x 6 bit Blue Data 00 0 gt 01 1 FC FD FE FF 1 bit per pixe data from Image Buffer unused Look Up Table entries Figure 11 5 1 Bit Per Pixel Color Mode Data Output Path S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 135 Vancouver Design Center 2 Bit Per Pixel Color Red Look Up Table 256x6 po a 6 bit Red Data 02 10 03 11 Fo A FD FE FF Green Look Up Table 256x6 00 00 bi 01 01 6 bit Green Data 02 10 03 11 FC FD A FE FF Blue Look Up Table 256x6 Ay oo 6 bit Blue Data 02 10 03 11 FC FD e FE FF 2 biper pixel data from Image Buffer unused Look Up Table entries Figure 11 6 2 Bit Per Pixel Color Mode Data Output Path Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 136 4 Bit Per Pixel Color Epson Research and Development Vancouver Design Center 4 bit per pixel data from Image Buffer Red Look Up Table 256x6 Green Look Up Table 256x6
235. FPLINE y M DRDY MOD X ay E HDP pa MP FPSHIFT 21s Ts 21s 21s Ts 27s 2Ts Ts 2s e Ts Ts Ts Ts Ts Ts Ts 77777 FPDAT7 nvalid 1 R1 X 1 B3 Y 1 66 X X Y a XI Invalid X FPDAT6 Iwaid Tar RN eoe Te m FPDAT5 maid BARR X Y X X XIRI Invalid FPDAT4 maid irea O a KESIN invalid X FPDAT3 nvalid X 1 X 1 R5 X 1 87 X Y gt XTESIO Invalid Y FPDAT2 nvalid 182 X 1 65 Y 1 78 X y Y TESEN T R320X Invalid Y FPDAT1 maid X R XIB5 XTX X X VISO inaid Y FPDATO nvalid X 1 X 1 Re X 1 B8 Y Y1 B320 invalid Notes The duty cycle of FPSHIFT changes in order to process 8 pixels in 3 FPSHIFT rising clocks Ts Pixel clock period PCLK Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 6 23 Single Color 8 Bit Panel Timing Format 2 VDP Vertical Display Period REG 1 Dh bits 1 0 REG 1Ch bits 7 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 19h bits 1 0 REG 18h bits 7 0 REG 1Dh bits 1 0 REG 1 Ch bits 7 0 Lines Horizontal Display Period REG 14h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts HDP 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Rese
236. G 76h must be programmed with the address of pixel D To calculate the value of the address of pixel D use the following formula assumes 8 bpp color depth Main Window Display Start Address bits 16 0 image address offset x panel height 1 panel width x bpp 8 4 1 0 480 pixels x 319 pixels 480 pixels x 8 bpp 8 4 1 38399 95FFh 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 141 Vancouver Design Center Line Address Offset The Main Window Line Address Offset registers REG 78h REG 79h is based on the display width and programmed using the following formula Main Window Line Address Offset bits 9 0 display width in pixels 32 bpp 480 pixels 32 8 bpp 120 78h 12 4 270 SwivelView 270 SwivelView requires the Memory Clock MCLK to be at least 1 25 times the frequency of the Pixel Clock PCLK i e MCLK gt 1 25PCLK The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed The application image is written to the 1D13706 in the following sense A B C D The display is refreshed by the S1D13706 in the following sense C A D B physical memory start address A JA B a gt 3 SwivelView O ae window Ss 5 display start address S amp A panel origin 2s E w C D M a 480 320 image seen by
237. G OCh Look Up Table Blue Read Data Register 100 REG 0Dh Look Up Table Green Read Data Register 100 REG OEh Look Up Table Red Read Data Register 101 REG OFh Look Up Table Read Address Register 101 REG 10h Panel Type Register 101 REG 11h MOD Rate Register 103 REG 12h Horizontal Total Register 103 REG 14h Horizontal Display Period Register 103 REG 16h Horizontal Display Period Start Position Register O 104 REG 17h Horizontal Display Period Start Position Register 1 104 REG 18h Vertical Total Register 0 105 REG 19h Vertical Total Register 1 105 REG 1Ch Vertical Display Period Register 0 105 REG 1Dh Vertical Display Period Register 1 105 REG 1Eh Vertical Display Period Start Position Register O 106 REG 1Fh Vertical Display Period Start Position Register 1 106 REG 20h FPLINE Pulse Width Register 106 REG 22h FPLINE Pulse Start Position Register O 107 REG 23h FPLINE Pulse Start Position Register 1 107 REG 24h FPFRAME Pulse Width Register 107 REG 26h FPFRAME Pulse Start Position Register 0 108 REG 27h FPFRAME Pulse Start Position Register 1 108 REG 28h D TFD GCP Index Register 108 REG 2Ch D TFD GCP Data Register 108 REG 70h Display Mode Register 109 REG 71h Special Effects Register 111 REG 74h Main Window Display Start Address Register 0 113 REG 75h Main Window Display Start Address Register 1 113 REG 76h Main Window Display Start Address Register 2 113 REG 78h Main Window Line Address O
238. GE LEFT BLANK S1D13706 Linux Console Driver X31B E 004 02 Issue Date 01 09 19 EPSON 1D13706 Embedded Memory LCD Controller QNX Photon v2 0 Display Driver Document Number X31B E 005 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 QNX Photon v2 0 Display Driver X31B E 005 02 Issue Date 01 09 10 Epson Research and Development Page 3 Vancouver Design Center QNX Photon v2 0 Display Driver The Photon v2 0 display drivers for the S1D13706 Embedded Memory LCD controller are intended as reference source code for OEMs developing for QNX platforms The driver package provides support for 8 and 16 bit per pixel color depths The source code is written for portability and contains functionality for most features of the S1D1
239. GPIO pins as inputs at power on CNF4 Big Endian bus interface CNF5 Active high WAIT CNF 7 6 see Table 4 2 CLKI to BCLK Divide Selection for recommended setting 0 GPIO pins as HR TFT D TFT outputs configuration for Toshiba TMPR3905 12 microprocessor Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 recommended setting for TMPR3905 12 microprocessor In this implementation the TMPR3905 12 control signal CARDREG is ignored This means that the S1D13706 takes up the entire PC Card slot 1 The S1D13706 is a memory mapped device and uses two 128K byte blocks which are selected using A17 from the MPC821 A17 is connected to the S1D13706 M R pin The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block The registers occupy the range Oh through 1FFFFh while the on chip display memory occupies the range 20000h through 3FFFFh Demultiplexed address lines A 25 18 are ignored Therefore the S1D13706 is aliased 256 times at 256K byte intervals over the 64M byte PC Card slot 1 memory space Note If aliasing is undesirable additional decoding circuitry must be added Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 01 02 23 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and W
240. GPIO6 and GPIO 4 0 Figure 4 1 D TFD Power On Off Sequence Timing Table 4 1 D TFD Power On Off Sequence Timing Symbol Parameter Min Max Units t1 LCD power active to LCD signals active Note 1 t2 Power Save Mode Enable bit low to LCD signals active 0 20 ns t3 Power Save Mode Enable bit high to LCD signals low 20 ns t4 LCD signals low to LCD power inactive Note 1 t5 LCD signals active to GPIO5 active 2 FRAME t6 GPIO5 Pin IO Status high to GPIO5 active 20 ns t7 GPIO5 Pin IO Status low to GPIO5 inactive 20 ns t8 GPIO5 inactive to LCD signals low 3 FRAME 1 tl and t4 are controlled by software and must be determined from the timing requirements of the panel connected 1D13706 Connecting to the Epson D TFD Panels X31B G 012 03 Issue Date 01 02 23 Epson Research and Development Page 19 Vancouver Design Center 5 GCP Data Signal The D TFD panel uses a 256 bit bit chain to control the pixel FPSHIFT XSCL positions relative to the falling edge of the GPIO4 RES signal A one in each bit indicates the presence of a GCP pulse at that pixel XSCL position A zero indicates the absence of a GCP pulse For D TFD AC Timing required by the S1D13706 see the D 3706 Hardware Functional Specification document number X31B A 001 xx 5 1 GCP Data Structure The S1D13706 uses two registers to program the GCP Data e D TFD GCP Index Register REG 28h e D TFD GCP Data Register REG 2Ch
241. H Epson Singapore Pte Ltd 20 F Harbour Centre Riesstrasse 15 No 1 25 Harbour Road 80992 Munich Germany Temasek Avenue 36 00 Wanchai Hong Kong Tel 089 14005 0 Millenia Tower Tel 2585 4600 Fax 089 14005 110 Singapore 039192 Fax 2827 4346 Tel 337 7911 Copyright 2000 2001 Epson Research and Development Inc All rights reserved Fax 334 2716 VDC Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Palm Computing is a registered trademark and the Palm OS platform Platinum logo is a trademark of Palm Computing Inc 3Com or its subsidiaries Microsoft Windows and the Windows Embedded Partner Logo are registered trademarks of Microsoft Corpo ration All other trademarks are the property of their respective owners MEN X31B C 001 03 B C 001 03 EPSON 1D13706 Embedded Memory LCD Controller Hardware Functional Specification Document Number X31B A 001 08 Copyright 1999 2001 Epson Research and Development Inc All Rights Reserved Information in this docume
242. HIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B G 016 02 Issue Date 01 02 26 Epson Research and Development Page 3 Vancouver Design Center Table of Contents VA JATFOGUCTION iene as a a ie note ara la Sata a aie ee arte a A eat 7 2 Interfacing to the MC68VZ328 8 2 1 The MC68VZ328 System Bus ee o 8 2 2 Chip Select Module 2 2 ee eee 8 3 S1D13706 Host Bus Interface 9 3 1 Host Bus Interface Pin Mapping 2 2 2 2 9 3 2 Host Bus Interface Signals 2 2 2 2 2 2 10 4 MC68VZ328 to S1D13706 Interface 11 4 1 Hardware Description 2 ee ee 11 4 2 S1D13706 Hardware Configuration 2 2 a a ee eee ee 12 4 2 1 Register Memory Mapping osaa aaa 13 4 2 2 MC68VZ328 Chip Select and Pin Configuration aooaa a 13 5 SOTWare ss A A ee a a det ae Ge Taa 14 References iia a a as GO ae a eg as a oe es a as da 15 61 DOCUMENES wisi AEP se a is ee A ey oe karaga et te Re LE Aosta Ae ok US 6 2 Document Sources o 15 Technical Support os E a de A Se Me a aa 16 7 1 EPSON LCD CRT Controllers S1D13706 2 2 2 2 02 2 2 2 2 2 16 72 Motorola MC68VZ328 Processor e o 16 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor S1D13706 Issue Date 01 02
243. HIS PAGE LEFT BLANK S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This manual describes the setup and operation of the S5U13706B00C Rev 1 0 Evaluation Board The board is designed as an evaluation platform for the S1D13706 Embedded Memory LCD Controller This user manual is updated as appropriate Please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd epson com for the latest revision of this document before beginning any devel opment We appreciate your comments on our documentation Please contact us via email at documentation Oerd epson com S5U13706B00C Rev 1 0 Evaluation Board User Manual S1D13706 Issue Date 01 02 23 X31B G 004 04 Page 8 2 Features 1D13706 X31B G 004 04 Epson Research and Development Vancouver Design Center Following are some features of the S5U13706B00C Rev 1 0 Evaluation Board 100 pin TQFP S1D13706F00A Embedded Memory LCD Controller with 80K bytes of embedded SRAM Headers for connecting to various Host Bus Interfaces Configuration options Manual or software adjustable positive LCD bias power supply from 20V to 40V Manual or software adjustable negative LCD bias power supply from 24V to 8V Software adjustable backlight intensity support 4 8 bit 3 3V or 5V single monochrome
244. Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk 1D13706 X31B G 018 02 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http Awww epson electronics de Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http Awww epson com sg Integrating the CFLGA 104 pin Chip Scale Package Issue Date 01 02 26 EPSON S1D13706 Embedded Memory LCD Controller Interfacing to the Intel StrongARM SA 1110 Microprocessor Document Number X31B G 019 02 Copyright 2001 2002 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current
245. IFT XSCL A 16 0 gt AB 16 0 DRY Gee D 31 1 31 16 DB 15 0 EEOO er GPIO1 c YSCL DS gt WE1 GPIO2 gt FR ASH 5 gt BS GPIO3 FR S1D13706 R W gt RD WR GPIO4 _ RES E SIZ1 RDF GPIOS _ DP SIZO WEO GPIO6 gt YSCLD H 09 DSACK1 WAIT ES GPO CLK gt CLKI RESET gt RESET Figure 3 6 Typical System Diagram MC68K 2 Motorola 32 Bit 68030 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 17 Vancouver Design Center Oscillator REDCAP2 BUS HIOVDDA Y BS Y ME a 4 bit A 21 17 Decoder M R FPDAT 7 4 p30 Single osn gt CS FPSHIFT rpsHiFt LCD Display A 16 1 gt AB 16 1 D 15 0 ld gt DB 15 0 FPFRAME FPFRAME g FPLINE FPLINE DRDY MOD S a RW gt RD WR S1 D13706 GPO i OE gt RD EBT gt WEOH EBO gt WE1 CLK gt CLKI RESET_OUT gt RESET ABO VSS V Note CSn can be any of CS0 CS4 Figure 3 7 Typical System Diagram Motorola REDCAP2 Bus Oscillator MC68EZ328 MC68VZ328 y DragonBall ND A S BUS id A 8 bit RD WR FPDAT 7 0 D 7 0 o D A 25 17 __ Decoder p M R FPSHIFT FPSHIFT Display TSX CS FPFRA
246. IO3 FRS t17 t17 gt A Eros XA DD_P1 Figure 6 34 160x240 Epson D TFD Panel Horizontal Timing S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 83 Vancouver Design Center Table 6 28 160x240 Epson D TFD Panel Horizontal Timing Symbol Parameter Min Typ Max Units t1 FPLINE pulse width 9 Ts note 1 t2 FPLINE falling edge to FPSHIFT start position 8 5 Ts t3 FPSHIFT active period 167 Ts t4 FPSHIFT start to first data 4 Ts t5 Horizontal display period 160 Ts t6 Last data to FPSHIFT inactive 3 Ts t7 FPLINE falling edge to GPIO4 first pulse falling edge 1 Ts t8 Horizontal total period 400 Ts t9 GPIO4 first pulse falling edge to second pulse falling edge 200 Ts t10 GPIO4 pulse width 11 Ts t11 GPIO1 pulse width 100 Ts t12 GPIO1 low period 100 Ts t13 GPIOO pulse width 200 Ts t14 GPIO6 low pulse width 90 Ts t15 GPIO6 rising edge to GPIOO falling edge 10 Ts t16 GPIO2 toggle to GPIO3 toggle 1 Ts t17 GPIO5 low pulse width 7 Ts 1 Ts pixel clock period Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 84 Epson Research and Development Vancouver Design Center GPIO4 RES t2 DRDY AN A en AA GCP GCP Data Register 1 1 0 1 0 0
247. IT H WAIT BUSCLK CLKI System RESET p RESET Note When connecting the S1D13706 RESET pin the system designer should be aware of all conditions that may reset the S1D13706 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of 8 bit Processor to SID13706 Interface Interfacing to 8 bit Processors Issue Date 01 02 23 1D13706 X31B G 015 02 Page 12 4 2 S1D13706 Hardware Configuration Epson Research and Development Vancouver Design Center The S1D13706 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13706 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a S1D13706 to generic 8 bit processor Table 4 1 Summary of Power On Reset Configuration Options S1D13706 Pin Name CNF 2 0 CNF3 value on this pin at the rising edge of RESET is used to configure 1 0 1 GPIO pins as inputs at power on CNF4 Big Endian bus interface CNF5 Active high WAIT CNF 7 6 see Table 4 2 CLKI to BCLK Divide Selection for recommended setting GPIO pins as HR TFT D TFT outputs 0 E configuration for generic 8 bit processor Table 4 2 CLKI to BCLK Divide Selection
248. Increments for Color Depth o o o 44 Table 8 4 32 bit Address Increments for Color Depth o o o 46 Table 10 1 HAL FUNCIONS o noy ed a Pele ask st 62 Programming Notes and Examples S1D13706 Issue Date 01 02 23 X31B G 003 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 10 1 Page 7 Vancouver Design Center List of Figures Pixel Storage for 1 Bpp in One Byte of Display Buffer 14 Pixel Storage for 2 Bpp in One Byte of Display Buffer 15 Pixel Storage for 4 Bpp in One Byte of Display Buffer 15 Pixel Storage for 8 Bpp in One Byte of Display Buffer 16 Pixel Storage for 16 Bpp in Two Bytes of Display Buffer 16 Picture in Picture Plus with SwivelView disabled o 37 Picture in Picture Plus with SwivelView disabled 48 Picture in Picture Plus with SwivelView 90 enabled o o 51 Picture in Picture Plus with SwivelView 180 enabled 54 Picture in Picture Plus with SwivelView 270 enabled 57 Components needed to build 13706 HAL application
249. LAOLE ely eld ble ola 0Old9 Ol did MS 6H ey Ze 98 SY tH ASL ASL AS ASL AS ASL ey ASL ASL ASL zH i IMS AeE TRIANA ain DOI 2 W9 so u gS 10 Schematics Page 28 01 02 23 Issue Date S5U13706B00C Rev 1 0 Evaluation Board User Manual Figure 10 1 SIDI3706B00C Schematics 1 of 6 1D13706 X31B G 004 04 Page 29 JO z SUR 000s 80 THEY AEPSSUpy lt oog gt g Jequiny juauinoog azis 4901 0 L A Y DODB90LELNSS on nosna 9S 184205 158 1 i 195008 159 E fino an9 mo go ONS 39 L ON 99M by T ASt ON 994 Fer L qe an sn as t gn 104 ave F e du T du T e195 ale sto vio a vigozaol net 2 OLN bey 4 PHN ISLE FL owiolwas Fy a TOSTE 1NOTVLX A NrWLX E 30 h n nmaumd Ra s ANONA ee x POOKIE NONI OLNI 3 orst UN gt e Z lt VIVOS Oldo gl v0DHVZ 1TONTOA E lt un 38 210 05 gos El lt T En ES Pp AN deo Ae et F oiaoi Ent T nwo T p vOOHV PL alo Ho oto z LNOMIOW Y F p vero Ae e Ast ES I 1 1 1 El Epson Research and Development Vancouver Design Center
250. LEFT BLANK 1D13706 Interfacing to the PC Card Bus X31B G 005 02 Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and the PC Card PCMCIA bus The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the PC Card Bus S1D13706 Issue Date 01 02 23 X31B G 005 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PC Card Bus 2 1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness This section is an overview of the operation of the 16 bit PC Card interface conforming to the PCMCIA 2 0 JEIDA 4 1 Standard or later 2 1 1 PC Card Overview The 16 bit PC Card provides a 26 bit address bus and additional control lines which allow access to three 64M byte address ranges These ranges are used for common memory space IO s
251. LID Figure 6 10 Motorola DragonBall Interface without DTACK Timing S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 53 Vancouver Design Center Table 6 13 Motorola DragonBall Interface without DTACK Timing MC68EZ328 MC68VZ328 Symbol Parameter 2 0V 3 3V 2 0V 3 3V Unit Min Max Min Max Min Max Min Max feiko Bus Clock frequency 16 16 20 33 MHz Terko Bus Clock period 1 fcLko 1 fcLko 1 fcLko 1 fcLko ns t1 Clock pulse width high 28 1 28 1 225 13 6 ns t2 Clock pulse width low 28 1 28 1 225 13 6 ns A 16 1 setup 1st CLKO when CSX 0 and 8 either UWE LWE or OE 0 0 0 0 ns t4 A 16 1 hold from CSX rising edge 0 0 0 0 ns CSX asserted for MCLK BCLK ta CPU wait state register should be programmed 8 8 8 8 TeLKo to 4 wait states CSX asserted for MCLK BCLK 2 t5b CPU wait state register should be programmed 11 11 11 11 TeLKo to 6 wait states CSX asserted for MCLK BCLK 3 toc CPU wait state register should be programmed Note 1 Note 1 13 13 TeLKo to 10 wait states CSX asserted for MCLK BCLK 4 t5d CPU wait state register should be programmed Note 1 Note 1 17 17 Teo to 12 wait states t6 CSX setup to CLKO rising edge 0 0 0 0 ns t7 CSX rising edge setup to CLKO rising edge 0 0 0 0 ns t8 UWE LWE setup to CLKO rising edge 1 0 1 0 ns t9 UWE LWE rising edg
252. LUT are used Each byte in the display buffer contains four adjacent pixels Table 4 6 Suggested LUT Values for 2 bpp Color Index Red Green Blue 00 00 00 00 01 00 00 FF 02 FF 00 00 03 FC FC FC 04 FF se Indicates unused entries in the LUT 1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 4 bpp color Page 23 When the 1D13706 is configured for 4 bpp color mode the first 16 entries in the LUT are used Each byte in the display buffer contains two adjacent pixels The upper and lower nibbles of the byte are used as indices into the LUT The following table shows LUT values that simulate those of a VGA operating in 16 color mode Table 4 7 Suggested LUT Values to Simulate VGA Default 16 Color Palette Index Red Green Blue 00 00 00 00 01 80 00 00 02 00 80 00 03 80 80 00 04 00 00 80 05 80 00 80 06 00 80 80 07 CO CO CO 08 80 80 80 09 FC 00 00 0A 00 FC 00 0B FC FC 00 oC 00 00 FC 0D FC 00 FC OE 00 FC FC OF FC FC FC 10 FF iF Indicates unused entries in the LUT Programming Notes and Examples Issue Date 01 02 23 1D13706 X31B G 003 03 Page 24 8 bpp color When the 1D13706 is configured for 8 bpp color mode all 256 entries in the LUT are used Each byte in the display buffer corresponds to one pixel and is used as
253. ME FPFRAME 5 FPLINE FPLINE 8 A 16 1 AB 16 1 a D 15 0 la gt DB 15 0 S1 D1 3706 ins me i LWE gt WEO GPO i UWE gt WE1 OE gt RD DTACK q WAIT CLKO gt CLKI RESET gt RESET ABO VSS V Figure 3 8 Typical System Diagram Motorola MC68EZ328 MC68VZ328 DragonBall Bus Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Vancouver Design Center Epson Research and Development Page 18 Pins 4 4 1 Pinout Diagram TQFP15 100pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 a el a S 9 8 e S 98 8 5 g afal el 18E pa SST ERE ESE E COREVDDZ NE S vss FPFRAME DB9 FPLINE DB10 FPSHIFT DB11 FPDATO DB12 FPDAT1 DB13 FPDAT2 DB14 FPDAT3 DB15 FPDAT4 WAIT FPDAT5 4 HIOVDD FPDAT6 N CLKI vss m vss NIOVDD T RESET FPDAT7 O RD WR FPDAT8 T WE1 FPDAT9 o WEO FPDAT10 RD FPDAT11 BS FPDAT12 M R FPDAT13 CS FPDAT14 ABO FPDAT15 ABI FPDAT16 AB2 FPDAT17 3 Q AB3 ss ESTER TAS ses o 2065555585856 2 222222 zS LE 3 3 3 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 Figure 4 1 Pinout Diagram TQFP15 100pin S1D13706F00A Note Package type 100 pin surface mount TQFP15 Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Epson Research and Development Vancouver Design Center 4 2 Pinout Diagram CFLGA 104pin
254. Non Display Period bit 3 Memory Controller Power Save Status This read only status bit indicates the power save state of the memory controller When this bit 0 the memory controller is powered up When this bit 1 the memory controller is powered down and the MCLK source can be turned off Note Memory writes are possible during power save mode because the 1D13706 dynamical ly enables the memory controller for display buffer writes bit 0 Power Save Mode Enable When this bit 1 the software initiated power save mode is enabled When this bit 0 the software initiated power save mode is disabled At reset this bit is set to 1 For a summary of Power Save Mode see Section 15 Power Save Mode on page 149 Note Memory writes are possible during power save mode because the 1D13706 dynamical ly enables the memory controller for display buffer writes Reserved REG A1h Read Write n a Reserved 7 5 4 3 2 1 0 bit O Reserved This bit must remain at 0 S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 121 Vancouver Design Center Reserved REG A2h Read Write Reserved n a Reserved 7 6 5 4 3 2 1 0 bit 7 Reserved This bit must remain at 0 bit 0 Reserved This bit must remain at 0 Reserved REG A3h Read Write Reserved n a 7 6 5 4 3 2 1 0 bit 7 Reserved This bit must remain at 0 Scratch Pad Register
255. O Status ANS EL o O RW Vertical Total REG 04h MEMORY CLOCK CONFIGURATION REGISTER 2 RW Bit7 Bit 6 Bit5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0 MCLK Divide Select n a n a Reserved REG 19h VERTICAL TOTAL REGISTER 1 RW bit 1 bit 0 REG 05h PIXEL CLOCK CONFIGURATION REGISTER 24 PCLK Divide Sel Bit 2 Bit 1 PCLK Source Select sit Bito REG 08h LOOK UP TABLE BLUE WRITE DATA REGISTER Bit 5 Bit 4 LUT Blue Write Data Bit 3 Bit2 Bit 1 wO REG 09h LOOK UP TABLE GREEN WRITE DATA REGISTER REG OAh LOOK UP TABLE RED WRITE LUT Green Bit 3 Write Data Bit 2 DATA REGISTER wO Bit5 Bit 4 LUT Red Write Data Bit 3 Bit 2 REG 0Bh Look Up TABLE WRITE ADDRESS REGISTER LUT Write Address REG 0Ch Look Up TABLE BLUE READ DATA REGISTER RO Bit 5 Bit 4 LUT Blue Read Data Bit 3 Bit 2 Bit 1 Bit O n a n a REG 0Dh LOOK UP TABLE GREEN READ DATA REGISTER Bit 5 Bit 4 LUT Green Bit 3 Read Data Bit 2 REG 0Eh LOOK UP TABLE RED READ DATA REGISTE Bit 5 Bit 4 LUT Red Write Data Bit 3 Bit 2 Vertical Total n a n a n a n a n a n a i 4 Bit 9 Bit 8 REG 1Ch VERTICAL DISPLAY PERIOD REGISTER 0 RW Bit 7 Bit 6 Bit 5 Vertical Display Period Bit 4 Bit 3 Bit 2 Bit 1 REG 1Dh VERTICAL DISPLAY PERIOD REGISTER 1 Display Dithering Hardware Software ae Bit per pixel Select Blank Disable Enable Video
256. ON UNITED CHEMI CON 6 2 24 032 10u 63V yee Sees Lead 63V KMF63VB10RMS5X11LL or 7 equivalent 7 4 C30 C34 C35 C37 68u 10V Tantalum D Size 10V 10 8 1 C31 1n 50V X7R 5 1206 pckg 9 2 C36 C33 33u 20V Tantalum D Size 20V 10 i A Schottky Barrier Rectifier rae 10 2 D2 D1 1N5819 MELF pckg Lite on 1N5819M or equivalent 41 4 H1 HEADER 20X2 20x2 025 sq shrouded Thomas amp Betts P N 636 4207 or header keyed equivalent 12 4 H2 HEADER 8X2 8x2 025 sq shrouded Thomas amp Betts P N 636 1607 or header keyed equivalent 13 2 H4 H3 HEADER 17X2 17x2 025 sq unsnrouaeg header 14 2 JP7 JP1 HEADER 2 2x1 1 pitch guasa header gt 3x1 1 pitch unshrouded 15 5 JP2 JP3 JP4 JP5 JP6 HEADER 3 header J W Miller PM105S 470M or A a Shielded SMT power inductor ee is 16 2 L2 L1 47uH 4 20 1 17A 0 18 ohm Digi key M1033CT ND or equivalent 17 1 Q1 MMBT3906 PNP Transistor SOT 23 Motorola or equivalent 18 4 Q2 MMFT3055VL N channel FET SOT 223 Motorola MMFT3055VL or pckg equivalent 19 1 Q3 a High gain e SOT 223 Zetex FZT792A or FZT751 20 2 Q4 Q5 MMBT2222A NPN transistor SOT 23 pckg Motorola or equivalent R1 at 5 21 14 Ro R33 R36 R37 R38 R39 tots e R10 R11 R12 R13 R14 R1 E 22 9 5 R16 R17 R18 330K 1206 5 23 1 R19 12 4K 1 1206 1 E 96 series 24 2 R20 R21 80K 1206 5 S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 S1D13706
257. PIO6 39 LB3M This pin has multiple functions e YSCLD for Epson D TFD NIOVDD 0 General purpose IO pin 6 GPIO6 See Table 4 10 LCD Interface Pin Mapping on page 31 for summary PWMOUT 38 LB3P This output pin has multiple functions NIOVDD 0 e PWM Clock output e General purpose output CVOUT 46 LB3P This output pin has multiple functions NIOVDD 0 e CV Pulse Output e General purpose output Hardware Functional Specification Issue Date 01 11 13 1D13706 X31B A 001 08 Page 28 4 4 3 Clock Input Epson Research and Development Vancouver Design Center Table 4 5 Clock Input Pin Descriptions 10 RESET ae Pin Name Type Pin Cell Voltage State Description CLKI 15 LI NIOVDD Typically used as input clock source for bus clock and memory clock CLKI2 l 77 LI NIOVDD Typically used as input clock source for pixel clock 4 4 4 Miscellaneous Table 4 6 Miscellaneous Pin Descriptions f 10 RESET pat Pin Name Type Pin Cell Voltage State Description These inputs are used to configure the S1D13706 see Table 4 8 Summary of Power On Reset Options on page 29 CNF 7 0 l 78 85 LI NIOVDD Note These pins are used for configuration of the S1D13706 and must be connected directly to IO Vpp or Vss General Purpose Output possibly used for controlling the LCD GPO O 47 LO3 NIOVDD 0 power It may al
258. PS Horizontal Display Period Start Position For TFT panels REG 17h bits 1 0 REG 16h bits 7 0 5 Ts HPS FPLINE Pulse Start Position REG 23h bits 1 0 REG 22h bits 7 0 1 HPW FPLINE Pulse Width REG 20h bits 6 0 1 VT Vertical Total REG 19h bits 1 0 REG 18h bits 7 0 1 VDP Vertical Display Period REG 1 Dh bits 1 0 REG 1Ch bits 7 0 1 VDPS Vertical Display Period Start Position REG 1Fh bits 1 0 REG 1Eh bits 7 0 Lines HT VPS FPFRAME Pulse Start Position REG 27h bits 1 0 REG 26h bits 7 0 VPW FPFRAME Pulse Width REG 24h bits 6 0 1 1 For passive panels the HDP must be a minimum of 32 pixels and must be increased by multiples of 16 For TFT panels the HDP must be a minimum of 8 pixels and must be increased by multiples of 8 2 The following formulas must be valid for all panel timings HDPS HDP lt HT VDPS VDP lt VT Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 58 Epson Research and Development Vancouver Design Center 6 4 1 Generic STN Panel Timing VT 1 Frame VPW FPFRAME FPLINE MOD DRDY l y FPDAT 17 0 a a a oe HT 1 Line i gt p HPS ji HPW k FPLINE FPSHIFT i 1PCLK y MOD DRDY FPDATII7 0
259. PWM clock circuitry Parameters Enable Set to TRUE or FALSE to enable or disable PWM Return Value None void seCvEnable int Enable Description This function enables or disables the Contrast Voltage CV pulse circuitry Parameters Enable Set to TRUE or FALSE to enable or disable CV Return Value None void sePwmControl CLOCKSELECT ClkSource int ClkDivide int DutyCycle Description This function sets up the Pulse Width Modulation PWM clock configuration registers Parameters ClkSource The clock source for PWM set to either CLKI or CLKI2 ClkDivide The clock source is divided by 2 ClkDivide Legal values for ClkDivide are from 0 to 12 decimal For example if ClkDivide is 3 the clock source is divided by 243 8 DutyCycle The PWM clock duty cycle values can be from 0 to 255 A value of 0 makes the PWM output always low and a value of 255 makes the PWM output high for 255 out of 256 clock periods Return Value None void seCvControl CLOCKSELECT ClkSource int ClkDivide int BurstLength Description This function sets up the Contrast Voltage CV pulse configuration registers Parameters ClkSource The clock source for CV set to either CLKI or CLKI2 ClkDivide The clock source is divided by 2 ClkDivide Legal values for ClkDivide are from 0 to 12 decimal For example if ClkDivide is 3 the clock source is divided by 243 8 BurstLength The number of pulses generated in a single CV pulse burst Legal values
260. Panels Issue Date 01 02 23 Epson Research and Development Page 13 Vancouver Design Center 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals The vertical system power supplies are swung between positive and negative values However the vertical control signals from the S1D13706 are between GND and VCC Signals going to the panel must be level shifted to the swinging power supply levels The transition from high to low and low to high for these control signals must take place at the same time that the swing power supply switches states Figure 2 6 Logic for Vertical Control Signals shows the circuitry required for the vertical control signals The control signals on the left are outputs from the 1D13706 and the derived control signals on the right are connected to the LCD panel YSCLD 220p 50V R1 vs gt 220p 50V U1B O vecy VB C1 TC7WO4FU 100 74AC32 S0 220p50V R2 C2 100 XINH gt 220p 50V EA C3 T4AC32ISO VCCY vay R5 D1 R4 2 7K 188388 100 o gt a gt L DY Figure 2 6 Logic for Vertical Control Signals Connecting to the Epson D TFD Panels 1D13706 Issue Date 01 02 23 X31B G 012 03 Page 14 Epson Research and Development Vancouver Design Center 3 S1D13706 to D TFD Panel Pin Mapping S1D13706 X31B G 012 03 The S1D13706 outputs and the external signals are sent to the D TFD panels through two flat cable connectors
261. Power Consumption Document Number X31B G 006 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Power Consumption X31B G 006 02 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center 1 1D13706 Power Consumption S1D13706 power consumption is affected by many system design variables Input clock frequency CLKI CLKI2 the CLKI CLKI2 frequency determines the LCD frame rate CPU performance to memory and other functions the higher the input clock frequency the higher the frame rate performance and power consumption CPU interface the S1D13706 current consumption depends on the BCLK frequency data width number of toggling pins and other factors the higher the BCLK the higher the CPU performance
262. RW 5 REG 10h Panel Type Register Software R d Vi Y 1 Vi Pi LCD Panel Data Width seca wa wa ug wa va ma Reset WO Panel Data Width Bits 1 0 ve Biy id Active Panel Data Width Size REG A3h RESERVED RW Reserved n a n a n a n a n a n a n a 10 Te bit T8 Dt 11 Reserved Reserved REG A4h SCRATCH PAD REGISTER 0 RW Scratch Pad Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Panel Type STN REG A5h SCRATCH PAD REGISTER 1 RW TFT Scratch Pad HR TFT Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 7 REG 70h Display Mode Register REG A8h GENERAL PURPOSE IO PINS CONFIGURATION REGISTER 0 RW a GPIOS Pin GPIO5 Pin GPIO4 Pin GRIOS Pin GPIO2 Pin GPIQ1 Pin GPIO0 Pin a Maximum Number of Colors Shades Rags No pe onfig onfig onfig onfig onfig onfig onfig i per pixel Color Depth bpp Passive Panel Simu laneously Select Bits 1 0 Dithering On TFT Panel Displayed Colors REG A9h GENERAL PURPOSE IO PINS CONFIGURATION REGISTER 1 RW 9 Shades GPIO Pin 256K 64 256K 64 272 Input Enable Reserved Reserved Reserved Reserved Reserved Reserved Reserved D56K 64 D56R 64 Wa 256K 64 256K 64 16 16 REG ACh GENERAL PURPOSE IO PINS STATUS CONTROL REGISTER 0 RW 256K 64 256K 64 256 64 n a GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin GPIO2 Pin GPIO1 Pin GPIOO Pin 100 16 bpp 64K 64 64K 64 64K 64 ES ANS E Cte REG ADh GENERAL PURPOSE IO PINS STATUS CONTROL REGISTER 1 RW 8 REGI 71h Special Effects Register GPO Control Reserved Reserved Reserved Reserved
263. Reserved Reserved Reserved SwivelView Mode Select Bits SwivelView Orientation Normal REG BOh PWM CLOCK CV PULSE CONTROL REGISTER RW CV Pulse 10 180 PWM Clock PWM Clock CV Pulse CV Pulse CV Pulse Force High na n a Enable Force High Burst Status Burst Start Enable 11 270 REG B1h PWM CLock CV PULSE CONFIGURATION REGISTER 9 10 RO RW PWM Clock Divide Select Bit 3 Bit 2 Bit 1 Bit 0 CV Pulse Divide S Bit 2 Bit 1 elect Bit 0 PWMCLK Source Select Page 2 Dh Fh Reserved 10 REG B1h PWM Clock CV Pulse Configuration Register CV Pulse Divide Select Bits 2 0 CV Pulse Divide Amount Oh 1 3h 8 7h 128 11 REG B3h PWMOUT Duty Cycle Register PWMOUT Duty Cycle 7 0 PWMOUT Duty Cycle 00h Always Low Oth High for 1 out of 256 clock periods 02h High for 2 out of 256 clock periods FFh High for 255 out of 256 clock periods 01 02 26 EPSON 1D13706 Embedded Memory LCD Controller 13706CFG Configuration Program Document Number X31B B 001 03 Copyright 2000 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc di
264. Round up to the nearest integer all line address values that have fractional parts REG 7Ch Sub Window Display Start Address Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 7Dh Sub Window Display Start Address Register 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 7Eh Sub Window Display Start Address Register 2 n a n a n a n a n a n a n a Bit 16 Programming Notes and Examples Issue Date 01 02 23 These registers represent a dword address which points to the start of the sub window image in the display buffer An address of 0 is the start of the display buffer For the following SwivelView mode descriptions the desired byte address is the starting display address for the sub window image and panel width and panel height refer to the physical panel dimensions Width and height are used respective to the given Swivel View mode For example the sub window height in Swivel View 90 is the sub window width in SwivelView 180 In SwivelView 0 program the start address desired byte address 4 In SwivelView 90 program the start address desired byte address sub window width x bpp 8 4 1 1D13706 X31B G 003 03 Page 40 Epson Research and Development Vancouver Design Center In SwivelView 180 program the start address desired byte address sub window width x sub window heig
265. S A17 gt M R HIO Voo HIO Vpp A BS 1K RD WR DTACK WAIT UWE WE1 LWE WEO OE RD CLKO CLKI System RESET gt RESET ie Note When connecting the S1D13706 RESET pin the system designer should be aware of all conditions that may reset the S1D13706 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MC68VZ328 to S1D13706 Interface Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor 1D13706 Issue Date 01 02 26 X31B G 016 02 Page 12 4 2 S1D13706 Hardware Configuration Epson Research and Development Vancouver Design Center The S1D13706 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13706 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a S1D13706 to Motorola MC68VZ328 microprocessor Table 4 1 Summary of Power On Reset Configuration Options 1D13706 Pin Name CNF 2 0 CNF3 value on this pin at the rising edge of RESET is used to configure 1 0 GPIO pins as inputs at power on CNF4 CNF5 CNE 7 6 see Table 4 2 CLKI to BCLK Divide Selection for recommended settings 1 GPIO pins as HR TFT D TFT
266. S 6 2 Document Sources o 15 Technical Support 2 o A Sek A A a aaa 16 7 1 EPSON LCD CRT Controllers S1D13706 2 2 2 2 02 2 2 2 2 2 16 7 2 Motorola MC68030 Processor ee ee ee 16 Interfacing to the Motorola MC68030 Microprocessor 1D13706 Issue Date 01 02 23 X31B G 013 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola MC68030 Microprocessor X31B G 013 02 Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2 1 SIZ Signal Encoding 2 2 0 2 a a a a a a E E a 8 Table 2 2 DSACK Decoding o ee ee ee 8 Table 3 1 Host Bus Interface Pin Mapping e 10 Table 4 1 Summary of Power On Reset Configuration Options 13 Table 4 2 CLKI to BCLK Divide Selection o o e 13 List of Figures Figure 4 1 Typical Implementation of MC68030 to S1D13706 Interface 12 Interfacing to the Motorola MC68030 Microprocessor S1D13706 Issue Date 01 02 23 X31B G 013 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola MC68030 Microprocessor X31B G 013 02 Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required
267. S1D13706 X31B G 002 02 A data transfer is initiated when the address is placed on the PC Card bus and one or both of the card enable signals CARD1CSL and CARD1CSH are driven low CARDREG is inactive for memory and IO cycles If only CARD1CSL is driven low 8 bit data transfers are enabled and AO specifies whether the even or odd data byte appears on the PC Card data bus lines D 7 0 If only CARD 1CSH is driven low an odd byte transfer occurs on PC Card data lines D 15 8 If both CARDICSL and CARD1CSH are driven low a 16 bit word transfer takes place on D 15 0 During a read cycle either RD or CARDIORD is driven low depending on whether a memory or IO cycle is specified A write cycle is specified by driving WE memory cycle or CARDIOWR IO cycle low The cycle can be lengthened by driving CARD1WAIT low for the time required to complete the cycle Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 01 02 23 Epson Research and Development Page 9 Vancouver Design Center Figure 2 1 Toshiba 3905 12 PC Card Memory Attribute Cycle illustrates a typical memory attribute cycle on the Toshiba 3905 12 PC Card bus A 25 0 x CARDREG ALE D 31 16 x CARD1CSL CARD1CSH RD WE CARD1WAIT 7 Figure 2 1 Toshiba 3905 12 PC Card Memory Attribute Cycle Figure 2 2 Toshiba 3905 12 PC Card IO Cycle illustrates a typical IO cycle
268. SON dll NK SH The file MODEO H located in x wince platform cepc drivers display S 1D 13706 contains the register values required to set the screen resolution color depth bpp display type active display LCD CRT TV display rotation etc Before building the display driver refer to the descriptions in the file MODEO H for the default settings of the driver If the default does not match the configuration you are building for then MODEO H will have to be regenerated with the correct informa tion Use the program 13706CFG to generate the header file For information on how to use 13706CFG refer to the 13706CFG Configuration Program User Manual document number X31B B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13706 WinCE Drivers Save the new configuration as MODEO H in x wince platform cepc drivers display S 1D 13706 replacing the original configura tion file Edit the file PLATFORM REG to match the screen resolution color depth bpp ac tive display LCD CRT TV and rotation information in MODE H PLATFORM REG is located in x wince platform cepc files 1D13706 X31B E 001 04 Page 6 Epson Research and Development Vancouver Design Center For example the display driver section of PLATFORM REG should be as follows when using a 320x240 LCD panel with a color depth of 8 bpp in Swivel View 0 landscape mode Default for EPSON Di
269. Save t1 Mode Enable REG AOh bit 0 LCD Signals It is recommended to use the general purpose output pin GPO to control the LCD bias power The LCD power on sequence is activated by programming the Power Save Mode Enable bit REG AOHh bit 0 to 0 L CD Signals include FPDAT 17 0 FPSHIFT FPLINE FPFRAME and DRDY Figure 6 11 Passive TFT Power On Sequence Timing Table 6 14 Passive TFT Power On Sequence Timing Symbol Parameter Min Max Units ti LCD signals active to LCD bias active Note 1 Note 1 t2 Power Save Mode disabled to LCD signals active 0 20 ns 1 t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel connected Note For HR TFT Power On Off sequence information see Connecting to the Sharp HR TFT Panels document number X31B G 011 xx For D TFD Power On Off sequence information see Connecting to the Epson D TFD Panels document number X31B G 012 xx S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 55 Vancouver Design Center 6 3 2 Passive TFT Power Off Sequence t1 4 gt GPO Power Save Mode Enable REG AOh bit 0 t2 LCD Signals It is recommended to use the general purpose output pin GPO to control the LCD bias power The LCD power off sequence is activated by programming the P
270. T connects to DSACK1 and is a signal which is output from the S1D13706 which indicates the MC68030 must wait until data is ready read cycle or accepted write cycle on the host bus Since MC68030 accesses to the S1D13706 may occur asynchro nously to the display update it is possible that contention may occur in accessing the S1D13706 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete BS connects to AS the address strobe from the MC68030 and must be driven low when a valid address has been placed on the address bus Interfacing to the Motorola MC68030 Microprocessor 1D13706 Issue Date 01 02 23 X31B G 013 02 Page 12 Epson Research and Development Vancouver Design Center 4 MC68030 to S1D13706 Interface 4 1 Hardware Description The interface between the S1D13706 and the MC68030 requires external glue logic Address decoding logic is required to provide the chip select CS and memory register M R signals to the S1D13706 since the MC68030 does not have a chip select module SIZ1 is modified to signal the S1D13706 that 24 bit and 32 bit accesses are to converted into word byte and word word accesses respectively Misaligned operands for 24 bit and 32 bit cycles are not supported with this external circuitry for SIZ1 RD must be connected to the following logic circuitry instead of directly to SIZ1 RD SIZO amp SI
271. T Blue LUT Blue Write Data Write Data Write Data Write Data Write Data Write Data n a n a Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 09h Look Up Table Green Write Data Register LUT Green LUT Green LUT Green LUT Green LUT Green LUT Green Write Data Write Data Write Data Write Data Write Data Write Data n a n a Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 0Ah Look Up Table Red Write Data Register LUT Red LUT Red LUT Red LUT Red LUT Red LUT Red Write Data Write Data Write Data Write Data Write Data Write Data n a n a Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 These registers contain the data to be written to the blue green red components of the Look Up Table The data is stored in these registers until a write to the LUT Write Address Register REG OBh moves the data to the Look Up Table Note The LUT entries are updated only when the LUT Write Address Register REG OBh is written to 1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Page 18 Epson Research and Development Vancouver Design Center REG OBh Look Up Table Write Address Register LUT Write Address Bit 7 LUT Write Address Bit 6 LUT Write Address Bit 5 LUT Write Address Bit 4 LUT Write Address Bit 3 LUT Write Address Bit 2 LUT Write Address Bit 1 LUT Write Address Bit 0 This register forms a pointer into the Look Up Table LUT which is used to write LUT data stored in REG O8h REG 09
272. T Panels X31B G 01 1 04 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center Page 13 Table 2 2 SID13706 to LQO39Q2DSO01 Pin Mapping Continued LCD Pin LCD Pin S1D13706 Describtion Remarks No Name Pin Name p 26 BO FPDAT17 Blue data signal LSB 27 Bi FPDAT16 Blue data signal 28 B2 FPDAT15_ Blue data signal 29 B3 FPDATS8 _ Blue data signal 30 B4 FPDAT 7 Blue data signal 31 B5 FPDAT6 Blue data signal MSB E See Section 2 1 External Power 32 VSHD Digital power supply Supplies on page 8 33 DGND Vss Digital ground Ground pin of S1D13706 34 PS GPIOO Power save signal 35 LP FPLINE Data latch signal of source driver 36 DCLK FPSHIFT Data sampling clock signal 37 LBR Selection for horizontal scanning direction Connect to VSHD left right scanning 38 SPR Sampling start signal for right left scanning Right to left scanning not supported See Section 2 1 External Power 39 VSHA A Analog power supply Supplies on page 8 40 VO Standard gray scale voltage black eee Section 21 External Power Supplies on page 8 41 Vi z Standard gray scale voltage e Secon Ana Supplies on page 8 42 V2 Standard gray scale voltage See Section 2 1 External Fower Supplies on page 8 43 V3 Standard gray scale voltage See Section Fala eral Power Supplies on page 8 44 V4 Standard gray scale voltage
273. T Read Address Bit 3 LUT Read Address Bit 2 LUT Read Address Bit 1 LUT Read Address Bit 0 1D13706 X31B G 003 03 This register forms a pointer into the Look Up Table LUT which is used to read LUT data to REG OCh REG ODh and REG OEh The data is placed in REG OCh REG 0Dh and REG OEh only with the completion of a write to this register This is a write only register and returns 00h if read Note For further information on the S1D13706 LUT architecture see the D13706 Hard ware Functional Specification document number X31B A 001 xx Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 19 Vancouver Design Center 4 2 Look Up Table Organization e The Look Up Table treats the value of a pixel as an index into an array of colors or gray shades For example a pixel value of zero would point to the first LUT entry whereas a pixel value of seven would point to the eighth LUT entry e The value contained in each LUT entry represents the intensity of the given color or gray shade This intensity can range in value between 0 and OFh e The S1D13706 Look Up Table is linear This means increasing the LUT entry number results in a lighter color or gray shade For example a LUT entry of OFh in the red bank results in bright red output while a LUT entry of 05h results in dull red Table 4 1 Look Up Table Configurations
274. The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Intel StrongARM SA 1110 Microprocessor X31B G 019 02 Issue Date 02 06 26 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 INGPOdUCTION s ers oe ta he AR SE ee AR A A 7 2 Interfacing to the StrongARM SA 1110 Bus 2 2 ee eee ee ee 8 2 1 The StrongARM SA 1110 System Bus 8 2 1 1 StrongARM SA 1110 Overview 0 0 2 00202 eee ee ee 8 2 1 2 Variable Latency IO Access Overview 0 00 a 8 2 1 3 Variable Latency IO Access Cycles 0 o e eee ee ee ee 9 3 1D13706 Host Bus Interface 1 2 22 eee es 11 3 1 Host Bus Interface Pin Mapping 11 3 2 Host Bus Interface Signal Descriptions 2 2 2 42 2 12 4 StrongARM SA 1110 to S1D13706 Interface 13 4 1 Hardware Description ee 13 4 2 S1D13706 Hardware Configuration 14 4 3 StrongARM SA 1110 Register Configuration 15 4 4 Register Memory Mapping 16 SoftWare a vere ah a SAS aod 17 References us ke ie
275. V to 32V range The swing circuit is shown in Figure 2 5 Swing Power Supply for Vertical System Voltages VDDH 220p 50V C5 D1 1SS355 c8 R5 4 7K 0 1u 16V c1 0 047u 50V C6 4 7u 16V XP4601 Q1B C4 220p 50V C2 0 047u 50V C3 220p 50V Q1A XP4601 V5Y D2 R7 188355 220 VEEY 1D13706 X31B G 012 03 Figure 2 5 Swing Power Supply for Vertical System Voltages The swing power supply is controlled by the S1D13706 output signal GPIO3 FRS When GPIO3 is low transistor Q1B turns on and Q1A turns off V5Y vertical logic low potential goes to GND Transistor U1 also turns on and VCCY vertical logic high potential VCC 3 3V VOY vertical liquid crystal drive supply swings to VEEY 4 5 when GPIO3 goes low since the reference changes to VEEY from GND for this signal When GPIO3 is high transistor Q1A turns on and Q1b turns off VSY goes to the level of VEEY VCCY is now referenced to VEEY and its level goes to VEEY VCC Diode D8 forward biases and sets VOY VDDH 4 5V The following table shows the values of VSY VOY and VCCY for the high and low values of the control signal GPIO3 FRS Table 2 1 Swing Power Supply Values FRS GPIO3 FRS GPIO3 FRS Low GND High 3 3V Power Supply Potential VOY VEEY VDDH VDDH Power Supply Potential VCCY VCC VEEY VCC Power Supply Potential VOY GND VEEY Connecting to the Epson D TFD
276. View requires the Memory Clock MCLK to be at least 1 25 times the frequency of the Pixel Clock PCLK i e MCLK 2 1 25PCLK The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed The application image is written to the S1D13706 in the following sense A B C D The display is refreshed by the S1D13706 in the following sense B D A C physical memory start address A 480 A B SwivelView a 3 a o winaon display start address 2 5 Q panel origin EE 9 E lt E O C D 480 320 r T image seen by programmer image refreshed by S1D13706 image in display buffer Figure 12 1 Relationship Between The Screen Image and the Image Refreshed in 90 Swivel View 1D13706 X31B A 001 08 Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 139 Vancouver Design Center 12 2 1 Register Programming Enable 90 SwivelView Mode Set Swivel View Mode Select bits REG 71h bits 1 0 to 01 Display Start Address The display refresh circuitry starts at pixel B therefore the Main Window Display Start Address registers REG 74h REG 75h REG 76h must be programmed with the address of pixel B To calculate the value of the address of pixel B use the following formula assumes 8 bpp color depth Main Window Display Start Address bits 16 0 image address panel height x b
277. View 0 is selected the panel will be in a portrait orientation A selection of Swivel View 90 or SwivelView 270 rotates to a landscape orientation The S1D13706 provides hardware support for Swivel View in all color depths 1 2 4 8 and 16 bpp For further details on the Swivel View feature see the S1D13706 Hardware Functional Specification document number X31B A 001 xx Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 32 7 1 Registers These are the registers which control the Swivel View feature Epson Research and Development Vancouver Design Center REG 71h Special Effects Register Display Data Word Swap Display Data Byte Swap n a Sub Window Enable n a The Swivel View modes are selected using the Swivel View Mode Select Bits 1 0 The combinations of these bits provide the following rotations Table 7 1 SwivelView Enable Bits SwivelView Enable SwivelView Enable SwivelView Bit 1 Bit 0 Orientation 0 0 0 normal 0 1 90 1 0 180 1 1 270 REG 74h Main Window Display Start Address Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 75h Main Window Display Start Address Register 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 76h Main Window Display Start Address Register 2
278. W ulse Polarity Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sub Window Display Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 22h FPLINE PULSE START POSITION REGISTER 0 RW FPLINE Pulse Start Position REG 7Eh SUB WINDOW DISPLAY START ADDRESS REGISTER 2 RW Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sub Window Display Start Address Bit REG 23h FPLINE PULSE START POSITION REGISTER 1 RW 16 FPLINE Pulse Start n a n a n a n a n a n a Position REG 80h SuB WinDow LINE ADDRESS OFFSET REGISTER 0 Bit 9 Bit 8 Sub Window Line Address Offset REG 0Fh LOOK UP TABLE READ ADDRESS REGISTER LUT Read Address Bit 4 Bit 3 wo REG 24h FPFRAME PULSE WIDTH REGISTER FPFRAME Pulse Polarity Bit 2 FPFRAME Pulse Width RW Bit 1 Bit 0 56 REG 26h FPFRAME PuLsE START POSITION REGISTER 0 RW REG 10h PANEL TYPE REGISTER RW P I Dat P I Data Width P IT FPFRAME Pulse Start Position anel Data anel Data Wi R anel Type Format Solor Mono Active Panel n a yp Bit7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Select Panel Select Bit 1 Bit O Res Select Bit 1 Bit O REG 27h FPFRAME PuLsE START POSITION REGISTER 1 RW REG 11h MOD RATE REGISTER RW FPFRAME Pulse Stari n a n a n a n a n a n a Position bit 5 Bit 9 Bit 8 RW REG 28h D TFD GCP INDEX REGISTER RW REG 12h HORIZONTAL TOTAL REGISTER n a y Bit 6 Bit 5 Bit 4 Horizontal Total Bit 3 Bit 2 Bit 1 Bit 0
279. X31B G 004 04 Page 26 Table 9 1 Parts List Epson Research and Development Vancouver Design Center Pare Manufacturer Part No Item Qty Designation Part Value Description Assembly Instructions 25 1 R22 402 1 1206 1 E 96 series 26 1 R23 301 1 1206 1 E 96 series 27 1 R24 200 POT Trim POT Spectrol 635201 or equivalent 28 1 R25 0 22 1 4W 1210 5 1 4W O a TORENA Eeo equivalent 29 1 R26 470 1206 5 30 1 R27 22K 1206 5 31 3 R28 R29 R32 100K 1206 5 32 1 R30 1 2M 1206 5 33 1 R31 500K POT Trim POT Spectrol 635504 or equivalent 34 4 R34 R35 R40 R41 1K 1206 5 35 1 swi SW DIP 10 Dip Switch 10 Position 36 1 S1 SW DIP 4 DIP switch 4 position Doinot populate Do not purchase 100 pin TQFP15 surface mount Do not purchase supplied by 37 1 U1 S1D13706F00A package EPSON R amp D i 5V fixed voltage regulator Linear Technology LT1117CST 38 1 U2 LT1117CST 5 SOT 223 5 NS 74VHC04 or TI 74AHC04 39 1 U3 74AHC04 SO 14 package S0 14 package 40 1 U4 ICD2061A Wide SO 16 package Cypress ICD2061A 41 2 U6 U5 Test Socket Aeon machine socket 42 4 U7 U8 U9 U10 74HCT244 SO 20 package Maxim MAX754CSE or 43 1 U11 MAX754 16 pin narrow SO pckg MAX754ESE a 3 3V fixed volt reg M Linear Technology LT1117CST 4a h pie SECM 3 package Plastic DD 3 3 Maxim MAX749CSA or 45 1 U13 MAX749 8 pin SO pckg MAX749
280. Z1 The polarity of the WAIT signal must be selected as active high by connecting CNF5 to NIO Vpp see Table 4 1 Summary of Power On Reset Configuration Options on page 13 The diagram below shows a typical implementation of the MC68030 to S1D13706 interface Note MC68030 1D13706 A 16 0 AB 16 0 D 31 16 gt DB 15 0 p gt FC 2 0 Decode Logic CS gt M R AS gt BS DSACK1 WAIT DS gt WE1 SIZO gt WEO R W RD WR siz Do gt ros CLK gt CLKI System RESET gt RESET When connecting the S1D13706 RESET pin the system designer should be aware of all conditions that may reset the S1D13706 e g CPU reset can be asserted during wake up from power down modes or during debug states S1D13706 X31B G 013 02 Note Figure 4 1 Typical Implementation of MC68030 to SIDI13706 Interface The interface was designed using a Motorola MC68030 Integrated Development Platform IDP Interfacing to the Motorola MC68030 Microprocessor Issue Date 01 02 23 Epson Research and Development Page 13 Vancouver Design Center 4 2 S1D13706 Hardware Configuration The S1D13706 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13706 Hardware Functional Specification document number X31B A 001 xx
281. a Power 10 VEE Power supply of gate driver low level P e Power 11 VCOM z Common electrode driving signal See Becton Sle oma OWEN Supplies on page 14 12 VCOM Common electrode driving signal See Section Boh ee einer ewer Supplies on page 14 13 SPL GPIO3 Sampling start signal for left right scanning 14 RO FPDAT11 Red data signal LSB 15 R1 FPDAT10 Red data signal 16 R2 FPDAT9 Red data signal 17 R3 FPDAT2 Red data signal 18 R4 FPDAT1 Red data signal 19 R5 FPDATO Red data signal MSB 20 GO FPDAT14 Green data signal LSB 21 G1 FPDAT13 Green data signal 22 G2 FPDAT12 Green data signal 23 G3 FPDAT5 Green data signal 24 G4 FPDAT4 Green data signal 25 G5 FPDAT3 Green data signal MSB 1D13706 Connecting to the Sharp HR TFT Panels X31B G 01 1 04 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center Page 17 Table 3 1 SIDI3706 to LOO31BIDDxx Pin Mapping Continued LCD Pin LCD Pin S1D13706 Describtion Remarks No Name Pin Name P 26 BO FPDAT17 Blue data signal LSB 27 B1 FPDAT16 Blue data signal 28 B2 FPDAT15 Blue data signal 29 B3 FPDAT8 Blue data signal 30 B4 FPDAT7 _ Blue data signal 31 B5 FPDAT6 Blue data signal MSB se See Section 3 1 External Power 32 VSHD Digital power supply Supplies on page 14 33 DGND Vss Digital ground Ground pin of S1D13706 3
282. a is stored at the odd system memory address location Bus data byte swapping automatic when the S1D13706 is configured for Big Endian causes the 16 bit pixel data to be stored byte swapped in the S1D13706 display buffer During display refresh this stored data must be byte swapped again before it is sent to the display 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Page 148 14 1 2 1 2 4 8 Bpp Color Depth Epson Research and Development Vancouver Design Center For 1 2 4 8 bpp color depth byte swapping must be performed on the bus data but not the display data For 1 2 4 8 bpp color depth the Display Data Byte Swap bit REG 71h bit 6 must be set to 0 f Display pies gt Buffer D 7 0 Address 15 y 0 15 L 0 ze 0 CPU Data 06 A E da Byte Swap 22 11 System Memory Address A A 11 22 System Memory Big Endian Display Buffer Little Endian High byte lane D 15 8 data e g 11 is associated with even address Low byte lane D 7 0 data e g 22 is associated with odd address 1D13706 X31B A 001 08 Figure 14 2 Byte swapping for 1 2 4 8 Bpp Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 149 Vancouver Design Center 15 Power Save Mode A software initiated Power Save Mode is incorporated into the S1D13706 t
283. able and Lower Write Enable UWE LWE are asserted during memory write cycles for the upper and lower bytes of the 16 bit data bus They may be directly connected to the write enable inputs of a typical memory device 2 2 Chip Select Module 1D13706 X31B G 016 02 The MC68VZ328 can generate up to 8 chip select outputs which are organized into four groups A through D Each chip select group has a common base address register and address mask register allowing the base address and block size of the entire group to be set In addition each chip select within a group has its own address compare and address mask register to activate the chip select for a subset of the group s address block Each chip select may also be individ ually programmed to control an 8 or 16 bit device Lastly each chip select can either generate from 0 through 6 wait states internally or allow the memory or peripheral device to terminate the cycle externally using the standard MC68000 DTACK signal Chip select groups A and B are used to control ROM SRAM and Flash memory devices and have a block size of 128K bytes to 16M bytes Chip select AO is active immediately after reset and is a global chip select so it is typically used to control a boot EPROM device AO ceases to decode globally once its chip select registers are programmed Groups C and D are special in that they can also control DRAM interfaces These last two groups have block size of 32K bytes to 4M bytes
284. able signal for data byte 1 WE1 e For MC68K 1 this pin inputs the upper data strobe UDS For MC68K 2 this pin inputs the data strobe DS e For REDCAP2 this pin inputs the byte enable signal for the D 15 8 data byte EBO For DragonBall this pin inputs the byte enable signal for the D 15 8 data byte UWE See Table 4 9 Host Bus Interface Pin Mapping on page 30 for summary CS LI HIOVDD Chip select input See Table 4 9 Host Bus Interface Pin Mapping on page 30 for summary M R LIS HIOVDD This input pin is used to select between the display buffer and register address spaces of the S1D13706 M R is set high to access the display buffer and low to access the registers See Table 4 9 Host Bus Interface Pin Mapping on page 30 for summary Hardware Functional Specification Issue Date 01 11 13 S1D13706 X31B A 001 08 Page 24 Epson Research and Development Vancouver Design Center Table 4 3 Host Interface Pin Descriptions Pin Name Type Pin Cell 10 Voltage RESET State Description BS LIS HIOVDD This input pin has multiple functions e For Generic 1 this pin must be tied to HIO Vpp e For Generic 2 this pin must be tied to HIO Vpp e For SH 3 SH 4 this pin inputs the bus start signal BS e For MC68K 1 this pin inputs the address strobe AS e For MC68K 2 this pin inputs the ad
285. ace Timing with DTACK e g MC68EZ328 MC68VZ328 Terko t t2 lt le e AAA 13 t4 A 16 1 4 t5 gt t6 PELTA CSX 8 _ 9 UWE LWE write o t10 HA OE read t12 413 4 gt D 15 0 Hi Z Hi Z write t15 t14 D 15 0 Hi Z Hi Z Mead VALID t19 5 t17 t16 p t18 DTACK Figure 6 9 Motorola DragonBall Interface with DTACK Timing S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 51 Vancouver Design Center Table 6 12 Motorola DragonBall Interface with DTACK Timing MC68EZ328 MC68VZ328 Symbol Parameter 2 0V 3 3V 2 0V 3 3V Unit Min Max Min Max Min Max Min Max fcLko Bus Clock frequency 16 16 20 33 MHz Terko Bus Clock period 1 fcLko 1 fcLko 1 fcLko 1 fcLko ns ti Clock pulse width high 28 1 28 1 22 5 13 5 ns t2 Clock pulse width low 28 1 28 1 22 5 13 5 ns A 16 1 setup 1st CLKO when CSX 0 and either t3 eae OE co 0 0 0 0 ns t4 A 16 1 hold from CSX rising edge 0 0 0 0 ns t5a CSX asserted for MCLK BCLK 8 8 8 8 TeLko t5b CSX asserted for MCLK BCLK 2 11 11 11 11 TeLKo t5c CSX asserted for MCLK BCLK 3 13 13 13 13 Teo t5d CSX asserted for MCLK BCLK 4 17 17 17 17 Telko t6 CSX setup to CLKO rising edge 0 0 0 0 ns t7 CSX rising edg
286. age Vss IO Vop V Topr Operating Temperature 40 25 85 C Note The S1D13706 requires that Core VDD lt HIO VDD and Core VDD lt NIO VDD Table 5 3 Electrical Characteristics for VDD 3 3V typical Symbol Parameter Condition Min Typ Max Units Ipps Quiescent Current Quiescent Conditions 170 uA liz Input Leakage Current 1 1 uA loz Output Leakage Current 1 1 uA VDD min VoH High Level Output Voltage lon 6mA Type 2 Vpp 0 4 V 12mA Type 3 VDD min VoL Low Level Output Voltage lo 6mA Type 2 0 4 V 12mA Type 3 Vin High Level Input Voltage LVTTL Level Vpp max 2 0 V Vit Low Level Input Voltage LVTTL Level Vpp min 0 8 V Vx High Level Input Voltage LVTTL Schmitt 1 1 2 4 V Vr Low Level Input Voltage LVTTL Schmitt 0 6 1 8 V Vu Hysteresis Voltage LVTTL Schmitt 0 1 V Rpp Pull Down Resistance Vi Vop 20 50 120 kQ Ci Input Pin Capacitance 10 pF Co Output Pin Capacitance 10 pF Cio Bi Directional Pin Capacitance 10 pF S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 33 Vancouver Design Center 6 A C Characteristics Conditions HIO Vpp 2 0V 10 and HIO Vpp 3 3V 10 Ta 40 C to 85 C Tise and Tay for all inputs must be lt 5 nsec 10 90 C 50pF Bus MPU Interface C OpF LCD Panel Interface 6 1 Clock Timing 6 1 1 Input Clocks Clock Input Waveform PWH mI tw gt 90 Vin VIL 10 tr t
287. alid y FPDAT2 Invalid 1 84 X1 R10 X 1 G15X X Se Y 1 G639X Invalid X X FPDAT1 Invalid 1 65 Y 1 B10X 1 R16 X y C eE y i R640 invalid Y FPDATO Invalid X 1 R6 X1 G11 X 1 B16X X X L X X1 B640X Invalid Notes The duty cycle of FPSHIFT changes in order to process 16 pixels in 3 FPSHIFT rising clocks Ts Pixel clock period PCLK Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6 25 Single Color 16 Bit Panel Timing VDP Vertical Display Period REG 1Dh bits 1 0 REG 1Ch bits 7 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 19h bits 1 0 REG 18h bits 7 0 REG 1 Dh bits 1 0 REG 1Ch bits 7 0 Lines HDP Horizontal Display Period REG 1 4h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 71 Vancouver Design Center t2 Sync Timing lt ti gt FPFRAME t4 4 t3 FPLINE t5 ge DRDY MOD i Data Timing FPLINE t6 4 t8 gt t9 gt t7 t14 tii t10 4 gt 4 gt gt FPSHIFT t12 t13 FPDAT 15 0 X Figure 6 26 Single Color 16 Bit Panel A C Timing Table 6 22 Single Color 16 Bit Pane
288. alize the chip i e programs all registers and then clear the Power Save Mode Enable bit Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 150 Epson Research and Development Vancouver Design Center 16 Mechanical Data 100 pin TQFP15 surface mount package 1600 14 0 0 16 0 0 4 1 3 max 0 10 All dimensions in mm Figure 16 1 Mechanical Data 100pin TQFP15 SIDI3706F00A S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 151 Vancouver Design Center 104 pin CFLGA package 8 0015 1 00max TOP VIEW SIDE VIEW gt 00 Um T7TQICxAxr BOTTOM VIEW All dimensions in mm Figure 16 2 Mechanical Data 104pin CFLGA SIDI3706B00A Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 152 Epson Research and Development Vancouver Design Center 17 References The following documents contain additional information related to the S1D13706 Document numbers are listed in parenthesis after the document name All documents can be found at the Epson Research and Development Website at www erd epson com 1D13706 X31B A 001 08 13706CFG Configuration Utility Users Manual X31B B 001 xx 13706SHOW Demonstration Program Users Manual X31B B 002 xx 13706PLAY Diagnostic Utility Users Manual
289. alled seGetLcdOrientation It is now rec ommended to call seGetSwivelViewMode instead of seGetLcdOrientation None LANDSCAPE _ Not rotated ROTATE90 Display is rotated 90 degrees counterclockwise ROTATE180 Display is rotated 180 degrees counterclockwise ROTATE270 Display is rotated 270 degrees counterclockwise int seCheckSwivelViewClocks unsigned BitsPerPixel unsigned Rotate Description Parameters Return Value 1D13706 X31B G 003 03 This function verifies that the clocks are properly configured for the a Swivel View mode given the bits per pixel and rotation see the section titled Swivel View in the S1D13706 Hardware Functional Specification document BitsPerPixel The given color depth BitsPerPixel can be one of the following 1 2 4 8 16 Rotate The values for Rotate are LANDSCAPE display not rotated ROTATE90 display rotated 90 degrees counterclockwise ROTATE 180 display rotated 180 degrees counterclockwise ROTATE270 display rotated 270 degrees counterclockwise ERR_OK The function completed with no problems ERR_SWIVELVIEW_CLOCK The clocks are not configured correctly Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 73 Vancouver Design Center int seDelay DWORD Seconds Description Parameters Return Value This function intended for non Intel platforms delays for the specified number of seconds then returns to the calling routine On s
290. alue Epson Research and Development Vancouver Design Center Call seSetClock to set the clock rate of the programmable clock ClockSelect FreqIndex ERR_OK ERR_FAILED 10 2 3 Surface Support 1D13706 X31B G 003 03 The ICD2061A programmable clock chip supports two output clock signals ClockSelect chooses which of the two output clocks to adjust Valid ClockSelect values for CLKI or CLKI2 defined in HAL H FreqIndex is an enumerated constant and determines what the output frequency should be Valid values for FreqIndex are FREQ_ 6000 6 000 MHz FREQ_10000 10 000 MHz FREQ_14318 14 318 MHz FREQ_17734 17 734 MHz FREQ_ 20000 20 000 MHz FREQ_24000 24 000 MHz FREQ_25000 25 000 MHz FREQ_25175 25 175 MHz FREQ_28318 28 318 MHz FREQ_30000 30 000 MHz FREQ_31500 31 500 MHz FREQ_ 32000 32 000 MHz FREQ_ 33000 33 000 MHz FREQ_ 33333 33 333 MHz FREQ_ 34000 34 000 MHz FREQ_ 35000 35 000 MHz FREQ_ 36000 36 000 MHz FREQ_40000 40 000 MHz FREQ_49500 49 500 MHz FREQ_50000 50 000 MHz FREQ_56250 56 250 MHz FREQ_ 65000 65 000 MHz FREQ_30000 80 000 MHz FREQ_100000 100 000 MHz The function completed with no problems seSetClock failed because of an invalid ClockSelect or an invalid frequency index The S1D13706 HAL library depends heavily on the concept of surfaces Through surfaces the HAL tracks memory requirements of the main window and sub window Surfaces allow the HAL to permit or fail function calls which change the
291. amming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 85 Vancouver Design Center void seReadLut BYTE pRGB int Count Description Parameters Return Value seReadLut reads one or more lookup table entries and returns the result in the array pointed to by pRGB The read always begins at the first lookup table entry This routine allows reading all the lookup table elements used by the current color depth in one library call pRGB A pointer to an array of bytes large enough to hold the requested number of lookup table entries Each lookup table entry consists of three bytes the first byte will contain the red data the second the green data and the third the blue data Count The number of lookup table entries to read None int seSetMode unsigned BitsPerPixel Description IMPORTANT Parameters Return Value seSetMode changes the color depth of the display and updates the appropriate LUT Dis play memory is automatically released and then reallocated as necessary for the display resolution Note seSetMode was previously called seSetBitsPerPixel It is now recommended to call seSetMode instead of seSetBitsPerPixel In addition hardware display swapping is enabled or disabled based on the requirements described in seEnableHardwareDisplay Swapping When the LCD color depth is changed memory allocated for both the main window and sub window display buffer is fr
292. and or compiled to work with your hardware platform The program 13706CFG EXE can be used to configure 13706PLAY For further information on 13706CFG refer to the 13706CFG Users Manual document number X31B B 001 xx This software is designed to work in both embedded and personal computer PC environ ments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection 1D13706 Supported Evaluation Platforms 13706PLAY Diagnostic Utility Issue Date 01 02 23 13706PLAY supports the following S1D13706 evaluation platforms PC with an Intel 80x86 processor running Windows 9x NT M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor MC68030IDP Integrated Development Platform board revision 3 0 with a Motorola MC68030 processor SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor DSP56654ADS Applications Development System board with a Motorola REDCAP2 processor Note The 13706PLAY source code can be modified or recompiled to allow 13706PLAY
293. and power consumption Vpp voltage level the voltage level affects power consumption the higher the voltage the higher the consumption Display mode the resolution and color depth affect power consumption the higher the resolution color depth the higher the consumption Internal CLK divide internal registers allow the input clock to be divided before going to the internal logic blocks the higher the divide the lower the power consumption There is a power save mode in the S1D13706 The power consumption is affected by various system design variables e Clock states during the power save mode disabling the clocks during power save mode has substantial power savings Power Consumption S1D13706 Issue Date 01 02 23 X31B G 006 02 Page 4 1 1 Conditions Epson Research and Development Vancouver Design Center The following table gives an example of a specific environment and its effects on power consumption Table 1 1 S1D13706 Total Power Consumption in mW Power Save Mode e 1D137 All Vpp 3 3V Ratio Depth mW Active Removed mW mW 1 16 1 bpp 6 58 3 02 0 00 LCD Panel 60Hz 320x240 8 bit Single Color Format 2 1 8 2 bpp 7 76 3 02 0 00 CLKI 6 MHz CLKI2 6 MHz 1 4 4 bpp 8 80 3 02 0 00 1 2 8 bpp 10 61 3 02 0 00 LCD Panel 60Hz 320x240 4 bit Single Color CLKI 6 MHz CLKI2 6 MHz 1 2 8 bpp 11 16 3 02 0 00 LCD Panel 60Hz 320x240 4 bit Single Monochrome
294. and the processor reverts to normal bus cycles for the remaining data transfers Burst cycles are mainly intended to facilitate cache line fills from program or data memory They are normally not used for transfers to from IO peripheral devices such as the S1D13706 therefore the interfaces described in this document do not attempt to support burst cycles 2 3 Memory Controller Module 2 3 1 General Purpose Chip Select Module GPCM The General Purpose Chip Select Module GPCM is used to control memory and peripheral devices which do not require special timing or address multiplexing In addition to the chip select output it can generate active low Output Enable OE and Write Enable WE signals compatible with most memory and x86 style peripherals The MPC821 bus controller also provides a Read Write RD WR signal which is compatible with most 68K peripherals The GPCM is controlled by the values programmed into the Base Register BR and Option Register OR of the respective chip select The Option Register sets the base address the block size of the chip select and controls the following timing parameters The ACS bit field allows the chip select assertion to be delayed with respect to the address bus valid by 0 4 or Y clock cycle The CSNT bit causes chip select and WE to be negated clock cycle earlier than normal The TRLX relaxed timing bit inserts an additional one clock delay between assertion of the address bus and c
295. angle can be outlined or filled seDrawCircle seDrawMainWinCircle seDrawSubWinCircle Draws a circle of given radius and color at the specified center point seDrawEllipse seDrawMainWinEllipse seDrawSubWinEllipse seGetLinearDisplayAddress Draws an ellipse centered on a given point with the specified horizontal and vertical radius Returns the linear address of the start of physical display memory seGetLinearRegAddress Returns the linear address of the start of S1D13706 control registers 1D13706 X31B G 003 03 Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 65 Vancouver Design Center 10 2 Initialization Initialization functions are normally the first functions in the HAL library that an appli cation calls These routines return information about the controller and prepare the HAL library for use int seRegisterDevice const LPHAL_STRUC IpHallnfo Description Parameters Return Value This function registers the S1D13706 device parameters with the HAL library The device parameters include such items as address range register values desired frame rate etc These parameters are stored in the HAL_STRUCT structure pointed to by IpHalInfo Additionally this routine allocates system memory as address space for accessing registers and the display buffer IpHalInfo A pointer to a HAL_STRUCT structure This structure must be filled with appropriate
296. any information to the WinCE registry If however you support more that one display mode you should create registry values see below that will establish the initial display mode If your display driver contains multiple mode tables and if you do not add any registry values the display driver will default to the first mode table in your list To select which display mode the display driver should use upon boot add the following lines to your PLATFORM REG file HKEY_LOCAL_MACHINE Drivers Display S 1D13706 Width dword 140 Height dword FO Bpp dword 8 Windows CE 3 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 13 Vancouver Design Center Rotation dword 0 RefreshRate dword 3C Flags dword 1 Note that all dword values are in hexadecimal therefore 140h 320 FOh 240 and 3Ch 60 The value for Flags should be 1 LCD When the display driver starts it will read these values in the registry and attempt to match a mode table against them All values must be present and valid for a match to occur otherwise the display driver will default to the first mode table in your list A WinCE desktop application or control panel applet can change these registry values and the display driver will select a different mode upon warmboot This allows the display driver to support different display configurations and or orientations An example appli cation that contr
297. arch and Development Page 69 Vancouver Design Center Sync Timing ti 2 FPFRAME l 4 gt t3 gt FPLINE y MaS DRDY MOD Data Timing FPLINE t6 te t9 t7 t14 t11 t10 4 gt gt FPSHIFT t12 t13 1a FPDAT 7 0 1 2 X Figure 6 24 Single Color 8 Bit Panel A C Timing Format 2 Table 6 21 Single Color 8 Bit Panel A C Timing Format 2 Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 14 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 2 Ts t9 FPSHIFT period 2 Ts t10 FPSHIFT pulse width low 1 Ts t11 FPSHIFT pulse width high 1 Ts t12 FPDAT 7 0 setup to FPSHIFT falling edge 1 Ts t13 FPDAT 7 0 hold to FPSHIFT falling edge 1 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 Umin HPS t4min 3 t2min t8min HPS t4min 4 tBmin HT 5 t4min HPW 6 min HPS 1 7 t6min HPS HDP HDPS 1 if negative add t3 min 8 t14min HDPS HPS 4 nin if negative add t3min Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 70 Epson Research and Development Vancouver Design Center 6 4 7 Single Color 16 Bit Panel Timing
298. are from 1 to 256 Return Value None Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 80 Epson Research and Development Vancouver Design Center 10 2 4 Register Access The Register Access functions provide a convenient method of accessing the control registers of the S1D13706 controller using byte word or dword widths To reduce the overhead of the function call as much as possible two steps were taken To gain maximum efficiency on all compilers and platforms byte and word size argu ments are passed between the application and the HAL as unsigned integers This typi cally allows a compiler to produce more efficient code for the platform Index alignment for word and dword accesses is not tested On non Intel platforms attempting to access a word or dword on a non aligned boundary may result in a processor trap It is the responsibility of the caller to ensure that the requested index offset is correctly aligned for the target platform The word and dword register functions will swap bytes if the endian of the host CPU differs from the S1D13706 the S1D13706 is little endian unsigned seReadRegByte DWORD Index Description This routine reads the register specified by Index and returns the value Parameters Index Offset in bytes to the register to read Return Value The least significant byte of the return value is the byte read from the register unsigned seReadRegWord DWORD Index Desc
299. arkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MC68VZ328 Processor e Motorola Design Line 800 521 6274 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Local Motorola sales office or authorized distributor 1D13706 X31B G 016 02 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 01 02 26 EPSON 1D13706 Embedded Memory LCD Controller Integrating the CFLGA 104 pin Chip Scale Package Document Number X31B G 018 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or In
300. art Address register REG 7Ch is set to 8Eh REG 7Dh is set to 25h and REG 7Eh is set to 00h Determine the sub window line address offset number of dwords per line image width 32 bpp Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 53 Vancouver Design Center 120 32 4 15 OFh Program the Sub window Line Address Offset register REG 80h is set to OFh and REG 8 1h is set to 00h 7 Determine the value for the sub window X and Y start and end position registers Let the top left corner of the sub window be x1 y1 and let x2 x1 width y2 yl height The X position registers set the vertical coordinates of the sub window top right and bottom left corner Program the X Start Position registers y1 Program the X End Position registers y2 1 The Y position registers set the horizontal coordinates of the sub window top right and bottom left corner Program the Y Start Position registers panel height x2 32 bpp Program the Y End Position registers panel height x1 32 bpp 1 X Start Position registers 80 50h Y Start Position registers 240 64 120 32 4 07h X End Position registers 80 160 1 239 EFh Y End Position registers 240 64 32 4 1 2 15h Program the Sub window X Start Position register REG 84h is set to 50h and REG 85h is set to 00h Program the Sub window Y Start Posit
301. ary The following table details the connections between the pins and signals of the MPC821 and the S1D13706 Table 4 1 List of Connections from MPC821ADS to S1D13706 MPC821 Signal Name MPC821ADS Connector and Pin Name 1D13706 Signal Name Vcc P6 A1 P6 B1 COREVDD HIOVDD NIOVDD A15 P6 D20 A16 A16 P6 B24 A15 A17 P6 C24 A14 A18 P6 D23 A13 A19 P6 D22 A12 A20 P6 D19 A11 A21 P6 A19 A10 A22 P6 D28 A9 A23 P6 A28 A8 A24 P6 C27 A7 A25 P6 A26 A6 A26 P6 C26 AS A27 P6 A25 A4 A28 P6 D26 A3 A29 P6 B25 A2 A30 P6 B19 A1 A31 P6 D17 AO DO P12 A9 D15 D1 P12 C9 D14 D2 P12 D9 D13 D3 P12 A8 D12 D4 P12 B8 D11 D5 P12 D8 D10 D6 P12 B7 D9 D7 P12 C7 D8 D8 P12 A15 D7 D9 P12 C15 D6 D10 P12 D15 D5 Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 23 Epson Research and Development Vancouver Design Center Page 17 Table 4 1 List of Connections from MPC8214DS to S1D13706 Continued MPC821 Signal Name MPC821ADS Connector and Pin Name 1D13706 Signal Name D11 P12 A14 D4 D12 P12 B14 D3 D13 P12 D14 D2 D14 P12 B13 D1 D15 P12 C13 DO SRESET P9 D15 RESET SYSCLK P9 C2 CLKI CS4 P6 D13 CS TA P6 B6 to inverter enabled by CS WAIT WEO P6 B15 WE1 WE1 P6 A14 WE0 OE P6 B16 RD WR RD P12 A1 P12 B1 P12 A2 P12 B2 GND P12 A3 P12 B3 P12 A4 P1
302. ation Issue Date 01 11 13 Epson Research and Development Page 25 Vancouver Design Center Table 4 3 Host Interface Pin Descriptions 3 IO RESET aaa Pin Name Type Pin Cell Voltage State Description During a data transfer this output pin is driven active to force the system to insert wait states It is driven inactive to indicate the completion of a data transfer WAIT is released to the high impedance state after the data transfer is complete Its active polarity is configurable See Table 4 8 Summary of Power On Reset Options on page 29 For Generic 1 this pin outputs the wait signal WAIT For Generic 2 this pin outputs the wait signal WAIT For SH 3 mode this pin outputs the wait request signal WAIT WAIT O 17 LB2A HIOVDD Hi Z For SH 4 mode this pin outputs the device ready signal RDY For MC68K 1 this pin outputs the data transfer acknowledge signal DTACK e For MC68K 2 this pin outputs the data transfer and size acknowledge bit 1 DSACK1 e For REDCAP2 this pin is unused Hi Z For DragonBall this pin outputs the data transfer acknowledge signal DTACK See Table 4 9 Host Bus Interface Pin Mapping on page 30 for summary RESETH 13 LIS HIOVDD 0 Active low input to set all internal registers to the default state and to force all signals to their inactive states Hardware Functional Specification 1D13706 Issue Da
303. atus 7 CNF6 Status CNF5 Status CNF4 Status CNF3 Status CNF2 Status CNF1 Status CNFO Status 6 5 4 3 2 1 0 bits 7 0 CNF 7 0 Status These read only status bits return the status of the configuration pins CNF 7 0 CNF 7 0 are latched at the rising edge of RESET 8 3 2 Clock Configuration Registers Memory Clock Configuration Register REG 04h Read Write n a MCLK Divide Select Bits 1 0 n a Reserved Y 6 5 4 3 2 1 0 bits 5 4 MCLK Divide Select Bits 1 0 These bits determine the divide used to generate the Memory Clock MCLK from the Bus Clock BCLK Table 8 2 MCLK Divide Selection MCLK Divide Select Bits BCLK to MCLK Frequency Ratio 00 1 1 01 2 1 10 3 1 11 4 1 bit O Reserved Hardware Functional Specification Issue Date 01 11 13 This bit must remain at 0 1D13706 X31B A 001 08 Page 98 Epson Research and Development Vancouver Design Center Pixel Clock Configuration Register REG 05h Read Write n a PCLK Divide Select Bits 2 0 n a PCLK Source Select Bits 1 0 7 6 5 4 3 2 1 0 bits 6 4 PCLK Divide Select Bits 1 0 These bits determine the divide used to generate the Pixel Clock PCLK from the Pixel Clock Source Table 8 3 PCLK Divide Selection PCLK Divide Select Bits PCLK Source to PCLK Frequency Ratio 000 1 1 001 2 1 010 3 1 011 4 1 1XX 8 1 bits 1
304. ay memory power is turned off instruct Windows CE to redraw all images upon power on Unfortunately it is not possible to instruct Windows CE to redraw any off screen images such as icons slider bars etc so in this case the OEM must also configure the display driver to never use off screen memory e Ensure that display memory never loses power Windows CE 3 x Display Drivers 1D13706 Issue Date 01 05 25 X31B E 006 01 Page 14 1D13706 X31B E 006 01 Epson Research and Development Vancouver Design Center Using off screen display memory significantly improves display performance For ex ample slider bars appear more smooth when using off screen memory To enable or disable the use of off screen memory edit the file x wince300 platform cepc driv ers display S 1D13706 sources In SOURCES there is a line which when uncom mented will instruct Windows CE to use off screen display memory if sufficient display memory is available CDEFINES CDEFINES DEnablePreferVmem In the file PROJECT REG under CE 3 0 there is a key called PORepaint search the Windows CE directories for PROJECT REG PORepaint is relevant when the Sus pend state is entered or exited PORepaint can be set to 0 1 or 2 as described below a PORepaint 0 This mode tells Windows CE not to save or restore display memory on sus pend or resume Since display data is not saved and not repainted this is the FASTEST mode Main display data in d
305. ayMainWinBlank and seDisplaySubWinBlank blank the display for the surface indicated in the function name Blank Call with Blank set to TRUE to blank the display Call with Blank set to FALSE to un blank the display None Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 74 Epson Research and Development Vancouver Design Center void seDisplayEnable BOOL Enable void seMainWinDisplayEnable BOOL Enable void seSubWinDisplayEnable BOOL Enable Description These functions enable or disable the selected display device seDisplayEnable enables or disables the display for the active surface seMainWinDisplayEnable enables or disables the main window display for the S1D13706 the display blank feature is used to enable or disable the main window seSubWinDisplayEnable enables or disables the sub window display Parameters Enable Call with Enable set to TRUE to enable the display device Call with Enable set to FALSE to disable the device Return Value None S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 75 Vancouver Design Center 10 2 2 Advance HAL Functions The advanced HAL functions include a level of access that most applications will never need to access int seBeginHighPriority void Description Parameters Return Value Writing and debugging software under the Windows operating system greatly si
306. be a multiple of 32 bits per pixel In Swivel View 180 these registers set the vertical coordinates y of the sub window s bottom right corner Increasing values of y move the bottom right corner downwards in steps of 1 line Program the Sub Window Y Start Position registers so that sub window Y start position registers panel height y In Swivel View 270 these registers set the horizontal coordinates x of the sub window s bottom left corner Increasing values of x move the bottom left corner towards the right in steps of 32 bits per pixel see Table 8 2 Program the Sub Window Y Start Position registers so that sub window Y start position registers x 32 bits per pixel Note x must be a multiple of 32 bits per pixel Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 44 Epson Research and Development Vancouver Design Center REG 8Ch Sub Window X End Position Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 8Dh Sub Window X End Position Register 1 n a n a n a n a n a n a Bit 9 Bit 8 1D13706 X31B G 003 03 These bits determine the X end position of the sub window in relation to the origin of the panel Due to the S1D13706 SwivelView feature the X end position may not be a horizontal position value only true in 0 and 180 Swivel View For further information on defining the value of t
307. be set as close to the maximum 50 MHz as possible The MCLK source is BCLK Specifies the divide ratio for the clock source signal The divide ratio is applied to the MCLK source to derive MCLK This divide ratio should be left at 1 1 unless the resultant MCLK is greater that 50MHz This field shows the actual MCLK frequency used by the configuration process 13706CFG Configuration Program Issue Date 01 03 29 Epson Research and Development Page 13 Vancouver Design Center PWMCLK 13706CFG Configuration Program Issue Date 01 03 29 Enable Force High Source Divide Timing Duty Cycle Contrast Voltage Pulse Enable Force High Source Divide Timing Burst Length These controls configure various PWMCLK settings The PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel When this box is checked the PWMCLK circuitry is enabled The signal PWMOUT is forced high when this box is checked PWMOUT is forced low when this box is not checked and Enable is not checked Selects the PWMCLK source Possible sources include CLKI and CLKI2 Specifies the divide ratio for the clock source signal The divide ratio is applied to the PWMCLK source to derive PWMCLK This field shows the actual PWMCLK frequency used by the configuration process Selects the number of cycles that PWMOUT is high out of 256 clock periods These controls configure various Contrast Voltage
308. bits 7 0 REG 1Dh bits 1 0 1 Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 56 Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 106 Epson Research and Development Vancouver Design Center Vertical Display Period Start Position Register 0 REG 1Eh Read Write Vertical Display Period Start Position Bits 7 0 7 6 5 4 3 2 1 0 Vertical Display Period Start Position Register 1 REG 1Fh Read Write nla Vertical Display Period Start Position Bits 9 8 7 6 5 4 3 2 1 0 bits 9 0 Vertical Display Period Start Position Bits 9 0 These bits specify the Vertical Display Period Start Position for panels in 1 line resolution For passive LCD panels these bits must be set to 00h For TFT panels VDPS is calculated using the following formula VDPS REG 1Fh bits 1 0 REG 1Eh bits 7 0 Note l This register must be programmed such that the following formula is valid VDPS VDP lt VT 2 For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 56 FPLINE Pulse Width Register REG 20h Read Write ddr FPLINE Pulse Width Bits 6 0 Polarity 7 6 5 4 3 2 1 0 bit 7 FPLINE Pulse Polarity This bit selects the polarity of the horizontal sync signal For passive panels this bit must be set to 1 For TFT panels this bit is
309. ble on www erd epson com was built using Red Hat Linux 6 1 kernel version 2 2 17 For information on building the kernel refer to the readme file at ftp ftp linuxberg com pub linux kernel README Note Before continuing with modifications for the S1D13706 you should ensure that you can build and start the Linux operating system 2 Unzip the console driver files Using a zip file utility unzip the S1D13706 archive to a temporary directory e g tmp When completed the files s1d13xxxfb c s1d13706 h Config in fbmem c fbcon cfb4 c and Makefile should be located in the temporary directory Copy the console driver files to the build directory Copy the files tmp s1d13xxxfb c and tmp s1d13706 h to the directory usr src linux drivers video Copy the remaining source files tmp Config in tmp fbmem c tmp fbcon cfb4 c and tmp Makefile into the directory usr src linux drivers video replacing the files of the same name Linux Console Driver Issue Date 01 09 19 Epson Research and Development Page 5 Vancouver Design Center If your kernel version is not 2 2 17 or you want to retain greater control of the build process then use a text editor and cut and paste the sections dealing with the Epson driver in the corresponding files of the same names 4 Modify s1d13706 h The file s1d13706 h contains the register values required to set the screen resolution color depth bpp display type active display LCD d
310. ble signal allows byte steering of read and write oper ations M R memory register selects between memory or register accesses This signal may be connected to an address line allowing system address A17 to be connected to the M R line Chip Select CS must be driven low by nCSx where x is the SA 1110 chip select used whenever the S1D13706 is accessed by the SA 1110 WE1 connects to nCAS1 the high byte enable signal from the SA 1110 which in conjunction with the low byte enable signal allows byte steering of read and write oper ations WEO connects to nWE the write enable signal from the SA 1110 and must be driven low when the SA 1110 is writing data to the S1D13706 RD connects to nOE the read enable signal from the SA 1110 and must be driven low when the SA 1110 is reading data from the S1D13706 WAIT connects to RDY and is a signal output from the S1D13706 that indicates the SA 1110 must wait until data is ready read cycle or accepted write cycle on the host bus Since SA 1110 accesses to the S1D13706 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13706 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Start BS and RD WR signals are not used for this Host Bus Interface and should be tied high connected to Vpp The RESET active low
311. called before a surface has been initial ized DWORD seGetSurfaceOffsetAddress void Description Parameters Return Value This function returns the offset from the first byte of display memory to the first byte of memory associated with the active display surface None The return value is the offset in bytes from the start of display memory to the start of the active surface An address of 0 indicates the surface starts in the first byte of display buffer memory Note This function also returns 0 if there is no memory allocated to an active surface You must ensure that memory is allocated before calling seGetSurfaceOffsetAddress Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 78 Epson Research and Development Vancouver Design Center DWORD seAllocMainWinSurface DWORD Size DWORD seAllocSubWinSurface DWORD Size Description Parameters Return Value These functions allocate display buffer memory for a surface If the surface previously had memory allocated then that memory is first released Newly allocated memory is not cleared Call seAllocMainWinSurface or seAllocSubWinSurface to allocate the requested amount of display memory for the indicated surface These functions allow an application to bypass the automatic surface allocation which occurs when functions such as seInitReg or seSetMode are called Size The size in bytes of the requested memory bl
312. ce lt lt es 10 3 1 Host Bus Interface Pin Mapping LO 3 2 Host Bus Interface Signals A da a nas oo UL 4 Toshiba TMPR3905 12 to S1D13706 Interface lt 12 4 1 Hardware Description O RR ae oh teat EZ 4 2 1D13706 Hardware Configuration sb o Je a he a a es TA 4 3 Memory Mapping and Aliasing 14 5 SoftWare a EEE hee wae A E eee eet S a ce he ee 15 References iaa a di Sy eae wee ak eae we ee ep a ae la G 16 GL DOCUMENES aras a ae ee A a A oe ee te a eh a ar 6 6 2 Document Sources 2 2 ee ee ee ee 16 Technical S pport lt og ee eee le eg A we Sek ae ee ed Me Ads 17 7 1 EPSON LCD Controllers S1D13706 2 17 7 2 Toshiba MIPS TMPR3905 12 Processor 2 1 ee ee ee ee ee ee 17 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors 1D13706 Issue Date 01 02 23 X31B G 002 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 02 Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 2 0 0 0000 ee eee 10 Table 4 1 Summary of Power On Reset Configuration Options 14 Table 4 2 CLKI to BCLK Divide Selection 0 0 0 0000 14 List of
313. cesses This signal may be connected to an address line allowing system address A17 to be connected to the M R line WEO connects to BWEO the low byte enable signal from the MCF5307 and must be driven low when the MCF5307 is writing the low byte to the S1D13706 WE1 connects to BWE1 the high byte enable signal from the MCF5307 and must be driven low when the MCF5307 is writing the high byte to the S1D13706 RD and RD WR are read enables for the low order and high order bytes respectively Both signals are driven low by OE when the Motorola MCF5307 is reading data from the S1D13706 WAIT connects to TA and is a signal which is output from the S1D13706 that indi cates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13706 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13706 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode and must be tied high to HIO Vpp Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 4 M
314. cification Issue Date 01 11 13 Page 5 1D13706 X31B A 001 08 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Vancouver Design Center List of Tables Table 4 1 CFLGA Pin Mapping 0 0 0 0 0002 eee Table 4 2 Pinout Assignments Die Form S1D13706DO0A Table 4 3 Host Interface Pin Descriptions 0000 4 Table 4 4 LCD Interface Pin Descriptions o o e Table 4 5 Clock Input Pin Descriptions o e e Table 4 6 Miscellaneous Pin Descriptions o o e e Table 4 7 Power And Ground Pin Descriptions o o e Table 4 8 Summary of Power On Reset Options ooa o o e Table 4 9 Host Bus Interface Pin Mapping o e Table 4 10 LCD Interface Pin Mapping o Table 5 1 Absolute Maximum Ratings o e e e Table 5 2 Recommended Operating Conditions o o Table 5 3 Electrical Characteristics for VDD 3 3V typical Table 6 1 Clock Input Requirements for CLKI when CLKI to BCLK divide gt 1 Table 6 2 Clock Input Requirements for CLKI when CLKI to BCLK divide 1 Table 6 3 Clock Input Requirements forCLKI2 Table 6 4 Internal Clock Requi
315. cified in the 1D 3706 Hardware Functional Specifi cation document number X31B A 001 xx If this is done unpredictable results may occur Epson Research and Development Inc does not assume liability for any damage done to the display device as a result of configuration errors 13706CFG Configuration Program Issue Date 01 03 29 EPSON 1D13706 Embedded Memory LCD Controller 13706SHOW Demonstration Program Document Number X31B B 002 03 Page 2 Epson Research and Development Vancouver Design Center Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners THIS PAGE LEFT BLANK 1D13706 13706SHOW Demonstration Program X31B B 002 03 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center 13706SHOW 13706SHOW is designed to demon
316. couver Design Center 2 1 2 Digital Analog Power Supplies The digital power supply VSHD must be connected to a 3 3V supply The analog power supply VSHA must be connected to a 5 0V supply 2 1 3 DC Gate Driver Power Supplies The gate driver high level power supply Vpp and the gate driver logic low power supply Vss have typical values of 15V and 15V respectively These power supplies can be provided by a Linear Technology high efficiency switching regulator LT1172 The two power supplies can be adjusted through their allowable ranges using the potentiometer VRI The gate driver logic high power supply Vcc is defined as Vss VSHD The typical Voc voltage of 11 7V can be supplied from Vgg using a 3 3V zener diode which provides the necessary voltage change Figure 2 2 Panel Gate Driver DC Power Supplies shows the schematic for V ss Vpp and Voc Figure 2 2 Panel Gate Driver DC Power Supplies Connecting to the Sharp HR TFT Panels 1D13706 Issue Date 01 02 23 X31B G 011 04 Page 10 Epson Research and Development Vancouver Design Center 2 1 4 AC Gate Driver Power Supplies The gate drive low level power supply Vgp is an AC power supply with a DC offset voltage offset typically 9 0V The AC component is the common electrode driving signal Vcom which has a voltage of 2 5V Vcom must be alternated every horizontal period and every vertical period The
317. croprocessor 4 4 Register Memory Mapping The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh so the S1D13706 is addressed starting at 40 0000h The S1D13706 uses two 128K byte blocks which are selected using A14 from the MPC821 A14 is connected to the S1D13706 M R pin The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block 1D13706 X31B G 009 02 Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 23 Epson Research and Development Page 19 Vancouver Design Center 4 5 MPC821 Chip Select Configuration Chip select 4 is used to control the S1D13706 The following options are selected in the base address register BR4 BA 0 16 0000 0000 0100 0000 0 set starting address of S1D13706 to 40 0000h AT 0 2 0 ignore address type bits PS 0 1 1 0 memory port size is 16 bits PARE 0 disable parity checking WP 0 disable write protect MS 0 1 0 0 select General Purpose Chip Select module to control this chip select V 1 set valid bit to enable chip select The following options were selected in the option register OR4 AM 0 16 1111 1111 1100 0000 0 mask all but upper 10 address bits S1D13706 consumes 4M byte of address space ATM 0 2 0 ignore address type bits CSNT 0 normal CS WE negation ACS 0 1 1 1 delay CS assertion by clock cycle from address l
318. ction 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals on page 13 Y 9 YSCL GPIO1 Shift clock signal See Section 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals on page 13 XINH GPIOO Thinning control signal See Section 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals on page 13 SHF Shift direction selection for shift registers Forward scanning V5Y Reverse scanning VCCY Connect to V5Y GND VSS GND Ground and power supply for liquid crystal drive Connecting to the Epson D TFD Panels Issue Date 01 02 23 1D13706 X31B G 012 03 Page 18 Epson Research and Development Vancouver Design Center 4 Power On Off Sequence The D TFD panel requires a specific sequence to power on off For further information on power sequencing the D TFD panel see the specification for each specific panel t1 tf GPO Power Save Ey Mode Enable REG AOH bit 0 t3 t4 gt gt LCD Signals AGING t5 e GPIO5 Pin IO Status Control REG ACh bit 5 3 16 t7 18 GPIO5 DD_P1 Active It is recommended that LCD power be controlled using the general output pin GPO The LCD power off sequence is activated by programming the Power Save Mode Enable bit REG AOHh bit 0 to 1 LCD Signals include FPDAT 17 0 FPSHIFT FPLINE FRFRAME DRDY
319. cts to WEO the high byte enable signal from the MPC821 and must be driven low when the MPC821 is writing the high byte to the S1D13706 RD and RD WR are read enables for the low order and high order bytes respectively Both signals are driven low by OE when the Motorola MPC821 is reading data from the S1D13706 WAIT connects to TA and is a signal which is output from the S1D13706 which indi cates the MPC821 must wait until data is ready read cycle or accepted write cycle on the host bus Since MPC821 accesses to the S1D13706 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13706 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS signal is not used in this implementation of the MPC821 interface using the Generic 1 Host Bus Interface This pin must be tied high connected to HIO Vpp Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 23 Epson Research and Development Page 15 Vancouver Design Center 4 MPC821 to S1D13706 Interface 4 1 Hardware Description The interface between the S1D13706 and the MPC821 requires no external glue logic The polarity of the WAIT signal must be selected as active high by connecting CNF5 to NIO Vpp see Table 4 2 Summary of Power On Reset Configuration Options on page 18 BS bus start
320. cument Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 02 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center Table of Contents E gt INGFODUCTION s or ws a A RA AR oe ie AR 7 2 Interfacing to the REDCAP2 2 20 cs se ee ee a we Oe ae es 8 2 1 The REDCAP2 SystemBus 2 2 8 2d MONCRVIEW a ois ta Bh oe a as Be ROE BS ds i an Gt eh Roe hy he th oe pb 2 3 Bus Transactions 3 S1D13706 Host Bus Interface es 10 3 1 Host Bus Interface Pin Mapping LO 3 2 Host Bus Interface Signals s 2 2 a ee ee 11 4 REDCAP2to S1D13706 Interface 12 4 1 Hardware Description te tasas man dear aaa ee 1 42 Hardware Connections o 13 4 3 S1D13706 Hardware Configuration 2 ee ee eee 15 4 4 Register Memory Mappi
321. current color depth Table 8 13 32 bit Address Increments for Color Depth Color Depth Pixel Increment x 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 For 90 and 270 SwivelView the X end position is incremented in 1 line increments Depending on the color depth some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels Note l These bits have no effect unless the PIP Window Enable bit is set to 1 REG 71h bit 4 2 The effect of REG 84h through REG 9 1h takes place only after REG 9 1h is written and at the next vertical non display period Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 119 Vancouver Design Center PIP Window Y End Position Register 0 REG 90h Read Write PIP Window Y End Position Bits 7 0 7 6 5 4 3 2 1 0 PIP Window Y End Position Register 1 REG 91h Read Write na PIP Window Y End Position Bits 9 8 7 6 5 4 3 2 1 0 bits 9 0 PIP Window Y End Position Bits 9 0 These bits determine the Y end position of the PIP window in relation to the origin of the panel Due to the 1D13706 SwivelView feature the Y end position may not be a vertical position value only true in 0 and 180 SwivelView For further information on defining the value of the Y End Position register see Section 13 Picture in Picture Plus PIP
322. cycle or accepted write cycle on the host bus The MC68VZ328 accesses to the S1D13706 may occur asyn chronously to the display update BS is not used for the Dragonball host bus interface and must be tied high to HIO Vpp Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 01 02 26 Epson Research and Development Page 11 Vancouver Design Center 4 MC68VZ328 to S1D13706 Interface 4 1 Hardware Description The interface between the S1D13706 and the MC68VZ328 does not requires any external glue logic Chip select module B is used to provide the S1D13706 with a chip select and A17 is used to select between memory and register accesses In this example the DTACK signal is made available for the S1D13706 Alternately the S1D13706 can guarantee a maximum cycle length that the Dragonball VZ handles by inserting software wait states see Section 4 2 2 MC68VZ328 Chip Select and Pin Configuration on page 13 A single resistor is used to speed up the rise time of the WAIT DTACK signal when terminating the bus cycle The following diagram shows a typical implementation of the MC68VZ328 to S1D13706 using the Dragonball host bus interface For further information on the Dragonball Host Bus interface and AC Timing refer to the S1D13706 Hardware Functional Specification document number X31B A 001 xx MC68VZ328 S1D13706 A 16 0 AB 16 0 D 15 0 DB 15 0 CSB1 gt C
323. d Memory Read Write Required Required Not Required Not Required Look Up Table Register F 4 Read Write Required Required Not Required Not Required Software Power Save Required Not Required Not Required Not Required LCD Output Required Required Required Not Required Note IPWMCLK is an optional clock see Section 7 1 4 PWMCLK on page 92 S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Vancouver Design Center 8 Registers Page 95 This section discusses how and where to access the S1D13706 registers It also provides detailed information about the layout and usage of each register 8 1 Register Mapping The S1D13706 registers are memory mapped When the system decodes the input pins as CS 0 and M R 0 the registers may be accessed The register space is decoded by A 16 0 8 2 Register Set The S1D13706 register set is as follows Table 8 1 S1D13706 Register Set Register REG 00h Revision Code Register Pg 96 Register REG 01h Display Buffer Size Register Pg 97 REG 02h Configuration Readback Register REG 04h Memory Clock Configuration Register 97 97 REG 05h Pixel Clock Configuration Register 98 REG 08h Look Up Table Blue Write Data Register 99 REG 09h Look Up Table Green Write Data Register 99 REG OAh Look Up Table Red Write Data Register 99 REG OBh Look Up Table Write Address Register 100 RE
324. d CLKI2 It is possible to use one clock input only e Bus clock is derived from CLKI and can be internally divided by 2 3 or 4 e Memory clock is derived from bus clock It can be internally divided by 2 3 or 4 e Pixel clock can be derived from CLKI CLKI2 bus clock or memory clock It can be internally divided by 2 3 4 or 8 2 7 Miscellaneous e Hardware Software Video Invert e Software Power Save mode e General Purpose Input Output pins are available e 100 pin TQFP15 package e 104 pin CFLGA package e Die form available Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 14 Epson Research and Development Vancouver Design Center 3 Typical System Implementation Diagrams Oscillator Generic 1 BUS HIOVDD y y x BS a 16 bit A 27 17 Decoder ____ M R FPDAT 15 0 gt D 15 0 Single FPFRAME gt FPFRAME LCD Display CSn P CSR FPLINE gt FPLINE g A 16 1 gt AB 16 1 FPSHIFT FPSHIFT D 15 0 e gt DB 15 0 DRDY g S1D13706 ae WEO gt WEO i WE1 gt WEI GPO RDO gt RD RD1 gt RD WR WAIT a WAIT BUSCLK gt CLKI RESET gt RESET ABO VSS Figure 3 1 Typical System
325. d D TFD panels as GPIOO is required in each panels LCD interface pin mapping Refer to the 1D 3706 Hardware Functional Specification document number X28B A 001 xx for details Note When configured for Sharp HR TFT or Epson D TFD panels JP1 must be set to no jumper and JP6 must be set to position 2 3 JP1 GPIOO connected GPIOO disconnected to SW1 9 E from SW1 9 Figure 3 2 Configuration Jumper JP1 Location S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 S1D13706 X31B G 004 04 Page 12 Epson Research and Development Vancouver Design Center JP2 CLKI2 Source JP2 selects the source for the CLKI2 Position 1 2 sets the CLKI2 source to MCLKOUT from the Cypress clock synthesizer default setting Position 2 3 sets the CLKI2 source to the external oscillator at U5 KI p F JP2 E MCLKOUT External Oscillator U5 Figure 3 3 Configuration Jumper JP2 Location JP3 CLKI Source JP2 selects the source for the CLKI Position 1 2 sets the CLKI2 source to VCLKOUT from the Cypress clock synthesizer default setting Position 2 3 sets the CLKI2 source to the external oscillator at U6 acest a JP3 eee B B VCLKOUT External Oscillator U6
326. d Windows CE display drivers are available for the S1D13706 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CEG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and display drivers are available from your sales support contact or Www eea epson com S1D13706 Connecting to the Sharp HR TFT Panels X31B G 011 04 Issue Date 01 02 23 Epson Research and Development Page 19 Vancouver Design Center 5 References 5 1 Documents e Sharp Electronics Corporation LQO39Q2DSO01 Specification e Sharp Electronics Corporation LQ031B1DDxx Specification Epson Research and Development Inc 1D13706 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples Document Number X31B G 003 xx 5 2 Document Sources e Sharp Electronics Corporation Website http www sharpsma com e Epson Electronics America Website http www eea epson com Connecting to the Sharp HR TFT Panels S1D13706 Issue Date 01 02 23 X31B G 011 04 Epson Research and Development Page 20 Vancouver Design Center 6 Technical Support 6 1 EPSON LCD Controllers S1D13706 Japan Seiko Epson Corporation Electronic
327. d as an output writing a 1 to this bit drives GPIOO high and writing a 0 to this bit drives GPIOO low When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIOO is configured as an input a read from this bit returns the status of GPIOO When a D TFD panel is enabled REG 10h bits 1 0 11 GPIOO outputs the XINH sig nal automatically and writing to this bit has no effect When a HR TFT panel is enabled REG 10h bits 1 0 10 GPIOO outputs the PS signal automatically and writing to this bit has no effect General Purpose IO Pins Status Control Register 1 REG ADh Read Write GPO Control n a 7 5 4 3 2 1 0 bit 7 GPO Control This bit controls the General Purpose Output pin Writing a 0 to this bit drives GPO to low Writing a 1 to this bit drives GPO to high Note Many implementations use the GPO pin to control the LCD bias power see Section 6 3 LCD Power Sequencing on page 54 Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 126 Epson Research and Development Vancouver Design Center 8 3 9 Pulse Width Modulation PWM Clock and Contrast Voltage CV Pulse Configuration Registers PWMCLK y gt PWM Clock Divider Clock Source 2 CV Pulse Divider Clock Source 2 x CV Pulse Divide Select value Divided Clock m PWM Clock Divide Select value Divided Clock PWM Clock Enab
328. d as an output pin GPIOS Pin IO Configuration When this bit 0 default GPIOS is configured as an input pin When this bit 1 GPIOS is configured as an output pin GPIO4 Pin IO Configuration When this bit 0 default GPIO4 is configured as an input pin When this bit 1 GPIO4 is configured as an output pin GPIO3 Pin IO Configuration When this bit 0 default GPIO3 is configured as an input pin When this bit 1 GPIO3 is configured as an output pin GPIO2 Pin IO Configuration When this bit 0 default GPIO2 is configured as an input pin When this bit 1 GPIO2 is configured as an output pin GPIO1 Pin IO Configuration When this bit 0 default GPIO1 is configured as an input pin When this bit 1 GPIO1 is configured as an output pin GPIOO Pin IO Configuration When this bit 0 default GPIOO is configured as an input pin When this bit 1 GPIOO is configured as an output pin General Purpose IO Pins Configuration Register 1 REG A9h Read Write GPIO Pin ala Input Enable 7 6 5 4 3 2 1 0 bit 7 GPIO Pin Input Enable This bit is used to enable the input function of the GPIO pins It must be changed to a 1 after power on reset to enable the input function of the GPIO pins default is 0 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Vancouver Design Center Page 123 Gen
329. dress offset register x 32 bits per pixel and the sub window image must be drawn right justified to this virtual width Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 61 Vancouver Design Center 9 Identifying the S1D13706 The S1D13706 can be identified by reading the value contained in the Revision Code Register REG 00h To identify the S1D13706 follow the steps below 1 Read REG OOh 2 The production version of the S1D13706 returns a value of 28h 00101000b 3 The product code is Ah 001010b based on bits 7 2 4 The revision code is Oh 00b based on bits 1 0 Programming Notes and Examples S1D13706 Issue Date 01 02 23 X31B G 003 03 Page 62 Epson Research and Development Vancouver Design Center 10 Hardware Abstraction Layer HAL The HAL is a processor independent programming library designed to help port applica tions and utilities from one SED13xx product to another Epson has provided this library as a result of developing test utilities for the SED13xx LCD controller products The HAL contains functions which are designed to be consistent between SED13xx products but as the semiconductor products evolve so must the HAL consequently there are some differences between HAL functions for different SED13xx products Note As the SED13xx line of products changes the HAL may change significantly or cease to be a useful tool Seiko Epson reserves the right to change the f
330. dress strobe AS e For REDCAP2 this pin must be tied to HIO Vpp e For DragonBall this pin must be tied to HIO Vpp See Table 4 9 Host Bus Interface Pin Mapping on page 30 for summary RD WR 12 LIS HIOVDD This input pin has multiple functions For Generic 1 this pin inputs the read command for the upper data byte RD1 e For Generic 2 this pin must be tied to HIO Vpp e For SH 3 SH 4 this pin inputs the RD WR signal The S1D13706 needs this signal for early decode of the bus cycle e For MC68K 1 this pin inputs the R W signal e For MC68K 2 this pin inputs the R W signal e For REDCAP2 this pin inputs the RW signal For DragonBall this pin must be tied to HIO Vpp See Table 4 9 Host Bus Interface Pin Mapping on page 30 for summary RD LIS HIOVDD This input pin has multiple functions For Generic 1 this pin inputs the read command for the lower data byte RDO e For Generic 2 this pin inputs the read command RD e For SH 3 SH 4 this pin inputs the read signal RD e For MC68K 1 this pin must be tied to HIO Vpp e For MC68K 2 this pin inputs the bus size bit 1 SIZ1 For REDCAP2 this pin inputs the output enable OE e For DragonBall this pin inputs the output enable OB See Table 4 9 Host Bus Interface Pin Mapping on page 30 for summary 1D13706 X31B A 001 08 Hardware Functional Specific
331. e Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a S1D13706 to Motorola MFC5307 microprocessor Table 4 1 Summary of Power On Reset Configuration Options 6 Pin CNF 2 0 S1D1370 value on this pin at the rising edge of RESET is used to configure 1 0 111 Generic 1 H us Ir GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs jian nterface Little Endian bus interface igh WAIT Active low WAIT See Table 4 2 CLKI to BCLK Divide Selection for recommended setting Ss configuration for MFC5307 host bus interface Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 recommended setting for MFC5307 host bus interface Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 23 Epson Research and Development Page 15 Vancouver Design Center 4 3 Register Memory Mapping The S1D13706 uses two 128K byte blocks which are selected using A17 from the MCF5307 A17 is connected to the S1D13706 M R pin The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block These two blocks of memory are aliased over the entire 2M byte space Note If aliasing is not desirable the upper addresses must be fully decoded 4 4 MCF5307 Ch
332. e Pin Mapping o 13 3 2 Host Bus Interface Signals 2 a eo 4 MPC821 to S1D13706 Interface es 15 4 1 Hardware Description LS Bc ds ems he Ae E AS 4 2 MPC821ADS Evaluation Board Hardware Connections 16 4 3 S1D13706 Hardware Configuration a ee eee 18 4 4 Register Memory Mapping 2 18 4 5 MPC821 Chip Select Configuration 19 4 6 TestSoftware 2 o 20 Software n an Be heed ee ER os Bs ieee Ses Gos Se hes 21 References eri ee ee ae ee ee A ee ee a AE 22 6 1 Documents 2 ica eS Be che RA A Se ER a 22 6 2 Document Sources 22 YT Technical Support sse 502024020000 RR A RA A 23 7 1 EPSON LCD CRT Controllers S1D13706 0 0 02 23 7 2 Motorola MPC821 Processor 2 ee ee ee 23 Interfacing to the Motorola MPC821 Microprocessor S1D13706 Issue Date 01 02 23 X31B G 009 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 02 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center Table 3 1 Table 4 1 Table 4 3 Table 4 2 Figure 2 1 Figure 2 2 Figure 2 3 Figure 4 1 Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 23 Page 5 List of Tables Host Bus Interface Pin Mapping oaa ee 13 List of Connecti
333. e The dword value to be written to the registers Return Value None Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 82 Epson Research and Development Vancouver Design Center 10 2 5 Memory Access The Memory Access functions provide convenient method of accessing the display memory on an S1D13706 controller using byte word or dword widths To reduce the overhead of these function calls as much as possible two steps were taken To gain maximum efficiency on all compilers and platforms byte and word size argu ments are passed between the application and the HAL as unsigned integers This typi cally allows a compiler to produce more efficient code for the platform Offset alignment for word and dword accesses is not tested On non Intel platforms attempting to access a word or dword on a non aligned boundary may result in a processor trap It is the responsibility of the caller to ensure that the requested offset is correctly aligned for the target platform These functions will not swap bytes if the endian of the host CPU differs from the S1D13706 the S1D13706 is little endian unsigned seReadDisplayByte DWORD Offset Description Reads a byte from the display buffer memory at the specified offset and returns the value Parameters Offset Offset in bytes from start of the display buffer to the byte to read Return Value The return value in the least significant byte is the byte read from di
334. e file as opened by the Open option is created containing the new configuration information 13706CFG Configuration Program 1D13706 Issue Date 01 03 29 X31B B 001 03 Page 22 Epson Research and Development Vancouver Design Center Configure Multiple After determining the desired configuration Configure Multiple allows the information to be saved into one or more executable files built with the HAL library From the Menu Bar select File then Configure Multiple to display the Configure Multiple Dialog Box This dialog box is also displayed when a file s is dragged onto the 13706CFG window Configure Multiple Ed Select files to configure Selected files 1S706bmp e88 an Add gt 13706cfg exe 13706play exe Add All gt gt 13706show exe lt Remove lt lt Remove All C Show all files Show conf files only gt ih C 4S1D13706 Cancel J Preserve physical addresses 1D13706 X31B B 001 03 The left pane lists files available for configuration the right pane lists files that have been selected for configuration Files can be selected by clicking the Add or Add All buttons double clicking any file in the left pane or by dragging the file s from Windows Explorer Selecting Show all files displays all files in the selected directory whereas selecting Show conf files only will display only files that can be configured using 13706CFG i e exe
335. e following section includes CPU interface AC Timing for both 2 0V and 3 3V The 2 0V timings are based on HIO Vpp Core Vpp 2 0V The 3 3V timings are based on HIO Vpp Core Vpp 3 3V 6 2 1 Generic 1 Interface Timing gt 13 A 16 1 i i M R t6 o p A CS lt t7 gt RDO RD1 t8 WEO WE1 t9 t10 gt ig WAIT A t11 t12 gt e gt l D 15 0 write zy a EN t15 D 15 0 read VALID S1D13706 X31B A 001 08 Figure 6 2 Generic 1 Interface Timing Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 37 Vancouver Design Center Table 6 5 Generic 1 Interface Timing 2 0V 3 3V Symbol Parameter Min Max Min Max Unit fcuk Bus Clock frequency 20 50 MHz Tex Bus Clock period 1 foLk YcLk ns t1 Clock pulse width high 22 5 9 ns t2 Clock pulse width low 22 5 9 ns 3 A 16 1 M R setup to first CLK rising edge where CS 0 and 4 4 s either RDO RD1 0 or WEO WE1 0 A 16 1 M R hold from either RDO RD1 or WEO WE1 t4 ie 0 0 ns rising edge t5 CS setup to CLK rising edge 0 1 ns t6 CS hold from either RDO RD1 or WEO WE1 rising edge 0 0 ns t7a RDO RD1 WEO WE1 asserted for MCLK BCLK 8 5 8 5 ToLk t7b RDO RD1 WEO WE1 asserted for MCLK BCLK
336. e new hardware as a new PCI Device and bring up the FOUND NEW HARDWARE dialog box Click NEXT The New Hardware Wizard will bring up the dialog box to search for a suitable driver Click NEXT When Windows does not find the driver it will allow you to specify the location of it Type the driver location or select BROWSE to find it Click NEXT Windows 2000 will open the installation file and show the option EPSON PCI Bridge Card Select this file and click OPEN Windows then shows the path to the file Click OK 10 Click NEXT 11 Click FINISH All ISA Bus Evaluation Cards X00A E 003 04 1 2 Install the evaluation board in the computer and boot the computer Go to the CONTROL PANEL and select ADD REMOVE HARDWARE click NEXT Select ADD TROUBLESHOOT A DEVICE and click NEXT Windows 2000 will attempt to detect any new plug and play device and fail The CHOOSE HARDWARE DEVICE dialog box appears Select ADD NEW HARDWARE and click NEXT Select NO I WANT TO SELECT FROM A LIST and click NEXT Select OTHER DEVICE from the list and click NEXT Click HAVE DISK Specify the location of the driver files select the SID13XXX INF file and click OPEN Click OK S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 Epson Research and Development Page 5 Vancouver Design Center Windows 98 ME All PCI Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer
337. e steps a In the Tornado Workspace Views window click on the Builds tab b Expand the Sbpp Builds or 16bpp Builds view by clicking on the next to it The expanded view will contain the item default Right click on default and select Properties A Properties window will appear c Select the C C compiler tab to display the command switches used in the build Remove the ansi switch from the line that contains g mpentium ansi nostdinc DRW_MULTI_THREAD Refer to GNU ToolKit user s guide for details 9 Compile the VxWorks image Select the Builds tab in the Tornado Workspace Views window Right click on Sbpp files or 16bpp files and select Dependencies Click on OK to regenerate project file dependencies for All Project files Right click on Sbpp files or 16bpp files and select ReBuild All vxWorks to build VxWorks 10 Copy the VxWorks file to the diskette From a command prompt or through the Windows interface copy the file x 13706 8bpp default vxW orks or x 13706 1 6bppMefaultivxWorks to the bootable disk created in step 4 11 Start the VxWorks demo Boot the target PC with the VxWorks bootable diskette to run the UGL demo program automatically Wind River WindML v2 0 Display Drivers 1D13706 Issue Date 01 04 06 X31B E 002 03 Page 6 Epson Research and Dev
338. e this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 13706PLAY Diagnostic Utility X31B B 003 02 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center 13706PLAY 13706PLAY is a diagnostic utility allowing a user to read write to all the S1D13706 registers Look Up Tables and display buffer 13706PLAY is similar to the DOS DEBUG program commands are received from the standard input device and output is sent to the standard output device console for Intel terminal for embedded platforms This utility requires the target platform to support standard IO stdio 13706PLAY commands can be entered interactively by a user or be executed from a script file Scripting is a powerful feature which allows command sequences to be used repeatedly without re entry The 13706PLAY diagnostic utility must be configured
339. e timing parameters for the S1D13706 Generic 2 Host Bus Interface The address bus of the TMPR3905 12 PC Card interface is multiplexed and must be demul tiplexed using an advanced CMOS latch e g 74AHC373 BS bus start and RD WR are not used in this implementation and should be tied high connected to HIO Vpp A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle The following diagram demonstrates a typical implementation of the TMPR3905 12 to S1D13706 interface EN S1D13706 TMPR3905 12 HIOVop CORE Vop CARDIORD gt RDA CARDIOWR gt WEO gt M Rit CARD1CSL CARD1CSH WE1 HIO Vpop A BS A17 Lo RD WR ENDIAN System RESET RESET 7 Latch ALE E P GS A 12 0 AB 16 13 AB 12 0 D 31 24 gt DB 7 0 D 23 16 gt DB 15 8 HIOVDD pull up CARD1WAIT e WAIT DCLKOUT See text gt CLKI2 gt Glock divider gt 0 Oscillator gt CLK Note When connecting the S1D13706 RESET pin the system designer should be aware of all conditions that may reset the S1D13706 e g CPU reset can be asserted during wake up from power down modes or during debug states 1D13706 X31B G 002 02 Figure 4 1 S1D13706 to TMPR3905 12 Direct Connection Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 01 02 23
340. e to CLKO rising edge 0 0 0 0 ns t8 UWE LWE falling edge to CLKO rising edge 1 0 1 0 ns t9 UWE LWE rising edge to CSX rising edge 0 0 0 0 ns t10 OE falling edge to CLKO rising edge 1 1 1 1 ns t11 OE hold from CSX rising edge 0 0 0 0 ns u2 D 15 0 setup to 3rd CLKO when CSX 4 0 4 0 ae UWE LWE asserted write cycle see note 1 t13 D 15 0 in hold from CSX rising edge write cycle 0 0 0 0 ns t14 Falling edge of OE to D 15 0 driven read cycle 4 30 3 15 4 30 3 15 ns 15 ELO edge to D 15 0 output Hi Z 4 01 2 12 4 21 2 12 e t16 CSX falling edge to DTACK driven high 3 20 3 13 3 20 3 13 ns t17 DTACK falling edge to D 15 0 valid read cycle 0 2 0 2 ns t18 CSX high to DTACK high 5 34 3 16 5 34 3 16 ns t19 CLKO rising edge to DTACK Hi Z 5 40 1 6 5 40 1 6 ns 1 t12 is the delay from when data is placed on the bus until the data is latched into the write buffer Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 52 Epson Research and Development Vancouver Design Center 6 2 9 Motorola DragonBall Interface Timing w o DTACK e g MC68EZ328 MC68VZ328 TeLko tl t2 pl la CLKO Po AA J wee o a t3 t4 A 16 1 t5 4 gt t6 PTEN CSX ene AR _ 9 UWE LWE f write o L t10 PERSEN OE read t13 a t12 R lt gt D 15 0 Hi Z Hi Z write t15 lt t16 t14 D 15 0 Hi Z Hi Z read VA
341. e to CSX rising edge 0 0 0 0 ns t10 OE setup to CLKO rising edge 1 1 1 1 ns t11 OE hold from CSX rising edge 0 0 0 0 ns D 15 0 setup to 3rd CLKO after CSX UWE LWE t12 1 0 1 0 ns asserted write cycle see note 2 113 CSX rising edge to D 15 0 output Hi Z write 0 0 0 0 ae cycle t14 Falling edge of OE to D 15 0 driven read cycle 4 30 3 15 4 30 3 15 ns 1st CLKO rising edge after OE and CSX Pa sie Te ae ti5ba asserted low to D 15 0 valid for MCLK BCLK ZKO X SIKO UNG oa ns read cycle 1st CLKO rising edge after OE and CSX t15b asserted low to D 15 0 valid for MCLK BCLK STeiKot 8 5ToLKo STeiko B5TorkO ns 2 read cycle 1st CLKO rising edge after OE and CSX t15c asserted low to D 15 0 valid for MCLK BCLK ete quo ee E 1a Teiko ns 3 read cycle 1st CLKO rising edge after OE and CSX t15d asserted low to D 15 0 valid for MCLK BCLK 13TeLko TES TOLKO a 145TeLko ns 4 read cycle 116 CLKO rising edge to D 15 0 output Hi Z 4 21 2 12 4 2 2 12 on read cycle 1 The MC68EZ328 cannot support the MCLK BCLK 3 and MCLK BCLK 4 settings without DTACK 2 t12 is the delay from when data is placed on the bus until the data is latched into the write buffer Hardware Functional Specification Issue Date 01 11 13 1D13706 X31B A 001 08 Page 54 Epson Research and Development Vancouver Design Center 6 3 LCD Power Sequencing 6 3 1 Passive TFT Power On Sequence GPO Power
342. e value of 37 0V Figure 2 2 VEE Switching Power Supply shows a standard topology buck boost switching power supply controlled by the 1D13706 output signal GPIOS DD_P1 VDDH c1 220p 50V vec DD_P1 D gt C2 3 4 7u 16V Q1 2SJ285 D2 188388 C3 2 2u 50V PTZTE2536A Figure 2 2 VEE Switching Power Supply The circuit in Figure 2 2 VEE Switching Power Supply uses GPIOS DD_P1 a S1D13706 output that has a 200KHz 96 duty cycle signal as the switching control of the switching power supply The duty cycle of the input to the gate of Q1 is varied by the feedback of VEE through D1 This diode feedback causes an overshoot on the rising edge of GPIOS DD_P1 that is proportional to the output level of VEE This overshoot settles to a steady level after a variable time depending on how high the overshoot was This variable time causes the high speed CMOS inverter U1 to trigger at different times thereby varying the duty cycle of the control input to Q1 When Q1 turns on the inductor L1 builds up its magnetic field using current from VDDH and D2 is reversed biased When Q2 turns off current flows from L1 causing the voltage across it to reverse polarity and forward bias D2 The output capacitor C3 is charged and holds the output voltage with an acceptable output ripple when the cycle repeats Q1 turns on The output voltage is regulated by the feedback controlling the on off times o
343. earch and Development Vancouver Design Center Main Window Line Address Offset Register 0 REG 78h Read Write Main window Line Address Offset Bits 7 0 7 6 5 4 3 1 0 Main Window Line Address Offset Register 1 REG 79h Read Write a Main window Line Address Offset Bits 9 8 7 6 5 4 3 1 0 bits 9 0 Main Window Line Address Offset Bits 9 0 This register specifies the offset in DWORDS from the beginning of one display line to the beginning of the next display line in the main window Note that this is a 32 bit address increment Calculate the Line Address Offset as follows Main Window Line Address Offset bits 9 0 display width in pixels 32 bpp Note A virtual display can be created by programming this register with a value greater than the formula requires When a virtual display is created the image width is larger than the display width and the displayed image becomes a window into the larger virtual image 1D13706 X31B A 001 08 Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 115 Vancouver Design Center 8 3 6 Picture in Picture Plus PIP Registers PIP Window Display Start Address Register 0 REG 7C Read Write PIP Window Display Start Address Bits 7 0 7 6 5 4 3 2 1 0 PIP Window Display Start Address Register 1 REG 7Dh Read Write PIP Window Display Start Address Bits 15 8 7 6 5 4 3 2
344. ecimal values attach a t suffix to the value e g 100t is 100 decimal To use binary values attach a b suffix to the value e g 0111 b WD addr data Writes dword s of data to specified memory address Where addr Address data is written to data Data to be written hex Data can be a list of dwords to be repeated for the duration of the write To use decimal values attach a t suffix to the value e g 100t is 100 decimal To use binary values attach a b suffix to the value e g 0111 b WW addr data Writes word s of data to specified memory address Where addr Address data is written to data Data to be written hex Data can be a list of words to be repeated for the duration of the write To use decimal values attach a t suffix to the value e g 100t is 100 decimal To use binary values attach a b suffix to the value e g 0111 b 13706PLAY Diagnostic Utility Issue Date 01 02 23 Epson Research and Development Page 9 Vancouver Design Center X index data Writes byte data to the register at index If no data is specified reads the 8 bit byte data from the register at index Where index Index into the registers hex data Data to be written to read from register hex Data can be a list of bytes to be repeated for the duration of the write To use decimal values attach a t suffix to the value e g 100t is 100 decimal To use binary
345. ecoded Interfacing to the PC Card Bus 1D13706 Issue Date 01 02 23 X31B G 005 02 Page 14 5 Software 1D13706 X31B G 005 02 Epson Research and Development Vancouver Design Center Test utilities and Windows CE v2 11 2 12 display drivers are available for the S1D13706 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the PC Card Bus Issue Date 01 02 23 Epson Research and Development Page 15 Vancouver Design Center 6 References 6 1 Documents PC Card PCMCIA Standard March 1997 Epson Research and Development Inc 1D 3706 Hardware Functional Specification document number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx Epson Research and Development Inc 1D 3706 Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources e PC Card website http www pc card com e Epson Electronics America website http
346. econdary window or PIP window within the main display window The PIP window may be positioned anywhere within the virtual display and is controlled through the PIP window control registers REG 7Ch through REG 91h The PIP window retains the same color depth and Swivel View orientation as the main window The following diagram shows an example of a PIP window within a main window and the registers used to position it 0 SwivelView REG 85h REG 84h panel s origin PIP window x start position PIP window x end position PIP window y start position REG 89h REG 88h PIP window y end position REG 91h REG 90h main window PIP window REG 8Dh REG 8Ch Figure 13 1 Picture in Picture Plus with SwivelView disabled Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 144 Epson Research and Development Vancouver Design Center 13 2 With SwivelView Enabled 13 2 1 SwivelView 90 90 SwivelView panel s origin PIP window x start position PIP window x end position REG 85h REG 84h REG 8Dh REG 8Ch Te Ya CJ PIP window PIP window y start position REG 89h REG 88h PIP window y end position REG 91h REG 90h main window Figure 13 2 Picture in Picture Plus with SwivelView 90 enabled 13 2 2 SwivelView 180 180 SwivelView l a
347. ect Bits SwivelView Orientation 00 0 Normal 01 90 10 180 11 270 Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 113 Vancouver Design Center Main Window Display Start Address Register 0 REG 74h Read Write Main window Display Start Address Bits 7 0 7 6 5 4 3 2 1 0 Main Window Display Start Address Register 1 REG 75h Read Write Main window Display Start Address Bits 15 8 7 6 5 4 3 2 1 0 Main Window Display Start Address Register 2 REG 76h Read Write Main window Display Start ive Address Bit 16 7 6 5 4 3 2 1 0 bits 16 0 Main Window Display Start Address Bits 16 0 This register specifies the starting address in DWORDS for the LCD image in the display buffer for the main window Note that this is a double word 32 bit address An entry of 00000h into these registers represents the first double word of display memory an entry of 00001h represents the sec ond double word of the display memory and so on Calculate the Display Start Address as follows Main Window Display Start Address bits 16 0 image address 4 valid only for Swivel View 0 Note For information on setting this register for other Swivel View orientations see Section 12 Swivel View on page 138 Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 114 Epson Res
348. ectronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Page 15 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13706 X31B G 015 02 Page 16 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to 8 bit Processors X31B G 015 02 Issue Date 01 02 23 EPSON 1D13706 Embedded Memory LCD Controller Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Document Number X31B G 016 02 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center T
349. ed Mie Yak hea e eee Seok Ge ee tend a 37 Sly Concepts ds aoe 2 ho waa a A Ro RoR Aone eM ea ag Ag es a dete 237 821 JRESiSterss ua ar cy Bi EA oy ant Se i Ge Ge a el ea Se oe oe LA 8 3 Picture In Picture Plus Examples 2 2 ee ee 48 Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 4 Epson Research and Development Vancouver Design Center 8 3 1 SwivelView 0 Landscape Mode 0 000 eee ee ee 48 8 3 2 Swivel View 90 te ea en hee ah ie te A a ie a ree SS 51 8 3 3 Swivel View 180 uu des a e da dd i 54 8 314 Swivel View 270 o dr St ek ll eae ee te ee id Y 57 8 4 Limitations Sia o RA ae Stet Se 60 8 4 1 SwivelView 0 and 180 2 2 e 60 8 4 2 SwivelView 90 and 270 2 ee 60 9 Identifying the S1D13706 6 64445464 ba Oe ee sa 61 10 Hardware Abstraction Layer HAL lt lt 62 10 1 API for 13706HAL 62 10 2 Initialization A hr ae ARA DA Be Ph ot A ee 65 10 2 1 General HAL apace earch eset ay Fa ee pa ter Gk ae alge es aa RP road e ia he 68 10 2 2 Advance HAL Functions 0 2 0 0000 eee eee eee 75 10 2 3 Surface Support cavidad Hae at Ge ee Bh De aed BL 76 10 2 4 Register Access 200 sii Re be ee eb A 80 10 25 Memory Access inea ie a ee A a ee ae eee A E 82 10 2 6 Color Manipulation 2 0 0 0 0200000002000 2G 84 10 2 7 Virtual Display eee ee a ee ee Pe 87 10 28 Dra Wine vac e
350. ed for using the Epson supplied Intel32 evaluation and test programs for the S1D13xxx family of LCD controllers with Windows 9x ME The file SIDI3XXX SYS is required for using the Epson supplied Intel32 evaluation and test programs for the S1D13xxx family of LCD controllers with Windows NT 4 0 2000 The file S1D13XXX INF is the install script For updated drivers ask your Sales Representative or visit Epson Electronics America on the World Wide Web at www eea epson com Driver Requirements Video Controller S1D13xxx Display Type N A BIOS N A DOS Program No Dos Version N A Windows Program Yes Windows 9x ME NT 4 0 2000 device driver Windows DOS Box N A Windows Full Screen N A 0S 2 N A Installation Windows NT Version 4 0 All evaluation boards require the driver to be installed as follows 1 2 Install the evaluation board in the computer and boot the computer Copy the files S1D13XXX INF and S1D13XXX SYS to a directory on a local hard drive Right click your mouse on the file SID13XXX INF and select INSTALL from the menu Windows will install the device driver and ask you to restart S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 X00A E 003 04 Page 4 Windows 2000 Epson Research and Development Vancouver Design Center All PCI Bus Evaluation Cards 9 Install the evaluation board in the computer and boot the computer Windows will detect th
351. edge is asserted and the bus cycle is aborted For example a peripheral device may assert TEA if a parity error is detected or the MPC821 bus controller may assert TEA if no peripheral device responds at the addressed memory location within a bus time out period For 32 bit transfers all data lines D 0 31 are used and the two low order address lines A30 and A31 are ignored For 16 bit transfers data lines DO through D15 are used and address line A31 is ignored For 8 bit transfers data lines DO through D7 are used and all address lines A 0 31 are used Note This assumes that the Power PC core is operating in big endian mode typically the case for embedded systems 2 2 2 Burst Cycles Burst memory cycles are used to fill on chip cache memory and to carry out certain on chip DMA operations They are very similar to normal bus cycles with the following exceptions e Always 32 bit e Always attempt to transfer four 32 bit words sequentially e Always address longword aligned memory i e A30 and A31 are always 0 0 Do not increment address bits A28 and A29 between successive transfers the addressed device must increment these address bits internally 1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 02 Issue Date 01 02 23 Epson Research and Development Page 11 Vancouver Design Center If a peripheral is not capable of supporting burst cycles it can assert Burst Inhibit BI simultaneously with TA
352. edge note 6 Ts t6b FPSHIFT2 falling edge to FPLINE rising edge note 7 Ts t a FPSHIFT falling edge to FPLINE falling edge t6a t4 Ts t7b FPSHIFT2 falling edge to FPLINE falling edge t6b t4 Ts t8 FPLINE falling edge to FPSHIFT rising FPSHIFT2 falling edge t14 2 Ts t9 FPSHIFT2 FPSHIFT period 4 6 Ts t10 FPSHIFT2 FPSHIFT pulse width low 2 Ts t11 FPSHIFT2 FPSHIFT pulse width high 2 Ts t12 FPDAT 7 0 setup to FPSHIFT2 FPSHIFT falling edge 1 Ts t13 FPDAT 7 0 hold from FPSHIFT2 FPSHIFT falling edge 1 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 tl min HPS t4 min 3 t2min t8min HPS t4min 4 83min HT 5 t4min HPW 6 t6amin HPS HDP HDPS if negative add t3min 7 t6bmin HPS HDP HDPS 2 if negative add t3 min 8 tl4min HDPS HPS t4min if negative add t3min Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 68 Epson Research and Development Vancouver Design Center 6 4 6 Single Color 8 Bit Panel Timing Format 2 k VDP o gt FPFRAME TT A ioi FPLINE l Jl es eal f l l j l DRDY MOD xX le Y FPDAT 7 0 X Invalid LINE1 X LINE2 X LINES X LINE4 X XLINE239XLINE240X Invalid X LINE X LINE2
353. eed and the display buffer memory is reassigned The application must redraw the main window display and re initialize the sub window if used and redraw the sub window after calling seSetMode BitsPerPixel The new color depth BitsPerPixel can be one of the following 1 2 4 8 16 ERR_OK Function completed successfully ERR_NOT_ENOUGH_MEMORY There is insufficient free display memory for the given bits per pixel mode and display resolution ERR_ FAILED Function failed because of invalid BitsPerPixel void seUseMainWinlmageForSubWin void Description This function instructs the HAL to use the image pointed to by the main window registers as the image to be used by the sub window The sub window start address and sub win dow line address offset registers are programmed accordingly Note It is the responsibility of the caller to first free any memory used by the sub window be fore calling this function Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 86 Epson Research and Development Vancouver Design Center Parameters None Return Value None unsigned seGetBitsPerPixel void Description seGetBitsPerPixel returns the current color depth for the associated display surface Parameters None Return Value The color depth of the surface This value will be 1 2 4 8 or 16 1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Developmen
354. efined by the SwivelView mode Parameters xl The sub window x start position upper left corner yl The sub window y start position upper left corner x2 The sub window x end position lower right corner y2 The sub window y end position lower right corner Return Value None Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 70 Epson Research and Development Vancouver Design Center void seGetSubWinCoordinates DWORD x1 DWORD y1 DWORD x2 DWORD y2 Description Parameters Return Value seGetSubWinCoordinates return the upper left and lower right corners of the sub window display The coordinates are adjusted for Swivel View orientation xl A pointer to an unsigned long which will receive the sub window x start position upper left corner yl A pointer to an unsigned long which will receive the sub window y start position upper left corner x2 A pointer to an unsigned long which will receive the sub window x end position lower right corner y2 A pointer to an unsigned long which will receive the sub window y end position lower right corner None unsigned seGetBytesPerScanline void unsigned seGetMainWinBytesPerScanline void unsigned seGetSubWinBytesPerScanline void Description Parameters Return Value These functions return the number of bytes in each line of the displayed image Note that the displayed image may be larger than the physical size
355. egenerated with the correct information Use the program 13706CFG to generate the header file For information on how to use 13706CFG refer to the 13706CFG Configuration Program User Manual document number X31B B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13706 WinCE Drivers Save the new configuration as MODEO H in the wince300 platform cepc drivers display replacing the original configuration file From the Platform window click on ParameterView Tab Show the tree for MY PLATFORM Parameters by clicking on the sign at the root of the tree Expand the the WINCE300 tree and click on Hardware Specific Files then double click on PLATFORM REG Edit the file PLATFORM REG to match the screen resolution color depth and rotation information in MODE H For example the display driver section of PLATFORM REG should be as follows when using a 320x240 LCD panel with a color depth of 8 bpp and a SwivelView mode of 0 landscape Default for EPSON Display Driver 320x240 at 8 bits pixel LCD display no rotation Useful Hex Values 1024 0x400 768 0x300 640 0x280 480 0x1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display S 1D 13706 Width dword 140 Height dword FO Bpp dword 8 Windows CE 3 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 7 Vancouver Design Center Act
356. egister 126 REG ADH General Purpose IO Pins Status Control Register 1 125 REG B1h PWM Clock CV Pulse Configuration Register 128 REG B2h CV Pulse Burst Length Register 129 REG B3h PWMOUT Duty Cycle Register 129 8 3 Register Descriptions Unless specified otherwise all register bits are set to O during power on 8 3 1 Read Only Configuration Registers Revision Code Register REG 00h Read Only Product Code Bits 5 0 Revision Code Bits 1 0 7 6 5 4 3 2 1 0 Note The S1D13706 returns a value of 28h bits 7 2 Product Code These are read only bits that indicates the product code The product code is 001010 bits 1 0 Revision Code These are read only bits that indicates the revision code The revision code is 00 S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 97 Vancouver Design Center Display Buffer Size Register REG 01h Read Only Display Buffer Size Bits 7 0 7 6 5 4 3 2 1 0 bits 7 0 Display Buffer Size Bits 7 0 This is a read only register that indicates the size of the SRAM display buffer measured in 4K byte increments The S1D13706 display buffer is SOK bytes and therefore this register returns a value of 20 14h Value of this register display buffer size 4K bytes 80K bytes 4K bytes 20 14h REG 02h Configuration Readback Register Read Only CNF7 St
357. elect LCDCS is driven low The read enable RD or write enable WR signals are driven low for the appropriate cycle LCDRDY is driven low by the S1D13706 to insert wait states into the cycle The system high byte enable is driven low for 16 bit transfers and high for 8 bit transfers Figure 2 1 NEC VR4102 VR4111 Read Write Cycles shows the read and write cycles to the LCD Controller Interface TCLK f RM A UU NA ADD 25 0 VALID SHB x LCDCS WR RD D 15 0 write VALID a Hi Z O y LCDRDY Figure 2 1 NEC VR4102 VR4111 Read Write Cycles Interfacing to the NEC VR4102 VR4111 Microprocessors 1D13706 Issue Date 01 02 23 X31B G 007 02 Page 10 Epson Research and Development Vancouver Design Center 3 S1D13706 Host Bus Interface The S1D13706 directly supports multiple processors The S1D13706 implements a 16 bit Generic 2 Host Bus Interface which is most suitable for direct connection to the NEC VR4102 4111 microprocessor Generic 2 supports an external Chip Select shared Read Write Enable for high byte and individual Read Write Enable for low byte The Generic 2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 13
358. elopment Vancouver Design Center ti gt p t2 t3 FPDAT 1791 AO A A AA AAAA joc 00 7 XK KK t4 FPFRAME A O SPS t5 t6 GPIO1 f POT U U T A I tz ri gt GPIOO ec UP EZ Y ALE PU U ud een dt FN ey FPSHIFT PA E A A A UE mid le t10 t11 t12 GPIO1 el A CLS y tis t14 GPIOO a LS PS Figure 6 31 160x160 Sharp Direct HR TFT Panel Vertical Timing 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 79 Vancouver Design Center Table 6 25 160x160 Sharp Direct HR TFT Panel Vertical Timing Symbol Parameter Min Typ Max Units tl Vertical total period 203 264 Lines t2 Vertical display start position 40 Lines t3 Vertical display period 160 Lines t4 Vertical sync pulse width 2 Lines t5 FPFRAME falling edge to GPIO1 alternate timing start 5 Lines t6 GPIO1 alternate timing period 4 Lines t7 FPFRAME falling edge to GPIOO alternate timing start 40 Lines 18 GPIOO alternate timing period 162 Lines t9 GPIO1 first pulse rising edge to FPLINE rising edge 4 Ts note 1 t10 GPIO1 first pulse width 48 Ts t11 GPIO1 first pulse falling edge to second pulse rising edge 40 Ts t12 GPIO1 second pulse width 48 Ts t13 GPIOO
359. elopment Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Wind River WindML v2 0 Display Drivers X31B E 002 03 Issue Date 01 04 06 EPSON 1D13706 Embedded Memory LCD Controller Wind River UGL v1 2 Display Drivers Document Number X31B E 003 02 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Wind River UGL v1 2 Display Drivers X31B E 003 02 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center Wind River UGL v1 2 Display Drivers The Wind River UGL v1 2 display drivers for the S1D13706 Embedded Memory LCD Controller are intended as reference source code for OEMs developing for Wind River s UGL v1 2 The dri
360. emory The S1D13706 requires this block of memory to be set to 256K bytes With this configuration the S1D13706 internal registers starting address is located at physical memory location 133C_0000h and the display buffer is located at memory location 133E_0000h The NEC VR4181A must be configured through its internal registers to map the S1D13706 to the external LCD controller space The following register values must be set e Register LCDGPMD at address 0B00_032Eh must be set as follows e Bit 7 must be set to 1 to disable the internal LCD controller and enable the external LCD controller interface Disabling the internal LCD controller also maps pin SHCLK to LCDCS and pin LOCLK to MEMCS 16 e Bits 1 0 must be set to 10b to reserve 256Kbytes of memory address range 133C_0000h to 133F_FFFFh for the external LCD controller e Register GPMD2REG at address 0B00_0304h must be set as follows e Bits 9 8 GP20MD 1 0 must be set to 11 b to map pin GPIO20 to UBE e Bits 5 4 GP18MD 1 0 must be set to 01 b to map pin GPIO18 to IORDY Interfacing to the NEC VR4181A Microprocessor Issue Date 01 02 23 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and Windows CE v2 11 2 12 display drivers are available for the S1D13706 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 137
361. emory LCD Controller Connecting to the Epson D TFD Panels Document Number X31B G 012 03 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Connecting to the Epson D TFD Panels X31B G 012 03 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 introduction sas we sik oe A Bet ew A AR A AR 7 2 External Power Supplies 02 402 2 doe a he oe ee ae eee So he es 8 2 1 VDDH and VDD Horizontal and Vertical Analog Voltages 8 2 2 VEEY LCD Panel Drive Voltage for Vertical Power Supplies Basie Reference 9 2 3 VCC Horizontal Logic Power Supply sec Ld 2 4 Swing Power Supply for the Vertical Drive VOY and Logic vecY VSY Voltages 12 2 5 Level Shift and Clamp C
362. eneric 8 bit processor using the Generic 2 Host Bus Interface These pins must be tied high connected to HIO Vpp Interfacing to 8 bit Processors Issue Date 01 02 23 Epson Research and Develo Vancouver Design Center pment Page 11 4 8 Bit Processor to S1D13706 Interface 4 1 Hardware Connections The interface between the S1D13706 and an 8 bit processor requires minimal glue logic A decoder is used to generate the chip select for the S1D13706 based on where the S1D13706 is mapped into memory Alternatively if the processor supports a chip select module it can be programmed to generate a chip select for the S1D13706 without the need of an address decoder An inverter inverts AO to generate the BHE signal for the S1D13706 If the 8 bit host interface has an active high WAIT signal it must be inverted as well BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO Vpp In order to support an 8 bit processor with a 16 bit peripheral the low and high order bytes of the data bus must be connected together The following diagram shows a typical imple mentation of an 8 bit processor to S1D 13706 interface Generic 8 bit Bus S1D13706 HIO Vop RD WR BS A17 gt M R A 16 0 AB 15 0 D 7 0 j4 gt DB 7 0 gt DB 15 8 Decoder gt CS WE gt WE RD gt RD AO o gt BHE WA
363. ent number X31B A 001 xx CLKI iFreq Selects a preset clock frequency MHz for CLKI If the option is used the list of available frequencies for CLKI is displayed Where Displays a list of available frequencies for CLKI MHz iFreq Sets CLKI to an index representing a preset frequency MHz specified by iFreq iFreq is based on the table provided with the command CLKI Note The CLKI command programs preset frequencies available on the S5U13706B00C evaluation board This function is not designed for use on other evaluation platforms or prototype designs CLKI2 iFreq Selects a preset clock frequency MHz for CLKI2 If the option is used the list of available frequencies for CLKI2 is displayed Where Displays a list of available frequencies for CLKI2 MHz iFreq Sets CLKI2 to an index representing a preset frequency MHz specified by iFreq iFreq is based on the table provided with the command CLKI2 Note The CLKI2 command programs preset frequencies available on the S5U13706B00C evaluation board This function is not designed for use on other evaluation platforms or prototype designs CW word Sends a 24 bit hexadecimal value to the programmable clock Note that the programmable clock documentation uses the term word to describe the 24 bit value The use of word does not imply a 16 bit value in this case 13706PLAY Diagnostic Utility S1D13706 Issue Date 01 02 23 X31B B 003 02 Page 6
364. enter Confirm the sub window coordinates are valid The horizontal coordinates and horizontal width must be a multiple of 32 bpp 60 32 3 4 7 5 invalid 120 32 4 15 The sub window horizontal start coordinate is invalid Therefore a valid coordinate close to 60 must be chosen For example 8 x 32 4 64 Consequently the new sub window coordinates are 64 80 Determine the main window display start address The main window is typically placed at the start of display memory which is at dis play address 0 main window display start address register desired byte address panel height x bpp 8 4 1 0 240 x 4 8 4 1 29 1Dh Program the Main Window Display Start Address registers REG 74h is set to 1Dh REG 75h is set to 00h and REG 76h is set to 00h Determine the main window line address offset number of dwords per line image width 32 bpp 240 32 4 30 1Eh Program the Main Window Line Address Offset register REG 78h is set to 1Eh and REG 79h is set to 00h Determine the sub window display start address The main window image must take up 320 x 240 pixels 2 pixels per byte 9600h bytes Ifthe main window starts at address Oh then the sub window can start at 9600h sub window display start address register desired byte address sub window width x bpp 8 4 1 9600h 120 x 4 8 4 1 9614 258Eh Program the Sub window Display St
365. er Usage At the prompt type 13706bmp bmpfile1 bmpfile2 ds n ds move n noinit r90 r180 r270 v Where bmpfile1 Specifies filename of the windows format bmp image used for the main window display surface 0 bmpfile2 Specifies filename of the windows format bmp image used for the sub window display surface 1 If bmpfile2 is not specified bmpfilel is also used for the sub window ds n Selects display surfaces see Section Display Surfaces on page 5 ds Shows available display surfaces see Section Display Surfaces on page 5 move n Automatically moves the sub window for n seconds To move the sub window indefinitely set n 1 noinit Skips full register initialization Only registers used for changing the color depth bpp are updated Additionally some registers are read to determine infor mation such as display size r90 Enables SwivelView 90 mode counter clockwise hardware rotation of the LCD image by 90 degrees r180 Enables SwivelView 180 mode counter clockwise hardware rotation of the LCD image by 180 degrees 11270 Enables SwivelView 270 mode counter clockwise hardware rotation of the LCD image by 270 degrees Iv Verbose mode provides information about the displayed image n Displays the help message Note 13706BMP displays the bmpfile image s and returns to the prompt S1D13706 13706BMP Demonstration Program X31B B 004 02 Issue Date 01 02 23 Ep
366. er configuration data on the rising edge of RESET For details on configuration refer to the S1D13706 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a S1D13706 to NEC VR4102 4111 interface Table 4 1 Summary of Power On Reset Configuration Options S1D13706 value on this pin at the rising edge of RESET is used to configure 1 0 Pin Name 1 0 CNF 2 0 CNF3 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs CNF4 Big Endian bus interface CNF5 Active high WAIT CNF 7 6 see Table 4 2 CLKI to BCLK Divide Selection for recommended setting configuration for NEC VR4102 VR4111 Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 a recommended setting for NEC VR4102 VR4111 Interfacing to the NEC VR4102 VR4111 Microprocessors 1D13706 Issue Date 01 02 23 X31B G 007 02 Page 14 Epson Research and Development Vancouver Design Center 4 3 NEC VR4102 VR4111 Configuration 1D13706 X31B G 007 02 The NEC VR4102 4111 provides the internal address decoding necessary to map an external LCD controller Physical address 0A00_0000h to OAFF_FFFFh 16M bytes is reserved for an external LCD controller by the NEC VR4102 4111 The S1D13706 is a memory mapped device The S1D13706 uses two 128K byte blocks which a
367. er applications During normal operation the internal clocks are dynamically disabled when not required The S1D13706 design also includes a Power Save Mode to further save power When Power Save Mode is initiated LCD power sequencing is required to ensure the LCD bias power supply is disabled properly For further information on LCD power sequencing see Section 6 LCD Power Sequencing on page 29 For Power Save Mode AC Timing see the S D13706 Hardware Functional Specification document number X31B A 001 xx 5 1 Overview The S1D13706 includes a software initiated Power Save Mode Enabling disabling Power Save Mode is controlled using the Power Save Mode Enable bit REG AOh bit 0 While Power Save Mode is enabled the following conditions apply e LCD display is inactive e LCD interface outputs are forced low e Memory is in accessible e Registers are accessible e Look Up Table registers are accessible S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 27 Vancouver Design Center 5 2 Registers 5 2 1 Power Save Mode Enable REG A0h Power Save Configuration Register Read Write Memory VNDP Status n na na Controller nla Wa RO Power Save Status RO The Power Save Mode Enable bit initiates Power Save Mode when set to 1 Setting the bit back to 0 returns the S1D13706 back to normal mode Note Enabling disabling Po
368. er at a specific location TOOLDIR enumerates the list of files that go into the target and builds a a library file as the output of the build process To build the software for our target example type the following at the root directory of the software i e C 13706 make TARGETS SH3 BUILDS release Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 98 Epson Research and Development Vancouver Design Center 11 Sample Code Example source code demonstrating programming the S1D13706 using the HAL library is available on the internet at www eea epson com 1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 S1D13706 Register Summary REG 00h Revision CODE REGISTER RO REG 16h HORIZONTAL DISPLAY PERIOD START POSITION REGISTER 0 X31B R 001 02 REG 70h DispLay MODE REGISTER RW Bit 5 Bit 4 Product Code 001010 Bit 3 Bit 2 Revision Code 00 bit 7 bit 6 Horizontal Display Period Start Position bit 5 bit 4 bit 3 bit 2 REG 01h DISPLAY BUFFER SIZE REGISTER RW REG 17h HORIZONTAL DISPLAY PERIOD START POSITION REGISTER RW Display Buffer Size Horizontal Display Period Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Biti Bito n a n a na n a n a Start Position bit 9 bit 8 REG 02h CONFIGURATION READBACK REGISTER RO CNF7 Status CNF6 Status CNF5 Status CNF4 Status CNFS Status CNF2 Status CNF1 Status CNF
369. eral Purpose IO Pins Status Control Register 0 REG ACH Read Write n a GPIO6 Pin IO GPIO5 Pin IO GPIO4 Pin IO GPIO3 Pin IO GPIO2 Pin IO GPIO1 Pin IO GPIOO Pin IO Status Status Status Status Status Status Status 7 6 5 4 3 2 1 0 Note For information on GPIO pin mapping when HR TFT D TFD panels are selected see Table 4 10 LCD Interface Pin Mapping on page 31 bit 6 GPIO6 Pin IO Status When a D TFD panel is not selected REG 10h bits 1 0 and GPIO6 is configured as an output writing a 1 to this bit drives GPIO6 high and writing a 0 to this bit drives GPIO6 low When a D TFD panel is not selected REG 10h bits 1 0 and GPIO6 is configured as an input a read from this bit returns the status of GPIO6 When a D TFD panel is enabled REG 10h bits 1 0 11 GPIO6 outputs the YSCLD signal automatically and writing to this bit has no effect bit 5 GPIOS Pin IO Status When a D TFD panel is not selected REG 10h bits 1 0 and GPIOS is configured as an output writing a 1 to this bit drives GPIOS high and writing a 0 to this bit drives GPIOS low When a D TFD panel is not selected REG 10h bits 1 0 and GPIOS is configured as an input a read from this bit returns the status of GPIOS When a D TFD panel is enabled REG 10h bits 1 0 11 and a 1 is written to this bit the D TFD signal DD_P1 signal is enabled When a D TFD panel is enabled REG 10h bits 1 0 11 and a 0 is written to this bit the D TFD signal DD_P1 signal is forced l
370. erfacing to the TMPR3905 12 2 1 The Toshiba TMPR3905 12 System Bus 2 1 1 Overview The TMPR39XX family of processors features a high speed system bus typical of modern MIPS RISC microprocessors This section provides an overview of the operation of the CPU bus in order to establish interface requirements The TMPR3905 12 is a highly integrated controller developed for handheld products The microprocessor is based on the R3900 MIPS RISC processor core The TMPR3905 12 implements an external 26 bit address bus and a 32 bit data bus allowing it to communicate with its many peripheral units The address bus is multiplexed A 12 0 using an address latch signal ALE which controls the driving of the address onto the address bus The full 26 bit address bus A 25 0 is generated to devices not capable of receiving a multiplexed address using external latches controlled by ALE The TMPR3905 12 provides two revision 2 01 compliant PC Card slots The 16 bit PC Card slots provide a 26 bit multiplexed address and additional control signals which allow access to three 64M byte address ranges IO memory and attribute space The signal CARDREG selects memory space when high and attribute or IO space when low Memory and attribute space are accessed using the write and read enable signals WE and RD When CARDREG is low card IO space is accessed using separate write CARDIOWR and read CARDIORD control signals 2 1 2 Card Access Cycles
371. eriod HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 63 Vancouver Design Center tl t2 Sync Timing ea FPFRAME is 4 t3 gt FPLINE f Shy DRDY MOD Data Timing FPLINE UE to t8 t9 t7 t14 t11 t10 4 gt gt lt 1 FPSHIFT t12 t13 FPDAT 7 0 JE A 7 X Figure 6 18 Single Monochrome 8 Bit Panel A C Timing Table 6 18 Single Monochrome 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 4 Ts t9 FPSHIFT period 8 Ts t10 FPSHIFT pulse width low 4 Ts t11 FPSHIFT pulse width high 4 Ts t12 FPDAT 7 0 setup to FPSHIFT falling edge 4 Ts t13 FPDAT 7 0 hold to FPSHIFT falling edge 4 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 tl min HPS t4min 3 t2min t8min HPS t4min 4 tBmin HT 5 t4min HPW 6 min HPS 1 7 t6min
372. ers REG 78h is set to 1Eh and REG 79h is set to 00h Determine the sub window display start address The main window image must take up 320 x 240 pixels 2 pixels per byte 9600h bytes If the main window starts at address Oh then the sub window can start at 9600h sub window display start address register desired byte address sub window height 1 x sub window width x bpp 8 4 9600h 160 1 x 120 x 4 8 4 11985 2ED1h Program the Sub window Display Start Address registers REG 7Ch is set to D1h REG 7Dh is set to 2Eh and REG 7Eh is set to 00h Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 59 Vancouver Design Center 6 Determine the sub window line address offset number of dwords per line image width 32 bpp 120 32 4 15 OFh Program the Sub window Line Address Offset REG 80h is set to OFh and REG 81h is set to OOh 7 Determine the value for the sub window X and Y start and end position registers Let the top left corner of the sub window be x1 y1 and let x2 x1 width y2 yl height The X position registers sets the vertical coordinates of the sub window top right and bottom left corner Program the X Start Position registers panel width y2 Program the X End Position registers panel width yl 1 The Y position registers sets the horizontal coordinates of the sub window top right and bottom left cor
373. ert the following text after the line IF ODO_NODISPLAY IF CEPC_DDI_S1D13706 ddi dll FLATRELEASEDIR epson dil NK SH ENDIF b Find the section shown below and insert the lines as marked IF CEPC_DDI_S1D13706 Insert this line IF CEPC_DDI_S3VIRGE IF CEPC_DDI_CT655X IF CEPC_DDI_VGASBPP ddi dll FLATRELEASEDIRMddi_s364 dll NK SH Windows CE 2 x Display Drivers 1D13706 Issue Date 01 05 25 X31B E 001 04 Page 8 1D13706 X31B E 001 04 10 11 Epson Research and Development Vancouver Design Center ENDIF ENDIF ENDIF ENDIF Insert this line The file MODEO H located in x wince platform cepc drivers display S 1D 13706 contains the register values required to set the screen resolution color depth bpp display type active display LCD CRT TV display rotation etc Before building the display driver refer to the descriptions in the file MODEO H for the default settings of the driver If the default does not match the configuration you are building for then MODEO H will have to be regenerated with the correct informa tion Use the program 13706CFG to generate the header file For information on how to use 13706CFG refer to the 13706CFG Configuration Program User Manual document number X31B B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13706 WinCE Drivers Save the new configuration as MODEO H in x wince platform cepc d
374. erted precharged and reasserted repeatedly Figure 2 1 illustrates a typical variable latency IO access read cycle on the SA 1110 bus A 25 0 ADDRESS VALID nCS4 nOE nWE RDY D 31 0 nCAS 3 0 X DATA VALID Figure 2 1 SA 1110 Variable Latency IO Read Cycle Interfacing to the Intel StrongARM SA 1110 Microprocessor S1D13706 Issue Date 02 06 26 X31B G 019 02 Page 10 Epson Research and Development Vancouver Design Center Figure 2 2 illustrates a typical variable latency IO access write cycle on the SA 1110 bus A 25 0 i ADDRESS VALID nCS4 nWE nOE RDY D 31 0 DATA VALID nCAS 3 0 Figure 2 2 SA 1110 Variable Latency IO Write Cycle Interfacing to the Intel StrongARM SA 1110 Microprocessor 1D13706 X31B G 019 02 Issue Date 02 06 26 Epson Research and Development Page 11 Vancouver Design Center 3 S1D13706 Host Bus Interface The S1D13706 directly supports multiple processors The 1D13706 implements a 16 bit Generic 2 Host Bus Interface which is most suitable for direct connection to the SA 1110 The Generic 2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration For details on S1D13706 configuration see Section 4 2 S1D13706 Hardware Configu ratio
375. ertical coordinates of the sub window s top left and bottom right corners Program the Y Start Position registers yl Program the Y End Position registers y2 1 X Start Position registers 80 32 4 10 0Ah Y Start Position registers 60 3Ch X End Position registers 80 160 32 4 1 29 1Dh Y End Position registers 60 120 1 179 B3h Program the Sub window X Start Position register REG 84h is set to OAh and REG 85h is set to 00h Program the Sub window Y Start Position register REG 88h is set to 3Ch and REG 89h is set to 00h Program the Sub window X End Position register REG 8Ch is set to 1Dh and REG 8Dh is set to 00h Program the Sub window Y End Position register REG 90h is set to B3h and REG 91h is set to 00h Enable the sub window Program the Sub window Enable bit REG 71h bit 4 is set to 1 Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 8 3 2 SwivelView 90 Page 51 90 SwivelView sub window x end position REG 8Dh REG 8Ch Pahl va sub window main window panel s origin sub window x start position REG 85h REG 84h sub window y start position REG 89h REG 88h sub window y end position REG 91h REG 90h Figure 8 3 Picture in Picture Plus with SwivelView 90 enabled SwivelView 90 is a mode in which both the mai
376. esearch and Development Page 47 Vancouver Design Center Program the Sub Window Y End Position registers so that sub window Y end position registers panel height y 1 In Swivel View 270 these registers set the horizontal coordinates x of the sub window s top right corner Increasing values of x move the top right corner towards the right in steps of 32 bits per pixel see Table 8 4 Program the Sub Window Y End Position registers so that sub window Y end position registers x 32 bits per pixel 1 Note x must be a multiple of 32 bits per pixel Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 48 Epson Research and Development Vancouver Design Center 8 3 Picture In Picture Plus Examples 8 3 1 SwivelView 0 Landscape Mode 0 SwivelView sub window y start position panel s origin REG 89h REG 88h sub window y end position REG 91h REG 90h main window y sub window gt sub window x start position sub window x end position REG 85h REG 84h REG 8Dh REG 8Ch Figure 8 2 Picture in Picture Plus with SwivelView disabled SwivelView 0 or landscape is a mode in which both the main and sub window are non rotated The images for each window are typically placed consecutively with the main window image starting at address 0 and followed by the sub window image In addition both images must start at addresses which
377. esign Center 4 bpp gray shade The 4 bpp gray shade mode uses the green component of the first 16 LUT entries The remaining indices of the LUT are unused Table 4 4 Suggested LUT Values for 4 Bpp Gray Shade Unused entries 8 bpp gray shade When configured for 8 bpp gray shade mode the green component of all 256 LUT entries may be used However the green component alone only provides 64 intensities 6 bits 16 bpp gray shade The Look Up Table is bypassed at this color depth therefore programming the LUT is not required As with 8 bpp there are limitations to the colors which can be displayed In this mode the six bits of green are used to set the absolute intensity of the image This results in 64 gray shades Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 22 Epson Research and Development Vancouver Design Center 4 2 2 Color Modes In color display modes the number of LUT entries used is automatically selected depending on the color depth 1 bpp color When the S1D13706 is configured for 1 bpp color mode the first 2 entries in the LUT are used Each byte in the display buffer contains eight adjacent pixels Table 4 5 Suggested LUT Values for I bpp Color Index Red Green Blue 00 00 00 00 01 FC FC FC 02 FF Indicates unused entries in the LUT 2 bpp color When the S1D13706 is configured for 2 bpp color mode the first 4 entries in the
378. ess offset registers to the same value as the main win dow line address offset registers Note The Sub Window X Start Position registers Sub Window Y Start Position registers Sub Window X End Position registers and Sub Window Y End Position registers are named according to the Swivel View 0 orientation In SwivelView 180 these registers switch their functionality as described in Section 8 2 Registers Example 7 In SwivelView 180 program the main window and sub window regis ters for a 320x240 panel at 4 bpp with the sub window positioned at SwivelView 180 coordinates 80 60 with a width of 160 and a height of 120 1 Confirm the main window coordinates are valid The horizontal coordinates must be a multiple of 32 bpp 320 32 4 40 Main window horizontal coordinate is valid Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 55 Vancouver Design Center 2 Confirm the sub window coordinates are valid The horizontal coordinates and horizontal width must be a multiple of 32 bpp 80 32 4 10 160 32 4 20 Sub window horizontal coordinates and horizontal width are valid 3 Determine the main window display start address The main window is typically placed at the start of display memory which is at display address 0 main window display start address register desired byte address panel width x panel height x bpp 8 4 1 0
379. essor X31B G 019 02 Issue Date 02 06 26 Epson Research and Development Page 17 Vancouver Design Center 5 Software Test utilities and display drivers are available for the S1D13706 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and display drivers are available from your sales support contact or on the internet at www erd epson com Interfacing to the Intel StrongARM SA 1110 Microprocessor 1D13706 Issue Date 02 06 26 X31B G 019 02 Page 18 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents Intel Corporation StrongARM SA 1110 Microprocessor Advanced Developer s Manual Order Number 278240 001 Epson Research and Development Inc S1D13706 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples Document Number X31B G 003 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X31B G 004 xx 6 2 Document Sources e Intel Developers Website http developer intel com e Intel Literature contact 1 800 548 4725
380. everal evaluation platforms it was not readily apparent where to obtain an accurate source of time delays seDelay was the result of the need to delay a specified amount of time on these platforms For non Intel platforms seDelay works by calculating and counting the number of vertical non display periods in the requested delay time This implies two conditions for proper operation a The S1D13706 control registers must be configured to correct values b The display interface must be enabled not in power save mode For Intel platforms seDelay calls the C library time functions to delay the desired amount of time using the system clock Seconds The number of seconds to delay for ERR_OK Returned by all platforms at the completion of a successful delay ERR_FAILED Returned by non Intel platforms in which the power save mode is enabled void seDisplayBlank BOOL Blank void seMainWinDisplayBlank BOOL Blank void seSubWinDisplayBlank BOOL Blank Description Parameters Return Value These functions blank their respective display Blanking the display is a fast convenient means of temporarily shutting down a display device For instance updating the entire display in one write may produce a flashing or tearing effect If the display is blanked prior to performing the update the operation is perceived to be smoother and cleaner seDisplayBlank will blank the display associated with the current active surface seDispl
381. exibility allows almost any type of memory or peripheral device to be accommodated by the MPC821 In this application note the GPCM is used instead of the UPM since the GPCM has enough flexibility to accommodate the 1D 13706 and it is desirable to leave the UPM free to handle other interfacing duties such as EDO DRAM 1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 02 Issue Date 01 02 23 Epson Research and Development Page 13 Vancouver Design Center 3 S1D13706 Host Bus Interface The S1D13706 directly supports multiple processors The S1D13706 implements a 16 bit Generic 1 Host Bus Interface which is most suitable for direct connection to the Motorola MPC821 microprocessor Generic 1 supports a Chip Select and an individual Read Enable Write Enable for each byte The Generic 1 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 3 S1D13706 Hardware Configuration on page 18 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping deeb Motorola MPC821 AB 16 0 A 15 31 DB 15 0 D O 15 WE1 WEO CS CS4 M R A14 CLKI SYSCLK BS Connect to HIO Vpp RD WR OE see note RD OE see no
382. f Q1 The longer Q1 is turned on the more current is stored in L1 and the resulting polarity change when Q1 is turned off is greater Connecting to the Epson D TFD Panels 1D13706 Issue Date 01 02 23 X31B G 012 03 Page 10 Epson Research and Development Vancouver Design Center The power supply is configured to generate a voltage VEE of 34 0V This voltage is used as an input into the temperature compensation circuit shown in Figure 2 3 Temperature Compensated VEEY which generates VEEY for use by the vertical power supplies VEE 34V O R10 10K vec VDDH o R2 33K 2 R1 50K POT Q2A XP4501 R3 2 2 10K POT i 0 01u 50V R5 XP4401 XP4401 10K R4 QA 018 15K O R7 VDDH C2 0 047u 50V 390K C3 2 2u 50V Q2B XP4501 1D13706 X31B G 012 03 Figure 2 3 Temperature Compensated VEEY The brightness reference VEEY must be temperature compensated to ensure the D TFD display remains stable over a range of temperatures The compensation circuit shown in Figure 2 3 Temperature Compensated VEEY uses temperature dependent diode forward voltage drops to adjust the output level of VEEY The three serially connected diodes are connected to VDDH and grounded through resistor R10 which causes them to be forward biased At room temperature the forward voltage of each diode is approxi mately 0 7V which sets the base voltage of Q1A at 2 4V When the temperature changes the base
383. f this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola MC68030 Microprocessor X31B G 013 02 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T introduction a aero eta Bit a cara a AAA SA Sate A oaths 7 2 Motorola MC68030 Bus Interface 0 02 eee e 8 Qk SOVERVIEW gt m a A a Ps ae ke Fa ee a ee ed A ek ee ee A a Cas 8 2 2 Dynamic B S SIZE sock sk oe os Ok as we wah eA A awe a oe 8 2 3 Asynchronous Synchronous Bus Operation 3 S1D13706 Host Bus Interface a 10 3 1 Host Bus Interface Pin Mapping LO 3 2 Host Bus Interface Signals cointa A y a eee 11 4 MC68030 to S1D13706 Interface lt lt 12 4 1 Hardware Description 2 ee eee 1 4 2 S1D13706 Hardware Configuration 2 2 ee ee ee eee ee 13 4 3 Register Memory Mapping 2 13 5 Sottware a na 6 Sard Woe ale So Be Be a ee A a dot ee a ee 14 References iaa a a a GO a a eas te el ee a nea a A 15 61 DOCUMENTS sie eaat se oa is ee A ay os kar aa ee Re a eae U
384. falling edge to FPLINE rising edge 4 Ts t14 GPIOO low pulse width 24 Ts 1 Ts pixel clock period Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 80 Epson Research and Development Vancouver Design Center 6 4 11 320x240 Sharp Direct HR TFT Panel Timing e g LQ039Q2DS01 FPFRAME SPS BUNE AA T A LP FPLINE LP oie post oCseatee ne a CLK FPDAT 17 0 Dy p oX X X XD320 t7 t8 a gt GPIO3 SPL GPIO1 CLS t12 GPIOO PS t13 GPIO2 REV Figure 6 32 320x240 Sharp Direct HR TFT Panel Horizontal Timing 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 81 Vancouver Design Center Table 6 26 320x240 Sharp Direct HR TFT Panel Horizontal Timing Symbol Parameter Min Typ Max Units tt FPLINE start position 14 Ts note 1 t2 Horizontal total period 400 440 Ts 13 FPLINE width 1 Ts t4 FPSHIFT period 1 Ts t5 Data setup to FPSHIFT rising edge 0 5 Ts t6 Data hold from FPSHIFT rising edge 0 5 Ts t7 Horizontal display start position 60 Ts t8 Horizontal display period 320 Ts t9 FPLINE rising edge to GPIO3 rising edge 59 Ts t10 GPIO3 pulse wid
385. ffset Register 0 114 REG 79h Main Window Line Address Offset Register 1 114 Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 96 Epson Research and Development Vancouver Design Center Table 8 1 SIDI3706 Register Set Register Pg Register Pg REG A8h General Purpose IO Pins Configuration RegisterO 122 REG 7Ch PIP Window Display Start Address Register O 115 REG 7Dh PIP Window Display Start Address Register 1 115 REG 7Eh PIP Window Display Start Address Register 2 115 REG 80h PIP Window Line Address Offset Register 0 115 REG 81h PIP Window Line Address Offset Register 1 115 REG 84h PIP Window X Start Position Register 0 116 REG 85h PIP Window X Start Position Register 1 116 REG 88h PIP Window Y Start Position Register 0 117 REG 89h PIP Window Y Start Position Register 1 117 REG 8Ch PIP Window X End Position Register O 118 REG 8Dh PIP Window X End Position Register 1 118 REG 90h PIP Window Y End Position Register 0 119 REG 91h PIP Window Y End Position Register 1 119 A I o Miscellaneous Registers REG A0h Power Save Configuration Register 120 REG A1h Reserved 120 REG A2h Reserved 121 REG ASh Reserved 121 REG A4h Scratch Pad Register O 121 REG A5h Scratch Pad Register 1 121 REG A9h General Purpose lO Pins Configuration Register 1 122 REG ACH General Purpose lO Pins Status Control Register O 123 REG BOh PWM Clock CV Pulse Control R
386. following sections Compile Switches There are several switches specific to the S1D13706 display driver which affect the display driver The switches are added or removed from the compile options in the file SOURCES WINCEVER This option is automatically set to the numerical version of WinCE for version 2 12 or later If the environment variable WINCEOSVER is not defined then WINCEVER will default 2 11 The display driver may test against this option to support different WinCE version specific features ENABLE_CLOCK_CHIP This option is used to enable support for the ICD2061A clock generator This clock chip is used on the S5U13706B00C evaluation board The S1D13706 display drivers can program the clock chip to support the frequencies required in the MODE tables If you are not using the S5U13706B00C evaluation adapter you should disable this option EpsonMessages This debugging option enables the display of EPSON specific debug messages These debug message are sent to the serial debugging port This option should be disabled unless you are debugging the display driver as they will significantly impact the performance of the display driver DEBUG_MONITOR This option enables the use of the debug monitor The debug monitor can be invoked when the display driver is first loaded and can be used to view registers and perform a few debugging tasks The debug monitor is still under development and is untested This option should
387. g a selection other than Auto indicates that the values for CLKI or CLKI2 are known and are fixed by the system design Options for LCD frame rates are limited to ranges determined by the clock values Note Changing clock values may modify or invalidate Panel settings Confirm all settings on the Panel tab after modifying any clock settings 13706CFG Configuration Program Issue Date 01 03 29 Epson Research and Development Vancouver Design Center Page 11 The 1D13706 may use as many as two input clocks or as few as one The more clocks used the greater the flexibility of choice in display type and memory speed CLKI CLKI2 PCLK Source Divide Timing 13706CFG Configuration Program Issue Date 01 03 29 This setting determines the frequency of CLKI Select Auto to have the CLKI frequency determined automatically based on settings made on other configu ration tabs After completing the other configurations the required CLKI frequency will be displayed in blue in the Auto section If the system design requires the CLKI frequency to be fixed at a particular rate set this value by selecting a preset frequency from the drop down list or entering the desired frequency in MHz This setting determines the frequency of CLKI2 Select Auto to have the CLKI2 frequency determined automatically based on settings made on other configu ration tabs After completing the other configurations the required
388. g either PCLK or non display period values Higher frame rates correspond to smaller horizontal and vertical non display values or higher frequencies Select the desired Pixel Clock in MHz from the drop down list The range of frequencies displayed is dependent on settings selected on the Clocks tab For example If CLKI is chosen to be Auto and PCLK is sourced from CLKI on the Clocks tab then the range for Pixel Clock will range from 1 5 MHz to 80 MHz Selecting a fixed PCLK on the Clocks tab say 25 175 MHz will result in only four selections 6 293 8 392 12 587 and 25 175 MHz these frequencies represent the four possible frequencies from a fixed 25 175 MHz input clock divided by the PCLK divider These settings allow fine tuning of the TFT line pulse parameters and are only available when the selected panel type is TFT D TFD HR TFT Refer to 1D 3706 Hardware Functional Specification document number X31B A 001 xx for a complete description of the FPLINE pulse settings Start pos Specifies the delay in pixels from the start of the horizontal non display period to the leading edge of the FPLINE pulse Pulse Width Specifies the delay in pixels from the start of the horizontal non display period to the leading edge of the FPLINE pulse 13706CFG Configuration Program Issue Date 01 03 29 Epson Research and Development Page 17 Vancouver Design Center TFT FPFRAME lines These settings allow fine tuning of
389. g to dis play memory xl The X co ordinate in pixels of the upper left corner of the rectangle yl The Y co ordinate in pixels of the upper left corner of the rectangle x2 The X co ordinate in pixels of the lower right corner of the rectangle y2 The Y co ordinate in pixels of the lower right corner of the rectangle Color Specifies the color to draw the line with Color is interpreted differently at different color depths At 1 2 4 and 8 bpp display colors are derived from the lookup table values The least significant byte of Color is an index into the lookup table At 16 bpp the lookup table is bypassed and each word of display memory forms the color to display In this mode the least significant word describes the color to draw the line with in 5 6 5 RGB format SolidFill A boolean value specifying whether to fill the interior of the rectangle Set to FALSE to draw only the rectangle border Set to TRUE to instruct this routine to fill the interior of the rectangle None Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 93 Vancouver Design Center void seDrawCircle long xCenter long yCenter long Radius DWORD Color void seDrawMainWinCircle long xCenter long yCenter long Radius DWORD Color void seDrawSubWinCircle long xCenter long yCenter long Radius DWORD Color Description These routines draw a circle on the screen in the specified color The circle is centered a
390. gisters xa Exit the program q e All displayed numeric values are considered to be hexadecimal unless identified otherwise For example e 10 10h 16 decimal e 10t 10 decimal 010 b 2 decimal e Redirecting commands from a script file PC platform allows those commands to be executed as if entered by a user 1D13706 X31B B 003 02 Page 12 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 13706PLAY Diagnostic Utility X31B B 003 02 Issue Date 01 02 23 EPSON 1D13706 Embedded Memory LCD Controller 13706BMP Demonstration Program Document Number X31B B 004 02 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK
391. gned around the 100MHz VR4110 CPU core which supports the MIPS III and MIPS16 instruction sets The CPU communicates with external devices via an ISA interface While the VR4181A has an embedded LCD controller this internal controller can be disabled to provide direct support for an external LCD controller through its external ISA bus A 64 to 512K byte block of memory is assigned to the external LCD controller with a dedicated chip select signal LCDCS Word or byte accesses are controlled by the system high byte signal UBE Interfacing to the NEC VR4181A Microprocessor Issue Date 01 02 23 Epson Research and Development Page 9 Vancouver Design Center 2 1 2 LCD Memory Access Signals The S1D13706 requires an addressing range of 256K bytes When the VR4181A external LCD controller chip select signal is programmed to a window of that size the S1D13706 resides in the VR4181A physical address range of 133C 0000h to 133F FFFFh This range is part of the external ISA memory space The following signals are required to access an external LCD controller All signals obey ISA signalling rules A 16 0 is the address bus UBE is the high byte enable active low LCDCS is the chip select for the S1D13706 active low D 15 0 is the data bus MEMRD is the read command active low MEMWR is the write command active low MEMCS 16 is the acknowledge for 16 bit peripheral capability active low IORDY is the ready signal fr
392. guration 2 a a a eee A 5 DOMWAIG a CA oe ea ea Se ek Oe aS o ee eee eee 15 ROTerentes ia a ee ee EL ea ee a ew la G 16 GL DOCUMENTS strar eas ae he a ee ay oh er a Ek A O 6 2 Document Sources 2 2 ee ee ee ee 16 Technical S pport e ogee hoe ele Rog E we Sk ale eae ed eens 17 7 1 Epson LCD Controllers SI1D13706 o eee ee eT 7 2 NEC Electronics Inc 2 2 1 ee eee 17 Interfacing to the NEC VR4181A Microprocessor 1D13706 Issue Date 01 02 23 X31B G 008 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the NEC VR4181A Microprocessor X31 B G 008 02 Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 20 2 0 0000 ee eee 10 Table 4 1 Summary of Power On Reset Configuration Options 13 Table 4 2 CLKI to BCLK Divide Selection o o e 13 List of Figures Figure 4 1 Typical Implementation of VR4181A to S1D13706 Interface 12 Interfacing to the NEC VR4181A Microprocessor S1D13706 Issue Date 01 02 23 X31B G 008 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the NEC VR4181A Microprocessor X31 B G 008 02 Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction T
393. h and REG OAh The data is updated to the LUT only with the completion of a write to this register This is a write only register and returns 00h if read Not e For further information on the S1D13706 LUT architecture see the D13706 Hard ware Functional Specification document number X31B A 001 xx 4 1 2 Look Up Table Read Registers REG 0Ch Look Up Table Blue Read Data Register LUT Blue LUT Blue LUT Blue LUT Blue LUT Blue LUT Blue Read Data Read Data Read Data Read Data Read Data Read Data n a n a Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG ODh Look Up Table Green Read Data Register LUT Green LUT Green LUT Green LUT Green LUT Green LUT Green Read Data Read Data Read Data Read Data Read Data Read Data n a n a Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG OEh Look Up Table Red Read Data Register LUT Red LUT Red LUT Red LUT Red LUT Red LUT Red Read Data Read Data Read Data Read Data Read Data Read Data n a n a Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O These registers contains the data returned from the blue green red components of the Look Up Table The data is read and placed in these registers only when a write to the LUT Write Address Register REG OFh copies the data from the Look Up Table REG OFh Look Up Table Read Address Register LUT Read Address Bit 7 LUT Read Address Bit 6 LUT Read Address Bit 5 LUT Read Address Bit 4 LU
394. h and Development Vancouver Design Center 2 Interfacing to the MPC821 2 1 The MPC8XX System Bus The MPC8xx family of processors feature a high speed synchronous system bus typical of modern RISC microprocessors This section provides an overview of the operation of the CPU bus in order to establish interface requirements 2 2 MPC8XX Bus Overview The MPC8xx microprocessor family uses a synchronous address and data bus All IO is synchronous to a square wave reference clock called MCLK Master Clock This clock runs at the machine cycle speed of the CPU core typically 25 to 50 MHz Most outputs from the processor change state on the rising edge of this clock Similarly most inputs to the processor are sampled on the rising edge Note The external bus can run at one half the CPU core speed using the clock control register This is typically used when the CPU core is operated above 50 MHz The MPC821 can generate up to eight independent chip select outputs each of which may be controlled by one of two types of timing generators the General Purpose Chip Select Module GPCM or the User Programmable Machine UPM Examples are given using the GPCM It should be noted that all Power PC microprocessors including the MPC8xx family use bit notation opposite from the convention used by most other microprocessor systems Bit numbering for the MPC8xx always starts with zero as the most significant bit and incre ments in value to the least s
395. he X End Position register see Section 8 3 Picture In Picture Plus Examples on page 48 The register is also incremented differently based on the SwivelView orientation For 0 and 180 SwivelView the X end position is incremented by X pixels where X is relative to the current color depth Table 8 3 32 bit Address Increments for Color Depth Bits Per Pixel Color Depth Pixel Increment X 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 For 90 and 270 SwivelView the X end position is incremented in 1 line increments In Swivel View 0 these registers set the horizontal coordinates x of the sub windows s bottom right corner Increasing values of x move the bottom right corner towards the right in steps of 32 bits per pixel see Table 8 3 Program the Sub Window X End Position registers so that sub window X end position registers x 32 bits per pixel 1 Note x must be a multiple of 32 bits per pixel In Swivel View 90 these registers set the vertical coordinates y of the sub window s bottom left corner Increasing values of y move the bottom left corner downward in steps of 1 line Program the Sub Window X End Position registers so that sub window X end position registers y 1 Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 45 Vancouver Design Center In Swivel View 180 these registers set the horizontal coordina
396. he following line device a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy LOADCEPC EXE and HIMEM SYS to the bootable floppy disk Search for the loadCEPC utility in your Windows CE directories e Copy NK BIN to c f Boot the system from the bootable floppy disk 2 To start CEPC after booting from a hard drive a Copy LOADCEPC EXE to CA Search for the loadCEPC utility in your Windows CE directories b Edit CONFIG SYS on the hard drive to contain only the following line device c himem sys c Edit AUTOEXEC BAT on the hard drive to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy NK BIN and HIMEM SYS to c e Boot the system 1D13706 Windows CE 3 x Display Drivers X31B E 006 01 Issue Date 01 05 25 Epson Research and Development Page 11 Vancouver Design Center Configuration Compile Switches WINCEVER There are several issues to consider when configuring the display driver The issues cover debugging support register initialization values and memory allocation Each of these issues is discussed in the following sections There are several switches specific to the S1D13706 display driver which affect the display driver The switches are added or removed from the compile options in the file SOURCES This option is automatically set to the numerical version of
397. he main window image must be drawn right justified to this virtual width Similarly the sub window line address offset register requires the sub window image width to be a multiple of 32 bits per pixel If this is not the case then the sub window line address offset register must be programmed to a longer line which is a multiple of 32 bits per pixel This longer line creates a virtual image whose width is sub window line address offset register x 32 bits per pixel and the sub window image must be drawn right justified to this virtual width 8 4 2 SwivelView 90 and 270 1D13706 X31B G 003 03 In Swivel View 90 and 270 the main window line address offset register requires the panel height to be a multiple of 32 bits per pixel If this is not the case then the main window line address offset register must be programmed to a longer line which is a multiple of 32 bits per pixel This longer line creates a virtual image whose width is main window line address offset register x 32 bits per pixel and the main window image must be drawn right justified to this virtual width Similarly the sub window line address offset register requires the sub window image width to be a multiple of 32 bits per pixel If this is not the case then the sub window line address offset register must be programmed to a longer line which is a multiple of 32 bits per pixel This longer line creates a virtual image whose width is sub window line ad
398. he pin PWMOUT PWMOUT can be used to control LCD panels which support PWM control of the back light inverter S1D13706 X31B A 001 08 Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 93 Vancouver Design Center 7 2 Clock Selection The following diagram provides a logical representation of the S1D13706 internal clocks CLKI e 00 2 01 o gt BCLK 3 10 4 11 CNF 7 6 e REG 04h bits 5 4 ej 00 0 2 01 MCLK o 3 10 4 11 00 01 000 o 10 o 2 001 CLKI2 o 11 f o 3 010 gt PCLK e E 011 REG O5h bits 1 0 8 1xx 57 REG O5h bits 6 4 al gt PWMCLK y REG B1h bit 0 Figure 7 1 Clock Selection Note CNF 7 6 must be set at RESET Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 94 Epson Research and Development Vancouver Design Center 7 3 Clocks versus Functions Table 7 6 S1D13706 Internal Clock Requirements lists the internal clocks required for the following S1D13706 functions Table 7 6 SID13706 Internal Clock Requirements ancien Bus Clock Memory Clock Pixel Clock PWM Clock BCLK MCLK PCLK PWMCLK Register Read Write Required Not Required Not Required Not Require
399. heable to ensure that accesses to the S1D13706 occurs in proper order and also to ensure that the MPC821 does not attempt to cache any data read from or written to the S1D13706 or its display buffer The source code for this test routine is as follows equ 120 CS4 base register equ 124 CS4 option register equ 42 0000 address of S1D13706 display buffer qu 40 0000 address of Revision Code Register mfspr rl IMMR get base address of internal registers andis ly rl Str clear lower 16 bits to 0 andis r2 r0 0 clear r2 oris r2 r2 MemStart write base address ori r2 r2 0801 port size 16 bits select GPCM enable stw r2 BR4 r1 write value to base register andis 2 100 clear r2 oris r2 r2 ffc0 address mask use upper 10 bits ori r2 r2 0708 normal CS negation delay CS clock inhibit burst stw r2 OR4 r1 write to option register andis r1 r0 0 clear rl oris r1 r1 MemStart point rl to start of S1D13706 mem space lbz r0 RevCodeReg r1 read revision code into rl b Loop branch forever Note MPC8BUG does not support comments or symbolic equates These have been added for clarity only Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 23 Epson Research and Development Page 21 Vancouver Design Center 5 Software Test utilities and Windows CE v2 11 2 12 display drivers are available for the S1D13706 Full source code is available for both the test utilities and the drivers The test utilities are
400. high byte enable signal from the NEC VR4102 4111 which in conjunction with address bit 0 allows byte steering of read and write opera tions WEO connects to WR the write enable signal from the NEC VR4102 4111 and must be driven low when the VR4102 4111 is writing data to the S1D13706 RD connects to RD the read enable signal from the NEC VR4102 4111 and must be driven low when the VR4102 4111 is reading data from the S1D13706 WAIT connects to LCDRDY and is a signal output from the 1D13706 that indicates the VR4102 VR4111 must wait until data is ready read cycle or accepted write cycle on the host bus Since VR4102 VR4111 accesses to the S1D13706 may occur asynchro nously to the display update it is possible that contention may occur in accessing the S1D13706 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS and Read Write RD WR signals are not used in this implemen tation of the NEC VR4102 4111 interface using the Generic 2 Host Bus Interface These pins must be tied high connected to HIO Vpp Interfacing to the NEC VR4102 VR4111 Microprocessors 1D13706 Issue Date 01 02 23 X31B G 007 02 Page 12 Epson Research and Development Vancouver Design Center 4 VR4102 VR4111 to S1D13706 Interface 4 1 Hardware Description The NEC VR4102 VR4111 microprocessor is specifically designed to sup
401. hip select This accommodates memory and peripherals with long setup times The EHTR Extended hold time bit inserts an additional 1 clock delay on the first access to a chip select Up to 15 wait states may be inserted or the peripheral can terminate the bus cycle itself by asserting TA Transfer Acknowledge Any chip select may be programmed to assert BI Burst Inhibit automatically when its memory space is addressed by the processor core Interfacing to the Motorola MPC821 Microprocessor 1D13706 Issue Date 01 02 23 X31B G 009 02 Page 12 Epson Research and Development Vancouver Design Center Figure 2 3 GPCM Memory Devices Timing illustrates a typical cycle for a memory mapped device using the GPCM of the Power PC CLOCK A 0 31 D 0 31 XOXO Valid Figure 2 3 GPCM Memory Devices Timing 2 3 2 User Programmable Machine UPM The UPM is typically used to control memory types such as Dynamic RAMs which have complex control or address multiplexing requirements The UPM is a general purpose RAM based pattern generator which can control address multiplexing wait state gener ation and five general purpose output lines on the MPC821 Up to 64 pattern locations are available each 32 bits wide Separate patterns may be programmed for normal accesses burst accesses refresh timer events and exception conditions This fl
402. his application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and the NEC VR4181A microprocessor The NEC VR4181A microprocessor is specifically designed to support an external LCD controller The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the NEC VR4181A Microprocessor S1D13706 Issue Date 01 02 23 X31B G 008 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4181A 2 1 The NEC VR4181A System Bus 2 1 1 Overview 1D13706 X31B G 008 02 The VR Series family of microprocessors features a high speed synchronous system bus typical of modern microprocessors Designed with external LCD controller support and Windows CE based embedded consumer applications in mind the VR4181A offers a highly integrated solution for portable systems This section is an overview of the operation of the CPU bus to establish interface requirements The NEC VR4181A is designed around the RISC architecture developed by MIPS This microprocessor is desi
403. ht x bpp 8 4 1 In SwivelView 270 program the start address desired byte address sub window height 1 x sub window width x bpp 8 4 Note SwivelView 0 and 180 require the panel width to be a multiple of 32 bpp Swivel View 90 and 270 require the panel height to be a multiple of 32 bpp If this is not possible a virtual display one larger than the physical panel size is required which does satisfy the above requirements To create a virtual display program the sub win dow line address offset to values which are greater than that required for the given dis play width REG 80h Sub Window Line Address Offset Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 81h Sub Window Line Address Offset Register 1 n a n a n a n a n a n a Bit 9 Bit 8 These registers indicate the number of dwords per line in the sub window image number of dwords per line image width 32 bpp Note The image width must be a multiple of 32 bpp 1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center Page 41 REG 84h Sub Window X Start Position Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 85h Sub Window X Start Position Register 1 n a n a n a n a n a n a Bit 9 Bit 8 Programming N
404. i NEC VR4181A AB 16 0 A 16 0 DB 15 0 D 15 0 WE1 UBE CS LCDCS M R A17 CLKI SYSCLK BS Connect to HIO Vpp RD WR Connect to HIO Vpp RD MEMRD WEO MEMWR WAIT IORDY RESET RESET Interfacing to the NEC VR4181A Microprocessor Issue Date 01 02 23 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The interface requires the following signals CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example SYSCLK from the NEC VR4181A is used for CLKI The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the NEC VR4181A address A 16 0 and data bus D 15 0 respectively CNF4 must be set to select little endian mode Chip Select CS must be driven low by LCDCS whenever the S1D 13706 is accessed by the VR4181A M R memory register selects between memory or register accesses This signal may be connected to an address line allowing system address A17 to be connected to the M R line WE1 connects to UBE the high byte enable signal from the NEC VR4181A which in conjunction with address bit 0 allows byte steering of read and write operations WEO connects to MEMWR the write enable signal from the NEC VR4181A and must be driven low when the NEC VR4181A is writing data to the S1D13706
405. ignificant bit For example the most significant bits of the address bus and data bus are AO and DO while the least significant bits are A31 and D31 The MPC8xx uses both a 32 bit address and data bus A parity bit is supported for each of the four byte lanes on the data bus Parity checking is done when data is read from external memory or peripherals and generated by the MPC8xx bus controller on write cycles All IO accesses are memory mapped meaning there is no separate IO space in the Power PC architecture Support is provided for both on chip DMA controllers and off chip other processors and peripheral controllers bus masters For further information on this topic refer to Section 6 References on page 22 The bus can support both normal and burst cycles Burst memory cycles are used to fill on chip cache memory and for certain on chip DMA operations Normal cycles are used for all other data transfers 1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 02 Issue Date 01 02 23 Epson Research and Development Page 9 Vancouver Design Center 2 2 1 Normal Non Burst Bus Transactions A data transfer is initiated by the bus master by placing the memory address on address lines AO through A31 and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e TSIZ 0 1 Transfer Size indicates whether the bus cycle is 8 16 or 32 bit e RD WR
406. implementation of a S1D13706 to PC Card bus interface Table 4 1 Summary of Power On Reset Configuration Options S1D13706 value on this pin at the rising edge of RESET is used to configure 1 0 Pin Name 1 0 CNF 2 0 CNF3 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs CNF4 Big Endian bus interface CNF5 Active high WAIT CNF 7 6 see Table 4 2 CLKI to BCLK Divide Selection for recommended setting configuration for PC Card Bus Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 recommended setting for PC Card Bus 4 3 Register Memory Mapping The S1D13706 is a memory mapped device The S1D13706 uses two 128K byte blocks which are selected using A17 from the PC Card bus A17 is connected to the 1D13706 M R pin The internal registers occupy the first 128K byte block and the 80K byte display buffer occupies the second 128K byte block The PC Card socket provides 64M bytes of memory address space However the S1D13706 only needs a 256K byte block of memory to accommodate its 80K byte display buffer and register set For this reason only address bits A 17 0 are used while A 25 17 are ignored The S1D13706 s memory and registers are aliased every 256K bytes for a total of 256 times in the 64M byte PC Card memory address space Note If aliasing is not desirable the upper addresses must be fully d
407. in clock synthesizer because selected frequency not in table void seGetHalVersion const char pVersion const char pStatus const char pRevision Description Parameters Return Value 1D13706 X31B G 003 03 Retrieves the HAL library version information By retrieving and displaying the HAL ver sion information along with application version information it is possible to determine at a glance whether the latest version of the software is being run pVersion A pointer to the string containing the HAL version code pStatus A pointer to the string containing the HAL status code A B designates a beta version of the HAL a NULL indicates the release version pRevision A pointer to the string containing the HAL revision status The version information is returned as the contents of the pointer arguments A typical return might be pVersion 1 01 HAL version 1 01 pStatus B BETA release pRevision 5 fifth update of the beta Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 67 Vancouver Design Center int seHalTerminate void Description Parameters Return Value int seGetld int pld Frees up memory allocated by HAL before application exits none ERR_OK HAL is now ready for application to exit ERR_PCI_DRIVER_NOT_FOUND Could not find PCI driver Intel Windows platform only ERR_PCI_BRIDGE_ADAPTER_NOT_FOUND Could not fi
408. indow positioned at SwivelView 270 coordinates 60 80 with a width of 120 and a height of 160 1 Confirm the main window coordinates are valid The vertical coordinates must be a multiple of 32 bpp 240 32 4 30 Main window coordinates are valid Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 58 1D13706 X31B G 003 03 Epson Research and Development Vancouver Design Center Confirm the sub window coordinates are valid The horizontal coordinates and horizontal width must be a multiple of 32 bpp 60 32 4 7 5 invalid 120 32 4 15 The sub window horizontal start coordinate is invalid Therefore a valid coordinate close to 60 must be chosen For example 8 x 32 4 64 Consequently the new sub window coordinates are 64 80 Determine the main window display start address The main window is typically placed at the start of display memory which is at dis play address 0 main window display start address register desired byte address panel width 1 x panel height x bpp 8 4 0 320 1 x 240 x 4 8 4 9570 2562h Program the Main Window Display Start Address registers REG 74h is set to 62h REG 75h is set to 25h and REG 76h is set to 00h Determine the main window line address offset number of dwords per line image width 32 bpp 240 32 4 30 1Eh Program the Main Window Line Address Offset regist
409. indows CE v2 11 2 12 display drivers are available for the S1D13706 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or www eea epson com Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors 1D13706 Issue Date 01 02 23 X31B G 002 02 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e Toshiba America Electrical Components Inc TMPR3905 12 Specification e Epson Research and Development Inc S1D 3706 Hardware Functional Specification Document Number X31B A 001 xx e Epson Research and Development Inc S5U13706B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X31B G 004 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources e Toshiba America Electrical Components Website http www toshiba com taec e Epson Electronics America Website www eea epson com 1D13706 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 02 Issue
410. ines BI 1 assert Burst Inhibit SCY 0 3 0 wait state selection this field is ignored since external transfer acknowledge is used see SETA below SETA 1 the S1D13706 generates an external transfer acknowledge using the WAIT line TRLX 0 normal timing EHTR 0 normal timing Interfacing to the Motorola MPC821 Microprocessor 1D13706 Issue Date 01 02 23 X31B G 009 02 Page 20 Epson Research and Development Vancouver Design Center 4 6 Test Software BR4 OR4 MemStart RevCodeReg Start Loop end 1D13706 X31B G 009 02 The test software to exercise this interface is very simple It configures chip select 4 CS4 on the MPC821 to map the 1D 13706 to an unused 256K byte block of address space and loads the appropriate values into the option register for CS4 Then the software runs a tight loop reading the 13706 Revision Code Register REG 00h This allows monitoring of the bus timing on a logic analyzer The following source code was entered into the memory of the MPC821ADS using the line by line assembler in MPC8BUG the debugger provided with the ADS board Once the program was executed on the ADS a logic analyzer was used to verify operation of the interface hardware It is important to note that when the MPC821 comes out of reset its on chip caches and MMU are disabled If the data cache is enabled then the MMU must be set up so that the S1D13706 memory block is tagged as non cac
411. ing Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 90 Epson Research and Development Vancouver Design Center DWORD seGetPixel long x long y DWORD seGetMainWinPixel long x long y DWORD seGetSubWinPixel long x long y Description Parameters Return Value S1D13706 X31B G 003 03 Returns the pixel color at the specified display location Use seGetPixel to read the pixel color at the specified x y co ordinates on the current active surface See seSetMainWinAsActiveSurface and seSetSubWinAsActiveSurface for information about changing the active surface Use seGetMainWinPixel and seGetSubWinPixel to read the pixel color at the specified x y co ordinate on the display surface referenced in the function name x The X co ordinate in pixels of the pixel to read y The Y co ordinate in pixels of the pixel to read The return value is a dword describing the color read at the x y co ordinate Color is interpreted differently at different color depths If no memory was allocated to the surface the return value is DWORD 1 At 1 2 4 and 8 bpp display colors are derived from the lookup table values The return value is an index into the lookup table The red green and blue components of the color can be determined by reading the lookup table values at the returned index At 16 bpp the lookup table is bypassed and each word of display memory form the color to display In this mode
412. ing table shows the configuration required for this implementation of a S1D13706 to NEC VR181A interface Table 4 1 Summary of Power On Reset Configuration Options 1D1370 value on this pin at the rising edge of RESET is used to configure 1 0 6 Pin Name CNF 2 0 CNF3 1 GPIO pins as inputs at power on CNF4 Big Endian bus interface CNF5 Active high WAIT CNF 7 6 see Table for recommended setting 0 GPIO pins as HR TFT D TFT outputs nm configuration for NEC VR4181A Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 e recommended setting for NEC VR4181A Interfacing to the NEC VR4181A Microprocessor Issue Date 01 02 23 1D13706 X31B G 008 02 Page 14 Epson Research and Development Vancouver Design Center 4 3 NEC VR4181A Configuration 1D13706 X31B G 008 02 The S1D13706 is a memory mapped device The S1D13706 uses two 128K byte blocks which are selected using A17 from the NEC VR181A A17 is connected to the S1D13706 M R pin The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block When the VR4181A embedded LCD controller is disabled the external LCD controller chip select signal LCDCS decodes either a 64K byte 128K byte 256K byte or 512K byte memory block in the VR4181A external ISA m
413. ing to the Epson D TFD Panels Issue Date 01 02 23 Epson Research and Development Page 21 Vancouver Design Center 6 Test Software Test utilities and display drivers are available for the S1D13706 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and display drivers are available from your sales support contact or www eea epson com Connecting to the Epson D TFD Panels S1D13706 Issue Date 01 02 23 X31B G 012 03 Page 22 Epson Research and Development Vancouver Design Center 7 References 7 1 Documents Epson Research and Development Inc 1D13706 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples Document Number X31B G 003 xx 7 2 Document Sources e Epson Electronics America Website http www eea epson com S1D13706 Connecting to the Epson D TFD Panels X31B G 012 03 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 8 Technical Support 8 1 EPSON LCD Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino
414. ing to the Intel StrongARM SA 1110 Microprocessor 1D13706 Issue Date 02 06 26 X31B G 019 02 Page 14 Epson Research and Development 4 2 S1D13706 Hardware Configuration 1D13706 X31B G 019 02 Vancouver Design Center The S1D13706 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13706 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a S1D13706 to SA 1110 interface Table 4 1 Summary of Power On Reset Configuration Options 1D13706 Pin Name CNF 2 0 CNF3 value on this pin at the rising edge of RESET is used to configure 1 0 GPIO pins as inputs at power on CNF4 Big Endian bus interface CNF5 Active high WAIT CNF 7 6 see Table 4 2 CLKI to BCLK Divide Selection for recommended setting GPIO pins as HR TFT D TFT outputs SS configuration for SA 1110 Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 recommended setting for SA 1110 Interfacing to the Intel StrongARM SA 1110 Microprocessor Issue Date 02 06 26 Epson Research and Development Page 15 Vancouver Design Center 4 3 StrongARM SA 1110 Register Configuration The SA 1110 requires configuration of several
415. interface e Direct support for Epson D TFD and Sharp HR TFT Power Down Modes Software Initiated Power Save Mode external timing control IC not required Operating Voltage e Typical resolutions supported COREypnp 1 8 to 2 2 volts and 3 0 to 3 6 volts Be ere ol HlOypp 1 8 to 2 2 volts and 3 0 to 3 6 volts 160x160 16bpp 160x240 16bpp NIOypp 3 0 to 3 6 volts Clock Source Package 100 pin TQFP15 e 104 pin CFLGA e Two clock inputs single clock possible e Clock source can be internally divided down for a higher frequency clock input CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS e S1D13706 Technical Palm OS Hardware DstGNED FoR at AC Manual Abstraction Layer so Windows S5U13706 Evaluation Boards Windows CE Display Driver hae y Embedded G CPU Independent Software VXWorks Tornado Display Pron patrati Utilities Driver Japan North America Taiwan Seiko Epson Corporauon nate Epson Electronics America Inc Epson Taiwan Technology amp Trading Ltd Electronic Devices Marketing Division 150 River Oaks Parkway 10F No 287 oye Hino Hino sh San Jose CA 95134 USA Nanking East Road Tokyo 191 8501 Jf Tel 408 922 0200 Sec 3 Taipei Taiwan Teles eae Fax 408 922 0238 Tel 02 2717 7360 bak 042 S8 D301 F http www eea epson com Fax 02 2712 9164 http www epson co jp Hong Kong Europe Singapore Epson Hong Kong Ltd Epson Europe Electronics Gmb
416. ion 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 62 Epson Research and Development Vancouver Design Center 6 4 3 Single Monochrome 8 Bit Panel Timing VDP VNDP h db FPFRAME dE FPLINE l fl L fl fl l l DRDY MOD X tae X FPDAT 7 0 X Invalid LINE1 X LINE2 X LINES X LINE4 XLINE479XLINE480 Invalid LINE1 YX LINE2 FPLINE 7 DRDY MOD y a HDP HNDP ja gt rele eh Ure iy mE em Ap M FPDAT7 Invalid X 11 19 X X AS Y Y 1633X Invalid X FPDAT6 Invalid 1 2 X 1 10 X Y E Y y Y 534 invalid Y y FPDAT5S mwad Xos Xmm X NOOO maa X X FPDAT4 invalid 14 112 X Y x Y Y X 1636X Invalid X X FPDAT3 Invalid T5 Y 1 13 Y Y So ey Y y 537 invalid y FPDAT2 Invalid X 16 X 114 X X PE E Y Y 638X Invalid X FPDAT1 Imad ECO A nati X FPDATO Invalid Xais XiX X S X XO X1s0Y Invalid y Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6 17 Single Monochrome 8 Bit Panel Timing VDP Vertical Display Period REG 1Dh bits 1 0 REG 1Ch bits 7 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 19h bits 1 0 REG 18h bits 7 0 REG 1 Dh bits 1 0 REG 1Ch bits 7 0 Lines HDP Horizontal Display Period REG 14h bits 6 0 1 x 8Ts HNDP Horizontal Non Display P
417. ion file The file mode0 h contains the register values required to set the screen resolution col or depth bpp display type rotation etc The mode0 h file included with the drivers may not contain applicable values and must be regenerated The configuration pro gram 13706CFG can be used to build a new mode0 h file If building for 8 bpp place the new mode0 h file in the directory x 13706 8bpp File If building for 16 bpp place the new mode0 h file in x 13706 16bpp File Wind River UGL v1 2 Display Drivers Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center Note Mode0 h should be created using the configuration utility 13706CFG For more infor mation on 13706CFG see the 13706CFG Configuration Program User Manual docu ment number X31B B 001 xx available at www erd epson com 6 Open the S1D13706 workspace From the Tornado tool bar select File gt Open Workspace gt Existing gt Browse and select the file x 13706 8bpp 13706 wsp or x11370616bpp113706 wsp 7 Add support for single line comments The UGL v1 2 display driver source code uses single line comment notation rather than the ANSI conventional comments P To add support for single line comments follow these steps a In the Tornado Workspace window click on the Builds tab b Expand the Sbpp Builds or 16bpp Builds view by clicking on the
418. ion register REG 88h is set to 07h and REG 89h is set to 00h Program the Sub window X End Position register REG 8Ch is set to EFh and REG 8Dh is set to 00h Program the Sub window Y End Position register REG 90h is set to 15h and REG 91h is set to 00h 8 Enable the sub window Program the Sub window Enable bit REG 71h bit 4 is set to 1 Programming Notes and Examples S1D13706 Issue Date 01 02 23 X31B G 003 03 Page 54 Epson Research and Development Vancouver Design Center 8 3 3 SwivelView 180 180 SwivelView sub window x end position REG 8Dh REG 8Ch sub window x start position REG 85h REG 84h sub window Py main window sub window y end position ds REG 91h REG 90h sub window y start position panel s origin REG 89h REG 88h 1D13706 X31B G 003 03 Figure 8 4 Picture in Picture Plus with SwivelView 180 enabled SwivelView 180 is a mode in which both the main and sub windows are rotated 180 counter clockwise when shown on the panel The images for each window are typically placed consecutively with the main window image starting at address 0 and followed by the sub window image In addition both images must start at addresses which are dword aligned the last two bits of the starting address must be 0 Note It is possible to use the same image for both the main window and sub window To do so set the sub window line addr
419. ip Select Configuration Chip Selects 0 and 1 have programmable block sizes from 64K bytes through 2G bytes However these chip selects would normally be needed to control system RAM and ROM Therefore one of the IO chip selects CS2 through CS7 is required to address the entire address space of the S1D13706 These IO chip selects have a fixed 2M byte block size In the example interface chip select 4 is used to control the S1D13706 The CSBAR register should be set to the upper 8 bits of the desired base address The following options should be selected in the chip select mask registers CSMR4 5 e WP 0 disable write protect e AM 0 enable alternate bus master access to the S1D13706 e C I 1 disable CPU space access to the S1D13706 e SC 1 disable Supervisor Code space access to the S1D13706 e SD 0 enable Supervisor Data space access to the S1D13706 e UC 1 disable User Code space access to the S1D13706 e UD 0 enable User Data space access to the S1D13706 e V 1 global enable Valid for the chip select The following options should be selected in the chip select control registers CSCR4 5 e WS0 3 0 no internal wait state setting e AA 0 no automatic acknowledgment e PS 1 0 1 0 memory port size is 16 bits e BEM 0 Byte enable write enable active on writes only e BSTR 0 disable burst reads e BSTW 0 disable burst writes Interfacing to the Motorola MCF5307 ColdFire Microprocessor
420. ircuit for Vertical Logic Control Signals 13 3 S1D13706 to D TFD Panel Pin Mapping 02020 eee eee 14 3 1 LCD Pin Mapping for Horizontal Connector LF37SQT and LF26SCT 15 3 2 LCD Pin Mapping for Y Connector LF37SQT 2 2 2 2 2 ee 16 3 3 LCD Pin Mapping for Y Connector LF26SCT 2 0 2 2 2 2 07 Power On Off Sequence 0 2 eee e 18 GCP Data Signal cuicos A ee a Be A a ee A 19 Sil GCP Data Structure 04 e426 ia aha el de ae en a a a MS 5 2 Programming GCP Data 2 2 2 5 52 20 Test Software viet Aeris a O Sh SA ee eae eee bg ee SYA ene 21 R ferentes n 0d gw i woe Bw ae ee ae a a eee the el ee 22 LI Documents e ta A Oe a BR ee a A a oe el RR 7 2 Document Sources 22 8 Technical Support 5242 aaa A A a 23 8 1 EPSON LCD Controllers S1D13706 2 2 02 2 2 23 Connecting to the Epson D TFD Panels S1D13706 Issue Date 01 02 23 X31B G 012 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Connecting to the Epson D TFD Panels X31B G 012 03 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center Table 2 1 Table 3 1 Table 3 2 Table 3 3 Table 4 1 Table 5 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 4 1 Figure 5 1 Connecting to the Epson D TFD Panels Issue Date 01 02 23 List of Tables Swing Power Supply Val
421. isplay Buffer unused Look Up Table entries Figure 11 3 4 Bit per pixel Monochrome Mode Data Output Path 8 Bit per pixel Monochrome Mode Green Look Up Table 256x6 00 0000 0000 01 0000 0001 02 0000 0010 03 0000 0011 04 0000 0100 05 0000 0101 06 0000 0110 07 0000 0111 6 bit Gray Data gt F8 1111 1000 F9 1111 1001 FA 1111 1010 FB 1111 1011 FC 1111 1100 FD 1111 1101 FE 11111110 FF 11111111 8 bit per pixel data from Display Buffer Figure 11 4 8 Bit per pixel Monochrome Mode Data Output Path Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 134 Epson Research and Development Vancouver Design Center 16 Bit Per Pixel Monochrome Mode The LUT is bypassed and the green data is directly mapped for this color depth See Display Data Formats on page 131 11 2 Color Modes 1 Bit Per Pixel Color Red Look Up Table 256x6 6 bit Red Data 00 0 gt 01 1 FC FD FE FF Green Look Up Table 256x6 p 6 bit Green Data 00 0 gt 01 1 FD FE
422. isplay memory must NOT be corrupted or lost on sus pend The memory clock must remain running Off screen data in display memory must NOT be corrupted or lost on sus pend The memory clock must remain running This mode cannot be used if power to the display memory is turned off b PORepaint 1 This is the default mode for Windows CE This mode tells Windows CE to save the main display data to the system memory on suspend This mode is used if display memory power is going to be turned off when the system is suspended and there is enough system memory to save the image Any off screen data in display memory is LOST when suspended Therefore off screen memory usage must either be disabled in the display driver i e EnablePreferVmem not defined in SOURCES file or new OEM specific code must be added to the display driver to save off screen data to system memory when the system is suspended and restored when resumed If off screen data is used provided that the OEM has provided code to save off screen data when the system suspends additional code must be added to the display driver s surface allocation routine to prevent the display driver from allocating the main memory save region in display memory When WinCE OS attempts to allocate a buffer to save the main display data WinCE OS marks the allocation request as preferring display memory We believe this is incorrect Code must be added to prevent this specific allocation
423. isplay rotation etc Before building the console driver refer to the descriptions in the file s1d13706 h for the default settings of the console driver If the default does not match the configura tion you are building for then s1d13706 h will have to be regenerated with the correct information Use the program 13706CFG to generate the required header file For information on how to use 13706CFG refer to the 13706CFG Configuration Program User Manual document number X31B B 001 xx available at www erd epson com After selecting the desired configuration choose File gt Export and select the C Header File for S1D13706 Generic Drivers option Save the new configuration as s1d13706 h in the usr src linux drivers video replacing the original configuration file 5 Configure the video options From the command prompt in the directory usr src linux run the command make menuconfig This command will start a text based interface which allows the selection of build time parameters From the text interface under Console drivers options select Support for frame buffer devices Epson LCD CRT controllers support S1D13706 support Advanced low level driver options xBpp packed pixels support where x is the color depth being compile for If you are using the Epson PCI evaluation board then you must also select Epson PCI Bridge adapter support Once you have configured the kernel op
424. it 0 GPIOO has no effect on the video data When this bit 1 video data may be inverted via GPIOO Note The S1D13706 requires some configuration before the hardware video invert feature can be enabled CNF3 must be set to 1 at RESET e GPIO Pin Input Enable REG A9h bit 7 must be set to 1 e GPIOO Pin IO Configuration REG A8h bit 0 must be set to 0 If Hardware Video Invert is not available i e HR TFT panel is used the video invert function can be controlled by software using REG 70h bit 4 The following table summa rizes the video invert options available Table 8 8 Inverse Video Mode Select Options enana ime creo too 0 0 xX Normal 0 1 xX Inverse 1 X 0 Normal 4 X 1 Inverse Note Video data is inverted after the Look Up Table Software Video Invert When this bit 0 video data is normal When this bit 1 video data is inverted See Table 8 8 Inverse Video Mode Select Options Note Video data is inverted after the Look Up Table Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 111 Vancouver Design Center bits 2 0 Bit per pixel Select Bits 2 0 These bits select the color depth bit per pixel for the displayed data for both the main window and the PIP window if active Note 1 2 4 and 8 bpp color depths use the 18 bit LUT allowing a maximum number of 256K available colors on TFT panels 16 bpp mode bypasses
425. it per pixel Select Bits 2 0 Enable 7 6 5 4 3 2 1 0 bit 7 Display Blank When this bit 0 the LCD display pipeline is enabled When this bit 1 the LCD display pipeline is disabled and all LCD data outputs are forced to zero i e the screen is blanked bit 6 Dithering Disable Hardware Functional Specification Issue Date 01 11 13 Dithering allows 64 intensity levels for each color component RGB In monochrome modes where only the Green color component of the Look Up Table is used 64 shades of gray are available for each position used in the LUT In color modes 64 shades of color are available for each color component resulting in 256K possible color combinations When this bit 0 dithering is enabled for passive LCD panels When this bit 1 dithering is disabled for passive LCD panels Note This bit does not refer to the number of simultaneously displayed colors but rather the maximum available colors refer to Table 8 9 LCD Bit per pixel Selection on page 111 for the maximum number of simultaneously displayed colors 1D13706 X31B A 001 08 Page 110 bit 5 bit 4 1D13706 X31B A 001 08 Epson Research and Development Vancouver Design Center Hardware Video Invert Enable This bit allows the Video Invert feature to be controlled using the General Purpose IO pin GPIOO This option is not available if configured for a HR TFT or D TFD as GPIOO is used as an LCD control signal by both panels When this b
426. ition of the vertical sync signal in 1 line resolution For passive panels these bits must be set to 00h For TFT HR TFT D TFD panels VDPS is calculated using the following formula VPS REG 27h bits 1 0 REG 26h bits 7 0 Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 56 D TFD GCP Index Register REG 28h Read Write n a D TFD GCP Index Bits 4 0 7 6 5 4 3 2 1 0 bits 4 0 D TFD GCP Index Bits 4 0 For D TFD panels only These bits form the index that points to 32 8 bit GCP data regis ters D TFD GCP Data Register REG 2Ch Read Write D TFD GCP Data Bits 7 0 7 6 5 4 3 2 1 0 bits 7 0 D TFD GCP Data Bits 7 0 For D TFD panel only This register stores the data to be written to the GCP data bits and is controlled by the D TFD GCP Index register REG 28h For further information on the use of this register see Connecting to the Epson D TFD Panels document number X31B G 012 xx Note The Panel Type bits REG 10h bits 1 0 must be set to 11 D TFD for the GCP Data bits to have any hardware effect 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Vancouver Design Center Page 109 8 3 5 Display Mode Registers Display Mode Register REG 70h Read Write ep teas Hardware Display Blank ae 9 Video Invert a n a B
427. iveDisp dword 1 Rotation dword 0 13 From the Build menu select Rebuild Platform to generate a Windows CE image file NK BIN in the project directory x myproject myplatform reldir x86_release nk bin Build for CEPC X86 on Windows CE Platform Builder 3 00 using the Command Line Interface 1 Windows CE 3 x Display Drivers Issue Date 01 05 25 Install Microsoft Windows 2000 Professional or Windows NT Workstation version 4 0 with Service Pack 5 or later Install Windows CE Platform Builder 3 00 Create a batch file called x wince300 cepath bat Put the following in cepath bat Xx cd wince300 public common oak misc call wince x86 i486 CE MAXALL CEPC set IMGNODEBUGGER 1 set WINCEREL 1 set CEPC_DDI_S1D13X0X 1 Generate the build environment by calling cepath bat Create a new folder called S1D13706 under x wince300 platform cepc drivers dis play and copy the 1D13706 driver source code into x wince300 platform cepc driv ers display S 1D13706 Edit the file x wince300 platform cepc drivers display dirs and add S1D13706 into the list of directories Edit the file x wince300 platform cepc files platform bib and make the following two changes a Insert the following text after the line IF ODO_NODISPLAY IF CEPC_DDI_S1D13X0X ddi dil FLATRELEASEDIRAS1D13X0X d1l NK SH ENDIF b Find the section shown below and insert the lines as marked IF CEPC_DDI_FLAT IF CEPC_DDI_S1D13X0X In
428. ixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 1D13706 X31B G 003 03 Figure 3 1 Pixel Storage for 1 Bpp in One Byte of Display Buffer At a color depth of 1 bpp each byte of display buffer contains eight adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the unchanged bits and setting the appropriate bits to 1 One bit pixels provide 2 gray shades color possibilities For monochrome panels the gray shades are generated by indexing into the first two elements of the green component of the Look Up Table LUT For color panels the 2 colors are derived by indexing into the first 2 positions of the LUT Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 15 Vancouver Design Center 3 3 Memory Organization for Two Bit per pixel 4 Colors Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 1 Pixel 2 Pixel 3 Bits 1 0 Bits 1 0 Bits 1 0 Bits 1 0 Figure 3 2 Pixel Storage for 2 Bpp in One Byte of Display Buffer At a color depth of 2 bpp each byte of display buffer contains four adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the unchanged bits and setting the appropriate bits to 1 Two bit pixels provide 4 gray shades color possibilities For monochrome panels the gray shades are generated by indexing into the first 4 elements of the green c
429. l A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 14 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 3 Ts t9 FPSHIFT period 5 Ts t10 FPSHIFT pulse width low 2 Ts t11 FPSHIFT pulse width high 2 Ts t12 FPDAT 15 0 setup to FPSHIFT rising edge 2 Ts t13 FPDAT 15 0 hold to FPSHIFT rising edge 2 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 t min HPS t4 min 3 t2min t8min HPS t4min 4 83min HT 5 t4min HPW 6 t5mn HPS 1 7 t6min HPS HDP HDPS 2 if negative add t3 min 8 tl4min HDPS HPS t4min if negative add t3min Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 72 Epson Research and Development Vancouver Design Center 6 4 8 Generic TFT Panel Timing
430. l input with pull down resistor typical value of 50Q at 3 3V High Impedance LVTTL is Low Voltage TTL see Section 5 D C Characteristics on page 32 4 4 1 Host Interface Table 4 3 Host Interface Pin Descriptions Pin Name Type 10 RESET Pin Cell Description Voltage State ABO This input pin has multiple functions For Generic 1 this pin is not used and should be connected to VSS For Generic 2 this pin inputs system address bit O AO e For SH 3 SH 4 this pin is not used and should be connected to VSS e For MC68K 1 this pin inputs the lower data strobe LDS e For MC68K 2 this pin inputs system address bit O AO For REDCAP2 this pin is not used and should be connected to VSS For DragonBall this pin is not used and should be connected to VSS See Table 4 9 Host Bus Interface Pin Mapping on page 30 for summary 5 LIS HIOVDD 0 AB 16 1 87 99 24 LI HIOVDD 0 System address bus bits 16 1 1D13706 X31B A 001 08 Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Vancouver Design Center Page 23 Table 4 3 Host Interface Pin Descriptions Pin Name Type Pin Cell IO Voltage RESET State Description DB 15 0 18 24 27 35 LB2A HIOVDD Hi Z Input data from the system data bus For Generic 1 these pins are connected to D 15 0
431. l of transceivers U17 and U18 is low only during read access even when EBC in the CS1 Control Register is set to 0 Interfacing to the Motorola RedCap2 DSP With Integrated MCU Issue Date 01 02 23 Epson Research and Development Page 15 Vancouver Design Center 4 3 S1D13706 Hardware Configuration The S1D13706 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13706 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a S1D13706 to Motorola REDCAP2 microprocessor Table 4 2 Summary of Power On Reset Options S1D13706 state of this pin at rising edge of RESET is used to configure 1 0 Pin Name 1 0 CNF 2 0 CNF3 GPIO pins as inputs at power on GPIO pins as HR TFT D TFD outputs CNF4 Little Endian bus interface CNF5 WAIT is active high WAIT is active low CLKI to BCLK divide select CNF7 CNF6 CLKI to BCLK Divide Ratio CNF 7 6 oe A 0 1 2 1 1 0 3 1 1 1 4 1 configuration for REDCAP2 microprocessor 4 4 Register Memory Mapping The S1D13706 is a memory mapped device The S1D13706 uses two 128K byte blocks which are selected using A17 from the REDCAP2 bus A17 is connected to the S1D13706 M R pin The internal registers occupy the first 128K byte block and the 80K byte display buffer
432. le PWM Duty Cycle Modulation Duty n 256 n PWM Clock Duty Cycle PWM Clock Force High CV Pulse Enable CV Pulse Burst Generation E to PWMOUT frequency Clock Source 2 X 256 y pulse burst y Burst Length value CV Pulse Force High B to CVOUT frequency Clock Source 2 X 2 Figure 8 2 PWM Clock CV Pulse Block Diagram Note For further information on PWMCLK see Section 7 1 4 PWMCLK on page 92 PWM Clock CV Pulse Control Register REG BOh Read Write PWM Clock y PWM Clock CV Pulse Beak isn CV Pulse CV Pulse Force High Enable Force High RO Burst Start Enable 7 6 5 4 3 1 0 bit 7 and bit 4 PWM Clock Force High bit 7 and PWM Clock Enable bit 4 These bits control the PWMOUT pin and PWM Clock circuitry as follows Table 8 15 PWM Clock Control Bit 7 Bit 4 Result 0 4 PWM Clock circuitry enabled controlled by REG B1h and REG B3h 0 0 PWMOUT forced low 1 x PWMOUT forced high x don t care S1D13706 X31B A 001 08 When PWMOUT is forced low or forced high it can be used as a general purpose output Note The PWM Clock circuitry is disabled when Power Save Mode is enabled Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 127 Vancouver Design Center bit 3 and bit 0 CV Pulse Force High bit
433. le Note The LUT entry is updated only when the LUT Write Address Register REG OBh is written to Look Up Table Red Write Data Register REG OAh Write Only LUT Red Write Data Bits 5 0 n a 7 5 4 3 2 1 0 bits 7 2 LUT Red Write Data Bits 5 0 Hardware Functional Specification Issue Date 01 11 13 This register contains the data to be written to the red component of the Look Up Table The data is stored in this register until a write to the LUT Write Address register REG OBh moves the data into the Look Up Table Note The LUT entry is updated only when the LUT Write Address Register REG OBh is written to S1D13706 X31B A 001 08 Page 100 Epson Research and Development Vancouver Design Center Look Up Table Write Address Register REG OBh Write Only LUT Write Address Bits 7 0 7 5 4 3 2 1 0 bits 7 0 LUT Write Address Bits 7 0 This register forms a pointer into the Look Up Table LUT which is used to write LUT blue green and red data stored in REG 08h REG O9h and REG OAh The data is updated to the LUT only with the completion of a write to this register This is a write only register and returns 00h if read Note When a value is written to the LUT Write Address register the same value is automati cally written to the LUT Read Address register REG OFh Look Up Table Blue Read Data Register REG OCh Read Only LUT Blue Read Data Bit
434. les document number X31B G 003 xx 6 2 Document Sources e Motorola Inc Motorola Literature Distribution Center 800 441 2447 e Motorola website http www mot com e Epson Electronics America website http www eea epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor S1D13706 Issue Date 01 02 23 X31B G 010 02 Page 18 7 Technical Support 7 1 EPSON LCD Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MCF5307 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor S1D13706 X31B G 010 02 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Towe
435. line switches 13706SHOW Demonstration Program Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center 5 To show solid vertical stripes type the following 13706SHOW s The program displays the default color depth as selected by 13706CFG Press any key to go to the next screen Once all screens are shown the program exits To exit the pro gram immediately press the Esc key The s switch can be used in combination with other command line switches Comments e If 13706SHOW is started without specifying the color depth b the program automat ically cycles through the available color depths from highest to lowest The first color depth shown is the default color depth value saved to 13706SHOW using 13706CFG This approach avoids showing color depths not supported by a given hardware configu ration e 13706SHOW cannot show a greater color depth than the display device allows 13706SHOW Demonstration Program 1D13706 Issue Date 01 02 23 X31B B 002 03 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 13706SHOW Demonstration Program X31B B 002 03 Issue Date 01 02 23 EPSON 1D13706 Embedded Memory LCD Controller 13706PLAY Diagnostic Utility Document Number X31B B 003 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and us
436. ller Interfacing to the PC Card Bus Document Number X31B G 005 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the PC Card Bus X31B G 005 02 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T Introductions a a ELA aa AIDA AN AA A 7 2 Interfacing to the PC CardBus 8 2 1 The PC Card System Bus e 8 ZEE PC Card Overview se sarua da sa e as Aye ia Gon 2 8 2 1 2 Memory Access Cycles o e 8 3 1D13706 Host Bus Interface vioc oooc ca e a ee aes Se ee See 10 3 1 Host Bus Interface Pin Mapping LO 3 2 Host Bus Interface Signals s 2 a 2 eee 11 4 PC Card to S1D137
437. ls only When these bits are all 0 the MOD output signal DRDY toggles every FPFRAME For a non zero value n the MOD output signal DRDY toggles every n FPLINE Horizontal Total Register REG 12h Read Write n a Horizontal Total Bits 6 0 7 6 5 4 3 2 1 0 bits 6 0 Horizontal Total Bits 6 0 These bits specify the LCD panel Horizontal Total period in 8 pixel resolution The Hori zontal Total is the sum of the Horizontal Display period and the Horizontal Non Display period Since the maximum Horizontal Total is 1024 pixels the maximum panel resolu tion supported is 800x600 Horizontal Total in number of pixels REG 12h bits 6 0 1 x 8 Note This register must be programmed such that the following formulas are valid HDPS HDP lt HT 2 For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 56 Horizontal Display Period Register REG 14h Read Write n a Horizontal Display Period Bits 6 0 7 6 5 4 3 2 1 0 bits 6 0 Horizontal Display Period Bits 6 0 These bits specify the LCD panel Horizontal Display Period HDP in 8 pixel resolution The Horizontal Display Period should be less than the Horizontal Total to allow for a suf ficient Horizontal Non Display Period Horizontal Display Period in number of pixels REG 14h bits 6 0 1 x 8 Note For passive panels HDP must be a minimum of 32 pixels and can be inc
438. ly entered pixel widths must be a minimum of 32 pixels and can be increased by multiples of 16 For TFT panels manually entered pixel widths must be a minimum of 16 pixels and can be increased by multiples of 8 If a value is entered that does not match these requirements a notification box appears and 13706CFG rounds up the value to the next allowable width It is recommended that these automatically generated Display Total values be used without adjustment However manual adjustment may be useful in fine tuning the horizontal and vertical display totals The display total equals the display period plus the non display period It is recommended that these automatically generated Display Start values be used without adjustment However manual adjustment may be useful in fine tuning the horizontal and vertical display start positions For passive panels these values must always be 0 13706CFG Configuration Program Issue Date 01 03 29 1D13706 X31B B 001 03 Page 16 1D13706 X31B B 001 03 Frame Rate Pixel Clock TFT FPLINE pixels Epson Research and Development Vancouver Design Center Select the desired frame rate in Hz from the drop down list The values in the list are the range of possible frame rates using the currently selected pixel clock To change the range of frame rates select a different Pixel Clock rate in MHz Panel dimensions are fixed therefore frame rate can only be adjusted by changin
439. m when data is placed on the bus until the data is latched into the write buffer Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 46 Epson Research and Development Vancouver Design Center 6 2 6 Motorola MC68K 2 Interface Timing e g MC68030 A 16 0 M R SIZ 1 0 DS R W DSACK1 D 31 16 write D 31 16 read t 2 T t3 t4 gt gt CS AS t7 e gt e t8 R ht t11 gt e t10 12 y t13 4 t17 t18 gt 4 gt t19 t20 t21 gt a gt gt VALID S1D13706 X31B A 001 08 Figure 6 7 Motorola MC68K 2 Interface Timing Note For information on the implementation of the Motorola 68K 2 Host Bus Interface see Interfacing To The Motorola MC68030 Microprocessor document number X31B G 013 xx Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Vancouver Design Center Table 6 10 Motorola MC68K 2 Interface Timing Page 47 2 0V 3 3V Symbol Parameter Unit Min Max Min Max fcuk Bus Clock frequency 20 50 MHz Terk Bus Clock period T toLk 1 fcLk ns t1 Clock pulse width high 22 5 9 ns t2 Clock pulse width low 22 5 9 ns 3 A 16 0 SIZ 1 0 M R setu
440. mation in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 9 10 11 12 Table of Contents Introduction o eee cece ie ca a Boe we GOP ee a a eee weg Features lt 24 35 ia EC A Gr ee a A e Installation and Configuration 2 2 eee es 3 1 Configuration DIP Switches 3 2 Configuration Jumpers CPU Interfaces 23 ene elec oar a ond So BA eee 4 1 CPU Interface Pin Mapping 4 2 CPU Bus Connector Pin Mapping LCD Interface Pin Mapping lt o ee Technical Description jx a AA A on ah 6 1 PCI Bus Support Ky de 6 2 Direct Host Bus Interface Support 6 3 S1D13706 Embedded Memory 6 4 Manual Software Adjustable LCD Panel Positive Power pe VDDH
441. ment is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 INtKFOCMUCTION ie 6 chee a el See ee ee A ee we ae as 9 InitiallZation s EL ores Ses ates Gla are io ee Go aoe OF de 10 Memory Model gt e s a e ite o a ee ee ew a ee a ee a 14 3 1 Display Buffer Location ke on Fa bon 4 ak 14 3 2 Memory Organization for One Bit per Peel Q Colors Gray Shades A E 3 3 Memory Organization for Two Bit per pixel 4 Colors Gray Shades 15 3 4 Memory Organization for Four Bit per pixel 16 Colors Gray Shades 15 3 5 Memory Organization for 8 Bpp 256 Colors 64 Gray Shades 16 3 6 Memory Organization for 16 Bpp 65536 Colors 64 Gray Shades
442. mory LCD Controller The S1D13706 is a color monochrome LCD graphics controller with an embedded 80K byte SRAM display buffer While supporting all other panel types the S1D13706 is the only LCD controller to directly interface to both the Epson D TFD and the Sharp HR TFT family of products thus removing the requirement of an external Timing Control IC This high level of integration provides a low cost low power single chip solution to meet the demands of embedded markets such as Mobile Communications devices and Palm size PCs where board size and battery life are major concerns The S1D13706 utilizes a guaranteed low latency CPU architecture thus providing support for micropro cessors without READY WAIT handshaking signals The 32 bit internal data path provides high perfor mance bandwidth into display memory allowing for fast screen updates Products requiring a rotated display image can take advantage of the SwivelView feature which provides hardware rotation of the display memory transparent to the software application The S1D13706 also provides support for Picture in Picture Plus a variable size Overlay window The S1D13706 provides impressive support for Palm OS handhelds however its impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications E FEATURES e Embedded Display Buffer e SwivelView 90 180 270 hardware EPSON e Low Operating Voltage rotation of di
443. mplifies the development process for the S1D13706 evaluation system One issue which impedes application programming is that of latency Time critical operations i e performance measurement are not guaranteed any set amount of processor time This function raises the priority of the thread and virtually eliminates the question of latency for programs running on a Windows platform Note The application should not leave it s thread running in a high priority state for long peri ods of time As soon as a time critical operation is complete the application should call seEndHighPriorty None The priority nest count which is the number of times seBeginHighPriority has been called without a corresponding call to seEndHighPriority int seEndHighPriority void Description Parameters Return Value This function decreases the priority nest count When this count reaches zero the thread priority of the calling application is set to normal After performing some time critical operation the application should call seEndHighPrior ity to return the thread priority to a normal level None The priority nest count which is the number of times seBeginHighPriority has been called without a corresponding call to seEndHighPriority Programming Notes and Examples S1D13706 Issue Date 01 02 23 X31B G 003 03 Page 76 int seSetClock CLOCKSELECT ClockSelect FREQINDEX FreqIndex Description Parameters Return V
444. n on page 14 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping S1D13706 Pin Name SA 1110 AB 16 1 A 16 1 ABO nCASO DB 15 0 D 15 0 WE1 nCAS1 M R A17 CS nCS4 CLKI SDCLK2 BS Vop RD WR Vop RD nOE WEO nWE WAIT RDY RESET system RESET Interfacing to the Intel StrongARM SA 1110 Microprocessor 1D13706 Issue Date 02 06 26 X31B G 019 02 Page 12 Epson Research and Development Vancouver Design Center 3 2 Host Bus Interface Signal Descriptions The S1D13706 Generic 2 Host Bus Interface requires the following signals 1D13706 X31B G 019 02 CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example it is driven by one of the SA 1110 signals SDCLK1 or SDCLK2 The example implementation in this document uses SDCLK2 For further information see Section 4 3 StrongARM SA 1110 Register Configuration on page 15 The address inputs AB 16 1 and the data bus DB 15 0 connect directly to the SA 1110 address bus A 16 1 and data bus D 15 0 respectively CNF4 must be set to select little endian mode ABO connects to nCASO the low byte enable signal from the SA 1110 which in conjunction with the high byte ena
445. n HPS t4 min 3 t2min t8min HPS t4min 4 38min HT 5 t4min HPW 6 t5mn HPS 1 7 t6min HPS HDP HDPS 1 5 if negative add t3min 8 t14min HDPS HPS t4min 1 if negative add t3 min Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 66 Epson Research and Development Vancouver Design Center 6 4 5 Single Color 8 Bit Panel Timing Format 1 FPFRAME mae TR FPLINE ERAI FPDAT 7 0 X Invalid LINE1 X LINE2 X LINES X LINE4 X XLINE239 XLINE240 Invalid LINE1 X LINE2 X FPLINE dl HDP HNDP 3 sS S s Ss s s s 2Ts di d 2Ts EPSHIET 2Ts 2T 2Ts 4T 2T 2T 2Ts 2T 2Ts 4Ts 2Ts 2Ts 4Ts 2Ts 4Ts 2Ts 2Ts 4Ts 2Ts 2Ts 4Ts 2Ts 2Ts 4Ts 2Ts FPSHIFT2 a 2Ts 2Ts 4Ts 2Ts 2Ts 2Ts 2Ts 2Ts FPDAT7 imei KAKAA OOOO ADORA ma TX FPDAT6 invalid KEKA ON O OONA EX maia XX FPDATS mi XAXA OOOO COO Ol FPDAT4 invalid XAXA EAO OOOO XOXOXO XE rs XX FPDAT3 maid iain ow View Yad van VY XXX KOOOCX Dex invalid X FPDAT2 Iwai XAAR XOXO ADO nais X FPDAT1 Ina KAKAA OO OOOO OOOO OOE a FPDATO Imai XAA OOOO OOOO tral 0 Notes The duty cycle of FPSHIFT changes in order to pr
446. n Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Windows CE 3 x Display Drivers X31B E 006 01 Issue Date 01 05 25 Epson Research and Development Page 3 Vancouver Design Center WINDOWS CE 3 x DISPLAY DRIVERS The Windows CE 3 x display driver is designed to support the S1D13706 Embedded Memory LCD Controller running the Microsoft Windows CE operating system version 3 0 The driver is capable of 4 8 and 16 bit per pixel landscape modes no rotation and 8 and 16 bit per pixel SwivelView 90 degree 180 degree and 270 degree modes This document and the source code for the Windows CE drivers are updated as appropriate Before beginning any development please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd epson com for the latest revisions We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Windows CE 3 x Displa
447. n and sub windows are rotated 90 counter clockwise when shown on the panel The images for each window are typically placed consecutively with the main window image starting at address 0 and followed by the sub window image In addition both images must start at addresses which are dword aligned the last two bits of the starting address must be 0 Note It is possible to use the same image for both the main window and sub window To do so set the sub window line address offset registers to the same value as the main win dow line address offset registers Note The Sub Window X Start Position registers Sub Window Y Start Position registers Sub Window X End Position registers and Sub Window Y End Position registers are named according to the Swivel View 0 orientation In Swivel View 90 these registers switch their functionality as described in Section 8 2 Registers Example 6 In SwivelView 90S program the main window and sub window registers for a 320x240 panel at 4 bpp with the sub window positioned at Swivel View 90 coordinates 60 80 with a width of 120 and a height of 160 1 Confirm the main window coordinates are valid The vertical coordinates must be a multiple of 32 bpp 240 32 4 30 Main window vertical coordinate is valid Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 52 1D13706 X31B G 003 03 Epson Research and Development Vancouver Design C
448. nce tab contains settings pertaining to the initial display state During runtime these settings may be changed Panel SwivelView The S1D13706 SwivelView feature is capable of rotating the image displayed on an LCD panel 90 180 or 270 in a counter clockwise direction This sets the initial orientation of the panel Panel Invert The S1D13706 can invert the display data going to the LCD panel The display data is inverted after the Look Up Table S W Invert Enable The Video Invert feature can be controlled by software using REG 70h bit 4 When this box is checked the Software Video Invert bit is set to one and video data is inverted If the box is unchecked the bit is set to zero and video data remains normal H W Invert Enable The Video Invert feature can be controlled by hardware if the GPIOO is available Hardware control is not possible if a HR TFT or D TFD panel is used as both panels use GPIOO as an LCD control signal Panel Color Depth Sets the initial color depth on the LCD panel 13706CFG Configuration Program S1D13706 Issue Date 01 03 29 X31B B 001 03 Page 10 Clocks Tab 1D13706 X31B B 001 03 PCLK Source 51D13706 Configuration Utility File Help CLKI MHz Timing Auto Auto 50 000 MHz Timing Auto y Auto 50 000 MHz ELKI2 MH gt dewi affect th allowable choices for panel frame rates After making changes make sure t
449. nd Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Intel StrongARM SA 1110 Microprocessor X31B G 019 02 Issue Date 02 06 26 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13706 Embedded Memory LCD Controller and the Intel StrongARM SA 1110 Microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Research and Development website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the Intel StrongARM SA 1110 Microprocessor 1D13706 Issue Date 02 06 26 X31B G 019 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the StrongARM SA 1110 Bus 2 1 The StrongARM SA 1110 System Bus The StrongARM SA 1110 microprocessor is a highly integrated communications micro controller that incorporates a 32 bit StrongARM RISC processor core The SA 1110 is ideally suited to interface to the S1D13706 LCD controller and provides a high perfor mance power efficient solution for embedded systems 2 1 1 StrongARM SA 1
450. nd PCI Bridge Adapter board Intel Windows platform only ERR_FAILED Could not free memory Description Reads the 1D13706 revision code register to determine the controller product and revi sion Parameters pld A pointer to an integer to receive the controller ID The value returned is the revision code Return Value ERR_OK The operation completed with no problems ERR_UNKNOWN_DEVICE The product code was not for the S1D13706 Programming Notes and Examples S1D13706 Issue Date 01 02 23 X31B G 003 03 Page 68 Epson Research and Development Vancouver Design Center 10 2 1 General HAL Support This category of HAL functions provide several essential services which do not readily group with other functions DWORD seGetinstalledMemorySize void Description This function returns the size of the display buffer in bytes For the S1D13706 seGetInstalledMemorySize and seGetAvailableMemorySize return the same value Parameters None Return Value The return value is the size of the display buffer in bytes 1 4000h for the S1D13706 DWORD seGetAvailableMemorySize void Description This function returns an offset to the last byte of memory accessible to an application An application can directly access memory from offset zero to the offset returned by this function On most systems the return value will be the last byte of physical display mem ory For the S1D13706 seGetInstalledMemorySize and seGetAvailableMemorySize
451. nding on the color depth some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels Note 1 These bits have no effect unless the PIP Window Enable bit is set to 1 REG 71h bit 4 2 The effect of REG 84h through REG 9 1h takes place only after REG 91h is written and at the next vertical non display period Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 118 Epson Research and Development Vancouver Design Center REG 8Ch PIP Window X End Position Register 0 Read Write 7 6 PIP Window X End Position Bits 7 0 5 4 3 2 1 0 REG 8Dh PIP Window X End Position Register 1 Read Write T PIP Window X End Position Bits 9 8 5 4 8 2 1 0 n a bits 9 0 1D13706 X31B A 001 08 PIP Window X End Position Bits 9 0 These bits determine the X end position of the PIP window in relation to the origin of the panel Due to the S1D13706 Swivel View feature the X end position may not be a horizontal position value only true in 0 and 180 SwivelView For further information on defining the value of the X End Position register see Section 13 Picture in Picture Plus PIP on page 143 The register is also incremented differently based on the Swivel View orientation For 0 and 180 SwivelView the X end position is incremented by x pixels where x is relative to the
452. ndows will detect the card as a new PCI Device and launch the UPDATE DEVICE DRIVER wizard If The Driver is on Floppy Disk 3 4 5 6 Place the disk into drive A and click NEXT Windows will find the EPSON PCI Bridge Card Click FINISH to install the driver Windows will ask you to restart the system If The Driver is not on Floppy Disk 3 4 10 11 12 13 14 15 16 17 Click NEXT Windows will search the floppy drive and fail Windows will attempt to load the new hardware as a Standard VGA Card Click CANCEL The Driver must be loaded from the CONTROL PANEL under ADD NEW HARDWARE Select NO for Windows to DETECT NEW HARDWARE Click NEXT Select OTHER DEVICES from HARDWARE TYPE and Click NEXT Click HAVE DISK Specify the location of the driver and click OK Click OK EPSON PCI Bridge Card will appear in the list Click NEXT Windows will install the driver Click FINISH Windows will ask you to restart the system Windows will re detect the card and ask you to restart the system S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 Epson Research and Development Page 7 Vancouver Design Center All ISA Bus Evaluation Cards Install the evaluation board in the computer and boot the computer Go to the CONTROL PANEL and select ADD NEW HARDWARE Click NEXT Select NO and click NEXT Select OTHER DEVICES and click NEXT Click Have Disk Specify the location
453. ne address offset number of dwords per line image width 32 bpp 320 32 4 40 28h Program the Main Window Line Address Offset registers REG 78h is set to 28h and REG 79h is set to 00h Determine the sub window display start address The main window image must take up 320 x 240 pixels 2 pixels per byte 9600h bytes If the main window starts at address Oh the sub window can start at 9600h sub window display start address desired byte address 4 9600h 4 2580h Program the Sub window Display Start Address register REG 7Ch is set to 80h REG 7Dh is set to 25h and REG 7Eh is set to 00h Determine the sub window line address offset number of dwords per line image width 32 bpp 160 32 4 20 14h Program the Sub window Line Address Offset register REG 80h is set to 14h and REG 81h is set to 00h S1D13706 X31B G 003 03 Page 50 1D13706 X31B G 003 03 Epson Research and Development Vancouver Design Center 7 Determine the value for the sub window X and Y start and end position registers Let the top left corner of the sub window be x1 y1 and let x2 x1 width y2 yl height The X position registers set the horizontal coordinates of the sub window top left and bottom right corners Program the X Start Position registers x1 32 bpp Pro gram the X End Position registers x2 32 bpp 1 The Y position registers in landscape mode set the v
454. ned with external LCD controller support and Windows CE based embedded consumer applications in mind the VR4102 VR4111 offers a highly integrated solution for portable systems This section is an overview of the operation of the CPU bus to establish interface requirements The NEC VR series microprocessor is designed around the RISC architecture developed by MIPS The VR4102 microprocessor is designed around the 66MHz VR4100 CPU core and the VR4111 is designed around the 80 100MHz VR4110 core These microprocessors support 64 bit processing The CPU communicates with the Bus Control Unit BCU through its internal SysAD bus The BCU in turn communicates with external devices with its ADD and DATA busses which can be dynamically sized for 16 or 32 bit operation The NEC VR4102 VR4111 can directly support an external LCD controller through a dedicated bus interface Specific control signals are assigned for an external LCD controller in order to provide an easy interface to the CPU A 16M byte block of memory is assigned for the LCD controller with its own chip select and ready signals available Word or byte accesses are controlled by the system high byte signal SHB Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 01 02 23 Epson Research and Development Page 9 Vancouver Design Center 2 1 2 LCD Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus ADD 25 0 the LCD chip s
455. ner Program the Y Start Position registers x1 32 bpp Pro gram the Y End Position registers x2 32 bpp 1 X start position registers 320 80 160 80 50h Y start position registers 64 32 4 08h X end position registers 320 80 1 239 EFh Y end position registers 64 120 82 4 1 22 16h Program the Sub window X Start Position registers REG 84h is set to 50h and REG 85h is set to 00h Program the Sub window Y Start Position registers REG 88h is set to 08h and REG 89h is set to 00h Program the Sub window X End Position registers REG 8Ch is set to EFh and REG 8Dh is set to 00h Program the Sub window Y End Position registers REG 90h is set to 16h and REG 91h is set to OOh 8 Enable the sub window Program the Sub window Enable bit REG 71h bit 4 is set to 1 Programming Notes and Examples S1D13706 Issue Date 01 02 23 X31B G 003 03 Page 60 8 4 Limitations Epson Research and Development Vancouver Design Center 8 4 1 SwivelView 0 and 180 In SwivelView 0 and 180 the main window line address offset register requires the panel width to be a multiple of 32 bits per pixel If this is not the case then the main window line address offset register must be programmed to a longer line which is a multiple of 32 bits per pixel This longer line creates a virtual image where the width is main window line address offset register x 32 bits per pixel and t
456. ng 2 2 5 4 5 REDCAP2 Chip Select Configuration 2 2 42 2 16 SoftWare ds 5 Segre ete ae veh a ah eae be Bend os eter eae ae ad aa 17 References us kee te at Arne Ad SR ed ara A ee Berm cat wa 18 Hi DOCUMENTS a 4 il oe be MB oP ee ob ok we PA obi he A Ge te odie we See AS 6 2 DocumentSources 2 1 ee ee ee 18 7 Technical Support tii e o et ee Se ee EE he a et At 19 7 1 EPSON LCD CRT Controllers S1D13706 02 2 2 2 2 2 19 7 2 Motorola REDCAP2 Processor ee ee ee ee ee 19 Interfacing to the Motorola RedCap2 DSP With Integrated MCU S1D13706 Issue Date 01 02 23 X31B G 014 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 02 Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 10 Table 4 1 List of Connections from REDCAP2 ADM to S5U13706BOO0C 13 Table 4 2 Summary of Power On Reset Options e e 15 List of Figures Figure 2 1 REDCAP2 Memory Read Cycle o o a 9 Figure 2 2 REDCAP2 Memory Write Cycle 0 o 000000000000 9 Figure 4 1 Typical Implementation of REDCAP2 to S1D13706 Interface 12 Interfacing to the Motorola RedCap2 DSP With Integrated MCU S1D13706 Issue
457. ng Page 73 FPFRAME FPLINE FPDAT 17 0 DRDY FPLINE FPSHIFT DRDY FPDAT 17 0 Note DRDY is used to indicate the first pixel VNDP ee LINE240 A LINE1 X gt LINE480 HDP invalid Example Timing for 18 bit 320x240 panel VDP VNDP VNDP1 VNDP2 HDP HNDP HNDP1 HNDP2 Hardware Functional Specification Issue Date 01 11 13 Vertical Display Period VDP Lines Vertical Non Display Period VNDP1 VNDP2 VT VDP Lines Vertical Non Display Period 1 VNDP VNDP2 Lines Vertical Non Display Period 2 VDPS VPS Lines Horizontal Display Period HDP Ts Horizontal Non Display Period HNDP1 HNDP2 HT HDP Ts Horizontal Non Display Period 1 HDPS HPS Ts Horizontal Non Display Period 2 HPS HDP HDPS Ts Figure 6 28 18 Bit TFT Panel Timing if negative add VT if negative add HT if negative add HT S1D13706 X31B A 001 08 Page 74 Epson Research and Development Vancouver Design Center t1 t2 4 gt FPFRAME J t3 me Ue US y E u t4 lt 4 gt FPLINE J L t5 t8 t6 t7 lt Label gt DRDY J t9 t12 t13 t14 t10 t11 EN aE PUPA t15 z 1 1 FPDAT 17 0 invalid 1 2 ad 320 invalid Note DRDY is used to indicate the
458. ng characteristics e reinforced land type footprint e 4 reinforced pads land size 1 05mm 042 in diameter e 104 pads e land size 0 3mm 0 012 in diameter e distributed on a 11 x 11 grid with a 0 65mm 0 025 pitch e solder mask 0 43mm 0 017 in diameter Note The reinforcement pads located in the corner of the footprint provide extra mechanical strength once the chip has been mounted For pinout diagrams and mechanical drawings see the S D13706 Hardware Functional Specification document number X31B A 001 xx 1D13706 Integrating the CFLGA 104 pin Chip Scale Package X31B G 018 02 Issue Date 01 02 26 Epson Research and Development Page 7 Vancouver Design Center 3 Routing 3 1 Perimeter Pads Perimeter pads of the S1D13706 CSP are usually fanned out on the top layer using 0 004 traces with 0 0045 spaces at the passage between pads The traces are terminated using standard via technology i e 0 025 via with 0 012 hole The following diagram shows an example for perimeter pad routing Figure 3 1 Example Perimeter Pad Routing Integrating the CFLGA 104 pin Chip Scale Package 1D13706 Issue Date 01 02 26 X31B G 018 02 Page 8 Epson Research and Development Vancouver Design Center 3 2 Inner Pads The inner pads on top layer require microvias connecting them with the microvia specific layer located just below the top layer The pads on the microvia specific layer have a land size of
459. nics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor 1D13706 Issue Date 01 02 26 X31B G 016 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MC68VZ328 2 1 The MC68VZ328 System Bus The Motorola MC68VZ328 Dragonball VZ is the third generation in the Dragonball microprocessor family The Dragonball VZ is an integrated controller designed for handheld products It is based upon the FLX68000 microprocessor core and uses a 24 bit address bus and 16 bit data bus The Dragonball VZ is faster than its predecessors and the DRAM controller now supports SDRAM The bus interface consists of all the standard MC68000 bus interface signals except AS plus some new signals intended to simplify the interface to typical memory and peripheral devices The 68000 signals are multiplexed with IrDA SPI and LCD controller signals The MC68000 bus control signals are well documented in the Motorola user manuals and are not be described here The new signals are as follows e Output Enable OE is asserted when a read cycle is in progress It is intended to connect to the output enable control signal of a typical static RAM EPROM or Flash EPROM device e Upper Write En
460. notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the NEC VR4181A Microprocessor X31 B G 008 02 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T Introductions a sara ias A AAA ada a 7 2 Interfacing to the NEC VR4181A 8 2 1 The NEC VR4181A System Bus 2 2 8 DIJE COVEVIEW sid eos dd Bed aio Bop acca ta a hades Boe be 8 2 1 2 LCD Memory Access Signals aaa aa ee 9 3 1D13706 Host Bus Interface 2 2 ee ee 10 3 1 Host Bus Interface Pin Mapping LO 3 2 Host Bus Interface Signals oo 2 a g a ee ee 11 4 VR4181A to S1D13706 Interface 12 4 1 Hardware Description 1 2 ee 1 4 22 S1D13706 Hardware Configuration 2 2 eee ee eee 13 4 3 NEC VR4181A Confi
461. nout Assignments Die Form SIDI3706D00A Pin No Pad No Pin Name X um Y um Pin No Pad No Pin Name X um Y um VDD 3149 9 VDD 8 66 2 3 AB3 2100 3149 52 122 FPFRAME 2100 3149 3 5 AB2 1932 3149 53 124 FPLINE 1932 3149 4 8 AB 1680 3149 54 127 FPSHIFT 1680 3149 5 10 ABO 1512 3149 55 129 FPDATO 1512 3149 6 12 CS 1344 3149 56 131 FPDAT1 1344 3149 7 15 M R 1092 3149 57 134 FPDAT2 1092 3149 8 17 BS 924 3149 58 136 FPDAT3 924 3149 9 20 RD 672 3149 59 139 FPDAT4 672 3149 10 22 WEO 504 3149 60 141 FPDAT5 504 3149 11 24 WE1 336 3149 61 143 FPDAT6 336 3149 12 27 RD WR 84 3149 62 146 VSS 84 3149 13 29 RESET 84 3149 63 148 HVDD 84 3149 14 31 VSS 252 3149 64 150 FPDAT7 252 3149 15 34 CLKI 504 3149 65 153 FPDAT8 504 3149 16 36 HVDD 672 3149 66 155 FPDAT9 672 3149 17 39 WAIT 924 3149 67 158 FPDAT10 924 3149 18 41 DB15 1092 3149 68 160 FPDATT1 1092 3149 19 43 DB14 1260 3149 69 162 FPDAT12 1260 3149 20 46 DBT3 1512 3149 70 165 FPDAT13 1512 3149 21 48 DB12 1680 3149 71 167 FPDAT14 1680 3149 22 50 DBT1 1848 3149 72 169 FPDAT15 1848 3149 23 53 DB10 2100 3149 73 172 FPDAT16 2100 3149 24 55 DB9 2331 3149 74 174 FPDAT17 2331 3149 25 58 VSS 2813 2478 75 177 VSS 2813 2478 26 60 HVDD 2813 2310 76 179 HVDD 2813 2310 27 62 DB8 2813 2142 77 181 CLKT2 2813 2142 28 65 DB7 2813 1890 78 184 CNF7 2813 1890 29 67 DB6 2813 1722 79 186 CNF6 28
462. nt is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction a ca a a HGP ee a as ea a eG 11 EI ISC s i o Ge Boies oe Ae oe oe A A A hs Ye Se oe ee lll 1 2 Overview Description e e a a ee ee 11 2 FOUR e IS a pe aes BS A a ke eA ER ee amp a 12 2 1 Integrated Frame Buffer 2 2 ee 12 2 2 CPU Interface boda oly By Bede ee ep os Git Gd Ble Ut a te gp ep TD 2 3 Display Support g siec s a 4 a koh aoa i aala a a ad 12 2 4 Display Modes 2 20 Je oia ee e ee ee a 20 Display Features soanar g Ca Yan ene at eet at Gs a UE ee a Ss Se ca os 13 26 gt gt Clock Sourcen Gas a ea Ga we ds ae oe a A Sear edt we Ba ae a or dS 2 7 Miscellaneous s ceo ene a o a
463. o Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http Awww epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http Awww eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http Awww epson electronics de Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Hardware Functional Specification Issue Date 01 11 13 S1D13706 X31B A 001 08 Page 154 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 EPSON 1D13706 Embedded Memory LCD Controller Programming Notes and Examples Document Number X31B G 003 03 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this docu
464. o accommodate the need for power reduction in the hand held devices market This mode is enabled via the Power Save Mode Enable bit REG AOh bit 0 Software Power Save Mode saves power by powering down the panel and stopping display refresh accesses to the display buffer Table 15 1 Power Save Mode Function Summary Software Normal Power Save IO Access Possible Yes Yes Memory Writes Possible Yes Yes Memory Reads Possible No Yes Look Up Table Registers Access Possible Yes Yes Sequence Controller Running No Yes Display Active No Yes LCD I F Outputs Forced Low Active PWMCLK Stopped Active GPIO Pins configured for HR TFT D TFD Forced Low Active GPIO Pins configured as GPIOs Access Possible Yes Yes Note 1 When power save mode is enabled the memory controller is powered down and the status of the memory controller is indicated by the Memory Controller Power Save Sta tus bit REG AOh bit 3 However memory writes are possible during power save mode because the S1D13706 dynamically enables the memory controller for display buffer writes 2 GPIO Pins are configured using the configuration pin CNF3 which is latched on the rising edge of RESET For information on CNF3 see Table 4 8 Summary of Power On Reset Options on page 29 3 GPIOs can be accessed and if configured as outputs can be changed After reset the S1D13706 is always in Power Save Mode Software must initi
465. o go to Panel section for the change to take effect Source CLKI2 Timing 6 250 MHz BCLK Source cur Timing 50 000 MHz m MELK Source BCLK Divide Auto hd EIN Kg Epson Research and Development PCLK Divide I Enable Force High Vancouver Design Center PWMCLK Force High PWMCLK Source cLKI y lt Source PWMCLK Divide Divide E ME Timing 50 000 MHz Duty cycle o y PWMCLK C CV Pulse Enable Contrast Voltage Pulse MT Enable I Force High A Src P CLKI Force Hi CV Pulse Divide of pulses in a burst MCLK Divide Divide E x lt Timing 50 000 MHz aida Burst Length 1 hs 4 Burst Length The Clocks tab is intended to simplify the selection of input clock frequencies and the source of internal clocking signals For further information regarding clocking and clock sources refer to the S D13706 Hardware Functional Specification document number X31B A 001 xx In automatic mode the values for CLKI and CLKI are calculated based on selections made for LCD timings from the Panel tab In this mode the required frequencies for the input clocks are displayed in blue in the Auto section of each group It is the responsibility of the system designer to ensure that the correct CLKI frequencies are supplied to the S1D13706 Makin
466. o provide sufficient screen refresh as well as acceptable CPU cycle latency The source clock options for MCLK may be selected as in the following table Table 7 2 MCLK Clock Selection Source Clock Options MCLK Selection BCLK REG 04h bit 5 4 00 BCLK 2 REG 04h bit 5 4 01 BCLK 3 REG 04h bit 5 4 10 BCLK 4 REG 04h bit 5 4 11 1D13706 X31B A 001 08 Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Vancouver Design Center 7 1 3 PCLK Page 91 PCLK is the internal clock used to control the LCD panel PCLK should be chosen to match the optimum frame rate of the LCD panel See Section 9 Frame Rate Calculation on page 130 for details on the relationship between PCLK and frame rate Some flexibility is possible in the selection of PCLK Firstly LCD panels typically have a range of permissible frame rates Secondly it may be possible to choose a higher PCLK frequency and tailor the horizontal and vertical non display periods to lower the frame rate to its optimal value The source clock options for PCLK may be selected as in the following table Table 7 3 PCLK Clock Selection Source Clock Options PCLK Selection MCLK REG 05h 00h MCLK 2 REG 05h 10h MCLK 3 REG 05h 20h MCLK 4 REG 05h 30h MCLK 8 REG 05h 40h BCLK REG 05h 01h BCLK 2 REG 05h 11h BCLK 3 R
467. oad the source from ftp ftp kernel org The S1D13706 reference driver requires Linux kernel 2 4 x or greater The example S1D13706 reference driver available on www erd epson com was built using Red Hat Linux 6 1 kernel version 2 4 5 For information on building the kernel refer to the readme file at ftp ftp linuxberg com pub linux kernel README Note Before continuing with modifications for the S1D 13706 you should ensure that you can build and start the Linux operating system 2 Unzip the console driver files Using a zip file utility unzip the S1D13706 archive to a temporary directory e g tmp When completed the files Config in fbmem c fbcon cfb4 c Makefile should be located in the temporary directory tmp and the files Makefile s1d13xxxfb c s1d13706 h should be located in a sub directory called epson within the temporary directory tmp epson 3 Copy the console driver files to the build directory Make the directory usr src linux drivers video epson Copy the files tmp epson s1d13xxxfb c tmp epson s1d13706 h tmp epson Makefile to the directory usr src linux drivers video epson 1D13706 X31B E 004 02 Page 8 Epson Research and Development Vancouver Design Center Copy the remaining source files tmp Config in tmp fbmem c Itmp fbcon cfb4 c tmp Makefile into the directory usr src linux drivers video replacing the files of the same name If your kernel version is not 2 4 5 or you wan
468. ocess 16 pixels in 6 FPSHIFT FPSHIFT2 rising edges Ts Pixel clock period PCLK Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 6 21 Single Color 8 Bit Panel Timing Format 1 VDP Vertical Display Period REG 1 Dh bits 1 0 REG 1Ch bits 7 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 19h bits 1 0 REG 18h bits 7 0 REG 1 Dh bits 1 0 REG 1Ch bits 7 0 Lines HDP Horizontal Display Period REG 14h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 67 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE A t6a t6b t8 t9 t7a t14 t11 t10 gt 4 gt FPSHIFT P t7b J FPSHIFT2 112113 112113 FPDAT 7 0 LAS X Figure 6 22 Single Color 8 Bit Panel A C Timing Format 1 Table 6 20 Single Color 8 Bit Panel A C Timing Format 1 Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t6a FPSHIFT falling edge to FPLINE rising
469. ock If the memory allocation succeeds then the return value is the linear address of the allo cated memory If the allocation fails then the return value is 0 A linear address is a 32 bit offset in CPU address space int seFreeSurface DWORD LinearAddress Description Parameters Return Value 1D13706 X31B G 003 03 This function can be called to free any previously allocated display buffer memory This function is intended to complement seAllocMainWinSurface and seAllocSubWin Surface After calling one of these functions the application must switch the active surface to one which has memory allocated before calling any drawing functions LinearAddress A valid linear address The linear address is a dword returned to the application by any surface allocation call ERR_OK Function completed successfully ERR_FAILED Function failed Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 79 Vancouver Design Center void seSetMainWinAsActiveSurface void void seSetSubWinAsActiveSurface void Description These functions set the active surface to the display indicated in the function name Before calling one of these surface selection routines that surface must have been allo cated using any of the surface allocation functions Parameters None Return Value None void sePwmEnable int Enable Description This function enables or disables the Pulse Width Modulation
470. odify write cycles of 4 bpp are eliminated making the update of each pixel faster Each byte indexes into one of the 256 positions of the LUT The S1D13706 LUT supports six bits per primary color This translates into 256K possible colors when color mode is selected Therefore the displayed mode has 256 colors available out of a possible 256K colors When a monochrome panel is selected the green component of the LUT is used to determine the gray shade intensity The green indices with six bits can resolve 64 gray shades 3 6 Memory Organization for 16 Bpp 65536 Colors 64 Gray Shades Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Red Component Green Component Bits 4 0 Bits 5 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Green Component Blue Component Bits 2 0 Bits 4 0 1D13706 Figure 3 5 Pixel Storage for 16 Bpp in Two Bytes of Display Buffer At acolor depth of 16 bpp the 1D13706 is capable of displaying 64K 65536 colors The 64K color pixel is divided into three parts five bits for red six bits for green and five bits for blue In this mode the LUT is bypassed and output goes directly into the Frame Rate Modulator Should monochrome mode be chosen at this color depth the output sends the six bits of the green LUT component to the modulator for a total of 64 possible gray shades Note that 8 bpp also provides 64 gray shades using less memor
471. of its internal registers to interface to the S1D13706 Generic 2 Host Bus Interface The Static Memory Control Registers MSC 2 0 are read write registers containing control bits for configuring static memory or variable latency IO devices These regis ters correspond to chip select pairs nCS 5 4 nCS 3 2 and nCS 1 0 respectively Each of the three registers contains two identical CNFG fields one for each chip select within the pair Since only nCS 5 3 controls variable latency IO devices MSC2 and MSC1 should be programmed based on the chip select used Parameter RTx lt 1 0 gt should be set to 01b selects variable latency IO mode Parameter RB Wx should be set to 1 selects 16 bit bus width Parameter RDFx lt 4 0 gt should be set according to the maximum desired CPU frequency as indicated in the table below Table 4 3 RDFx Parameter Value versus CPU Maximum Frequency CPU Frequency MHz RDFx 57 3 85 9 1 88 5 143 2 2 147 5 200 5 3 206 4 221 2 4 Parameter RDNx lt 4 0 gt should be set to 0 minimum command precharge time Parameter RRRx lt 2 0 gt should be set to 0 minimum nCSx precharge time The S1D13706 endian mode is set to little endian To program the SA 1110 for little endian set bit 7 of the control register register 1 to 0 The CLKI signal input to the 1D13706 from one of the SDCLK 2 1 pins is a deriva tive of the SA 1110 internal processor speed either divide by 2 or 4
472. of the driver files and click OK Click Next Click Finish Previous Versions of Windows 95 All PCI Bus Evaluation Cards 1 Ze Install the evaluation board in the computer and boot the computer Windows will detect the card Select DRIVER FROM DISK PROVIDED BY MANUFACTURER Click OK Specify a path to the location of the driver files Click OK Windows will find the S1D13XXX INF file Click OK Click OK and Windows will install the driver S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 X00A E 003 04 Page 8 Epson Research and Development Vancouver Design Center All ISA Bus Evaluation Cards X00A E 003 04 10 11 12 13 Install the evaluation board in the computer and boot the computer Go to the CONTROL PANEL and select ADD NEW HARDWARE Click NEXT Select NO and click NEXT Select OTHER DEVICES from the HARDWARE TYPES list Click HAVE DISK Specify the location of the driver files and click OK Select the file SID13XXX INF and click OK Click OK The EPSON PCI Bridge Card should be selected in the list window Click NEXT Click NEXT Click Finish S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 EPSON 1D13706 Embedded Memory LCD Controller S5U13706B00C Rev 1 0 Evaluation Board User Manual Document Number X31B G 004 04 Copyright 2001 Epson Research and Development Inc All Rights Reserved Infor
473. og Power Supplies e ee ee 9 2 1 3 DC Gate Driver Power Supplies seess voona a e e e 9 2 1 4 AC Gate Driver Power Supplies 0 0 2 020000 ee eee 10 2 2 HR TFT MOD Signal A ts A A ran ie eae feo dl ee 2 3 S1D13706 to LQ039Q2DS01 Pin Mapus Ei ae whet A hy ow ca ae E y 3 Connecting to the Sharp LQ031B1DDxx HR TFT lt 14 3 1 External Power Supplies 2 04 05 2 024 ae es 14 3 1 1 Gray Scale Voltages for Gamma Correction 2 0 008 14 3 1 2 Digital Analog Power Supplies aooaa aa ee 15 3 1 3 DC Gate Driver Power Supplies 0 0 00 ee eee 15 3 1 4 AC Gate Driver Power Supplies e 00002 ee eee 15 3 2 HR TFT MOD Signal E ate E ec 8 Oe See Ee ond Se Sh Ge ee he TD 3 3 S1D13706 to LQ031B1DDxx Pin Meda E te ely oe eae MO Test Software e Bot oe eat ae A A a ected Sag 18 REICFENCES ic we Ae ee e a Se A Re EA da 19 Sil Documents oi va es cas a oh ek Ede BE a ts A Bee ak ae wn er i ae Pe Mh ae VO 5 2 Document Sources 4 5 24 4 8 be we eee A ee a da 9 6 Techni al Support ica cada is ee ee 20 6 1 EPSON LCD Controllers S1D13706 gt a a a a a 20 6 2 Sharp HR TET Panel s 3 acre 4g a A AO a a 20 Connecting to the Sharp HR TFT Panels S1D13706 Issue Date 01 02 23 X31B G 011 04 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Connecting
474. ola MC68030 processor SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor MPC821ADS Applications Development System board revision B with a Motorola MPC821 processor 13706CFG Configuration Program S1D13706 Issue Date 01 03 29 X31B B 001 03 Page 6 Installation Usage 1D13706 X31B B 001 03 Epson Research and Development Vancouver Design Center Create a directory for 13706cfg exe and the S1D13706 utilities Copy the files 13706cfg exe and panels def to that directory Panels def contains configuration infor mation for a number of panels and must reside in the same directory as 13706cfg exe 13706CFG can be started from the Windows desktop or from a Windows command prompt To start 13706CFG from the Windows desktop double click the program icon or the link icon if one was created during installation To start 13706CFG from a Windows command prompt change to the directory 13706cfg exe was installed to and type the command 13706cfg The basic procedure for using 13706CFG is 1 Ze Start 13706CFG as described above Open an existing file to serve as a starting reference point this step is optional Modify the configuration For specific information on editing the configuration see 13706CFG Configuration Tabs on page 7 Save the new configuration The configuration information can be saved in two ways as an ASCII text file or by modifying the executable image on disk Several
475. ols these registry values will be made available upon the next release of the display driver preliminary alpha code is available by special request Resource Management Issues The Windows CE 3 0 OEM must deal with certain display driver issues relevant to Windows CE 3 0 These issues require the OEM balance factors such as system vs display memory utilization video performance and power off capabilities The section Simple Display Driver Configuration on page 15 provides a configuration which should work with most Windows CE platforms This section is only intended as a means of getting started Once the developer has a functional system it is recommended to optimize the display driver configuration as described below in Description of Windows CE Display Driver Issues Description of Windows CE Display Driver Issues The following are some issues to consider when configuring the display driver to work with Windows CE 1 When Windows CE enters the Suspend state power off the LCD controller and dis play memory may lose power depending on how the system is designed If display memory loses power all images stored in display memory are lost If power off power on features are required the OEM has several options e If display memory power is turned off add code to the display driver to save any images in display memory to system memory before power off and add code to restore these images after power on e If displ
476. om 1D13706 SYSCLK is the prescalable bus clock optional Once an address in the LCD block of memory is accessed the LCD chip select LCDCS is driven low The read or write enable signals HMEMRD or MEMWR are driven low for the appropriate cycle and IORDY is driven low by the S1D13706 to insert wait states into the cycle The high byte enable UBE is driven low for 16 bit transfers and high for 8 bit transfers Interfacing to the NEC VR4181A Microprocessor 1D13706 Issue Date 01 02 23 X31B G 008 02 Page 10 Epson Research and Development Vancouver Design Center 3 S1D13706 Host Bus Interface The S1D13706 directly supports multiple processors The S1D13706 implements a 16 bit Generic 2 Host Bus Interface which is most suitable for direct connection to the NEC VR4181A microprocessor Generic 2 supports an external Chip Select shared Read Write Enable for high byte and individual Read Write Enable for low byte The Generic 2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 13 3 1 Host Bus Interface Pin Mapping S1D13706 X31B G 008 02 The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping Set
477. omponent of the Look Up Table LUT For color panels the 4 colors are derived by indexing into the first 4 positions of the LUT 3 4 Memory Organization for Four Bit per pixel 16 Colors Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Bits 3 0 Pixel 1 Bits 3 0 Programming Notes and Examples Issue Date 01 02 23 Figure 3 3 Pixel Storage for 4 Bpp in One Byte of Display Buffer At a color depth of 4 bpp each byte of display buffer contains two adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the upper or lower nibble 4 bits and setting the appropriate bits to 1 Four bit pixels provide 16 gray shades color possibilities For monochrome panels the gray shades are generated by indexing into the first 16 elements of the green component of the Look Up Table LUT For color panels the 16 colors are derived by indexing into the first 16 positions of the LUT 1D13706 X31B G 003 03 Page 16 Epson Research and Development Vancouver Design Center 3 5 Memory Organization for 8 Bpp 256 Colors 64 Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Bits 7 0 Figure 3 4 Pixel Storage for 8 Bpp in One Byte of Display Buffer At a color depth of 8 bpp each byte of display buffer represents one pixel on the display At this color depth the read m
478. on For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 14 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping al Motorola MCF5307 AB 16 0 A 16 0 DB 15 0 D 31 16 WE1 BWE1 CS CS4 M R A17 CLKI BCLKO BS Connect to HIO Vpp RD WR OE RD OE WEO BWEO WAIT TA RESET system RESET Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13706 Issue Date 01 02 23 X31B G 010 02 Page 12 Epson Research and Development Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface requires the following signals 1D13706 X31B G 010 02 CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example BCLKO from the Motorola MCF5307 is used for CLKI The address inputs AB 16 0 connect directly to the MCF5307 address bus A 16 0 DB 7 0 connects D 23 16 the MCF5307 low order byte DB 15 8 connects to D 31 24 the MCF5307 high order byte CNF4 must be set to select big endian mode Chip Select CS must be driven low by CS4 whenever the S1D13706 is accessed by the Motorola MCF5307 M R memory register selects between memory or register ac
479. on gt aa ARA AAA ad wR Oar Es 7 2 Interfacing to an 8 bit Processor lt lt 8 2 1 The Generic 8 bit Processor System Bus ee ee eee 8 3 1D13706 Host Bus Interface 9 3 1 Host Bus Interface Pin Mapping 2 2 2 2 2 9 3 2 Host Bus Interface Signals 2 2 ee 10 4 8 Bit Processor to S1D13706 Interface lt lt lt ee ee 11 4 1 Hardware Connections 2 ee a eee 11 4 2 S1D13706 Hardware Configuration 2 2 ee ee eee ee 12 4 3 Register Memory Mapping 2 2054 42 12 SoftWare te a hry pa ae en acne ase gs ead Rene an alors Hy da Geena arate 13 Referenc s sa hor de i eT ER ee AA 14 6 1 Documents 2 a a a ee ee eee ee 14 6 2 Document Sources 2 2 ee ee ee ee ee ew 14 Y Technical Support s 2 222 202 ER eee ee de wee ee ee ee 15 7 1 EPSON LCD Controllers S1D13706 15 Interfacing to 8 bit Processors 1D13706 Issue Date 01 02 23 X31B G 015 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to 8 bit Processors X31B G 015 02 Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 2 e 9 Table 4 2 CLKI to BCLK Divide Selection o o e
480. on applications like a simple HelloApp for a new target platform requires the following e HelloApp code e 13706HAL library LIBSE library which contains target specific code for embedded platforms HelloApp Source code LIBSE for embedded platforms HelloApp 13706HAL Library Figure 10 1 Components needed to build 13706 HAL application For example when building HELLOAPP EXE for the x86 windows 32 bit platform you need the HELLOAPP source files the 13706HAL library and its include files and some Standard C library functions which in this case would be supplied by the compiler as part of its run time library As this is a 32 bit windows EXE application you do not need to supply start up code that sets up the chip selects or interrupts etc What if you wanted to build the application for an SH 3 target one not running windows Before you can build that application to load onto the target you need to build a C library for the target that contains enough of the target specific code like putch and getch to let you build the application Epson supplies the LIBSE for this purpose but your compiler may come with one included You also need to build the 13706HAL library for the target This library is the graphics chip dependent portion of the code Finally you need to build the final application linked together with the libraries described earlier The following examples assume that you have a co
481. on to Win32 WCE x86 Release a From the Build menu select Set Active Configuration b Select MYPLATFORM Win32 WCE x86 Release c Click the OK button Add the environment variable CEPC_DDI_S1D13X0X a From the Platform menu select Settings b Select the Environment tab c Inthe Variable box type CEPC_DDI_S1D13X0X Windows CE 3 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 5 Vancouver Design Center d Inthe Value box type 1 e Click the Set button f Click the OK button 7 Create a new directory S1D13706 under x wince300 platform cepc drivers display and copy the 1D13706 driver source code into this new directory 8 Add the 1D13706 driver component a From the Platform menu select Insert User Component b Set Files of type to All Files c Select the file x wince300 platform cepc drivers display S 1D13706 sources d Inthe User Component Target File dialog box select browse and then select the path and the file name of sources 9 Delete the component ddi_flat a In the Workspace window select the ComponentView tab b Show the tree for MYPLATFORM components by clicking on the sign at the root of the tree c Right click on the ddi_flat component d Select Delete e From the File menu select Save Workspace 10 From the Workspace window click on Paramete
482. ons from MPC821ADS to S1D13706 16 CLKI to BCLK Divide Selection 0 0 0 00 00 00 0000000000834 18 Summary of Power On Reset Configuration Options 4 18 List of Figures Power PC Memory Read Cycle o o e e 9 Power PC Memory Write Cycle o e ee 10 GPCM Memory Devices Timing e 12 Typical Implementation of MPC821 to S1D13706 Interface 15 S1D13706 X31B G 009 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 02 Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and the Motorola MPC821 microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Motorola MPC821 Microprocessor S1D13706 Issue Date 01 02 23 X31B G 009 02 Page 8 Epson Researc
483. or register accesses This signal may be connected to an address line allowing system address A17 to be connected to the M R line Note If A17 is unavailable on the 8 bit processor an external decode must be used to gen erate the M R signal BHE is the high byte enable for both read and write cycles and connects to the high byte chip select signal Note In an 8 bit environment this signal is driven by inverting address line AO thus indi cating that odd addresses are to be read write on the high byte of the data bus WE connects to WE the write enable signal and must be driven low when the 8 bit processor is writing data to the S1D13706 RD connects to RD the read enable signal and must be driven low when the 8 bit processor is reading data from the S1D13706 WAIT is a signal output from the S1D13706 that indicates the 8 bit processor must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU bus accesses to the S1D13706 may occur asynchronously to the display update it 1s possible that contention may occur in accessing the 13706 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read Write RD WR signals are not used in this implemen tation of a g
484. ory LCD Controller Interfacing to the NEC VR4102 VR4111 Microprocessors Document Number X31B G 007 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 02 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center Table of Contents ft gt INtFOdUCTION s ra se he AR A A A A 7 2 Interfacing to the NEC VR4102 VR4111 8 2 1 The NEC VR41XX System Bus 2 2 8 Qk COVEN EW coat and ada dk ae De head Be daa 8 2 1 2 LCD Memory Access Cycles 2 2 20 00 02 ee ee 9 3 S1D13706 Host Bus Interface es 10 3 1 Host Bus Interface Pin Mapping LO 3 2 Host Bus Interface Signals
485. ot critical nor does it have to be synchronous to the bus signals it may be the same as CLKI2 BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO Vpp The following diagram shows a typical implementation of the PC Card to 1D13706 interface PC Card Bus S1D13706 OE gt RDA WE gt WEO A17 gt M R CE1 CE2 id gt WE1 RESET gt o gt RESET HIO Vpp A RD WR BS gt CS A 16 0 gt AB 16 0 D 15 0 gt DB 15 0 15K pull up WAIT 4 WAIT CLKI Oscillator CLKI2 Note When connecting the S1D13706 RESET pin the system designer should be aware of all conditions that may reset the S1D13706 e g CPU reset can be asserted during wake up from power down modes or during debug states S1D13706 X31B G 005 02 Figure 4 1 Typical Implementation of PC Card to SID13706 Interface Interfacing to the PC Card Bus Issue Date 01 02 23 Epson Research and Development Page 13 Vancouver Design Center 4 2 S1D13706 Hardware Configuration The S1D13706 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13706 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this
486. otes and Examples Issue Date 01 02 23 These bits determine the X start position of the sub window in relation to the origin of the panel Due to the S1D13706 SwivelView feature the X start position may not be a horizontal position value only true in 0 and 180 Swivel View For further information on defining the value of the X Start Position registers see Section 8 3 Picture In Picture Plus Examples on page 48 The registers are also incremented differently based on the Swivel View orientation For 0 and 180 SwivelView the X start position is incremented by X pixels where X is relative to the current color depth Table 8 1 32 bit Address Increments for Color Depth Bits per pixel Color Depth Pixel Increment X 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 For 90 and 270 SwivelView the X start position is incremented in 1 line increments In Swivel View 0 these registers set the horizontal coordinates x of the sub windows s top left corner Increasing values of x move the top left corner towards the right in steps of 32 bits per pixel see Table 8 1 Program the Sub Window X Start Position registers so that sub window X start position registers x 32 bits per pixel Note x must be a multiple of 32 bits per pixel In Swivel View 90 these registers set the vertical coordinates y of the sub window s top right corner Increasing values of y move the top righ
487. ow bit 4 GPIO4 Pin IO Status Hardware Functional Specification Issue Date 01 11 13 When a D TFD panel is not selected REG 10h bits 1 0 and GPIO4 is configured as an output writing a 1 to this bit drives GPIO4 high and writing a O to this bit drives GPIO4 low When a D TFD panel is not selected REG 10h bits 1 0 and GPIO4 is configured as an input a read from this bit returns the status of GPIO4 When a D TFD panel is enabled REG 10h bits 1 0 11 GPIO4 outputs the RES signal automatically and writing to this bit has no effect 1D13706 X31B A 001 08 Page 124 bit 3 bit 2 bit 1 1D13706 X31B A 001 08 Epson Research and Development Vancouver Design Center GPIO3 Pin IO Status When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIO3 is configured as an output writing a 1 to this bit drives GPIO3 high and writing a 0 to this bit drives GPIO3 low When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIO3 is configured as an input a read from this bit returns the status of GPIO3 When a D TFD panel is enabled REG 10h bits 1 0 11 GPIO3 outputs the FRS signal automatically and writing to this bit has no effect When a HR TFT panel is enabled REG 10h bits 1 0 10 GPIO3 outputs the SPL sig nal automatically and writing to this bit has no effect GPIO2 Pin IO Status When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIO2 is
488. ower Save Mode Enable bit REG AOh bit 0 to 1 LCD Signals include FPDAT 17 0 FPSHIFT FPLINE FPFRAME and DRDY Figure 6 12 Passive TFT Power Off Sequence Timing Table 6 15 Passive TFT Power Off Sequence Timing Symbol Parameter Min Max Units ti LCD bias deactivated to LCD signals inactive Note 1 Note 1 t2 Power Save Mode enabled to LCD signals low 0 20 ns 1 t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel connected Hardware Functional Specification Issue Date 01 11 13 1D13706 X31B A 001 08 Page 56 Epson Research and Development Vancouver Design Center 6 4 Display Interface The timing parameters required to drive a flat panel display are shown below Timing details for each supported panel type are provided in the remainder of this section HT HDPS HPS HPW VDPS VPW VT Figure 6 13 Panel Timing Parameters 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Vancouver Design Center Table 6 16 Panel Timing Parameter Definition and Register Summary Page 57 Symbol Description Derived From Units HT Horizontal Total REG 12h bits 6 0 1 x 8 HDP Horizontal Display Period REG 14h bits 6 0 1 x 8 i For STN panels REG 17h bits 1 0 REG 16h bits 7 0 22 HD
489. p solution to meet the demands of embedded markets such as Mobile Communications devices and Palm size PCs where board size and battery life are major concerns The S1D13706 utilizes a guaranteed low latency CPU architecture providing support for microprocessors without READY WAIT handshaking signals The 32 bit internal data path provides high performance bandwidth into display memory allowing for fast screen updates Products requiring a rotated display image can take advantage of the Swivel View feature which provides hardware rotation of the display memory transparent to the software appli cation The S1D13706 also provides support for Picture in Picture Plus a variable size Overlay window The 1D13706 provides impressive support for Palm OS handhelds however its impar tiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 12 Epson Research and Development Vancouver Design Center 2 Features 2 1 Integrated Frame Buffer e Embedded 80K byte SRAM display buffer 2 2 CPU Interface Direct support of the following interfaces Generic MPU bus interface using WAIT signal Hitachi SH 3 Hitachi SH 4 Motorola M68K Motorola MC68EZ328 MC68VZ328 DragonBall Motorola REDCAP2 no WAIT signal e 8 bit processor support with glue logic e Fixed low latency
490. p to first CLK rising edge where 4 4 ds CS 0 ASH 0 DS 0 t4 A 16 0 SIZ 1 0 M R hold from ASH rising edge 0 ns t5 CS setup to CLK rising edge 1 ns t6 CS hold from AS rising edge 0 ns t7a_ AS asserted for MCLK BCLK 8 8 Telk t7b ASH asserted for MCLK BCLK 2 11 11 ToLk t7c AS asserted for MCLK BCLK 3 13 13 Telk t7d AS asserted for MCLK BCLK 4 18 18 TeLk t8 AS falling edge to CLK rising edge 1 1 ns t9 AS rising edge to CLK rising edge 1 3 ns t10 DS falling edge to CLK rising edge 1 1 ns t11 DS setup to CLK rising edge 1 3 ns t12 First CLK where AS 1 to DSACK1 high impedance 5 40 3 14 ns 113 R W setup to CLK rising edge before all CS 0 AS 0 and 4 4 He DS 0 t14 R W hold from AS rising edge 0 0 ns t15 AS 0 and CS 0 to DSACK1 rising edge 4 23 3 14 ns t16 AS rising edge to DSACK1 rising edge 6 39 4 17 ns 117 D 31 16 valid to third CLK rising edge where CS 0 ASH 0 4 0 Bs and DS 0 write cycle see note 1 t18 D 31 16 hold from falling edge of DSACK1 write cycle 0 0 ns t19 DS falling edge to D 31 16 driven read cycle 4 32 3 14 ns t20 DSACK1 falling edge to D 31 16 valid read cycle 0 2 ns 121 DS rising edge to D 31 16 invalid high impedance read cycle 5 36 3 13 ns 1 t17 is the delay from when data is placed on the bus until the data is latched into the write buffer Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 48
491. pace and attribute memory space Common memory may be accessed by a host system for memory read and write operations Attribute memory is used for defining card specific information such as configuration registers card capabilities and card use IO space maintains software and hardware compatibility with hosts such as the Intel x86 architecture which address peripherals independently from memory space Bit notation follows the convention used by most microprocessors the high bit is the most significant Therefore signals A25 and D15 are the most significant bits for the address and data bus respectively Support is provided for on chip DMA controllers To find further information on these topics refer to Section 6 References on page 15 PC Card bus signals are asynchronous to the host CPU bus signals Bus cycles are started with the assertion of either the CE1 and or the CE2 card enable signals The cycle ends once these signals are de asserted Bus cycles can be lengthened using the WAIT signal Note The PCMCIA 2 0 JEIDA 4 1 and later PC Card Standard support the two signals WAIT and RESET which are not supported in earlier versions of the standard The WAIT signal allows for asynchronous data transfers for memory attribute and IO ac cess cycles The RESET signal allows resetting of the card configuration by the reset line of the host CPU 2 1 2 Memory Access Cycles 1D13706 X31B G 005 02 A data transfer is initia
492. play Period REG 14h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts S1D13706 X31B A 001 08 Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 65 Vancouver Design Center ti t2 Sync Timing i gt FPFRAME t4 gt lt t3 gt FPLINE t5 Posie DRDY MOD 3 Data Timing FPLINE a 0 y t8 t9 t7 t14 tii t10 4 gt 4 gt lt gt FPSHIFT t12 t13 FPDAT 7 4 1 2 7 Figure 6 20 Single Color 4 Bit Panel A C Timing Table 6 19 Single Color 4 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 0 5 Ts t9 FPSHIFT period 1 Ts t10 FPSHIFT pulse width low 0 5 Ts t11 FPSHIFT pulse width high 0 5 Ts t12 FPDAT 7 4 setup to FPSHIFT falling edge 0 5 Ts t13 FPDAT 7 4 hold to FPSHIFT falling edge 0 5 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 t mi
493. play start 400 Ts 1 Ts pixel clock period Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 90 Epson Research and Development Vancouver Design Center 7 Clocks 7 1 Clock Descriptions 7 1 1 BCLK 7 1 2 MCLK BCLK is an internal clock derived from CLKI BCLK can be a divided version 1 2 3 4 of CLKI CLKI is typically derived from the host CPU bus clock The source clock options for BCLK may be selected as in the following table Table 7 1 BCLK Clock Selection Source Clock Options BCLK Selection CLKI CNF 7 6 00 CLKI 2 CNF 7 6 01 CLKI 3 CNF 7 6 10 CLKI 4 CNF 7 6 11 Note For synchronous bus interfaces it is recommended that BCLK be set the same as the CPU bus clock not a divided version of CLKD e g SH 3 SH 4 Note The CLKI 3 and CLKI 4 options may not work properly with bus interfaces with short back to back cycle timing MCLK provides the internal clock required to access the embedded SRAM The S1D 13706 is designed with efficient power saving control for clocks clocks are turned off when not used reducing the frequency of MCLK does not necessarily save more power Furthermore reducing the MCLK frequency relative to the BCLK frequency increases the CPU cycle latency and so reduces screen update performance For a balance of power saving and performance the MCLK should be configured to have a high enough frequency setting t
494. play start address The main window is typically placed at the start of display memory which is at dis play address 0 main window display start address register desired byte address panel width 1 x panel height x bpp 8 4 0 320 1 x 240 x 4 8 4 9570 2562h Program the Main Window Display Start Address registers REG 74h is set to 62h REG 75h is set to 25h and REG 76h is set to 00h Determine the main window line address offset number of dwords per line image width 32 bpp 240 32 4 30 1Eh Program the Main Window Line Address Offset registers REG 78h is set to 1Eh and REG 79h is set to 00h 7 3 1 SwivelView 0 and 180 In SwivelView 0 and 180 the main window line address offset register requires the panel width to be a multiple of 32 bits per pixel If this is not the case then the main window line address offset register must be programmed to a longer line which is a multiple of 32 bits per pixel This longer line creates a virtual image where the width is main window line address offset register x 32 bits per pixel and the main window image must be drawn right justified to this virtual width 7 3 2 SwivelView 90 and 270 1D13706 X31B G 003 03 In Swivel View 90 and 270 the main window line address offset register requires the panel height to be a multiple of 32 bits per pixel If this is not the case then the main window line address off
495. plete drivers Console drivers options Frame buffer support Support for frame buffer devices EXPERIMENTAL EPSON LCD CRT TV controller support EPSON S1D13706 Support Advanced low level driver options xbpp packed pixels support where x is the color depth being compile for If you are using the Epson PCI evaluation board then you must also select Epson PCI Bridge adapter support Once you have configured the kernel options save and exit the configuration utility S1D13706 Linux Console Driver X31B E 004 02 Issue Date 01 09 19 Epson Research and Development Page 9 Vancouver Design Center 6 Compile and install the kernel Build the kernel with the following sequence of commands make dep make clean make bzImage sbin lilo Gf running lilo 7 Boot to the Linux operating system If you are using lilo Linux Loader modify the lilo configuration file as discussed in the kernel build README file If there were no errors during the build from the com mand prompt run lilo and reboot your system Note In order to use the S1D13706 console driver with X server you need to configure the X server to use the FBDEV device A good place to look for the necessary files and in structions on this process is on the Internet at www xfree86 org Linux Console Driver S1D13706 Issue Date 01 09 19 X31B E 004 02 Page 10 Epson Research and Development Vancouver Design Center THIS PA
496. port an external LCD controller by providing the internal address decoding and control signals necessary By using the Generic 2 Host Bus Interface no glue logic is required to interface the S1D13706 and the NEC VR4102 VR4111 A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO Vpp The following diagram shows a typical implementation of the VR4102 VR4111 to S1D13706 interface NEC VR4102 VR4111 1D13706 WR gt WEO SHB gt WE1 RD gt RD LCDCS P gt CS ull up To LCDRDY WAIT ADD17 gt M R System RESET RESET ADD 16 0 gt AB 16 0 DAT 15 0 e gt DB 15 0 BUSCLK gt CLKI HIO Vo A BS RD WR Note When connecting the S1D13706 RESET pin the system designer should be aware of all conditions that may reset the S1D13706 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of VR4102 VR4111 to SID13706 Interface 1D13706 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 02 Issue Date 01 02 23 Epson Research and Development Page 13 Vancouver Design Center 4 2 S1D13706 Hardware Configuration The S1D13706 uses CNF7 through CNFO to allow selection of the bus mode and oth
497. pp 8 4 1 0 320 pixels x 8 bpp 8 4 1 79 4Fh Line Address Offset The Main Window Line Address Offset registers REG 78h REG 79h is based on the display width and programmed using the following formula Main Window Line Address Offset bits 9 0 display width in pixels 32 bpp 320 pixels 32 8 bpp 80 50h Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 140 Epson Research and Development Vancouver Design Center 12 3 180 SwivelView The following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed The application image is written to the S1D13706 in the following sense A B C D The display is refreshed by the S1D13706 in the following sense D C B A physical memory display start address start address panel origin A B a 9 SwivelView o MOPUIM N N window oe MOIAJ9AIMS ra C D g Vv 4 480 A 4 480 5 image seen by programmer image refreshed by S1D13706 image in display buffer Figure 12 2 Relationship Between The Screen Image and the Image Refreshed in 180 SwivelView 12 3 1 Register Programming Enable 180 SwivelView Mode Set SwivelView Mode Select bits REG 71h bits 1 0 to 10 Display Start Address The display refresh circuitry starts at pixel D therefore the Main Window Display Start Address registers REG 74h REG 75h RE
498. programmer image refreshed by S1D13706 image in display buffer Figure 12 3 Relationship Between The Screen Image and the Image Refreshed in 270 SwivelView Hardware Functional Specification 1D13706 X31B A 001 08 Issue Date 01 11 13 Page 142 Epson Research and Development Vancouver Design Center 12 4 1 Register Programming 1D13706 X31B A 001 08 Enable 270 SwivelView Mode Set SwivelView Mode Select bits REG 71h bits 1 0 to 11 The display refresh circuitry starts at pixel C therefore the Main Window Display Start Address registers REG 74h REG 75h REG 76h must be programmed with the address of pixel C To calculate the value of the address of pixel C use the following formula assumes 8 bpp color depth Main Window Display Start Address bits 16 0 image address panel width 1 x offset x bpp 8 4 0 480 pixels 1 x 320 pixels x 8 bpp 8 4 38320 95B0h Line Address Offset The Main Window Line Address Offset registers REG 78h REG 79h is based on the display width and programmed using the following formula Main Window Line Address Offset bits 9 0 display width in pixels 32 bpp 320 pixels 32 8 bpp 80 50h Hardware Functional Specification Issue Date 01 11 13 Epson Research and Development Page 143 Vancouver Design Center 13 Picture 13 1 Concept in Picture Plus PIP Picture in Picture Plus enables a s
499. ption The interface between the S1D13706 and the REDCAP2 requires no external glue logic The information in this section describes the environment necessary to connect the S5U13706B00C Evaluation Board and the Motorola DSP56654 Application Development Module ADM For a list of connections between the pins and signals of the REDCAP2 and the S1D13706 see Table 4 1 List of Connections from REDCAP2 ADM to S5U13706B00C on page 13 The following figure demonstrates a typical implementation of the S1D13706 to REDCAP 2 interface REDCAP2 S1D13706 HIO Vop A BS A17 M R A 16 0 AB 16 0 D 15 0 p DB 15 0 CS1 p CS RAW RD WR OE p RD EB1 gt WEO EBO gt WE1 CLK gt CLKI System RESET gt RESET Note This example uses CS1 CSn can be any of CS0 CS4 Note When connecting the S1D13706 RESET pin the system designer should be aware of all conditions that may reset the S1D13706 e g CPU reset can be asserted during wake up from power down modes or during debug states S1D13706 X31B G 014 02 Figure 4 1 Typical Implementation of REDCAP2 to S1D13706 Interface Interfacing to the Motorola RedCap2 DSP With Integrated MCU Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 4 2 Hardware Connections Page 13 The following table details the connections between the pins and signals of the REDCAP2 and the S1D13706
500. py of the complete source code for the S1D13706 utilities including the makefiles as well as a copy of the GNU Compiler v2 8 1 for Hitachi SH3 These are available on the Epson Electronics America Website at WWW eea epson com S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 97 Vancouver Design Center 10 3 1 Building the LIBSE library for SH3 target example In the LIBSE files there are two main types of files e C and assembler files that contain the target specific code e makefiles that describe the build process to construct the library The C and assembler files contain some platform setup code evaluation board communi cations chip selects and jumps into the main entry point of the C code that is contained in the applications main function For our example the startup file which is sh3entry c performs some board configuration board communications and assigning memory blocks with chip selects and a jump into the applications main function In the embedded targets putch xxxputch c and getch xxxgetch c resolve to serial character input output For SH3 much of the detail of handling serial IO is hidden in the monitor of the evaluation board but in general the primitives are fairly straight forward providing the ability to get characters to from the serial port For our target example the nmake makefile is makesh3 mk This makefile calls the Gnu compil
501. r face on page 56 FPFRAME Pulse Width Register REG 24h Read Write FPFRAME n a FPFRAME Pulse Width Bits 2 0 Pulse Polarity 7 6 5 4 3 2 1 0 bit 7 FPFRAME Pulse Polarity This bit selects the polarity of the vertical sync signal For passive panels this bit must be set to 1 For TFT panels this bit is set according to the horizontal sync signal of the panel typically FPFRAME SPS or DY When this bit 0 the vertical sync signal is active low When this bit 1 the vertical sync signal is active high bits 2 0 FPFRAME Pulse Width Bits 2 0 These bits specify the width of the panel vertical sync signal in 1 line resolution The ver tical sync signal is typically FPFRAME SPS or DY depending on the panel type FPFRAME Pulse Width in number of lines REG 24h bits 2 0 1 Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 56 Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 108 Epson Research and Development Vancouver Design Center FPFRAME Pulse Start Position Register 0 REG 26h Read Write FPFRAME Pulse Start Position Bits 7 0 7 6 5 4 3 2 1 0 FPFRAME Pulse Start Position Register 1 REG 27h Read Write ae FPFRAME Pulse Start Position Bits 9 8 7 6 5 4 3 2 1 0 bits 9 0 FPFRAME Pulse Start Position Bits 9 0 These bits specify the start pos
502. r Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 23 EPSON 1D13706 Embedded Memory LCD Controller Connecting to the Sharp HR TFT Panels Document Number X31B G 011 04 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Connecting to the Sharp HR TFT Panels X31B G 01 1 04 Issue Date 01 02 23 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 iIntrod ction gt s a AA oe A AR A ie a ew 7 2 Connecting to the Sharp LQ039Q2DS01 HR TFT 8 2 1 External Power Supplies 2 ee ee ee 8 2 1 1 Gray Scale Voltages for Gamma Correction o e 8 2 1 2 Digital Anal
503. r void seDrawMainWinEllipse long xc long yc long xr long yr DWORD Color void seDrawSubWinEllipse long xc long yc long xr long yr DWORD Color Description These routines draw an ellipse on the screen in the specified color The ellipse is centered at the co ordinate x y and is drawn in the specified color with the indicated radius for the x and y axis These functions only draw the border of the ellipse there is no solid fill fea ture Use seDrawEllipse to draw the ellipse on the current active display surface See seSet MainWinAsActiveSurface and seSetSubWinAsActiveSurface for information about changing the active surface Use seDrawMainWinEllipse and seDrawSubWinEllipse to draw the ellipse on the dis play surface indicated by the function name If no memory was allocated to the surface these functions return without writing to dis play memory Parameters XC The X co ordinate in pixels of the center of the ellipse yc The Y co ordinate in pixels of the center of the ellipse xr A long integer specifying the X radius of the ellipse in pixels yr A long integer specifying the Y radius of the ellipse in pixels Color A dword specifying the color to draw the ellipse Color is interpreted differently at different color depths At 1 2 4 and 8 bpp display colors are derived from the lookup table values The least significant byte of Color is an index into the lookup table At 16 bpp the lookup table is bypa
504. r its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example CLKO from the Motorola MC68VZ328 is used for CLKI The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the MC68VZ328 address A 16 0 and data bus D 15 0 respectively CNF4 must be set to one to select big endian mode Chip Select CS must be driven low by one of the Dragonball VZ chip select outputs from the chip select module whenever the S1D13706 is accessed by the MC68VZ328 M R memory register selects between memory or register accesses This signal is generated by the external address decode circuitry For this example M R may be connected to an address line allowing system address A17 to be connected to the M R line WEO connects to LWE the low data byte write strobe enable of the MC68VZ328 and is asserted when valid data is written to the low byte of a 16 bit device WE1 connects to UWE the upper data byte write strobe enable of the MC68VZ328 and is asserted when valid data is written to the high byte of a 16 bit device RD connects to OE the read output enable of the MC68VZ328 and is asserted during a read cycle of the MC68VZ328 microprocessor RD WR is not used for the Dragonball host bus interface and must be tied high to HIO Vpp WAIT connects to DTACK and is a signal which is output from the 1D 13706 indi cating the MC68VZ328 must wait until data is ready read
505. r the bus cycle is 8 16 or 32 bit e R W set high for read cycles and low for write cycles e TT 1 0 Transfer Type Signals provides more detail on the type of transfer being attempted TIP Transfer In Progress asserts whenever a bus cycle is active When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MCF5307 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 23 Epson Research and Development Page 9 Vancouver Design Center Figure 2 1 MCF5307 Memory Read Cycle illustrates a typical memory read cycle on the MCF5307 system bus polka LJ LI LI LI LUI LU LI TS TA TIP Ast X Rw XX OOO SIZ 1 0 TT 1 0 X A D131 01 AXXXMAXMAAXMAXMAAXMAXMAAX AXA Sampled when TA low Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 1 MCF5307 Memory Read Cycle Figure 2 2 MCF5307 Memory Write Cycle illustrates a typical memory write cycle on the MCF5307 system bus BCLKO TS TA mer aog X X aw IA 5
506. rView Tab Show the tree for MY PLATFORM Parameters by clicking on the sign at the root of the tree Expand the the WINCE300 tree and then click on Hardware Specific Files and then double click on PLATFORM BIB Edit the file the PLATFORM BIB file and make the fol lowing two changes a Insert the following text after the line IF ODO_NODISPLAY IF CEPC_DDI_S1D13X0X ddi dll FLATRELEASEDIRAS1D13X0X d1l NK SH ENDIF b Find the section shown below and insert the lines as marked IF CEPC_DDI_FLAT IF CEPC_DDI_S1D13X0X Insert this line IF CEPC_DDI_S3VIRGE IF CEPC_DDI_CT655X IF CEPC_DDI_VGA8BPP IF CEPC_DDI_S3TRIO64 IF CEPC_DDI_ATI Windows CE 3 x Display Drivers 1D13706 Issue Date 01 05 25 X31B E 006 01 Page 6 1D13706 X31B E 006 01 11 12 Epson Research and Development Vancouver Design Center ddi dll FLATRELEASEDIRNddi_flat dl NK SH ENDIF ENDIF ENDIF ENDIF ENDIF ENDIF Insert this line ENDIF Modify MODEO H The file MODEO H located in x wince300 platform cepc drivers display S 1D 13706 contains the register values required to set the screen resolution color depth bpp display type active display LCD CRT TV display rotation etc Before building the display driver refer to the descriptions in the file MODEO H for the default settings of the console driver If the default does not match the configura tion you are building for then MODEO H will have to be r
507. ration Program User Manual document number X31B B 001 xx Note The WindML display drivers are provided as reference source code only They are in tended to provide a basis for OEMs to develop their own drivers for WindML v2 0 These drivers are not backwards compatible with UGL v1 2 For information on the UGL v1 2 display drivers see Wind River UGL v1 2 Display Drivers document number X31B E 003 xx This document and the source code for the WindML display drivers is updated as appro priate Please check the Epson Electronics America website at http www eea epson com or the Epson Research and Development website at http www erd epson com for the latest revisions before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Wind River WindML v2 0 Display Drivers 1D13706 Issue Date 01 04 06 X31B E 002 03 Page 4 Epson Research and Development Vancouver Design Center Building a WindML v2 0 Display Driver 1D13706 X31B E 002 03 The following instructions produce a bootable disk that automatically starts the UGL demo program These instructions assume that Wind River s Tornado platform is already installed Note For the example steps where the drive letter is given as x Substitute x with the drive letter that your development environment is on 1 Create a working directory and unzip the WindML display driver into
508. rd requires 0 5 seconds to fully discharge Other power supply designs may vary This section assumes the LCD bias power is controlled through GPO The S1D13706 GPIO pins are multi use pins and may not be available in all system designs For further infor mation on the availability of GPIO pins see the S1D13706 Hardware Functional Specifi cation document number X31B A 001 xx Note This section discusses LCD power sequencing for passive and TFT non HR TFT D TED panels only For further information on LCD power sequencing the HR TFT see Connecting to the Sharp HR TFT Panels document number X31B G 011 xx For fur ther information on LCD power sequencing the D TFD see Connecting to the Epson D TFD Panels document number X31B G 012 xx Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 30 Epson Research and Development Vancouver Design Center 6 1 Enabling the LCD Panel The HAL function seDisplayEnable TRUE can be used to enable the LCD panel The function enables the LCD panel using the following steps 1 Enable the LCD signals Set Display Blank bit REG 70h bit 7 to 0 2 Wait the required delay time as specified in the LCD panel specification must be set using 13706CFG For further information on 13706CFG see the 13706CFG User Manual document number X31B B 001 xx 3 Enable GPO to activate the LCD bias power Note seLcdDisplayEnable is included in the C source file hal_misc c
509. rdware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 61 Vancouver Design Center t1 t2 Sync Timing lt 4 gt FPFRAME By lt t3 gt FPLINE t5 oop g DRDY MOD Data Timing FPLINE TS t6 4 t7 gt 4 FPSHIFT FPDAT 7 4 Figure 6 16 Single Monochrome 4 Bit Panel A C Timing Table 6 17 Single Monochrome 4 Bit Panel A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 14 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 2 Ts t9 FPSHIFT period 4 Ts t10 FPSHIFT pulse width low 2 Ts t11 FPSHIFT pulse width high 2 Ts t12 FPDAT 7 4 setup to FPSHIFT falling edge 1 Ts t13 FPDAT 7 4 hold to FPSHIFT falling edge 2 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 tl min HPS t4 min 3 t2min t8min HPS t4min 4 83min HT 5 t4min HPW 6 t5mn HPS 1 7 t6min HPS HDP HDPS 2 if negative add t3 min 8 t14min HDPS HPS t4min if negative add t3min Hardware Functional Specificat
510. rdware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 88 Epson Research and Development Vancouver Design Center ti 4 gt GPIO4 RES t2 DRDY i i EN Pr TM GCP i f i GCP Data Register 1 1 0 1 0 1 1 0 REGIZCAD bit bito bit7 ene Index 00h Index 01h Index 00h Figure 6 38 320x240 Epson D TFD Panel GCP Horizontal Timing Table 6 32 320x240 Epson D TFD Panel GCP Horizontal Timing Symbol Parameter Min Typ Max Units t1 Half of the horizontal total period 200 Ts note 1 t2 GOP clock period 1 Ts 1 Ts pixel clock period S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 89 Vancouver Design Center Vertical Total 250HT FPFRAME l DY 12 eron yA REA ee ee E ee LEDO YSCL Sr nae ua AS EE eg A a ae 13 clio linet line2 HAY HA GPIO2 FR 0 i i odd frame A o even frame Figure 6 39 320x240 Epson D TFD Panel Vertical Timing Table 6 33 320x240 Epson D TFD Panel Vertical Timing Symbol Parameter Min Typ Max Units t1 FPFRAME pulse width 200 Ts note 1 t2 Horizontal total period 400 Ts t3 Vertical dis
511. re selected using ADD17 from the NEC VR4102 4111 ADD17 is connected to the S1D13706 M R pin The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block The starting address of the S1D13706 internal registers is located at 0A00_0000h and the starting address of the display buffer is located at 0A02_0000h These blocks are aliased over the entire 16M byte address space Note If aliasing is not desirable the upper addresses must be fully decoded The NEC VR4102 VR4111 has a 16 bit internal register named BCUCNTREG2 located at 0B00_0002h It must be set to the value of 0001h which indicates that LCD controller accesses use a non inverting data bus The 16 bit internal register named BCUCNTREGI located at OB00_0000h must have bit D 13 USA LCD bit set to O This reserves 16M bytes from 0A00_0000h to OAFF_FFFFh for use by the LCD controller and not as ISA bus memory space Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 01 02 23 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and Windows CE v2 11 2 12 display drivers are available for the S1D13706 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customi
512. reased by mul tiples of 16 For TFT panels HDP must be a minimum of 16 pixels and can be increased by multiples of 8 For panel AC timing and timing parameter definitions see Section 6 4 Display Interface on page 56 Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 104 Epson Research and Development Vancouver Design Center Horizontal Display Period Start Position Register 0 REG 16h Read Write Horizontal Display Period Start Position Bits 7 0 7 6 5 4 3 2 1 0 Horizontal Display Period Start Position Register 1 REG 17h Read Write ne Horizontal Display Period Start Position Bits 9 8 7 6 5 4 3 2 1 0 bits 9 0 Horizontal Display Period Start Position Bits 9 0 These bits specify a value used in the calculation of the Horizontal Display Period Start Position in 1 pixel resolution for TFT HR TFT and D TFD panels For passive LCD panels these bits must be set to 00h which will result in HDPS 22 HDPS REG 17h bits 1 0 REG 16h bits 7 0 22 For TFT HR TFT D TFD panels HDPS is calculated using the following formula HDPS REG 17h bits 1 0 REG 16h bits 7 0 5 For further information on calculating the HDPS see the specific panel AC Timing in Sec tion 6 4 Display Interface on page 56 Note This register must be programmed such that the following formula is valid HDPS HDP lt HT S1D13706 Hardware Functional Specification
513. rements o o e e Table 6 5 Generic 1 Interface TlMINg o e e Table 6 6 Generic 2 Interface TlMINB e e Table 6 7 Hitachi SH 4 Interface TiMiN8 o Table 6 8 Hitachi SH 3 Interface TiMiN8 o Table 6 9 Motorola MC68K 1 Interface Timing o o Table 6 10 Motorola MC68K 2 Interface Timing 4 Table 6 11 Motorola REDCAP2 Interface Timing Table 6 12 Motorola DragonBall Interface with DTACK Timing Table 6 13 Motorola DragonBall Interface without DTACK Timing Table 6 14 Passive TFT Power On Sequence Timing Table 6 15 Passive TFT Power Off Sequence Timing Table 6 16 Panel Timing Parameter Definition and Register Summary Table 6 17 Single Monochrome 4 Bit Panel A C Timing Table 6 18 Single Monochrome 8 Bit Panel A C Timing 0 Table 6 19 Single Color 4 Bit Panel A C TiMiNn8 o o Table 6 20 Single Color 8 Bit Panel A C Timing Format l Table 6 21 Single Color 8 Bit Panel A C Timing Format2 Table 6 22 Single Color 16 Bit Panel A C Timing o Table 6 23 TFT A C Timing Table 6 24 160x160 Sharp Direct HR TFT Horizontal Timing Hardware Functional Specification I
514. resses for Register address and Display buffer address 13706CFG Configuration Program S1D13706 Issue Date 01 03 29 X31B B 001 03 Page 8 Epson Research and Development Vancouver Design Center Register Address The physical address of the start of register decode space in hexadecimal This field is automatically set according to the Decode Address unless the User Defined decode address is selected Display Buffer Address The physical address of the start of display buffer decode space in hexadecimal This field is automatically set according to the Decode Address unless the User Defined decode address is selected Note When Epson S5U13706B00B B00C Evaluation Board is selected the register and display buffer addresses are blanked because the evaluation board uses the PCI interface and the decode addresses are determined by the system BIOS during boot up If using the S1D13706 Evaluation Board on a PCI based platform both Windows and the S1D13XXX device driver must be installed For further information on the S1D13xxx device driver see the SIDI3XXX 32 bit Windows Device Driver Installation Guide document number XOOA E 003 xx 1D13706 13706CFG Configuration Program X31B B 001 03 Issue Date 01 03 29 Epson Research and Development Page 9 Vancouver Design Center Preferences Tab 51D13706 Configuration Utility Panel SwivelView S W Invert Enable H W Invert Enable The Prefere
515. ription This routine reads two consecutive registers as a word and returns the value Parameters Index Offset to the first register to read Return Value The least significant word of the return value is the word read from the S1D13706 regis ters DWORD seReadRegDword DWORD Index Description This routine reads four consecutive registers as a dword and returns the value Parameters Index Offset to the first of the four registers to read Return Value The return value is the dword read from the S1D13706 registers void seWriteRegByte DWORD Index unsigned Value Description This routine writes Value to the register specified by Index Parameters Index Offset to the register to be written Value The value in the least significant byte to write to the register Return Value None S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 81 Vancouver Design Center void seWriteRegWord DWORD Index unsigned Value Description Parameters Return Value This routine writes the word contained in Value to the specified index Index Offset to the register pair to be written Value The value in the least significant word to write to the registers None void seWriteRegDword DWORD Index DWORD Value Description This routine writes the value specified to four registers starting at Index Parameters Index Offset to the first of four registers to be written to Valu
516. rite to the lookup table The array must consist of three bytes the first byte contains the red value the second byte contains the green value and the third byte contains the blue value None void seReadLutEntry int Index BYTE pRGB Description Parameter Return Value seReadLutEntry reads one lookup table entry and returns the results in the byte array pointed to by pRGB Index Offset to the lookup table entry to be read i e setting index to 2 returns the value of the third RGB element of the lookup table pRGB A pointer to an array to receive the lookup table data The array must be at least three bytes long On return from this function the first byte of the array will contain the red data the second byte will contain the green data and the third byte will contain the blue data None void seWriteLut BYTE pRGB int Count Description Parameter Return Value 1D13706 X31B G 003 03 seWriteLut writes one or more lookup table entries starting at offset zero These routines are intended to allow setting as many lookup table entries as the current color depth allows pRGB A pointer to an array of lookup table entry values to write to the LUT Each lookup table entry must consist of three bytes The first byte must contain the red value the second byte must contain the green value and the third byte must contain the blue value Count The number of lookup table entries to modify None Progr
517. river and integrate it into the QNX operating system These instructions assume the QNX developer environment is correctly installed and the developer is familiar with building for the QNX operating system Unpack the Graphics Driver Development Kit Archive 1 Install the QNX ddk package using the Package Manager utility For information about the Drivers Development Kit contact QNX directly 2 Once the ddk package is installed copy the directory tree usr scr gddk_v1 0 into the Project directory 3 Change directory to Project gddk_1 0 devg 4 Unpack the display driver files using the commands gunzip S1D13706 tar gz tar xvf S1D13706 tar This unpacks the files into the directory Project gddk_1 0 devg S1D13706 Configure the Driver The files s1d13706_16 h and s1d13706_8 h contain register values required to set the screen resolution color depth bpp display type rotation etc The s1d13706 h file included with the drivers may not contain applicable values and must be regenerated The configuration program 13706CFG can be used to build new s1d13706_16 h and s1d13706_8 h files Note S1d13706 h should be created using the configuration utility 13706CFG For more in formation on 13706CFG see the 13706CFG Configuration Program User Manual document number X31B B 001 xx available at www erd epson com Build the Driver The first time the driver is built the following command ensures that all drivers and required libraries are
518. rivers display S 1D 13706 replacing the original configura tion file Edit the file PLATFORM REG to match the screen resolution color depth bpp ac tive display LCD CRT TV and rotation information in MODE H PLAT FORM REG is located in x wince platform cepc files For example the display driver section of PLATFORM REG should be as follows when using a 320x240 LCD panel with a color depth of 8 bpp in Swivel View 0 landscape mode Default for EPSON Display Driver 320x240 at 8 bits pixel LCD display no rotation Useful Hex Values 1024 0x400 768 0x300 640 0x280 480 0x1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display S 1D13706 Width dword 140 Height dword FO Bpp dword 8 ActiveDisp dword 1 Rotation dword 0 Delete all the files in wince release directory and delete x wince platform cepc bif Windows6 CE 2 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 9 Vancouver Design Center 12 Generate the proper building environment by double clicking on the Epson project icon Build Epson for x86 13 Type BLDDEMO lt ENTER gt at the command prompt of the Build Epson for x86 window to generate a Windows CE image file NK BIN Windows CE 2 x Display Drivers 1D13706 Issue Date 01 05 25 X31B E 001 04 Page 10 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once the NK BIN file is built the CEPC
519. rmine infor mation such as display size r90 Enables SwivelView 90 mode counter clockwise hardware rotation of LCD image by 90 degrees r180 Enables SwivelView 180 mode counter clockwise hardware rotation of LCD image by 180 degrees 11270 Enables SwivelView 270 mode counter clockwise hardware rotation of LCD image by 270 degrees s Displays a vertical stripe pattern 13706SHOW Demonstration Program Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center n Displays the help screen Test Only Switches The following switches were added for testing and validation They are not supported at the customer level bigmem Assumes memory size is 2M bytes instead of 80K bytes for testing purposes only noclkerr Allows invalid SwivelView clock settings for testing purposes only read After drawing the image continually reads the entire display buffer in dword increments for testing purposes only write Continually writes to one word of offscreen memory for testing purposes only Note Pressing the Esc key will exit the program 13706SHOW Demonstration Program 1D13706 Issue Date 01 02 23 X31B B 002 03 Page 6 Epson Research and Development Vancouver Design Center 13706SHOW Examples 13706SHOW is designed to demonstrate and test some of the features of the S1D13706 The following examples show how to use the program in both instances Using 13706SHOW For Demonstration
520. rnally by the S1D13706 Motorola 1D13706 Generic 1 Generic 2 Hitachi Motorola Motorola Motorola MC68EZ328 Pin Name SH 3 SH 4 MC68K 1 MC68K 2 REDCAP2 MC68VZ328 DragonBall AB 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 ABO Ao AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 CSH External Decode CSn External Decode CSn CSA M R External Decode CLKI BUSCLK BUSCLK CKIO CLK CLK CLK CLK BS Connected to Vpp BS AS AS Connected to Vpp RD WR Ro Connectedto oye R W R W rwg Connected to Vop Vpop RD RDO RD RD te 9 SIZ1 OE OE DD WEO WEO WE WEO sbi to SIZO EBI LWE DD WE1 WE1 BHE WE1 UDS DS EBO UWE WAIT WAIT WAIT pene DTACK DSACK1 N A DTACK RESET RESET RESET RESET RESET RESET RESET RESET Note 2 Tf the target MC68K bus is 32 bit then these signals should be connected to D 31 16 3 These pins are not used in their corresponding Host Bus Interface mode Systems are responsible for externally connecting them to the host interface IO Vpp S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 S1D13706 X31B G 004 04 Page 16 4 2 CPU Bus Connector Pin Mapping 1D13706 X31B G 004 04 Table 4 2 CPU Bus Connector H3 Pinout Epson Research and Development Vancouver Design Center Connector Pin No
521. rocessor MC68030IDP Integrated Development Platform board revision 3 0 with a Motorola MC68030 processor SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor DSP56654ADS Applications Development System board with a Motorola REDCAP2 processor Note The 13706SHOW source code can be modified or recompiled to allow 13706SHOW to run on other evaluation platforms not listed above 13706SHOW Demonstration Program 1D13706 Issue Date 01 02 23 X31B B 002 03 Page 4 Installation Usage 1D13706 X31B B 002 03 Epson Research and Development Vancouver Design Center PC platform Copy the file 13706show exe to a directory specified in the path e g PATH C 13706 Embedded platform Download the program 13706show to the system PC Platform At the prompt type 13706SHOW a bigmem b n g n noclkerr noinit r90 r180 r270 read s write Embedded platform Execute 13706show and type the command line argument at the prompt Where la Cycles through all video modes automatically b n Shows the LCD display at a user specified color depth bpp where n 1 2 4 8 16 g n Shows the image overlaid with a 20 pixel wide grid where n white 0 or black 1 If n is not specified the grid defaults to white noinit Skips full register initialization Only registers used for changing the color depth bpp are updated Additionally some registers are read to dete
522. rst mode table in your list To select which display mode the display driver should use upon boot add the following lines to your PLATFORM REG file HKEY_LOCAL_MACHINE Drivers Display S 1D13706 Width dword 140 Height dword FO Bpp dword 8 Rotation dword 0 RefreshRate dword 3C Flags dword 1 Note that all dword values are in hexadecimal therefore 140h 320 FOh 240 and 3Ch 60 The value for Flags should be 1 LCD When the display driver starts it will read these values in the registry and attempt to match a mode table against them All values must be present and valid for a match to occur otherwise the display driver will default to the FIRST mode table in your list Windows CE 2 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 13 Vancouver Design Center Comments A WinCE desktop application or control panel applet can change these registry values and the display driver will select a different mode upon warmboot This allows the display driver to support different display configurations and or orientations An example appli cation that controls these registry values will be made available upon the next release of the display driver preliminary alpha code is available by special request The display driver is CPU independent allowing use of the driver for several Windows CE Platform Builder supported platforms By default the 13706CFG program
523. rting QNX with the S1D13706 as the primary display To verify the driver type the following command at the root of the Project source tree gddk_1 0 directory util bench nto x86 0 devg bench dldevg S 1D13706 nto x86 dll devg S 1D13706 so mW H C F d0x0 0x0 Where W is the configured width of the display H is the configured height of the display C is the color depth in bpp either 8 or 16 F is the configured frame rate This command starts the bench utility which will initialize the driver as the secondary display and exercise the drivers main functions If the display appears satisfactory restart QNX Photon and the restart will result in the S1D13706 display driver becoming the primary display device QNX Photon v2 0 Display Driver 1D13706 Issue Date 01 09 10 X31B E 005 02 Page 6 Epson Research and Development Vancouver Design Center Comments e To restore the display driver to the default comment out changes made to the trap file crt NODE 1D13706 QNX Photon v2 0 Display Driver X31B E 005 02 Issue Date 01 09 10 EPSON 1D13706 Embedded Memory LCD Controller Windows CE 3 x Display Drivers Document Number X31B E 006 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epso
524. rts e 4 8 bit single monochrome passive panels e 4 8 16 bit single color passive panels e 9 12 18 bit TFT active matrix panels e 18 bit Sharp HR TFT panels e 18 bit Epson D TFD panels All the necessary signals are provided on the 40 pin LCD connector H1 For connection information refer to Table 5 1 LCD Signal Connector H1 on page 18 6 7 1 Buffered LCD Connector The buffered LCD connector H1 provides the same LCD panel signals as those directly from S1D13706 but with voltage adapting buffers selectable to 3 3V or 5 0V Pin 32 on this connector provides a voltage level of 3 3V or 5 0V to the LCD panel logic see JP6 LCD Panel Voltage on page 14 for information on setting the panel voltage 6 7 2 Extended LCD Connector The S1D13706 directly supports Sharp 18 bit HR TFT and Epson 18 bit D TFD panels The extended LCD connector H3 provides the extra signals required to support these panels The signals on this connector are also buffered from the 1D13706 and adjustable to 3 3V or 5 0V see JP6 LCD Panel Voltage on page 14 for details on setting the panel voltage S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 Epson Research and Development Page 23 Vancouver Design Center 7 Clock Synthesizer and Clock Options For maximum flexibility the S5U13706B00C implements a Cypress ICD2061A Clock Generator MCLKOUT from the clock synthesizer is connected to
525. s big endian i e Motorola Return Value None Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 72 Epson Research and Development Vancouver Design Center int seSetSwivelViewMode int rotate Description IMPORTANT Parameters Return Value This function sets the SwivelView orientation of the LCD display Display memory is automatically released and then reallocated as necessary for the display size When the Swivel View mode is changed memory allocated for both the main window and sub window display buffer is freed and the display buffer memory is reassigned The application must redraw the display and re initialize the sub window if used and redraw after calling seSetSwivel ViewMode rotate The values for rotate are LANDSCAPE display not rotated ROTATE90 display rotated 90 degrees counterclockwise ROTATE 180 display rotated 180 degrees counterclockwise ROTATE270 display rotated 270 degrees counterclockwise ERR_OK The new rotation was completed with no problems ERR_NOT_ENOUGH_MEMORY Insufficient display buffer int seGetSwivelViewMode void Description Parameters Return Value This function retrieves the SwivelView orientation of the LCD display The Swivel View status is read directly from the S1D13706 registers Calling this function when the LCD display is not initialized will result in an erroneous return value Note seGetSwivelViewMode was previously c
526. s 5 0 n a 7 5 4 3 2 1 0 bits 7 2 LUT Blue Read Data Bits 5 0 This register contains the data from the blue component of the Look Up Table The LUT position is controlled by the LUT Read Address Register REG OFh This is a read only register Note This register is updated only when the LUT Read Address Register REG OFh is writ ten to Look Up Table Green Read Data Register REG ODh Read Only LUT Green Read Data Bits 5 0 n a 7 5 4 3 2 1 0 bits 7 2 LUT Green Read Data Bits 5 0 This register contains the data from the green component of the Look Up Table The LUT position is controlled by the LUT Read Address Register REG OFh This is a read only register Note This register is updated only when the LUT Read Address Register REG OFh is writ ten to 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 101 Vancouver Design Center Look Up Table Red Read Data Register REG 0Eh Read Only LUT Red Read Data Bits 5 0 n a 7 6 5 4 3 2 1 0 bits 7 2 LUT Red Read Data Bits 5 0 This register contains the data from the red component of the Look Up Table The LUT position is controlled by the LUT Read Address Register REG OFh This is a read only register Note This register is updated only when the LUT Read Address Register REG OFh is writ ten to Look Up Table Read Address Register R
527. s are available from your sales support contact or on the internet at http www eea epson com Interfacing to 8 bit Processors 1D13706 Issue Date 01 02 23 X31B G 015 02 Page 14 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents Epson Research and Development Inc 1D13706 Hardware Functional Specification document number X31B A 001 xx Epson Research and Development Inc SSUI3706BO0C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources e Epson Electronics America website http www eea epson com S1D13706 Interfacing to 8 bit Processors X31B G 015 02 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Interfacing to 8 bit Processors Issue Date 01 02 23 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe El
528. scale voltages can be generated using a precise resistor divider network as described in Section 2 1 1 Gray Scale Voltages for Gamma Correction on page 8 Alternately they can be generated using a Sharp gray scale IC The Sharp IR3E203 elimi nates the large resistor network used to provide the 10 gray scale voltages and combines their function into a single IC The S1D13706 output signal REV is used to alternate the gray scale voltages and connects to the SW input of the IR3E203 IC The COM signal is used in generating the gate driver panel AC voltage Vcom and is explained in Section 3 1 4 AC Gate Driver Power Supplies on page 15 Figure 3 1 Sharp LQ031B1DDxx Gray Scale Voltage VO V9 Generation shows the circuit that generates the gray scale voltages using the Sharp IR3E203 IC SHARP IR3E203 Figure 3 1 Sharp LQ031B1DDxx Gray Scale Voltage VO V9 Generation 1D13706 Connecting to the Sharp HR TFT Panels X31B G 01 1 04 Issue Date 01 02 23 Epson Research and Development Page 15 Vancouver Design Center 3 1 2 Digital Analog Power Supplies The digital power supply VSHD must be connected to a 3 3V supply The analog power supply VSHA must be connected to a 5 0V supply 3 1 3 DC Gate Driver Power Supplies See Section 2 1 3 DC Gate Driver Power Supplies on page 9 and Figure 2 2 Panel Gate Driver DC Power Supplies on page 9 for details on generating Vss Vpp and Vcc 3 1 4 AC Gate
529. sclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 13706CFG Configuration Program X31B B 001 03 Issue Date 01 03 29 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 137066 FG ai at A a eh A eee oe eee BV a eS 5 S1D13706 Supported Evaluation Platforms z5 Installation 6 Usage te iy SP wat Ves eed 6 13706CFG Configuration Tabs Bh i E oa ee ee ae eR de tok ee General Tab tano e GE cae ik Ae alate ta So ae ta dados 7 Preferences Tabi a urna Baa dee are A bare Mae bar A ja 9 Clocks Labs coa e ti ae Beata a aia amp 10 Panel Tabs phen dt la A Ls estes a ta Macs 14 Panel Power Tabi ais tl ID a Se ea a 18 Registers Tabia m 8 a be Qa hee a Aa AS ES 19 13706CFG Menus 2 22 6 2 4 BO de A Mh le ok ee i eek la od ie Oe pee eo en Bk te da ta ZN OPC aye A eta GA oak Coot ee ai a Se Meni da 20 DAVES a O A ee agen cise es epee oak ate a A A a a a ten ena 21 SIMA a Nec Lee Qh ate Me naa 21 Configure Multiple 24 42 wo a Rae et Mae aw Ba Ete o eae ak
530. sert this line IF CEPC_DDI_S3VIRGE IF CEPC_DDI_CT655X IF CEPC_DDI_VGA8BPP IF CEPC_DDI_S3TRIO64 IF CEPC_DDI_ATI 1D13706 X31B E 006 01 Page 8 1D13706 X31B E 006 01 Epson Research and Development Vancouver Design Center ddi dll FLATRELEASEDIRNddi_flat dl NK SH ENDIF ENDIF ENDIF ENDIF ENDIF ENDIF Insert this line ENDIF Modify MODEO H The file MODEO H located in x wince300 platform cepc drivers display S 1D 13706 contains the register values required to set the screen resolution color depth bpp display type active display LCD CRT TV display rotation etc Before building the display driver refer to the descriptions in the file MODEO H for the default settings of the display driver If the default does not match the configura tion you are building for then MODEO H will have to be regenerated with the correct information Use the program 13706CFG to generate the header file For information on how to use 13706CFG refer to the 13706CFG Configuration Program User Manual document number X31B B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13706 WinCE Drivers Save the new configuration as MODEO H in the wince300 platform cepc drivers display replacing the original configuration file Edit the file PLATFORM REG to match the screen resolution color depth and rota tion information in MODE H PLATFORM REG is loca
531. set register must be programmed to a longer line which is a multiple of 32 bits per pixel This longer line creates a virtual image whose width is main window line address offset register x 32 bits per pixel and the main window image must be drawn right justified to this virtual width Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 37 Vancouver Design Center 8 Picture In Picture Plus 8 1 Concept Picture in Picture Plus enables a sub window within the main display window The sub window may be positioned anywhere within the main window and is controlled through the Sub Window control registers see Section 8 2 Registers The sub window retains the same color depth and SwivelView orientation as the main window The following diagram shows an example of a sub window within a main window 0 SwivelView main window sub window Figure 8 1 Picture in Picture Plus with SwivelView disabled 8 2 Registers These are registers which control the Picture In Picture Plus feature REG 71h Special Effects Register Display Data Word Swap Display Data SwivelView SwivelView p ay n a n a n a Mode Select Mode Select Byte Swap Bit 1 Bit 0 This bit enables a sub window within the main window The location of the sub window within the landscape window is determined by the Sub Window X Position registers REG 8
532. setting must be configured according to the specification for the panel being used This value is only used by Epson evaluation software designed for the S5U13706B00C evaluation board This setting controls the time delay between when the S1D13706 control signals are turned on and the LCD panel is powered on This setting must be configured according to the specification for the panel being used This value is only used by Epson evaluation software designed for the S5U13706B00C evaluation board 13706CFG Configuration Program Issue Date 01 03 29 Epson Research and Development Page 19 Vancouver Design Center Registers Tab 51D13706 Configuration Utility IS AX File Help Register Hex Register Name Double click on a line to modify a register The Registers tab allows viewing and direct editing the S1D13706 register values Scroll up and down the list of registers and view their configured value based on the settings the previous tabs Individual register settings may be changed by double clicking on the register in the listing Manual changes to the registers are not checked for errors so caution is warranted when directly editing these values It is strongly recommended that the 1D13706 Hardware Functional Specification document number X31B A 001 xx be referred to before making an manual register settings Manually entered values may be changed by 13706CFG if further configuration changes are made on the other tabs
533. so be used for the MOD control signal of the Sharp HR TFT panel Test Enable input used for production test only has type 1 pull TESTEN l 36 M NIOVDD E down resistor with a typical value of 50Q at 3 3V 4 4 5 Power And Ground Table 4 7 Power And Ground Pin Descriptions 10 RESET de og Pin Name Type Pin Cell Voltage State Description a IO Vpp pins associated with the host interface pins as described in PHONED Ce eres Section 4 4 1 Host Interface on page 22 IO Vpp pins associated with the non host interface pins as NIOVDD p 37 49 p _ 5 described in Section 4 4 2 LCD Interface on page 26 Section 63 76 4 4 3 Clock Input on page 28 and Section 4 4 4 Miscellaneous on page 28 COREVDD P 1 51 P 2 Core Vpp pins 14 25 36 50 l VSS P 62 75 P 7Vgg pins 100 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 29 Vancouver Design Center 4 5 Summary of Configuration Options These pins are used for configuration of the S1D13706 and must be connected directly to NIOV pp or Vgs The state of CNF 6 0 is latched on the rising edge of RESET Changing state at any other time has no effect Table 4 8 Summary of Power On Reset Options S1D13706 Power On Reset State Configuration Input 1 connected to NIOVpp 0 Connected to Vss Select hos
534. son Research and Development Page 5 Vancouver Design Center Display Surfaces A display surface is a block of memory assigned to the main window and or sub window of the S1D13706 The sub window is a feature of the S1D13706 Picture In Picture Plus feature For further information on Picture In Picture Plus see the 1D13706 Hardware Functional Specification document number X31B A 001 xx 13706BMP includes three predefined display surfaces 0 2 which cover the possible combinations of these windows Table 1 Display Surfaces lists the display surfaces that may be selected Table 1 Display Surfaces Display Surface Window s using Window s using ds Memory Block 0 Memory Block 1 0 Main Window 1 Main amp Sub window 2 Main Window Sub window When ds 0 bmpfile1 bmp is displayed in the main window If ds n is not specified on the command line this setting is automatically used when bmpfile2 bmp is not provided This should be chosen when a sub window is not required When ds 1 bmpfile1 bmp is displayed in the main window and also in the sub window Note that only a portion of bmpfile 1 bmp is displayed if the sub window is smaller than the resolution of the bmpfile When ds 2 bmpfile1 bmp is displayed in the main window and bmpfile2 bmp is displayed in the sub window This is the most useful combination to demonstrate the Picture In Picture Plus feature 13706BMP Demons
535. splay Driver 320x240 at 8 bits pixel LCD display no rotation Useful Hex Values 1024 0x400 768 0x300 640 0x280 480 0x1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display S 1D13706 Width dword 140 Height dword FO Bpp dword 8 ActiveDisp dword 1 Rotation dword 0 11 Delete all the files in the x wince release directory and delete x wince plat form cepc bif 12 Generate the proper building environment by double clicking on the sample project icon i e X86 DEMO7 13 Type BLDDEMO lt ENTER gt at the command prompt of the X86 DEMO7 window to generate a Windows CE image file NK BIN Build for CEPC X86 on Windows CE Platform Builder 2 1x using a Command Line Interface 1D13706 X31B E 001 04 Throughout this section 2 1x refers to either 2 11 or 2 12 as appropriate 1 Install Microsoft Windows NT v4 0 or 2000 2 Install Microsoft Visual C C version 5 0 or 6 0 3 Install Platform Builder 2 1x by running SETUP EXE from compact disk 1 4 Follow the steps below to create a Build Epson for x86 shortcut which uses the current Minshell project icon shortcut on the Windows desktop a Right click on the Start menu on the taskbar b Click on the item Explore and Exploring Start Menu window will come up c Under x winnt profiles all users start menu programs microsoft windows ce platform builder x86 tools find the icon Build Minshell for x8
536. splay memory unsigned seReadDisplayWord DWORD Offset Description Reads one word from display buffer memory at the specified offset and returns the value Parameters Offset Offset in bytes from start of the display buffer to the word to read Return Value The return value in the least significant word is the word read from display memory DWORD seReadDisplayDword DWORD Offset Description Reads one dword from display buffer memory at the specified offset and returns the value Parameters Offset Offset in bytes from start of the display buffer to the dword to read Return Value The DWORD read from display memory void seWriteDisplayBytes DWORD Offset unsigned Value DWORD Count Description This routine writes one or more bytes to the display buffer at the offset specified by Offset Parameters Offset Offset in bytes from start of display memory to the first byte to be written Value An unsigned integer containing the byte to be written in the least significant byte Count Number of bytes to write All bytes will have the same value Return Value None S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 83 Vancouver Design Center void seWriteDisplayWords DWORD Offset unsigned Value DWORD Count Description This routine writes one or more words to display memory starting at the specified offset Parameters Offset Offset in bytes from the start of displa
537. splayed image e Low latency CPU interface e Picture in Picture Plus e Direct support for the multiple CPU types e Software Initiated Power Save Mode e Programmable Resolutions and Color depths e Hardware or Software Video Invert e STN LCD support e 100 pin TQFP15 package e Active Matrix LCD support e 104 pin CFLGA package e Reflective Active Matrix support E SYSTEM BLOCK DIAGRAM Data and Digital Out Control Signals 3S1D13706 gt O y E A v Flat Panel X31B C 001 03 1 E DESCRIPTION Memory Interface Display Modes Embedded 80K byte SRAM display buffer 1 2 4 8 16 bit per pixel bpp support Up to 64 gray shades using FRM and dithering on CPU Interface monochrome passive LCD panels Pied lowmatoney UPU AECeS8 MNES Up to 64K colors on passive STN panels e Direct support for Hitachi SH 4 SH 3 Up to 64K colors on active matrix panels Motorola M68xxx REDCAP2 DragonBall ColdFire e SwivelView direct hardware rotation of display image MPU bus interface with programmable READY by 90 180 270 Display Support Picture in Picture Plus displays a variable size AB bitmon chrome LCD interface window overlaid over background image Double Buffering multi pages provides smooth 4 8 16 bit color STN LCD interface animation and instantaneous screen update e Single panel single drive passive displays e 9 12 18 bit Active matrix TFT
538. splaying until all data has been shown Where lines Number of lines that are shown before halting the displayed data decimal value I Initializes the S1D13706 registers with the default register settings as configured by the utility 13706CFG To initialize the S1D13706 with different register values reconfigure 13706PLAY using 13706CFG For further information on 13706CFG see the 3706PLAY User Manual document number X31B B 001 xx 13706PLAY Diagnostic Utility Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center L index red green blue Writes red green and blue Look Up Table LUT components for a given display type If the red green and blue components are not specified reads the components at the given index Where index Index into the LUT hex red Red component of the LUT hex green Green component of the LUT hex blue Blue component of the LUT hex Note Only bits 7 2 of each color are used in the LUT For example 04h is the first color in tensity after 00h Valid LUT colors follow the pattern 00h 04h FCh LA Reads all LUT values Note Only bits 7 2 of each color are used in the LUT For example 04h is the first color in tensity after 00h Valid LUT colors follow the pattern 00h 04h FCh M bpp Sets the color depth bpp If no color depth is provided information about the current settings are listed Where bpp Color depth to be set 1 2 4 8 16 bpp
539. ssed and each word of display memory forms the color to display In this mode the least significant word describes the color to draw the circle with in 5 6 5 RGB format Return Value None 1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 95 Vancouver Design Center 10 2 9 Register Display Memory The S5U13706 Evaluation Board utilizes 2M bytes of display memory address space The S1D13706 contains 80K bytes of embedded SDRAM In order for an application to directly access the S1D13706 display memory and registers the following two functions are provided DWORD seGetLinearDisplayAddress void Description Parameters Return Value This function returns the linear address for the start of physical display memory None The return value is the linear address of the start of display memory A linear address is a 32 bit offset in CPU address space DWORD seGetLinearRegAddress void Description Parameters Return Value This function returns the linear address of the start of S1D13706 control registers None The return value is the linear address of the start of S1D13706 control registers A linear address is a 32 bit offset in CPU address space Programming Notes and Examples S1D13706 Issue Date 01 02 23 X31B G 003 03 Page 96 Epson Research and Development Vancouver Design Center 10 3 Porting LIBSE to a new target platform Building Eps
540. ssue Date 01 11 13 Page 7 1D13706 X31B A 001 08 Page 8 Table 6 25 Table 6 26 Table 6 27 Table 6 28 Table 6 29 Table 6 30 Table 6 31 Table 6 32 Table 6 33 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 7 6 Table 8 1 Table 8 2 Table 8 3 Table 8 4 Table 8 5 Table 8 6 Table 8 7 Table 8 8 Table 8 9 Table 8 10 Table 8 11 Table 8 12 Table 8 13 Table 8 14 Table 8 15 Table 8 16 Table 8 17 Table 8 18 Table 8 19 Table 15 1 1D13706 X31B A 001 08 Epson Research and Development Vancouver Design Center 160x160 Sharp Direct HR TFT Panel Vertical Timing 79 320x240 Sharp Direct HR TFT Panel Horizontal Timing 81 320x240 Sharp Direct HR TFT Panel Vertical Timing 81 160x240 Epson D TFD Panel Horizontal Timing 83 160x240 Epson D TFD Panel GCP Horizontal Timing 84 160x240 Epson D TFD Panel Vertical Timing o 85 320x240 Epson D TFD Panel Horizontal Timing 87 320x240 Epson D TFD Panel GCP Horizontal Timing 88 320x240 Epson D TFD Panel Vertical Timing 89 BCEK Clock Selection daa a ented ag r dA OE A eS 90 MCEK Clock Selecti0M o 90 PELE Clock Selection siris sel ate ah rr dr do wd a 91 Relationship between MCLK and PCLK o e 92 PWMCLK Clock Selection
541. st be considered when determining the frequency of CLKI See Section 6 1 2 Internal Clocks on page 35 for internal clock requirements Table 6 3 Clock Input Requirements for CLKI2 2 0V 3 3V Symbol Parameter Units Min Max Min Max fosc Input Clock Frequency CLKI2 20 66 MHz Toso Input Clock period CLKI2 Tose Wosc ns towy nput Clock Pulse Width High CLKI2 3 3 ns toy nput Clock Pulse Width Low CLKI2 3 3 ns t Input Clock Fall Time 10 90 5 5 ns a Input Clock Rise Time 10 90 5 5 ns Note Maximum internal requirements for clocks derived from CLKI2 must be considered when determining the frequency of CLKI2 See Section 6 1 2 Internal Clocks on page 35 for internal clock requirements 1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 35 Vancouver Design Center 6 1 2 Internal Clocks Table 6 4 Internal Clock Requirements 2 0V 3 3V i Symbol Parameter Units Min Max Min Max fsck Bus Clock frequency 20 66 MHz fMCLK Memory Clock frequency 20 50 MHz ek Pixel Clock frequency 20 50 MHz fopwucLk PWM Clock frequency 20 66 MHz Note For further information on internal clocks refer to Section 7 Clocks on page 90 Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 36 6 2 CPU Interface Timing Epson Research and Development Vancouver Design Center Th
542. start address desired byte address panel height x bpp 8 4 1 In SwivelView 180 program the start address desired byte address panel width x panel height x bpp 8 4 1 In SwivelView 270 program the start address desired byte address panel width 1 x panel height x bpp 8 4 Note SwivelView 0 and 180 require the panel width to be a multiple of 32 bits per pixel SwivelView 90 and 270 require the panel height to be a multiple of 32 bits per pix el If this is not possible a virtual display one larger than the physical panel size is re quired which does satisfy the above requirements To create a virtual display program the main window line address offset to values which are greater than that required for the given display width Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 39 Vancouver Design Center REG 78h Main Window Line Address Offset Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 79h Main Window Line Address Offset Register 1 n a n a n a n a n a n a Bit 9 Bit 8 These registers indicate the number of dwords per line in the main window image typically the panel width number of dwords per line image width 32 bpp Note The image width must be a multiple of 32 bpp If the panel width is not such a multi ple a slightly larger width is chosen Note
543. start pulse X 13 RES GPIO4 Reset signal for GCP signal X 14 DO5 FPDATO Red digital data signal MSB X 15 D04 FPDAT1 Red digital data signal X 16 D03 FPDAT2 Red digital data signal X 17 D02 FPDAT9 Red digital data signal X 18 D01 FPDAT10 Red digital data signal X 19 DOO FPDAT11 Red digital data signal LSB X 20 XSCL FPSHIFT Shift clock signal X 21 SHL NIOVDD Shift direction selection for shift registers o e ra X 22 D15 FPDAT3 Green digital data signal MSB X 23 D14 FPDAT4 Green digital data signal X 24 D13 FPDAT5 Green digital data signal X 25 D12 FPDAT12 Green digital data signal X 26 D11 FPDAT13 Green digital data signal X 27 D10 FPDAT14 Green digital data signal LSB X 28 GND VSS GND pc supply logic low and liquid X 29 GND VSS GND a supply logic low and liquid X030 EIO1 VSS GND 1 O enable signal led outed ee Connecting to the Epson D TFD Panels Issue Date 01 02 23 1D13706 X31B G 012 03 Page 16 3 2 LCD Pin Mapping for Y Connector LF37SQT Epson Research and Development Vancouver Design Center Table 3 2 LCD Pin Mapping for Y Connector Pins for Y Driver LF37SQT LCDPin LCD Pin S1D13706 Description Remarks No Name Pin Name P WE GND VSS GND Ground and power supply for liquid crystal drive Forward scanning V5Y Y 2 SHF Shift direction selection for shift registers Reverse scanning VCCY Connect
544. strate and test some of the S1D13706 display capabil ities The program can cycle through all color depths and display a pattern showing all available colors or shades of gray Alternately the user can specify a color depth and display configuration 13706SHOW supports Swivel View 90 180 and 270 hardware rotation of the display image The 13706SHOW demonstration program must be configured and or compiled to work with your hardware platform The utility 13706CFG EXE can be used to configure 13706SHOW For further information on 13706CFG refer to the 13706CFG Users Manual document number X31B B 001 xx This software is designed to work in both embedded and personal computer PC environ ments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which 1s then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection S1D13706 Supported Evaluation Platforms 13706SHOW supports the following S1D13706 evaluation platforms PC system with an Intel 80x86 processor running Windows 9x NT M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 p
545. t the co ordinate x y and is drawn with the specified radius and Color These functions only draw the border of the circle there is no solid fill feature Use seDrawCircle to draw the circle on the current active display surface See seSet MainWinAsActiveSurface and seSetSubWinAsActiveSurface for information about changing the active surface Use seDrawMainWinCircle and seDrawSubWinCircle draw the circle on the display surface indicated by the function name If no memory was allocated to the surface these functions return without writing to dis play memory Parameters x The X co ordinate in pixels of the center of the circle y The Y co ordinate in pixels of the center of the circle Radius Specifies the radius of the circle in pixels Color Specifying the color to draw the circle Color is interpreted differently at different color depths At 1 2 4 and 8 bpp display colors are derived from the lookup table values The least significant byte of Color is an index into the lookup table At 16 bpp the lookup table is bypassed and each word of display memory forms the color to display In this mode the least significant word describes the color to draw the circle with in 5 6 5 RGB format Return Value None Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 94 Epson Research and Development Vancouver Design Center void seDrawEllipse long xc long yc long xr long yr DWORD Colo
546. t 13706CFG Comments 1D13706 X31B B 001 03 Epson Research and Development Vancouver Design Center Tooltips provide useful information about many of the items on the configuration tabs Placing the mouse pointer over nearly any item on any tab generates a popup window containing helpful advice and hints To enable disable tooltips check uncheck the Tooltips option form the Help menu Note Tooltips are enabled by default This Help menu item is actually a hotlink to the Epson Research and Development website Selecting Help then ERD on the Web starts the default web browser and points it to the ERD product web site The latest software drivers and documentation for the S1D13706 is available at this website Selecting the About 13706CFG option from the Help menu displays the about dialog box for 13706CFG The about dialog box contains version information and the copyright notice for 13706CFG e On any tab particular options may be grayed out if selecting them would violate the operational specification of the S1D13706 i e Selecting TFT or STN on the Panel tab enables disables options specific to the panel type e The file panels def is a text file containing operational specifications for several supported and tested panels This file can be edited with any text editor e 13706CFG allows manually altering register values The manual changes may violate memory and LCD timings as spe
547. t Page 69 Vancouver Design Center int seGetResolution unsigned Width unsigned Height void seGetMainWinResolution unsigned Width unsigned Height void seGetSubWinResolution unsigned Width unsigned Height Description Parameters Return Value seGetResolution returns the width and height of the active surface main window or sub window seGetMainWinResolution and seGetSubWinResolution return the width and height of the respective window Virtual dimensions are not accounted for in the return values for width and height For example seGetMainWinResolution always returns the panel dimensions regardless of the value of the line address offset registers The width and height are adjusted for Swivel View orientation Width A pointer to an unsigned integer which will receive the width in pixels for the indicated surface Height A pointer to an unsigned integer which will receive the height in pixels for the indicated surface seGetResolution returns one of the following ERR_OK Function completed successfully ERR_FAILED Returned when there is not an active display surface seGetMainWinResolution and seGetSubWinResolution do not return any value void seSetSubWinCoordinates DWORD x1 DWORD y1 DWORD x2 DWORD y2 Description seSetSubWinCoordinates sets the upper left and lower right corners of the sub window display x1 y1 and x2 y2 are relative to the upper left corner of the panel as d
548. t Page 87 Vancouver Design Center 10 2 7 Virtual Display int seVirtInit DWORD Width DWORD Height int seMainWinVirtinit DWORD Width DWORD Height int seSubWinVirtInit DWORD Width DWORD Height int seMainAndSubWinVirtInit DWORD width DWORD height Description Parameters Return Value These functions prepare the S1D13706 to display a virtual image Virtual Image describes the condition where the image contained in display memory is larger than the physical display In this situation the physical display is used as a window into the larger display memory area display surface Panning right left and scrolling up down are used to move the display in order to view the entire image a portion at a time seVirtInit prepares the current active surface for a virtual image display Memory is allo cated based on width height and the current color depth seMainWinVirtInit initializes and allocates memory for the main window based on width and height and color depth seSubWin VirtInit initializes and allocates memory for the sub window based on current width and height and color depth seMainAndSubWinVirtInit initializes and allocates one block of memory for both the main window and sub window based on width and height and color depth Memory previously allocated for the given display surface is released then reallocated to the larger size Note The width programmed may be larger than that requested in the
549. t bus interface as follows CNF4 CNF2 CNF1 CNFO Host Bus 1 0 0 0 SH 4 SH 3 interface Big Endian 0 0 0 0 SH 4 SH 3 interface Little Endian 1 0 0 1 MC68K 1 Big Endian 0 0 0 1 Reserved 1 0 1 0 MC68K 2 Big Endian 0 0 1 0 Reserved 1 0 1 1 Generic 1 Big Endian CNF4 CNF 2 0 0 0 1 1 Generic 1 Little Endian 1 1 0 0 Reserved 0 1 0 0 Generic 2 Little Endian 1 1 0 1 REDCAP2 Big Endian 0 1 0 1 Reserved 1 1 1 0 DragonBall MC68EZ328 MC68VZ328 Big Endian 0 1 1 0 Reserved X 1 1 1 Reserved Note The host bus interface is 16 bit only Configure GPIO pins as outputs at power on for use CNF3 Configure GPIO pins as inputs at power on by HR TFT D TFD when selected CNF5 WAIT is active high WAIT is active low CLKI to BCLK divide select CNF7 CNF6 CLKI to BCLK Divide Ratio CNF 7 6 0 0 1 1 0 1 2 1 1 0 3 1 1 1 4 1 Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 30 Epson Research and Development Vancouver Design Center 4 6 Host Bus Interface Pin Mapping Table 4 9 Host Bus Interface Pin Mapping Motorola S1D13706 Generic 1 Generic 2 Hitachi Motorola Motorola Motorola MC68EZ328 Pin Name SH 3 SH 4 MC68K 1 MC68K 2 REDCAP2 MC68VZ328 DragonBall AB 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 ABO Ao AO Ao LDS AO Ao Ao DB 15 0 D 15 0 D 15 0 D 15 0 D 15
550. t corner downward in steps of 1 line Program the Sub Window X Start Position registers so that sub window X start position registers y 1D13706 X31B G 003 03 Page 42 Epson Research and Development Vancouver Design Center In Swivel View 180 these registers set the horizontal coordinates x of the sub window s bottom right corner Increasing values of x move the bottom right corner towards the right in steps of 32 bits per pixel see Table 8 1 Program the Sub Window X Start Position registers so that sub window X start position registers panel width x 32 bits per pixel Note panel width x must be a multiple of 32 bits per pixel In Swivel View 270 these registers set the vertical coordinates y of the sub window s bottom left corner Increasing values of y move the bottom left corner downwards in steps of 1 line Program the Sub Window X Start Position registers so that sub window X start position registers panel width y REG 88h Sub Window Y Start Position Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 89h Sub Window Y Start Position Register 1 n a n a n a n a n a n a Bit 9 Bit 8 S1D13706 X31B G 003 03 These bits determine the Y start position of the sub window in relation to the origin of the panel Due to the S1D13706 SwivelView feature the Y start position may not be a vertical position value only true
551. t corner of the sub window be x1 y1 and let x2 x1 width y2 yl height The X position registers set the horizontal coordinates of the sub window bottom right and top left corner Program the X Start Position registers panel width x2 32 bpp Program the X End Position registers panel width x1 32 bpp 1 The Y position registers set the horizontal coordinates of the sub window bottom right and top left corner Program the Y Start Position registers panel height y2 Pro gram the Y End Position registers panel height y1 1 X start position registers 320 80 160 32 4 10 0Ah Y start position registers 240 60 120 60 3Ch X end position registers 320 80 32 4 1 29 1Dh Y end position registers 240 60 1 179 B3h Program the Sub window X Start Position registers REG 84h is set to OAh and REG 85h is set to 00h Program the Sub window Y Start Position registers REG 88h is set to 3Ch and REG 89h is set to 00h Program the Sub window X End Position registers REG 8Ch is set to 1Dh and REG 8Dh is set to 00h Program the Sub window Y End Position registers REG 90h is set to B3h and REG 91h is set to 00h Enable the sub window Program the Sub window Enable bit REG 71h bit 4 is set to 1 Programming Notes and Examples Issue Date 01 02 23 Epson Research and Development Page 57 Vancouver Design Center 8 3 4 SwivelView 270
552. t enable signal nOE is driven low A write cycle is specified by driving nOE high and driving the write enable signal nWE low The cycle can be lengthened by driving RDY high for the time needed to complete the cycle 1D13706 Interfacing to the Intel StrongARM SA 1110 Microprocessor X31B G 019 02 Issue Date 02 06 26 Epson Research and Development Page 9 Vancouver Design Center 2 1 3 Variable Latency IO Access Cycles The first nOE assertion occurs two memory cycles after the assertion of chip select nCS3 nCS4 or nCS5 Two memory cycles prior to the end of minimum nOE or nWE assertion RDF 1 memory cycles the SA 1110 starts sampling the data ready input RDY Samples are taken every half memory cycle until three consecutive samples at the rising edge falling edge and following rising edge of the memory clock indicate that the IO device is ready for data transfer Read data is latched one half memory cycle after the third successful sample on falling edge Then nOE or nWE is deasserted on the next rising edge and the address may change on the subsequent falling edge Prior to a subsequent data cycle nOE or nWE remains deasserted for RDN 1 memory cycles The chip select and byte selects nCAST 1 0 for 16 bit data transfers remain asserted for one memory cycle after the final nOE or nWE deassertion of the burst The SA 1110 is capable of burst cycles during which the chip select remains low while the read or write command is ass
553. t required Wait states are inserted with the synchronous signal STERM which signals that the data is to be latched on the next clock when asserted Interfacing to the Motorola MC68030 Microprocessor 1D13706 Issue Date 01 02 23 X31B G 013 02 Page 10 Epson Research and Development Vancouver Design Center 3 S1D13706 Host Bus Interface The S1D13706 directly supports multiple processors The S1D13706 implements a MC68K 2 Host Bus Interface which directly supports the Motorola MC68030 micropro cessor The MC68K 2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 13 3 1 Host Bus Interface Pin Mapping 1D13706 X31B G 013 02 The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping oe Motorola MC68030 AB 16 0 A 16 0 DB 15 0 D 31 16 WE1 DS CS External Decode M R External Decode CLKI CLK BSH AS RD WR R W RD External Decode of SIZ1 and SIZO WEO SIZO WAITH DSACK1 RESET System RESET Interfacing to the Motorola MC68030 Microprocessor Issue Date 01 02 23 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface
554. t to retain greater control of the build process then use a text editor and cut and paste the sections dealing with the Epson driver in the corresponding files of the same names 4 Modify s1d13706 h The file s1d13706 h contains the register values required to set the screen resolution color depth bpp display type active display LCD display rotation etc Before building the console driver refer to the descriptions in the file s1d13706 h for the default settings of the console driver If the default does not match the configura tion you are building for then s1d13706 h will have to be regenerated with the correct information Use the program 13706CFG to generate the required header file For information on how to use 13706CFG refer to the 13706CFG Configuration Program User Manual document number X31B B 001 xx available at www erd epson com After selecting the desired configuration choose File gt Export and select the C Header File for S1D13706 Generic Drivers option Save the new configuration as s1d13706 h in the usr src linux drivers video replacing the original configuration file 5 Configure the video options From the command prompt in the directory usr src linux run the command make menuconfig This command will start a text based interface which allows the selection of build time parameters From the options presented select Code maturity level options Prompt for development and or incom
555. te WEO WE1 WAIT TA RESET System RESET Note The Motorola MPC821 chip select module only handles 16 bit read cycles As the S1D13706 uses the chip select module to generate CS only 16 bit read cycles are pos sible and both the high and low byte enables can be driven by the MPC821 signal OE Interfacing to the Motorola MPC821 Microprocessor 1D13706 Issue Date 01 02 23 X31B G 009 02 Page 14 Epson Research and Development Vancouver Design Center 3 2 Host Bus Interface Signals 1D13706 X31B G 009 02 The Host Bus Interface requires the following signals CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example SYSCLK from the Motorola MPC821 is used for CLKI The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the MPC821 address A 15 31 and data bus D 0 15 respectively CNF4 must be set to select big endian mode Chip Select CS must be driven low by CS4 whenever the S1D13706 is accessed by the Motorola MPC821 M R memory register selects between memory or register accesses This signal may be connected to an address line allowing system address A14 to be connected to the M R line WEO connects to WEI the low byte enable signal from the MPC821 and must be driven low when the MPC821 is writing the low byte to the S1D13706 WE1 conne
556. te 01 11 13 X31B A 001 08 Page 26 Epson Research and Development Vancouver Design Center 4 4 2 LCD Interface Table 4 4 LCD Interface Pin Descriptions 10 RESET mee Pin Name Type Pin Cell Voltage State Description 74 64 E FPDAT 17 0 O 61 55 LB3P NIOVDD 0 Panel Data bits 17 0 This output pin has multiple functions e Frame Pulse e SPS for Sharp HR TFT DY for Epson D TFD See Table 4 10 LCD Interface Pin Mapping on page 31 for summary FPFRAME O 52 LB3P NIOVDD 0 This output pin has multiple functions e Line Pulse LP for Sharp HR TFT LP for Epson D TFD See Table 4 10 LCD Interface Pin Mapping on page 31 for summary FPLINE O 53 LB3P NIOVDD 0 This output pin has multiple functions e Shift Clock e CLK for Sharp HR TFT e XSCL for Epson D TFD See Table 4 10 LCD Interface Pin Mapping on page 31 for summary FPSHIFT O 54 LB3P NIOVDD 0 This output pin has multiple functions Display enable DRDY for TFT panels e 2nd shift clock FPSHIFT2 for passive LCD with Format 1 interface GCP for Epson D TFD e LCD backplane bias signal MOD for all other LCD panels See Table 4 10 LCD Interface Pin Mapping on page 31 for summary DRDY O 48 LO3 NIOVDD 0 This pin has multiple functions PS for Sharp HR TFT XINH for Epson D TFD GPIOO IO 45 LB3M NIOVDD 0 General purpose lO pin 0 GPIOO e Hardware Video Invert See Table 4
557. te oe A a A las a BS oy teed a EE ea Te es eB 89 10 2 9 Register Display Memory a 95 10 3 Porting LIBSE to a new target platform By Ae Bute a Bat eke 2 ok HO 10 3 1 Building the LIBSE library for SH3 target ls Eaa ARS ard ane es 97 11 Sample Code sucia e eb a o a Bek Ee Mae ens 98 1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2 1 Example Register Values 2 2 2 0 0 20 002 e 11 Table 4 1 Look Up Table Configurations 0 2 0 0 0 000000004 19 Table 4 2 Suggested LUT Values for 1 Bpp Gray Shade 000 20 Table 4 3 Suggested LUT Values for 4 Bpp Gray Shade o o o 20 Table 4 4 Suggested LUT Values for 4 Bpp Gray Shade o o oo 21 Table 4 5 Suggested LUT Values for 1 bpp Color o o o o e o 22 Table 4 6 Suggested LUT Values for 2 bpp Color o o oo e 22 Table 4 7 Suggested LUT Values to Simulate VGA Default 16 Color Palette 23 Table 4 8 Suggested LUT Values to Simulate VGA Default 256 Color Palette 24 Table 7 1 SwivelView Enable Bits o e e 32 Table 8 1 32 bit Address Increments for Color Depth o o o 41 Table 8 2 32 bit Address Increments for Color Depth o o o 42 Table 8 3 32 bit Address
558. ted in x wince300 plat form cepc files For example the display driver section of PLATFORM REG should be as follows when using a 320x240 LCD panel with a color depth of 8 bpp and a Swivel View mode of 0 landscape Default for EPSON Display Driver 320x240 at 8 bits pixel LCD display no rotation Useful Hex Values 1024 0x400 768 0x300 640 0x280 480 0x 1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display S 1D 13706 Width dword 140 Height dword FO Bpp dword 8 ActiveDisp dword 1 Rotation dword 0 Windows CE 3 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 9 Vancouver Design Center 10 Delete all the files in the x wince300 release directory and delete the file x wince300 platform cepc bif 11 Type BLDDEMO lt ENTER gt at the command prompt to generate a Windows CE image file The file generated will be x wince300 release nk bin Windows CE 3 x Display Drivers 1D13706 Issue Date 01 05 25 X31B E 006 01 Page 10 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once the NK BIN file is built the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system The two methods are described below 1 To start CEPC after booting from a floppy drive a Create a bootable floppy disk b Edit CONFIG SYS on the floppy disk to contain only t
559. ted when the memory address is placed on the PC Card bus and one or both of the card enable signals CE1 and CE2 are driven low REG must be kept inactive If only CE1 is driven low 8 bit data transfers are enabled and AO specifies whether the even or odd data byte appears on data bus lines D 7 0 If both CE1 and CE2 are driven low a 16 bit word transfer takes place If only CE2 is driven low an odd byte transfer occurs on data lines D 15 8 Interfacing to the PC Card Bus Issue Date 01 02 23 Epson Research and Development Page 9 Vancouver Design Center During a read cycle OE output enable is driven low A write cycle is specified by driving OE high and driving the write enable signal WE low The cycle can be lengthened by driving WAIT low for the time needed to complete the cycle Figure 2 1 illustrates a typical memory access read cycle on the PC Card bus A 25 0 REG CE1 CE2 OE WAIT D 15 0 ADDRESS VALID Hi Z DATA VALID Be Transfer Start Transfer Complete Figure 2 1 PC Card Read Cycle Figure 2 2 illustrates a typical memory access write cycle on the PC Card bus A 25 0 REG CE1 CE2 OE WAIT D 15 0 ADDRESS VALID nr Hi Z Hi Z DATA VALID Transfer Start Transfer Complete Figure 2 2 PC Card Write Cycle Interfacing to the P
560. ternational Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Integrating the CFLGA 104 pin Chip Scale Package X31B G 018 02 Issue Date 01 02 26 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 INGFOdUCTION 40 sersa sik ee ales AR A AR A AA 5 Package Description ss soe moe A A AA A AS 6 ROUUINO 2 00 eather ow wise Tee E A e AOS E Gl AA ok 7 3D Perimeter Pads 2 ica e ea d ar ee cal e a Re A os a al 327 Inner Pads its aa a A A A a Me ar ES 4 Referentes dcir a A A ala A AA ee a ia 9 4 1 Doctiments e g aora Go ae BO dt a ta ae Ry a as 4D 42 Document Sources Adi 2 9 5 Techni al Support hos aai Eo ae o ai Soe ae ee 10 5 1 EPSON LCD Controllers S1D13706 2 2 2 2 2 2 2 10 List of Figures Figure 3 1 Example Perimeter Pad Routing 2 2 2 0 02 0000000000008 7 Figure 3 2 Example Inner Pad Routing 0 00000022 eee eee 8 Integrating the CFLGA 104 pin Chip Scale Package 1D13706 Issue Date 01 02 26 X31B G 018 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Integrating the CFLGA 104 pin Chip Scale Package X31B G 018 02 Issue Date 01 02 26 Epson Research and Development Page 5 Vancouver Design Center 1 Introd
561. tes x of the sub window s top left corner Increasing values of x move the top left corner towards the right in steps of 32 bits per pixel see Table 8 3 Program the Sub Window X End Position registers so that sub window X end position registers panel width x 32 bits per pixel 1 Note panel width x must be a multiple of 32 bits per pixel In Swivel View 270 these registers set the vertical coordinates y of the sub window s top right corner Increasing values of y move the top right corner downwards in steps of 1 line Program the Sub Window X End Position registers so that sub window X end position registers panel width y 1 Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 46 Epson Research and Development Vancouver Design Center REG 90h Sub Window Y End Position Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 91h Sub Window Y End Position Register 1 n a n a n a n a n a n a Bit 9 Bit 8 1D13706 X31B G 003 03 These bits determine the Y end position of the sub window in relation to the origin of the panel Due to the S1D13706 Swivel View feature the Y end position may not be a vertical position value only true in 0 and 180 SwivelView For further information on defining the value of the Y End Position register see Section 8 3 Picture In Picture Plus Examples on page
562. th 1 Ts t11 GPIO1 GPIO0 pulse width 353 Ts t12 GPIO1 rising edge GPIOO falling edge to FPLINE rise edge 5 Ts t13 GPIO2 toggle edge to FPLINE rise edge 11 Ts 1 Ts pixel clock period 2 tityp REG 22h bits 7 0 1 3 t2typ REG 12h bits 6 0 1 x8 4 t8typ REG 20h bits 6 0 1 5 t7typ REG 16h bits 7 0 5 REG 22h bits 7 0 1 6 t8typ REG 14h bits 6 0 1 x8 t1 le t2 t3 4 eo OOO e e III III t4 n FPFRAME a ee SPS Figure 6 33 320x240 Sharp Direct HR TFT Panel Vertical Timing Table 6 27 320x240 Sharp Direct HR TFT Panel Vertical Timing Symbol Parameter Min Typ Max Units t1 Vertical total period 245 330 Lines t2 Vertical display start position 4 Lines 13 Vertical display period 240 Lines 14 Vertical sync pulse width 2 Lines Hardware Functional Specification S1D13706 Issue Date 01 11 13 X31B A 001 08 Page 82 Epson Research and Development Vancouver Design Center 6 4 12 160x240 Epson D TFD Panel Timing e g LF26SCR t1 FPLINE PO LP t2 t3 e gt FPSHIFT A a er ae a es ae oy XSCL t4 t5 p t6 el FPDAT 17 0 12 Ya Ya 160 R G B t7 18 e gt e LE rid t9 gt t10 t10 gt GPIO4 RES t11 t12 t11 t12 e pid pid pid gt GPIO1 z YSCL t13 a gt GPIOO XINH t14 t15 k f gt GPIO6 YSCLD GPIO2 A FR ha t16 GP
563. the LUT allowing a maximum of only 64K available colors Table 8 9 LCD Bit per pixel Selection Maximum Number of Available Max No Of it per pi Colors Shades i Bit per pixel Color Depth bpp Simultaneously Select Bits 2 0 Passive Panel Displayed Dithering On is Colors Shades 000 1 bpp 64K 64 256K 64 2 2 001 2 bpp 64K 64 256K 64 4 4 010 4 bpp 64K 64 256K 64 16 16 011 8 bpp 64K 64 256K 64 256 64 100 16 bpp 64K 64 64K 64 64K 64 101 110 111 Reserved Special Effects Register REG 71h Read Write Display Data Display Data A PIP Window nla SwivelView Mode Select Word Swap Byte Swap Enable Bits 1 0 7 6 5 4 3 2 1 0 bit 7 Display Data Word Swap The display pipe fetches 32 bits of data from the display buffer This bit enables the lower 16 bit word and the upper 16 bit word to be swapped before sending them to the LCD dis play If the Display Data Byte Swap bit is also enabled then the byte order of the fetched 32 bit data is reversed Note For further information on byte swapping for Big Endian mode see Section 14 Big Endian Bus Interface on page 146 Hardware Functional Specification 1D13706 Issue Date 01 11 13 X31B A 001 08 Page 112 bit 6 Epson Research and Development Vancouver Design Center Display Data Byte Swap The display pipe fetches 32 bits of data from the display buffer This bit enables byte 0 and byte 1 to be swapped
564. the display data output path only Note When Video Data Invert is enabled the video data is inverted after the Look Up Table 11 1 Monochrome Modes The green Look Up Table LUT is used for all monochrome modes 1 Bit per pixel Monochrome Mode Green Look Up Table 256x6 00 00 6 bit Gray Data 5 01 oo 1 bit per pixel data unused Look Up Table entries from Display Buffer Figure 11 1 1 Bit per pixel Monochrome Mode Data Output Path 2 Bit per pixel Monochrome Mode Green Look Up Table 256x6 on 6 bit Gray Data 02 10 03 11 2 bit per pixel data unused Look Up Table entries from Display Buffer Figure 11 2 2 Bit per pixel Monochrome Mode Data Output Path S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 133 Vancouver Design Center 4 Bit per pixel Monochrome Mode Green Look Up Table 256x6 00 7 0000 01 __ 0001 02 0010 03 0011 04 0100 05 0101 06 0110 bi 07 o lora 6 bit Gray Data i 08 1000 09 1001 OA 1010 0B 1011 oC 1100 0D 1101 0E 1110 OF 1111 FC FD FE FF 4 bit per pixel data from D
565. tion S1D13706 X31B A 001 08 Page 10 Figure 6 27 Figure 6 28 Figure 6 29 Figure 6 30 Figure 6 31 Figure 6 32 Figure 6 33 Figure 6 34 Figure 6 35 Figure 6 36 Figure 6 37 Figure 6 38 Figure 6 39 Figure 7 1 Figure 8 1 Figure 8 2 Figure 10 1 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 11 5 Figure 11 6 Figure 11 7 Figure 11 8 Figure 12 1 Figure 12 2 Figure 12 3 Figure 13 1 Figure 13 2 Figure 13 3 Figure 13 4 Figure 14 1 Figure 14 2 Figure 16 1 Figure 16 2 1D13706 X31B A 001 08 Epson Research and Development Vancouver Design Center Generic TFT Panel Timing se hk at we Se a ek Ba 72 18 Bit TFT Panel Timing 20 005 Se ee ee ee ee 73 TET AcG Timing tos ated Jed eke Gadd es Se bP Oh Gots ook a adea 74 160x160 Sharp Direct HR TFT Panel Horizontal Timing 76 160x160 Sharp Direct HR TFT Panel Vertical Timing 78 320x240 Sharp Direct HR TFT Panel Horizontal Timing 80 320x240 Sharp Direct HR TFT Panel Vertical Timing 81 160x240 Epson D TFD Panel Horizontal Timing o a 82 160x240 Epson D TFD Panel GCP Horizontal Timing 84 160x240 Epson D TFD Panel Vertical Timing 0 85 320x240 Epson D TFD Panel Horizontal Timing 320x240 Epson D TFD Panel GCP Horizontal Timing 320x240 Epson D TFD Panel Vertical Timing
566. tional Specification document number X31B A 001 xx 2GPO on H1 can be inverted by setting JP4 to 2 3 gt The Sharp HR TFT MOD signal controls the panel power This must not be confused with the MOD signal used on many passive panels S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center Table 5 2 Extended LCD Signal Connector H2 Page 19 S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date 01 02 23 ne arse Need Color Passive Panel Color TFT Panel seni on re Single Single Others HR D TFD Format 1 Format 2 TFT 4 bit 8 bit 4 bit 8 bit 8 bit 16 Bit 9 bit 12 bit 18 bit 18 bit 18 bit GPIOO 1 GPIOO PS XINH GPIO1 3 GPIO1 CLS YSCL GPIO2 5 GPIO2 REV FR GPIO3 7 GPIO3 SPL FRS GPIO4 9 GPIO4 GPIO4 RES GPIO5 11 GPIO5 GPIO5 DD_P1 GPIO6 13 GPIO6 GPIO6 YSCLD CVOUT 15 CVOUT wo EE eno Note 1 When dip switch SW1 4 is open CNF3 0 at RESET GPIO 6 0 are at low output states after reset If REG 10h bits 1 0 are set for either HR TFT or D TFD some of the pins are used for the HR TFT or D TFD interfaces and are not available as GPIO pins 1D13706 X31B G 004 04 Page 20 Epson Research and Development Vancouver Design Center 6 Technical Description 6 1 PCI Bus Support The S1D13706 does not have on chip PCI bus interface s
567. tions save and exit the configuration utility 6 Compile and install the kernel Build the kernel with the following sequence of commands make dep make clean make bzImage sbin lilo if running lilo Linux Console Driver S1D13706 Issue Date 01 09 19 X31B E 004 02 Page 6 Epson Research and Development Vancouver Design Center 7 Boot to the Linux operating system If you are using lilo Linux Loader modify the lilo configuration file as discussed in the kernel build README file If there were no errors during the build from the com mand prompt run lilo and reboot your system Note In order to use the 1D13706 console driver with X server you need to configure the X server to use the FBDEV device A good place to look for the necessary files and in structions on this process is on the Internet at www xfree86 org S1D13706 Linux Console Driver X31B E 004 02 Issue Date 01 09 19 Epson Research and Development Page 7 Vancouver Design Center Building the Console Driver for Linux Kernel 2 4 x Linux Console Driver Issue Date 01 09 19 Follow the steps below to construct a copy of the Linux operating system using the S1D13706 as the console display device These instructions assume that the GNU devel opment environment is installed and the user is familiar with GNU and the Linux operating system 1 Acquire the Linux kernel source code You can obtain the Linux kernel source code from your Linux supplier or downl
568. to run on other evaluation platforms not listed above 1D13706 X31B B 003 02 Page 4 Installation Usage 1D13706 X31B B 003 02 Epson Research and Development Vancouver Design Center PC platform Copy the file 13706play exe to a directory in the path e g PATH C S1D13706 Embedded platform Download the program 13706play to the system PC platform At the prompt type 13706play Where displays copyright and program version information Embedded platform Execute 1370 6p1lay and at the prompt type the command line argument Where displays copyright and program version information 13706PLAY Diagnostic Utility Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center Commands The following commands are designed to be used from within the 13706PLAY program However simple commands can also be executed from the command line If a command with multiple arguments is executed from the command line it must be enclosed in double quotes e g 13706play f 0 14000 AB q Note If the endian mode of the host platform is big endian reading writing words and dwords to from the registers and display buffer may be incorrect It may be necessary for the user to manually swap the bytes in order to perform the IO correctly For further infor mation on little big endian and the S1D13706 byte word swapping capabilities see the SID13706 Hardware Functional Specification docum
569. to values which are greater than that required for the given display width REG 78h Main Window Line Address Offset Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 79h Main Window Line Address Offset Register 1 n a n a n a n a n a n a Bit 9 Bit 8 These registers indicate the number of dwords per line in the main window image typically the panel width number of dwords per line image width 32 bpp Note The image width must be a multiple of 32 bpp If the panel width is not such a multi ple a slightly larger width is chosen Note Round up to the nearest integer all line address values that have fractional parts 7 2 Examples Example 1 In SwivelView 0 normal mode program the main window registers for a 320x240 panel at color depth of 4 bpp 1 Confirm the main window coordinates are valid The horizontal coordinates must be a multiple of 32 bpp 320 32 4 40 Main window horizontal coordinate is valid Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 34 1D13706 X31B G 003 03 Epson Research and Development Vancouver Design Center 2 Determine the main window display start address The main window is typically placed at the start of display memory which is at display address 0 main window display start address register desired byte address 4 0 Program the Main Window
570. translates all byte accesses correctly to the S1D13706 register and display buffer locations To maintain the correct translation for 16 bit word access even address bytes must be mapped to the MSB of the 16 bit word and odd address bytes to the LSB of the 16 bit word For example Byte write 11h to register address IEh gt REG 1Eh lt 11h Byte write 22h to register address 1Fh gt REG 1Fh lt 22h Word write 1122h to register address 1Eh gt REG 1Eh lt 11h REG 1Fh lt 22h S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Page 147 Vancouver Design Center 14 1 1 16 Bpp Color Depth For 16 bpp color depth the Display Data Byte Swap bit REG 71h bit 6 must be set to 1 Display D 15 8 Buffer D 7 0 Address 15 4 0 15 o 0 Su bb CPU Data oe Byte Swap bb aa System gt Memory cc dd dd e Address bd j i Display Data MSB LSB Byte Swap y OLE dd on System AAA Memory Big Endian Display Buffer Little Endian MSB is assumed to be associated with even address LSB is assumed to be associated with odd address Figure 14 1 Byte swapping for 16 Bpp For 16 bpp color depth the MSB of the 16 bit pixel data 1s stored at the even system memory address location and the LSB of the 16 bit pixel dat
571. tration Program 1D13706 Issue Date 01 02 23 X31B B 004 02 Page 6 Epson Research and Development Vancouver Design Center 13706BMP Examples Comments 1D13706 X31B B 004 02 To display a bmp image in the main window on an LCD type the following 13706bmp bmpfile1 bmp ds 0 To display a bmp image in the main window with 90 SwivelView enabled type the following 13706bmp bmpfile1 bmp ds 0 r90 To display the same bmp image in both the main window and the sub window type the following 13706bmp bmpfile1 bmp ds 1 To display different bmp images independently in the main and sub windows and have the sub window move indefinitely within the main window type the following 13706 bmpfile1 bmp bmpfile2 bmp ds 2 move 1 e 13706BMP displays only Windows BMP format images e A 24 bit true color bitmap is displayed at a color depth of 16 bit per pixel e Only the green component of the image is seen on a monochrome panel 13706BMP Demonstration Program Issue Date 01 02 23 EPSON 1D13706 Embedded Memory LCD Controller Windows CE 2 x Display Drivers Document Number X31B E 001 04 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims an
572. uction This manual provides an example for integrating the CFLGA 104 pin chip scale package CSP available for the S1D13706 It includes an overview of the package and provides an example of how to route the pads This application note is updated as appropriate Please check the Epson Electronics America website at www eea epson com or the Epson Research and Development website at www erd epson com for the latest revision of this document before beginning any devel opment We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Integrating the CFLGA 104 pin Chip Scale Package 1D13706 Issue Date 01 02 26 X31B G 018 02 Page 6 Epson Research and Development Vancouver Design Center 2 Package Description Designing a Chip Scale Package part i e S1D13706 into a printed circuit board requires the use of microvia technology Before starting development of a PCB consult with the board manufacturer for information about the particular microvia technology they use Microvias are commonly defined as vias that have holes less than 0 15mm 0 006 in diameter Microvia technology typically uses the layer located just below the outermost layer Microvias are blind vias that go down only one layer and connect the outer layer with the microvia specific layer The traces on microvia specific layers are connected to the other layers of the board by standard vias The S1D13706 CSP has the followi
573. ues 2 20 00 2 ee ee 12 LCD Pin Mapping for Horizontal Connector Pins for Horizontal Driver 15 LCD Pin Mapping for Y Connector Pins for Y Driver LF37SQT 16 LCD Pin Mapping for Y Connector Pins for Y Driver LF26SCT 17 D TFD Power On Off Sequence Timing e e 18 GCP Data Bit Chain Values for LF37SQT and LF26SCT 20 List of Figures VDDH and VDD Voltage Generation e 8 VEE Switching Power Supply 2 2 0 2 02 002 eee eee eee 9 Temperature Compensated VEEY 0 2 00 eee ee eee 10 VCC Power Supply cco Wk Hehe or ee ar ed Wie ee Ba eB 11 Swing Power Supply for Vertical System Voltages o oo 12 Logic for Vertical Control Signals 2 2 o o ee 13 D TFD Power On Off Sequence TiMiN8 e 18 GCP Data ii oi a id A a Se le ok Fe Beri ay oe A 19 Page 5 1D13706 X31B G 012 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Connecting to the Epson D TFD Panels X31B G 012 03 Issue Date 01 02 23 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software required to connect the S1D13706 to two Epson D TFD Digital Thin Film Diode panels the 320 x 240 LF37SQT and the 160 x 240 LF26SCT The designs described in this document are presented only as examples
574. ul o s sod csr pg te en oe ae ee Oe or es a ee 10 3 1D13706 Host Bus Interface 11 3 1 Host Bus Interface Pin Mapping 11 3 2 Host Bus Interface Signals 2 2 eee 12 4 MCF5307 To S1D13706 Interface lt o o ee 13 4 1 Hardware Description ee 13 4 2 S1D13706 Hardware Configuration 2 2 e ee ee ee 14 4 3 Register Memory Mapping 2 2 2 2 15 4 4 MCF5307 Chip Select Configuration 15 5 SOM Wale cr O tee A A a eh eee aa at ee 16 References ta aos ail ay enh ae Pecan ei ere Minne ac a ay Oe aS 17 6 1 Documents gt arras DE ab ee ae Ae Qe Seok A 6 2 Document Sources a 17 7 Technical Support 2102 ds de See ee A Be Sop a 18 7 1 EPSON LCD Controllers S1D13706 2 2 2 2 2 2 2 2 42 42 18 7 2 Motorola MCF5307 Processor 2 ee ee ee ee 18 Interfacing to the Motorola MCF5307 ColdFire Microprocessor S1D13706 Issue Date 01 02 23 X31B G 010 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X31B G 010 02 Issue Date 01 02 23 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 11 Table 4 2 CLKI to BCLK Divide Selection o o e 14 Table
575. unctionality of the HAL or discontinue its use if no longer required 10 1 API for 13706HAL This section is a description of the HAL library Application Programmers Interface APD Updates and revisions to the HAL may include new functions not included in the following documentation Table 10 1 HAL Functions Function Description Registers the S1D13706 parameters with the HAL seRegisterDevice MUST be the first HAL function called by an application seRegisterDevice selnitReg Initializes the registers LUT and allocates memory for default surfaces seGetHalVersion Returns HAL library version information seHalTerminate Frees up memory allocated by the HAL before the application exits seGetld Identifies the controller by interpreting the revision code register seGetlnstalledMemorySize Returns the total size of the display buffer in bytes seGetAvailableMemorySize Determines the last byte of display buffer available to an application seEnableHardwareDisplaySwapping Enables hardware data swapping for Big Endian systems seGetResolution seGetMainWinResolution Returns the width and height of the active display surface seGetSubWinResolution seSetSubWinCoordinates Sets the sub window coordinates seGetSubWinCoordinates Returns the sub window coordinates seGetBytesPerScanline seGetMainWinBytesPerScanline seGetSubWinBytesPerScanline Returns the number of bytes in each line of the displa
576. upport The S1D13706B00C uses the PCI Bridge FPGA to support the PCI bus 6 2 Direct Host Bus Interface Support The S5U13706B00C is specifically designed to work using the PCI Bridge FPGA in a standard PCI bus environment However the S1D13706 directly supports many other host bus interfaces Connectors H3 and H4 provide the necessary IO pins to interface to these host buses For further information on the host bus interfaces supported see CPU Interface on page 15 Note The PCI Bridge FPGA must be disabled using SW1 10 in order for direct host bus inter face to operate properly 6 3 S1D13706 Embedded Memory The S1D13706 has 80K bytes of embedded SRAM The 80K byte display buffer address space is directly and contiguously available through the 17 bit address bus 6 4 Manual Software Adjustable LCD Panel Positive Power Supply VDDH Most passive LCD color and passive single monochrome LCD panels require a positive bias voltage between 24V and 40V The S5U13706B00C uses a Maxim MAX754 LCD Contrast Controller to provide this voltage range The signal VDDH can be adjusted manually using a potentiometer or controlled through software When JPS is set to position 1 2 VDDH can be controlled through software to provide an output voltage from 20V to 40V CVOUT and GPO of the S1D13706 are connected to LADJ and LON of MAX754 The output voltage VDDH can be adjusted from 20V to 40V in 64 steps by sending pulses to CVOUT Each CVOUT
577. v0 Sto wo evo rh vh nek net nzz o nzo nezo nzo F zvo tvo 0o 6 9 ny 4 ne nse bis vda ms 688 K 1SY Aot AG Age K xo psTeiidog 30N NNOYA3 VONeIbyuos yO da 89d bbLOd3 ou oo py mo NOD Asto OA 1190 MRS AS o 9dn viva H yog sin j 3 H 190 _ NOQ 3NOD 39u 90 LOL Ol 120 LOL as n Z Y LOL9094d3 s o suaac a o 9t aw lt 13934 Na non a ES E in Epson Research and Development Vancouver Design Center 1D13706 X31B G 004 04 D OOOO Figure 10 6 SIDI3706B00C Schematics 6 of 6 01 02 23 S5U13706B00C Rev 1 0 Evaluation Board User Manual Issue Date Page 34 11 Board Layout 1D13706 X31B G 004 04 Epson Research and Development aon a R26 N N O zo 2 CoN y L S z a es S x p AS va z T o S F jea Rg Pees re e 00 oe a Es A E ly gt v o R E 8 O 2 x m 380 5 nA A Mm o u gt 5 o gt SBR OR USDA at 5 Nm Q La a zea 7 53 8 ecu gt N 99 sol de KR gt zo ER e 2 SA o Lo a E gar o vio Zar e LCI 00 gt 2 Ba z q uw wo sw U14 c39 C43 c40 C44 Figure 11 1 SsU13706BO0C Board Layout Vancouver
578. values attach a b suffix to the value e g 0111 b XA Reads all the S1D13706 registers XD index data Writes dword data to the register at index If no data is specified reads the 32 bit dword data from the register at index Where index Index into the registers hex data Data to be written to read from register hex Data can be a list of dwords to be repeated for the duration of the write To use decimal values attach a t suffix to the value e g 100t is 100 decimal To use binary values attach a b suffix to the value e g 0111 b XW index data Writes word data to the register at index If no data is specified reads the 16 bit word data from the register at index Where index Index into the registers hex data Data to be written to read from register hex Data can be a list of words to be repeated for the duration of the write To use decimal values attach a t suffix to the value e g 100t is 100 decimal To use binary values attach a b suffix to the value e g 0111 b 9 Displays the help screen 13706PLAY Diagnostic Utility S1D13706 Issue Date 01 02 23 X31B B 003 02 Page 10 Epson Research and Development Vancouver Design Center 13706PLAY Example 1D13706 X31B B 003 02 1 8 9 Configure 13706PLAY using the utility 13706CFG For further information on 13706CFG see the 13706CFG User Manual document number X31B B 001 xx Type
579. vers provide support for both 8 and 16 bit per pixel color depths The source code is written for portability and contains functionality for most features of the S1D13706 Source code modification is required to provide a smaller more efficient driver for mass production The UGL display drivers are designed around a common configuration include file called mode0 h which is generated by the configuration utility 13706CFG This design allows for easy customization of display type clocks addresses rotation etc by OEMs For further information on 13706CFG see the 13706CFG Configuration Program User Manual document number X31B B 001 xx This document and the source code for the UGL display drivers are updated as appropriate Please check the Epson Electronics America website at http www eea epson com or the Epson Research and Development website at http www erd epson com for the latest revisions before beginning any development We appreciate your comments on our documentation Please contact us via e mail at documentation erd epson com Wind River UGL v1 2 Display Drivers 1D13706 Issue Date 01 02 23 X31B E 003 02 Page 4 Epson Research and Development Vancouver Design Center Building a UGL v1 2 Display Driver 1D13706 X31B E 003 02 The following instructions produce a bootable disk that automatically starts the UGL demo software These instructions assume that the Wind River Tornado platform is correctly installed
580. w 180 mode program the main window registers for a 320x240 panel at a color depth of 4 bpp Confirm the main window coordinates are valid The horizontal coordinates must be a multiple of 32 bpp 320 32 4 40 Main window horizontal coordinate is valid Determine the main window display start address The main window is typically placed at the start of display memory which is at display address 0 main window display start address register desired byte address panel width x panel height x bpp 8 4 1 0 320 x 240 x 4 8 4 1 9599 257Fh Program the Main Window Display Start Address registers REG 74h is set to 7Fh REG 75h is set to 25h and REG 76h is set to 00h Determine the main window line address offset number of dwords per line image width 32 bpp 320 32 4 40 28h Program the Main Window Line Address Offset registers REG 78h is set to 28h and REG 79h is set to 00h Example 4 In SwivelView 270 mode program the main window registers for a 1 Programming Notes and Examples Issue Date 01 02 23 320x240 panel at a color depth of 4 bpp Confirm the main window coordinates are valid The vertical coordinates must be a multiple of 32 bpp 240 32 4 30 Main window coordinates are valid 1D13706 X31B G 003 03 Page 36 7 3 Limitations Epson Research and Development Vancouver Design Center 2 Determine the main window dis
581. wer Save Mode requires proper LCD Power Sequencing See Sec tion 6 LCD Power Sequencing on page 29 5 2 2 Memory Controller Power Save Status REG A0h Power Save Configuration Register Read Write VNDP Status n aie a nja hla Power Save RO Mode Enable The Memory Controller Power Save Status bit is a read only status bit which indicates the power save state of the S1D13706 SRAM interface When this bit returns a 1 the SRAM interface is powered down When this bit returns a 0 the SRAM interface is active This bit returns a O after a chip reset Note The memory clock source may be disabled when this bit returns a 1 Programming Notes and Examples S1D13706 Issue Date 01 02 23 X31B G 003 03 Page 28 Epson Research and Development Vancouver Design Center 5 3 Enabling Power Save Mode Power Save Mode must be enabled using the following steps 1 Disable the LCD bias power using GPO Note The S5U13706B00C uses GPO to control the LCD bias power supplies Your system design may vary Wait for the LCD bias power supply to discharge The discharge time must be based on the time specified in the LCD panel specification Enable Power Save Mode set REG AOb bit 0 to 1 At this time the LCD pixel clock source may be disabled Optional Optionally when the Memory Controller Power Save Status bit REG AOh bit 3 returns a 1 the Memory Clock source may be safely shut down
582. y Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Page 17 Vancouver Design Center 4 Look Up Table LUT This section discusses programming the S1D13706 Look Up Table LUT Included is a summary of the LUT registers recommendations for color gray shade LUT values and additional programming considerations For a discussion of the LUT architecture refer to the 1D13706 Hardware Functional Specification document number X31B A 001 xx The S1D13706 is designed with a LUT consisting of 256 indexed red green blue entries Each LUT entry is six bits wide The color depth bpp determines how many indices are used to output the image to the display For example 1 bpp uses the first 2 indices 2 bpp uses the first 4 indices 4 bpp uses the first 16 indices and 8 bpp uses all 256 indices Note that 16 bpp color depths bypass the LUT entirely In color modes the pixel values stored in the display buffer index directly to an RGB value stored in the LUT In monochrome modes the pixel value indexes into the green component of the LUT and the amount of green at that index controls the intensity Monochrome mode look ups are done based on the Color Mono Panel Select bit REG 10h bit 6 4 1 Registers 4 1 1 Look Up Table Write Registers REG 08h Look Up Table Blue Write Data Register LUT Blue LUT Blue LUT Blue LUT Blue LU
583. y representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13706 Windows CE 2 x Display Drivers X31B E 001 04 Issue Date 01 05 25 Epson Research and Development Page 3 Vancouver Design Center WINDOWS CE 2 x DISPLAY DRIVERS The Windows CE display driver is designed to support the S1D13706 Embedded Memory LCD Controller running under the Microsoft Windows CE 2 x operating system The driver is capable of 4 8 and 16 bit per pixel landscape modes no rotation and 4 8 and 16 bit per pixel Swivel View 90 degree 180 degree and 270 degree modes This document and the source code for the Windows CE drivers are updated as appropriate Before beginning any development please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd epson com for the latest revisions We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Windows CE 2 x Display Drivers 1D13706 Issue Date 01 05 25 X31B E
584. y Drivers 1D13706 Issue Date 01 05 25 X31B E 006 01 Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds The following sections describe how to build the Windows CE display driver for 1 Windows CE Platform Builder 3 00 using the GUI interface 2 Windows CE Platform Builder 3 00 using the command line interface In all examples x refers to the drive letter where Platform Builder is installed Build for CEPC X86 on Windows CE Platform Builder 3 00 using the GUI Interface S1D13706 X31B E 006 01 1 Install Microsoft Windows 2000 Professional or Windows NT Workstation version 4 0 with Service Pack 5 or later Install Windows CE Platform Builder 3 00 Start Platform Builder by double clicking on the Microsoft Windows CE Platform Builder icon Create a new project a Select File New b In the dialog box select the Platforms tab c In the platforms dialog box select WCE Platform set a location for the project such as x myproject set the platform name such as myplatform and set the Processors to Win32 WCE x86 d Click the OK button e In the dialog box WCE Platform Step 1 of 2 select CEPC f Click the Next button g In the dialog box WCE Platform Step 2 of 2 select Maximum OS Maxall h Click the Finish button j i o In the dialog box New Platform Information click the OK button Set the active configurati
585. y memory to the first word to write Value An unsigned integer containing the word to written in the least significant word Count Number of words to write All words will have the same value Return Value None void seWriteDisplayDwords DWORD Offset DWORD Value DWORD Count Description This routine writes one or more dwords to display memory starting at the specified offset Parameters Offset Offset in bytes from the start of display memory to the first dword to write Value The value to be written to display memory Count Number of dwords to write All dwords will have the same value Return Value None Programming Notes and Examples 1D13706 Issue Date 01 02 23 X31B G 003 03 Page 84 Epson Research and Development Vancouver Design Center 10 2 6 Color Manipulation The functions in the Color Manipulation section deal with altering the color values in the Look Up Table directly through the accessor functions and indirectly through the color depth setting functions Keep in mind that all lookup table data is contained in the upper six bits of each byte void seWriteLutEntry int Index BYTE pRGB Description Parameter Return Value seWriteLutEntry writes one lookup table entry to the specified index of the lookup table Index Offset to the lookup table entry to be modified i e a 0 will write the first entry and a 255 will write the last lookup table entry pRGB A pointer to a byte array of data to w
586. y the 1D13706 output signal REV which toggles every time a horizontal sync signal is sent to the panel The REV signal is also used to generate the highest gray scale voltage VO or black by buffering REV and shifting its maximum level to the maximum gray scale voltage CON_POWER CON_POWER is supplied by a National Semiconductor micropower Voltage Regulator LP2951 Figure 2 1 Sharp LQ039Q2DS01 Gray Scale Voltage VO V9 Generation shows the schematic for gray scale voltage generation AIN LK con Power ABA ASK 10 i alia BO RAIH iS a apap aga azar Bu RASH z BI OR AIR Hanveg EE ag aasa su RAL 1 E faid BB BB BE o 2 E z 4 ie asa ae ours ha ours ae ABA MA m swo Evo RW ALSK 1 Pon zac PRA ALEC RA ALSK 1 PEN ALSK 1 A PRA ALE Ex 8 zz 5 202 88 389 22 B gt gt CON POWER AK IR Gl E PSR Bet aA AS E ABI El AIR AD BARANG pag E 5 19 5 ABS ATSK 1 y O RR ATS 5 50K Sd aa Sq 03 75 220uF 25V lt rev Y 74ACTO4 Y 74ACTO4 CON POWER X F2002E S1D13706 X31B G 011 04 Figure 2 1 Sharp LQ039Q2DSO01 Gray Scale Voltage VO V9 Generation Connecting to the Sharp HR TFT Panels Issue Date 01 02 23 Epson Research and Development Page 9 Van
587. ycle see note 1 1 0 ns t15 D 15 0 hold write cycle 0 0 ns t16 WAIT rising edge to D 15 0 valid read cycle 0 ns t17 Rising edge RD to D 15 0 high impedance read cycle 5 31 3 12 ns 1 t14 is the delay from when data is placed on the bus until the data is latched into the write buffer Note Minimum one software WAIT state is required Hardware Functional Specification S1D13706 X31B A 001 08 Page 44 Epson Research and Development Vancouver Design Center 6 2 5 Motorola MC68K 1 Interface Timing e g MC68000 Terk t1 t2 an Y t3 t4 gt 4 A 16 1 M R t6 t5 cs e t7 gt eooo Oh ght AS t11 gt t10 PELEN UDS e LDS t13 t14 gt R W t15 116 DTACK sooo ao t17 t18 lt gt D 15 0 write t19 t20 t21 a gt D 15 0 read VALID Figure 6 6 Motorola MC68K 1 Interface Timing S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Epson Research and Development Vancouver Design Center Table 6 9 Motorola MC68K 1 Interface Timing Page 45 2 0V 3 3V Symbol Parameter Unit Min Max Min Max fcuk Bus Clock Frequency 20 50 MHz Terk Bus Clock period T tcLk I foLk ns t1 Clock pulse width high 22
588. yed image Note that the displayed image may be larger than the physical size of the LCD seSetPowerSaveMode Enables disables power save mode seGetPowerSaveMode Returns the current state of power save mode seSetPowerUpDelay Sets the power on delay for power save mode seSetPowerDownDelay Sets the power down delay for power save mode seCheckEndian Returns the Endian mode of the host CPU platform S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center Table 10 1 HAL Functions Continued Function Description seSetSwivelViewMode Sets the SwivelView orientation of the LCD seGetSwivelViewMode Returns the SwivelView orientation of the LCD seCheckSwivelViewClocks Verifies the clocks are set correctly for the requested SwivelView orientation seDelay Delays the given number of seconds before returning seDisplayBlank seMainWinDisplayBlank seSubWinDisplayBlank Blank unblank the display seDisplayEnable seMainWinDisplayEnable seSubWinDisplayEnable Enable disable the display seGetSurfaceDisplayMode seBeginHighPriority Increase thread priority for time critical routines seEndHighPriority Return thread priority to normal seSetClock Set the programmable clock Returns the display surface associated with the active surface seGetSurfaceSize Returns the number of b
589. ytes allocated to the active surface seGetSurfaceLinearAddress Returns the linear address of the start of display buffer for the active surface seGetSurfaceOffsetAddress Returns the offset from the start of display buffer to the start of surface memory seAllocMainWinSurface seAllocSubWinSurface Manually allocates display buffer memory for a surface seFreeSurface Frees any allocated surface memory seSetMainWinAsActiveSurface seSetSubWinAsActiveSurface Changes the active surface sePwmEnable Enables the PWMCLK circuitry seCvEnable Enables the CV Pulse circuitry sePwmControl Configures the PWMCLK registers seCvControl Configures the CV Pulse registers seReadRegByte Reads one register using a byte access seReadRegWord Reads two registers using a word access seReadRegDword Reads four registers using a dword access seWriteRegByte Writes one register using a byte access seWriteRegWord Writes two registers using a word access seWriteRegDword Writes four registers using a dword access seWriteLutEntry seReadDisplayByte Reads one byte from display buffer seReadDisplayWord Reads one word from display buffer seReadDisplayDword Reads one dword from display buffer seWriteDisplayBytes Writes one or more bytes to display buffer seWriteDisplayWords Writes one or more words to display buffer seWriteDisplayDwords Writes one or more dwords to display buffer
590. zed by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the NEC VR4102 VR4111 Microprocessors 1D13706 Issue Date 01 02 23 X31B G 007 02 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents NEC Electronics Inc VR4102 VR4111 64 32 bit Microprocessor Preliminary User s Manual Epson Research and Development Inc 1D13706 Hardware Functional Specification document number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx Epson Research and Development Inc 1D13706 Programming Notes and Examples document number X31B G 003 xx 6 2 Document Sources e NEC Electronics Inc website http www necel com e Epson Electronics America website http www eea epson com S1D13706 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 02 Issue Date 01 02 23 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 Epson LCD Controllers S1D13706 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson

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