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2. rmn rg 10 OLED BLOCK ee eased 11 PELOCK RESSOURCES a eod R ve a ces 11 SCONTROL CPLD 12 9 TPS WITCHES E 12 SBRITFDGEPPGAQ L uu au aya ah eis tote ut etn A a os ath a 12 S LEPGAZS esa ca Siena EE 12 OD SIO RAM E 12 SET RINE Wie ocu de dt Mete ode yay 12 9 4SERIALE PORT uuu wakaya aD MO aU dei uae aa 12 9 5CPLD INTERFACE sic ede fr tee acp Pct y a pier eoa a EDU dE 13 O9 6F EASH INTERFACE L cati debo omo a Sie edunt Seta 13 9 7 PROGRAMMABLEE CTOCKS siiis di pe chee eee icio eod eodd ete pu eo ns 13 OSS PCIE UE 13 RR GAGs usutay dete bx eh a Asda RU ADR RP vans Pato cera Pus Erro RUNE Da tal se SS 14 DIQ TSRAM BANKS avete oy a gus sua Divo Dee codecs 14 1022DRAM BANKZ u CD 14 10 3MEZZANINE INTERFACE 14 10 3 Hnterface signals u a pao ses uad Vega a Eva 14 10 3 2PoWer SUPPI Va davies eine o du Peru erai i vu dr Read 14 10 4BOARD TO BOARD INTERFACE nnne nennen nnne nnn nnn nnn nnn nnn 14 LIREPFEREBGE DESEIGONS uu u esami dr kiswar auqa 15 Li IDESIGNIR LEES u usa la aaa de eee aan uu duod os eva 15 TI PCONFIGURA TION icai Ets t c
3. 1 14 15 16 17 18 19 2 20 21 22 TP23 TP24 TP25 TP26 TP27 TP28 TP29 TP3 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP4 TP5 TP6 TP7 TP8 TP9 Net avddl phy netc22005 vbatt vcc1 2 vcc1 8 vcc2 5 vcc3 3 vcore_cpld vin_3021a vin 3021b vin 3021c avddh phy vin12 netc22001 vmezz vmgtb1 2 vmgtal 2 vmgt rxb1 5 vmgt rxal 5 vmgt tx1 5 vmgt2 5 vmgt2 0 gnd vpci3 0 vref ddr vref mezz vterm ddr v1 8 phy v1 5 phy netc3013 3V pcie 12V pci 12V con gnd gnd gnd gnd netc5001 netc5010 2 5V vdda u22002 1 8v 3 3V 3 3V 3 3V 3 3V vin 3021d 1 2V 1 7V 3 0V 0 9V 0 6V 0 9V vboot u3001 3 3V 12V 12V vcca u5002 vcca u5005 3 3V 4 5V 3 3V 3 3V page 23
4. agus 15 BZ PL CR 7 oae rote Rees xl an cecal road e ca gaa akoya Quay gaa david a Dd 15 tive e ie ee ede nce Rai a deum eec AA 16 12 1MGT NUMBERING SCHEME nr 16 0 0 Version Issue 10 6 12 2BRIDGE MAIN MGT INTERCONNECT eai 16 12 3 POWERING SCHEME PE 17 12 4MGT REFERENCE CLOCK 125 MHZ sees nns 17 12 5MGT EINE RATE SELECTION rri aa trn raa eei no ez eee nin 18 12 6 NIGT Ke CHARACTERS va ia dias 19 12 7LOGIC CLOCKING SCHEME r 20 12 7 1C locking OVelVIQWS s oer enda ciel U U U valida evan ate elu EU aea EE EV eS Ev YER 20 12 7 2Location of Clock Reset and Test pins nnnm 20 12 7 2T65t heaters o setasevenc o rers Cus erated SE viva as nh Y DADA Reg Ee ER 21 12 8ASSEMBLY DRAWINGS a 22 1AT E uu asawa ete vena 22 12 9 2 2 A sa eda at e E E ETE RARO CU Re RR NU ud dd 22 128 3 TESt POINTS MUT DR 23 page 4 0 ATLAS TDAQ 0 Version Issue 10 6 1 Introduction Brief introductory text 1 1 Glossary acronyms and abbreviations Something else to be defined And here is the description for something
5. The others are freely usable If no protocol is used the following map is suggested page 19 0 0 Version Issue 10 6 12 7 Logic clocking scheme 12 7 1 Clocking overview Logic Clocking 2 Mezz z Main FPGA Program 200MHz 125MHz ICS 156MHz 85411 Bridge FPGA 74LVC CPLD 12 7 2 Location of Clock Reset and Test pins 0 ATLAS TDAQ 0 Version Issue 10 6 NA NA i 12 7 3 Test headers Bridge P12000 Pin 1 2 3 4 5 6 7 8 9 10 2 5V TestO Testl Test2 Test3 Test4 5 Test6 Test7 GND Main P19000 Pin 1 2 3 4 5 6 1 8V TestO Testl Test2 Test3 GND P19000 P12000 1 1 YR ACID ads Pet a ho ah MA e ee ee ee en iut D v LM er page 21 0 Version Issue 10 6 12 8 Assembly drawings 12 8 1 Top O icio cloooo0 IC O O tnb O O O O ale niit pun dug ines cir nn a i mei l hn qne m z E
6. 0 6 8 Control CPLD vhdl cpld cpld1 latex refman pdf 8 1 Switches All switches are defined by the CPLD The current layout is as follows Off Full chain On only FPGA OFF upper FLASH offset ON lower FLASH offset Off fan controlled by temperature sensor On fan on Off auto config after powerup On no auto config 5 Off pci_reset used to trigger reconfiguration ON don t use pci reset Directly mapped to CLK SEL input of 05004 to select 125 0 or 156 25 MHz 1 05001 fixed to 0 General purpose bit forwarded to bridge FPGA via bio switch Default settings are switch 1 left most one ON ON ON OFF ON ON OFF OFF 9 Bridge FPGA 9 1 FPGA 9 2 SDRAM 9 3 Ethernet 9 4 Serial Port A small connector P6000 next to the battery provides two serial interfaces one from each FPGA 5 3 1 Bridge RxD GND Bridge TxD Main TxD GND Main RxD 6 4 2 The corresponding FPGA pins are Main TxD AF21 Main RxD AF19 Bridge TxD A14 Bridge RxD A13 page 12 0 ATLAS TDAQ 0 Version Issue 10 6 9 5 9 6 9 7 9 8 To connect to the serial port of a PC the pins must be connected to the following pins of a 9 pin sub D connector Bridge MPRACE 2 gt sub D 5 3 3 5 1 2 e Main MPRACE gt sub D 6 3 4 5 2 2 CPLD Interface FLASH Interface Programmable Clocks Two programmable clock generators ICS8430AYI 61LF are ava
7. Universitat Mannheim AK 2007 06 1 Lehrstuhl Informatik V MPRACE 2 Insitut fur Technische Informatik Reconfigurable Accelerator User Manual Document Version 1 0 Document ID AK 2007 06 01 Document Date 1899 12 30 Document Status Draft Abstract User manual for the re configurable accelerator MPRACE 2 Institutes and Authors Mannheim University A Kugel 0 page 1 00 0 0 Version Issue 10 6 Table 1 Document Change Record owe e es m EARE 2008 03 28 Clock usage ZARA 2008 04 09 Pin infos and K characters 2010 09 13 Test pin info added page 2 0 ATLAS TDAQ 0 Version Issue 10 6 Contents LEINTRODUCTEIODN S Su Lau aa sao ct cp wide ae RE Nada dans vues NOM aa buaya 5 1 1GLOSSARY ACRONYMS AND ABBREVIATIONS 5 DL 2REEERENGES Ey AE OAE EEEN E 5 ZBOARD DESCRIPTION eie oe eaae es aed tages cun ce RENE sang ONCE Eas Dal cce ee a d d 5 3CONFIGURATION u uu nte uiui aaa dedecus tton n s uA As 7 3 1JTAG CONFIGURATION cis oceans e pr pene asawa pe eb et e DR tes 7 Su ICPEHD Contrada n mnn uut x Uer Pak nl On Ka uk cuc V a eor ia ahay io CO fei 7 3d Ze GA conf gura O costs u Au in mpu m a talus eor Ru be VR SEIEN FEAR FERES DR 7 4POWER ON CONFIGURATIDON nara naar ana 8 SPARALLEL
8. X0Y1 GT11CLK102 X0Y1 X0Y3 GT11CLK110 X1Y0 X1Y1 GT11CLK113 X1Y1 X1Y3 Gt11102A X0Y3 Gt11102B X0Y2 Gt11105A X0Y1 Gt11105B X0Y0 m MGT 12 2 BRIDGE MAIN MGT Interconnect MPRACE2 Aurora link Bridge FX20 FX60 Pin p n Main FX60 Pins p n Lane 0 MGT102A XOY3 XOY7 MGT102A X0Y7 Lane 1 MGT102B X0Y2 XOY6 MGT102B X0Y6 Lane 2 MGT105A XOY1 MGT103A X0Y5 Lane 3 MGT105B XOYO XO0Y2 MGT103B X0Y4 MGTCLK GT11CLK102 1 F26 G26 GT11CLK102 M34 N34 page 16 0 ATLAS TDAQ 0 Version Issue 10 6 12 3 MGT powering scheme 3 regulator MGT supply Main unused 106 109 101 114 aoaw lt 22 gt 59999 aoouuvcrck z3za2r 22z 312 pe Eze foc sz oz Cpe Mr Aba Sty Eta bho 6 g dol foorHAvoX 251144 Bridge unused 103 112 Bridge 102 105 110 112 113 connected to VMGTC1 2 Bridge 103 Main 101 110 112 113 114 connected to 1 2 Main 102 103 105 106 109 connected to VMGTA1 2 12 4 MGT reference clock 125 MHz The latest 2008 XILINX datasheets prohibit the use of a 125 MHz reference clock for data rates of 2 5 Gbit s and higher When CoreGenerator is used to generate such cores the user should select the 156 25MHz reference clock If this is not viable a 250MHz reference clock should be selected instead and the generated source files be modified accordingly The following list shows the different
9. d the bridge FPGA next to the TDO pin gt main is first device LEFT bridge is second device RIGHT in JTAG chain see Figure 4 The JTAG chain is defined by the CPLD and can be modified to include other JTAG capable resources on the board B iMPACT C daten work projekte mprace2 vhdl cpld cpld1 default ipf Boundary Scan 0 x File Edit View Operations Output Debug Window Help B 5 aso x x H SBoundary Scan Available Operations are 23 SlaveSerial S9SelectMAP P SalDesktop Configuration t g3Direct SPI Configuration z B SystemACE xc vfx5 xe4yvtx60 i E PROM File Formatter bypass pcietest bit Operations Boundary Scan X Value of DONE pin 1 Indicates when ID value written does not match chip ID Decryptor error Signal System Monitor Over Temperature Alarm INFO iMPACT 2219 Status register values INFO iMPACT 0011 1111 1111 1110 0000 0000 0000 0000 INFO iMPACT 579 2 Completed downloading bit file to device INFO iMPACT 2 Checking done pin done 2 Programmed successfully PROGRESS END End Operation Elapsed time 6 sec PROGRESS START Starting Operation Configuration Parallel IV 5 MHz LPT1 Z Figure 4 FPGA JTAG Chain page 7 0 Version Issue 10 6 4 Power on configuration The 8MB FLASH memory provides space for 2 sets of configuration bit
10. e p 2 file C daten work projekte mprace2 vhdl main hwtest clkTest clkte 2 Loading file C daten work projekte mprace2 vhdl main hwtest clkTest clktestmain z bit INFO iMPACT Elapsed time 1 sec done INFO iMPACT 501 2 Added Device xc4vfx60 successfully BATCH CMD setCurrentDeviceChain index D file C daten work projekte mprace2 vhdl bridge hwTest cfgTest pcietestfx20 bit used size BATCH CMD setCurrentDeviceChain index D file C daten work projekte mprace2 vhdl main hwtest clkTest clktestmain z bit used size 5235680 4046752 Add one device Figure 5 Prom with data files Now click Generate File in the operations tab The file will be in HEX format and needs to be converted by the download utility 5 Parallel configuration While the bridge FPGA can only be configured through the CPLD power up or JTAG the main FPGA can be configured also from a host PC through the bridge FPGA in one of the parallel SelectMAP modes SMAP8 or SMAP32 SMAP32 mode requires a special setting in the UCF file of the FPGA project CONFIG CONFIG MODE S SELECTMAP32 or CONFIG CONFIG_MODE S_SELECTMAP32 READBACK The latter is required if readback or re configuration will be used and makes the SMAP32 interface persistent Designs compiled without this constraint have to use the SMAP8 mode To be confirmed page 10 0 ATLAS TDAQ 0 Version Issue 10 6 6 LED Block A numbe
11. e proper bitstream region is selected via the switch Click finish on the third screen page 8 0 ATLAS TDAQ 0 Version Issue 10 6 E iMPACT Specify Parallel PROM Device Downstream Daisy Chait Compression Fill Value Output Forma Swap Bits true LoadDirection UP PROM Basename Untitled File Location C daten work projekte mpracez vhdl cpld cpld1 Auto Selcet false Number of Data Stream 1 Number of PROMS 1 PROM Size 83 END of Report page 9 0 Version Issue 10 6 Now add the bitfile for the BRIDGE followed by the bitstream for the MAIN FPGA The bitstreams should be generated with CCLK and drive DONE options DONE pins are NOT wired and on MPRACE 2 There are no data file parameters clock OK on that screen Ix E IMPACT C daten work projektemprace2 vhdl cpld cpld1 default ipf PROM File Formatter File Edit View Operations Window Help _ la enuu S les ole a a Available Operations are H galBoundary Scan p Generate File SlaveSerial SelectMAP Desktop Configuration i mabirect SPI Configuration i gt E SystemACE 2 PROM File Formatter 8M 1983 pul xc4vfx20 xc vfxB pcietestfx20 bit clktestmain z bit Operations 4 Boundary Scan Eq PROM File Formatter J Add one device BATCH CMD setCurrentDeviceChain index 0 BATCH CMD addDevic
12. else 1 2 References 1 XILINX Virtex 4 datatsheet http direct xilinx com bvdocs publications ds302 pdf 2 XILINX Virtex 4 user guide http direct xilinx com bvdocs userguides ug070 pdf 3 XILINX configuration guide http direct xilinx com bvdocs userguides ug071 pdf 4 XILINX coolrunner datasheet http direct xilinx com bvdocs publications ds090 pdf 5 XILINX coolruner userguide http direct xilinx com bvdocs publications ds094 pdf 6 2 Board description Fehler Referenz nicht gefunden shows the block diagram of MPRACE 2 A small Virtex 4FX FPGA 1 2 1 2 implements the bridge to PCIe or PCI X host bus MPRACE 2 Block diagram MGT External frequency 200 250MHz Expansion 110 pi LA MGT n DDR 12 SODIMM Max 128M 64 1GB Main FPGA DDR SRAI XCAVFX60 lt DDR 2 SRAM 1M 2M 72 1M 2M 72 CIk 25 125 200MHz Prog Clock i PECL100 400MHz gt lt lt APCIe PCI X Bridg pe gel Y V Fast configuration interface NXCAVFX 0 SDR ri 4 serial lanes each 2 5GBd per dir PCIe 4 lanes 2 5GBd oi PCI X 133 MHz Figure 1 Block diagram page 5 0 0 Version Issue 10 6 It is equipped with 16MB of SDRAM a GbE interface a serial port and connects to the control CPLD 1 21 2 Via the CPLD the FLASH memory can be accessed which stores configuration bitstreams and potentially boot software for the embedded processor The main FPGA connec
13. gister area dummy RAM via PCI BAR2 It consists of the following modules e BRIDGE FPGA design mprace2 vhdl bridge hwtest cfgTest e MAIN FPGA design mprace2 vhdl main hwtest clkTest e Test program mprace2 c cfgTest page 15 0 0 Version Issue 10 6 12 Appendix 12 1 MGT numbering scheme MAIN FPGA Fx60 FX100 Additional MGTs 100 GT11CLK102 X0Y3 MGT Clocking Gt11101A X0Y9 GT11CLK105 X0Y1 Gt11101B X0Y8 GT11CLK113 X1Y3 GT11CLK110 X1Y1 Gt11114A X0Y9 I Gt11114B X0Y8 Gt11106A X0Y1 105 TO B2Bup Gt11106B Mezz PAN aA B106 5 Gt11105A XOY3 Gt11105B 2 Gt11103A XOY5 3105 Main FPGA 110 Gt11103B XOY4 XCAVFX60 Gt11102A X0Y7 103 T i Gt11102B X0Y6 jo 0 1 2 3 0 1 2 A 102 113 3 B2Bdn Gt11109A X1Y1 Gt11109B X1YO Gt11110A X1Y3 Gt11110B X1Y2 Gt11112A X1Y5 Gt11112B X1Y4 Gt11113A X1Y7 Gt11113B X1Y6 102 113 PClexpress 102 110 20 XOY7 oe LaneO 110A X1Y1 110 Lane1 110B X1Y0 B B Lane2 113A X1Y3 Lane3 113B X1Y2 A A CLK 113 GT11CLKX1Y1 105 113 X0Y6 B B PCle FX60 X0Y3 P LaneO 110A 1 X0Y2 105 __ 1 110B X1Y2 _ Lane2 113A X1Y7 Gt11113A X1Y3 X1Y7 Lane3 113B X1Y6 Gt11113B X1Y2 X1Y6 Gt11110A X1Y1 X1Y3 Gt11110B X1Y0 X1Y2 Bridge FPGA Fx20 FX60 GT11CLK105 X0Y0
14. ilable to provide clock frequencies in the range of 25 to 250 MHz to the main FPGA One generator feeds the FPGA fabric clocking resources the other one feeds a MGT clock in each of the two columns The clock generators are programmed to a default frequency of 125MHz via the RESET signal Care must be taken that the control lines from the bridge FPGA are properly initialised to 0 PCle PCI X MPRACE 2 uses the following PCI configuration words hex PCle Version e Vendor ID 10DC e Device ID 0153 e Subsystem vendor ID 0084 e Subsystem device ID AC2E PCI X Version e Vendor ID 10DC e Device ID 0153 e Subsystem vendor ID 0084 e Subsystem device ID AC2A page 13 0 0 Version Issue 10 6 10 Main FPGA DDR2 SDRAM E Add On Connector lt P gt INVE Figure 6 Main FPGA bank MGT usage 10 1 SRAM banks 10 2 DRAM bank 10 3 Mezzanine interface 10 3 1 Interface signals 10 3 2 Power supply 10 4 Board to board interface page 14 0 ATLAS TDAQ 0 Version Issue 10 6 11 Reference designs 11 1 Design Rules 11 2 Configuration 11 2 1 CfgTest CfgTest is available at the CVS repository and provides the following functionality e Access to CPLD registers e Access to FLASH memory e SMAP8 and SMAP32 configuration of MAIN FPGA e Access to MAIN FPGA re
15. r of LEDs are used to display status information 4 LEDs connect to the CPLD and two LEDs to each of the FPGAs The LED are labelled left to right D5000 D5001 LD4001 LD4000 U d OU DUE ood quot u ooo oooi 2004 cay amp 22004 S 14150 14044 14045 1405 Figure 9 LED block LD6000 LD4001 LD4000 D5000 and 5001 are single LEDs the others are bi colour LEDs The LEDs are positioned in the upper right area of the board close to the upper JTAG connector a shown in Fehler Referenz nicht gefunden LED Usage D5000 Design dependent LD4000 lower red CPLD LEDO Power good normally ON Table 2 LED block 7 Clock ressources A number of fixed and variable frequency oscillators is available on MPRACE 2 All MGT clocks with the exception of the PCIe interface can be derived from the dual frequency oscillator U5004 which provides 125MHz default or 156 25MHz selectable via a CPLD signal On the MAIN FPGA the MGT clocks can alternatively be derived from the programmable clock source U5005 see section 9 7 According to the 2008 datasheet an MGT reference clock of 125 MHz is no longer valid In future assembly versions the 125MHz will be replaced by 250MHz See appendix 12 4 on how to modify MGT cores generated by the XILINX tools to use 125MHz page 11 0 0 Version Issue 1
16. settings 1 250 MHz case e MGT attributes in instantiation code VHDL RXPLLNDIVSEL gt 10 TXPLLNDIVSEL gt 10 page 17 0 0 Version Issue 10 6 e MGT attributes in UCF constraints alternative to VHDL INST mgt instance RXPLLNDIVSEL 10 INST mgt instance TXPLLNDIVSEL 10 e UCF timing constraints NET ref clk1 left 1i PERIOD 4 0 ns 2 125 MHz case e MGT instantiation code generic map RXPLLNDIVSEL gt 20 TXPLLNDIVSEL gt 20 e MGT attributes in UCF constraints alternative to VHDL INST mgt instance RXPLLNDIVSEL 20 INST mgt instance TXPLLNDIVSEL 20 e UCF constraints NET ref_clk1_left_i PERIOD 8 0 ns All tests done so far show proper operation with a 125MHz reference clock as well 12 5 MGT Line rate selection The MGT line rate can be selectied to 2 5 Gbit s or 5 0 Gbit s via the parameters TXOUTDIV2SEL RXOUTDIV2SEL in the VHDL UCF file Choose a value of 2 for 2 5 Gbit s and 1 for 5 0 Gbit s Choose the proper settings for the reference clock as described above page 18 0 ATLAS TDAQ 0 Version Issue 10 6 12 6 MGT K characters Table B 2 Valid Control K Characters Name HGF EDCBA abcdei fghj abcdei fghj Notes 1 Used for testing and characterization only Note Bit positions of 10 bit values are reversed wrt CoreGen Normally one of the K characters is used for comma alignement Two more K28 1 and K28 7 also trigger the comma alignement circuitry of the MGT
17. streams and for PowerPC software The memory regions are defined by the CPLD For the MPRACE 2 prototypes which have an XCAVFX60 device as bridge care has to be taken that the combined size of the bridge and main FPGA bitstreams does not exceed 3MB This can normally be achieved using bitstream compression but cannot be guaranteed for all designs For the moment the configuration set is selected using one of the DIP switches However an automatic setting using the PCl power available signal can also be implemented by modification of the CPLD code 3 iMPACT Prepare PROM Files b 10 x want to target a C Xilinx PROM Generic Parallel PROM C 3rd Party SPI PROM C PROM Supporting Multiple Design Versions Spartan3E MultiBoot PROM File Format C MCS C TEK C C format C C BIN ISC HEX Swap Bits Checksum Fill Value 2 Hex Digits FF PROM File Name Location C daten work projekte mprace2 vhdl cpld cpld1 Browse Figure 2 Prepare PROM The configuration bitstreams are loaded by the CPLD in slave serial mode into the chain of the two FPGAs The first device is the bridge FPGA The top most 2MB of the FLASH can be used for boot code for the PowerPC in the bridge FPGA The FLASH file has to be prepared from two bitfiles with the BRIDGE content located at the beginning lower address Impact can be used to generate the content in HEX format see below Make sure that th
18. ts via 4 serial links and a parallel 32 bit interface to the bridge FPGA The parallel interface is mainly intended for configuration purposes SelectMAP8 SelectMAP32 but may be used otherwise as well The main FPGA is equipped with 2 banks of SRAM and 1 bank of DRAM all of DDR 2 type A set of high speed connectors enable expansion via mezzanine boards In addition two e g daisy chain style board to board connections can be established via serial links PWR Reconfigurable MPRACE 2 Accelerator GbE Emm PHY Figure 1 Board sketch A sketch of the final board is shown in Figure 1 and a picture of the first version is shown in Fehler Referenz nicht gefunden Assembly drawings version 2 are displayed in sections and CPLD JTAG v8vr616tL00 5090050 e511533 O9XJAVOX T XCHLLMLA FPGA JTAG Figure 3 MPRACE 2 version 1 page 6 0 ATLAS TDAQ 0 Version Issue 10 6 3 Configuration 3 1 JTAG configuration 3 1 1 CPLD configuration Configuration of the CPLD XC2C256 is done via JTAG using the connector at the upper side of the board close to main FPGA 3 1 2 FPGA configuration JTAG configuration of the two FPGAs is done via the lower connector close to the PCIe PCI X connector The FPGAs form a chain defined by logic in the CPLD with the main FPGA next to the TDI pin an

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