Laboratory assignment 1
Contents
1. as shown in 8 8 To program the FPGA press Start 9 Verify that your design works by changing the position of the toggle switches on the DE1 SoC board X Programmer mn felt u11 ketilroe Data teaching fys4220 labs lab1 quartus lab1_gx lab1_gx Ch File Edit View Processing Tools Window Help Search altera com A Hardware Setup DE Soc 1 1 3 Mode JTAG bed Progress I Enable real time ISP to allow background programming for MAX II and MAX V devices Sh Start Device Checksum Usercode Programy Verify Blank sailed nels Configure Check a Stop SOCVHPS 00000000 lt none gt r jE E m 4 Auto Detec X Delete ity Add File hele anmannan XLED amaa m Found devices with shared JTAG ID for device 2 Please select your device C 5CSEBA5 5CSEMA5 i Change File ab Save File Add Device C 5CSTFD5D5 fh Up C 5CSXFC5C6 J Down C 5CSXFC5D6 File Edit View Processing Tools Window Help 3 Search alteraccom A Hardware Setup DE Soc 1 1 3 Mode JTAG bd Progress I Enable real time ISP to allow background programming for MAX II and MAX V devices B Start Device Checksum Usercode Program Verify Blank a Configure Check dh Stop SOCVHPS 00000000 lt none gt E E a fF 5CSEMA5 00000000 lt none gt fz r E Auto Detec x Delete ty Add File is Change File lab Save File 3 Add Device Th Up J Down SOCVHPS 5CSEMA5 Figure 7 Two devi2. acc lt HEXA L line_18 lab1 top_le Process acc lt View Declaration ke stimuli_process tb_labl1 tes Process acc lt View Memory Contents W standard standard Package Package acc lt OT W textio textio Package Package acc lt Add Wave Ctrl W W std_logic 1164 std_logic_1 Package Package acc lt Add Wave New W numeric_std numeric_std Package Package acc lt Add Wave To r Add Dataflow Ctrl D Figure 13 Add signals to the wave window npile Add Objects Tools Layout 3 Start Simulation m e Runtime Options ault a Run 100 _ Step r Restart Continue Run Next Top Break DU Ii End Simulation DU Ii lablitop le Process labl top le Process Figure 14 Choos Run all under Run Simulation 13 UiO University of Oslo rel Wave or n f P oes File Edit View Add Format Tools Bookmarks Window Help Use the zoom buttons to provide the best view of your simulation result i E 8 x ie B Feats pean a E E we J ER 100 ps 2 zl ek EL G A GA F l wo a A fv e LEELA Es gE Ge Search v i a in iT T Msgs tb_lab1_gx LEDR 0000000000000 G00000000d00000cho J000000 000000 1000000 J000000 1000000 000000 Joo0000 1000000 000000 J000000 J000000 000000 J000000 000000 1000000 tb_lab1 gx Sw 00000 90000 Jo0001 1 00002 100003 a 00004
3. should be in creased in steps of 1 counter lt counter 1 on the rising edge of the clk and only when the ext_ena_n 0 e Include the library numeric std all in order to allow for arithmetic opera tions and the use of the type unsigned 4 Modify the test bench file tb_labl vhd in order to simulate the functional be haviour of the counter see 5 You need to update the component and port map of lab1 with the relevant new ports add the corresponding test bench signals generate a 50 MHz clock and produce the relevant stimuli to test the counter 14 UiO University of Oslo J Run a functional simulation and verify that the output HEXO counts up as ex pected 6 Before trying the new design on the DE1 SoC card you need to first add the correct pinning assignments for the new ports Add the assignments as shown in Listing 6 to the pinning tcl file and re run the tcl script Verify that the new pinning assignments have been performed library ieee use ieee std_logic_1164 all1 use ieee numeric_std all entity tb_labi is end architecture testbench of tb_labi is signal LEDR std_logic_vector 9 downto 0 signal SW std_logic_vector 9 downto 0 signal HEXO std_logic_vector 6 downto 0 Signal clk50 std_logic Signal reset_n std_logic Signal ext_ena_n std_logic signal clk_ena boolean constant clk_period time 20 ns 50 MHz component labi is port LEDR out std_logic_ve
4. timing netlist by double clicking on Create Timing Netlist Choose File gt New SDC file The SDC editor opens Choose Edit gt Insert constraint gt Create clock This will open a new window as seen in Figure 17 Set the clock name to be the same as the name of the clock input port of the design clk50 Constrain the clock to 50 MHz by setting a clock period of 20 ns The constraint needs to be identified with its correct port Press the button next to the Target field and find the clk50 port as shown in 18 The corresponding SDC command is also shown Press Insert and this command will be added to the SDC editor Save this file in the constraints folder with the name labl_gx sdc Add this file to the Quartus project Project gt Add current file to project Close the SDC editor window and recompile the Quartus project Verify that the warning Timing requirements not met is no longer present and that the clock has been constraint to 50 MHz in the com pliation report 4 Program the FPGA 5 Press KEYO to start the counter What happens Are you able increment the value of the 7 segment display in steps of 1 If not can you explain why 17 UiO University of Oslo Jar r OH S Ol gt F G oel w Compilation Report lab1_gx x Table of Contents Ae KLS CE Fowsummay clock name type Period Frequency Rise Fan E Flow Settings 1 cIk50 Base 1 000 1000 0MHz 0 000 0
5. 500 Flow Non Default Global E5 Flow Elapsed Time EA Flow OS Summary E Flow Log Analysis amp Synthesis Fitter a Assembler 2 TimeQuest Timing Analy E Summary A Parallel Compilation _ E Slow 1100mv 85C Mo _ amp Slow 1100mv OC Mod _ amp G Fast 1100mv 85C Mo _ amp Fast 1100mv OC Mod E Multicomer Timing An 49 Multicorner Datashee 8 09 Advanced I O Timing H amp Clock Transfers Report TCCS E Report RSKM E Unconstrained Paths QD Messages 9 EDA Netlist Writer D Flow Messages i CD Flow Suppressed a gt an C Ee ea Figure 16 Compilation report showing that a clock frequency of 1000 MHz have been considered for the design 8 0 0 N Create Clock Clock name ckSO Period 20 000 ns Waveform edges Rising Doo ns Falling Doo ns PL 0 00 10 00 20 00 Targets get_ports clk50 SDC command clock name clk50 period 20 000 get_ports clk50 Insert Cancel Help i af Figure 17 Constrain the clock to 50 MHz by setting a clock period of 20 ns 18 UiO University of Oslo eoo Name Finder Collection get_ports Filter Options M Case insensitive F Hierarchical E Compatibility mode No duplicates Matches List 30 matches found 1 selected name clk50 SDC commana get_ports clk50 OK Cancel Help Figure 18 Find the target port to which the co
6. GXB Channel PMA GXB Channel PCS PC 5CSEMA5F31C6 1 1V 32070 457 457 0 0 0 Help lt Back O Next gt Finish Cancel Figure 2 Choose the correct FPGA device UiO University of Oslo Figure 3 EDA Tool Settings page 4 of 5 Specify the other EDA tools used with the Quartus II software to develop your project EDA tools Tool Name lt None gt v Tool Type Format s lt None gt v Run Tool Automatically Design Entry Synthesis Run this tool automatically to synthesize the current design ModelSim Altera Z E Run gate evel simulation automatically after compilation Timing Symbol Signal Integrity Simulation Formal Verification Board Level Boundary Scan Select ModelSim Altera and VHDL under Simulation and press next Create a new VHDL file 1 Inside the directory lab1 create a new directory called vhd_src 2 Open your favourite text editor e g Notepad enter the VHDL description as shown in Listing 1 and add the appropriate statement for controlling the LEDs using the switches Save the file in the directory lab1 vhd src and give it the name labl vhd 3 Add the new VHDL file to the project as shown in Figure 4 Project gt Add Remove Files in Project Settings lab1 Category 1 Locate correct file E General Files n Select the design files you want to include in the project Click Add All to add design files in the Libraries project director
7. Joo005 J00006 100007 oo008 00009 0000A 100008 Jooooc 0000D J0000E JD000F_ tblat x HEXO 1000000 1000000 4111001 0100100 0110000 jo0011001 0010010 J0000010 1111000 J0000000 J0010000 0001000 J0000011 1000110 0100001 0000110 J0001110 act lul Now 100000 ps Cursor 1 23398 ps 4 ri 4 i k 14478 ps to 100828 BY right clicking on any of the signals you can e g select to show the values in hexadecimal format Radix gt Hexadecimal Figure 15 Simulation result Program the FPGA 1 Return to Quartus compile the design and program the FPGA Verify that you can use the switches to set the correct number on the 7 segment display 2 Synchronous process 2 1 4 bit counter and push button In the second part of this lab assignment you will implement a counter and use one of the push button KEY1 on the DEI SoC card to increase the counter value in steps of one The counter value will be shown on the 7 segment display A second push button KEYO will be used to reset the counter The reset will be synchronous to the system clock Create the 4 bit counter with active low synchronous reset i Modify the entity of lab1 and add the following ports clk50 in std_logic_vector reset_n in std_logic_vector 6 ext_ena_n in std_logic 2 Declare the internal signal e signal counter unsigned 3 downto 0 0000 3 Write a VHDL process for the 4 bit counter The counter value
8. UiO University of Oslo Course Group number FYS4220 Real time and embedded systems Laboratory assignment 1 Combinational logic and synchronous process August 20 2015 DUE DATE 15 September 2015 Completed by Date Name E mail Name E mail Requirements ONLY the following files documents are to be submitted Report fys4220_report_groupX_name1_name2 pdf Final design file containing all the relevant sub assignments lab1 vhd The report must be in pdf format be well structured contain a coverpage similar to the coverpage of this document describe what you have done and any problems you have encountered during the work answer any questions which are listed in the assignment text include figures with screenshots of the various wave diagrams produced when simulating the 7 segment decoder and 4 bit counter Submitted requested files documents by e mail to the course responsible UiO University of Oslo Contents 1 Quartus project combinatorial logic and functional simulation 2 1 1 Switches and LEDs oaaae aa ww ee ew Bw 2 1 2 segment decoder with functional simulation 9 2 Synchronous process 14 2A Asi counter and push DUTON gt as s se a a soes sarera tenan 14 22 FEdped tector se se s soss sda cs mad aa Sara RR ed Re YR 19 Introduction This lab assignment contains two parts In the first part you will implement a simple desi
9. binations of input values for SW 3 downto 0 and validate the expected value of HEXO Chang value every 20 ns SW 3 downto 0 lt X 0 process wait SW 3 wait SW 3 wait SW 3 wait SW 3 wait SW 3 wait SW 3 wait SW 3 wait SW 3 wait SW 3 wait SW 3 wait SW 3 wait SW 3 wait SW 3 wait SW 3 wait SW 3 wait end process stimuli_process for 20 downto for 20 downto for 20 downto for 20 downto for 20 downto for 20 downto for 20 downto for 20 downto for 20 downto for 20 downto for 20 downto for 20 downto for 20 downto for 20 downto for 20 downto ns 0 lt ns 0 lt ns 0 lt ns 0 lt ns 0 lt ns 0 lt ns 0 lt ns 0 lt ns 0 lt ns 0 lt ns 0 lt ns 0 lt ns 0 lt ns 0 lt ns 0 lt a ye ae xs x q4 Des dare KO X 7 AS Os xu AM X B xc l Xx D X E X F end architecture testbench Listing 4 Some caption 11 UiO University of Oslo eoo x Create Project Project ame H H H_ 7 i Project Location space GITprojects fys4220 lab 1abl sim Browse Default Library Xame s HH _ work Copy Settings From 14 al modelsim ase modelsim ini Browse Copy Library Mappings Reference Library Mappings OK Cancel Figure 9 Creating a project in Modelsim X Add i
10. ces are detected in the JTAG chain UiO University of Oslo O O X Programmer mn felt u11 ketilroe Data teaching fys4220 labs lab1 quartus lab1 _gx labl_gx Ch File Edit View Processing Tools Window Help 3 Hardware Setup DE SoC 1 1 3 Mode JTAG Progress o Enable real time ISP to allow background programming for MAX II and MAX V devices i Device Checksum Usercode Program Verify Blank Exa Mo stats eo ae ee Confi mi C ab Stoj SOCVHPS 00000000 lt none gt J 4 Auto Detec z x Delete Add File i Change File output_files lab1_gx sof 5CSEMA5F31 OOAFASB8 OOAFASBS SOCVHPS 5CSEMA5F31 Figure 8 Final setup for programming of the FPGA To program the FPGA press Start 1 2 segment decoder with functional simulation The objective of this part is to control one of the 7 segment displays using four switches on the DE1 SoC board For this you need to implement a 7 segment decoder in VHDL Before programming the board you will verify the correct behaviour of the design using a functional simulation Preparing the project 1 The 7 segment decoder see FYS4220 lecture 2 3 shall be added as a statement in the labl vhd design file and implemented using selected signal assignment with select 2 You also need to modify the entity description by adding an additional output port vector 7 bits wide using the identifier nam
11. clocks defined in design Synopsys Design Constraints File file not found These warnings can for the moment be ignored 3 If the compilation of the project was successful Quartus has generated and SRAM object file sof either in the project directory itself or in the directory output files under the project directory This is the programming file that will be downloaded to the FPGA Make sure to connect the USB cable to the USB connector on the DE1 SoC board marked with BLASTER Connect the power cable and turn on the power by pressing the red button 4 Open the Quartus programmer Tools gt Programmer 5 If the field next to the button Hardware Setup shows No Hardware make sure the USB cable is connect to both the PC and the DE1 SoC board and that the power is turned on Press the Hardware Setup and choose USB blaser under the Currently selected hardware Press Close 6 Pressing Auto Detect will bring up a small window as seen in Figure 6 where you will have to specify the correct device 5CSEMA5 Press OK As shown in 7 two devices are detected in the JTAG chain One is the Hard Processor System HPS of the Cyclone V SoC FPGA ARM CPU and the other is the programmable logic part of the same FPGA UiO University of Oslo T Double click on the 5CSEMA5 device and select the correct programming file Tick the box for Programming Configure You should now end up with a setup
12. convenient to represent them as arrays in the entity description of the VHDL code UiO University of Oslo library IEEE use EEE std_logic_1164 all entity labi is port LEDR out std_logic_vector 9 downto 0 Red LEDs SW in std_logic_vector 9 downto 0 Switches end entity labi architecture top_level of labi is begin Insert statement to assign all switches to the LEDs end architecture top_level Listing 1 Top level VHDL code for connecting the switch inputs to the LED outputs Perform the following steps to implement a circuit corresponding to the VHDL code in Listing 1 on the DE1 SoC board Create a new project 1 Create a new directory called lab1 at a suitable location such as in your UiO home directory which is backed up every day Inside this directory create an other directly called quartus 2 Start the Quartus II program 3 Create a new Quartus II project from File gt New Project Wizard called lab1 and choose lab1 quartus as the working directory The name of the top level design will automatically take the same name as the project Keep this name Press Next Figure 1 4 For page 2 of 5 press Next without adding any files Design files will be added later 5 For page 3 of 5 Figure 2 select the correct FPGA model Cyclone V SE 5CSEMA5F31C6 as the target chip Press Next 6 For page 4 of 5 you should select Modelsim Altera under Simulation Tool name and VHDL unde
13. ctor 9 downto 0 SW in std_logic_vector 9 downto 0 HEXO out std_logic_vector 6 downto 0 cl1k50 in std_logic reset_n in std_logic ext_ena_n in std_logic end component lab1 begin UUT labi port map LEDR gt LEDR SW gt SW HEXO gt HEXO clk50 gt c1k50 reset_n gt reset_n ext_ena_n gt ext_ena_n create a 50 MHz clock clk50 lt not clk50 after clk_period 2 when clk_ena else 0 stimuli_process process begin 2ab set default values clk_ena lt false reset_n lt 1 15 UiO University of Oslo ext_ena_n lt 1 SW lt others gt 07 enable clk and wait for 3 clk periods clk_ena lt true wait for 3 clk_period assert reset_n for 3 clk periods reset_n lt Q wait for 3 clk_period deassert reset_n for 3 clk periods reset_n 1 wait for 3 clk_period enable counter and wait for 20 clk_periods ext_ena_n lt 0 wait for 20 clk_period assert reset_n for 3 clk periods reset_n lt Q wait for 3 clk_period deassert reset_n for 10 clk periods reset_n lt 1 wait for 3 clk_period disable clk clk_ena lt false end of simulation wait end process stimuli_process end architecture testbench Listing 5 Some caption 50MHz clock set_location_assignment PIN_AF14 to clk50 External asynchronous inputs Push buttons for external reset and enable keyo set_location_assignment PIN_AA14
14. e HEXO 3 The four inputs of the decoder will be controlled by the toggle switches SW 3 downto 0 4 In order to make sure that the new output ports will be connected to the correct pins you need to add the pin assignment listed in Listing 3 to the pinning tcl file After saving the files run the tcl script Tools gt Tcl Script Again verify the the correct pin assignments have been performed in the pinning assignment editor UiO University of Oslo Seven segment display set_location_assignment PIN_AE26 to HEXO O0 set_location_assignment PIN_AE27 to HEXO 1 set_location_assignment PIN_AE28 to HEXO 2 set_location_assignment PIN_AG27 to HEXO 3 set_location_assignment PIN_AF28 to HEXO 4 set_location_assignment PIN_AG28 to HEXO L5 set_location_assignment PIN_AH28 to HEXO L6 Listing 3 Pin assignments for HEX display Simulating the design l Before downloading the new design to the FPGA we want to verify that the design is working as expected For this purpose we will be using the test bench design shown in Listing 4 Create a new file called tb_labl vhd in the directory vhd_src add the test bench design and save the file Open Modelsim and create a new project File gt New gt Project as shown in Figure 9 When asked to add items to the project choose Add Existing File browse to the vhd_sre directory and add both the labl vhd and tb_labl vhd file as shown in Figures 10 and 11 The fil
15. es have to be compiled in the correct ordert E g tb_labl vhd is dependent on labl vhd labl vhd therefore has to be compiled first To compile right click on the file and choose Compile gt Compile Selected To start the simulation Simulate gt Start Simulation and choose the design unit tb_labl vhd under the work library as shown in Figure 14 Open the wave window if not already opened View gt Wave Add the signals SW HEXO and LEDR to the wave window by marking them in the objects window right click and choose Add Wave as shown in Figure 13 Run the simulation and verify that the design is working as expected by checking that values of HEXO and SW You should see a similar result as shown in Figure hes library ieee use ieee std_logic_1164 all use ieee numeric_std all entity tb_labi is end architecture testbench of tb_labi is signal LEDR std_logic_vector 9 downto 0 signal SW std_logic_vector 9 downto 0 signal HEXO std_logic_vector 6 downto 0 component labi is port LEDR out std_logic_vector 9 downto 0 10 UiO University of Oslo SW in std_logic_vector 9 downto 0 HEXO out std_logic_vector 6 downto 0 end component lab1 begin UUT labl port map LEDR gt LEDR SW gt SW HEXO gt HEXO stimuli_process begin set 1 as the default values for input SW SW 9 downto 0 lt others gt 0 wait for 20 ns Run through all com
16. gn to connect the onboard toggle switches to the onboard LEDs and a 7 segment decoder to show the value of the first 4 toggle swithces on the 7 segment display To verify the correct behaviour of the 7 segment decoder you will simulate the design using a test bench setup which has already been prepared for you For the second part you will implement a 4 bit counter that will be used as input to the 7 segment decoder The counter will be synchronous to the onboard 50 MHz crystal and a push butten will be used to activate the counter A push button will be used to increment the counter To verify the correct behaviour of the 4 bit counter you will again use an already prepared test bench setup 1 Quartus project combinatorial logic and functional simulation 1 1 Switches and LEDs The purpose of this first assignment is to learn how to connect simple input and output devices to an FPGA chip and implement a circuit that uses these devices We will use the switches on the DE1 SoC 1 2 board as inputs to the circuit and we will connect the outputs to the light emitting diodes LEDs The DE1 SoC board provides 10 toggle switches called SW9 0 which can be used as inputs to a circuit and 10 red LEDs called LEDR9 0 that can be used to display output values Listing 1 shows a simple VHDL description where you will need to insert the appropriate statement in order to connect the switches to the LEDs Since there are 10 switches and 10 LEDs it is
17. ls gt Tcl Scripts The tcl script should be visible under the project folder Mark the file and click RUN Verify that the correct assignments have been performed by opening the pin assignment editor Assignments gt Assignment editor You should see a similar SW O SW 1 SW 2 SW 3 SW 4 SW 5 SW 6 SW 7 swWL8 SW 9 LEDR 0 LEDR 1 LEDR 2 LEDR 3 LEDR 4 LEDR 5 LEDR 6 LEDR 7 LEDR 8 LEDR 9 UiO University of Oslo OK 3 3 SW 0 Location PIN_AB12 Yes in SW 1 Location PIN_ACI12 Yes in SW 2 Location PIN_AF9 Yes in SW 3 Location PIN AF10 Yes i SW 4 Location PIN_AD11 Yes in SW 5 Location PIN_AD12 Yes t SW 6 Location PIN AE11 Yes in SWI7 Location PIN ACS Yes in SW 8 Location PIN_AD10 Yes w SWI Location PIN AE12 Yes ou LEDR O Location PIN_V16 Yes ou LEDR 1 Location PIN W116 Yes out LEDR 2 Location PIN V17 Yes ou LEDR 3 Location PIN _V18 Yes 24 LEDR 4 Location PIN_W17 Yes 2t LEDR 5 Location PIN W19 Yes ou LEDR 6 Location PIN _Y19 Yes 24 LEDR 7 Location PIN_W20 Yes 24 LEDR 8 Location PIN_W21 Yes 2t LEDR 9 Location PIN_Y21 Yes Figure 5 Assignment editor view Compile the project and program the FPGA 1 Compile the project Processing gt Start Compilation 2 During compilation of the project you will see some warnings related to missing constraint information sdc file Some pins have incomplete I O assignments e No
18. nstraint will apply 2 2 Edge detector Implement the appropriate logic which is needed to control the incremental stepping of the counter and thereby the value on the 7 segment display The design must be verified by simulation before it is downloaded to the FPGA Provide screenshots of you simulations which clearly demonstrates the functionallity of your solution References 1 DE1 SoC webpage http www terasic com tw cgi bin page archive pl Language EnglishkNo 836 2 DE1 SoC User Manual rev C rev D Board http www terasic com tw cgi bin page archive_download pl Language English amp No 836 amp F ID ae336c1d5103cac0462 9ed1568a8bc3 3 FYS4220 Lecture 2 http www uio no studier emner matnat fys FYS4220 h15 lectures 19
19. pinning tcl Add the new tcl file to the project Project gt Add Remove Files in Project list as shown in Figure 5 Toggle switches set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment LED outputs Red LEDs set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment To avoid that the FPGA Listing 2 Pinning information for LEDs and switches PIN_AB12 PIN_AC12 PIN_AF9 PIN_AF10 PIN_AD11 PIN_AD12 PIN_AE11 PIN_AC9 PIN_AD10 PIN_AE12 PIN_V16 PIN_W16 PIN_V1i7 PIN_V18 PIN_W17 PIN_W19 PIN_Y19 PIN_W20 PIN_W21 PIN_Y21 ts driving an unintended value on pins that are not in use set_global_assignment name RESERVE_ALL_UNUSED_PINS AS INPUT TRI STATED to tO to toO to to tO toO toO toO to toO to to TO to to toO toO to Inside the directory lab1 create a new directory called constraints Open your favourite text editor e g Notepad enter the pinning constraints as shown in Listing 2 Save the file in the directory lab1 constraints and give it Run the tcl script to make the pin assignments Too
20. r Simulation format Leave the other options as illustrated in Figure 3 and press Next b Page 5 of 5 now shows a summary your settings Press Finish to create the project UiO University of Oslo New Project Wizard Directory Name Top Level Entity What is the working directory for this project media psf Home workspace fys4220 lab lab1 quartus What is the name of this project labl What is the name of the top level design entity for this project This name is case sensitive and must exactly match the entity name in the design file C E Use Existing Project Settings Help lt Back Next gt Finish Cancel Figure 1 Provide information about project location and project name New Project Wizard Family amp Device Settings Select the family and device you want to target for compilation You can install additional device support with the Install Devices command on the Tools menu To determine the version of the Quartus II software in which your target device is supported refer to the Device Support List webpage Device family Show in Available devices list Family Cyclone V E GX GT SX SE ST Package Any Devices Cyclone V SE Mainstream Pin count Any Core Speed grade Any Name filter SCSEMA5F31C6 Specific device selected in Available devices list Show advanced devices Target device Available devices Name Core Voltage ALMs Total I Os GPIOs
21. tems to the Project Click on the icon to add items of that type 5 L B Create New File Add Existing File M a Create Simulation Create New Folder Close Figure 10 Choose Add Existing File e00 x Add file to Project File Name mmm Epro eeta 2y31220 1ab 1ab1 oh abi v Browse Add file as type _____y Folder ____ aera vr E Level kd Reference from current location Copy to project directory OK Cancel Figure 11 Add labl vhd and tb_labl vhd from the vhd_src folder 12 UiO University of Oslo oo x Start Simulation Design VHDL Verilog Libraries SDF Others gt tiName s s sSsSCSCCsCdiT per Path work Library work E lab Entity jmn felt u E tb_lab1 Entity jmn felt ul 220model Library MODEL_T 220model_ver Library MODEL_T f altera Library MODEL_T f altera_Insim Library MODEL_T altera_Insim_ver Library MODEL_T mW altera mf l ihrarw MOMEL T hA J al Design Unit s H ___ Resolution Eas z Cancel Cancel Figure 12 Choose the correct design unit to simulate Caneel J y A J 2 sim Default EHAK i nstance Design unit Design unit type T op Category Visibility Total coverage f tb_lab1 tb_lab1 tes Architecture DU Instance acc lt LEDR mi al UUT labl top_le Architecture DU Instance acc lt eo line_23 lab1 top_le Process
22. to reset_n keyl set_location_assignment PIN_AA15 to ext_ena_n Listing 6 Pinning information for clk reset and counter enable signal Timing analysis 1 Compile the full project A In addition to the warnings seen when compiling the first project in this lab assignment you will now also see the warning Timing requirements not met This warning indicates that the design in most cases now has a register to register path that exceeds the clock period However we have not yet specified the actual clock period for our design and a default clock period of 1000 MHz have therefore been set by Quartus as a default value Verify this setting by opening the compilation report and navigate to the Clocks part of the TimeQuest Timing Analyzer Processing gt Compilation Report Ctrl R 16 UiO University of Oslo 3 Timing settings are critically important for a successful design For this tuto rial we will specify the correct clock frequency of 50 MHz by creating a basic Synopsys Design Constraints File sdc that the Quartus I TimeQuest Timing Analyzer will use during design compilation A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints Without it the Compiler will not properly optimize the design To create an SDC perform the following steps Open the TimeQuest Timing Analyzer by choosing Tools gt TimeQuest Timing Analyzer Create the
23. y to the project v IP Settings IP Catalog Search Locations File name Design Templates ig v Operating Settings and Conditic File Name Type Library Design Entry Synthesis Tool Add All Voltage vhd_src labl vhd VHDL File lt None gt Temperature Ren v Compilation Process Settings Incremental Compilation v EDA Tool Settings Design Entry Synthesis Simulation Formal Verification Board Level v Compiler Settings VHDL Input Verilog HDL Input Default Parameters TimeQuest Timing Analyzer Assembler Design Assistant SignalTap II Logic Analyzer Logic Analyzer Interface PowerPlay Power Analyzer Setti SSN Analyzer 4 Press OK to close window 3 Add file 3 Apply change W Buy Software K Cancel Help Figure 4 Instructions for adding new file to project UiO University of Oslo Create tcl scripting file and make pin assignemnts The DE1 SoC board has hardwired connections between its FPGA chip and the switches and LEDs To use SW9 0 and LEDR9 0 it is necessary to include in your Quartus II project the correct pin assignments which are given in the DE1 SoC User Manual 2 For example the manual specifies that SW 0 is connected to the FPGA PIN_AB12 and LEDR 0 is connected to PIN_V16 Each pin can be assigned manually through the Quartus II pin assignment manager however a more elegant approach is to make the pin assignment using a tcl scripting file Create and import pin settings the name
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