INAP375R APIX2 Receiver pdf, 710.4 kB
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1. Semiconductors Datasheet Parameter Description Setup Time for STOP condition tsusto Standard Mode Fast Mode Bus Free Time Standard Mode Fast Mode fall time of SDA and SCL Standard Mode Fast Mode 300 pulse width of spike suppression Standard Mode Fast Mode 50 Table 1 16 PC Interface characteristics a max valid time typ non applicable since device stretches the LOW period 4 ow of the SCL signal b output buffers without slope control for falling edges use series resistors to slow down falling edges if needed c valid for SCL signal no spike suppression on SDA signal 1 3 4 6 RESET and Boot Strap timing taq RESET DOHO BSTx tss gt 1 gt Figure 1 9 Reset and Boot Strap Timing Diagram For a valid Reset Low Time ow all supply voltages needs to be stable the operating condition At reset release rising edge RESET a stable reference clock is required All values specified for 25 Parameter Description laEsLOW Reset Low Time tBsu Boot Strap In Setup Time Boot Strap In Hold Time Table 1 17 Boot Strap Reset Timing DS_INAP375R Revision 1 1_B7 Inova Semiconductors Page 15 of 37 Semiconductors Datasheet 1 3 4 7 GPIO Interface 1 3 4 7 1 GPIO Interface Downstream2. Semiconductors Datasheet Revision 1 1 B7 APIXC2 3GBit s Digital Automotive Pixel Link Receiver The INAP375R together with an APIX2 transmitter offers the next generation high speed digital serial link for DISPLAY and CAMERA applications It provides a DC balanced AC coupled low latency point to point link over shielded twisted pair STP cables Its scalable physical layer provides bandwidth of up to 3 GBit s at lowest EMI The INAP375R supports popular automotive displays with video resolutions such as 1600x600 pixels and refresh rates of up to 100Hz The device offers a flexible video interface configurable to handle 1 or 2 independent video streams with output interfaces such as parallel RGB 1x24 Bit or 2x10 Bit or openLDI LVDS e g 2x 4 lanes clock Software adjustable driver characteristics at the transmitter combined with the powerful adaptive equalizer and configurable operating modes allow the transmission of 3 GBit s at distances of up to 12m over a single pair of wires In addition to the video transmission the INAP375R provides completely indepen dent Full Duplex Communication channels Using the internal AShell protocol data transfers are protected by error detection and retransmission mechanisms Offering a Media Independent Interface MII the INAP375R can be directly connected to an ethernet Media Access Controller offering full network capabilities through the APIX link
3. Semiconductors Datasheet 3 2 2 Signal Mapping aQFN Signal 2 5 Signal Pin pu A9 A10 B2 B3 B7 8 B pa DVDD G2 VDD Signal Pin PX16 C8 AVDD LVDS C9 STATUS C10 GPIOO C11 GND C 12 125 D1 DVDD_XTAL XTAL_IN PX28 010 DVDD PX18 PX17 E1 GND E2 TEST E3 E GPIO1 10 SBDWN_CLK 125 12 XTAL_OUT F1 PX25 F10 PX27 PX22 G1 RESET 125 I28 SDATA VDD XTAL GND XTAL AVDD EN o G12 H1 H2 z H3 PX29 zx o PX30 PX26 AVDD VCO AVDD H11 J1 PX23 PX24 J11 NC J12 NC K1 K2 GND K3 AVDD LVDS PLL K4 PX20 K6 AVDD_LD K7 8 K9 GND E N ND X8 XT L5 ND D 14 16 VD L8 PX13 L10 PX10 L11 PX12 L12 SPI S MB1 DV SBDWN_DATA1 BST6 SCL INBOUND_TS p SD OUTBOUND TS PX9 M5 M6 GND M7 PX6 D NC K5 GN M9 SPI M SDO CLK BST5 GND SPI S SDO BST3 SPI S 0 SBUP_DATAO SPI S CS187 TXD1 SBUP_DATA1 SPI S RXD2 SBDWN DATAO BST M10 Table 3 3 Signal Mapping List aQFN TXD3 DVDD PX15 PX5 PX2 AVDD_LVDS SPI_M_SDI TX SPI_M_CS1 SPI_M_CS2 SPI S SCK DVDD SPI 2 SPI_S_RW TXD2 PX4 RXD1
4. MIL TXD 3 0 j Figure 1 12 MII NIBBLE Interface Timing Diagram Receive Parameter Description fuil Clock Frequency f Clock Frequency 100 tsETUP Setup Time Hold Time toutv Data Output Valid Table 1 23 MII NIBBLE Interface Timings DS_INAP375R Revision 1 1_B7 Inova Semiconductors Page 20 of 37 Semiconductors Datasheet 1 3 5 Reference Clock The INAP375R requires an external clock source like a crystal or oscillator acting as reference for the internal PLL Parameter Description fref_osc Nominal Reference Frequency Fro Frequency Tolerance ESRxTAL Equivalent Series Resistance Drive Level see Table 1 25 Table 1 24 Reference clock requirements The INAP375R core clock frequency is generated by an internal PLL controlled by an external 10 MHz crystal Alternatively a stable 10 MHz clock signal 3 3 CMOS can be directly connected to XTAL_IN with XTAL_OUT left open Figure 1 13 shows a typical crystal design required for the oscillator circuit The values for C1 C2 and R1 need to be selected to match the oscillation requirements of the crystal Q1 Q1 C1 XTAL IN 54 z XTAL_OUT I 2 Figure 1 13 Crystal clock schematic example For resonance at the correct frequency the crystal needs to be loaded with its specified load
5. Semiconductors APIXC2 Datasheet Signal Name Type Description SPI S SPI S MBO SPI Slave mailbox 0 output RXD2 RXD2 Receive Data Output 2 SBDWN DATAO SBDWN DATAO APIX1 Downstream data output 0 BST1 BST1 Boot strap option 1 input SPI S MB1 SPI S MB1 SPI slave mailbox 1 output RX DV DV MII Receive Data Valid output SBDWN 1 SBDWN APIX1 Downstream data output 1 BST6 BST6 Boot strap option 6 input TXD3 TXD3 MII Transmit Data Input I2C_SCL I2C SCL Clock output INBOUND_TS INBOUND_TS Inbound Nibble Data Target select output I2C_SD 2 SD Data pin OUTBOUND TS OUTBOUND TS Outbound Nibble Data Target select input SD UP IN P 18 Serial Link Upstream Serial Link Input from 2nd RX SD_UP_IN_N Serial Link Upstream Serial Link Input from 2nd RX SD_DWN_OUT_N Serial Link Downstream Serial Link output to 279 RX SD DWN OUT P Serial Link Downstream Serial Link output to 279 RX SD DWN IN P Serial Link Downstream Serial Link input from TX SD DWN IN P Serial Link Downstream Serial Link input from TX SD UP OUT N Serial Link Upstream Serial Link output to SD UP OUT P Serial Link Upstream Serial Link output to XTAL_IN 10MHz Oscillator input XTAL_OUT O 10MHz Oscillator output 125 O 25 Interface Fra
6. DS_INAP375R Revision 1 1_B7 Inova Semiconductors Page 10 of 37 zlinova Semiconductors Datasheet 1 3 4 3 SPI Master Interface timing l CSH SPI_M_CS0 1 4 testo CPOL 1 SPI M SCK lt 4 loc t CPOL 0 SPI_M_SCK lt 77 hoa J 7 7 bo SPI M SDO MSB OUT Bite OUT Y LSB OUT CPHA 0 Figure 1 5 SPI Master Timing Diagram CPHA 0 t 4 CSH SPI_M_CSO 1 lt loss testo CPOL 1 SPI M SCK tog th ur CPOL 0 SP M SCK on tsek t lespov T lt lou SPI M SDO MSB OUT Bit OUT LSB OUT 1 Figure 1 6 SPI Master Timing Diagram CPHA 1 The SPI Master interface can be flexible configured with the parameters cfg spi m cpol cfg spi m cpha cfg spi m clock div cfg spi m cs delay and cfg byte cnt For further informations please refer to the INAP375R user manual Core clock frequency for APIX1 Mode 125MHz and for APIX2 Mode 187 5MHz All values specified for 25 APIX1 mode APIX2 mode Parameter Description Min Max Min Max fsck SCK Clock Frequency 0 007 0 011 tki SCK High Time 18 12 tsckL SCK Low Time 22 16 Table 1 14 SPI Master Interface characteristics DS_INAP375R Revision 1 1_B7 In
7. zlinova Semiconductors Datasheet 1 1 Absolute Maximum Ratings The absolute maximum ratings define values beyond which damage to the device may occur Exposure to absolute maximum rating conditions for extended periods may affect device reliability The functional operation of the device at these or any other conditions beyond the recommended operating ratings is not guaranteed Parameter Description _ DC Supply Voltage VAVDD LVDS Input Voltage XTAL Current D DC or transient any pin Ts Storage Temperature tg Soldering Temperature 40 seconds maximum ESD Protection HBM JEDEC JESD22 A114 Rp 1 5kO Cs 100pF AEC Q100 002 ESD Protection CDM EIA JEDEC JESD22 C101 AEC Q100 003 ESD Protection MM EIA JEDEC JESD22 A115A AEC Q100 011 Table 1 1 Absolute maximum ratings DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 3 of 37 Semiconductors Datasheet 1 2 Recommended Operating Conditions Parameter Description xTAL Digital Core supply Oscillator supply Digital IO Supply VDvpD_XTAL Digital Oscillator supply VAVDD VAVDD VCO CML PHY supply voltage VCO supply VAVDD_LVDS LVDS PLL amp Core supply VAVDD LVDS VsuPPLY NOISE Analog and Digital Supp
8. I2C SD OUTBOUND TS are open drain outputs and require external pull up circuitry All values specified for 25 Parameter Description Test Condition Input High Voltage Input Low Voltage Pull Down Current Vin Vpypp Input High Current Vin Vpypp Input Low Current Vin 0V Output High Voltage 3mA Figure 1 15 Output Low Voltage IOL 3mA Figure 1 15 Output Rise Time b C 5pF Output Fall Time P lt Table 1 11 General IO Characteristics a pins with internal pull down to GND b not relevant for open drain outputs DS_INAP375R Revision 1 1 7 Inova Semiconductors Page 8 of 37 al inova APIX2 Semiconductors Datasheet 1 3 4 2 SPI Slave Interface timing Usa SPI S 50 1 2 4 lt testo CPOL 1 SPI S SCK lt sca ic C CPOL 0 SPI S SCK lt 7 brow DISU tomo SPI S SDI MSB IN Bit 6 IN WAN LSB IN t 42 e tov 4 9 toro 5 bonis SPI 00 MSB OUT Bit6 OUT Y LSB OUT CPHA 0 Figure 1 3 SPI Slave Timing Diagram CPHA 0 gt SPI_S_CS0 1 2 pe 2 t CPOL 1 SPI S SCK a to CPOL 0 SPI S SCK loa 7 ER SPI 8 SDI MSB IN Bit 6 IN YS LSB IN zm t
9. The GPIO interface is only available in APIX2 mode Receiver GPIO downstream interface outputs GPIO data coming from a connected APIX2 transmitter device Maximum output frequency can be configured using pa rameters GPIO Bandwidth gpio bw dwn and GPIO halved gpio_bw_div For further information please re fer to the INAP375R user manual All values specified for 25 Downstream GPIO GPIO Maximum Output Bandwidth Bandwidth halved Frequency 3 GBit s high off 13 260 3 GBit s low off 3 340 3 GBit s high on 6 660 3 GBit s low on 1 670 3 GBit s high off 6 660 3 GBit s low off 1 670 3 GBit s high on 3 330 3 GBit s low on unsupported 1 GBit s high off 8 450 1 GBit s low off 2 220 1 GBit s high on 4 450 1 GBit s low on 1 110 1 GBit s high off 4 440 1 GBit s low off 1 110 1 GBit s high on 2 220 1 GBit s low on 0 550 500 MBit s high off 8 450 500 MBit s low off 1 110 500 MBit s high on 4 450 500 MBit s low on 1 110 500 MBit s high off 4 440 500 MBit s low off 1 110 500 MBit s high on 2 220 500 MBit s low on 0 550 Table 1 18 GPIO Interface Downstream DS_INAP375R Revision 1 1_B7 Inova Semiconductors Page 16 of 37 Semiconductors Datasheet 1 3 4 7 2 GPIO interface upstream At receiver side GPIO data upstream input ports are sampled asynchronously and tr
10. within the limits as specified in Table 1 26 All 1 8V supplies have to be ramped up simultaneously starting from GND according Figure 1 14 Reset has to be held low until all supplies reached recommended operating con ditions NE i steady rise GND Figure 1 14 Steady Voltage Ramp Up Parameter Description tramp Supply Ramp Up Time for all supplies GND to min Table 1 26 Power Supply Ramp Up Time DS_INAP375R Revision 1 1_B7 Inova Semiconductors Page 22 of 37 APX Semiconductors Datasheet 1 4 Typical Operating Characteristics Output driver in low state Output driver in high state 25 0 0 1 2 3 20 5 lt 15 lt E 8 5 15 0 0 1 2 3 20 voltage V voltage V Figure 1 15 typical general IO characteristics DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 23 of 37 aAinova Semiconductors Datasheet APIXC2 2 0 Pin Description Signal Name Type Description PX 30 1 O Video Interface pin SPI M SDO SPI M SDO SPI Master Data Output CLK Interface Clock Output BST5 BST5 Boot strap option 5 input SPI M SDI SPI SDI SPI Master Data Input TX EN TX EN MII Transmit Enable Input SPI M SCK SPI M SCK SPI Master Serial Clock Output RXD1 1 Receive Data Output 1 BST2 BST2 Boot strap opt
11. Additionally the link is optimized to carry low latency GPIO signals for reset or synchronization purposes The inbuilt audio path allows synchronous transmission of up to 4 stereo audio channels with highly precise clock regenera tion at the receiver for high end rear seat entertainment applications Applications Central Information Displays Round View Camera Systems Head up Displays Cluster Displays Rear Seat Entertainment Systems Stereo Camera Systems Rear View Camera Systems Sensor Fusion Systems Automotive Driver Assistance Surveillance Systems Inspection Systems INAP375R INAP375RAQ Features Backwards compatibility with APIX1 500 MBit s 1 GBit s and 3 GBit s sustained downstream link bandwidth for video data rates up to 2591 MBit s up to 187 5 MBit s upstream link bandwidth Supports 2 independent video streams Configurable video interface Parallel RGB 10 12 18 or 24 Bit openLDI compliant LVDS interfacel Single Pixel Format 18 or 24 Bit Dual Pixel Format 18 or 24 Bit Parallel Bulk Data Mode 10 12 18 24 Bit Video resolutions up to HD resolutions Configurable full duplex communication channel Daisy chain output to a 2nd receiver Media Independent Interface SPI data interfaces 2 Master interface GPIOs for direct signalling and camera synchronization support Embedded AShell 25 Audio interface supports 16 24 32 Bit word length supports up to 192kHz sampling TDM su
12. BST2 SPI M 50 RXDO VDD SPI S SDI SPI STALL MII COL BST4 Video Interface Data Interface L DS_INAP375R Revision 1 1_B7 Inova Semiconductors Page 33 of 37 aAinova Semiconductors Datasheet APIXX2 Supply Name B8 G2 H11 M8 Supply Name GND A8 B5 C3 C12 E12 G1 G3 G12 H10 K3 K5 K7 M11 B2 C5 L1 L10 M4 AVDD VCO D10 C11 D11 VDD XTAL C9 AVDD LVDS 5 L5 DVDD XTAL A10 AVDD LVDS PLL F1 XTAL GND Table 3 4 Supply Pins aQFN C10 DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 34 of 37 al inova APX Semiconductors Datasheet 3 2 3 Package Dimensions aQFN b mc lt t 2 a lt lt lt lt lt lt 02 g ul 2 gt lt gt gt E t Uu Ee 5 25 ag E BH gt lt e E Zz P _ B u 5 VIEW 4 Figure 3 4 Package Drawing 104 pin aQFN DS_INAP375R Re
13. Interface DS_INAP375R Revision 1 1_B7 Inova Semiconductors Page 29 of 37 Semiconductors Datasheet Supply Name Supply Name 8 16 25 34 38 42 46 60 68 76 88 90 100 7 24 69 77 99 AVDD_VCO 47 45 48 VDD_XTAL 54 AVDD_LVDS 9 67 DVDD_XTAL 55 AVDD_LVDS_PLL 87 GND_XTAL 51 Table 3 2 Supply Pins LQFP 17 35 59 89 GND DS_INAP375R Revision 1 1 7 Inova Semiconductors Page 30 of 37 APX Datasheet imensions LQFP Semiconductors 3 1 3 Package D 1 02 31v9S 1 001 31 25 3 9 9 NOILO3S z n 1 4 PpP e e F 1 3SV 3015 3 1 130 401 MJA WOLLOS M3NMOO Page 31 of 37 Package Drawing 100 pin LOFP Inova Semiconductors Figure 3 2 DS INAP375R Revision 1 1 B7 al inova APDC2 Semiconductors Datasheet 3 2 104 Pin aQFN Package 3 2 1 Pinout Diagram aQFN G9 4 09 2 8 G9 69 amp INAP375RAQ 104 pad aQFN 3 9 9 9 9 9 69 6 3 9 9 9 2 9 9 9 2 COCOON Figure 3 3 Pinout diagram 104 pin aQFN Exposed PAD connect to GND plane DS_INAP375R Revision 1 1_B7 Inova Semiconductors Page 32 of 37
14. lt t lt bov gt tons SPI S SDO MSB OUT Bit OUT LSB OUT I CPHA 1 Figure 1 4 SPI Slave Timing Diagram CPHA 1 SPI Slave interface can be flexible configured with the parameters cfg spi s cpol cfg spi s cpha For further informations please refer to the INAP375R user manual DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 9 of 37 Semiconductors Datasheet Core clock frequency for APIX1 Mode 125MHz and for APIX2 Mode 187 5MHz All values specified for TA725 C APIX1 Mode APIX2 Mode Parameter Description Min Max Min Max fsck SCK Clock Frequency 11 15 sexi SCK High Time tsckL SCK Low Time CS High Time tess CS Setup Time tcsHo CS Hold Time tpisu Data In Setup Time tpiHo Data in Hold Time tpov Data Output Valid Time Data Output Hold Time tpopis Data Output Disable Time ta Data Access Time Table 1 12 SPI Slave Interface characteristics Read Access APIX1 Mode APIX2 Mode Parameter Description Min Max Min Max fsck SCK Clock Frequency 31 41 lack SCK High Time tsckL SCK Low Time fcn CS High Time tess CS Setup Time tcsHo CS Hold Time tpisu Data In Setup Time tpiHo Data In Hold Time Table 1 13 SPI Slave Interface characteristics Write Only Access
15. R Revision 1 1_B7 Inova Semiconductors Page 28 of 37 Semiconductors Datasheet APIX2 3 1 2 Signal Mapping LQFP vos 30 SPI M SDO 11 CLK BST5 m SPI M SDI TX EN SPI M 5 13 RXD1 BST2 508 MIl_RXDO SPI_M_CS1 VDD SPI_M_CS2 SPI S SDO BST3 SPI 5 SDI 1 SPI 5 STALL COL BST4 5 5 508 7 MIl_TXDO SBUP_DATAO 4 DVDD CS1 MII_TXD1 7 2 SBUP DATA1 2 5 17 20 21 22 23 2 GND 45 46 47 Wami pu E 20 sess 4 23 sese 4 s SPI_S_RW TXD2 SPI S 0 RXD2 SBDWN BST SPI S 1 DV SBDWN_DATA1 BST6 TXD3 2 SCL7 INBOUND TS 2 SD OUTBOUND TS GND VDD AVDD LD GND AVDD GND AVDD VCO AVDD 55 58 59 60 61 62 65 67 68 69 73 4 75 DVDD_XTAL 8 128 8 128 84 125 SDATA 85 VDD 8 125 88 8 GPIOO 90 STATUS TEST RESET 9 9 9 9 9 9 D GPIO1 SBDWN_CLK D DVDD 6 PX16 PX17 98 PX21 99 PX22 100 PX18 PX19 GND DVDD 2 3 6 7 9 1 2 3 5 7 XTAL_OUT VDD_XTAL PX26 PX25 Table 3 1 Signal Mapping List LQFP PX24 PX23 PX20 AVDD_LVDS_PLL lt O z 2 Video Interface Data
16. V Table 1 8 RGB characteristics PERIOD PX1 PX30 rising edge PX1 PX30 falling edge PX2 PX29 Figure 1 2 RGB Interface Timing The active edge of pixel clock can be set to rising or falling For further information please refer to the INAP375R user manual fpixeL_cLocx is the reciprocal of tpeRiop All values specified for 25 Parameter Description Test Condition feixEL cLock Pixel Clock Output Frequency Skew Pixel Clock Active Edge To Pixel tskew Data Table 1 9 RGB Interface timing DS_INAP375R Revision 1 1_B7 Inova Semiconductors Page 6 of 37 Semiconductors Datasheet 1 3 3 2 LVDS Interface OpenLDI interface with outputs according to LVDS specification Exceptions are listed at table 1 10 Parameter Description Differential Output Voltage Offset Voltage Change to Change to Vogl Short Circuit Current Receiver Threshold Voltage fivbs LVDS Clock Frequency Table 1 10 LVDS interface exceptions to TIA EIA644 specification DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 7 of 37 zlinova Semiconductors Datasheet 1 3 4 Data Interface 1 3 4 1 General Characteristics The following characteristics are valid for SP SBDOWN SBUP GPIO 25 MII Nibble data and 12 function ality The pins 2 SCL INBOUND TS
17. ail info inova semiconductors de URL _http Awww inova semiconductors de Ari xX is a registered trademark of Inova Semiconductors GmbH All other trademarks or registered trademarks are the property of their respective holders Inova Semiconductors GmbH does not assume any liability arising out of the applications or use of the product described herein nor does it convey any license under its patents copyright rights or any rights of others Inova Semiconductors products are not designed intended or authorized for use as components in systems to support or sustain life or for any other application in which the failure of the product could create a situation where personal injury or death may occur The infor mation contained in this document is believed to be current and accurate as of the publication date Inova Semiconductors GmbH reserves the right to make changes at any time in order to improve reliability function or performance to supply the best product possible Inova Semiconductors GmbH assumes no obligation to correct any errors contained herein or to advise any user of this text of any cor rection if such be made Inova Semiconductors 2015 DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 37 of 37
18. ansmitted to configurable GPIO output ports at transmitter side Transmitter GPIO upstream interface outputs GPIO data coming from either one or two APIX2 receiver devices For further informations please refer to the INAP375R user manual All values specified for T4225 C Number of Upstream GPIO Rx Bandwidth GPIO Ports Bandwidth Sampling Frequency 187 5 MBit s high 13 39 187 5 MBit s low 3 35 187 5 MBit s high 13 39 187 5 MBit s low 3 35 62 5 MBit s high 4 46 62 5 MBit s low 62 5 MBit s high 62 5 MBit s low 187 5 MBit s high 187 5 MBit s low 187 5 MBit s high 187 5 MBit s low 62 5 MBit s high 62 5 MBit s low 62 5 MBit s high NI NI NM NM N 62 5 MBit s low Table 1 19 GPIO Interface Upstream DS_INAP375R Revision 1 1_B7 Inova Semiconductors Page 17 of 37 zlinova Semiconductors Datasheet 1 3 4 8 Sideband Interface 1 3 4 8 1 Sideband Interface Downstream The Sideband interface is only available in APIX1 mode Receiver Sideband interface downstream outputs sideband data coming from transmitter side All values specified for T4225 C Downstream Bandwidth Maximum Output Frequency 1 GBit s 13 89 500 MBit 6 94 Table 1 20 Sideband Interface Downstream 1 3 4 8 2 Sideband Interface Upstream At receiver side upstream sideband data input ports are sampled asynch
19. capacitance which is the value of capacitance used in conjunction with the oscillation unit The INAP375R oscillator provides some of the load with internal capacitance which is specified within the range of 10pF to 12 5pF The remainder is generated by the external capacitors and tuning capacitors labeled C1 and C2 The load capacitance C be calculated from C Cint C1 C2 E g selecting C1 and C2 with 15pF can be calculated to C 12 5pF 7 5pF 20pF DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 21 of 37 zlinova Semiconductors Datasheet The crystal needs to be able to withstand the power dissipation produced by the INAP375R The power dissi pation depends on the ESR of the crystal and is reflected by the maximum drive level of the crystal Table 1 25 illustrates the power dissipation of the INAP375R and therefore the minimum drive level capabilities of the crys tal at different crystal ESR levels INAP375R Power dissipation Minimum crystal drive level Crystal ESR 30 77 50 80 Table 1 25 Minimum Drive level 1 3 6 Power Up Sequencing To avoid high IO currents 1 8V supply voltages have to ramp before 3 3V supply on power up On pow er down 3 3V supply have to be powered down before 1 8V On power up all supply voltages have to rise steadily from GND level up to the level without turn to negative direction The ramping times must be
20. ion V Upstream differential output voltage Table 1 5 Upstream output interface characteristics SD UP OUT P SD UP OUT N The optional upstream input interface expects serial data coming from a second connected APIX2 receiver Parameter Description in Max Differential Input in Voltage Range 800 V Serial input common Vaypp 0 5V 0 5 mode range 1 2 1 2 Table 1 6 Upstream input interface characteristics SD UP IN P SD UP IN 1 3 2 Supply Current Parameter Description Digital Core amp Oscillator Supply lvpp xraL Current Digital IO amp Oscillator Supply IpvDD_XTAL Current lavop_tvps LVDS Core amp PLL Supply Current laVDD LVDS CML PHY Supply Current lavDD VCO VCO Supply Current Table 1 7 Supply current DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 5 of 37 zlinova Semiconductors Datasheet 1 3 3 Pixel Interface INAP375R s pixel interface can be configured to RGB or and openLDI LVDS outputs For further infor mations please refer to the INAP375R user manual 1 3 3 1 RGB Interface Parameter Description Test Condition Min Max Units Vou Output High Voltage 4mA 24 V VoL Output Low Voltage IOL 4mA 0 4
21. ion 2 input SPI 50 SPI_M_CS0 SPI Master Chip select 0 Output Data Channel 0 RXDO RXDO MII Receive Data Output 0 SPI M 51 SPI_M_CS1 SPI Master Chip select 1 Output Data Channel 1 MII Receive Data Output SPI M 52 O SPI_M_CS2 SPI Master Chip select 2 Output Configuration SPI_S_SDO SPI S SDO SPI Slave Data Output BST3 BST3 Boot strap option 3 input SPI S SDI 18 SPI Slave Data Input SPI S 18 SPI Slave Serial Clock Input SPI S STALL High SPI Slave not ready or buffer full SPI S STALL Low SPI Slave ready to receive data STALL STALL High Nibble IF not ready or buffer full BST4 Low Nibble IF ready to receive data MII COL MII Collision Detect output BST4 Boot strap option 4 input SPI S 50 SPI S 50 SPI Slave Chip select 0 Input Data channel 0 TXDO TXDO MII Transmit Data Input 0 SBUP_DATAO SBUP_DATAO APIX1 Upstream data input 0 SPI S CS1 SPI 5 50 SPI Slave Chip select 1 input Data channel 1 TXD1 TXD1 Transmit Data input 1 SBUP DATA1 SBUP APIX1 Upstream data input 1 SPI S 52 SPI Slave Chip select 2 input Configuration SPI S RW SPI_S_RW SPI Slave Read Write input only used in single SPI mode MII TXD2 TXD2 Transmit Data Input 2 Table 2 1 Pin description DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 24 of 37
22. ly Noise Ambient Temperature aQFN Ta Ambient Temperature LQFP Table 1 2 Recommended operating conditions 1 3 Electrical Characteristics 1 3 1 Serial Interface 1 3 1 1 Downstream interfaces The INAP375R offers two serial interfaces in downstream direction The downstream input interface expects serial data coming from an APIX transmitter device Parameter Description Min Differential input 60 9 500 voltage range V Serial input common mode Vaypp 0 5V Vavpp 0 5 cmm_SDIN range i 2 i 2 Jacceptance Random Jitter acceptance 27 5 Table 1 3 Downstream input interface characteristics SD DWN IN P SD DWN Min value at 0 3 0 7 UI The optional downstream output interface acts as transmitter output to a second connected APIX2 Rx device Specified with a load of 500 Parameter Description Downstream differential output Vout nom dwn voltage Table 1 4 Downstream output interface characteristics SD DWN OUT P SD DWN OUT N DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 4 of 37 Semiconductors Datasheet 1 3 1 2 Upstream interfaces The INAP375R offers two serial interfaces in upstream direction The upstream output interface transmits serial data to a connected APIX transmitter device Specified with a load of 500 Parameter Descript
23. me clock output 125 O 25 Interface Bit clock output I2S_SDATA 29 Interface Data output 125 O 25 Interface Master Clock output GPIO1 General purpose I O GPIO1 SBDWN_CLK a Sampling clock output for SBDWN DATA 1 0 APIX1 DEBUG Interface Debug Output Pin1 ee 1 0 STATUS O STATUS Device status output Table 2 1 Pin description DS_INAP375R Revision 1 1_B7 Inova Semiconductors Page 25 of 37 Semiconductors 8 Datasheet Ari xX 2 Signal Name Description RESET Reset AVDD_LD Common Mode voltage connect to decoupling capacitor DVDD Digital I O power supply AVDD LVDS PLL LVDS PLL power supply VDD Core supply AVDD LVDS LVDS power supply AVDD Serial Link core power supply AVDD VCO Serial Link VCO Power supply VDD XTAL 10MHz Oscillator core supply DVDD XTAL 10MHz Oscillator digital supply GND XTAL 10MHz Oscillator Ground GND Ground Exposed PAD EP must be connected to GND plane TEST a with internal pull down b n channel open drain c CML interface d schmitt trigger input 2 1 Reset reserved pull down external over 100kO to GND Table 2 1 Pin description The pin RESET triggers an asynchronous reset active low and can be activated any time This reset erases all configuration settings Please see Table 2 2 for the
24. meter Description Min Max Min Max fsck SCK Clock Frequency 0 98 1 46 SCK High Time 512 341 scit SCK Low Time 512 341 tess CS Setup Time tcsuo CS Hold Time tpisu Data In Setup Time tpiHo Data In Hold Time tpov Data Output Valid Time Table 1 15 SPI Master EEPROM Interface characteristics DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 13 of 37 aAinova Semiconductors Datasheet 1 3 4 5 Interface timing 2 SDA 2 SCL The timings depend on the accuracy of the external 10 2 reference clock and are therefore listed as typ tsupar tupsrx le 4 HIGH ul SUSTA t F Figure 1 8 Timing Diagram ical values All values specified for 25 Parameter Description SCL Clock Frequency Standard Mode Fast Mode SCL High Time Standard Mode Fast Mode ti ow SCL Low Time Standard Mode Fast Mode lupsTA Hold Time repeated START condition Standard Mode Fast Mode t a HDDAT Data Hold Time Standard Mode Fast Mode tsupat Data Setup Time Standard Mode Fast Mode tsusTa Setup Time for repeated START condition Standard Mode Fast Mode Table 1 16 Interface characteristics DS_INAP375R Revision 1 1_B7 Inova Semiconductors
25. ova Semiconductors Page 11 of 37 Semiconductors Datasheet APIX1 mode APIX2 mode Parameter Description Min Max Min Max CS High Time 8 6 tesa CS Setup Time configurable 85 tcsHo CS Hold Time 30 tpov Data Output Valid Time tpouo Data Output Hold Time 5 tespov CS To Data Valid Time Table 1 14 SPI Master Interface characteristics a can be configured from core clock 16384 to core clock 8 by cfg_spi_m_clock_div b can be configured from 16 to 48 core clock cycles by cfg_spi_m_cs_delay and depends on CPOL CPHA DS_INAP375R Revision 1 1 7 Inova Semiconductors Page 12 of 37 zlinova Semiconductors Datasheet 1 3 4 4 SPI EEPROM Master Interface timing SPI_M_CS2 N ties gt lt testo SPI_M_SCK SPI M SDO SPI M SDI t X 1 006 Figure 1 7 SPI EEPROM Master Timing Diagram The SPI Master timings depend on the accuracy of the external 10MHz reference clock and are therefore listed as typical values For the EEPROM Master Timing the internal parameters are used CPOL 0 CPHA 0 tess delay 48 wait core cycles and divider core clock 128 Core clock frequency for APIX1 Mode 125MHz and for APIX2 Mode 187 5MHz All values specified for 25 APIX1 mode APIX2 mode Para
26. pport for up to 8 channels Diagnostic Features Built In PRBS Checker Embedded diagnostics Up to 12m distance at 3 GBit s Package 100 pin LOFP 104 pin aQFN Temperature Quality LQFP 40 C to 105 C aQFN 40 C to 85 C AEC Q100 DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 1 of 37 aAinova Semiconductors Datasheet 1 0 Characteristics Integrity support o Algo 24vps N Y ae Pixel clock synth E 3 Video video D AGC Deframer Input CML gt gt a DFE Deserializer FIFO APIX Pixel clock synth Downstream di 7 gt Audio 12S Audio Output lt lt lt clock synth Als GPIOs Ha gt GPIO lt N gt Dc I2C Dev pc E ini Serializer EEPROM APIX AShell MII Upstream Nibble Ethemet Z lt pata NS 2 Deframer b LH Input CML Deserializer M P E e gt EEPROM Configuration 5 Data VCO Osc Reset Control statis SPIS MCCC Configuration 10MHz Reset Figure 1 1 INAP375R Block Diagram DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 2 of 37
27. ronously and transmitted to the cor responding output ports at transmitter side All values specified for 25 Upstream Bandwidth Sampling Frequency 62 5 MBit s 10 41 31 25 MBit s 5 21 Table 1 21 Sideband Interface Upstream DS_INAP375R Revision 1 1_B7 Inova Semiconductors Page 18 of 37 APX Semiconductors Datasheet 1 3 4 9 125 Audio Interface 1 tpERIOD BCK duty cycle D tPERIOD 10096 All values specified for 25 PERIOD t HIGH bow 125 25 FRCK gt a t I2S_SDATA X X m Figure 1 10 25 Audio Interface Timing Diagram Parameter Description feck 25 BCK frequency 25 MCLK frequency tuicu ti ow 25 BCK Duty Cycle t Skew between 25 BCK SKEW FRCK and 125 FRCK Skew between 125 ISKEW SDATA and 125 Data Table 1 22 125 Audio Interface Timing DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 19 of 37 zlinova Semiconductors Datasheet 1 3 4 10 MII NIBBLE Interface Timings CLK 1 tPERIOD All values specified for 25 lt t gt PERIOD tuw N DV MIFCOL Figure 1 11 MII NIBBLE Interface Timing Diagram Transmit terion gt 2 2
28. status of all pins during reset Signal Name Reset State Functional State PX 30 1 Tri State Output SPI M 800 CLK BST5 Input Output SPI M SDI TX EN Input Input SPI M SCK MII RXD1 BST2 Input Output SPI M CSO RXDO Output Output SPI M CS1 RXD3 Output Output SPI CS2 Output Output Table 2 2 Reset States DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 26 of 37 APD Semiconductors Datasheet Signal Name Reset State Functional State SPI S SDO BST3 Input Output SPI S SDI Input Input SPI S SCK Input Input SPI S STALL MII COL BST4 Input Output SPI S CSOZ MII SBDWN DATAO Input Input SPI_S_CS1 TXD1 SBDWN DATA1 Input Input SPI S CS2 Input Input SPI S RW MII TXD2 Input Input SPI S RXD2 SBUP DATAO BST1 Input Output SPI S MB1 MII DV SBUP DATA1 BST6 Input Output MII TXD3 Input Input 2 SCL INBOUND TS Tri State Tri State Output 2 SD OUTBOUND TS Tri State Tri State Input Output 125 FRCK Output Output 125 Output Output I2S_SDATA Output Output 125 MCLK Tri State Tri State Output GPIO1 SBDWN_CLK Input Input Output GPIOO SBUP_CLK Input Input Output STATUS Output Output Table 2 2 Reset States DS_INAP375R Revision 1 1_B7 Ino
29. va Semiconductors Page 27 of 37 aAinova APIX2 Semiconductors Datasheet 3 0 Package Information 3 1 100 Pin LQFP Package 3 1 1 Pinout Diagram LQFP x 9 o a Oy lt a 5 Soren oo Qu POS jj lt lt 8 DOONOSNNN ASKS 75 51 GND 76 so SD UP OUT P DVDD SD UP OUT N PX28 AVDD PX27 AVDD PX26 GND PX25 AVDD PX30 SD DWN IN N PX29 SD DWN IN P PX24 GND PX23 AVDD LD PX20 SD DWN OUT P AVDD LVDS INAP375R SD DWN OUT N GND GND VDD 4 100 pin LQFP SD UP IN GND SD UP IN P PX8 4 VDD PX7 GND PX14 12 SD OUTBOUND TS PX13 12 SCL INBOUND TS PX10 TXD3 PX9 4 SPI 5 MB1 MII DV SB DWN DATA1 BST6 PX12 SPI S RXD2 SBDWN DATAO BST1 PX11 SPI 5 RW MII TXD2 DVDD SPI 5 CS2 GND 100 2 SPI CS14 MII TXD1 SBUP DATA1 1 25 l T TT p p T T T T T TT T T TIT T Eo bob Loco 10 Qo cO N N Q O N O o lt fo r QO Lxxxxxnzaxce tctaa azasecocort n ELT DEELER XF a 9 od gt gt zl 2 See 58270692 za zo m 9 z9o 82850 38 23977 z v I San oz 5 N N 77 o Figure 3 1 Pinout diagram 100 pin LQFP Exposed PAD connect to GND plane DS_INAP375
30. vision 1 1_B7 Inova Semiconductors Page 35 of 37 aAinova Semiconductors APIDXC2 Datasheet 4 0 Ordering Information Device RoHS Minimum Order Ordering Code Package compliant Quality Temperature Range Quantity INAP375R T LQFP100 yes AEC Q100 40 C to 105 C 90 pcs tray INAP375R R1 LQFP100 yes AEC Q100 40 C to 105 C 1000 pcs reel INAP375RAQ T aQFN104 yes AEC Q100 40 C to 85 C 260 pcs tray INAP375RAQ R2 aQFN104 AEC Q100 40 C to 85 C yes 2000 pcs reel Table 4 1 Ordering Information 5 0 Bibliography 1 OpenLDI Specification National Semiconductors Rev 0 95 13 of May 1999 2 ANSI TIA EIA 644 1995 Electrical Characteristics of Low Voltage Differential Signaling LVDS In terface Circuits November 1995 3 INAP375R User Manual 6 0 Revision History Revision Date Changes 1 0 Nov 2014 release version 1 0 1 1 May 2015 Added description for INAP375RAQ Added package information for aQFN Updated LQFP Package Drawing Table 6 1 Revision History DS INAP375R Revision 1 1 B7 Inova Semiconductors Page 36 of 37 al inova APIDC2 Semiconductors Datasheet Inova Semiconductors GmbH Grafinger Str 26 D 81671 Munich Germany Phone 49 0 89 45 74 75 60 Fax 49 0 89 45 74 75 88 Em
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