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MN101C115/117 LSI User`s Manual

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1. Example The timer 3 clock source is 15 4 fosc 8MHz and a baud rate of 300 bps is desired Since fs fosc 2 compare register set value 8 x 109 2 4 300 x 2x 8 1 207 Half duplex UART Serial Interface 105 Chapter 5 Serial Functions 106 Serial Interface Control Registers 5 4 Serial Interface Control Registers 5 4 1 Overview 7 registers control the serial interface See table 5 4 1 Table 5 4 1 Serial Interface Registers Name Address R W Function SCOMDO X 03F50 Serial interface 0 mode register 0 SCOMDI X 03F51 R W Serial interface 0 mode register 1 SCOMD2 X 03F52 Serial interface 0 mode register 2 SCOMD3 X 03F53 Serial interface 0 mode register 3 SCOCTR X 03F54 R W Serial interface 0 control register SCOTRB X 03F55 W Serial interface 0 transmit receive shift register SCORXB 03 56 R Serial interface 0 receive data buffer Chapter 5 Serial Functions 5 4 2 Transmit Receive Shift Registers Receive Data Buffer 1 Serial interface 0 transmit receive shift register SCOTRB This 8 bit writable register shifts the transmission data and the reception data The direction of transfer can be specified as LSB first or MSB first 7 6 5 4 3 2 1 0 SCOTRB SCOTRB7 SCOTRB6 SCOTRB5 SCOTRB4 SCOT
2. 1 Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the count operation of timer 2 2 Set bit 2 of the port 1 output input mode register to the special function pin setting Bit 2 of port 1 will be specified as the PWM output pin 3 Set the TM2CK2 to 0 flags of the TM2MD register to select fs fs 4 fx or synchronous fx as the clock source The period of the output waveform is determined based on the clock source 4 Set the TM2PWM flag of the TM2MD register to 1 so that PWM operation is selected 5 Set a value in compare register 2 TM2OC The high interval of the output waveform is determined based on the value of the 2 compare register 6 Set the TM2EN flag of the TM2MD register to 1 to start the timer 7 When timer 2 begins operation binary counter 2 will count upward from X 00 8 high level signal is output from the port beginning when binary counter 2 starts counting at X 00 and ending when the value of binary counter 2 matches the value set in the TM2OC register 9 When the value of binary counter 2 matches that of the TM2OC register a low level signal is output from the port 10 Binary counter 2 continues to count upward until X FF is reached At the next count up cycle the value of binary counter 2 is reset to 00 a high level signal is output from the port and counting begins again ANNEE
3. 120 Chapter 7 AC Zero Cross Circuit Noise Filter 7 1 7 2 7 3 7 4 ero ETE 122 AC Zero Cross Circuit Operation eeu nn 123 T21 Setup abd Operations see EROR Der tees 123 Noise FIRST D 124 7 3 1 OVERVIEW awa aqa 124 7 3 2 Example Input and Output Waveforms for Noise Filter 125 AC Zero Cross Control ReSISfer eder tre IP i 126 7841 OWGIVIEW iux S u a NE TREE MIE net 126 7 4 2 Noise Filter Control Register NFCTR 127 Appendices 8 1 EPROM Versions ie eoo ec rie qe e ee ttu 130 8 1 1 Overview seen ote PE E eU ER E OR ertet pts 130 8 1 2 Cautions on Use ee ee 131 8 1 3 Erasing Written Data Windowed Packages a 132 PX AP101C11 SDC PX AP101C11 FBC 8 1 4 Characteristics of EPROM Versions 133 8 1 5 Writing to Internal 134 8 1 6 Cautions on Handling the ROM Writer 136 8 1 7 Option Bit eeepc e de EEE etaed 137 8 1 8 Writing Adapter Connection 138 8 2 Instruction Sets icio qo UR IR e RO FOR EE 141 8 3 Instruction Maps oe nth 147 8 4 Special Function ReEgiSterS sss a ee tee
4. B P70 to P71 oc neset 5 R Pull up pull down resistor control P t T Write 1L N Read Reset R Pull up pull down resistor selection DQ Write JL Read Reset o 5 gt i i a direction control P DQ E Write L XZ Read o gt 9 Reset LDH R Port output data DQ Write L Read m gt 277 Port input data 4 Read P71 Control bit Register address Pull up pull down resistor control P7PLUDO Pul up Control bit resistor control address P7PLUD1 P7PLUD X 03F47 P7RDWN FLOATI X 03F4B Control bit Register address Control bit Register address direction control Port input P7DIRO P7DIR1 P7DIR X 03F37 P7INO Control bit Register address Port output 0 P7INI P7IN X 08F27 P7OUTI P7OUT X 03F17 Figure 3 3 7 Configuration and Functions of P70 53 Port Configuration and Functions Chapter 3 Port Functions 60 to P67 P80 to P87 Reset Pull up resistor control Bd Write Reset 1 direction control g
5. Dual Function Function Description 24028 P10toP14 RMOUT I O port 1 5 bit CMOS tri state I O port TM2IO to Each bit can be set individually as either an input or output by theP1DIR register A pull up resistor for each bit can be selected individually by the PIPLU register At reset the input mode is selected and pull up resistors are disabled high impedance output 4 bit input port A pull up resistor for each bit can be selected IRQO Input port 2 individually by the P2PLU register At reset the input mode is IRQI SENS selected and pull up resistors are disabled high impedance output 20 23 pin does not exist for 42 SDIP 44 QFP packages 43 27 Input RST Input port 2 Port P27 has an n channel open drain configuration When 0 is written and the reset is initiated by software a low level will be output 33to40 P60toP67 I O port 6 8 bit CMOS tri state I O port I O port 7 Each bit can be set individually as either an input or output by the P DIR register A pull up resistor for each bit can be selected individually by the P6PLU register At reset the input mode is selected and pull up resistors for P60 to P67 are disabled high impedance output 2 bit CMOS tri state I O port Each individual bit can be switched to an input or output by the P7DIR register A pull up pull down resistor for each bit can be selected individually by the P7PLUD registe
6. 124 Noise Filter Chapter 7 AC Zero Cross Circuit Noise Filter 7 3 2 Example Input and Output Waveforms for Noise Filter When the noise filter is used the waveform input to the IRQO pin is sampled based on the clock specified by the 50 and NFOCKSI flags of the noise filter control register NFCTR The waveform input to the IRQI pin is also sampled based on the clock specified by the NFICKSO and NFICKS1 flags If the sampled level remains the same for 3 consecutive samples it is sent the CPU otherwise the previous level is maintained sm LLL DIM IR Waveform after noise filtering Figure 7 3 2 Noise Filter Input and Output Waveform Example a Noise filtering cannot be used in the STOP or HALT modes Noise Filter 125 Chapter 7 AC Zero Cross Circuit Noise Filter 2 4 3 Interrupt Control Registers External Interrupt Control Registers 3 2 2 I O Port Control Registers B Pin Control Registers 126 AC Zero Cross Control Register 7 4 AC Zero Cross Control Register 7 4 1 Overview Four registers control the AC zero cross circuit Table 7 4 1 AC Zero Cross Control Register Name Address R W Function IRQOICR X 03FE2 R W External interrupt control register 0 X 03FE3 External interrupt control register 1 FLOATI X 03F4B Pin control register 1 NFCTR X 03F8A
7. gt ANN PAO PA1 PA2 4 5 7 Pull up Control bit PAPLUDO PAPLUDI PAPLUD2 PAPLUD3 PAPLUD4 PAPLUDS PAPLUD6 PAPLUD7 resistor Register PAPLUD control address X 03F4A Control bit PARDWN Presistor Register FLOATI control address X 03F4B Input mode Control bit PAAINO PAAINI PAAIN2 PAAIN3 PAAIN4 PAAINS PAAING PAAINT Register PAIMD address X 03F3A Control bit PAINI PAIN2 PAIN3 PAIN4 PAINS PAING PAIN7 Port input Register PAIN address X 03F2A Special function Special function ANO ANI AN2 AN3 ANS AN6 AN7 Figure 3 3 3 Configuration and Functions of PAO to PA7 Port Configuration and Functions 49 Chapter 3 Port Functions E Pin Configuration for P20 P22 to P23 He Pull up resistor control vA Write 1 Va Read 5 Schmitt trigger input Port input data n Read Special function input data 20 P22 P23 Pull up Control bit P2PLUO P2PLU2 P2PLU3 P23 is only for resistor Register P2PLU yd i control address X 03F42 SDN package Control bit P2INO P2IN2 P2IN3 Port input Register P2IN address X 03F22 Special melon Interrupt input IRQO IRQ2 IRQ3
8. yore pappe asind WA dF L 91 1 1 OJIM PESH 8HIM PESH indui 91 8 7 3 260 Figure 4 1 2 Timer 4 Block Diagram Overview 58 Chapter 4 Timer Functions 3 Le swg z ZHW8 5 60 ZHYZE suosz lt acl uoneziu oJuou S 24 lt lt A 250 J OSSIA Jejunoo 1 8 SHTISNL VIS ZHISWL I J n A C 2 5 Z uote F ZHNSE 8 0 2 2 26 SOE CHOSWL IMOSIAL o OMOSIAL n Y XAN 250 Figure 4 1 3 Timer 5 Time Base Block Diagram 59 Overview Chapter 4 Timer Functions Ww a 4 jezzng 30718 re all 05708 ISAIQ
9. 6 Set the TM2EN flag of the TM2MD register to 1 to start the timer 7 When timer 2 begins operation binary counter 2 will count upward from X 00 8 When the value of binary counter 2 matches that of the TM2OC register the timer 2 Binary counter 200 interrupt request flag is set and the binary counter 2 is reset to X 00 and begins to count upward again Matches compare register Chapter 4 Timer Functions The period of a signal output to the port is 1 2 of the period set in the TM2OC register If port 1 is to be used as a pulse output pin it is necessary to set the port 1 output direction control register P1 DIR and the port 1 pull up pull down resistor control register P1PLU Figure 4 2 3 Timer Pulse Output Timing 8 bit Timer Operation timers 2 3 65 Chapter 4 Timer Functions If the flag of the TM3MD register is set to 1 and timer 2 PWM output is selected the PWM output of timer 2 will also be output from the pin If port 1 is to be used as a PWM output pin the P1DIR and P1PLU registers must be set 66 8 bit Timer Operation timers 2 3 PWM Output Function Timer 2 Settings for the PWM output function are listed below
10. Noise filter control register 7 4 2 Noise Filter Control Register NFCTR This 6 bit readable and writable register controls the noise filter 7 6 5 4 3 2 1 IFCTR NFICKS1 NF1CKSO NFIEN NFOCKS1 NFOCKSO Chapter 7 AC Zero Cross Circuit Noise Filter NFOEN at reset 000000 NFOEN IRQO noise filter setup and operation 0 IRQO noise filter off 1 IRQO noise filter on noise filter sampling period selection 0 0 5 2 1 15 28 fs 2 1 10 1 15 2 NFIEN noise filter setup and operation 0 1 noise filter off 1 IRQ1 noise filter on NeicKSt NFickso noise filter sampling period selection 0 0 2 1 16 28 fs 1 10 1 fs 2 Figure 7 4 1 Noise Filter Control Register NFCTR R W AC Zero Cross Control Register 127 Chapter 7 AC Zero Cross Circuit Noise Filter 128 Appendices 8 129 Chapter 8 Appendices 130 EPROM Versions 8 1 EPROM Versions 8 1 1 Overview EPROM version is microcomputer which was replaced with the mask ROM of the MN101C11 with an electronically programmable 16 KB EPROM Because the MN101CP117 DP BF HP is sealed in plastic once data is written to the internal PROM it cannot be erased Because the PX AP101C11 SDC and PX AP101C11 FBC are
11. Figure 3 3 4 Configuration and Functions of P20 P22 P23 50 Port Configuration and Functions 21 Chapter 3 Port Functions Pull up resistor control Data bus Special function input data L Read N Z Read Port input data AC zero cross detection circuit Special function input data KE 21 Pull up Control bit P2PLUI resistor Register P2PLU control address x 03F42 Control bit P2INI Port input Register P2IN address x 03F22 Special Special function SENS Control bit P21IM pu i Figure 3 3 5 Configuration and Functions of P21 lt Schmitt trigger input Port Configuration and Functions 51 Chapter 3 Port Functions 52 P27 N Schmitt trigger input Reset signal inpu lt e a 5 5 Port output data DQ gt p Write L 777 27 Special input RST Special function Soft reset output Special I bi function Control bit P20UT7 output Register P20UT address x 03F12 Figure 3 3 6 Configuration and Functions of P27 Port Configuration and Functions Chapter 3 Port Functions
12. O v 419410 one pes Os uondo lt 050 nol 4 980 9 2 1 S lt S0 g L 9809184 19594 H Naam HLOGM Refer to the aragraph 1 6 1 ROM option a 5 indui Figure 4 1 4 Watchdog Timer Buzzer Block Diagram Overview 60 Chapter 4 Timer Functions 1ndino UOIeZIUOIJOUAS ell E yndino l Figure 4 1 5 Remote Control Transmission Block Diagram 61 Overview Chapter 4 Timer Functions 62 8 bit Timer Operation timers 2 3 4 2 1 Overview Functions for timers 2 and 3 are listed below 4 2 8 bit Timer Operation timers 2 3 Table 4 2 1 Summary of 8 bit Timer Functions Timer2 Timer 8 bit 8 bit Interrupt TM2IRQ Timer operation Event counter Timer pulse output O Serial x transmission clock SIFO PWM output connection Remote control carrier pulse generation 4 2 2 Timer Operation timers 2 3 Settings for timer operation are listed below Timer 2 is used as an example 2 counter 4 Set the TM2EN flag of the timer 2 mode register TM2MD to 0
13. TM4EN count control 0 Halt the count 1 Operate the count Figure 4 9 15 Timer 4 Mode Register TM4MD X O3F84 R W Timer Function Control Registers 87 Chapter 4 Timer Functions 88 7 6 5 4 Timer 5 mode register TM5MD 4 3 2 1 0 TM5MD TMSCLRS TMSIR2 TMSIR1 TM5IRO TMSCK3 TMSCK2 TMSCK1 TM5CKO at reset Time base timer Timer Function Control Registers TMSCK0 clock source selection 0 fosc 1 Use Prohibited fx 48QFH package only TM5CK3 TM5CK2 TM5CK1 Timer 5 clock source selection 0 fosc 9 1 fs 4 0 0 Use Prohibited 1 1 Output of time base timer 0 Use Prohibited 1 Synchronous time base timer output TMSIR2 mU 0 0 1 2 of the clock source 0 1 1 28 of the clock source 0 1 2 of the clock source 1 1 2 of the clock source 1 x x 1 213 of the clock source TM5CLRS 0 Enable initialization of TM5BC during write to 1 Disable initialization of TMSBC during a write to 5 If TM5CLRS 0 5 is disabled Figure 4 9 16 Timer 5 Mode Register TM5MD X O3F88 R W Chapter 4 Timer Functions 4 9 4 Timer Control Registers 1 Watchdog timer control register WDCTR 7 6 5 4 3 2 1 0 WDCTR m WDEN
14. d16 An Dm mem8 d16 An Dm 0110 1ADm lt d16 MOV d4 SP Dm 8 d4 SP gt Dm 0110 01Dm lt d4 gt MOV d8 SP Dm 8 d8 SP gt Dm 0110 01Dm lt d8 MOV d16 SP Dm 0110 00Dm lt d16 MOV 8 mem8 IOTOP io8 Dm 0110 00Dm io8 MOV abs8 Dm mem8 abs8 5 Dm 0100 01Dm abs MOV abs12 Dm 8 d16 SP gt Dm mem8 abs12 5Dm 0100 00Dm abs MOV abs16 Dm mem8 abs16 5Dm 1100 00Dm abs MOV Dn Am Dnmem8 Am 0101 1aDn MOV Di n d8 Am Dn mem8 d8 Am 0111 1aDn 98 Dn d16 Am Dn mem8 d16 Am 0111 1aDn lt d16 MOV Dn d4 SP Dn mem8 d4 SP 0111 01Dn lt d4 gt MOV Dn d8 SP 0111 01Dn 98 Dn d16 SP Dn mem8 d16 SP 0111 00Dn lt d16 MOV Dn io8 Dn mem8 IOTOP i08 0111 00Dn lt io8 MOV Dn abs8 8 058 0101 01Dn abs MOV n Dn abs12 Dn mem8 d8 SP Dn mem8 abs12 0101 00Dn lt abs MOV Dn abs16 516 1101 00Dn lt abs MOV imm8 io8 imm8 mem8 IOTOP io8 0000 0010 lt 08 MOV imm abs8 imm8 meme8 abs8 0001 0100 abs MOV imm8 abs12
15. 10 Input capture register TM4ICH upper 8 bits 7 6 5 4 3 2 1 0 TM4ICH7 TM4ICH6 5 TM4ICH3 TM4ICH2 TM4ICH1 TM4ICHO at reset undefined Figure 4 9 10 Input Capture Register TM4ICH X O3F67 11 Compare register 5 TM5OC 7 6 5 4 3 2 1 0 TM50C7 TM50C6 50 4 usocs TM5OC2 50 1 50 0 at reset undefined Figure 4 9 11 Compare Register 5 TM5OC X 03F78 R W 12 Binary counter 5 TM5BC 7 6 5 4 3 2 1 0 TM5BC7 TM5BC6 5 5 TM5BC4 TM5BC3 TM5BC2 TM5BC1 TM5BCO reset 00000000 Figure 4 9 12 Binary Counter 5 TM5BC X O3F68 84 Timer Function Control Registers 4 9 3 Timer Mode Registers Four readable and writable 6 byte timer mode registers Control timers 2 3 4 5 and the time base 1 Timer 2 mode register TM2MD Chapter 4 Timer Functions 7 6 5 4 3 2 1 0 TM2MD 2 TM2PWM TM2CK2 TM2CK1 TM2CKO at reset OOXXX TM2CK2 TM2CK1 2 Clock source selection X 0 0 fs 1 fs 4 0 1 0 fx 1 2 input 0 Synchronous fx 1 Synchronous TM210 input 48QFH package only TM2PWM TM2 operation mode selection 0 Normal timer operation 1 PWM operation TM2bEN 2 count control 0 Halt the count 1 Operate the count Figure 4 9 13 Timer 2 Mode Register T
16. A push pull or n channel open drain configuration can be selected for TXD by the SCOMDI register Pull up resistors can be selected by the POPLU register The TXD and pins are also allocated as and respectively When not used as serial UART pins these can be used as normal I O pins 20 5 00 Output TXD P00 Serial interface transmit data output pin Transmit data output pin for serial interfaces 0 The output configuration either CMOS push pull or n channel open drain and pull up resistors can be selected by the software Set these pins to the output mode by the PODIR register SBOO is allocated as 00 This may be used as normal I O pin when the serial interface is not used 21 SBIO Input RXD P01 Serial interface receive data input pin Receive data input pin for serial interfaces 0 Pull up resistor be selected by the POPLU register Set these pins to the input mode by the PODIR register SBIO is allocated as This be used as normal I O pin when the serial interface is not used 22 SBTO I O P02 Serial interface clock I O pin Clock I O pin for serial interface 0 The output configuration either CMOS push pull or n channel open drain output can be selected by the software The direction of SBTO is selected by the PODIR register in accordance with the communication mode Pull up resistors can be selected by the POPLU registe
17. At reset the input mode is selected and pull up resistors are disabled high impedance output Bi Port 2 P2 4 bit CMOS tri state input port Table 3 1 4 Port 2 Functions Pin Name Type Dual Function Description P20 to P23 Input 00 pull up resistor for each bit be selected individually IRQI SENS bythe P2PLU register At reset the input mode pull up IRQ to 3 resisters are disabled high impedance output Only 48 QFH has P23 Port 6 P6 8 bit CMOS tri state I O port Table 3 1 5 Port 6 Functions Pin Name Type Dual Function Description P60 to P67 Each bit can be set individually as either an input or output by the P6DIR register A pull up resistor for each bit can be selected individually by the POPLU register At reset the input mode pull up resisters are disabled high impedance output Overview 39 Chapter 3 Port Functions E Port 7 P7 8 bit CMOS tri state I O port Table 3 1 6 Port 7 Functions Pin Name P70 to P71 Type I O Port 8 P8 8 bit CMOS tri state I O port Dual Function Description Each individual bit can be switched to an input or output by the P7DIR register A pull up or pull down resistor for each bit can be selected individually by the P7PLU register However pull up and pull down resistors cannot be mixed At reset the input mode pull up resisters are disabled
18. Output off RMOUT 1 8 duty Figure 4 7 1 Remote Control Carrier Output Waveform Remote Control Output Operation 79 Chapter 4 Timer Functions 80 Buzzer Output 4 8 Buzzer Output 4 8 1 Buzzer Output Setup and Operation The square wave having a frequency 1 2 to 1 2 of the system clock can be output from the PO6 BUZZER pin 1 2 3 4 Set the BUZOE flag of the oscillation stabilization wait control register DLYCTR to 0 so that the buzzer output is turned off Set the buzzer output frequency with the BUZCKI and BUZCKO flags of the DLYCTR Set the BUZOE flag of the DLYCTR register to 1 and set 06 to the buzzer output mode The BUZOE flag of the DLYCTR register controls whether the buzzer output is ON or OFF Chapter 4 Timer Functions 4 9 Timer Function Control Registers 4 9 1 Overview 19 registers control the timers See table 4 9 1 Table 4 9 1 Timer Control Registers Address Function 2 X OSF72 Compare register 2 TM2BC X OSF62 Binary counter 2 TM2MD X O3F82 Timer 2 mode register X OSF73 Compare register 3 TMSBC X O3F63 Binary counter 3 TM3MD X O3F83 Timer 3 mode register TM4OCL X 03F 74 Compare register 4 lower 8 bits TM4OCH X OSF75 Compare register 4 upper 8 bits TM4BCL 03 64 Binary counter 4 lower 8 bits TM4BCH X O3F65 Binary counter 4 upper 8 bits TM4ICL X O3F66 Input capture regis
19. at reset 0 WDEN Watchdog timer enable 0 Clear watchdog timer disable operation 1 Enable WDT timer Figure 4 9 17 Watchdog Timer Control Register X OSF02 R W 2 Oscillation stabilization wait control register DLYCTR 7 6 5 4 3 2 1 0 DLYCTR BUZOE BUZCK1 BUZCKO DLYS1 DLYSO at reset OXX 00 Oscillation stabilization wait period setting DLYS1 DLYSO 0 1 214 of the system clock fs 1 1 2 of the system clock fs 1 0 1 26 of the system clock fs 1 1 Disable use After reset is released the oscillation stabilization wait period is fixed at 1 215 0 Buzzer output BUZCK1 BUZCKO frequency selection 1 212 of the system clock fs 1 2 of the system clock fs 1 21 of the system clock fs 1 29 of the system clock fs BUZOE P06 output selection 0 port output P06 buzzer output Figure 4 9 18 Oscillation Stabilization Wait Counter Control Register DLYCTR X 03F03 R W Timer Function Control Registers 89 Chapter 4 Timer Functions 90 3 Remote control carrier output control register RMCTR 2 1 0 at reset 00XX0 RMCTR jura Timer Function Control Registers Be Must be set to 0 Remote control carrier RMDTYO output duty selection 0 1
20. MOVW DWn Am Extension code b 0010 2nd nibble 3rd nibble 0 1 MOVW An Am MOVW An d4 SP MOVW DWn 04 5 CMPW PUSH Dn 8 9 A B MOVW SP Am MOVW An SP ADDW 8 5 ADDW 4 SP D 5 8 Dm J 0 J SR A0 J MP 1 JSR MOV PSW Dm REP 38 BGT d7 BHI d7 BLS d7 d7 BNS d7 d7 BVS d7 NOT Dn ROR Dn BGT d11 BHI d11 BLS 411 BNC 011 5 d11 BVC d11 BVS 911 ASR Dn LSR Dn SUBW DWn DWm SUBW 16 DWm SUBW 16 Am SUBW DWn Am MOVW DWn Am ADDW DWn DWm ADDW 16 DWm ADDW 16 Am ADDW DWn Am CMPW DWn Am MOV d16 SP Dm MOV d8 SP Dm d16 An Dm MOV Dn d16 5P Dn d8 SP MOV Dn d16 Am MOVW DWn DWm n m CMPW DWn DWm ADDUW Dn Am EXT Dn DWm AND OR 8 PSW Dn PSW ADDSW Dn Am SUB Dn Dm SUB 8 Dm SUBC Dn Dm MOV abs16 Dm MOVW abs16 Am MOVW abs16 DW CBEQ 8 Dm d12 MOVW An DWm MOV Dn abs16 MOVW 0516 MOVW DWh abs16 CBNE 8 Dm d12 CBEQ 8 abs8 d7 d11 48 abs8 d7 d11 MOVW d16 SP Am MOVW d16 5P DWm MOVW d8 SP Am MOVW d8 SP DWi MOVW An Am ADDW 8 Am DIVU MOVW An d16 SP MOVW DWn d16 SP MOVW An d8 SP MOVW DWn d8 SP MOVW An Am MULU 147 I
21. Operating Conditions retener ER EIER ER tuse tt ep tope 14 5 3 uu 17 1 5 4 A D Converter Characterist1Cs ecciesie etae iter aene enne on etes 21 ipM aqa 22 126 1 ROM PARU 22 1 6 2 Option Check basti die hen ind MR 23 Dra win SS 24 Chapter 2 Basic CPU Functions 2 1 2 2 2 3 2 4 han i 28 Address Space 2 2 1 Memory Configuration u anu G titre tine a eee nn etus 28 2 2 2 Special Function Registers 28 Bus Interface en ME 29 2 3 1 OV CRVICW T 30 2 3 2 Gonttol Reglster esce teo pU Ete teense 30 31 2 4 1 Accepting and Returning from Interrupts sese 31 2 4 2 Interrupt Sources and Vector Addresses a 33 2 4 3 Interrupt Control Registers 34 Reset siue an E E Nes 36 Chapter 3 Port Functions 3 1 3 2 3 3 OVETVIEW 38 Port Control Registers iie p ORE pb eh ra tie hernie 41 3 22 te e eee 41 3 2 2
22. Port Control Registers sd 45 Port Configuration and Functions 47 Chapter 4 Timer Functions 4 1 4 2 4 3 4 4 4 7 4 8 4 9 OVErVIEW item t e d ati e eee ete I e rt E 56 8 bit Timer Operation timers 2 3 ss 62 42241 OVETVICW 62 452 2 S Operationince cosines tek AA a uuu Nas 63 16 bit Timer Operation timer 4 69 4 3 l OVerVI W isis eee nei e pete ite p iE fond 69 4 3 2 sionis epson edulis eo 69 8 bit Timer Operation timer 5 76 4 4 1 e mitte etes 76 4 4 2 Operation idit e Re per re 76 Time Base Operation ass eere TI 4 5 COVGIVIEW iicet eia dp esee he d TI 4 5 2 Operation inse e egere detache ii tatur TI Watchdog Timer Operation ss 78 4 621 OVerVIeW iicet eti ose eterne Rer aiti ost itte 78 4 6 2 Setup and Operation eet eicere teen 78 Remote Control Output Operation 79 4 7 e UR t UH RS 79 42722 Setup and Operation reto en pe Peor nee ped 79 B zzer o ete eee edt e ee o Eee 80 4 8 1 Buzzer Output Setup and 80 Timer Function Control Registers ss 81 4 9 OVerVI W ede peribit dr 81 4 9 2 Programmable Timer Counters 2 2 82
23. R W External Interrupt Control Registers IRQnICR The external interrupt control registers IRQnICR control the interrupt level valid edge and request enable 7 6 5 4 3 2 1 0 IRQnICR xxxLV1XxxxLVO xxxlE xxxIR at reset 000 00 xxxIR External interrupt request flag 0 No interrupt request 1 Happens interrupt request xxxIE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt REDGn External interrupt valid edge flag 0 Falling edge 1 Rising edge xxxLV1 xxxL VO Interrupt level flag for external interrupt The CPU has interrupt levels from 0 to 3 This flag sets the interrupt level for interrupt requests n 0 1 2 3 4 Figure 2 4 3 External Interrupt Control Register IRQnICR X OSFE2 to to X OSFED R W Internal Interrupt Control Registers TMnICR TBICR SCOICR ATCICR ADICR The internal interrupt control registers TMnICR TBICR SCnICR ATCICR ADICR control the interrupt levels of internal interrupts timer interrupts serial interrupts A D conversion complete interrupts and interrupt request enable Be sure to disable all interrupts before writing to these registors 7 6 5 4 3 2 1 0 TMnICR TBICR SCniCR at reset 00 00
24. 4 9 3 Timer Mode Registers 85 4 9 4 imer Control Registers eto erre ee e rete tene 89 Contents 2 Contents 3 Chapter 5 Serial Functions 5 I 5 2 5 3 5 4 rA aquqa M 92 Synchronous Serial Interface ect OR 94 9 21 OVVIE W ee n OE HR 94 3 272 Setup and Operation ep ertet ii ie ere 94 5 2 3 Serial Interface Transfer Timing 99 Half duplex UART Serial Interface ss 101 9 3 1 101 2 3 2 Set p and Op ration etie eere vetet uo oen da 101 5 3 3 How to Use the Baud Rate 105 serial Interface Control Registers uoo Seo Oe PESO TERRE 106 541 OVERVIEW 106 5 4 2 Transmit Receive Shift Registers Receive Data Buffer 107 5 4 3 Serial Interface Mode Registers ss 108 5 4 4 Serial Interface Control Register 112 Chapter 6 A D Conversion Functions 6 1 6 2 6 3 OO VEEVIeW DRE SEEN PERDRE EO EAR 114 A D CONVERSION I 115 A D Converter Control Reglstets nn 117 OI OVERVIEW 117 6 3 2 A D Control Register l 118 6 3 3 A D Bulfers
25. ATCICR ADICR 1 xxxIR xxxIR Interrupt request flag 0 No interrupt request 1 Happens interrupt request XXXIE Interrupt enable flag 0 Disable interrupt Enable interrupt xxxLV1 xxxLVO Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Figure 2 4 4 Internal Interrupt Control Registers TMnICR TBICR SCOICR ADICR X OSFE6 to X OSFEA to R W Chapter 2 Basic CPU Functions By setting xxxLVn to 11 level 3 the corresponding interrupt vector will be disabled regardless of the state of the interrupt enable and interrupt request flags Interrupts 35 Chapter 2 Basic CPU Functions For the reset to be stable the low pulse must be maintained for at least four clock cycles However it is important to minimize noise since a reset may occur in a smaller number of clock cycles 36 Reset 2 5 Reset The CPU contents are reset and registers are_initialized when the RST pin is pulled to low Initiating a Reset There are two methods to initiate a reset 1 Drive the RST pin low for at least four clock cycles RST 4 clock cycles 200ns for a 20MHz oscillation Figure 2 5 1 Minimum Reset Pulse Width 2 Set bit 7 P2OUT7 flags of the P2OUT register to 0 After reset is released the P
26. IRQ2 P22 IRQ3 P23 RST P27 AN7 PA7 AN6 PA6 AN5 PA5 AN4 PA4 AN3 PA3 e 2d S5 s x x gt gt gt 5 P60 Sub clock lt lt P6 oscillator MN101C00 gt 62 oscillator m w P63 gt 64 ROM RAM 2 4 5 P65 16 512 bytes P66 m 3 4 gt P67 8 bit timer 2 External interrupt gt 70 HU lt lt P71 8 bit timer 3 Serial interface 0 5 a 16 bit timer 4 Time base timer 5 P80 LEDO pP81 LED1 A D conversion Watchdog timer 4 5 21 2 e 5 P83 LED3 a AN2 PA2 J 1 1 ANO PA0 12 Overview of Function P84 LED4 P85 LED6 4 35 P86 LED6 P87 LED7 Figure 1 4 1 Block Diagram of Functions 1 5 Electrical Characteristics Contes Model MN101C117 115 Classification CMOS integrated circuit Use General purpose Function CMOS 8 bit single chip microcomputer Chapter 1 Overview 1 5 1 Absolute Maximum Ratings This LSI manual describes standard specifications Before using the LSI please obtain product specifications from the sales office Parameter Symbol Rating Unit 1 Supply voltage M 0 3 to 7 0
27. Matches 2 __ register Binary counter 2 PWM output amd gt Time specified by TM2OC register lt gt Time until binary counter 2 reaches X FF Figure 4 2 4 PWM Output Timing Chapter 4 Timer Functions Clock PWM output Figure 4 2 5 PWM Output Timing when 2 register is X 00 Matches TM2CC register Overflow P Binary counter 2 PWM output Figure 4 2 6 PWM Output Timing when 2 register is X FF 8 bit Timer Operation timers 2 3 67 Chapter 4 Timer Functions The clock source for the serial interface has a frequency that is 1 2 of the overflow output of timer 3 For serial interface settings refer to the chapter on serial functions Disable the timer 2 interrupt Serial Transfer Clock Function timer 3 Settings for the serial transfer clock function are listed below 1 2 3 4 5 6 7 8 Set the TM3EN flag of the timer 3 mode register TM3MD to 0 to stop the count operation of timer 3 Set the SCOCK1 and SCOCKO flags of the serial interface 0 mode register 1 SCOMD1 to select 1 2 of the timer 3 overflow frequency as the clock source Set the TM3CK2 to 0 flags of the TM3MD register to select fosc fs fs 4 or fs 16 as the clock source Set the TM3PWM flag of the TM3MD register to
28. Option bit 7 6 5 4 3 2 1 0 PKGSEL2 PKGSEL1 WDSEL2 WDSEL1 NSSTRT Selection of oscillation mode NSSTRT after resetting 0 Low mode 1 NORMAL mode WDSEL2 WDSEL1 Watchdog timer cycle setting 0 219 0 18 1 5 2 1 X PKGSEL2 PKGSEL1 Package 0 X SDIP042 P 0600 0 QFP044 P 1010 1 QFH048 P 0707 Fig 8 1 2 Option bit Address X 07FFF EPROM Versions 137 Chapter 8 Appendices 8 1 8 Writing Adapter Connection VSS VSS VSS VSS VSS VSS vcce A149 VSS VSS VSS VSS Al VSS lt iUe VSS A11 CI A109 55 9 NCE gt 12 C 00 14 I D19 2 gt 15 I 2 D3 A4 gt D4 A59 gt 15650 05 6 f D6 7 D79 VSS VCC Package Code SDIP042 P 0600 Fig 8 1 3 MN1 1CP117 DP DC EPROM Writing Adapter Connections Refer to the pin connection drawing of the 256 bit 4 27 256 138 EPROM Versions Chapter 8 Appendices ss TESS ARRAS OO m c C D3 gt 1 P836 63 lt gt 2 P6282 lt 24 019 19 61 1 lt 1 4 4 lt A0 A8 gt 5 foe 22 9 lt Aes cfe MNIOICP117 A10 P20 27 11 VSS A12 VSS 13 VSS VSS VSS S lt
29. e e 8 45 0010 1100 10Dm 48 dii 8 116 if Dm4imm8 PC 8PC CBEQ imm8 abs8 label _if mem8 abs8 imm8 PC 9 d7 label HPC e e 9 6 7 0010 1101 1100 abs 8 gt 8 gt lt d7 x2 117 if mem8 abs8 zimm8 PC4 9 PC CBEQ imm8 abs8 label _ if mem8 abs8 imm8 PC 10 d1 1 label H5PC mem8 abs8 zimm8 PC 10 PC CBEQ imm8 46516 lif mem amp abst6 imm8 PC 11 d7 abe H2PC e e 11 7 8 0011 1101 1100 abs 16 gt lt d7 H 118 C C e ee e 10 67 0010 1101 1101 abs 8 48 gt dii 3 117 if mem8 abs16 imm8 PC 11 P if mem8 abs16 imm8 PC 12 d1 label H if mem8 abs16 4imm8 PC 122 PC CBEQ imm8 abs16 label 12 7 0011 1101 1101 abs 16 gt lt dii H 3 118 CBNE imm8 Dm label if DmZimm8 PC 6 d7 label HOPC e e 6 3 4 1101 10Dm 48 gt lt d7 H gt 119 if Dm imm8 PC 6 PC CBNE imm8 Dm label if Dm4imm8 PC 8 d1t labe HOPC e e e 8 4 5 0010 1101 10Dm 48 gt dii 3 119 8 8 CBNE imm8 abs8 label lif mem amp abs8 Zimm8 PC 9 d7 abe HOPC e e 9 6 7 0010 1101 1110 abs 8 lt 8 gt lt d7 120 if mem8 abs8 imm8 PC4 9 PC CBNE immB abs8 label _ if mem8 abs8 4imm8 PC 10 d1 label 3PC 10 6 7 0010 1101 1111 abs 8
30. gt lt gt lt gt e lt gt ED OEY e lt n Q n n n n m gt gt gt gt gt gt gt gt gt lt Package code QFP044 P 1010 Pin pitch 0 8mm Fig 8 1 4 MN101CP117 BL BC EPROM Writing Adapter Connections Refer to the pin connection drawing of the 256 bit 4 27 256 EPROM Versions 139 Chapter 8 Appendices 0022 9 Q OQ Q Q gt gt gt gt lt lt lt lt MN101CP117 lt gt lt gt CO CO unong gt gt gt gt gt gt gt gt 2 gt Package code QFH048 P 0707 Pin pitch 0 5mm Fig 8 1 5 MN101CP117 HP EPROM Writing Adapter connections Refer to the pin connection drawing of the 256 bit 4 27 256 2 A19 vsse9 vsse9 vsse9 vsse9 vsse9 VSS 140 EPROM Versions 8 2 Instruction Set 101 00 SERIES INSTRUCTION SET Mnemonic Data move instructions MOV Dn Dm Operation Dn Dm Affected FI 1010 DnDm Machine Code 6 7 8 Chapter 10 Appendices MOV imm8 Dm imm8 5Dm 1010 DmDm lt 8 MOV Dn PSW 1001 01Dn PSW Dm PSW Dm 0001 01Dm MOV An Dm mem8 An Dm 0100 1ADm MOV d8 An Dm mem8 d8 An 5 Dm 0110 1ADm lt 08 MOV
31. imm8 mem8 abs12 0001 0101 lt abs MOV immB abs16 imm8 gt mem8 abs16 1101 1001 lt abs MOV Dn HA Dn mem8 HA 1101 00Dn MOVW An DWm mem16 An DWm 1110 MOVW 16 gt 1110 10Aa MOVW d4 SP DWm mem16 d4 SP DWm 1110 0114 16 44 5 gt 1110 010 MOVW d4 SP Am MOVW d8 SP DWm mem16 d8 SP DWm 1110 0114 MOVW d8 SP Am mem16 d8 SP Am 1110 010a mem16 1110 001d MOVW d16 SP Am mem16 d164SP Am 1110 000a MOVW abs8 DWm mem16 abs8 2DWm 1100 0114 MOVW abs8 A mem16 abs8 Am 1100 010a MOVW abs16 DWm d16 SP DWm mem16 abs16 2DWm 1100 0114 MOVW d16 SP DWm a MOVW abs16 Am 16 5516 gt 1100 010 MOVW DWn Am DWn mem16 Am 1111 00aD MOVW gt 16 1111 10 MOVW DWn d4 SP DWn gt mem16 d4 SP 1111 011D MOVW An d4 SP An mem16 d4 SP 1111 010A MOVW DWn d8 SP DWn gt mem16 d8 SP 1111 011 MOVW An d8 SP 16 8 5 1111 010 MOVW DWn d16 SP DWn gt mem16 d16 SP 1111 001D MOVW An d16 SP 16 16 5 1111 000A MOVW DWn abs8
32. 0 SCOCTR SCOBSY SCOCMD scorer Sooper conr at reset 00XX000X SCOORE Overrun error detection 0 No Error 1 Error SCOPEK Parity error detection 0 No Error 1 Error SCOFEF Framing error detection 0 No Error 1 Error Synchronous serial SCOCMD UART selection 0 Synchronous serial 1 UART SCOBSY Serial bus status 0 Other use 1 Serial transmission in progress Figure 5 4 7 Serial Interface 0 Control Register SCOCTR X O3F54 R W available with SCOCMD only 112 Serial Interface Control Registers A D Conversion Chapter 6 Functions 113 Chapter 6 A D Conversion Functions 6 1 Overview The MN101C117 has an internal A D converter with 10 bit resolution A sample and hold circuit is contained on chip and software can switch the analog input between channels 0 to 7 ANO to AN7 When the A D converter is stopped power consumption can be reduced by turning off the internal ladder resistors 0 ANBUF1 0 ANBUFO 0 ANBUF10 ANBUF11 ANBUF12 ANOTRO 0 L ANBUF13 I AN HeT z i ANBUF14 E ANCHS1 lt A D NEUE ANCHS2 _ ANBUF16 ANBUFO6 ANARE ANBUF17 ANBUFO7 ANCK1 A A ANSH0 ANSH1 7 3 Y RS Y ANO gt 2 AN2 2 Y
33. 0 to select timer 3 output Set a value in compare register 3 Set the TM3EN flag of the TM3MD register to 1 to start the timer When timer 3 begins operation binary counter 3 counts upward from 00 When the value of binary counter 3 matches that of the TM3OC register the timer 3 interrupt request flag is set the value of binary counter 3 is reset to 00 and counting begins again Cascade Connection Function timer 2 timer 3 Settings for the cascade connection function are listed below Timer 2 and timer 3 are connected to operate as a 16 bit timer 1 2 3 4 5 6 7 8 9 10 Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the count operation of timer 2 Set the TM3EN flag of the timer 3 mode register TM3MD to 0 to stop the count operation of timer 3 Set the TM2CK2 to 0 flags of the TM2MD register to select fs fs 4 fx or synchronized fx as the clock source Use the TM3CK2 to 0 flags of the TM3MD register to set the clock source as a cascade connection with timer 2 Set the TM2PWM flag of the TM2MD register to 0 to select normal timer operation Set values in compare register 2 2 and compare register 3 TM3OC Set the TM2EN flag of the TM2MD register to 1 to start the timer Set the TM3EN flag of the TM3MD register to 1 to start the timer When timers 2 and 3 begin operation the binary counters begin counting upward from
34. 0000 as a 16 bit counter When the value of the 16 bit binary counter matches that of the 16 bit register 200 the timer 3 interrupt request flag is set the value of the 16 bit binary counter is reset to X 0000 and counting begins again 68 8 bit Timer Operation timers 2 3 Use a 16 bit access instruction to set the 20 register 4 3 16 bit Timer Operation timer 4 4 3 1 Overview Timer 4 is a 16 bit programmable counter that can be used as an event counter A signal with a frequency of 1 2 of the timer 4 overflow signal can be output from the TMAIO pin An input capture function and pulse added type PWM output function can also be used 4 3 2 Operation Timer Operation Settings for timer operation are listed below 1 2 3 4 5 6 7 Set the TM4EN flag of the timer 4 mode register TM4MD to 0 to stop the count operation of timer 4 Set TM4CK2 to 0 flags of TM4MD register to select fosc 15 4 fs 16 as the clock source Set the TM4PWM flag of the TM4MD register to 0 to select 16 bit timer operation Set a value in compare register 4 TM40CL Set the TM4EN flag of the TM4MD register to 1 to start the timer When timer 4 begins operation binary counter 4 counts upward from X 0000 When the value of binary counter 4 matches that of the TM4OCL registers the timer 4 interrupt request flag is set the valu
35. 1000 01Dd 1 81 CMPW DWn Am Am DWn PSW 0010 0101 11Da 81 CMPW An Am Am An PSW 3 0010 0000 01 2 82 CMPW imm16 DWm DWm imm16 PSW 0000 5 1100 1104 lt 16 de 82 CMPW imm16 Am Am imm16 PSW 1101 110a H6 gt 83 Logical instructions AND AND Dn Dm Dm amp Dn Dm 0 0e 2 0011 0111 DnDm 84 AND imm8 Dm Dm amp imm8 Dm 01 oe 2 0001 11Dm 48 gt 84 AND imm8 PSW PSW amp imm8 PSW 0000 5 0010 1001 0010 lt 8 gt 85 OR OR Dn Dm 018 008 3 2 0011 0110 DnDm 86 OR imm8 Dm 018 0 8 4 2 0001 10Dm lt 8 gt 86 OR imm8 PSW PSWlimm8 PSW 0000 s 3 0010 1001 0011 lt 8 gt 87 XOR Dn Dm Dm DnDm 01e 0e 3 2 0011 1010 DnDm 9 88 XOR imm8 Dm Dm imm8 Dm 0060 0853 0011 1010DmDm lt 8 gt 88 Note Page refers to the corresponding page in the Instruction Manual 1 D DWn d DWm 5 D DWm 49 man 2 A An a Am 4 sign extended 3 d DWm 7 8 sign extended 4 D DWk 8 Dn zero extended 142 Instruction Set 101 00 SERIES INSTRUCTION SET Chapter 10 Appendices Group Mnemonic Operation Affected Flag NotesPaga 7 Expand 1 10 11 NOT NOT Dn Dn2Dn eo 0010 89 ASR ASR Dn Dn msb temp Dn Isb 0011 90 Dn 1 Dn tempDn msb LSR LSR Dn Dn lsbSCF Dn 1 Dn oe 0011 91 0 Dn msb ROR ROR Dn Dn Isbtemp Dn 1 Dn 0 0010 92 Bit manipulation instructions CF Dn
36. 2 duty 1 1 3 duty Must be set to 0 RMOEN Enable remote control carrier output Output low level 1 Output remote control carrier Must be set to 0 Figure 4 9 19 Remote Control Carrier Control Register RMCTR X 03F89 R W Chapter 5 Serial Functions 91 Chapter 5 Serial Functions 5 1 Overview The 101 117 contains a serial interface that can operate in synchronous and simple UART modes An overview of serial functions is shown below Table 5 1 1 Overview of Serial Functions Serial 0 Interrupt SCOICR Synchronous Simple UART O fs 2 fs 4 Clock selection fs 16 BC3X1 2 External 1 8 period of clock 92 Overview Chapter 5 Serial Functions 2 1 IA z ixeog 9 I p s lt 2 5 4 288008 TE 070095 182028 032006 2098 319095 130098 234005 318005 040026 84005 ZON100S gt 1488026 240098 LSNT09S gt 281026 0971095 181026 H1909S oqwoos 1010925 Y X X n n N E 81 N 6 0402 Y 3d T X 01
37. 42 SDIP has no pins of P70 P71 44 QFP has no pin of p71 Table 3 1 7 Port 8 Functions Pin Name Type Dual Function Description P80 to P87 LEDO to 7 Each individual bit can be switched to an input or output by the P8DIR register A pull up resistor for each bit can be selected individually by the P8PLU register When configured as outputs it is possible to LED At reset when single chip mode is selected the input mode pull up resisters for P80 to P87 are disabled high impedance output Bi Port PA 8 bit CMOS tri state input port Table 3 1 8 Port A Functions Pin Name Type Dual Function Description 40 Overview PAO to PA7 Input ANO to AN7 A pull up or pull down resistor for each bit can be selected individually by the PAPLUD register However pull up and pull down resistors cannot be mixed At reset the input mode pull up resisters for PAO to PA7 are disabled 3 2 Port Control Registers 3 2 1 Overview 28 registers control the ports See table 3 2 1 Table 3 2 1 1 0 Port Control Registers 1 2 Name Address R W Function POOUT X 03F 10 R W Port 0 output register P1OUT X O3F11 R W Port 1 output register P2OUT X 03F12 R W Port 2 output register P6OUT X O3F16 R W Port 6 output register P7OUT X O3F17 R W Port 7 output register P8OUT X O3F18 R W P
38. 5 6 7 8 9 10 11 MOVW imm16 Am imm16 gt Am 61 3 1101 111a H6 m 54 MOVW SP Am SP Am 313 0010 0000 100a 55 MOVW 5 AnoSP 313 0010 0000 101 55 MOVW DWn DWm DWn DWm 831 3 0010 1000 56 MOVW DWn Am DWn Am 3 3 0010 0100 11Da 56 MOVW An DWm An DWm 3 3 0010 1100 11 57 MOVW 3 3 0010 0000 00 2 57 PUSH PUSH Dn SP 15SP Dn mem8 SP 213 1111 10Dn 58 PUSH SP 2 gt SP An mem16 SP 215 0001 011A 58 POP POP Dn mem8 SP gt Dn SP 1 SP 213 1110 10Dn 59 memi6e SP OAnSP422SP 2 4 0000 011A 59 EXT EXT DnDWm sign Dn 2DWm 291 12 81 8 0010 1001 000d 3 60 Arithmetic instructions ADD ADD Dn Dm Dm Dn gt Dm 2 O 0011 0011 DnDm 61 ADD imm4 Dm Dm sign imm4 Dm eoeo o9 2 1000 00Dm lt 4 gt 6 61 ADD imm8 Dm Dm imm8 Dm 0000 4 2 0000 10Dm lt 8 gt 62 ADDC ADDC Dn Dm Dm Dn CF gt Dm 2 O 0011 1011 63 ADDW ADDW DWn DWm DWm DWn DWm 3 0010 0101 1 64 ADDW DWn Am Am DWn gt Am O 0010 0101 10Da 64 ADDW imm4 Am Am sign imm4 gt Am eo o0 2 1110 110a lt 4 gt 6 65 ADDW imm8 Am Amesign imm8 Am 0000 5 3 0010 1110 110a lt 8 gt 7 65 ADDW imm16 Am Am imm16 Am 0000 7 4 0010 0101 011a lt 16 66 ADDW imm4 SP 5 5 4 3 2 1111 1101 lt gt 6 66 ADDW 8 5 SP
39. DWn gt mem16 abs8 1101 011D MOVW An abs8 An mem16 abs8 1101 010A MOVW DWn abs16 DWn mem 16 abs16 1101 011 MOVW An abs16 Anmem 6 abs16 1101 010A MOVW DWn HA DWn mem 16 HA 1001 010D MOVW gt 16 1001 011 MOVW imm8 DWm sign imm8 CDWm 0000 110d MOVW imm8 Am zero imm8 Am 0000 111a MOVW imm16 DWm Note Page refers to the corresponding page in the Instruction Manual imm16 5DWm AL uus o omm eo o o Boo RD o wl ajaja a o o m mi o o o m oo o s o o oo s mM Alm o e 1100 111d 1 48 sign extended 2 44 zero extended 3 d8 zero extended 4 5 6 A An a Am 8 sign extended 8 zero extended 141 Instruction Set Chapter 10 Appendices 101 00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag CodeCycle Re Machine Code Notes Pag VF ZF Size peat Expand 1 2 3 4
40. P10 to P14 Schmitt trigger input 40 Input high voltage Mos 0 8V 41 Input low voltage Vs 0 02 42 Input leakage current I VIN 0 to V 10 pA H Vppz5V Vin 1 5V 43 Input high current Lu Pull up resistor ON 30 100 300 pA 44 Output high voltage Vos Vhp 5V Ig 0 5mA 4 5 45 Output low voltage Vip 5V Ig 1 01 0 5 I O pin 7 P60 to P67 46 Input high voltage 1 0 8V 47 Input high voltage 2 V dio Vy 45 to 5 5V 0 Mop 48 Input low voltage 1 Vis 0 02 49 Input low voltage 2 Vi V o 4 5 to 5 5V 0 0 3 50 Input leakage current Li VIN 0 to V 10 pA 5 Vin 1 5V T x E 51 Input high current Piliup resistor ON 30 100 300 52 Output high voltage Nous 5V Ig 0 5mA 4 5 53 Output low voltage Mis Vhp 5V 1 1 0 0 5 VO pin 8 P70 to P71 54 Input high voltage 1 Viti 0 8V p 55 Input high voltage 2 Vis V o 24 50 5 5V 0 7V pp Von 56 Input low voltage 1 Mii 0 02 57 Input low voltage 2 Nas V op 4 5 to 5 5V 0 0 3 58 Input leakage current T VIN 010 10 pA Vpp 5V ViN 1 5V E E 59 Input high current Iu Pull up resistor ON 30 100 300 60 Input low current I 5 Vin 3 5V 30 100 300 zn Pull down resistor ON 61 Output high voltage Noui Vip 5V Ig 0 5mA 4 5 62 Output low voltage Vora Vip 5V 1 1 0 0 5 20 Electrical Characteristics C
41. Page X 3F59 Disables to use X 3F5A 9pisables to use X 3F5B 9pisables to use m X 3F5C pisables to use X 3F5D pisables to use X 3F60 pisables to use 3F61 Disables to use 9 9 2 7 2 6 TM2BC5 2 4 2 TM2BC2 2 1 2 0 2 82 2 Binary co pter2 e TM3BC7 6 TM3BC5 TM3BC4 TM3BC3 TM3BC2 TM3BC1 X 3F63 TM3BC 82 Binary coggter3 TM4B L7 TM4BCL6 5 TM4BCL4 TM4BCL3 2 1 X 3F64 e TM4BCL Binary counter 40 Lower 8 bits F TTM4BCH7 TM4BCH6 TM4BCH5 TMABCHATMABCH3 TMABCH2 TM4BCH1 TM4BCH0 X 3F65 TM4BCH 83 Binary counter4 Upper 8 bits TMAICL7 TM4ICL6 TM4ICL5 TM4ICL4 TM4ICL3 TM4ICL2 7 4611 TM4ICLO X 3F66 84 Input capture register Lower 8 bits TM4ICH6 TMAICH5 TM4ICH4 TM4ICH3 TM4ICH2 TM4ICH1 TMAICHO X 3F67 84 Input capture r gster Upper 8 bits TM5BC7 TM5BC6 TM5BC5 TM5BC4 5 3 5 2 TM5BC1 TM5BCO 68 TM5BC 84 Binary cou er 5 X 3F70 Disables to use X 3F71 Disables to use 20 7 20 6 TM20C5 20 4 TM20C3 20 2 TM20C1 20 0 X 3F72 9 M2OC 82 Compare register 2 TM30C7 TM30C6 5 TM30C4 TM3OC3 TM3OC2 TM3OCO X 3
42. TM4OCH TM4OCL register Timer Pulse Output Function Settings for the timer pulse output function are listed below 1 2 3 4 5 6 7 8 Binary counter 4 TM40UT 72 16 bit Timer Operation timer 4 Set the TM4EN flag of the timer 4 mode register TM4MD to 0 so that the count operation of timer 4 is stopped Set bit 4 of the port 1 output input mode register PIOMD to the special function pin setting Bit 4 of port 1 will be specified as the pulse output pin Use the TM4CK2 to 0 flags of the TM4MD register to select fosc fs 4 or fs 16 as the clock source Set the TM4PWM flag of the TM4MD register to 0 so that 16 bit timer operation is selected Set a value in compare register 4 TM40CL Set the TM4EN flag of the TM4MD register to 1 to start the timer When timer 4 begins operation binary counter 4 will count upward from X 0000 When the value of binary counter 4 matches that of the and TM40CL registers the timer 4 interrupt request flag is set and the binary counter 4 is reset to X 0000 and begins to count upward again Matches TM4OCL register s Figure 4 3 3 Timer Pulse Output Timing Chapter 4 Timer Functions ll Pulse Added Type PWM Output Function If bit 4 of port 1 is to be used as a PWM output pin set the P1DIR In
43. Timer Functions The upper 2 bits of the watchdog timer are cleared when the WDEN flag is set to 0 Therefore if WDEN flag is set to 0 when an uppermost bit of a watchdog timer is 1 WDT interrupt occurs depending on the timing of this clear the watchdog timer may be reset at 1 41 If the bit is to be repeatedly cleared and set at regular intervals those operations should be performed within 1 4 of the period 78 Watchdog Timer Operation 4 6 Watchdog Timer Operation 4 6 1 Overview The watchdog timer is controlled by the watchdog control register WDCTR and can be used for runaway program detection 4 6 2 Setup and Operation 1 Set the WDEN flag of the watchdog timer control register WDCTR to 1 to start the watchdog timer 2 Operate the watchdog timer by clearing the WDEN flag to 0 within the fixed amount of time T and then resetting the WDEN flag to 1 If the WDEN flag is not cleared a WDT interrupt will be generated after the fixed amount of time passes 3 When an illegal operation is detected the program encoded at the location of the WDT interrupt routine is executed T is set by the ROM option as fs 2 5 fs 2 fs 2 Illegal operation detection period vs WDEN clear period is shown by the following formula Illegal operation detection period WDEN clear period x 4 When software resetting is not triggered by WDT interrupt hardware resetting low level outpu
44. Upper 8 bits of A D pconversion data ibn MUX gt Sample amp hold 10 bit AN4 gt A D comparator AN5 n T Lower 2 bits of A D conversion data AN6 Vss fs 2 15 4 MUX 1 2 gt 15 8 fx x 2 1 6 MUX gt 1 18 Figure 6 1 1 A D Converter Block Diagram 114 Overview Chapter 6 A D Conversion Functions 6 2 A D Conversion The procedures for operating the A D conversion circuit are listed below 1 Set the ANCHS2 to ANCHSO flags of A D control register 0 ANCTRO to specify one of pins AN7 to ANO PA7 to as the analog input 2 Set the and flags of A D control register 0 to select the A D conversion clock Make this setting such that the period of the conversion clock which is based on the oscillator is greater than 800ns 3 With the ANSH1 and ANSHO flags of A D control register 0 set the sample and hold time Select a value for the sample and hold time that is suitable for the analog input impedance 4 Set the ANLADE flag of A D control register 0 to 1 so that current flows through Start the A D conversion after the the ladder resistors and the A D converter is on standby current flowing through the ladder Note Steps 1 to 4 above may performed all at the same time resistors stabilizes The time constant calculated time from the 5 Set the ANST flag of A D control register
45. V 2 Input clamp current SENS IC 500 to 500 3 Input pin voltage Vi 0 3 0 3 V 4 Output pin voltage 0 3 to 103 5 pin voltage 0 3 to V 0 3 V 6 P8 peak 30 7 Except P8 I peak 20 current Ole 8 All pins peak 10 mA 9 P8 I on avg 20 Average output 10 Other than P8 avg 15 current 9E 11 pins avg 5 12 Tolerable loss PD 400 mW 13 Ambient operating temperature T 40 to 85 C 14 Storage temperature T 55 to 125 G Note Applicable even for an interval of 100ms and GND to prevent from latchup does not damage a chip not guarantee the operation 2 Insert at least one bypass capacitor of 0 1uF or more between a power source pin Absolute maximum ratings indicate the allowable limit to which applied voltage Electrical Characteristics 13 Chapter 1 Overview 1 5 2 Operating Conditions Ta 40 to 85 22 01 5 5 V 0V Rating Parameter Symbol Conditions Unit MIN TYP MAX Supply voltage 1 fosc lt 20 0MHz 4 5 5 5 2 fosc 8 39MHz 2 7 5 5 __ Supply voltage pp V 3 during operation MS fosc lt 2 00MHz 2 0 5 5 4 Vins 32 768kHz 2 0 5 5 5 Voltage to maintain RAM data 5 STOP mode 1 8 5 5 Operating speed 6 tcl Vy 4 5 to 5 5V 0 100 7 tc2 2 7 to 5
46. bit count 5 5 1 5 0 5 SCOERE SCOTRI XC SCOMD1 i Select1 8 lock sourge selection B US 109 rec monitor request flag SCOFM1 SCOFMO a rM SCOPMO SCONPE 3F52 4 110 SCOMD2 Corro braka pecifies frame mode Specifies added bit SCOIOM SCOSBOM 5 05 SCOSBOS SCOSBIS 5 05 5 5 scoMp3 5 10 00 5 0 SelectSBT45electSBO CofitroISBISelectS ft pin connection selection pin format pin function input pin function SCOBSY SCOCMD SCOFEF 5 SCOORE 3 54 Status of Sdectsync Dekectfrarring Detect Detectoverun 112 serial bus seroalUART enr error enr SCOTRB7 SCOTRB6 SCOTRB5 SCOTRB4 SCOTRB3 SCOTRB2 SCOTRB1 SCOTRBO X 3F55 SCOTRB Serial interface 0 transmit receive shift register 107 SCORXB7 SCORXB6 SCORXB5 SCORXB4 SCORXB3 5 2 5 1 SCORXBO 107 X 3F56 5 Serial interface 0 receive data buffer X 3F57 Disables to use X 3F58 pisables to use Summary of Special Function Registers 151 Chapter 10 Appendices 152 Bit Symbol 9 Reference Agaress 3 55 7 Bite Bits Bits Bit2 Biti Bito
47. complete the SCOBSY flag of the SCOCTR register is cleared to 0 and the SCO transfer complete interrupt request flag is set to 1 The SCOTRI flag of the SCOMDI register is set to 1 After the transfer is complete the transfer bit count in the SCOLNG2 to 0 flags of the SCOMDO register will be changed Except in an 8 bit transfer count reset the transfer bit count at the time of the next reception When switching from reception to transmission set the SCOSBIS of the SCOMD3 register to 0 and then set the SCOSBOS flag to 1 Do not change both of these flags at the same time Chapter 5 Serial Functions When the serial port is enabled and the SCOCE 1 to 0 flags of the SCOMDO register are changed the transfer bit count in the SCOLNG2 to 0 flags of the SCOMDO register may by incremented Section 5 2 3 Serial Interface Transfer Timing If the start condition is enabled the SCOLNG2 to 0 flags of the SCOMDO register will be cleared when the start condition is received In this case the receive bit count is fixed at 8 bits The SCOSBTS flag of the SCOMD3 register must be set to 1 before setting the SCOSBIS flag of the 5 register to 1 If the internal clock is selected as the clock source after setting the SCOSBIS flag of the SCOMDS register to 1 write dummy data to the SCOTRB register If there is to be another reception write dummy data again to the SCOTRB register The SC
48. eerte dert endet thi 149 Contents 4 Chapter 1 Overview Chapter 1 Overview 2 Product Overview 1 1 Product Overview 1 1 1 Overview The MN101C00 series of 8 bit single chip microcomputers incorporate several types of peripheral functions This chip series is well suited for VCR MD TV CD LD printer telephone home automation pager air conditioner PPC remote control fax machine musical instrument and other applications The MN101CI17 has an internal 16 KB of ROM 512 bytes of RAM Peripheral functions include four sets of timers one set of serial interfaces an A D converter and remote control output The configuration of this microcomputer is well suited for applications as a system controller in a VCR selection timer CD player MD or portable terminal With two oscillation systems max 20 MHz 32 kHz contained on the chip of 48 pin QFP package the system clock can be switched between high and low speed When the oscillation source fosc is 8 MHz a machine cycle lasts for 250 ns When fosc is 20 MHz a machine cycle is 100 ns The package are available with three types of 42 pin SDIP 44 and 48 pin QFH 1 1 2 Product Summary This manual describes the following models of the MN101C11 series These products have identical functions Table 1 1 1 Product Summary Model ROM Size RAM Size Classification MNI01C115 8 KB 256 bytes Mask ROM version MNIO
49. is output in synchronization with the rising edge of the clock 5 00 Figure 5 2 6 Synchronous Serial Transmit Receive Timing data is received at the falling edge and transmitted at the rising edge 100 Synchronous Serial Interface Chapter 5 Serial Functions 5 3 Half duplex UART Serial Interface 5 3 1 Overview Setup and operation of UART transmission and reception are described below 5 3 2 Setup and Operation Transmission 1 Select UART by setting the SCOCMD flag of the serial interface 0 control register SCOCTR to 1 When the serial port is enabled 2 Specify the first bit to be transferred MSB first or LSB first with the andthe SC0CET dU 21 the SCOMDO register are SCODIR flag of the serial interface 0 mode register 0 SCOMDO toggled the transfer bit count 3 Select the valid edge of the clock signal with the SCOCEI to 0 flags of the may change SCOMDO register 4 Select the clock source with the SCOCKI to 0 flags of serial interface 0 mode register 1 SCOMD1 5 Setthe SCOCKM flags of the SCOMDI register to 1 to divide the clock The TXD pin goes to a high source frequency by 8 level after transmission is 6 Set the SCONPE flag of the serial interface 0 mode register 2 SCOMD2 to complete enable or disable parity Setting the SCOFM of the SCOMD2 register to frame mode automatically sets the SCOLNG2 to 0 flags of the SCOMDO register After the transfer is complete the
50. main text An explanation of terminology is also included Precautions and warnings Precautions are listed in case of lost functionality or damage Be sure to read How to Read This Manual 2 Finding Desired Information This manual provides four methods for finding desired information quickly and easily 1 2 3 4 Consult the index at the front of the manual to locate the beginning of each section Consult the table of contents at the front of the manual to locate desired titles Consult the list of figures at the front of the manual to locate illustrations and charts by title name Chapter names are located at the top outer corner of each page and section titles are located at the bottom outer corner of each page Related Manuals The following manuals are also available from Panasonic as part of the MN101COO series 101 00 Series LSI Manual Device Hardware Description MN101C00 Series Command Manual Command Descriptions MN101C00 Series Cross Assembler User s Manual Assembler Syntax and Entry Methods MN101C00 Series C Compiler Users Manual Operation C Compiler Installation Startup Option Descriptions MN101COO Series C Compiler Users Manual Language C Language Syntax Description MN101C00 Series C Compiler Users Manual Library C Compiler Standard Library Description MN101C00 Series C Source Code Debugger User s Manual C Source Code Debugg
51. msb temp CF BSET io8 bp mem8 IOTOP i08 amp bpdata PSW 1 meme8 IOTOP io8 bp BSET abs8 bp mem8 abs8 amp bpdata PSW 0 ole 1011 93 1 mem8 abs8 bp BSET abs16 bp mem8 absi6 amp bpdata PSW 0 1100 94 1 mem8 abs16 bp BCLR BCLR io8 bp mem8 IOTOP io8 amp bpdata PSW 0 e 0 e 1000 95 0 mem8 IOTOP io8 bp BCLR abs8 bp mem8 abs8 amp bpdata PSW 0e 1011 95 0 mem8 abs8 bp BCLR abs16 bp mem8 absi6 amp bpdata PSW 0 e 0 e 1100 96 0 mem8 abs16 bp BTST BTST imm8 Dm Dm amp imma8 PSW 01 oe 0000 97 BTST abs16 bp mem8 absie amp bpdata PSW 0 e 0 e 1101 97 Branch instructions PC 3 d4 label H PC 1001 PC 4 d7 label H PC PC 4 PC 1000 5 PC 5 d11 label H PC 1001 PC 3 d4 label H PC 1001 PC 4 d7 label H PC PC 4 PC 1000 if ZF 1 5 if ZF 0 PC 5 d11 label H PC 1001 if VF NF 0 PC 4 d7 label sHPC if VFANF 1 PC 4PC 1000 if VF NF 0 PC 5 d1 t label sHPC if VFANF 1 PC 5PC 1001 if CF 0 PC 4 d7 label H gt if CF 1 PC 4 PC 1000 if CF 0 PC 5 d1 1 label H if CF 1 5 1001 if CF 1 PC 4 d7 label H if CF 0 4 1000 if CF 0 5 if CF 1 PC 5 d1 1 1001 if VE NF 1 PC 4 07 label
52. pointer SP contents are update SP 6 SP 2 handy address register is pushed on to the stack HA upper byte gt SP 5 HA lower byte SP 4 3 program counter PC return address contents are pushed on to the stack PC bit 18 to bit 17 bit 0 SP 3 PC bit 16 to bit 9 SP 2 PC bit 8 to bit 1 SP 1 4 The PSW is pushed on to the stack PSW SP 5 xxxLVn of the accepted interrupt is copied to IM of the PSW Interrupt level IM 6 Execution branches to vector table Z 0 New SP PSW Low after interrupt is accepted ET 16109 18 17 Address 7 to 0 15108 Old SP Hen before interrupt is accepted Figure 2 4 1 Stack Status during an Interrupt instructions in the program to save these values as necessary on the a Since the contents of data and address registers are not saved use PUSH stack Interrupts 31 Chapter 2 Basic CPU Functions Operation when Returning from Interrupt After the program POPs the register and other values saved by the interrupt service routine an RTI instruction is implemented to return to the program that was being executed when the interrupt was received The processing sequence for the return from interrupt instruction RTI is listed below The processor status word PSW is pulled from the stack SP 2 program counter PC return address is pulled f
53. ports The value of data at the pins can be input by reading these registers These are read only registers 0 Pin is low 1 Pin is high Input and output registers are mapped to separate addresses To use these ports for I O configure them as I O ports in the PnOMD PnIMD registers described in this section Direction Control Registers PnDIR registers 0 Input mode 1 Output mode These registers set the port for use as an input or output Pull up Pull down Resistor Control Registers PnPLU registers These register settings determine whether internal pull up resistors are added to the ports 0 No pull up pull down resistor 1 Pull up Pull down resistor PnPLUD registers These register settings determine whether internal pull up or pull down resistors are added to the ports 0 No pull up pull down resistor 1 Pull up Pull down resistor Port Control Registers 45 Chapter 3 Port Functions Port Output Input Mode Registers 1 e PnOMD PnIMD registers These register settings determine whether the port pins P10 to P14 to 5 are used Setting the PAIMD register prevents unnecessary current from flowing in a pin when an intermediate voltage analog must be set voltage is applied to the pin as I O ports or as special function pins dual function If the special dual functions used the PnDIR PnPLU P
54. sealed in a ceramic package that has a window written data can beerased by illumination with ultraviolet light Plastic package uses a 42 pin shrink DIL package 44 pin flat package and 48 pin flat package Ceramic packages uses a 42 pin shrink DIL package and 44 pin flat package Setting the EPROM version to EPROM mode halts microcomputer functions and the internal EPROM can be programmed Refer to the EPROM mode pin diagram in figure 9 4 3 to 5 The specification for writing to the internal EPROM are the same as for a general purpose 256Kbit EPROM Vpp 12 5V tpw 0 2ms Therefore by replacing theEPROM Version s 42 pin socket with a special 28 pin socket adapter supplied by Panasonic having the same configuration as a normal EPROM a general purpose EPROM writer can be used to perform read and write operations The EPROM Version is described on the following items Cautions on use of the internal EPROM Erasing written Data in Windowed Package PX AP101C11 SDC PX AP101C11 FBC Characteristics of EPROM Versions Writing to the Microcomputer with Internal EPROM Cautions on operating a ROM writer Option bit Connections of a writing adaptor Chapter 8 Appendices 8 1 2 Cautions on Use EPROM Versions differs from the MN101C11 in some of its electrical characteristics The user should be aware of these differences 1 To prevent data from being erased by ultraviolet light after a program is written affix seal
55. subject to change Before a using this product please obtain product specifications from the sales office External Dimensions 25 Chapter 1 Overview Package code QFH048 P 0707 Unit mm SEATING PLANE Material Epoxy Resin Lead Material Fe Ni 42 Alloy Lead Finish Method Soldering dip Figure 1 7 3 48 QFH using this product please obtain product specifications from the sales The external dimensions of the package are subject to change Before 1 office 26 External Dimensions Chapter 2 Basic CPU Functions 27 Chapter 2 Basic CPU Functions 28 Overview Address Space 2 1 Overview Basic CPU functions in conformance with the 101 00 series manual architecture manual This chapter describes specifications unique to the MN101C1 17 115 2 2 Address Space 2 2 1 Memory Configuration A X 00000 Abs 8 addressing 256 bytes access area Internal 512 bytes X 00100 RAM space Data Y Y X 00200 256 bytes Special function registers Y A A X 04000 Interrupt 128 vector table X 04080 Subroutine 64 bytes vector table 16 KB Y Internal X 040C0 ROM space Instruction code table data Y X 07FFF Y Figure 2 2 1 Memory Map Differs depending upon the model 101 115 Internal RAM 00000 to X 000FF 256 bytes Internal ROM 04000 to X O5FFF 8 KB MNIOICP117 Internal RAM X 00000 to X 00
56. the pulse added method a 1 bit output is appended to the basic component of the 8 bit and P1PLU registers PWM output Precise control is possible based on the number of PWM repetitions 256 times to which this bit is appended Settings for the pulse added type PWM output function are listed below 1 Set the TM4EN flag of the timer 4 mode register TM4MD to 0 to stop the count operation of timer 4 2 Set bit 4 of the port 1 output input mode register PLOMD to the special function pin setting Bit 4 of port 1 will be specified as the PWM output pin 3 Use the 2 to 0 flags of the register to select fosc 15 4 or fs 16 as the clock source The period of the output waveform is determined based on the clock source 4 Set the TM4PWM flag of the TM4MD register to 1 so that PWM operation is selected 5 Set a value in the lower 8 bits of compare register 4 TMAOCL The high interval of the output waveform is determined based on the value of the lower 8 bits of compare register 4 TM4OCL 6 Set the position of the added pulse in the upper 8 bits of compare register 4 TMAOCH PWMA output is fixed at L with T Setthe TM4EN flag of the TM4MD register to 1 to start the timer Rad EA bits TM40CL of compare register 8 When timer 4 begins operation binary counter 4 will count upward from X 00 Use of timer 4 at PWM mode 9 A high level signal is output from the port beginning when b
57. timer 4 75 Chapter 4 Timer Functions 4 4 8 bit Timer Operation timer 5 4 4 1 Overview Timer 5 is an 8 bit timer that can have fosc fs 4 fx or time base output as its clock source 4 4 2 Operation Timer Operation Settings for timer operation are listed below When servicing an interrupt reset 1 Set TMSCLRS flag of the timer 5 mode register TMSMD to 0 die S request tag 2 Use the TM5CK3 to 1 flags of the TM5MD register to select fosc fs 4 fx efore starting timer 5 synchronized fx time base timer output or time base timer synchronized output as When choosing either time base timer output or time base timer the clock source synchronized output for the timer 5 3 Set a value in compare register 5 5 At this time if the TMSCLRS flag is clock source the time base must 0 binary counter 5 will be initialized to X 00 be set up 4 Binary counter 5 5 counts upward from 00 During a count operation be 5 When the value of binary counter 5 matches that of the TMSOC register the timer 5 careful if the value set in 5 interrupt request flag is set the binary counter is reset to X 00 and counting begins is smaller than the value of binary counter 5 since the count up operation will continue until overflow occurs again If the TM5CLRS flag of the TM5MD register is set to 0 binary If fx input is selected as the clock 5 will be in
58. to stop the count operation of timer 2 Set the TM2CK2 to 0 flags of the TM2MD register to select fs fs 4 fx or synchronized fx as the clock source Set the TM2PWM flag of the TM2MD register to 0 so that normal timer operation is selected Set a value in compare register 2 TM2OC Set the TM2EN flag of the TM2MD register to 1 to start the timer When timer 2 begins operation binary counter 2 TM2BC will count upward from X 00 When the value of binary counter 2 matches that of the TM2OC register the timer 2 interrupt request flag is set and the binary counter 2 is reset to X 00 and begins to count upward again Write to registers TM4OCH TM4OCL Figure 4 2 1 Binary Counter 2 2 Count Timing Chapter 4 Timer Functions When servicing an interrupt reset the timer 2 interrupt request flag before starting timer 2 During a count operation be careful if the value set in TM20C is smaller than the value of binary counter 2 since the count up operation will continue until overflow occurs If fx is to be selected as the clock source and the value of binary counter 2 is to be read during operation select synchronized fx in order to avoid reading data that may be incomplete during count up transitions However with synchronized fx it is not possible to return from STOP HALT modes If the TM2EN flag of TM2MD register is changed simultaneously wi
59. v s et lt 260 A 1 Y 1ndino I E indui pine euas OUIZINL lt 4 4 Andino P _ _ lt X ndino Andino OI N1 m HOSEINL C 5 8 I Jejunoo 9 8 Jejunoo 9 8 Y TM DOENL lt s 295 ejeduio NIENL JejsiBoJ L 1 WMdENL ZXOEINL OMOEWL Figure 4 1 1 Timers 2 3 Block Diagram 57 Overview Chapter 4 Timer Functions 112171 010171 GIATIA L A A 46 cOul LLL AM lt Y HOIVINL 19 91 lt 008 OILS uoneziu 1159 Y m lt zi Y Andino pOIO L 8 TOBPWL sS lt err PS lt poppe esing 3i 5 19 91 e u lt lt 1 e yN 4
60. 0 Fig 1 5 3 ns 22 Fall time twf 1 5 0 External clock input 2 XI XO is unconnected 2 23 Clock frequency fx 32 768 100 24 High level pulse width twh2 3 5 Fig 1 5 4 us 25 Low level pulse width twl 2 3 5 26 Rise time twr 2 20 Fig 1 5 4 ns 27 Fall time twf2 20 Setthe clock duty ratio to 45 to 55 2 Applicable only for 48 pin QFH package Chapter 1 Overview Electrical Characteristics 15 Chapter 1 Overview aS cH aste assaka 0 9 9 x twh1 gt twl1 gt twr picky Figure 1 5 3 OSC1 Timing Chart M E 0 9Voo Die a IAS ln an Ve AS ee en 0 1Voo twh2 gt 2 twr2 twf2 Figure 1 5 4 XI Timing Chart 16 Electrical Characteristics 1 5 3 DC Characteristics 40104859 V 2 0to55V V 0V Rating Unit Parameter Symbol Conditions MIN Supply current no load at output fosc 20 0MHz V__ 5V 1 Supply current DD 25 60 d mA 2 during operation fosc 8 39MHz V 5V 10 25 E 3 d fx 32 768kHz V 3V 100 4 2 fx 32 768kHz V 3V 8 Supply current during HALT mode d Ta 25 C PR 5 lox 40 to 85 C 18 pA 6 25V Ta 25 C 0 2 Supply current during STOP mode p pP 7 op 40 to 85 C 0 20 Note
61. 005 lt Jejunoo lt 4 1 Ee FRE 10109190 pueddy 0 n UOIpuoo 04102 949221 yeaig Y Y Y A X 00655101 2 1516 yl e 00d LaX L 008S ye lt 18 901 HIUS a n 9109 g Jejnq 8 dois gx409S 3800s 8 101026 1IN300S WO8S029S 08 dVMS OWd00S 51850205 3dN09S 8 8 18195005 caW09S 59 095 04 0185 LOd axu oias 00d 008S Figure 5 1 1 Serial 0 Block Diagram 93 Overview Chapter 5 Serial Functions Section 5 2 3 Serial Interface Transfer Timing 94 Synchronous Serial Interface 5 2 Synchronous Serial Interface 5 2 1 Overview A serial interface begins operation when data is written to the shift buffer A bit counter is incremented at each 1 bit transfer The transfer is complete when the counter overflows Bit transfers of an arbitrary 1 to 8 bits can be performed The transfer bit count must be set before performing the transfer 5 2 2 Setup and Operation Transmission 1 2 3 4 5 6 Select the synchronous serial interface by setting the SCOCMD flag of the serial interface 0 control register SCOCTR to 0 Select the transfe
62. 1 Chapter 1 Overview Option 1 6 Option 1 6 1 ROM Option The product equipped with this LSI or an EPROM with this LSI controls the oscillation mode after resetting as well as the runaway detection watchdog timer using bits 2 to 0 of the last address of the built in ROM Option bits 6 5 4 3 2 1 0 PKG PKG gu MDSEL2WDSEL NSSTRT NSSTRT Selection of oscillation mode after resetting 0 SLOW mode 1 NORMAL mode WDSEL2 WDSEL1 Watchdog timer cycle setting 0 16 219 1 fs 2 8 1 15 220 PKGSEL2 PKGSEL1 Packages SDIP042 P 0600 0 QFP044 P 1010 1 QFH048 P 0707 Figure 1 6 ROM Option Address X 7FFF 1 6 2 Option Form Date SE No Chapter 1 Overview Model Name 101 Customer Approval 1 Oscillation mode Type A Type B Note Type A Operation begins from the reset cycle in the NORMAL mode Type B Operation begins from the reset cycle in the SLOW mode 2 Watchdog timer period setting Detection Period Selection 5 216 5 218 5 220 Not used 3 Package selection Package Selection SDIP042 P 0600 QFP044 P 1010 48 0707 Contents of mask option are subject to change a When placing an order for masks plea
63. 1 ANCTRI to 1 to start the A D ladder resistance max 80 kQ conversion and the external bypass capacitor 6 After the sample and hold time set in step 3 the sampled A D conversion data is connected between Vdd and Vss sequentially compared to determine its value beginning with the MSB should be used as the criteria for 7 When the A D conversion is complete the ANST bit is cleared to 0 and conversion ma walt tme results are stored in A D buffers ANBUFO 1 At the same time an A D complete interrupt request ADIRQ is generated Tap 4 1 2 3 4 12 ANST A D conversion start A D conversion complete Ts A gt Sampling Hold Bit 9 Bit 8 Bto comparison comparison comparison Determine Determine Determine Determine bit 9 value bit 8 value bit 1 value bit 0 value AD interrupt n oq Figure 6 2 1 A D Conversion Timing A D Conversion 1 15 Chapter 6 A D Conversion Functions 116 A D Converter Control Registers A D converter 1 Use a maximum input pin impedance of 500 with an external capacitor C that is minimum 1 000pF and maximum 2 Take the RC time into consideration when setting the A D conversion interval 3 Changing the output level of the microcomputer or switching peripheral circuitry on or off when the A D converter is in use may cause the analog input pin or current pin to fluctuate resulting in a loss
64. 10 7 8 0011 1111 bp lt abs 16 gt dii 127 JMP JMP An 0 PC 17 16 An PC 15 0 0 PC H 0010 0001 00A0 128 JMP label abs18 label H PC 0011 1001 abs 18b 15 5 128 JSR JSR An SP 3 gt SP PC 3 bp7 0 gt mem8 SP PC 3 bp15 8 gt mem8 SP 1 PC 3 H mem8 SP 2 bp7 0 gt mem8 SP 2 bp6 2 PC 3 bp17 16 mem8 SP 2 bp1 0 0 PC bp17 16 An PC bp15 0 0 PC H 0010 0001 00 1 129 JSR label SP 3 gt SP PC 5 bp7 0 gt mem8 SP PC 5 bp15 8 gt mem8 SP 1 PC 5 H mem8 SP 2 bp7 0 gt mem8 SP 2 bp6 2 PC 5 bp17 16 mem8 SP 2 bp1 0 PC 5 d12 label H PC 0001 000H di2 3 129 JSR label SP 3 gt SP PC 6 bp7 0 gt mem8 SP PC 6 bp15 8 gt mem8 SP 1 PC 6 H mem8 SP 2 bp7 0 gt mem8 SP 2 bp6 2 PC 6 bp17 16 mem8 SP 2 bp1 0 PC 6 d16 label H PC 0001 001H di6 44 130 JSR label SP 35SP PC 7 bp7 0 mem8 SP PC 7 bp15 8 gt mem8 SP 1 PC 7 H mem8 SP 2 bp7 0 gt mem8 SP 2 bp6 2 PC 7 bp17 16 mem8 SP 2 bp1 0 abs18 label H PC 0011 1001 1aaH abs 18b 15 0 5 130 JSRV tbl4 SP 35 SP PC 3 bp7 0 mem8 SP 3 6 15 8 8 1 PC 3 H mem8 SP 2 bp7 0 8 2 6 2 PC 3 bp17 16 mem8 SP 2 bp1 0 mem8 x 004080 tbl4 lt lt 2 PC bp7 0 mem8 x 004080 tbl4 lt lt 2 1 PC bp15 8
65. 10 0011 0011 di 3 109 if CFIZF 0 PC 6 PC BNC label if NF 0 PC 5 d7 label H PC 5 3 4 0010 0010 0100 lt d7 2 110 1 5 BNC label if NF 0 PC 6 d11 label H3PC 6 3 4 0010 0011 0100 dii 3 110 1 6 BNS label NE 1 PC 5 d7 label H PC 5 3 4 0010 0010 0101 d7 2 111 0 5 BNS label if NF 1 PC 6 d11 label H PC 6 3 4 0010 0011 0101 dil 3 111 0 6 BVC labe if VF 0 PC 5 d7 label H PC 5 3 4 0010 0010 0110 lt d7 2 112 if VF 1 PC 5PC BVC label if VF 0 PC 6 d11 label H PC 6 3 4 0010 0011 0110 lt d11 112 if VF 1 PC 62PC BVS label VF 1 PC 5 d7 label H PC 5 3 4 0010 0010 0111 d7 2 113 if VF 0 PC 5 PC BVS label VF 1 PC 6 d11 label H PC 6 3 4 0010 0011 0111 dii 113 if VF 0 PC 6 PC BRA label PC 3 d4 label H PC 313 1110 111H lt d4 gt 1 114 BRA label PC 4 d7 label H PC 413 1000 1001 d7 H 2 114 BRA label PC 5 d11 label H PC 5 3 1001 1001 lt 911 3 115 CBEQ CBEQ imm8 Dm label if Dm imm8 PC 6 d7 label HoPC e e 6 3 4 1100 10Dm 8 gt 47 2 116 if Dm4imm8 PC 62PC CBEQ imm8 Dm label if Dm imm8 PC 8 d11 label H PC e
66. 1FF 512 bytes EP ROM X 04000 to X O1FFF 16 KB Chapter 2 Basic CPU Functions 2 2 2 Special Function Registers Memory control register MEMCTR is a 4 bit register which set up the base Table 2 2 1 Register Map 0 1 2 3 4 5 6 7 8 9 A B C D E F O3FOX CPUM MEMCTR DLYCTR CPU mode memory control 1 POOUT PIOUT P2OUT P6OUT P7OUT P8OUT Port output 03F2X POIN P1IN P2IN P6IN P7IN P8IN PAIN Port input PODIR P1DIR P6DIR P7DIR P8DIR P1OMD PAIMD mode control 3 POPLU P1PLUIP2PLU P6PLUJP7PLUD P8PLU PAPLUD FLOATI Resistor control O3F5X SCOMDO SCOMD1 SCOMD2 SCOMD3 SCOCTRISCOTRBISCORXB Serial interface control OSF6X TM2BC TM3BC TM4BCL TM4BCH TMAICL TM4ICH OSF7X TM20C TM3OC TMAOCL TIMOCH 50 Timer control OSF8X TM2MD TM3MD TMAMD TM5MD O3F9X ANCTRO ANCTRI ANBUFO ANBUFI A D control Reserved O3FDX OSFEX NMICR IRQOICRIIRQ1ICR TM2ICR TBICR SCOICRI ADICRIIRQ2ICR TMSICRITMAICR Interrupt control O3FFX Address Space 29 Chapter 2 Basic CPU Functions 30 MEMCTR Bus Interface 2 3 Bus Interface 2 3 1 Overview The MN101C117 unlike other MN101C series microcomputers does not support memory expansion mode and processor mode 2 3 2 Control Registers The memory control register is a four bit
67. 2OUT flag will be 1 Releasing the Reset When the RST pin changes from low to high an internal 15 bit counter begins counting at the oscillation clock frequency The interval from when this counter begins counting until it overflows is known as the stabilization wait time After waiting for this amount of time the internal reset is released and the CPU begins operation RST pin Peripheral register CPU 1 1 internal reset 1 1 1 1 1 1 1 1 1 1 1 T 1 Oscillation stabilization wait time 21 fosc Figure 2 5 2 Reset Release Sequence When returning from the STOP mode is terminating the software can use the DLYCTR register to select an oscillation stabilization wait time of 0 27 fosc 2 or 2 fosc Chapter 3 Port Functions 37 Chapter 3 Port Functions 3 1 Overview A total of 39 pins on the MN101C117 including those shared with special function pins are allocated for the 7 ports of PO to P2 P6 to P8 and PA Each port is assigned according to the special function register area in memory I O ports are operated in byte or bit units in the same way as RAM For each I O port the PnOUT register port n output register that sets the output value is assigned to memory address 1 and the PnIN register port n input register from which the input value is monitored is assigned to memory address X 3F2n This I O control is v
68. 48 gt dii 3 120 if mem8 abs8 imm8 PC 10 PC imm8 abs16 label if mem8 abs16 4imm8 PC 11 d7 label sH3PC e e e 11 7 8 0011 1101 1110 abs 16 gt gt lt d7 2 121 if mem8 abs16 imm8 PC 1 1 2PC CBNE imm8 abs16 label itimem8 abs16 imm8 PC t2 dti abe4H2PC 12 7 8 0011 1101 1111 abs 16 gt lt gt dii 3 121 if mem8 abs16 imm8 PC 12 PC TBZ TBZ abs8 bp label if memB abs8 bp 0 PC 7 d7 label H PC 0 0 6 7 6 7 0011 0000 Obp abs 8 d7 2 122 if mem8 abs8 bp 1 PC 7 PC TBZ abs8 bp label if mem abs8 bp 0 PC 8 dli labe H2PC 0 e 0 e 8 6 7 0011 0000 abs 8 dii 3 122 if mem8 abs8 bp 1 PC 8 PC Note Page refers to the corresponding page in the Instruction Manual 1 44 sign extended 2 d7 sign extended 3 411 sign extended 144 Instruction Set 101 00 SERIES INSTRUCTION SET Chapter 10 Appendices Group Mnemonic Operation Affected FI ag VF ZF il Re peat Expand 1 2 Machine Code 4 5 6 7 8 9 10 Notes Pag 11 TBZ BZ io8 bp label 0 PC 7 d abel H PC if mem8 IOTOP io8 bp 1 PC 7 gt PC 0 6 7 0011 0100 lt io8 gt 07 1 123 BZ io8 bp label i memB OTOP i
69. 5 Bit4 Bit3 Bit2 Bit1 Bit 0 Page X 3F24 9Disables to use X 3F25 isables to use _ P6IN7 P6IN6 P6IN5 P6INA P6IN3 P6IN2 P6IN1 P6INO x ar26 9 410 45 Port 6 input 0 P7INO X 3F27 P7IN Pot79 410 45 input P8IN7 P8IN6 P8IN5 P8INA P8IN3 P8IN2 P8IN1 P8INO X 3F28 Port 8 input 410 45 PAIN7 PAIN6 PAIN5 PAIN4 PAIN3 PAIN2 PAIN1 PAINO 2 PAIN 411 45 Port A input PODIR6 PODIR2 PODIR1 PODIRO PODIR 411 45 X 3F30 Port 0 I O direction control D P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIRO F DIR Port 11 0 direction control 45 X Disables to use X 3F34 isables to use X 3F35 Disables to use P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIRO 411 45 X 3F36 P6DIR Port 61 0 direction control D P7DIRO X 3F37 P7DIR Pot7 0 410 45 direction control P8DIR7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIRO X 3r38 P8DIR Port 8 direction control 410 45 P14TCO P13TCO P12TCO 10 4114 X 3F39 1 port S pecial function pin control 46 PAAIN5 PAAIN4 PAAIN3 PAAIN2 PAAIN1 PAAINO 3F3A PAIMD 411 46 port S pecial function pin control 0 X Disables to use POPLU6 POPLU2 POPLU1 POPLUO 40 POPLU 411 45 xara 9 Port 0 pull up resistor ON OFF control 0 PIPLUA PIPLU3 PIPLU2 P1PLU1 PIPLUO P1PLU 42 45 X 3F41 Por
70. 5V 0 238 us Instruction execution time 8 tc3 2010 5 5V 1 00 9 4 V 2 0 to 5 5V 40 125 Crystal oscillator 1 Fig 1 5 1 10 Crystal frequency fxtal 1 V 4 5 to 5 5V 1 0 20 0 MHz 11 C 20 External capacitors pF 12 20 12 13 Internal feedback resistor RF10 700 Crystal oscillator 2 Fig 1 5 2 14 Crystal frequency fxtal 2 32 768 kHz 15 C 20 __ External capacitors pF 16 C 20 22 17 Internal feedback resistor RF20 4 0 Note Only for 48 QFH package totu t OSCI is the CPU clock cl t XI is the CPU clock OSCI XI Rei somo xtal Lr Typ MNI101C OSC2 CI2 D 22 C21 gt The instruction cycle is twice clock cycle instruction cycle is four times the clock cycle The feedback resistor is built in The feedback resistor is built in Figure 1 5 1 Crystal Oscillator 1 Figure 1 5 2 Crystal Oscillator 2 1 14 Electrical Characteristics Rating Parameter Symbol Conditions Unit MIN TYP MAX External clock input 1 OSC1 OSC2 is unconnected 18 Clock frequency Toe 1 0 20 0 MHz 19 High level pulse width twh 1 20 0 30 0 Fig 1 5 3 ns 20 Low level pulse width twl 1 20 0 30 0 21 Rise time twr 1 5
71. 7BF MN101CP117HP top view No 1 Pin 52297 0 127 PX AP101C11 SDC top view PX AP101C11 FBC side view Figure 8 1 1 Mount on the writing adapter and position of No 1 pin 134 EPROM Versions Chapter 8 Appendices ROM writer Selection The device names should be set up as listed below Table 8 1 2 Device selection Equip name Vendor Device name Remarks Pecker30 Avarl Data Hitachi 27C256 1890A Minato Electronics Hitachi 27 256 Lab Site Data VO Hitachi 27256 Do not run ID check and pin connection inspection The above settings are based on the standard samples When you use the other equipment than the ones listed contact the nearest semiconductor design center Refer to the sales office table attached at the end of the manual EPROM Versions 125 Chapter 8 Appendices 136 EPROM Versions 8 1 6 Cautions Operating the ROM Writer Cautions on operating the ROM writer 1 The Vpp programming voltage for the EPROM versions is 12 5V Programming with a 21 volt ROM writer can lead to damage The ROM writer specifications must match those for standard 1 megabit EPROMS Vpp 12 5V V tpwz0 2ms 2 Make sure that the socket adapter matches the ROM writer socket and that the chip is correctly mounted in the socket adapter Faulty connections can lead to damage 3 After clearing all memory of the ROM writer load the program Write the data X FF on the address 0000 to
72. BUF1 This register stores the upper 8 bits of the A D conversion results 7 6 5 4 3 2 1 0 ANBUF1 _ 17 ANBUF16 ANBUF15 ANBUF14 ANBUF13 ANBUF12 ANBUF1 1 ANBUF10 at reset XXXXXXXX Figure 6 3 4 A D Buffer 1 ANBUF1 X OSF93 120 A D Converter Control Registers Chapter 7 Zero Cross 7 Circuit Noise Filter 121 Chapter 7 Zero Cross Circuit Noise Filter 7 1 Overview The P21 SENS pin is the input pin for the AC zero cross detection circuit The AC zero cross detection circuit outputs a high level when the input is at an intermediate level and a low level at all other times P21 IRQ1 SENS 122 Overview FLOAT1 P7RDWN PARDWN P211M AC zero cross gt P21 input IRQ1 detection circuit MUX to noise filter See figure 7 3 1 p Figure 7 1 1 P21 Input Circuit Block Diagram Chapter 7 Zero Cross Circuit Noise Filter 7 2 AC Zero Cross Circuit Operation 7 2 1 Setup and Operation Settings for zero cross circuit operation are listed below 1 Set the REDGI flag of the IRQIICR register to select the valid edge for IRQI 2 Setthe NFIEN and to 0 flags of the NFCTR register to set the noise filter and its sampling clock 3 With the P21IM flag of the FLOATI register set the P21 pin to zero cross detection 4 An IRQI interrupt is generated b
73. CEO flag is 0 data reception is synchronized to the opposite polarity edge of the transmit data edge When the SCnCEO flag is 1 data reception is synchronized to the same polarity edge as the transmit data edge Table 5 2 1 Serial Data Input Edge and Output Edge serial interface 0 SCOCEO SCOCE1 Receive Data Input Edge Transmit Data Output Edge 0 0 1 Y 0 1 Y 1 1 0 y y 1 1 Chapter 5 Serial Functions Synchronous Serial Interface 99 Chapter 5 Serial Functions When serial interface 0 is used for simultaneous transmission and reception set the 5 and SCnCEI flags of the SCnMDO register to 00 or 01 so that the reception data input edge is opposite in polarity to the transmit data output edge Also the polarity of the reception data input edge is opposite polarity of the transmit data output edge of the other device 1 1 4 1 1 SBTO d Data is input in synchronization with the rising edge of the clock 5 0 C 7 Data is output in synchronization with the falling edge of the clock SBOO Figure 5 2 5 Synchronous Serial Transmit Receive Timing data is received at the rising edge and transmitted at the falling edge 1 1 1 1 2 J Data is input in synchronization with the falling edge of the clock SBIO Data
74. COMD1 7 6 5 4 3 2 1 0 SCOMD1 SCOCKM SCOCK1 71221 scoentjscorn at reset X00000 Chapter 5 Serial Functions SCOTRI Transmit receive interrupt request flag 0 Transmit interrupt request Receive interrupt request SCOERE Error monitor 0 No error 1 Error Break SCOBRKF reak status receive monitor 0 Data 1 Break SCOCK1 SCOCKO Clock source fs 2 fs 4 fs 16 0 0 1 1 0 1 0 1 BC3x1 2 1 2 of timer 3 overflow SCOCKM Divide clock frequency by 8 0 Do not divide by 8 1 Divide by 8 An external clock can be selected as the clock source by setting the SBTO pin to the input mode Figure 5 4 4 Serial Interface 0 Mode Register 1 SCOMD1 X 03F51 R W Serial Interface Control Registers 109 Chapter 5 Serial Functions 3 Serial interface 0 mode register 2 SCOMD2 7 6 5 4 3 2 1 0 SCOMD2 scr SCONPE Parity enable 0 Parity enabled 1 Parity disabled Added bit specification SCOPM1 SCOPMO Transmission Reception Normally add 0 Check for 0 Normally add 1 Check for 1 Add odd parity Check for odd parity gt gt gt Add even parity Check for even parity SCOFM1 SCOFMO Frame mode spec
75. F73 TMC 82 Compare register 3 TM4OCL7 TM4OCL6 TM4OCL5 TM40CL4 TM4OCL3 TM40CL2 TM4OCL1 TM40CLO X 3F74 83 Compare register 40 Lower 8 bits Summary of Special Function Registers Chapter 10 Appendices BitSymbol 4 i Reference Address Register Bit 7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit 1 Bit 0 Page X 3FEO Disables to use WDIR 34 request flag IRQOLV1 IRQOLVO IRQOIE IRQOIR X 3FE2 IRQOICR Interrup level flag for Extemal interupt Interupt Interrupt 34 extemal interrupt valid edge enable flag request flag IRQILV1 IRQILVO REDG1 IROMR X 3FE3 9 IRQIICR Interruptlevel Exemalinienu Interrupt Intenupte 34 for extemal interrupt valud SEE enable ege request X 3FE4 Disables to use X 5 Disables to use TM2LV1 TM2LVO TM2IE TM2IR X 3FE6 TM2ICR Interrupt level f foro interrupt Interrupt 35 timer 2 interrupt enable flag request flag TBLV1 TBLVO TBIR X 3FE7 9 TBICR Interrupt level flag for Interrupt Interrupt 35 time base interrupt enal flag request flag SC V1 SCOLVO 5 4 SCOIR X 3FE8 49 SCOICR Interrupt level flag fo
76. H PC if VF4NF 0 PC 4 gt PC 1000 if VF NF 1 PC 5 d1 t label eHPC 0 5 1001 if VF NF ZF 0 PC 4 PC if VF NF ZF 1 PC 4 d7 label H5PC 1000 if VF NF ZF 0 PC 5 PC if VFANF ZF 1 PC 54d11 label H PC 1001 Note Page re if VF NF ZF 1 PC 5 PC if VF NF ZF 0 PC 5 d7 label HPC ers to the corresponding page in the Instruction Manual 0010 0010 d4 sign extended 2 47 sign extended 3 411 sign extended Instruction Set Chapter 10 Appendices 101 00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag Codebycld Re Machine Code Notes Pag vFINF crFIzr Size peat Expand 1 2 3 4 5 6 z 8 9 10 11 Bcc BGT label W VF NEJIZF 0 PCs6 dit labe sHaPC 6 3 4 0010 0011 0001 dii 3 107 if VF NF ZF 1 PC 6 PC BHI label if CFIZF 0 PC 5 d7 label H PC 5 3 4 0010 0010 0010 d7 H 2 108 if CFIZF 1 PC 5 PC BHI label if CFIZF 0 PC 6 d1 1 label H PC 6 3 4 0010 0011 0010 dit 3 108 if CFIZF 1 PC 6 PC BLS label if CFIZF 1 PC 5 d7 label H PC 5 3 4 0010 0010 0011 d7 H 2 109 if CFIZF 0 PC 5 PC BLS label if CFIZF 1 PC 6 d1 1 label H PC 6 3 4 00
77. IC117 16 KB 512 bytes Mask ROM version 117 16 KB 512 bytes EPROM version Under development 1 2 Hardware Functions ROM RAM Size Single chip mode Internal ROM 16 384x8 bit Internal RAM 512 8 Machine Cycles High speed mode 0 10us 20MHz 4 5V to 5 5V 0 25us 8MHz 2 7V to 5 5V 1 00us 2MHz 2 0V to 5 5V Low speed mode 12515 32 2 2 0 to 5 5V Interrupts 12 interrupts 11 interrupts except for 48 pin QFH package External interrupts gt The active edge can be selected for all external interrupts IRQO External interrupt can be connected to noise filter IRQI External interrupt can determine zero crossings can be connected to noise filter IRQ2 External interrupt IRQ3 External interrupt Timer interrupts gt 21 Timer 2 8 bit timer TM3IRQ Timer 3 8 bit timer TMAIRQ Timer 4 16 bit timer TMSIRQ Timer 5 8 bit timer TBIRQ Clock timer interrupts Serial communication interrupt SCOIRQ Serial 0 synchronous simple A D conversion complete interrupt ADIRQ A D conversion complete Watchdog timer interrupt NMI Overflow of watchdog timer Timer Counters five timers all can generate interrupts Timer2 8 bit timer Square wave output 8 bit PWM output are possible Clock source fs fs 4 fx TM2IO pin input Timer3 8 bit timer Square wave output synchronous serial UART baud rate timer Clock source fosc fs 4 fs 16 TM3IO pin
78. IR P8DIR PAIMD P7PLUD P8PLU PAPLUD Port Control Registers 7 6 5 4 3 2 1 0 P7OUTO P8OUT7 esoure psours esourd peours etourz psour P8OUTO P7IN1 P7INO P8IN7 P8IN6 P8IN5 P8IN4 P8IN3 P8IN2 P8INO PAIN7 PAINS PAIN4 PAINS PAIN2 PAIN1 PAINO P7DIR1 P7DIRO P8DIR7 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIRO PAAIN7 5 PAAIN4 2 PAAIN1 PAAINO um P7PLUDO 7 P8PLU6 P8PLUS P8PLU2 P8PLU1 PAPLUD7 um PAPLUDS um PAPLUD3 PAPLUDO at reset at reset at reset at reset at reset at reset at reset at reset at reset at reset at reset Figure 3 2 1 Port Control Registers 2 2 XXXXXXXX XXXXXXXX 00000000 00000000 00000000 00000000 Chapter 3 Port Functions 3 2 2 Port Control Registers This section describes the special function registers that control the MN101C117 s I O ports E Data Registers PnOUT registers Data registers to output to the ports Data written to these registers is output from the ports 0 Low Vss level is output 1 High level is output PnIN registers Data registers to input data from the
79. M2MD X O3F82 R W Timer Function Control Registers 85 Chapter 4 Timer Functions 2 Timer 3 mode register TM3MD 7 6 5 4 3 2 1 0 TM3MD TM3CK2 TM3CKO at reset 00 TM3CK2 Clock source selection fosc fs 4 fs 16 input Cascade connection with timer 2 Synchronous input 13 output selection during TM2 PWM operation 0 Timer 3 output 1 Timer 2 PWM output TM3PWM count control 0 Halt the count 1 Operate the count Figure 4 9 14 Timer Mode Register TM3MD X 03F83 R W 86 Timer Function Control Registers Chapter 4 Timer Functions 3 Timer 4 mode register TMAMD 7 6 5 4 3 2 1 0 TM4MD TMEN TM4PWM T4ICTS1 TAICTSO TM4CK2 at reset 0000XXX TM4CK2 Clock source selection 0 fosc 0 1 fs 4 0 1 0 fs 16 1 TMAIO input 1 1 1 Synchronous TM4IO input T4ICTS1 T4ICTSO input capture trigger selection Disable input capture operation IRQO IRQ1 IRQ2 0 1 0 1 TM4PWM operation mode selection 0 16 bit timer operation 1 PWM operation
80. OLNG2 to 0 flags change at the opposite edge of the transmit data output edge Serial interface 0 begins operation when the SCOSBOS flag or the SCOSBIS flag is set to 1 Set the SCOSBOS flag or the SCOSBIS flag after all conditions have been set Synchronous Serial Interface 97 Chapter 5 Serial Functions nnnnnnfi Start condition enabled Start condition disabled Interrupt SCOBSY start condition enabled Z SCOBSY start condition disabled sn Figure 5 2 3 Synchronous Serial Interface Reception Timing reception at rising edge pa JU Lhnnnnnni 000 OO Start condition enabled Start condition disabled Interrupt SCOBSY start condition enabled SCOBSY start condition disabled mes Figure 5 2 4 Synchronous Serial Interface Reception Timing reception at falling edge 98 Synchronous Serial Interface 5 2 3 Serial Interface Transfer Timing Serial interface 0 uses SCOCEO and SCOCEI flags of serial interface 0 mode register 0 SCOMDO to control the edge at which transmission data is output and the edge at which reception data is input During transmission when the SCnCEI flag is 0 data output is synchronized to the falling edge of the clock During reception when the SCn
81. Pana Series The One toWatch for Constant Innovation Making the Future Come Alive MICROCOMPUTER MN101C00 MN1010C115 117 SI User s Manual Pub No 21411 011E Panasonic PanaXSeries is trademark of Matsushita Electric Industrial Co Ltd The other corporation names logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations 1 2 3 4 5 Request for your special attention and precautions in using the technical information and semiconductors described in this book An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the Foreign Exchange and Foreign Trade Control Law is to be exported or taken out of Japan The contents of this book are subject to change without notice in matters of improved function When finalizing your design therefore ask for the most up to date version in advance in order to check for any changes We are not liable for any damage arising out of the use of the contents of this book or for any infringement of patents or any other rights owned by a third party No part of this book may be reprinted or reproduced by any means without written permission from our company This book deals with standard specifications Ask for the latest individual Product Standards or Specifications in advan
82. PeOUT P6IN P6DIR P6PLU Chapter 3 Port Functions 7 6 5 4 3 2 1 0 POOUT6 POOUT2 POOUT1 POOUTO at reset P10UT4 P10UT3 PTOUT2 P10UT1 at reset at reset POING POIN2 POIN1 POINO at reset P1INA P1IN3 P1IN2 P1IN1 at reset E P2IN2 P2IN1 P2IN0 at reset Poons P0DIR2 Poo at reset P1DIR4 P1DIR3 PTDIR2 P1DIR1 at reset 14 P13TCO P12TCO at reset px POPLU2 POPLUI P1PLU4 P1PLU3 P1PLU2 P1PLU1 P2PLU2 P2PLU1 P2PLUO at reset securi 6 0 5 recurs sou PeOUTO at reset P6IN7 P6IN6 P6IN5 P6IN4 pans P6IN2 En P6INO at reset Penine penas Penia penina penia P6DIR1 sono at reset PePLur PePLue PsPLUD at reset Figure 3 2 1 Port Control Registers 1 2 Port Control Registers 0 000 00000 X XXX XXXXX XXX 0 000 00000 00000 0 000 00000000 XXXXXXXX 00000000 00000000 43 Chapter 3 Port Functions 44 P7OUT P7IN P8IN PAIN P7D
83. R Interrup level flag for Extemalinterupt Inemup Interupt 34 extemal interrupt valid edge fag enable flag request flag IRQILV1 IRQILVO REDG1 IRQ R X 3FE3 IRQIICR Interruptlevel flag Exemalintemup Interrupt Interrupt 34 for extemal interrupt enable fag request flag 9 X 3FE4 Disables to use X 5 Disables to use TM2LV1 TM2LVO TM2IE TM2IR X 3FE6 TM2ICR Interrupt level for Interrupt Interrupt 35 timer 2 interrupt enable flag request TBLV1 TBLVO TBIR X 3FE7 9 TBICR Interrupt level flag for Interrupt 35 time base interrupt enalge flag request flag SC V1 SCOLVO sc amp e 5 3FE8 SCOICR Interrupt level flag for Interup Interrupt 35 serial 0 interrupt enable fag flag X 9 Disables to use AD V1 ADIE AD Interrup level flag fore Interrupt Interrupt 41 35 AD interrupt enable flag request flag IRQ2LV1 021 0 REDG2 IRQMR X 3FEB 2 Interrupt level flag Extemalinterupi Inemup Interupt 34 for extemal interrupt valid edge flag enable fag request flag X 3FEC IRQ3ICR X 3FED Disables to use TM3IE X 3FEE 9 TM3ICR Interrupt level 20 Interupt Interupt 35 for timer 3 interrupt enable flag request TMAIE X 3FEF Interrupt level flag Interrupt Interrupt 35 for timer 4 interrup
84. RB3 SCOTRB2 SCOTRB1 SCOTRBO at reset undefined Figure 5 4 1 Serial Interface 0 Transmit Receive Shift Register SCOTRB X 03F55 W 2 Serial interface 0 receive data buffer SCORXB 7 6 5 4 3 2 1 0 SCORXB SCORXB7 SCORXB6 SCORXB5 SCORXB4 SCORXB3 SCORXB2 SCORXB1 SCORXBO at reset undefined Figure 5 4 2 Serial Interface 0 Receive Data Buffer SCORXB 0 56 Serial Interface Control Registers 107 Chapter 5 Serial Functions 5 4 3 Serial Interface Mode Registers 1 Serial interface 0 mode register SCOMDO 7 6 5 4 3 2 1 0 SCOMDO SCOCEO SCOCE1 SCODIR SCOSTE SCOLNG2 SCOLNG1 SCOLNGO at reset 00XX000 SCOLNG2 SCOLNG1 SCOLNGO Transfer bit count 0 8 bit 1 7 bit 0 0 6 bit 1 1 5bit Abi 0 0 bit 4 1 3 bit 0 2 bit 1 1 SCOSTE Selection of synchronous serial start condition 0 Disable start condition 1 Enable start condition SCODIR First bit to be transferred 0 MSB first 1 LSB first Receive data Transmit data SCOCET input edge output edge 0 0 Rising Falling 0 1 Falling Rising 1 0 Falling Falling 1 1 Rising Rising Figure 5 4 3 Serial Interface 0 Mode Register 0 SCOMDO X 03F50 R W 108 Serial Interface Control Registers 2 Serial interface 0 mode register 1 S
85. S OFFICE Panasonic Industrial Europe G m b H PIEG Munich Office Hans Pinsel Strasse 2 85540 Haar Tel 89 46159 156 Fax 89 46159 195 U K SALES OFFICE Panasonic Industrial Europe Ltd PIEL Electric component Group Willoughby Road Bracknell Berkshire RG12 8FP Tel 1344 85 3773 Fax 1344 85 3853 FRANCE SALES OFFICE Panasonic Industrial Europe G m b H PIEG Paris Office 270 Avenue de President Wilson 93218 La Plaine Saint Denis Cedex Tel 14946 4413 Fax 14946 0007 B ITALY SALES OFFICE Panasonic Industrial Europe G m b H PIEG Milano Office Via Lucini N19 20125 Milano Tel 2678 8266 Fax 2668 8207 HONG KONG SALES OFFICE Panasonic Shun Hing Industrial Sales Hong Kong Co Ltd PSI HK 11 F Great Eagle Centre 23 Harbour Road Wanchai Hong Kong Tel 2529 7322 Fax 2865 3697 TAIWAN SALES OFFICE Panasonic Industrial Sales Taiwan Co Ltd PIST Head Office 6th Floor Tai Ping amp First Building No 550 Sec 4 Chung Hsiao E Rd Taipei 10516 Tel 2 2757 1900 Fax 2 2757 1906 Kaohsiung Office 6th Floor Hsien 1st Road Kaohsiung Tel 7 223 5815 Fax 7 224 8362 SINGAPORE SALES OFFICE Panasonic Semiconductor of South Asia PSSA 300 Beach Road 16 01 The Concourse Singapore 199555 Tel 390 3688 Fax 390 3689 B MALAYSIA SALES OFFICE Panasonic Industrial Company Malaysia Sdn Bhd Head Office PICM Tingkat 168 Menara PKNS No 17 Jalan Yong Shoo
86. SCOLNG2 to 0 flags of the SCOMDO register are automatically set with the transfer bit count Set SCOCKM flag of the SCOMD1 register to 1 to divide the clock source frequency by 8 Half duplex UART Serial Interface 101 Chapter 5 Serial Functions 7 8 9 Serial interface 0 begins 10 operation when the SCOSBOS 11 flag or the SCOSBIS flag is set to 1 Set the SCOSBOS flag 12 or the SCOSBIS flag after all 13 conditions have been set 14 15 16 TXD Parity enabled If parity is enabled by the SCONPE flag of the SCOMDO2 register set the 5 1 0 flags of the SCOMD2 register to specify the added parity bit Set the SCOFMI to 0 flags of the SCOMD2 register to specify the frame mode Set the SCOBRKE flag of the SCOMD2 register to control break status transmission Select the SCOSBOM flag of the SCOMD3 register Select the SCOIOM flag of the SCOMD3 register Set bit 0 of the port 0 direction control register PODIR to the output mode Select serial communication by setting the SCOSBOS flag of the SCOMD3 register to 1 Set transmit data to serial interface 0 transmit receive shift register 5 This will start the serial transmission When the serial transmission begins the SCOBSY flag of the SCOCTR register is set to 1 indicating that a serial transfer is in progress When the serial transmission is complete the SCOBSY flag of the SCOCTR register is cleared to 0 and th
87. TM3BC6 TM3BC5 TM3BC4 TM3BC3 TM3BC2 TM3BC1 TM3BCO at reset 00000000 Figure 4 9 4 Binary Counter TM3BC X O3F63 82 Timer Function Control Registers Chapter 4 Timer Functions 5 Compare register 4 TM4OCL lower 8 bits 7 6 5 4 3 2 1 0 woo won ITMAOCL5 TM4OCL4 TM4OCL2 ITM4OCLO at reset undefined Figure 4 9 5 Compare Register 4 TM4OCL 74 R W 6 Compare register 4 TM4OCH upper 8 bits 7 6 5 4 3 2 1 0 moo moore woo reset undefined Figure 4 9 6 Compare Register 4 TMAOCH 75 R W 7 Binary counter 4 TM4BCL lower 8 bits 7 6 5 4 3 2 1 0 7 TM4BCL6 5 TM4BCL4 TM4BCL3 TM4BCL2 TM4BCL1 TM4BCLO at reset 00000000 Figure 4 9 7 Binary Counter 4 TM4BCL 03 64 8 Binary counter 4 upper 8 bits 7 6 5 4 3 2 1 0 M4BCH7 TM4BCH6 5 2 M4BCH1 TM4BCHO at reset 00000000 Figure 4 9 8 Binary Counter 4 TM4BCH X O3F65 Timer Function Control Registers 83 Chapter 4 Timer Functions 9 Input capture register TM4ICL lower 8 bits 7 6 5 4 3 2 1 0 TM4ICL7 TM4ICL6 TM4ICL4 pac TM4ICL2 m TM4ICLO reset undefined Figure 4 9 9 Input Capture Register TM4ICL X 03F66
88. The relation between the value set in the register and the added pulse is shown in the table below If X 03 is set in the TMAOCH register bits are appended to pulse positions for X 01 and X 02 shown in table 4 3 1 The relation between the value set in the TM4OCH register and the position of the added bit is shown in figure 4 3 5 Table 4 3 1 Pulse Added PWM OutputFigure Value Set in TMAOCH Register Added Pulse Position value of Tn 00000000 00000001 X 80 00000010 X 40 X CO 00000100 20 60 00001000 X 10 X 30 X 50 X 70 X 90 X B0 X D0 X F0 00010000 X 08 X 18 X 28 X 38 X 48 X 58 X E8 X F8 00100000 04 0 14 1 24 2 4 01000000 X 02 X 06 X OA X OE X12 X 16 10000000 X 01 X 03 X 05 X 07 X 09 X 0B X FD X FF MSB LSB Repeated 256 times 70 X 40 X 80 X C0 X FF lt Position of added pulse 1 1L 1n GL n qm JJ L L L JUD JL JL JL J gt PWM basic component Position of added pulse X 87 Position of added pulse X 88 Figure 4 3 5 Pulse Added Type PWM Output 74 16 bit Timer Operation timer 4 Chapter 4 Timer Functions Capture Function Settings for the capture function are listed below 1 Set the TMAEN flag of the timer 4 mode register to 0 to stop the coun
89. X 7FFF 4 After confirming the device name write the addresses from the start to the final address 5 option bits for supporting the mask option are prepared at the final ROM address This writer has no internal ID codes of Silicon Signature and Intelligent Identifier of the auto device selection command of ROM writer If the auto device selection command is to be executed for this writer the device is likely damaged Therefore never use this command When disabling the writing When disabling the writing check the following points 1 Check that the device is mounted correctly on the socket pin bending connecting failure 2 Check that the erase check result is no problem 3 Check that the adapter type is identical to the device name 4 Check that the writing mode is set correctly 5 Check that the data is correctly transferred to the ROM writer 6 Recheck the check points 1 2 and 3 provided on the above paragraph of iCautions on Handling the ROM When the writing is disabled even after the above check points are confirmed and the device is replaced with another one contact the nearest semiconductor design center See the attached sales office table Chapter 8 Appendices 8 1 7 Option Bit The MN101C117 and the MN101CP117 control the oscillation mode after resetting as well as the runaway detection watch dog timer using bit 2 to 0 of the last address X 7FFF of the built in ROM
90. alid even when special functions are selected for the dual function pins Table 3 1 1 Status When Port Is Reset single chip mode Port Mode Pull up Pull down Resistor Port or Special Function Port 0 Input mode No pull up resistor 1 0 port Port 1 Input mode No pull up resistor 1 0 port Port 2 Input mode No pull up resistor port Port 6 Input mode No pull up resistor port Port 7 Input mode No pull up pull down resistors port Port 8 Input mode No pull up pull down resistors port Port A Input mode No pull up pull down resistors port Port 0 PO 4 bit CMOS tri state I O port Table 3 1 2 Port 0 Functions Pin Dual Function Description to P02 T O SBOO TXD Each bit can be set individually as either an input or P06 SBIO RXD output by the PODIR register A pull up resistor for each SBTO bit can be selected individually by the POPLU register BUZZER At reset the input mode is selected and pull up resistors are disabled high impedance output 38 Overview Chapter 3 Port Functions Bi Port 1 P1 5 bit CMOS tri state port Table 3 1 3 Port 1 Functions Pin Type Dual Function Description P10 to P14 RMOUT Each bit can be set individually as either an input or TM2IO to output by the PIDIR register A pull up resistor for each bit can be selected individually by the PIPLU register
91. and Functions of P80 to P87 Chapter 4 Functions 55 Chapter 4 Timer Functions 4 1 Overview The MN101C117 contains three 8 bit timers one 16 bit timer a watchdog timer a time base timer and circuits for remote control output and buzzer output Table 4 1 1 Summary of Timer Functions Timer 2 Timer 3 Timer 4 Timer 5 Time Base 8 bit 8 bit 16 bit 8 bit Interrupt TM2IRQ TMSIRQ TM4IRQ TM5IRQ TBIRQ Timer operation O Event counter Timer pulse output x x Serial Y transmission clock PWM output Cascade O E connection Capture function x 0 fs fosc fosc fosc fosc Clock 1 fs 4 fs 4 fs 4 fs 4 fx source fs 16 fs 16 TM210 input fosc fx 2 input input Remote Pulse Not Other control added possible to carrier pulse type temporarily generation PWM halt BC 56 Overview Chapter 4 Timer Functions 4 4 uonezju indui SH GINCIA L 5 Indu OISNL lt XNN lt lt 91 5 m
92. apter 1 Overview Electrical Characteristics 17 Chapter 1 Overview 18 Electrical Characteristics Ta 40 to 85 C V 2 0 to 5 5V V 0V Rating Parameter Symbol Conditions Unit MIN TYP MAX Input pin 1 MMOD 8 Input high voltage 1 Vin 0 8V p 9 Input high voltage 2 V o 4 5 to 5 5V 0 7 5 10 Input low voltage 1 0 0 2 11 Input low voltage 2 V o 4 5 to 5 5V 0 0 3 12 Input leakage current la VIN 010 Vip 10 Input pin 2 P20 22 23 Schmitt trigger input 13 Input high voltage 0 8V p 14 Input low voltage Vis 0 02 15 Input leakage current Is VIN 0 to 10 16 Input high current Rue ON 30 100 300 uA Input 3 1 P21 Schmitt trigger input 17 Input high voltage Mid 0 8V gt Mos M 18 Input low voltage 0 02 19 Input leakage current Les VIN 0 to V 10 20 Input high current Lia 30 100 300 pA Input pin 3 2 P21 when used as SENS 21 Input high voltage 1 aH 5 0 4 5 Yu V 22 Input low voltage 1 fences Vas 3 5 23 Input high voltage 2 Vou 1 5 24 Input low voltage 2 Visi Vas 0 5 25 Input leakage current Los VIN 0V to 10 26 Input clamp current 15 V 400 Chapter 1 Overview SENS pin 27 Rise time tr
93. ation is selected 4 Set a value in compare register 4 TMAOCH TMAOCL 5 Set the TMAEN flag of the TMAMD register to 1 to start the timer 6 When timer 4 begins operation binary counter 4 will count upward from 0000 7 When the value of binary counter 4 matches that of the and TM4OCL registers the timer 4 interrupt request flag is set and the binary counter 4 is reset to X 0000 and begins to count upward again When synchronized is selected the timer 4 clock source is synchronized with the system clock after a transition of the TM4IO input signal Timer 4 counts upward based on a signal synchronized to the system clock Therefore correct values can be read from binary counter 4 Figure 4 3 2 Timer 4 Event Counter Timing when synchronous TM4IO CPU system clock fs TM4IO input Synchronous circuit output Binary counter x n n 1 input is selected Chapter 4 Timer Functions If TM4IO input is selected as the clock source and the value of binary counter 4 is to be read during operation select synchronized TM4IO input to avoid reading data that may be incomplete during count up transitions However with synchronized TMAIO input it is not possible to return from STOP HALT modes 16 bit Timer Operation timer 4 71 Chapter 4 Timer Functions The period of the output signal from the port 1 2 of the period set in the
94. c amp bp 0 PC 8 d abes H PC if mem8 IOTOP io8 bp 1 PC 8PC 6 7 0011 0100 1bp lt io8 gt di 123 BZ abs16 bp label if mem8 abs16 bp 0 PC 9 d7 label eH PC if mem8 abs16 bp 1 PC 9 PC 7 8 0011 1110 Obp abs 16 d H 1 124 BZ abs16 bp label mem8 abs16 bp 0 PC 10 d1 1 label H PC if mem8 abs16 bp 1 PC 10 PC 10 7 8 0011 1110 1bp lt abs 16 gt dii 2 124 TBNZ BNZ abs8 bp label if memB abs8 bp PC 7 d7 label HPC if mem8 abs8 bp 0 PC 7 PC 6 7 0011 0001 Obp abs 97 125 abs8 bp label if mem8 abs8 bp 1 PC 8 d1 1 label H PC if mem8 abs8 bp 0 PC 8 PC 6 7 0011 0001 1bp abs dii 2 125 BNZ io8 bp label mem amp io bp 1 PC 7 d7 label H PC 8 0 7 gt 6 7 0011 0101 Obp lt 08 gt lt d7 1 126 BNZ io8 bp label if mem8 io bp 1 PC 8 d1 label H 3PC 8 0 8 6 7 0011 0101 1bp lt io8 a dit a 2 126 BNZ abs16 bp label if mem8 abs16 bp 1 PC 9 d7 label H PC 8 516 0 9 gt 7 8 0011 1111 Obp abs 16 gt 07 H 1 127 BNZ abs16 bp label if mem8 abs16 bp 1 PC 10 d1 1 label H PC if mem8 abs16 bp 0 PC 10 PC
95. capture function and added pulse PWM output function can also be used Timer Operation Settings for timer operation are listed below 1 Set the TM4EN flag of the timer 4 mode register TM4MD to 0 so that the count operation of timer 4 is stopped 2 Set the TM4CK2 0 flags of the TM4MD register to select fosc fs 4 or fs 16 as the clock source 3 Set the flag of the TM4MD register to 0 so that 16 bit timer operation is selected nnnm TM4EN Writ to registers m Wow e AR Figure 4 3 1 Binary Counter 4 Count Timing the TM4EN flag of the TM4MD register is changed simultaneously with other bits the switching operation may cause binary counter 4 to be incremented If the value of and TM4OCL registers is overwritten while timer 4 has stopped counting binary counter 4 will be reset to X 0000 Chapter 4 Timer Functions Summary When servicing an interrupt reset the timer 4 interrupt request flag before operating timer 4 During a count operation be careful if the value set TM4OCH and TM4OCL is smaller than the value of binary counter 4 since the count up operation will continue until overflow occurs 16 bit Timer Operation 4 83 Introduction to the section Supplementary information Supplementary information for the
96. ce for more detailed information required for your design purchasing and applications If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book or Matsushita Electronics Corporation s Sales Department How to Read This Manual The MN101C11x incorporates more than one ROM RAM to meet a variety of applications An EPROM version as well as a Mask ROM version is available so users can write a program by themselves RAM MN101C115 256 MN101C117 MN101CP117 1 Under plannin Unit Byte Organization In this LSI manual the MN101C117 functions are presented in the following order overview CPU basic functions port functions timer functions serial functions and other peripheral hardware functions How to Read This Manual 1 Manual Configuration Each section of this manual consists of a title summary main text supplemental information precautions and warnings The layout and definition of each section are shown below Subtitle Sub subtitle The smallest block in this manual Main text Key information Important information from the text 4 3 16 bit Timer Operation timer 4 4 3 1 Overview Timer 4 is a 16 bit programmable counter that can be used as an event counter A signal with frequency of 1 2 of the timer 4 overflow signal can be output from the pin An input
97. d parity bit 3 Set the SCOFMI to 0 flags of the SCOMD2 register to specify the frame mode 9 Select the SCOIOM flag of the 5 register 10 When the SCOIOM flag of the SCOMD3 register is specified that the pin is independent set bit 1 of the port 0 direction control register PODIR to the input mode 11 Set bit 0 of the port 0 pull up resistor control register POPLU 12 Select serial communication by setting the SCOSBIS flag of the SCOMD3 Serial interface 0 begins register to 1 operation when the SCOSBOS 13 When the serial transmission begins the SCOBSY flag of the SCOCTR or SCOSBIS flag is set to 1 Set the SCOSBOS or SCOSBIS flag after all conditions have been set register is set to 1 indicating that a serial transfer is in progress 14 When the serial transmission is complete the SCOBSY flag of the SCOCTR register is cleared to 0 and the SCO transfer complete interrupt request flag is set to 1 The SCOTRI flag of the SCOMDI register is cleared to 1 One machine cycle after the stop bit has been received the start condition will no longer be Setting the SCOFM flag of the 5 2 register to frame accepted Therefore mode automatically sets the SCOLNG2 to 0 flags of the consecutive reception must be performed carefully SCOMDO register After the transfer is complete the SCOLNG2 to 0 flags of the SCOMDO register are automatically set with the transfer bit count Half dup
98. der resistor control 0 A D ladder resistors off 1 A D ladder resistors on anckt ANCKO A D conversion clock selection 1 0 fs 2 0 1 fs 4 1 0 15 8 1 Use prohibited Sample and hold ime setting 2 0 Tap x 2 9 1 Tap x 6 1 0 Tao x 18 1 Use prohibited 1 A D control register 0 ANCTRO 1 Specify that where the period of the A D conversion clock is greater than 800ns 2 Sample and hold time is determined by the analog input impedance indicates the period of the A D conversion clock Figure 6 3 1 A D Control Register 0 ANCTRO 90 R W 118 A D Converter Control Registers Chapter 6 A D Conversion Functions 2 A D conversion control register 1 ANCTR1 ANCTR1 ANST at reset 0 ANST A D conversion status 0 A D conversion completed or stopped 1 A D conversion started or in progress Figure 6 3 2 A D Control Register 1 ANCTR1 X 03F91 R W A D Converter Control Registers 119 Chapter 6 A D Conversion Functions 6 3 3 A D Buffers ANBUF These read only registers store the A D conversion results 1 A D buffer 0 ANBUFO This register stores the lower 2 bits of the A D conversion results 7 6 5 4 3 2 1 0 ANBUFO ANBUF07 ANBUF06 at reset XX Figure 6 3 3 A D Buffer 0 ANBUFO X OSF92 R 2 A D buffer 1 AN
99. e is12000uW cm Remove any filters attached to the lamp By installing a mirrored reflector plate in the lamp illumination intensity will increase by afactor of 1 4 to 1 8 decreasing the erasure time If the window becomes dirty with oil adhesive etc UV light permeability will decrease causing the erasure time to increase considerably If this happens clean with alcohol or another solvent that will not harm the package The recommended above provides sufficient leeway with several times the amount of time it takes to erase all the bits However this value will reliably erase data over all temperature and voltage ranges and should not be altered The level of illumination should be regularly checked and the lamp operation verified Erasure begins when EPROM is exposed to light with a wavelength shorter than 400nm Since fluorescent light and sunlight have wavelengths in this range exposure to these light sources for extended periods of time could cause inadvertant erasure To prevent this cover the window with an opaque label Data is not erased at wavelengths longer than 400 to 500nm However because of typical semiconductor characteristics the circuit may malfunction if the chip is exposed to an extremely high illumination intensity The chip will operate normally if this exposure is stopped However for areas where it is continuous take necessary precautions Chapter 8 Appendices 8 1 4 Characteristics of EPROM Version T
100. e SCO transfer complete interrupt request flag is set to 1 The SCOTRI flag of the SCOMDI register is cleared to 0 TXD Parity disabled Stop Stop ul Interrupt ew Parity enabled Interrupt I Parity disabled SCOBSY Parity enabled SCOBSY Parity disabled 102 Half duplex UART Serial Interface Figure 5 3 1 UART Transmission Timing Chapter 5 Serial Functions Reception When the serial port is enabled and the SCOCE 1 to 0 flags of 1 Select UART by setting the SCOCMD flag of the serial interface 0 control the SCOMDO register are register SCOCTR to 1 toggled the transfer bit count may change 2 Specify the first bit to be transferred MSB first or LSB first with the SCODIR flag of the serial interface 0 mode register 0 SCOMDO The TXD pin goes to a high 3 Select the valid edge of the clock signal with the SCOCEI to 0 flags of the level after reception is SCOMDO register complete 4 Select the clock source with the SCOCK1 0 flags of serial interface 0 mode register 1 SCOMD1 5 Set the SCOCKM flags of SCOMDI register to 1 to divide the clock source frequency by 8 6 Set the SCONPE flag of the serial interface 0 mode register 2 SCOMD2 to enable or disable parity 7 If parity is enabled by the SCONPE flag of the SCOMDO2 register set the SCOPMI to 0 flags of the SCOMD2 register to specify the adde
101. e of binary counter 4 is reset to 0000 and counting begins again Chapter 4 Timer Functions When servicing an interrupt reset the timer 4 interrupt request flag before operating timer 4 During a count operation be careful if the value set in and TM4OCL is smaller than the value of binary counter 4 since the count up operation will continue until overflow occurs 16 bit Timer Operation timer 4 69 Chapter 4 Timer Functions Clock TM4EN E x Write to registers TM4OCL Binary 04 05 06 o9 00 counter 4 X 1 i f Figure 4 3 1 Binary Counter 4 TM4BC Count Timing If the TM4EN flag of the register is changed simultaneously with other bits the switching operation may cause binary counter 4 to be incremented If the value of the TM4OCL register is overwritten while timer 4 has stopped counting binary counter 4 will be reset to X 0000 70 16 bit Timer Operation timer 4 Event Count Function Settings for the event count function are listed below 1 Set the TMAEN flag of the timer 4 mode register to 0 to stop the count operation of timer 4 2 Use the TM4CK2 to 0 flags of the TM4MD register to select TM4IO input or synchronized TM4IO input as the clock source 3 Set the TM4PWM flag of the TM4MD register to 0 so that 16 bit timer oper
102. er Usage Methods 101 00 Series PanaX Series Installation Manual Installation of C Compiler Cross Assembler C Source Code Debugger In circuit Emulator Where to Send Inquires Please send any inquires or questions concerning the contents of this manual to the Panasonic semiconductor design center closest to you A list of addresses 1s provided at the end of this manual for your convenience How to Read This Manual 3 Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Contents Overview Basic CPU Functions Port Functions Timer Functions Serial Functions A D Conversion Functions AC Zero Cross Circuit Noise Filter Appendices E E ES ES ESL ES G Contents Contents 1 Contents Chapter 1 Overview 1 1 1 2 1 3 1 4 1 5 1 6 1 7 Product OVERVIEW ae 2 IMEEM 2 12122 Product iro e ee m E e Oeo tI I HER S EIER UE 2 Hardware F riCtions k uu uwa esp codes tese 3 p i MS 5 1 3 1 5 1 3 2 Pin Function Summity nee to etr oto RUD iet 8 Overview Of FUnCLOfS recortes rte maa RE a Oa Pep ass 12 1 4 Block u nee 12 Electrical Characteristics su u etr tenete ida EE ER Coda REEE 13 1 5 1 Absolute Maximum Ratings 13 1 5 2
103. hapter 1 Overview 40 to 85 V 2 0t05 5V V 0V Rating Parameter Symbol Conditions Unit MIN TYP MAX pin 9 P80 P87 63 Input high voltage 1 Vs 0 Vs V 64 Input high voltage 2 Maii Vp 45 to 5 5V 0 7 V 65 Input low voltage 1 V nas 0 0 2 66 Input low voltage 2 Nu Vp 45 to 5 5V 0 03 67 Input leakage current Ls VIN 0 to 10 68 Input high current Lun 30 100 300 pA 69 Output high voltage Voms Vhp 5V Ig 0 5mA 4 5 V 70 Output low voltage Miis 5V I mA 1 0 V 1 5 4 A D Converter Characteristics 4010485 V 20to55V V 0V Rating Parameter Symbol Conditions Unit MIN TYP MAX 1 Resolution 10 Bits 2 Nonlinear error 1 Von 75 0V V OV 23 LSB Veer gt Veer 70V 3 Differential linear error 1 800ns 23 15 4 Nonlinear error 2 5 0 V OV 5 LSB V age V 70V 5 Differential linear error 2 fx 32 768kHz 5 LSB 6 Zero traction voltage Vp 50V V 30 100 mV Vi Veer 70V 7 Full scale transition voltage 800ns 30 100 mV 8 800ns 9 6 us A D conversion time 9 fx 32 768kHz 183 us 10 fosc 2 1 0 36 us Sampling time 11 fx 32 768kHz 30 5 us 12 Analog input leakage current When Van 0 to 5V is off 22 uA Electrical Characteristics 2
104. he MN101C11 mask ROM version and the Microcomputer with internal EPROM version have the following differences Table 8 1 1 Difference between MN101C Mask ROM version and Internal EPROM version 101 11 0 ROM ver Internal EPROM version Operating temperature 4010059 20 to 85 C 4 510 5 5V 0 14 5 20 41 4 5 to 5 5V 0 1 s 20MHz 2 7 to 5 5 0 25 5 8 2 7 to 5 5v 0 25 s 8MHz Operating voltage 2 0 to 5 5v 1 000 s 2MHz 2 7 to 5 5v 1 0010 s 2MHz Pin DC characteristics Output current input current and input judge level are the same Hi speed low speed oscilla option EPROM option Internal ROM final address data EPROM final address data be SU be used as option data used as option data Package selection Final address X 07FFF Final address X 07FFF There are no other functional differences EPROM Versions 133 Chapter 8 Appendices 8 1 5 Writing to Microcomputer with Internal EPROM E Fit in the writing adapter and position the No 1 pin No 1 pin must be matched to this position socket of an adapter varies according to the package types Package type Product name 42 SDIP OTP42SD 101CP11 44 OTP44QF14 101CP11 48 QFH OTP48FH7 101CP11 No 1 gt gt MN101CP117DP No 1 Pin MN101CP11
105. hen the value of binary counter 2 matches that of the TM2OC register the timer 2 interrupt request flag is set and the binary counter 2 is reset to 00 and begins to count upward again When synchronized 210 is selected the timer 2 clock source is synchronized with the system clock after a transition of the TM2IO input signal Binary counter 2 counts upward based on a signal synchronized to the system clock Therefore correct values can be read from binary counter 2 CPU system clock fs TMAIO input Synchronous circuit output Binary counter 8 bit Timer Operation timers 2 3 Figure 4 2 2 Timer 2 Event Counter Timing when synchronous 2 input is selected Timer Pulse Output Function timers 2 3 Settings for the timer pulse output function are listed below Timer 2 is used as an example 1 Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the count operation of timer 2 2 Set bit 2 of the port 1 output input mode register PLOMD to 1 to set the special function pin Bit 2 of port 1 will be specified as the pulse output pin 3 Set the TM2CK2 to 0 flags of the TM2MD register to select fs fs 4 fx or synchronized fx as the clock source 4 Set the TM2PWM flag of the TM2MD register to 0 so that normal timer operation is selected 5 Set a value in compare register 2 2
106. ification 0 7 data bits 1 stop bit 1 7 data bits 2 stop bits 0 8 data bits 1 stop bits 1 8 data bits 2 stop bits SCOBRKE Break status transmit control 0 Data 1 Break Figure 5 4 5 Serial Interface 0 Mode Register 2 SCOMD2 52 R W 110 Serial Interface Control Registers 4 Serial interface 0 mode register 3 SCOMD3 7 6 5 4 3 2 1 0 SCOMD3 86010 5005 0 SCOSBTM SCOSBOS SCOSBIS SCOSBTS Chapter 5 Serial Functions at reset 000000 SCOSBTS SBTO pin function selection 0 Port Serial clock pin SCOSBIS SBIO input control 0 1 input 1 Serial input SCOSBOS 35800 pin function selection 0 Port 1 Serial communication SCOSBTM SBTO pin configuration selection 0 Push pull output 1 N channel open drain output SCOSBOM 5 0 pin configuration selection 0 Push pull output 1 N channel open drain output SCOIOM SBIO SBOO pin connection 0 Unconnected 1 Connected Figure 5 4 6 Serial Interface 0 Mode Register SCOMD3 X 03F53 R W Serial Interface Control Registers 111 Chapter 5 Serial Functions 5 4 4 Serial Interface Control Register 1 Serial interface 0 control register SCOCTR 7 6 5 4 3 2 1
107. imer 4 compare match TM4IRQ TM4ICR X 03FEF X 0403C 16 Timer 5 compare match 5 X OSFFO X 04040 17 Reserved X 03FF1 X 04044 18 Reserved X OSFF2 X 04048 19 Reserved X 03FF3 X 0404C 20 Reserved X 03FF4 X 04050 Set the vector addresses for reserved and unused interrupts to an address containing an RTI instruction Interrupts 33 Chapter 2 Basic CPU Functions Be sure to use the MIE flag of the PSW register to write to all interrupt control registers By setting xxxLVn to 11 level 3 the corresponding interrupt vector will be disabled regardless of the state of the interrupt enable and interrupt request flags 34 Interrupts 2 4 3 Interrupt Control Registers Interrupt control registers consist of the following a non maskable interrupt control register NMICR external interrupt control registers IRQnICR and internal interrupt control registers TMnICR TBICR SCnICR ATCICR ADICR Non maskable Interrupt Control Register NMICR Non maskable interrupt factors are stored in the non maskable interrupt control register NMICR and are used when a non maskable interrupt is generated 7 6 5 4 3 2 1 0 NMICR WDIR at reset 0 WDIR Watchdog interrupt request flag 0 No interrupt request 1 Happens interrupt request Figure 2 4 2 Non maskable Interrupt Control Register NMICR X OSFE1
108. inary counter 4 starts disables setting of X FF att counting from X 00 and ending when the value of binary counter 4 matches the TM4OCL register value set in the register 10 When the value of binary counter 4 matches that of the TM4OCL register a low level signal is output from the port 11 Binary counter 4 continues to count upward until X FF is reached At the next count up cycle the value of binary counter 4 is reset to 00 and counting begins again high level signal is output from the port Use a 16 bit access instruction to set the TM4OCL register Basic PWM components Added pulse mE 7 Added pulse 00 Tn X 01 Tn X 02 7 03 04 Tn X FF 0 Repeated 256 times Figure 4 3 4 Pulse Added Type PWM Output 16 bit Timer Operation timer 4 73 Chapter 4 Timer Functions 5 2 3 Serial Interface Setting the Added Pulse Position Transfer Timing TM4OCH Register setting value X 00 X 01 X 02 X 04 X 08 10 The upper 8 bits of compare register 4 TM4OCH set the position of the added pulse If the TM4OCH register is set to X 00 an additional bit is not appended to the basic PWM component If the register is set to an additional bit is repeatedly appended to the 255 basic PWM components during the period
109. input Remote control carrier can be generated Chapter 1 Overview 2 Differs depending upon the model 1 1 2 Product Summary 3 Bit 8 of the last adaress for the built in ROM of MN101C11X is an optional bit therefore this cannot be used as an ordinary ROM 4 Exclusive for a 48 pin QFH product Hardware Functions 3 Chapter 1 Overview 5 6 7 26 ports for 44 QFP 27 ports for 48 QFH 12 ports for 48 QFH 4 ports for 48 QFH Hardware Functions Remote control carrier output Buzzer output Serial interface A D converter Timers 2 and 3 can be cascaded Timer 4 16 bit timer Square wave output 16 bit PWM output are possible Clock source fosc fs 4 fs 16 pin input Input capture function Time base timer Clock source fosc fs 4 fx 215 4 or fosc 2 XIOat 32kHz can be set to measure one minute intervals Can operate independently as timer 5 8 bit timer Watchdog timer Selected by the mask option as fs 2 5 fs 2 or fs 2 Based on the timer output a remote control carrier with duty ratio of 1 2 1 3 can be output Output frequency can be selected from 15 27 fs 2 fs 2 fs 2 Synchronous Simple UART half duplex Transfer clock 15 2 15 4 fs 16 1 2 of timer 3 output When using timer 3 the transfer rates for a 12MHz oscillation are 19200 9600 4800 2400 1200 300 bps MSB or LSB can be selected as the first bit for transfer An arbitrary transfer
110. ins to ceramic or crystal oscillators for low speed clock operation If the clock is an external input connect it to XI and leave XO open The chip will not operate with an external clock when using the STOP mode If these pins are not used connect XI to VSS and leave XO open 42 SDIP and 44 QFP packages have no pins of this kind This pin resets the chip when power is turned on is allocated as P27 and contains an internal pull up resistor Typ 35 Setting this pin low initializes the internal state of the device is initialized Thereafter setting the input to an H level release the reset The hardware waits for the system clock to stabilize and then processes the reset interrupt Also if 0 is written to P27 and the reset is initiated by software a low level will be output The output has an n channel open drain configuration If a capacitor is to be inserted between RST and VDD it is recommended that a discharge diode be placed between RST and VDD 4 bit CMOS tri state I O port P06 SBIO RXD SBTO DK BUZZER Each bit can be set individually as either an input or output by the PODIR register A pull up resistor for each bit can be selected individually by the POPLU register At reset the input mode is selected and pull up resistors are disabled high impedance output 8 Pins Chapter 1 Overview Table 1 3 1 Pin Function Summary 2 4 4 to 42 P70 to P71
111. it data to serial interface 0 transmit receive shift register SCOTRB This will start the serial transmission When serial transmission begins the SCOBSY flag of the SCOCTR register 18 set to 1 indicating that a serial transfer is in progress When the serial transmission has completed the SCOBSY flag of the SCOCTR register is cleared to 0 and the SCO transfer complete interrupt request flag is set to 1 The SCOTRI flag of SCOMDI register 1 is cleared to 0 After the transfer is complete the transfer bit count in the SCOLNG2 to 0 flags of the SCOMDO register will be changed Except in an 8 bit transfer reset the transfer bit count at the time of the next transmission When switching from transmission to reception set the SCOSBOS flag of the 5 register to 0 and then set the SCOSBIS flag to 1 Do not change both of these flags at the same time The SCOSBTS of the SCOMD3 register must be set to 1 before the SCOSBOS flag of the SCOMD3 register is set to 4 c Chapter 5 Serial Functions When the serial port is enabled and the SCOCE 1 to 0 flags of the SCOMDO register are changed the transfer bit count in the SCOLNG2 to 0 flags of the SCOMDO register may be incremented Enabling the start condition drives the SBOO pin high for a fixed time interval 1 2 the clock source cycle after the transmission is completed If the start condition is disabled the SBOO pin will remain at the value of the
112. itialized ti data in the TM50C isteri andthe value ot binary counter 5 will be initialized every time data in the register is counter 5 is to be read during overwritten Timer 5 interrupts are disabled in this mode If timer 5 operation select synchronized fx interrupts are to be used the TM5CLRS flag must be reset to 1 pur IQ QVO reading after writing to the TM5OC register may be incomplete during count up transitions However with synchronized fx input it is not possible to return from STOP HALT modes 4 Timer 5 operation cannot be halted 76 8 bit Timer Operation timers 2 3 Chapter 4 Timer Functions 4 5 Time Base Operation 4 5 1 Overview The clock source for the time base timer can be set to fosc or fx Also the interrupt period for time base timer TBIRQ can be set to 1 27 1 25 1 29 1 21 or 1 2 of the clock source 4 5 2 Operation Time Base Function Settings for the time base function are listed below 1 Use the 5 flag of the timer 5 mode register TMSMD to select fosc or fx as the clock source 2 Use the TMSIR2 to 0 flags of TM5MD register to select the time base timer interrupt source 3 When the selected time interval passes the interrupt request flag of the time base interrupt control register TBICR is set Time base operation cannot be halted Table 4 5 1 Base Time Settings Time Base Operation 77 Chapter 4
113. k Lin 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 03 7516606 Fax 08 7516666 Penang Office Suite 20 17 MWE PLAZA No 8 Lebuh Farquhar 10200 Penang Malaysia Tel 04 2625550 Fax 04 2619989 Johore Sales Office 39 01 Jaran Sri Perkasa 2 1 Taman Tampoi Utama Tampoi 81200 Johor Bahru Johor Malaysia Tel 07 241 3822 Fax 07 241 3996 CHINA SALES OFFICE Panasonic SH Industrial Sales Shenzhen Co Ltd PSI SZ 74 107 International Business amp Exhibition Centre Futian Free Trade Zone Shenzhen 518048 Tel 755 359 8500 Fax 755 359 8516 Panasonic Industrial Shanghai Co Ltd PICS 1F Block A Development Mansion 51 Ri Jing Street Wai Gao Free Trade Zone Shanghai 200137 Tel 21 5866 6114 Fax 21 5866 8000 THAILAND SALES OFFICE Panasonic Industrial Thailand Ltd PICT 252 133 Muang Thai Phatra Complex Building 31st Fl Rachadaphisek Rd Huaykwang Bangkok 10320 Tel 02 6933407 Fax 02 6933423 080499
114. lex UART Serial Interface 103 Chapter 5 Serial Functions RXD Party enabled Y V JE RXD 000 Interrupt Parity enabled Interrupt Parity disabled SCOBSY Parity enabled SCOBSY Parity disabled Figure 5 3 2 UART Reception Timing 104 Half duplex UART Serial Interface Chapter 5 Serial Functions 5 3 3 How to Use the Baud Rate Timer Refer to the following when using the baud rate timer to set the UART transfer speed 1 Specifying the timer clock source The clock source is specified by the TM3CKS3 to 1 flags of the timer 3 mode register TM3MD 2 Setting the compare register The compare register value is set in the timer 3 compare register TM3OC This set value is computed according to the following formula overflow period compare register set value 1 x timer clock period baud rate 1 overflow period x 2 x 8 T SCOMD1 SCOCKM compare register set value timer clock frequency baud rate x 2x 8 1 Table 5 3 1 UART Transfer Rate Set the values from this table minus 1 in the compare register Transfer Speed 1200 2400 4800 9600 19200 Calculated Set Calculated Set Set Set Calculat e Value Value _ V Value _ Value Value Value Vale Value Set Value 208 1202 104 2403 52 4807 26 9615 11201 109 2402 55 4761 9699
115. mem8 x 004080 1bl4 lt lt 2 2 bp7 gt PC H mem8 x 004080 tbl4 lt lt 2 2 bp1 0 PC bp17 16 1111 1110 lt t4 gt 131 2 Note Page refers to the corresponding page in the Instruction Manual 0000 0000 1 2 3 4 47 sign extended d11 sign extended d12 sign extended d16 sign extended aa abs18 171 16 145 Instruction Set Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Flag Re Machine Code Notes Pag VF ZF Size Expand 1 2 8 9 0 11 0000 9 9 9 9 9 9 mem8 SP gt PC bp7 0 memB SP 1 6 150 9 memB SP42 bp72 PC H memB SP 2 bp1 0 PC bp17 SP435 SP e I memB SP o PSW mem8 SP 1 PC bp7 04 mem8 SP 42 PC bp15 8 memB SP 3 bp72 memB SP 3 bp1 0 gt 0 170 46 memB SP 44 5 e memB SP 45 5 HA h e SP465 SP e 5 8 99 re 9 1 22242 see esse N m 134 gt lt gt 2 999999909 21 eecccecefooce 6 6060606666666 6 661 0490966606466 66 gt ee ee eee eee amp amp 9 9 9 9 99 2 Contr
116. nPLUD and other registers 0 port 1 Special function pin Pin Control Registers FLOATI registers This register specifies whether the resistors attached to pins P7 and PA are pull up resistors or pull down resistors In addition this register selects either zero cross input or Schmitt trigger input for pin 21 7 6 5 4 3 2 1 0 FLOAT1 PARDWN P7RDWN at reset 000 P7RDWN P7 pull up pull down resistor selection 0 pull up resistor 1 pull down resistor PARDWN PA pull up pull down resistor selection 0 pull up resistor 1 pull down resistor 21 P21 input mode selection 0 Schmitt trigger input 1 SENS input Figure 3 2 2 Pin Control Register 1 FLOAT1 46 Port Control Registers Chapter 3 Port Functions 3 3 I O Port Configuration and Functions P00 P02 P10 to P14 FNG nese 2 Pull up resistor control gt gt Write L N Z Read Rese R direction control e Write Data bus nese R Port output data Write F Read Schmidt trigger input Port input data lt NJ Read Special function input data Special function out
117. nal interrupt The valid edge for these external interrupt input pins can be selected IRQ3 P21 SENS input pins with the IRQnICR registers P22 P23 is an external interrupt pin that is able to determine AC zero 6to 13 to ANT Input 7 Analog input pins Analog input pins for an 8 channel 10 bit A D converter crossings It can also be used as a normal external interrupt When IRQO to 3 are not used for interrupts these can be used as normal I O pins When not used for analog input these pins can be used as normal I O pins 30 SENS Input IRQI P21 AC zero cross detection input pin SENS is an input pin for an AC zero cross detection circuit The AC zero cross circuit outputs a high level when the input is at an intermediate level It outputs a low level at all other times SENS is connected to the P21 input circuit and the IRQI interrupt circuit When the AC zero cross detection circuit is not used this can be used as normal P21 input The P21IM flag of the FLOAT register sets which input is selected Pins 11 Chapter 1 Overview TXD SBOO P00 lt RXD SBIO P01 SBTO P02 POG lt gt RMOUT P10 11 lt 1 4 1 Block Diagram 1 4 Overview of Functions TM210 P12 13 14 IRQ0 P20 SENS IRQ1 P21
118. nstruction Map Chapter 10 Appendices Extension code b 0011 2nd nibble 3rd nibble 9 0 1 2 TBZ abs8 bp d7 8 9 A B C D E F TBZ abs8 bp d11 TBNZ abs8 bp d7 TBNZ abs8 bp d11 Dn Dm ADD Dn Dm TBZ io8 bp d7 TBZ io8 bp d11 TBNZ io8 bp d7 TBNZ io8 bp d11 OR Dn Dm AND Dn Dm BSET io8 bp BCLR io8 bp J MP abs18 label J SR abs18 label XOR Dn Dm XOR 8 Dm ADDC Dn Dm BSET abs16 bp BCLR abs16 bp BTST abs16 bp cmp 8 20516 mov 8 abs16 8 abs16 d7 11 8 abs16 d7 11 TBZ abs16 bp d7 TBZ abs16 bp d11 TBNZ abs16 bp d7 148 Instruction Map TBNZ abs16 bp d11 Ver2 0 1997 9 26 Chapter 10 Appendices 8 4 Summary of Special Function Registers Bit Symbol Address Register Reference Bit 7 Bit 6 Bit5 Bit4 Bit 3 Bit 2 Bit 1 page STOP HALT OSC1 OSCO MN101C00 series X 3F00 5 HALT oscillation control LSI Manual transfer requestansfer request IOW1 IOWO IVBA 9 IRWE e 3FOl MEMCTR 0 X 3F01 e 11 0 bus wait value set M WDEN 02 WDCTR Watchdog
119. ntrol output and timer output Port Configuration and Functions 47 Chapter 3 Port Functions B P01 BS Reset R Pull up resistor control D Q D Write L F Read R VO direction control DQ gt Write L N Z Read Y a g Rese e R Port output data D Q Write L N Z Read Schmitt trigger input Port input data Pc Read Special function input data Pull up Control bit POPLUI resistor Register POPLU control address X 03F40 Control bit PODIRI direction control Register PODIR address X 03F30 Control bit POOUTI Port output Register POOUT address X 03F10 Control bit Port input Register POIN address X 03F20 Special function input Special function SBIO RXD Figure 3 3 2 Configuration and Functions of PO1 48 I O Port Configuration and Functions Chapter 3 Port Functions PAO to PA7 N iii E R DQ Pull up pull down resistor control Write Read Rese R Pull up pull down resistor selection D gt Write L Read Y 5 Read 5 Port input data 1 7 Rese R Input mode control DQ 1 Write L MES Read Analog input
120. o timer table DLYS1 DLYSO X 3F03 DLYCTR Sets oscillation stabilization wait period Ex v POOUT6 POOUT2 POOUT1 POOUTO 10 Port 0 output 411 45 e P1OUT3 P1OUT2 P1OUTO P1OUT X 3F11 Port 1 output 41145 P2OUT7 P2OUT 411 45 X 3F12 Port 2 output 0 13 Disable to use 14 DisableSto use 15 isable o use P6OUT7 P6OUT6 5 P6OUTA P6OUT2 6 6 P6QUT 411 45 3 16 Port 6 output d P7OUTO 17 700 Pot7 410 45 output P8OUT7 P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 4 P8OUT 18 Port 8 output a 1 Disableso use POING POIN2 POIN1 POINO Tm POIN 410 45 x ar20 Port 0 input 0 P1IN2 411 45 X 3F21 Port 1 input J e e P2IN2 2 1 P2INO 22 P2IN Port 2input al 45 23 use Summary of Special Function Registers 149 Chapter 10 Appendices Bit ymbol Address Register Reference Bit 7 Bit6 Bit
121. of precision During setup and evaluation verify the waveform of the analog input pin a The following items must be implemented to maintain the accuracy of the Equivalent circuit of m analog signal output _ R I e input pin Cow x a dd c Vss puc EN 1 gt gt 1000 where R lt 500kQ 1 These values are reference values Figure 6 2 2 Recommended Circuit When Using A D Conversion 6 3 A D Converter Control Registers 6 3 1 Overview Four registers control the A D converter See table 6 3 1 Table 6 3 1 A D Converter Control Registers Name Address R W Function ANCTRO X 03F90 R W A D control register 0 ANCTRI R W A D control register 1 ANBUFO X 03F92 R A D buffer 0 ANBUFI X 03F93 R buffer 1 Chapter 6 A D Conversion Functions A D Converter Control Registers 117 Chapter 6 A D Conversion Functions 6 3 2 A D Control Register ANCTR This readable and writable 8 bit register controls the operation of the A D converter 7 6 5 4 3 2 1 0 at reset ANCTRO ANSH1 ANSHO ANCKO nois ANCHS1 ANCHS2 ANCHS1 ANCHSO Analog input selection 0 0 1 1 0 0 2 1 0 0 1 5 0 6 1 ANLADE A D lad
122. of the last data bit If the SCOIOM flag of the SCOMD3 register is set for a pin connection the SBIO pin can be used as a port The SBOO pin receives data during the input mode and transmits data during the output mode The SCOLNG2 to 0 flags change at the opposite edge of the transmit data output edge Serial interface 0 begins operation when the SCOSBOS flag or the SCOSBIS flag is set to 1 Set the SCOSBOS flag or the SCOSBIS flag after all conditions have been set Synchronous Serial Interface 95 Chapter 5 Serial Functions SBT ZEE SBO M Start condition enable disabled E C 7 Interrupt LT 00000000 Figure 5 2 1 Synchronous Serial Interface Transmission Timing falling edge w 000000 a 00000 SCOBSY 2000000000 Figure 5 2 2 Synchronous Serial Interface Transmission Timing rising edge 96 Synchronous Serial Interface Reception 1 2 3 4 5 6 7 8 9 10 Select the synchronous serial interface by setting SCOCMD flag of the serial interface 0 control register SCOCTR to 0 Select the transfer bit count with the SCOLNG2 to 0 flags of the serial interface 0 mode register 0 SCOMDO The transfer bit count can be set as 1 to 8 bits Specify whether the star
123. ol instruction REP imm3 imm3 RPC MOE Note Page refers to the corresponding page in the Instruction Manual 1 Number of repeats is 0 when imm3 0 Ver2 0 1997 9 26 146 instruction Set 8 3 Instruction 101 00 SERIES INSTRUCTION 1st nibble 2nd nibble 2 3 4 5 7 8 abs8 abs12 POP An ADD 8 Dm Chapter 10 Appendices C D E MOVW 8 DWm MOVW 8 Am J SR d12 label SR d16 label MOV 8 abs8 abs12 PUSH An OR 8 Dm AND 8 Dm When the extension code is b 0010 When the extension code is b 0011 MOV abs12 Dm MOV abs8 Dm MOV An Dm MOV Dn abs12 MOV Dn abs8 MOV Dn Am MOV io8 Dm MOV d4 SP Dm MOV d8 An Dm MOV Dn io8 MOV Dn d4 SP MOV Dn d8 Am ADD 4 Dm SUB Dn Dn d7 BRA d7 BEQ 07 47 d7 BCS 47 BLT 07 BLE d7 d4 BNE d4 MOVW DWn HA MOVW d11 BRA 911 BEQ d11 BNE 911 d11 BCS 011 BLT 411 BLE 411 MOV Dn Dm MOV 8 Dm BSET abs8 bp BCLR abs8 bp CMP 8 Dm MOVW abs8 Am MOVW abs8 DWm CBEQ 8 Dm d7 CMPW 16 DWm MOVW 16 DWm MOV Dn HA MOVW An abs8 MOVW DWn abs8 CBNE 8 Dm d7 CMPW 16 Am MOVW An DWm MOVW d4 SP Am MOVW d4 SP DWm POP Dn ADDW 4 Am
124. ort 8 output register POIN X 03F20 R Port 0 input register P1IN X 03F21 R Port 1 input register P2IN X 03F22 R Port 2 input register P6IN X 03F26 R Port 6 input register P7IN X 03F27 R Port 7 input register P8IN X 03F28 R Port 8 input register PAIN X 03F2A R Port A input register PODIR R W Port 0 direction control register P1DIR X 03F31 R W Port 1 direction control register Chapter 3 Port Functions Port Control Registers 41 Chapter 3 Port Functions 42 Port Control Registers Table 3 2 1 Port Control Registers 2 2 Name Address RAN Function P6DIR X 03F36 R W Port 6 direction control register P7DIR X 03F37 R W Port 7 direction control register P8DIR X 03F38 R W Port 8 direction control register 39 R W Port 1 output mode register PAIMD X OSF3A R W Port A input mode register POPLU X 03F40 R W Port 0 pull up control register P1PLU X 03F41 R W Port 1 pull up control register P2PLU X 03F42 R W Port 2 pull up control register PePLU 6 R W Port 6 pull up control register P7PLUD X 03F47 R W Port 7 pull up pull down control register P8PLU X 03F48 R W Port 8 pull up control register PAPLUD R W Port A pull up pull down control register FLOAT1 X 03F4B R W Pin control register 1 P1OUT P2OUT POIN 2 PODIR P1DIR P1OMD POPLU P1PLU P2PLU
125. put control Special function output data 00 02 10 P11 P12 P13 P14 Pull up Control bit POPLUO POPLU2 PIPLUO PIPLUI PIPLU2 PIPLU3 PIPLU4 resistor Register POPLU PIPLU control address X 03F40 X 03F41 o Control bit PODIRO PODIR2 PIDIRO PIDIRI PIDIR2 PIDIR3 PIDIR4 direction Register PODIR PIDIR control address X 03F30 X 03F31 Port Control bit POOUTO POOUT2 PIOUTO PIOUTI PIOUT2 PIOUT3 PIOUT4 tout Register POOUT PIOUT outpu address X 03F10 X 03F11 Port Control bit POINO POIN2 PIINO PIIN3 input Register POIN address X 03F20 X 03F21 Output Control bit SCOSBOM SCOSBTM format Register SCOMD3 control address X 03F53 Special function input Special function SBTO 21 TM3I TM4I Special Special sgoyrxb RMOUT Tmo TM30 function output Control bit scosBos SCOSBTS PIOTCO PI2TCO PI3TCO PI4TCO control 1 Register SCOMD3 PIOMD address X 03F53 X 03F39 Special Special RMOUT function function output Control bit scocmp RMOEN control 2 Register SCOCTR RMCTR address 03 54 X 3F89 Both TMORM flag of the RMCTR register and the flag of the PIOMD register are used to switch between remote co
126. r However pull up and pull down resistors cannot be mixed At reset the input mode is selected and pull up resistors are disabled high impedance output P70 and P71 pins do not exist for 42 SDIP package P71 pin does not exist for 44 QFP package either 1104 45 to 48 P80 to P87 LEDO to 7 I O port 8 6 to 13 PAO to PA7 Input to AN7 Input port A 8 bit CMOS tri state I O port Each individual bit can be switched to an input or output by the P8DIR register A pull up resistor for each bit can be selected individually by the P8PLU register When configured as outputs these pins can drive LED segments directly At reset the input mode is selected and pull up resistors for P80 to P87 are disabled high impedance output 8 bit input port A pull up or pull down resistor for each bit can be selected individually by the PAPLUD register However pull up and pull down resistors cannot be mixed At reset the PAO to PA7 input mode is selected and pull up resistors are disabled Pins 9 Chapter 1 Overview Table 1 3 1 Pin Function Summary 3 4 Pin No Name Type Dual Function Function Description 20 21 TXD RXD Output Input 5 00 SBIO PO1 UART transmit data output pin UART receive data input pin In the serial interface in UART mode these pins are configured as the receive data input pin and transmit data output pin
127. r Interup _ Interrupt 35 serial interrupt enable fag 120 X 3FE9 Disables to use AD V1 ADQ O ADIE AD X 3FEA Interrup level flag for Interrupt Interrupt 35 AD interrupt enable flag request fag 21 1 021 0 REDG2 IRQME IRQBIR X 3FEB IRQ2ICR Interuptlevel fag Inemup Inemup 34 for external interrupt valid edge fla enable flag request flag X 3FEC IRQ3ICR X 3FED Disables to use M X 3FEE 9 Interrupt level flag nempe Interupt 35 for timer 3 interrupt enable flag request flag TMAIE X 3FEF 9 Interrupt level fag Interrupt Interrupt 35 for timer 4 interrupt enable flag request flag e TMSIE 9 TMSICR Interuptlevel fag nenge 35 for timer 5 interrupt enable flag request flag 3FF1 Disables to use X 3FF2 9Disables to use E Summary of Special Function Registers 153 Chapter 10 Appendices Bit Symbol 4 Reference Address Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 Page X 3FEO Disables to use e WDIR x 3rE1 e9 NMICR Watchdog inerupt gt 34 requestfag IRQOLV1 IRQOLVO IRQOIE IRQOIR X 3FE2 9 IRQOIC
128. r SBTO is allocated as P02 This can be used as normal I O pin when the serial interface is not used 22 Buzzer 06 Buzzer output Piezoelectric buzzer driver pin The driving frequency can be selected in the range of fs 2 to fs 2 by the DLYCTR register Select output mode by the PODIR register and select buzzer output by the DLYCTR register When not used for buzzer output this pin can be used as a normal I O pin 24 RMOUT T O P10 Remote control transmit signal output pin Output pin for remote control transmit signal with a carrier signal Can be used as a normal I O pin when remote control is not used 26 to 28 TM2IO to TM4IO I O P12 to P14 Timer I O pins Event counter clock input pins overflow pulse output pins and PWM signal output pins for timer 2 to 4 To use these pins as event clock inputs configure them as inputs by the PIDIR register For overflow pulse and PWM output configure these pins as outputs by the P1DIR register When the pins are used as inputs pull up resistors can be specified by the PIPLU register When not used for timer I O these can be used as normal I O pins 10 Pins Chapter 1 Overview Table 1 3 1 Pin Function Summary 4 4 Pin No Name Type Dual Function Function Description 44 MMOD Input Test mode This pin sets the test mode switch input Must be set to L 29 0 32 IRQO to Input P20 Exter
129. r bit count with the SCOLNG2 to 0 flags of the serial interface 0 mode register 0 SCOMDO The transfer bit count can be set as 1 to 8 bits Specify whether the start condition is enabled or disabled with the SCOSTE flag of the SCOMDO register Specify the first bit to be transferred MSB first or LSB first with the SCODIR flag of the SCOMDO register Select the valid edge of the clock signal with the SCOCEI to 0 flags of the SCOMDO register When the clock source is an internal clock Select the clock source with the SCOCKI to 0 flags of serial interface 0 mode register 1 SCOMD1 Set the SCOCKM flag of the SCOMDI register specify whether or not the clock source frequency will be divided by 8 Select serial clock operation by setting the SCOSBTS flag of the serial interface 0 mode register 3 SCOMDJ2 to 1 Set the SCOSBTM flag of the SCOMD3 register Set bit 0 of the port 0 direction control register PODIR to the output mode Set bit 0 of the port 0 pull up resistor control register POPLU 7 8 9 10 11 12 When the clock source is an external clock SBTO pin input Set the SCOSBTM flag of the SCOMD3 register Set bit 2 of the PODIR register to input mode Set the POPLU register if necessary Select the SCOSBOM flag of the SCOMD3 register Select the SCOIOM flag of the SCOMD3 register Select serial communication by setting the SCOSBOS flag of the SCOMDS register to 1 Set transm
130. register that sets up wait count at a time of access to a base address of interrupt vector table and a special register zone 1 Memory control register MEMCTR 7 6 5 4 3 2 1 0 IOW1 IOWO IRWE at reset 11001011 Must be set to 11 IRWE Set software write for interrupt request flag Software write disable 0 Even if data is written to each interrupt control register the state of the interrupt request flag xxxIR will not change 1 Software write enable Must be set to 1 Must be set to 0 IVBA Base address setting for interrupt vector table 0 Interrupt vector base X 04000 1 Interrupt vector base 00100 IOW1 to 0 Number of wait cycles set when Bus cycle at accessing special register area 20 2 oscillation 00 No wait cycles 100ns 01 1 wait cycle 150ns 10 2 wait cycles 200ns 11 3 wait cycles 250ns Figure 2 3 1 Memory Control Register MEMCTR X 03F01 R W Chapter 2 Basic CPU Functions 2 4 Interrupts 2 4 1 Accepting and Returning from Interrupts In the MN101CO0 series when an interrupt is accepted the hardware pushes the program s return address and the PSW on to the stack and branches to the beginning address of the interrupt program specified by the interrupt vector table Operation when Interrupt is Accepted 1 stack
131. rom the stack SP 1 to 3 3 handy address register is pulled from the stack SP 4 5 4 SP is pulled SP 6 SP 5 Execution branches to the address indicated by the PC 32 Interrupts Chapter 2 Basic CPU Functions 2 4 2 Interrupt Sources and Vector Addresses In addition to reset there are 20 interrupt vectors that indicate the starting addresses of interrupt programs These vectors are located in the 80 byte ROM address area 04004 to 04053 Table 2 4 1 Interrupt Control Registers Vector Number Interrupt Source et Vector Address 0 Reset X 04000 1 Non maskable interrupt NMI 1 X 04004 2 External interrupt 0 IRQ0 IRQ0ICR X 03FE2 X 04008 3 External interrupt 1 IRQ1 IRQ1ICR X 03FE3 X 0400C 4 Reserved X 03FE4 X 04010 5 Reserved X 03FE5 X 04014 6 Timer 2 compare match TM2IRQ TM2ICR X OSFE6 X 04018 7 Time base period TBIRQ TBICR X 03FE7 X 0401C 8 SCO transfer complete SCOIRQ SCOICR X 03FE8 X 04020 9 Reserved X 03FE9 X 04024 10 A D conversion complete ADIRQ ADICR X 04028 11 External interrupt 2 IRQ2 IRQ2ICR X OSFEB X 0402C 12 External interrupt 3 IRQ3 IRQ3ICR X 03FEC X 04030 except for 48 QFH 13 Reserved X 03FED X 04034 package 14 Timer 3 compare match TM3IRQ TM3ICR X 03FEE X 04038 15 T
132. s Measured under conditions of Ta 25 C and no load L is measured under the The supply current during operation 1 following conditions After all I O pins are set to input mode and the oscillation is set to NORMAL mode the MMOD pin is fixed at V fixed at V p and a 20MHz 8 39 2 square wave of amplitude V to the OSCI pin The supply current during operation I the input pins are p 18 input 1 Measured under the following conditions After all I O pins are set to input mode and the oscillation is set to SLOW mode the MMOD pin is fixed at the input pins are fixed at ss and 32 768kHz square wave of amplitude V V is input to the XT pin DD is measured under the The supply current during HALT mode following conditions After all I O pins are set to input mode and the oscillation is set to lt HALT mode the MMOD pin is fixed at V at V the input pins are fixed and an 32 768kHz square wave of amplitude is input to the XI DD DD pin The supply current during STOP mode I is measured under the following ullus conditions After the oscillation mode is set to STOP mode the MMOD pin is fixed at the input pins are fixed at and the OSCI and XI pins are DD unconnected The items I I 1 are applicable only for 48 pin QFH package 5 DD6 7 DD8 Ch
133. s 30 Fig 1 5 5 us 28 Fall time tfs 30 ts ie tis gt M Eu Po Sa Dar 1 a ee TN at Ee Input voltage level 1 MICE LL P Sesia regeo Ehn VpHH Input Input voltage level 2 Output Figure 1 5 5 Operation of AC Zero Cross Detection Circuit 40 to 85 V 2 0 to 5 5V V 0V 7 Rating Parameter Symbol Conditions Unit MIN MAX Input pin 4 7 29 Input high voltage 1 Vas 0 8V gt Vipa 30 Input high voltage 2 Vi Vo 4 5 to 5 5V 07V p Mops 31 Input low voltage 1 Vis 0 02 32 Input low voltage 2 Vi Vo 4 5 to 5 5V 0 0 3 33 Input leakage current Lo VIN 0to V 22 HA Vpp 5V Vin 1 5V 34 Input high current Ius Pull up resistor ON 30 100 300 HA 35 Input low current Ls VOD 80 180 400 Pull down resistor ON Electrical Characteristics 19 Chapter 1 Overview Ta 40 to 85 C V 2 0to55V V 0V Rating Parameter Symbol Conditions Unit MIN TYP MAX pin 5 P27 RST 36 Input high voltage Yin 0 9V 37 Input low voltage Viz 0 02 38 Input leakage current T VIN 010 10 pA 5 Vin 1 5V 39 Input high current ih pias 30 100 300 pA pin 6 POO to
134. s impermeable to UV rays to the glass sections at the top and side sections of the CPU PX AP101C11 SDC PX AP101C11 FBC 2 Due to device characteristics of the MN101CP11XXX a writing test cannot be performed on all bits Therefore storage of the written data cannot be guaranteed in some cases 3 When program is written verify that Vc power supply 6V is connected before applying the Vpp power supply 12 5V Disconnect the Vpp supply before disconnecting the Vcc supply 4 Vpp should never exceed 13 5V including overshoot 5 If a device is removed while a of 12 5V is applied device reliability may be damaged 6 At CE VIL do not change Vpp from VIL to 12 5V or from 12 5V to VIL 7 From the time after a program is written until just before mounting storage at a high temperature is recommended Program Read High temperature storage 125 C 48H Read Mounting EPROM Versions 131 Chapter 8 Appendices 132 EPROM Versions 8 1 3 Erasing Written Data in Windowed Packages PX AP101C11 SDC PX AP101C11 FBC In an internal EPROM with windowed packaging data is erased 0 1 when UV light at 253 7nm permeates the window to irradiate the chip The recommended exposure is 10W s cm This coverage can be achieved by using a commercial UV lamp positioned 2 to 3cm above the package for 15 20 minutes when the illumination intensity of the package surfac
135. se request the most recent option list from the sales office Option of this product is used a part of the built in ROM When placing an order for programme please sed data on the address of the option Chapter 1 Overview 23 Chapter 1 Overview 1 7 Outline Drawings Package code SDIP042 P 0600 Unit mm SEATING PLANE Symbol y Mn Non Mex A J 40 43 46 A jJ 130 31 33 35 b o9 10 11 04 os 06 p2 _ lt 025 025 045 O 367 370 373 E 128 130 13 2 178 fp 1 524 __ J 30 33 36 jJ 15 l Body Material Epoxy Resin Lead Material Fe Ni Lead Finish Method Soldering dip Figure 1 7 1 42 SDIP using this product please obtain product specifications from the sales The external dimensions of the package are subject to change Before a office 24 External Dimensions Chapter 1 Overview Package code QFP044 P 1010 12 30 0 40 10 00 020 10 00 2020 2 00 0 20 2 10 0 30 1 15 20 20 0 60 20 SEATING PLANE Unit mm 1 JT Body Material Epoxy Resin Lead Material Fe Ni Lead Finish Method Soldering dip Figure 1 7 2 44 QFP The external dimensions of the package are
136. sign imm8 SP 41 2 1111 1100 lt 8 gt 7 67 ADDW imm16 SP SP imm16 SP 71 4 0010 1111 1100 6 gt 67 ADDW imm16 DWm DWm imm16 DWm 4 0010 0101 0104 H6 um 68 ADDUW ADDUW Dn Am Am zero Dn gt Am 606668 3 3 0010 1000 1aDn 8 69 ADDSW ADDSW Dn Am Am sign Dn gt Am O 0010 1001 1aDn 70 SUB SUB Dn Dm when Dm Dn 5 Dm 2 0010 1010 71 SUB Dn Dn 0001211 1000 01Dn 71 SUB imm8 Dm Dm imm8 Dm 3 0010 1010DmDm lt 8 gt 72 SUBC SUBC Dn Dm Dm Dn CF Dm 5 O 0010 1011 78 SUBW SUBW DWn DWm DWm DWn DWm 0000 0010 0100 00Dd 1 74 SUBW DWn Am Am DWnAm 00006 53 0010 0100 10Da 74 SUBW imm16 DWm DWm imm16 DWm 4 0010 0100 0104 lt 16 gt 75 SUBW imm16 Am Am imm16 Am 0000 7 4 0010 0100 011a lt 16 gt 75 MULU Dn Dm Dm Dn DWk 0 0010 1111 1110 4 76 DIVU DIVU Dn DWm DWm Dn DWm DWm h 00005 s 0010 1110 111d 5 77 Dn Dm Dm Dn PSW eoeo 9 2 0011 0010 DnDm 78 imm8 Dm Dm imm8 PSW 0000 2 1100 00Dm lt 8 gt 78 imme8 abs8 mem8 abs8 imm8 PSW 0000 0000 0100 abs 8 5 8 gt 79 imm8 abs12 mem 8 abs12 imm8 PSW 0000 0101 abs 12 gt lt 8 gt 79 imm8 abs16 memB8 abs16 imm8 PSW 0000 5 0011 1101 1000 lt abs 16 gt lt gt 80 CMPW CMPW DWn DWm DWm DWn PSW 0 000 53 0010
137. size of 1 to 8 bits can be selected 10 bits x 8 channels LED driver function 8 pins Ports I O ports 25 ports 8 have dual functions LED large current driver ports 8 ports push pull configuration Input ports 11 ports all have dual functions Number of pins with dual function for external interrupts 3 One of which can also be used for zero cross input Number of pins with dual function for A D input 8 Operation mode input pin 1 Reset input pin 1 Operation modes NORMAL mode Package SLOW mode HALT mode STOP mode and switches operating clock 42 SDIP 44 QFP 48 QFH 1 3 Pins 1 3 1 Pin Diagram TXD SBOO P 00 RXD SBIO P01 SBTO P026 BUZZER P06 RMOUT P 10 gt P116 TM2IO P 126 13 gt TM4IO P 146 IRQO P 206 GTT LTLDTOTNW 55 sc1 SC2 De 7 7 6 6 5 5 4 AN4 3 AN3 1 0 AN0 0 LED0 6811 201 22 202 683 203 64 4 65 205 66 1 206 871 207 Figure 1 3 1 Pin Diagram 42 SDIP TOP VIEW Chapter 1 Overview Pins 5 Chapter 1 Overview 6 Pins AN1 PA1 gt lt gt P84 LED4 lt gt P85 LED5 lt gt P86 LED6 P63 629 619 60 MN101C117 115 7 00 000 e 0 800 8 14 TM410 9 13 TM310 10 12 TM210 11 23 11 1000298886538 n OO Sc Omk u lt mu
138. t 8 Write lL Read 8 Reset R Port output data Pm Write L N Z Read 777 Schmidt trigger input Port input data lt 4 CN Read P60 P61 P62 P63 P64 P65 P66 P67 Pull up Control bit P6PLUO P6PLU2 P6PLU3 P6PLU4 P6PLUS P6PLU6 P6PLU7 resistor Register P6PLU control address x 03F46 yo Control bit P6DIRO P6DIRI P6DIR2 P6DIR3 P6DIR4 P6DIRS P6DIR6 P6DIR7 direction Register P6DIR control address x 03F36 Control bit PEOUTO P6GOUT 1 P6OUT2 P6OUT3 PGOUTA 5 P6OUT6 P6OUT7 Port output Register P6OUT address x 03F16 Control bit P6INO P6IN2 P6IN3 P6IN4 P6INS P6IN6 P6IN7 Port input Register P6IN address x 03F26 Figure 3 3 8 Configuration and Functions of P60 to P67 P80 P81 P82 P83 P84 P85 P86 P87 Pull up Control bit PSPLUO PSPLUI P8PLU2 P8PLU3 P8PLU4 P8PLUS P8PLU6 P8PLU7 resistor Register P8PLU control address x 03F48 VO Control bit P8DIRO P8DIR1 P8DIR2 PSDIR3 P8DIR4 P8DIR5 P8DIR6 P8DIR7 direction Register P8DIR control address x 03F38 Control bit PSOUTI PSOUT2 PSOUT3 PSOUT4 PSOUTS P8OUT6 PSOUT7 Port output Register P8OUT address 03 18 Control bit 8 P8IN2 P8IN3 P8IN4 P8IN5 P8ING PSIN7 Port input Register PSIN address x 03F28 54 Port Configuration and Functions Figure 3 3 9 Configuration
139. t operation of timer 4 2 Use TMACK to 0 flags of the TM4MD register to select fosc 15 4 18 16 as the clock source 3 Use the T4ICTS1 and T4ICTSO flags of the TM4MD register to select IRQ2 IRQI or IRQO as the input capture trigger 4 Set the REDGn flag of the external interrupt control register to specify the valid edge for the interrupt selected as the TM4 input capture trigger 5 Set the TM4PWM flag of the TMAMD register to 1 to select 16 bit timer operation 6 Set a value in compare register 4 TMAOCH TMAOCL 7 Set the TMAEN flag of the register to 1 to start the timer 8 When timer 4 begins operation binary counter 4 will count upward from X 0000 Setting a value in compare register 4 clears binary counter 4 until it reaches the value set in compare register 4 9 If the binary counter is to be used as a free running counter that counts from X 0000 to X FFFF set the compare register 4 to X FFFF When the value of binary counter 4 matches that of the TMAOCH TM4OCL register the timer 4 interrupt request flag is set binary counter 4 is reset to X 0000 and counting begins again 10 If the external interrupt selected as the input capture trigger is received during timer 4 operation the value of binary counter 4 will be written into the input capture If the event occurs before a read register TM4ICH that data will be overwritten 16 bit Timer Operation
140. t 1 pull up resistor ON OFF control 150 Summary of Special Function Registers Chapter 10 Appendices Bit Symbol i Reference Aadress Bit7 Bite Bits Bit2 1 Bito Page P2PLU2 P2PLU1 P2PLUO X 3F42 Port 2 pull up resistor ON OFF contro 420 45 X 3F43 Disables to use X 3F44 Disables to use E X 45 Disables to use ES P6PLU7 P6PLU6 P6PLU5 P6PLU3 P6PLU2 P6PLU1 P6PLUO X 3F46 9 PGPLU 421 45 Port 6 pull up resistor ON OFF control P7PLUDO X 3FA7 P7PLUD 420 45 resistor ON OFF control P8PLU7 P8PLU6 P8PLU5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 P8PLUO X 3F48 9 Port 8 pull up resistor ON OFF control 42 45 PAPLUD7 PAPLUDG PAPLUD5 PAPLUD4 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUDO X 3FAA PAPLUD 421 45 Port A pull up pull down resistor ON OFF control P21M PARDWN P7RDWN X 3FAB 9 FLOATI P21inpu Port A pullp ort 7 420 46 mode selection pulldown sel pulldown sel X 4 Disables to use E SCOCEO SCOCE1 SCODIR SCOSTE SCOI tG2 SCOLNG1 SCOLNGO X 3F50 9 SCOMDO Receive data input Statbisetup ynchrouou serial i 108 Transmit data output edge fortansmi select Transfer
141. t at the reset terminal takes place at the next WDT interrupt Chapter 4 Timer Functions 4 7 Remote Control Output Operation 4 7 1 Overview remote control carrier pulse can be generated using the overflow of timer 3 Two duty ratios of 1 2 or 1 3 can be selected 4 7 2 Setup and Operation 1 Set the RMOEN flag of the remote control carrier output control register RMCTR to 0 so that the remote control carrier output is switched off 2 Set timer 3 to select the base period of the remote control carrier the width that the remote control carrier output pulse is held at a high level Set bit 0 of the PTOMD register to 3 Set the RMDTYO flag of RMCTR register to select the carrier duty dh A ne same Tie remore 4 Set the P10 d Q and set P10 to th d selectth control output is switched on and 4 et the output data to and set to the output mode And select the remote je ulcer the saine de remite control carrier output by setting the TMORM flag of the RMCTR register to 0 control output is switched off 5 The RMOEN flag of the RMCTR register controls whether the remote control carrier output is on or off Even if the carrier output is at a high level and the RMOEN flag is set to 0 off the carrier waveform will be maintained by the synchronous circuit Base period set by RMOEN Output on
142. t condition is enabled or disabled with the SCOSTE flag of the SCOMDO register Specify the first bit to be transferred MSB first or LSB first with the SCODIR flag of the SCOMDO register Select the valid edge of the clock signal with the SCOCEI to 0 flags of the SCOMDO register When the clock source is an internal clock Select the clock source with the SCOCKI to 0 flags of serial interface 0 mode register 1 SCOMD1 Set the SCOCKM flag of the SCOMDI register to specify whether or not the clock source frequency will be divided by 8 Select serial clock pin operation by setting the SCOSBTS flag of the serial interface 0 mode register 3 SCOMD3 to 1 Set the SCOSBTM flag of the SCOMD3 register Set bit 2 of the port 0 direction control register PODIR to the output mode PO2 SBTO output mode If necessary set bit 2 of the port 0 pull up resistor control register POPLU to add the pull up resistor When the clock source is an external clock SBTO pin input Set bit 2 of the PODIR register to the input mode necessary set bit 2 of the POPLU register Select the SCOIOM flag of the SCOMD3 register Select serial communication by setting the SCOSBIS flag of the SCOMD3 register to 1 Reception data wait When the serial reception begins the SCOBSY flag of the serial interface 0 control register SCOCTR is set to 1 indicating that a serial transfer is in progress When the serial reception is
143. t enable flag request flag 9 X 3FF0 9 5 Interrupt level fag Interrupt Interrupt 35 for timer 5 interrupt enable flag request 1 Disables to use X 3FF2 Disables to use E 154 Summary of Special Function Registers MN101C115 117 LSI User s Manual August 1999 1st Edition Ist Printing Issued by Matsushita Electric Industrial Co Ltd Matsushita Electronics Corporation Matsushita Electric Industrial Co Ltd Matsushita Electronics Corporation Semiconductor Company Matsushita Electronics Corporation Nagaokakyo Kyoto 617 8520 Japan Tel 075 951 8151 http www mec panasonic co jp SALES OFFICES U S A SALES OFFICE Panasonic Industrial Company PIC New Jersey Office 2 Panasonic Way Secaucus New Jersey 07094 Tel 201 392 6173 Fax 201 392 4652 Milpitas Office 1600 McCandless Drive Milpitas California 95035 Tel 408 945 5630 Fax 408 946 9063 Chicago Office 1707 N Randall Road Elgin Illinois 60123 7847 Tel 847 468 5829 Fax 847 468 5725 Atlanta Office 1225 Northbrook Parkway Suite 1 151 Suwanee Georgia 30174 Tel 770 338 6940 Fax 770 338 6849 San Diego Office 9444 Balboa Avenue Suite 185 San Diego California 92123 Tel 619 503 2940 Fax 619 715 5545 CANADA SALES OFFICE Panasonic Canada Inc PCI 5700 Ambler Drive Mississauga Ontario LAW 2T3 Tel 905 624 5010 Fax 905 624 9880 GERMANY SALE
144. ter lower 8 bits X O3F67 Input capture register upper 8 bits TM4MD X O3F84 Timer 4 mode register TM5OC X OSF78 Compare register 5 TM5BC X O3F68 Binary counter 5 TM5MD X O3F88 Timer 5 mode register WDCTR X O3F02 Watchdog timer control register DLYCTR X O3F03 Oscillation stabilization wait control register RMCTR X OSF89 Remote control carrier output control register R W Readable and writable R Readonly Overview 81 Chapter 4 Timer Functions 4 9 2 Programmable Timer Counters Timers 2 5 all contain a programmable 8 bit timer counter 16 bit in timer 4 Programmable timer counters consist of a compare register and a binary counter 1 Compare register 2 2 7 6 5 4 3 2 1 0 20 7 20 6 20 5 20 4 20 3 TM20C2 20 1 TM20C0 at reset undefined Figure 4 9 1 Compare Register 2 TM2OC X 03F72 R W 2 Binary counter 2 TM2BC 7 6 5 4 3 2 1 0 2 7 TM2BC6 esos TM2BC4 TM2BC2 2 1 TM2BCO reset 00000000 Figure 4 9 2 Binary Counter 2 TM2BC 03 62 3 Compare register 3 TM3OC 7 6 5 4 3 2 1 0 TM30C7 TM30C6 5 TM30C4 nos 30 2 TM30C0 reset undefined Figure 4 9 3 Compare Register TM3OC X 03F 73 4 Binary counter 3 TM3BC 7 6 5 4 3 2 1 0 TM3BC7
145. th other bits the switching operation may cause binary counter 2 to be incremented If the value of TM2OC register is overwritten while timer 2 has stopped counting binary counter 2 will be reset to X 00 at the edge of next count clock The value of TM3CKO0 2 of T3MD register is unsettled If timer2 timer 3 is independently used any mode except cascade connection should be set 8 bit Timer Operation timers 2 3 63 Chapter 4 Timer Functions If TM2IO input is selected as the clock source and the value of binary counter 2 is to be read during X operation select synchronized TM210 input to avoid reading data that may be incomplete during count up transitions However with synchronized TM210 input it is not possible to return from STOP HALT modes 64 E Event Count Function timers 2 3 Settings for the event count function are listed below Timer 2 is used as an example 1 2 3 4 5 6 7 Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the count operation of timer 2 Use the TM2CK2 to 0 flags of the TM2MD register to select TM2IO input or synchronous TM2IO input as the clock source Set the TM2PWM flag of the TM2MD register to 0 so that normal timer operation is selected Set a value in compare register 2 TM2OC Set the TM2EN flag of the TM2MD register to 1 to start the timer When timer 2 begins operation binary counter 2 will count upward from 00 W
146. tuo USNE eg Figure 1 3 2 Pin Diagram 44 QFP TOP VIEW lt gt P27 NRST lt gt 84 04 lt gt P85 LED5 lt gt P86 LED6 lt gt 87 07 lt gt 71 gt P70 MMOD 101 117 115 30 00 0009 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 TXD SBOO P 00 RXD SBIO P01 SBTO P 02 BUZZER P 06 RMOUT P10 Figure 1 3 3 Pin Diagram 48 QFH TOP VIEW Chapter 1 Overview 1 IRQ1 SENS 0 800 4 TM4I0 13 TM310 12 TM210 11 Pins 7 Chapter 1 Overview 1 3 2 Pin Function Summary The pin numbers in the list correspond to the QFH package Refer to Figure 1 3 3 Pin connection Be careful when using SDIP and QFP packages Table 1 3 1 Pin Function Summary 1 4 Pin No Name Type Dual Function Function Description 17 14 VSS VDD Power supply pins Apply 2 0V to 5 5V to VDD and to VSS 16 15 18 19 43 20 to 23 OSCI OSC2 XI XO 00 to P02 Input Output Input Output I O 27 SBOO TXD Clock input pin Clock output pin Clock input pin Clock output pin Reset pin T O port 0 Connect these oscillation pins to ceramic or crystal oscillators for high speed clock operation If the clock is an external input connect it to OSC1 and leave OSC2 open The chip will not operate with an external clock when using either the STOP or SLOW modes Connect these oscillation p
147. y the falling edge or the rising edge of AC Zero cross detection output 10 ms at 50Hz 8 3 ms at 60Hz AC line waveform gt Ideal IRQ1 Actual IRQ1 Point Figure 7 2 1 AC Line Waveform and IRQ Generation Timing Actual IRQ interrupt requests will be generated multiple times Therefore the software must filter this signal before making any evaluations When noise filtering is selected for use the amount of evaluation processing by the software will be reduced However if the OSC stops a return from the backup mode will not be possible AC Zero Cross Circuit Operation 123 Chapter 7 AC Zero Cross Circuit Noise Filter 7 3 Noise Filter 7 3 1 Overview External interrupt pins IRQO and IRQ1 contain noise filtering circuit This circuitry can be used for remote control signal reception Data bus NFCTR NFOEN IRQO External interrupt 0 f B NFIEN_ Z IRQ1 External interrupt 1 f 2 8 i NN MUX 15 2 52 Y P20 IRQO gt filter MUX 1 IRQO interrupt Y fs 2 8 NEN fs 27 1 20 Y P21 IRQ1 SENS 25 5 Noise filter mux To IRQ1 Fig 7 1 1 interrupt Figure 7 3 1 Noise Filtering Circuit Block Diagram

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