UM10319 Cake8026_02_D
Contents
1. Read 40h 08h SUPL To be performed only if INT amp 10h 10h The IRQN line goes HIGH Insert a smart card in slot 1 The IRQN line goes LOW 12 Write 00h 48h ACK 12 Read 42h INT 01h Write 01h 48h ACK This read is performed because INT amp 01h 01h FC Read 40h 2 and Bit PRES has changed and is now 1 The IRQN line goes HIGH UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 16 of 27 NXP Semiconductors UM1 031 9 Cake8026 02 D Table 10 Manage the shutdown mode SDWNN must be connected to a host output Action Command Result Comment Power up and clear the pending interrupts may be done automatically by the interrupt service routine Be ne Ded ARR This instruction is just used to check that the TDA826 is awake and Read 40h Cth answers Pull the SDWNN line to GND The TDA8026 is in shutdown mode 12C Write 00h 48h NACK No ACK neither answer from the TDA8026 meaning that it is indeed in I C Read 40h shutdown mode Insert a card in slot 1 The IRQN line goes LOW No interrupt is pending This information is given to inform about the card insertion but the TDA8026 is still in shutdown mode Set the SDWNN line to VDDI The IRQN line goes HIGH The TDA8026 is being reset The IRQN line goes LOW End of the TDA8026 reset Clear the p2. advised of the possibility of such damages Notwithstanding any damages that customer might incur for any reason whatsoever including without limitation all damages referenced above and all direct or general damages the entire liability of NXP Semiconductors its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars US 5 00 The foregoing limitations exclusions and disclaimers shall apply to the maximum extent permitted by applicable law even if any remedy fails of its essential purpose 8 3 Trademarks Notice All referenced brands product names service names and trademarks are property of their respective owners NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 26 of 27 NXP Semiconductors UM10319 Cake8026 02 D 9 Contents 1 Introduction Enan 3 1 1 8 2 3 1 2 Cake8026 02 0 3 2 Configuration cessere 4 2 1 Power 44040 4 2 2 a S 5 2 3 DCDC CTRL 6 2 4 SPRES is 25526 7 3 Connection to the 8 4 Connection to a mother board 11 4 1 Conn
3. 03082 801 BRS IE 101 57405 t BST 4 58 RST3 TPI8e R 511 C81 c81 RSI3 RST3 QK3 190 301K3 m aki rsi2 ee 9512 103 TP20e lt _ 103 zr x 4 C41 a FS JOLK3 vece TP216 VCC 7 RSTI E gt RSTI CLK RST2 TP220 lt RST 2855 SS are Teese Kho 2845455584552456 a Comm wor PRES2TP26 ERES Sr leage IS 16 R118 ejz TP296 JCLK1 t BRS al t4 TP306 lt C41 CGND1 TP319 7 0 01 101 29 lt 7101 BRS C8 TP33e C81 T 517 349 PRE S1 oC5I cto lt I vec3 7 C61 caro lt 18513 13 gt ati carm 2013 DI PRLLS817 cach PIN H3 PRESS 2 io pee CGND2 pe CGND 7 2 SAM3 pei 2 47 1 2 R140 CCM03 3154 2051 Cie lt vecs Y acsi Cile C6 21 lt I RSTS 3 al Cla 105 gt oC C310 10105 104 gt gt ati 319 PRESS Fig 7 Cake8026 02 D schematic UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 18 of 27 NXP Semiconductors UM10319 Cake8026 02 D 7 Annex Layout and Components UM10319 User manual The board Layout and the equipment views are given in the next 6 pages The board has 4 layers named TOP GND POWER and BOTTOM The GND and POWER layers are internal and the BOTTOM layer is seen in transparency T
4. 4 D m H ho Gv 21 M F Biz pp 7e22 Q m o JPISTPISTPI2 O Fig 12 Cake8026 02 D layout Components TOP ge goo OOO OO All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved UM10319 User manual Rev 1 0 4 August 2011 24 of 27 NXP Semiconductors U M1 031 9 Cake8026 02 D L1 D D D D Fig 13 TDA8026 02 D layout Components BOTTOM UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 25 of 27 NXP Semiconductors UM10319 8 Legal information Cake8026 02 D 8 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 8 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and sha
5. 6 02 D 2 4 SPRES SPRES is used to choose the polarity of the smart card connector on slot 1 as described below Connecting ST10 SPRES 1 O normally closed card connector Connecting ST11 SPRES 0 normally open card connector The default value for this board is SPRES 0 as the default card connector type is normally open wy QO B00 30 moo a ni HI TPS OQ O Nooo Fig 4 8026 02 D SPRES configuration All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 7 of 27 NXP Semiconductors UM10319 3 Connection to the host Cake8026 02 D To start using the TDA a few wires are required Then the other wires can be added to evaluate more features of the TDA8026 The following tables give a summary of the connections to make in order to achieve a specific goal Please note The ground connection is not mentioned in the tables but shall always be connected between the host board and the Cake8026 02 D board Table 1 Connection to access the TDA8026 registers Cake8026 pin Host connection Cake 8026 pin TDA8026 application position example VDD VDDI Microcontroller power J3 1 and J2 1 or Read the product supply VDD and version VDDI test pin Check the pending SDA Master SDA pin J1 1 or SDA test pin 1 eck the ca
6. 7 NXP Semiconductors UM10319 UM10319 Table 5 Handle the TDA8026 s shutdown mode Cake8026 02 D Cake8026 pin VDD VDDI SDA SCL IOUC1 CLKIN1 IOUC2 CLKIN2 IRQN SDWNN Host connection Microcontroller power supply Master SDA pin Master SCL pin Host s ISO 7816 UART I O line Host s ISO 7816 UART CLK line Host s ISO 7816 UART I O line IOUC1 and IOUC2 can be connected together Host s ISO 7816 UART CLK line CLKIN1 and CLKIN2 can be connected together Microcontroller s external interrupt input Any microcontroller s output Cake8026 pin position J3 1 and J2 1 or VDD and VDDI test pin J1 1 or SDA test pin J1 3 or SCL test pin J2 3 or IOUC1 test pin J2 5 or CLKIN1 pin J1 5 or IOUC2 test pin J1 7 or CLKIN2 test pin J2 7 or IRQN test pin J3 6 or SDWNN test pin TDA8026 application example Put the TDA8026 in shutdown mode Insert a card and wake up the TDA8026 See Table 10 in chapter 5 TDA8026 application examples All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 10 of 27 NXP Semiconductors UM1 031 9 Cake8026 02 D 4 Connection to a mother board The Cake8026 02 D board has 4 connectors soldered on the bottom side They can be used to plug the Cake on a dedicated mother board with respect to the co
7. 8 and 679 Connecting ST8 AO 1 TDA8026 s addresses 4Ch 44h and 46h Connecting ST9 AO 0 TDA8026 s addresses 48h 40h and 42h 2 r c OO OO BB 1 B BOO 2 244 ww TT gn Q 7 e niu Ono vi c5 ET Oo TPS a En 123 TP A qi Om 3 in 2 Tee go r B OEO COD z HI zT O Fig 2 8026 02 D 0 configuration All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 5 of 27 NXP Semiconductors UM1 031 9 Cake8026 02 D 2 3 DCDC CTRL The DCDC CTRL pin allows enabling or disabling the DCDC converter It can be selected by soldering ST5 or ST7 Connecting ST5 DCDC_CTRL 1 0 DCDC disabled Connecting ST7 DCDC_CTRL 01 DCDC enabled 39 B Oooo OOOO M B TPE ae mer xv Hz ce Eu 9 n z GB ob ga uj Dg m B x 1P6 1 z0 pic TPIS gare rt s disabled 0000 Fig 3 8026 02 DCDC CTRL configuration UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 6 0f 27 NXP Semiconductors UM1 031 9 UM10319 Cake802
8. NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductor
9. UM10319 Cake8026 02 D Rev 1 0 4 August 2011 User manual Document information Info Content Keywords TDA8026 Demo Board Absiract This user manual describes how to use the Cake8026 02 D a demo board used to evaluate the TDA8026 device a 5 slots smart cards reader NXP Semiconductors UM1 031 9 Cake8026 02 D Revision history Rev Date Description 1 0 20110804 First version Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 2 of 27 NXP Semiconductors UM1 031 9 Cake8026 02 D 1 Introduction 1 1 TDA8026 The TDA8026 is 5 slots smart card reader interface It is mainly dedicated to Point Of Sales applications with one or two main slots for customer card and 4 or 3 extra slots for Secure Access Modules 1 2 Cake8026 02 D The demo board Cake8026 02 D is an evaluation board for the TDA8026 It allows testing the main functionalities of the TDA8026 This board embeds all the mandatory components to design the TDA8026 so that the user just need to connect the interface with its host to start developing applications based on the TDA8026 On this demo board the slot 1 can receive a general banking sized smart card while the slots f
10. and activation APDU transmission on IOUC1 The APDU is transmitted to the smart card 1 an answer is received on 101 The answer can be read on IOUC1 12 Write 05h 40h ACK Disable I O on slot 1 keep card activated at 5 V 12C Write 04h 48h ACK Select slot 4 12 Write 45h 40h ACK Enable I O line on slot 4 keep selection and activation APDU transmission on IOUC2 The APDU is transmitted to the card on 04 an answer is received 104 The answer can be read on IOUC2 UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 15 of 27 NXP Semiconductors UM1 031 9 Cake8026 02 D Table 9 Manage the interrupt IRQN must be connected to the host external interrupt input Action Command Result Comment Power up the TDA8026 The IRQN line goes HIGH with the power supply and then goes LOW Write 00h 48h ACK 12C Read 42h INT 1Fh IC Write 01h 48h ACK To be performed only if INT amp 01h 01h 12C Read 40h 08h SUPL 12C Write 02h 48h ACK To be performed only if INT amp 02h 02h 12C Read 40h 08h SUPL 12C Write 03h 48h ACK To be performed only if INT amp 04h 04h 12C Read 40h 08h SUPL 12C Write 04h 48h ACK EC Read 40h 08h SUPL To be performed only if INT amp 08h 08h Write 05h 48h ACK lC
11. e 00h 48h 12C Read 42h 12 Write 01h 48h IC Read 40h Insert a card in slot 1 Read 40h 12C Read 40h ACK from the TDA 00h ACK 00h 03h 01h Selection of the general registers All the pending interrupts have been cleared Select slot 1 No card is inserted Bit PRES 1 and bit PRESL 1 PRESL informs that bit PRES has changed PRESL is automatically reset after the read Bit PRES 1 The card is present UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 13 of 27 NXP Semiconductors UM1 031 9 Cake8026 02 D Table 7 Access slot 1 and CLKIN1 must be connected to the host ISO 7816 UART Action Command Result Comment Power up and clear the pending interrupts by reading each slot s 40h Insert card and clear the interrupt by reading the slot 1 40h 12C Write 01h 48h ACK Select slot1 IC Write 45h 40h ACK Enable I O line on slot1 select 5V activation and set START bit The smart card in slot 1 is activated The ATR is received on 101 The ATR is transmitted to the host through IOUC1 12C Write 47h 40h ACK IO enabled 5V card selected WARM 1 START 1 warm reset is performed on smart card 1 The ATR is received on 1 The ATR is transmitted to the host through IOUC1 APDU transmission on IOUC1 The APDU is transmitted
12. e the addresses are given numerically as 48h for bank 0 and 40h and 42h for bank 1 If AO is connected to VDDI AO 1 the addresses must be replaced by 4Ch 44h and 46h respectively Access TDS8026 s registers These applications can be achieved only with the power supply and the bus connected Action Command Power up 12C Write 00h 48h 12C Read 48h I C Read 40h 12C Read 42h 12 Write 01h 48h lC Read 48h IC Read 40h IC Read 40h 12C Write 02h 48h IC Read 40h Result ACK from the TDA 00h Cih 1Fh ACK from the TDA 01h 08h 00h ACK from the TDA 08h Comment Power up the TDA with VDD and VDDI The host writes 00h at address 48h The address and the value are acknowledged by the TDA Confirmation that the write command worked The written value 00h is read back The value read is the TDA8026 s version The first read to this address after power up gives 1Fh meaning that the 5 slots have an information to give Slot 1 selection The TDA8026 acknowledges the address and the data Confirmation that the write command worked The slot 1 is now selected The SUPL bit in slot 1 is set It is automatically cleared after the read The SUPL bit in slot 1 has been cleared Slot 2 selection The SUPL bit in slot 2 is set It is automatically cleared after the read Read SUPL bits for slots 3 to 5 as done for the slots 1 and 2 above 12 Writ
13. ections sess 11 4 2 12 4 3 Auxiliary smart card reader 12 5 TDA8026 application examples 13 6 Annex A Schematic 18 7 Annex B Layout and Components 19 8 Legal information 26 84 26 8 2 Disclalmmers 2 26 8 3 26 9 cu m 27 Please be aware that important notices concerning this document and the product s described herein have been included in the section Legal information NXP B V 2011 All rights reserved For more information visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 4 August 2011 Document identifier UM10319
14. eft unconnected Otherwise if AO and SPRES configuration solder points are not used the values can be configured outside on the mother board The good value must be input on the AO and SPRES pins on the connector J3 Auxiliary smart card reader An auxiliary device to read an extra smart card can be connected on the mother board sharing eventually the IOUC and CLKIN lines with the TDA8026 In this case the INTAUXN input of the TDA8026 available on J3 4 can be used to connect the interrupt output of the auxiliary device This enables the microcontroller to manage only one external interrupt for both smart card reader devices See TDA8026 s data sheet and application note AN10724 for details about management of this auxiliary interrupt All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 12 of 27 NXP Semiconductors UM10319 Cake8026 02 D 5 TDA8026 application examples Table 6 When the demo board is connected to the host it is possible to access the TDA8026 and test different features The access to the TDA is made with a standard I C protocol In the following examples the host is the master meaning that a write is a data write from the host to one of the TDA8026 s registers and a read is a TDA8026 s register read by the host The AO input of the TDA8026 is assumed to be 0 LOW level Therefor
15. ending interrupts as it is done after a power up Write 00h 48h ACK Check that the TDA8026 is available for communication Read 40h Cih UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 17 of 27 NXP Semiconductors U M1 031 9 Cake8026 02 D 6 Annex A Schematic TP46 00 yoo 03082 881 P46 ST r 100ni 01 2251 gt gt 0011 Celo CONDI RSTIL gt oti 061o CLK IC gt acil Clo 1101 Cat 1681 2 4 0 lt 5 100 2 TPG CLKIN2 TPS 001 TPT SDA wor yoo yoo 2 cig 100nF 100 g 102 CLKIN2 CLKIN lt J IQUC1 lt 110022 2 22 3 4 les los 5 5 wo l n BAS ie c Bs S vees TPS veces gt PRESS S dris BRS re Tigo REIS vtt 51 C SCL er Q5 IPITe GLKS SDA C gt SDA 55 105 TP12e 1105 INTAUXn DZ INTAUXN 2 5 weca TP13 lt 3 VCCA 2943 on TDA8826ET lt 2 4 8574 TP14e JRST4 no 45 E pes EE pee e ie eis Oe ols gt 2 NDC 28 gouge ee 119 lt 1 93
16. he components placement is given for both TOP and BOTTOM sides All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved 19 of 27 Rev 1 0 4 August 2011 UM10319 NXP Semiconductors Cake8026 02 D 20 of 27 n provided in this document 15 subject to leg Rev 1 0 4 August 2011 Fig 8 8026 02 D layout TOP Layer NXP Semiconductors 031 9 8026 02 Fig 9 8026 02 D layout GND Layer UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 21 of 27 NXP Semiconductors 031 9 8026 02 Fig 10 8026 02 D layout POWER Layer UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 22 of 27 NXP Semiconductors 031 9 8026 02 Fig 11 8026 02 D layout BOTTOM Layer UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 23 of 27 NXP Semiconductors UM10319 Cake8026 02 D ww C1 B J cec Ar su 5 E P ES I H ding EE TP4
17. in J2 3 or IOUC1 test pin J2 5 or CLKIN1 pin J1 5 or IOUC2 test pin J1 7 or CLKIN2 test pin TDA8026 application example Activate several smart cards and receive all ATR Access different smart cards alternatively See Table 8 in chapter 5 TDA8026 application examples Table 4 Handle the TDA8026 s interrupt Cake8026 pin VDD VDDI SDA SCL IOUC1 CLKIN1 IOUC2 CLKIN2 IRQN Host connection Microcontroller power supply Master SDA pin Master SCL pin Host s ISO 7816 UART line Host s ISO 7816 UART CLK line Host s ISO 7816 UART I O line IOUC1 and IOUC2 can be connected together Host s ISO 7816 UART CLK line CLKIN1 and CLKIN2 can be connected together Microcontroller s external interrupt input Cake 8026 pin position J3 1 and J2 1 or VDD and VDDI test pin J1 1 or SDA test pin J1 3 or SCL test pin J2 3 or IOUC1 test pin J2 5 or CLKIN1 pin J1 5 or IOUC2 test pin J1 7 or CLKIN2 test pin J2 7 or IRQN test pin TDA8026 application example Receive an interrupt after power up or for smart card insertion or extraction See Table 9 in chapter 5 TDA8026 application examples Note The IRQN line must be externally pulled up by a 1k resistor UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 9 of 2
18. ll have no liability for the consequences of use of such information In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage
19. nnected signals 4 1 Connections The following drawing shows the available signals on these 4 connectors o o INTAUXN 28SPRES N C O O A0 GND C SDWNN GND O OsGND SCL OO CLKIN2 GND OO GND vDDIDO N C 0 2 IOUC2 13 TDA8026 ji 14 12 GND O8GND IOUC1i OO IRQN1 GND QO GND ipio O CLKIN1 Fig 5 Cake8026_02_D J1 to pins position The drawing above is represented in top view To design the mother board 4 connectors are needed The reference of the connectors is Bar2x4FD Header Dual Row Straight Female Pitch 2 54 h 8 5 mm The positions of the connectors on the board must respect the following reference UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 11 of 27 NXP Semiconductors UM1 031 9 Cake8026 02 D 25 5 00575 00 J4 5 00 15 00 gt 0 00 0 00 ORIGIN Fig 6 8026 02 D Mother board connectors position 30 10 EI 1 31 85 0057500 e 18 24 21 23 22 LIS 19 EI 1 32 85 00 15 00 18 s e 4 2 4 3 UM10319 Configuration As explained in chapter 2 AO and SPRES can be connected in hardware on the board If this is done the corresponding pins AO J3 7 and SPRES J3 8 must be l
20. r SCL Master 2 SCL pin J1 3 or SCL test pin presence See Table 6 in chapter 5 TDA8026 application examples Table 2 Access slot 1 Cake8026 pin Host connection VDD VDDI Microcontroller power supply SDA Master SDA pin SCL Master 2 SCL pin IOUC1 Host s ISO 7816 UART I O line CLKIN1 Host s ISO 7816 UART CLK line Cake8026 pin position J3 1 and J2 1 or VDD and VDDI test pin J1 1 or SDA test pin J1 3 or SCL test pin J2 3 or IOUC1 test pin J2 5 CLKIN1 pin TDA8026 application example Activate the smart card Receive the ATR Send an APDU and receive the answer See Table 7 in chapter 5 TDA8026 application examples UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 8 of 27 NXP Semiconductors UM10319 Table 3 Access slots 1 to 5 Cake8026 02 D Cake8026 pin VDD VDDI SDA SCL IOUC1 CLKIN1 IOUC2 CLKIN2 Host connection Microcontroller power supply Master SDA pin Master SCL pin Host s ISO 7816 UART I O line Host s ISO 7816 UART CLK line Host s ISO 7816 UART I O line IOUC1 and IOUC2 can be connected together Host s ISO 7816 UART CLK line CLKIN1 and CLKIN2 can be connected together Cake8026 pin position J3 1 and J2 1 or VDD and VDDI test pin J1 1 or SDA test pin J1 3 or SCL test p
21. rom 2 to 5 have SIM sized smart card connectors UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 3 of 27 NXP Semiconductors UM1 031 9 Cake8026 02 D 2 Configuration UM10319 2 1 Power Supply The TDA8026 is supplied through 2 supply pins VDDI for the interface with the host and VDD for the core and the DCDC converter On the board the two pins can be connected together with the same power supply or be supplied separately VDD can be input by the ST13 connector The jumper can be removed and VDD applied on the pin described in Fig 1 VDDI can be applied in the same way on ST12 by removing the jumper See Fig 1 The ground must always be connected It can be easily plugged on a jumper called ST1 or ST2 0 512 GND p ON non e rn n H o000 ue anos SB Pay c Eg TPS a En 724 in pig 8888 pis IODO O gooo Fig 1 8026 02 D connect the power supply All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 4 of 27 NXP Semiconductors UM10319 UM10319 Cake8026 02 D 2 2 A0 0 allows choosing the address It can be fixed by hardware thanks to the soldering points ST
22. s products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from national authorities UM10319 All information provided in this document is subject to legal disclaimers Evaluation products This product is provided on an as is and with all faults basis for evaluation purposes only NXP Semiconductors its affiliates and their suppliers expressly disclaim all warranties whether express implied or statutory including but not limited to the implied warranties of non infringement merchantability and fitness for a particular purpose The entire risk as to the quality or arising out of the use or performance of this product remains with customer In no event shall NXP Semiconductors its affiliates or their suppliers be liable to customer for any special indirect consequential punitive or incidental damages including without limitation damages for loss of business business interruption loss of use loss of data or information and the like arising out the use of or inability to use the product whether or not based on tort including negligence strict liability breach of contract breach of warranty or any other theory even if
23. to the smart card 1 an answer is received on 1 The answer can be read on IOUC1 UM10319 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 0 4 August 2011 14 of 27 NXP Semiconductors UM1 031 9 Cake8026 02 D Table 8 Access to several slots IOUC2 and CLKIN2 must be connected to the host ISO 7816 UART they can be connected to IOUC1 and CLKIN1 Action Command Result Comment Power up and clear the pending interrupts by reading each slot s 40h Insert card in slot 1 and clear the interrupt by reading the slot 1 40h Insert a card in slot 4 12C Write 01h 48h ACK Select slot1 12 Write 45h 40h ACK Enable I O line on 1011 select 5V activation and set START bit The smart card in slot 1 is activated The ATR is received on 101 The ATR is transmitted to the host through IOUC1 12C Write 05h 40h ACK Clear IOEN bit in slot 1 but keep card activated at 5 V 12 Write 04h 48h ACK Select slot 4 12 Write 41h 40h ACK Enable I O line on slot4 select activation and set START bit The smart in slot 4 is activated The ATR is received on 104 The ATR is transmitted to the host through IOUC2 12C Write 05h 40h ACK Disable I O on slot 4 but keep card activated at 3 V 12 Write 01h 48h ACK Select slot 1 12 Write 45h 40h ACK Enable I O line on slot1 keep 5V selection
Download Pdf Manuals
Related Search