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Model VME-64C1 MULTI-FUNCTION CARD

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1. REGISTER 015 0141013 012011010 D9 D8 D7 D6 05 D4 D3 D2 D1 DO FUNCTION MODEL D DATA BIT ASCII 1 ASCII Platform This register holds VME platform code 64 in ASCII Find ASCII 6 is in upper byte and ASCII 4 in lower byte together 3634h REGISTER 15 014 013 012 011 010 D9 08 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION PLATFORM D DATA BIT ASCII 6 ASCII 4 Model The register holds product model in ASCII Find ASCII is in upper byte and ASCII space in lower byte together 4320h REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 05 D4 D3 D2 D1 DO FUNCTION MODEL D DATA ASCII ASCII Generation This register holds product generation code 1 in ASCII Find ASCII 1 is in upper byte and ASCII space in lower byte together 3120h REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION GENERATION D DATA ASCII 1 ASCII
2. REGISTER 015 014 013 0121011 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 328 164 82 40 96 20 48 10 24 5 12 2 56 1 28 0 64 0 32 0 16 0 08 0 04 0 02 value in mSec LSB 20HS DE BOUNCE TIME D DATA BIT 64 C1 001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 49 of 74 Input Output Interface The Input Output I O Interface be configured in a variety of ways pair of drive FETs and current circuits are provided at each pin See interface diagram below Output When configured as an output the interface can act as a High Side Low Side or Push Pull drive providing up to 500ma per channel The total output per module 16 channels cannot exceed 2 amps Input When configured as an input output drivers are disabled I O interface can act as a current source current sink or voltage sensing circuit For contact sensing set each channel for pull up or pull down using the Pull Up Down Current Configuration register and enter the appropriate current level in the Current For Sink Source register Define contact closure and hysteresis using Upper and Lower Threshold See Read O register to read input signal logic state No additional re
3. REGISTER 015 014 013 012 011 D10 09 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULEDESIGNREVISION D D DATA ASCII ASCII DSP Type binary word Range 0 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module DSP revision For example 0x000B is revision 12 REGISTER 015 014 013 0121011 D10 09 D8 D7 D6 05 D4 D3 D2 D1 DO FUNCTION MODULE DSP D D DATA Module FPGA Type binary word Range 0 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module FPGA revision For example 0x000B is revision 12 REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE FPGA 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 44 of 74 0 Read register to determine Module ID in ASCII For example find ASCII i
4. MODULE DSP DID D DATA Module FPGA Type binary word Range 0 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module FPGA revision For example 0x000B is revision 12 REGISTER 015 014 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 DO FUNCTION MODULE FPGA D DATA ID ASCII character in each upper and lower byte Range N A Read Write R Initialized Value 4431h Read register to determine Module ID in ASCII For example find ASCII D in upper byte and ASCII 1 in lower byte for Module D1 together 4431h REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE ID 0 D DATA ASCII D ASCII 1 Automatic background BIT testing BIT is always enabled and continually checks that each channel is functional This capability is accomplished by an additional test comparator that is incorporated into each 16 channel module The test comparator is sequentially connected across each channel and is compared against the operational channel Depending upon
5. 34 MODULE DESIGN REVISION E 34 MODULE Pl ea ese 34 MODULE FPGA 34 NODE 34 STATUS 35 STATUS INTERRUPT ENABLE sssscccesssscecssscececssssecsssessesssseeeesnsssecsensssesssceeceensssecsesesessseecsensssecseceeessusenecssnsnsecseeeessnsnness 35 D A MODULE F OR J i 36 64_C1_A001_Rev_6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 4 of 74 WRITE D A OUTPUT Ne 36 DA QUIPUT POLARITY 36 D A WRAP AROUND Ne 30 NopUEE DESIGN 55 37 MODULE DESIGN 5 de adis 37 ban Ie I 37 mat dtes um 37 MODULE 37 I STATS 38 GVERICURRENTIST T 38 BIT STATUS INTERRUPT ENABEE
6. REGISTER D15 D14 D13 D12 D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION PHASE S D DID DI DI DI D DIDIDID X X S SIGN BIT D DATA BIT Amplitude Type 16 bit unsigned integer Range 0 to 65535 0 to 10 volts peak 0 to 15 volts peak E2 Read Write R W Initialized Value 0 Value determines peak amplitude of selected waveform Amplitude in combination with the programmed DC Offset cannot be greater that the maximum or full scale output of that module For module E1 resolution is 10 65536 or approximately 0 15 millivolts For module E2 resolution is 15 65536 or approximately 0 22 millivolts From 1 to 9 Hz amplitude is not accurate Enter as per formula Peak to Peak Voltage 10 Value 65535 Volts Peak for module s 10 magnitude of DC Offet Peak to Peak Voltage 15 Value 65535 Volts Peak for module E2 s 15 magnitude of DC Offet Where Volts Peak is half Peak to Peak Voltage Out of range data will be changed to the maximum allowable value From 1 to 9 Hz amplitude is functional but not to accuracy specification REGISTER 015 014 013 012 11 D10 09 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION AMPLITUDE D DATA DC Offset Type 16 bit signed integer Range 32767 to 32767 10 volts E1 15 volts
7. EE HEU CE ECHTE EHE ERE Ee 64 OVERLOAD MEME 64 DA OVERRIDE ne 65 REFERENCE DESIGN VERSION 65 64 1 001 6 3 North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 6 of 74 REFERENCE DESIGN REVISION 4 65 DESIGN VERSION ss CEDERE ELTE e NN ERROR Fe etae ee zv pas eU dE ge 65 PLATFORM 65 65 GUI Wap 65 DS PEC TA Te BEG os oie bL Eb ER Mee 65 NTERRUPT IJEVBES 66 INTERRUPTS VECTOR DR AVE DER CREE EE das EN Va dg 66 FRONT AND REAR PANEL CONNECTORS 1 tasa ses s asses sete ease sese s e sesso sas e e eese sese s e 67 REFERENCE OUTPUT m 67 SO 68 SOT
8. REGISTER 015 014 013 012 011 D10 09 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE DSP D DATA BIT Module FPGA binary word Range 0 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module FPGA revision For example 0x000B is revision 12 REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 DO FUNCTION MODULE FPGA D DATA 10 ASCII character in each upper and lower byte Range N A Read Write R Initialized Value 4531h Read register to determine Module ID in ASCII For example find ASCII E in upper byte and ASCII 1 in lower byte for Module E1 together 4531h REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE ID D D I DIDID D D I ID D D D ASCII ASCII 1 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 35 of 74 Status binary Range 0 to 15 Read Write R Initialized Valu
9. 68 po 6 10 gs Hp a I 69 SO 69 OO 70 SEO 70 ENCODER COMMUTATION OUTPUT CONNECTION e etse te eese e e eite eset 71 PART NUMBER DESIGNAT ION een i osos re nae eo To co E rao aono ne eo Fea o Ue arn aeuo Poss so ra ere Ue Fog sa esae No erede n re SE eK Ro 72 REVISION AGE 73 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7114 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 7 of 74 SPECIFICATIONS General VME Data transfer Interrupts ESD protection Power Mother board Temperature operating Storage temperature Temperature cycling Size Weight A D Module C1 Resolution Input format Input scaling Over voltage Open Input sense Input Impedance Accuracy Linearity error Sampling rate Band Width Group delay Programmable filter Common mode rejection Common mode voltage Output Logic ESD protection Power Weight North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 For the Carrier Card Mother Board Data transfers within 200 ns One Interrupt capability is implemented One of seven priority lines can be specified Designed to meet the testing requirements of IEC 8
10. MODULE DSP D DATA Type binary word Range 0 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module FPGA revision For example 0x000B is revision 12 REGISTER 15 014 013 012 11 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE FPGA D DATA 10 ASCII character in each upper and lower byte Range N A Read Write R Initialized Value 4332h Read register to determine Module ID in ASCII For example find ASCII D in upper byte and ASCII 2 in lower byte for Module D2 together 4432h REGISTER 015 014 013 012 011 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE ID D DI DIDID D D JD D D D D DATA ASCII D ASCII 2 Automatic background BIT testing BIT is always enabled and continually checks that each channel is functional This capability is accomplished by an additional test comparator that is incorporated into each 11 channel module The test comparator is sequentially connected across each channel and is compared against the operational channel Depending upon configuration the Input data read o
11. 64 C1 A001 Rev 6 3 do 7 14 5 Cage Code OVGU1 Page 66 of 74 North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 631 567 1100 631 567 1823 fax www naii com e mail sales naii com Special Spec This register holds product special specification code in ASCII Find ASCII space used for none where ASCII space is in upper and lower bytes together 2020h REGISTER 015 014 013 012011 010 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION SPECIAL SPEC D DI DIDID D D ID D D D ASCII ASCII Interrupt Levels Write a 16 bit binary number to the nterrupt Level Register 0 lt no interrupt 1 7 indicates priority levels Any fault will latch the Status Registers and trigger an Interrupt if enabled Reading will unlatch registers When a status bit changes before registers are read the status change will be held in background an interrupt is not generated until the registers are read After reading registers will be updated with the background data within 250ms The Interrupt service routine should read the associated status register to unlatch data so additional faults will trigger another Interrupt Interrupts Vector Enter vector address to interrupt service routine Write 8 bit word 0 255 64 C1 001 6 3 0 North Atlantic Industries Inc 631 567 1100 631 567 1823
12. MEME EE MEE MEME II 61 ALERT sei M EaS 61 BIT STATUS INTERRUPT ENABLE eese sensit gases sense tete e 62 SIGNAL STATUS INTERRUPT ENABLE ee 62 REFERENCE STATUS INTERRUPT ENABLE et 62 ANGLE A ALERT INTERRUPT ENABLE ee 62 GENERAL USE REGISTER MEMORY 4 0 0202 2 23 4 4 41 41 0 0 4 418010 240 044 40 20 00 000 04 0001000 4 0 4110 0100 63 EE IEEE MEME MM 63 SERIAL NUMBER DELA OEEO AA IDA IU E IEEE 63 DATE GD 03 REVISIONS veu PE MED PRIMI MARI i 63 BOARD READY T 63 WATeHDDGTINER C 63 SOFT RESE Me E EL MEE 63 H 64 TEST D2 Ic NIMIUM I 64 TAT CH MERI LU A SU ES 64 DO TEST RANGE 04 TESTE VOETAGE C ELE 64 ID A RESET TO ZERO 64 D A RETRY OVERLOAD 5
13. High Threshold 10 R W Current For Sink Source Bank 2 05 08 R W 014 Min Low Threshold 02 R W 060 Upper Threshold 10 R W 0AC Current For Sink Source Bank 3 09 12 R W 016 De bounce time Ch 02 R W 062 Lower Threshold Ch 10 R W JOAE Current For Sink Source Bank 4 13 16 R W 018 Max High Threshold Ch 03 R W 1064 Min Low Threshold 10 R W 10 0 Up Down Current Config Ch 01 16 R W 01A Upper Threshold Ch 03 R W 1066 De bounce time 10 R W 1084 Value Bank 1 Ch 01 04 R 01C Lower Threshold Ch 03 R W 1068 High Threshold Ch 11 R W 086 Value Bank 2 Ch 05 08 R 01E Min Low Threshold Ch 03 R W 06 Upper Threshold Ch 11 R W 10 8 Value Bank Ch 09 12 R 020 De bounce time Ch 03 R W 06C Lower Threshold Ch 11 R W OBA Vcc Value Bank 4 Ch 13 16 R 022 Max High Threshold 04 R W 06E Min Low Threshold 11 R W JOBC Reset Over Current Ch 01 16 R W 024 Upper Threshold 04 R W 1070 De bounce time Ch 11 R W 0 0 Module Design Version R 026 Lower Threshold Ch 04 R W 072 High Threshold Ch 12 R W 0 2 Design Revision R 028 Min Low Threshold 04 R W 074 Upper Threshold Ch 12 R W 10 4 DSP1 R 02A De bounce time 04 R W 076 Lower Threshold 12 R W 10 6 FPGA 11 R 02 High Threshold Ch 05 R W 078 Min Low Threshold Ch 12 R W 10 8 Module FPGA 21 02 Upper Threshold Ch 05 R W 07A De bounce tim
14. a p 16 R D MODULE R2 FOUR 4 400Hz RESOLVER MEASUREMENT Ne 17 R D MODULE R3 FOUR 4 400Hz RESOLVER MEASUREMENT Ne 17 R D MODULE R4 FOUR 4 1200Hz RESOLVER MEASUREMENT Ne 17 S D MODULE S1 FOUR 4 400Hz SYNCHRO MEASUREMENT Ne 17 Reference Supply Include as Required 17 S D MODULE 52 FOUR 4 60 400HZ SYNCHRO MEASUREMENT Ne 18 SUPPOR 19 ADDRESSCONMIGURATIOIN 20 2 20 PRODUCT CONFIGURATION AND MEMORY 21 MODULE T E 22 TAR 22 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 3 of 74 A D RANGE amp POLARITY Ne 23 A D FILTER BREAK 4 23 MODULE DESIGN VERSION RR 23 MODULE DESIGN REVISION MEME M 23 hue mpl NC 23 MO
15. 5 oer eere eret C etr t ER Hehe eei eire Ee cese eec eae Yee se Eve De edv Prod Eo EE En leads 38 OVER CURRENT STATUS INTERRUPT ENABLE ee 38 HIGH VOLTAGE D A MODULE J7 vwisscsscccsssssssssosossccsesscsccssssevesesscsseusccsessnscscssesecdececdsesessdssscnascssessosoesseuccvsscsescescesesseses 39 M WRISEDAAOUEBUT S 5h etcetera tei EE ET 39 DA OUTPUT RANGE suier 40 OUTPUT 40 D A WRAP A ROUND sacs 40 MODULE DESIGN VERSION m 40 MODULE DESIGN REVISION ee 40 MODULE 40 MODULE ducc 41 41 BIT STATUS PETP 41 Gueck geleegssehccdualsanaes EEEE AEO EERE PE EEES 41 BIT STATUS INTERRUPT ENABLE ee 41 OVER CURRENT STATUS INTERRUPT ENABLE Ne 41 MODULE G 42 RESISTANCE 42 RANGE 43 W TRE IVI OD Bias EN NUI UN TE 43 MODULE DESIGN VERSION pH e Pe oe Eo RE Pe HR
16. X X Ch8 Ch7 Ch6 Ch5 Ch4 Ch3Ch2 Ch1 INTERRUPT Reference Status Interrupt Enable Type binary word Range N A Read Write RAW Initialized Value 0 Set the bit to enable interrupts for the corresponding channel When enabled a signal open status signal or reference input loss will trigger an interrupt Default is 0 to disable all channels When Status Interrupt is enabled Status Interrupt is reported through the Over Current Status Interrupt Vector in the General Use Memory Map REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION REFERENCE STATUS INTERRUPT ENABLE X Ch8 Ch7 Ch6 5 4 2 1 INTERRUPT Angle A Alert Interrupt Enable Type binary word Range 0 to 15 Read Write R W Initialized Value 0 Set the bit to enable interrupts for the corresponding channel When enabled an angle A alert will trigger an interrupt Default is O to disable all channels When Status Interrupt is enabled Status Interrupt is reported through the Max Hi Threshold Status Interrupt Vector in the General Use Memory Map REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION ANGLE A INTR ENA Xi XxX X X ICh8 Ch7 Ch6 Ch5 Ch4
17. Model VME 64C1 aE Apex Signal Division AID D A Discrete I O TTL I O RTD Synchro Resolver and LVDT RVDT Channels VME bus MULTI FUNCTION CARD AID D A Discrete TTL I O Differential I O RTD Synchro Resolver and LVDT RVDT Channels EXTENSIVE DIAGNOSTICS FOR COMMERCIAL AND MILITARY APPLICATIONS Photo Sample Configuration Heatsink removed for clarity FEATURES e Multiple functions available A D D A Digital I O Discrete I O Synchro Resolver Measurement Signal Generator on a single slot VME card Background Self Test No damage if Signals are applied when card is not powered Geographical addressing Field selectable Connections via Front panel P2 PO or both Conducted cooled versions available North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 141 64 1 001 6 3 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 1 of 74 DESCRIPTION This universal card eliminates the need for specialized single function cards by providing an assortment of functions on one single card The mother board contains 6 independent module slots each of which can be populated with a function specific module The available functions are as follows 1 25 to 10 40 50 VDC and 4 20ma versions 1 25 22 5 5V 10 VDC Isolated or Non Isolated versions High Voltage 20 to 80 VDC Isolated Funct
18. DIGITAL DIFFERENTIAL MULTI MODE TRANSCEIVERS MODULE DJ eese eee eere esee 28 WRITE 28 READIO c ccc Iu RR E 28 DE BOUNCE TIME ss 29 INPUT TERMINATION CONTR L EEA SREE ONS ENa ia ERENER E N ENE NAER s Saas 29 TINPUT OUTPUT F ORMA Sv MON uM HS 29 MODULE DESIGN V ERSION rper eder Pe oie Fo ERR Pe ER EE Te ER e RE E E REEE E PER SR EE OE SPESSE NEON Pe 29 MODULE DESIGN REVISION ee 29 MODUEE DS Biss HP 29 MODULE FRGIA E M 30 NI 30 AUTOMATIC BACKGROUND BIT TESTING 30 STATUS INDICATIONS 3 o Ir oin o Ir De eec RT Ce E RYE ee E HEURE d EE C EE e dos eie oerte PE 30 SIGNAL GENERATOR MODULE 31 FREQUENCY X 31 AS 32 NE 32 32 NI 33 WRAP AROUND FREQUENCY E n 33 WRAP AROUND AMPLITUDE etn c oi eec ER a ehe c eee eee eh ee Eee dv dede Ce EET Mie ades 33 WRAP AROUND DC OFFSET et 33 MODULE DESIGN
19. of this card MODULE MEMORY MAP 000 Ch 1 Frequency High R W 020 Ch 3 DC Offset R W 050 Ch 3 Wrap around Frequency High R 002 Ch 1 Frequency Low R W 022 Ch 3 Mode R W 052 Ch 3 Wrap around Frequency Low R 004 Not used 024 Ch 4 Freq Hi R W 054 Ch 3 Wrap around Amplitude R 006 Ch 1 Amplitude R W 026 Ch 4 Freq Lo R W 056 Ch 3 Wrap around DC Offset R 008 Ch 1 DC Offset R W 028 Ch 4 Phase R W 058 Ch 4 Wrap around Frequency High R 00A Ch 1 Mode R W 02A Ch 4 Amplitude R W 05A Ch 4 Wrap around Frequency Low R 00 Ch 2 Freq Hi R W 02C Ch 4 DC Offset R W 05C Ch 4 Wrap around Amplitude R 00 Ch 2 Freq Lo R W 02 Ch 4 Mode R W 05 Ch 4 Wrap around DC Offset R 010 Ch 2 Phase R W 040 Ch 1 Wrap around Frequency High R 0 0 Module Design Version 012 Ch 2 Amplitude R W 042 Ch 1 Wrap around Frequency Low 0C2 Module Design Revision R 014 Ch 2 DC Offset R W 044 Ch 1 Wrap around Amplitude R 0 4 Module DSP R 016 Ch 2 Mode R W 046 Ch 1 Wrap around DC Offset 0 6 Module FPGA 11 R 018 Ch 3 Freq Hi R W 048 Ch 2 Wrap around Frequency High R 0 8 Module FPGA 21 R Ch 3 Freq Lo R W 04A Ch 2 Wrap around Frequency Low R Module ID R 01C Ch 3 Phase R W 04C Ch 2 Wrap around Amplitude 0D0 Status Ch 1 4 R 01E Ch 3 Amplitude R W 04E Ch 2 Wrap around DC Offset R 0 8 Stat Interrupt Enable Ch 1 4 R W Note 1 As o
20. 11 70 volts 1 0 110101010 80 volts D A Output Polarity Write integer 4 to the channel s D A range register for unipolar mode Write integer 0 to the channel s D A range register for bi polar mode D A Wrap Around Read D A wrap around data register 16 bit 25 complement word 7FFFh FS 8000h FS bipolar mode or 16 bit binary word range 0 to FFFFh FS Module Design Version Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design version in ASCII For example ASCII 17 in upper byte and ASCII space in lower byte for Module Design Version 1 is together 3120h REGISTER 015 014 013 012011 010 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE SPECIAL SPEC D ID ID 00 0 0 0 D DATA ASCII 1 ASCII Module Design Revision Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design revision code in ASCII For example ASCII B in upper byte and ASCII space in lower byte for Module Design Revision B is together 4220h REGISTER D15 D14 D13 D12 D11 D10 09 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULEDESIGN
21. 16 15 14 Ch 13 12 Ch 11 Ch 10 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Lo Hi Transition 16 15 14 Ch 13 Ch 12 Ch 11 Ch 10 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Hi Lo Transition 16 15 14 Ch 13 Ch 12 Ch 11 Ch 10 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Fault Enable 16 15 14 Ch 13 Ch 12 Ch 11 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Over Current Enable 16 15 14 Ch 13 Ch 12 Ch 11 10 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Lo Hi Enable 16 15 14 Ch 13 Ch 12 11 10 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Hi Lo Enable 16 Ch 15 14 Ch 13 12 Ch 11 Ch 10 9 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 27 of 74 I O DIGITAL DIFFERENTIAL MULTI MODE TRANSCEIVERS MODULE D2 Differential RS422 RS485 I O channels in banks of 11 are programmable for either Input or Output and include extensive diagnostics Each Differential input channel has a selectable internal resistor 1200 or gt 1
22. X X ICh8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 CHANNEL STATUS 64 C1 001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 62 of 74 Status Interrupt Enable Type binary word Range 0 to 15 Read Write R W Initialized Value 0 Set the bit to enable interrupts for the corresponding channel When enabled a non compliant channel will trigger an interrupt Default is 0 to disable all channels REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION STATUS INTRENA X X EX X X X X X Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 INTERRUPT ENABLE Signal Status Interrupt Enable Type binary word Range N A Read Write R W Initialized Value 0 Set the bit to enable interrupts for the corresponding channel When enabled a signal open status signal or reference input loss will trigger an interrupt Default is 0 to disable all channels When Status Interrupt is enabled Status Interrupt is reported through the Open Status Interrupt Vector in the General Use Memory Map REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION SIGNAL STATUS INTERRUPT ENABLE
23. ede tea dece e 54 MODULE SR 55 TEA 56 hasse M n 56 RATIO 57 ANGLE 57 ANGEE A INITIATE urei 57 PAC TIVE CA II D 57 IE wio 58 SES DA NGUGE eo 58 TWO SPEED LOCK LOSS ee 58 VELOCIMY SCALE 58 AK 55 IMEEM 59 SYNCHRO 5 59 REFERENCE FREQUENCY d P riS 59 REFERENCE VOLTAGE odriin o cC FR REIP ael Ip dE RERO 59 MODULE DESIGN 2 4 4 2 44400 000000000000000000000000000000000000000 0 60 MODULE IDESIGN REVISION 60 MODULE DSP entendu dio eret 60 MODULE FPGA m 60 eMe 60 STADUS 61 SIGNAL STATUS E 61 REBERENCE STATUS
24. gt o Module o 4 6 FPGA N 3 gt DSP 64 C1 A001 Rev 6 3 do 21 of 74 A D MODULE C AD Module Block Diagram A D channels use individual A D converters with a high 50 kHz sampling rate per channel The 22421 AD 1 input range and gain is field programmable for PSA each channel Each of these differential channels includes a second order anti aliasing filter and a post filter that has a digitally programmable break point that enables user to field adjust the filtering for each channel All A D channels are self calibrating because each channel on a rotating 10 P AD 10 basis is automatically calibrated to eliminate offset and gain errors The ability to set lower 10 for Full Scale Input assures DA utilization of the full resolution does not apply to Current Measurement Module C3 which is fixed unipolar 0 25mA FS Open inputs cannot be sensed because scaling input resistor networks are used inputs are double buffered for immediate availability The Latch feature permits the user to read all A D channels at the same time The D2 test initiates automatic background BIT testing where each channel is checked to a test accuracy of 0 296 FS Any failure triggers an Interrupt if enabled with the results available in BIT status register The testing is totally transparent to the user requires no external programming has no effect
25. 0 0 Module Design Version R 002 2 R 016 Range amp Polarity 2 R W 02 Filter Break Freq 2 R W 0C2 Module Design Revision R 004 IData 3 R 018 Range amp Polarity 3 R W 02C Filter Break Freq 3 0C4 Module DSP2 R 006 Data 4 R 01A Range amp Polarity 4 R W 02 Filter Break Freq 4 R W 0C6 Module FPGA 12 R 008 5 R 01C Range amp Polarity 5 R W 030 Filter Break Freq 5 R W 0C8 Module FPGA 22 R 00A Data 6 R 01E Range amp Polarity 6 R W 032 Filter Break Freq 6 R W OCE ID R 00C Data 7 R 020 Range amp Polarity 7 R W 034 Filter Break Freq 7 R W 1000 Status Ch 1 10 R OOE Data 8 R 022 Range amp Polarity 8 R W 036 Filter Break Freq 8 R W 1002 Open Status Ch 1 10 R 010 Data 9 R 024 Range amp Polarity 9 R W 038 Filter Break Freq 9 R W 0 8 Stat Interrupt Enable Ch 1 10 R W 012 Data 10 R 026 Range amp Polarity 10 R W Filter Break Freq 10 R W OEA Stat INTR Enable Ch 1 10 R W Note 1 Range amp Polarity Register is simply called Range Register in software driver library Range amp Polarity does not apply to Current Measurement Module C3 2 As of July 2005 3 Open Status does NOT apply to High Voltage 20V to 80V or Current Measurement modules Data Read Two s complement format for bipolar mode 7FFFh FS 8 000h FS For unipolar mode range is from Oh to FFFFh FS 64 C1 A001 Rev 6 3 do North Atlantic
26. 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Over Current Enable 16 15 14 Ch 13 Ch 12 Ch 11 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Max Hi Threshold Enable Ch 16 15 Ch 14 Ch 13 12 11 Ch 10 Ch 9 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Min Lo Threshold Enable Ch 16 15 Ch 14 Ch 13 Ch 12 11 Ch 10 Ch 9 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Mid Range Enable 16 Ch 15 14 Ch 13 Ch 12 11 Ch 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Lo Hi Enable 16 15 14 Ch 13 Ch 12 Ch 11 Ch 10 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Hi Lo Enable 16 15 14 Ch 13 Ch 12 Ch 11 Ch 10 9 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Interrupt Enable Set the bit to enable interrupts for the corresponding channel monitored When status is indicated or bit is set bit value is logic 1 Reading will reset or unlatch Status Register 015 D14 D13 D12 D11 D9 Ds D7 De D5 D3 D2 D1 po Status Fault Ch 16 Ch 15 Ch 14 Ch 13 Ch
27. Ch 2 Ch 1 Status Interrupt Enable Set the bit to enable interrupts for the corresponding channel When enabled non compliant channel will trigger an interrupt Default is 001 to disable all channels 015 D14 D13 D12 D11 D10 D9 08 D7 06 D5 D4 D3 D2 D1 DO BIT Status Interrupt Enable X X X X X X X X X X x X Ch 4 Ch 3 Ch 2 Ch 1 Over Current Status Interrupt Enable Set the bit to enable interrupts for the corresponding channel monitored for Over Current Status D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Over Current Status Intr Enable X X X X X X X X X X Ch 4 Ch 3 Ch 2 Ch 1 64_C1_A001_Rev_6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 15 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 42 of 74 RTD MODULE The RTD channels use individual A D converters All RTD channels are self calibrating because each channel on a rotating basis is automatically calibrated to eliminate offset and gain errors The ability to set lower voltages for Full Scale Input assures the utilization of the full resolution Open inputs will be detected with the results dis
28. D DATA Threshold Programming All four threshold levels must be programmed For Input threshold levels define logic For output threshold levels are used in BIT wrap around test signal monitoring For proper operation the threshold values should be programmed such that Max High Upper Lower Min Low Threshold For proper operation all four voltage thresholds Max High Threshold must be set in this order a 0 25 volt minimum For hysteresis configuration differential between Upper Upper Threshold Lower Threshold Max High Threshold gt Upper Threshold gt Lower Threshold gt Min Low Threshold EM Threshold and Lower 4 Threshold is recommended Min Low Threshold Hysteresis Program Upper and Lower Thresholds to implement the required hysteresis and then add de bounce time as required When the input signal exceeds the Upper Threshold a logic high 1 is maintained until the input signal falls below the Lower Threshold Conversely when the input signal falls below the Lower Threshold a logic low 0 is maintained until the input signal rises above the Upper Threshold A 0 25 volt minimum differential is recommended between the Upper and Lower Threshold values Program Upper and 1 Lower Thresholds to implement hysteresis When the input signal exceeds the Upper Threshold a logic high 1
29. D3 D2 D1 DO Over Current Status Intr Enable x X X X X X Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 39 of 74 HIGH VOLTAGE D A MODULE J7 Four 4 D A channels are provided per module and includes extensive diagnostics To save power DC to DC output drive is internally scaled according to programmed output range Overloaded outputs will be detected with the results displayed in a status word This module incorporates major diagnostic capabilities that offer substantial improvements to system reliability because user is alerted to malfunctions within 5 seconds Two different tests one off line D2 and one on line D3 can be selected The D2 test initiates automatic background BIT testing where each channel is checked to a test accuracy of 2 FS and monitored for shorted output Any failure triggers an Interrupt if enabled with the results available in status registers The testing is totally transparent to the user requires no external programming has no effect on the operation of this card and can be enabled or disabled via the bus The D3 test uses an internal A D that measures all D A channels while they remain connected to the I O Each channel will be checked to a test ac
30. D3 D2 D1 DO FUNCTION MODE and LOCK SINE WAVE 1 TRIANGULAR WAVE SQUARE WAVE 1 SINE WAVE 00 Wrap around Frequency Type 32 bit unsigned integer Range 0 130 000 from 1 to 9 Hz amplitude is functional but not to accuracy specification Read Write R Initialized Value N A Read Wrap around Frequency High and Frequency Low registers combined to determine desired frequency in 1 Hz resolution LSB is 1 Hz FREQUENCY HIGH REGISTER FREQUENCY LOW REGISTER 015014013012 011 010090807 06 05 0403102 D1 DO 1015 014 013 0121011 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO XXXIX LX XIXIXIXIXIXIXIX X X D Dj D D D Wrap around Amplitude Type 16 bit unsigned integer Range 0 to 65535 0 to 10 volts peak 1 0 to 15 volts peak E2 Read Write R Initialized Value N A Read Wrap around Amplitude for D2 BIT test value to verify peak amplitude of selected waveform For module E1 resolution is 10 65536 or approximately 0 15 millivolts For module E2 resolution is 15 65536 or approximately 0 22 millivolts From 1 to 9 Hz amplitude is not accurate Decode v
31. Interrupt Vector Lo gt Hi Transition R W 614 Watchdog Timer R W 630 Design Version R 64A Interrupt Vector Hi gt Lo Transition RAW 616 Soft reset W 632 Platform 618 Enable RAW 634 Model R Address to General Use Registers has NO MODULE OFFSET ALL ADDRESS NOT SPECIFIED THROUGH 7FF HEX IS RESERVED Note 1 Only affects A D Modules 2 Only affects D A Modules 3 Open is Signal Status for SD modules 4 Over Current is Reference Status for SD modules 5 Max High Threshold id Angle A Alert for SD modules 6 As of July 2005 Part Number is read as a 16 bit binary word A unique 16 bit code is assigned to each model number Serial Number is read as a 16 bit binary word Date Code Read as a decimal number The four digits represent YYWW Year Year Week Week Revisions Read as a 16 bit binary word Board Ready Poll register Board is ready to be accessed only after you read 55 usually within 1 second after board power on but could be longer Following a soft reset board ready continues to indicate OxAA55 until approx 150ms have elapsed After that time the card is undergoing reset and the register indicates 0x0000 Following a soft reset wait 200ms before polling Board Ready About 1s later the register indicates OxAA55 which is board ready You may proceed with read write coding activity after that change Watchdog timer This feature monitors the watchdog timer reg
32. Module Design Revision R 30C Ch 7 Data Hi R 34C Ch 3 Velocity Scale R W 3C4 Module DSP R 30E Ch 8 Data Hi R 34E Ch 4 Velocity Scale R W 3C6 Module FPGA 11 R 310 Ch 1 Velocity R 350 Ch 5 Velocity Scale R W 3C8 Module FPGA 21 R 312 Ch 2 Velocity R 352 Ch 6 Velocity Scale R W Module ID Slot 4 R 314 Ch 3 Velocity R 354 Ch 7 Velocity Scale R W 300 Status Ch 1 8 R 316 Ch 4 Velocity R 356 Ch 8 Velocity Scale R W 302 Signal Status Ch 1 8 R 318 Ch 5 Velocity 358 A amp res Ch 1 R W 1304 Reference Status Ch 1 8 R 31A Ch 6 Velocity R 35A A amp B res Ch 2 R W 3D6 Angle A Alert Ch 1 8 R 31C Ch 7 Velocity R 35 A amp B res Ch 3 R W Status Interrupt Enable Ch 1 8 R W 31E Ch 8 Velocity 35E res Ch 4 R W Signal Status Interrupt Enable Ch 1 8 R W 320 Ratio Ch 2 Ch 1 R W 360 A res Ch 5 R W Reference Status Intr Enable Ch 1 8 R W 322 Ratio Ch 3 Ch 4 R W 362 A res Ch 6 R W Angle A Alert Interrupt Enable Ch 1 8 R W 324 Ratio Ch 5 Ch 6 R W 364 A res Ch 7 R W 4C0 Module Design Version1 R 326 Ratio Ch 7 Ch 8 R W 366 amp res Ch 8 R W 4 2 Design Revision R 328 Ch 1 Angle A R W 368 Reserved 4C4 Module DSP R 32A Ch 2 Angle A R W 36A Reserved 4C6 Module FPGA 11 R 32C Ch 3 Angle A R W 36 Reserved 4C8 Module FPG
33. Read Write R Initialized Value N A When two Synchros are geared to each other either electrically or mechanically in order to achieve higher accuracy the misalignment of the Coarse and Fine Synchros must not exceed 90 gear ratio or the digital angle output may not be valid Should this problem occur within a given channel pair the corresponding bit in the Two Speed Lock Loss register will be set to 0 REGISTER 015 014 013 012011 010 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION LATCH xix 78 X 56 X xX CHANNEL Velocity Scale Type 16 bit unsigned integer Range 9 5367 RPS to 152 5878 RPS Read Write R W Initialized Value N A The velocity scale factor is used to achieve a greater resolution at lower rotational speeds RPS The scale factor is 4095 152 5878RPS max RPS where the max RPS is selected by the user to achieve the maximum resolution for a desired RPS Enter the scale factor as an integer to the corresponding Velocity Scale register for that particular channel To scale the Max Velocity word for 152 5878 RPS set Velocity Scale Factor 4095 max velocity word of 32 767 7FFFh being 152 5878 RPS for CW rotation and 32 768 8000h being 152 5878 RPS for CCW rotation Scaling effects only the Velocity output word and not the dynamic performance To get a maximum velocity word
34. read logic state High 1 or Low 0 Each bit of 16 bit binary word corresponds to one of 11 channels REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D D5 D4 D3 D2 D1 DO FUNCTION 1111019 716 5 4131211 Channel READ I O D DATA BIT 64 C1 001 6 3 0 North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 711415 c 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 28 of 74 De bounce time Enter required de bounce time into appropriate channel registers Enter time in 1 28 5 increments up to 326 40 LSB 1 28 Value is 8 bits MSBs don t care Once a signal level is a logic voltage level period longer than the De bounce time Logic High gt 2 0 v and Logic Low 0 6 v a logic transition is validated Signal pulse widths less than De bounce time are filtered or ignored Once valid the interrupt transition register channel flag is set and the output logic changes state Enter a value of 0 to disable De bounce filtering De bounce defaults to 00 upon reset REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D3 D2 D1 DO FUNCTION 163 84 81 92 40 96 20 4840 24 5 12 2 56 1 28 value in mSec LSB 1 28HS DE BOUNCE TIME X X
35. 32 767 152 5878 RPS Scale Factor 4095 152 5878 152 5878 4095 OFFFh This results in a velocity resolution of 152 5878 RPS 32 767 x 360 RPS 1 676 sec factory default To get a maximum velocity word 32 767 50 8626 RPS Scale Factor 4095 152 5878 50 8626 12 285 2FFDh This is a velocity resolution of 50 8626 RPS 32 767 x 360 RPS 0 5588 sec For 9 5367 RPS max Scale Factor 4095 152 5878 9 5367 65 520 FFFOh 0 10477 sec res lowest setting REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION VELOCITY SCALE D DATA 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 59 of 74 A 8 B Resolution Type binary word Range N A Read Write RAW Initialized Value N A Individually configure encoder output resolution or commutation for each channel REGISTER 015 014 01301210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION A amp B RESOLUTION lt Integer 0 0 0 0 0 16 bit Encoder Resolution Integer 1 0 0 0 1 15 bit Encoder Resolution Integer 2 0 0 1
36. Ch 11 Ch 10 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Lo Hi Enable Ch 16 Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Hi Lo Enable Ch 16 Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 64 C1 A001 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 711415 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 55 of 74 S D MODULE 5 50 Block Di This S D measurement design has the capability ddp nan to automatically shift to higher bandwidths when q pss SD1 high acceleration events are encountered There is not data latency The shifting is smooth and g continuous with no glitches Tracking rates are Signal and State p only limited to bandwidth restrictions up to 150 Machine 2 E RPS at 16 bit resolution Both a software and 9 hardware LATCH feature is provided to permit the user to read all channels at the same time 4 T SD4 Reading will unlatch that channel The angle alert monitors each channel for the programmed angle 4 difference and sets an interrupt as soon as D S threshold is reached Thus no polling of the angle registers is required until an angle
37. D2 Register by writing OOh waiting 30 seconds then reading the register again to verify that background BIT testing is functioning Testing is totally transparent to the user requires no external programming has no effect on the standard operation of this card and associated status register s can be checked or polled at any given time Enable Interrupts within any interrupt enable register by setting the appropriate channel bits to 1 Status indications Fault Channel processing data read or write logic is inconsistent with redundant test circuit Status bit is set is indicated within 15 seconds A fault is latched until read Testing takes approx 1 second per channel Over current If over current or overload condition is sensed status is indicated bit is set within 80ps Max High Threshold If the signal exceeds this threshold status is indicated bit is set within 405 Min Low Threshold If the signal falls below this threshold status is indicated bit is set within 40us Lo Hi Transition If a Lo to High transition is sensed status is indicated bit is set within 40us Hi Low Transition If a High to Low transition is sensed status is indicated bit is set within 405 Mid Range When the signal is in between the Upper and Lower thresholds status is indicated bit set within 40 When status is indicated or bit is set bit value is logic 1 Reading will reset or unlatch Status Reg
38. Phase Power Weight North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 Eleven 11 Differential Multi Mode Transceivers 422 Differential 485 Differential 10V to 10V 7V to 12V 1200 gt 12kQ 200mV 200mV Each channel incorporates a 120 termination resistor that can be programmed on a channel by channel basis 1 02 seconds 1 128 useconds programmable 0 25V to 6V max 0 25 to 6V 12V 1 5V 6V 6V 1000 540 100 100hA 100hA 1 02 hseconds Short circuit protected Thermal shutdown Built in current limiting 31 ns into a 50pf load 5VDC at 1Watt quiescent 1 8Watts fully loaded 540 load 1 oz 28 Four 4 Programmable Frequency Generators Sine or Square Wave one per channel 10 130kHz with 1Hz resolution 0 10Volts peak 7 07Vrms Programmable per channel 696 FS volts for frequencies 100Hz t 196 FS volts 100Hz 20kHz t 696 FS volts for frequencies gt 20kHz 600 ohms min 7 max No load to full load 0 359 912 1 with 0 088 resolution relative to channel 1 Default is 0 5 VDC at 0 6A per module 1 oz 28g 64 C1 A001 Rev 6 3 do 7 14 5 Cage Code OVGU1 Page 11 of 74 631 567 1100 631 567 1823 fax www naii com e mail sales naii com D A Module F1 Output range Resolution Accuracy Offset Non linearity Gain error Output format Settling time Load Output
39. Reading any status bit will unlatch the entire register Reference Status is part of background testing and the status register may be checked or polled at any given time When Status Interrupt is enabled Status Interrupt is reported through the Over Current Status Interrupt Vector in the General Use Memory Map REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION REFERENCE STATUS x x x x x x x X Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Cht CHANNEL STATUS BIT Angle A Alert Type binary word Range 0 to 15 Read Write R Initialized Value 0 Check the corresponding bit for a channel s Angle A Alert Status Angle A Alert Status Data bit Chn where n is 1 to 8 is fail high true and indicates that the angle position of that channel has exceeded the minimum differential angle specified in the Angle A register Status is latched Reading any status bit will unlatch the entire register Angle Change Alert part of background testing and the status register may be checked or polled at any given time When Status Interrupt is enabled Status Interrupt is reported through the Max Hi Threshold Status Interrupt Vector in the General Use Memory Map REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION ANGLE A ALERT
40. affects slots 4 5 6 only PO is NOT required for slots 3 and 6 module if using J1 and J2 Front Panel I O J7 Module is 4 channels 2 channel Module J6 removed 2 9 Appends C3 Module Description GS 5 8 3 3 0 Edits Block Diagrams Lines up PN Adds J7 Pin out Appends J7 programming details GS 8 4 3 range and data output registers Updated E1 2 Adds separate High Voltage D A Description Added RTD application details E1 from 1 to 9 Hz amplitude is not accurate J7 current limit is 20ma Adds E1 BIT test Wrap around Freq Amp and DC Offset registers Clarified STATUS INDICATORS Adds D2 pinout Zin is 40K i o drawing K2 specification Input impedance is 40k ohms Corrects E1 Accuracy Specs Module E is NOT preliminary anymore High Voltage D A will be available in September 2003 Differential Multi Mode Transceiver is available Adds Module D2 section 3 1 TTL and Tranceiver Over current Status ands output is disabled D2 LSB is 1 28us J5is a GS 10 9 3 2 5 volt module To incorporate please contact factory Temperature spec is C 0 C to 70 C E 40 C to 85 C see part number 3 2 K2 Pullup Down Configuration is 1 for Pull up and 0 for Pull down 1 is default E2 is O GS 10 14 3 15 volts peak 3 3 Page 4 TTL debounce is 1 to 255 microseconds D1 o p 50ma 4 micro sec GS 11 12 3 3 4 RTD module accuracy is 0 80 for 2kQ range 0 270 for 6550 range Module E operates GS 1 5 4 64 C1 A001 Rev 6 3 do North At
41. configuration the Input data read or Output logic write of the operational channel and test comparator must agree or a fault is indicated with the results available in the associated status register Low to High and High to Low logic transitions are indicated Additional testing of output logic indicates Over current condition when output logic is invalid for a period greater than 80us Status indications Fault processing data read or write logic is inconsistent with redundant test circuit Status is indicated within 15 seconds A fault is latched until read Testing takes approx 1 second per channel Lo Hi Transition If a Lo to High transition is sensed status is indicated bit is set within 40us Hi Low Transition If a High to Low transition is sensed status is indicated bit is set within 40us Over current If over current or overload condition is sensed status is indicated bit is set within 80us Output is however immediately disabled at time of over current condition When status is indicated or bit is set bit value is logic 1 Reading will reset or unlatch Status Register D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 01 DO Status Fault 16 15 14 Ch 13 Ch 12 Ch 11 10 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Over Current
42. platform s SSK contents include html format help documentation which defines board specific library functions and their respective parameter requirements A board specific library and its source code is provided module level c and header files to facilitate function implementation independent of user operating system O S Portability files are provided to identify Board Support Package BSP dependent functions and help port code to other common VME BSPs With the use of the provided help documentation these libraries are easily ported to any 32 bit O S such as PSOS or Linux The latest version of a board specific SSK can be downloaded from our website www naii com Select the software downloads section A Quick Start Software Manual is also available for download where the SSK contents are detailed Quick Start Instructions provided and GUI applications are described therein 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7114 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 19 of 74 ADDRESS CONFIGURATION The VME bus interface will respond to A32 D16 A24 D16 and A16 D16 cycles A32 mode Unit responds to address modifiers OD OE and 09 Base address can be set anywhere in the 4 Gigabyte address space on 256 byte boundaries A24 mode Responds to address modifiers 3A 3D 3E and 39 Base address can be set anywhere in the 16 Megabyte addr
43. 021 29 NC M1Ch02 1 1 4 NC M1Ch01 RH M1Ch03 H 23 1 031 1 02 EXL 1 4 NC 1 01 M1ChO3L 4 31a M1Ch04H 1 2 H M1Ch02 Sig H M1Ch05 M1Ch05 M1Ch01 1 02 51 1 4 H 24 M1Cho4L M1Ch02L M1Ch02SigL M1Ch06 M1Ch06 GND M1Ch02S3 1 4 L 5 25c 1 05 NC M1Ch03EXH 1 07 M1Ch07 NC M1Ch02S2 M1Ch05H 25 26c M1ChO5L NC M1Ch03EXL M1Ch08 M1Ch08 NC M1Ch02 54 M1ChO5L 6 17d AGND NC M1Ch03SigH 1 5 8 NC M1Ch02 M1Ch02 RH M1Ch06 H 26 18d NC NC M1Ch03SigL 1 NC GND M1ChO2RL M1Ch06 L 40 27c M1Ch06H M1Ch03H M1Ch04 EX M1Ch09 M1Ch09 NC M1Ch03 51 M1GND 60 28 M1Cho6L 1 031 M1Ch04 M1Ch10 M1Ch10 NC M1Ch03 63 M1GND 41 29c M1Cho7H NC M1Ch04 Sig H 1 11 M1Ch11 M1Ch03 M1Ch03S2 M1Ch07 H 61 30c MIChO7L NC 1 04 Sig L 1 12 M1Ch12 GND M1Ch03 54 M1Ch07 L 42 31c MICh08H NC M1Ch05 1 12 NC NC M1Ch03 RH 1 H 62 32c M1Cho8L NC M1Ch05EXL M1Gnd9 12 NC NC M1ChO3RL M1Ch08 L 43 8a M1Ch09H M1Ch04H M1Ch05 Sig H 1 13 M1Ch13 M1Ch04 1 04 51 M1Ch09 H 63 9a M1ChO9L 1 041 M1Ch05 SigL 1 14 M1Ch14 GND M1Ch04 S3 1 091 10a M1Ch10H NC M1Ch06 EX H 1 15 M1Ch15 NC M1Ch04 S2 M1Ch10H 64 1 MICh10L NC M1Ch06 EXL M1Ch16 M1Ch16 NC M1Ch04 54 M1Ch10L 45 19d
44. 1 Adds Module E1 GS 11 25 2 1 6 Changes J3 amp J5 from 10 to 350 us settling time REMOVED FROM DESC These GS 11 26 2 multifunction cards require specific firmware and depending upon the functions required a select number of combinations may not be readily available Please contact factory customer service for availability Module C1 2 Open Status updated in 10 seconds 1 7 RTD Memory Map status register name is for 6 not 10 channels GS 12 5 2 1 8 Eliminated Module Descriptions Appendix 1 2 amp 3 Add Special Option Code used for code GS 12 10 2 99 remove shunt JP2 pin 7 8 remove jump to disable geographical addressing Added Module C3 to Spec parametric section Hid Signal Module E1 F1 non linearity is 0 0196 not 0 03 and Gain error is 0 02 not 2 1 9 Platform 64 is 3634 hex C amp 1 GS 1 712 Added Reference Specification Revealed Revision Control Sheet 2 0 Adds weight for each module ref and mother board GS 1 8 03 2 1 Adds Module list to PN Spec section and module details to description GS 1 03 Adds Signal Module E Spec and Memory Map Adds 120ohms and filter to D2 spec Adds Discrete Rear Panel wiring for MnGnd Common 2 2 Adds Preliminary to Module E1 Spec and Function Description GS 1 29 3 2 3 Appended Interrupt Level description to include The Interrupt service routine should read the GS 2 3 3 associated status register to unlatch data so additional faults will trigger another Interrupt Adde
45. 11 R W 066 Debounce time 10 R W ID R 00C Debounce time Ch 1 R W 070 Debounce time Ch 11 R W 000 Status Fault Ch 01 11 R 016 Debounce time Ch 2 R W 0A2 Input Termination Ch 01 11 R W 0D4 Status Over Current Ch 01 11 R 020 Debounce time Ch 3 R W 0 4 Input Output Format Ch 1 8 R W ODC Status Lo Hi Transition Ch 01 11 R 02A Debounce time Ch 4 R W 0A6 Input Output Format Ch 9 11 R W ODE Status Hi Lo Transition Ch 01 11 R 034 Debounce time Ch 5 R W 0C0 Module Design Version R 0 Interrupt Fault Enable Ch 01 11 R W Debounce time Ch 6 R W 0C2 Module Design Revision R OEC Interrupt Over Current Enable 01 11 R W 048 Debounce time Ch 7 R W 0C4 Module DSP1 R 0 4 Interrupt Lo Hi Transition Enable Ch 01 11 R W 052 Debounce time Ch 8 R W 0C6 Module 11 R OF6 interrupt Hi Lo Transition Enable 01 11 R W Note 1 As of July 2005 Write Output When channel is configured for Output write logic level High 1 or Low 0 to associated channel bit in 16 bit binary word Each bit corresponds to one of 11 channels REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 11 10 91817161514131211 Channel WRITE OUTPUT D DATA Read I O Independent of channel configuration Input or Output
46. 12 Ch 11 Ch 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Over Current Ch 16 Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Max Hi Threshold Ch 16 Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Min Lo Threshold Ch 16 Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Mid Range Ch 16 Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Lo Hi Transition Ch 16 Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Hi Lo Transition Ch 16 Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Fault Enable Ch 16 Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Over Current Enable Ch 16 Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Max Hi Threshold Enable Ch 16 Ch 15 Ch 14 Ch 13 12 Ch 11 Ch 10 Ch 9 Ch 8 ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Min Lo Threshold Enable Ch 16 Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Mid Range Enable Ch 16 Ch 15 Ch 14 Ch 13 Ch 12
47. Check the corresponding bit for a channel s BIT Status A 0 Normal 1 Non compliant A D conversion outside 0 296 FS accuracy spec Reading any status bit will unlatch the entire register BIT Status is part of background testing and the status register may be checked or polled at any given time 015 014 D13 D12 D11 D10 DB D7 06 D5 D3 D1 DO BIT Status X X X X X X Ch 10 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Open Status Check for an open or disconnect to the A D input Status of each channel is indicated at its corresponding bit A 0 Normal and 1 Open An open or disconnect to the input of an A D channel is detected within 10 seconds and will latch the corresponding bit in the Open Status register Reading any status bit will unlatch the entire register Open Status is part of background testing and the status register may be checked or polled at any given time NOTE Does not apply to Current Measurement Module C3 D15 D14 D13 D12 D11 D10 DB 07 06 D5 04 D3 01 DO Open Status X X X X X 10 ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 BIT Status Interrupt Enable Set the bit to enable interrupts for the corresponding channel When enabled a non compliant cha
48. D2 D1 DO FUNCTION ACTIVE CHANNEL x x x 2 1 CHANNEL ENABLE BIT 64_C1_A001_Rev_6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 711415 c 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 58 of 74 Latch Type 16 bit unsigned integer Range 0 or2 Read Write R Initialized Value 0 Writing the integer 2 to the Latch register will cause the channels to be latched Reading a particular channel will disengage the latch for that channel Writing a 0 to this register will disengage latch on all channels REGISTER D15 D14 D13 D12 D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION LATCH D DATA Angle 16 bit unsigned integer Range 0 to 359 9945 degrees Read Write W Initialized Value 30 Enter the DO test angle as per table REGISTER D15 D14 D13 D12 D11 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 180 90 45 22 5 11 2 5 62 2 81 1 401 703 352 176 088 044 022 011 0055 approximate value TEST ANGLE D D D DATA Degrees Two Speed Lock Loss Type binary word Range N A
49. D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE FPGA D DATA 10 ASCII character in each upper and lower byte Range N A Read Write R Initialized Value 4B31h Read register to determine Module ID in ASCII For example find ASCII K in upper byte and ASCII 1 in lower byte for Module K1 together 4B31h REGISTER 015 014 013 012 011 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE ID D DI IDIDID D D D D D D D DATA ASCII K ASCII 1 Automatic background BIT testing BIT is always enabled and continually checks that each channel is functional This capability is accomplished by an additional Test A D that is incorporated into each 16 channel module The Test A D is sequentially connected across each channel and compared against the operational channel Depending upon configuration the Input data read or Output logic write of the operational channel and Test A D must agree or a fault is indicated with the results available in the associated status register Additional testing is provided to check for Over current condition All four threshold levels must be set for each Input or Output channel to validate BIT testing The card will write 55h to the Test D2 Register every 30 seconds User can periodically clear the Test
50. M5Ch04 L 31 5d M5Ch05 NC M5Ch03 EXH 5 07 M5Ch07 NC M5Ch02 52 MBCh05 H 12 6d M5Ch05 L NC M5Ch03 EXL M5Ch08 M5Ch08 NC M5Ch02 54 M5Ch05 L 32 29d AGND NC NC M5Ch03 Sig M5Vcc5 8 NC M5Ch02 M5Ch02 RH M5Ch06 H 13 0 NC M5Ch03 SigL M5Gnd5 8 NC GND M5Ch02 RL M5ChO6L 66 74 M5Ch06 M5Ch03 M5Ch04 EXH M5Ch09 M5Ch09 NC M5Ch03 51 M5GND 47 8d M5Ch06 L M5Ch03 L M5Ch04 EXL M5Ch10 M5Ch10 NC M5Ch03 S3 M5GND 67 9 M5Ch07 H NC M5Ch04 Sig M5Ch11 M5Ch11 M5Ch03 M5Ch03 52 M5Ch07 H 48 10d M5Ch07 L NC M5Ch04 Sig M5Ch12 M5Ch12 GND M5Ch03 54 M5Ch07 L 68 11d MBCh08 H NC M5Ch05 EX H M5Vcc9 12 NC NC M5Ch03 RH M5Ch08 H 49 12d MBChO8 L NC M5Ch05 EX L M5Gnd9 12 NC NC M5ChO3 RL M5Ch08 L 69 13d M5Ch09 H M5Ch04 H M5Ch05 Sig M5Ch13 M5Ch13 M5Ch04 M5Ch04 S1 M5Ch09 H 50 14d MBChO9 L M5Ch04 L M5Ch05 Sig L M5Ch14 M5Ch14 GND M5Ch04 S3 M5Ch09 L 70 15d M5Ch10 H NC M5Ch06 EXH M5Ch15 M5Ch15 NC M5Ch04 52 5 1 H 511 1641 MBCh10L NC M5Ch06 EXL M5Ch16 M5Ch16 NC M5Ch04 54 5 1 L 71 292 NC NC M5Ch06 Sig M5Vcc13 16 NC NC M5Ch04 RH M5Ch11 H 52 31z NC NC M5Ch06 Sig L M5Gnd13 16 NC NC M5Ch04 RL M5Ch11L SLOT 6 J2 PO AD DA DA J7 RTD Discrete TTL Signal S D Differential 14 A1 M6Ch01 H M6Ch01 H M6Ch01 EXH M6Ch01 M6Ch01 NC Not Used M6Ch01 H 34 2 M6Ch01 L M6Ch01 L M6Ch01 EXL M6Ch02 M6Ch02 NC Not Used M6Ch01 L 15 M6Ch02 H NC M6Ch01 Sig M6Ch03 M6Ch03
51. Module Design Revision Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design revision code in ASCII For example ASCII B in upper byte and ASCII space in lower byte for Module Design Revision B is together 4220h REGISTER 015 014 013 012 011 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULEDESIGNREVISION D D D DATA ASCII ASCII Module DSP Type binary word Range 1 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module DSP revision For example 0x000B is revision 12 REGISTER 015 014 013 012 011 D10 09 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE DSP D DATA BIT Module FPGA binary word Range 1 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module FPGA revision For example 0x000B is revision 12 REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 DO FUNCTION MODULE FPGA D DA
52. N A Read Write R Initialized Value N A This register holds module design revision code in ASCII For example ASCII B in upper byte and ASCII space in lower byte for Module Design Revision B is together 4220h REGISTER 015 014 013 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE DESIGN REVISION D 00 0 0 0 D DATA BIT ASCII ASCII 64 C1 A001 Rev 6 3 do 7 14 5 Cage Code OVGU1 Page 53 of 74 631 567 1100 631 567 1823 fax www naii com e mail sales naii com North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 Module DSP Type binary word Range 0 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module DSP revision For example 0x000B is revision 12 REGISTER 015 014 013 0121011 D10 D9 D8 D7 D6 05 D4 D3 D2 D1 DO FUNCTION MODULE DSP D DATA BIT Module FPGA binary word Range 0 to 65535 Read Write Initialized Value N A Read register as 16 bt binary word to determine Module FPGA revision For example 0x000B is revision 12 REGISTER 15 014 013 012 11 010
53. NC NC M1Ch06 Sig M1Vcc13 16 NC NC M1Ch04 RH MICh11H 65 20d NC NC M1Ch06 Sig L M1Gnd13 16 NC NC M1Ch04 RL M1Ch11L SLOT 2 J1TP2T AD DA 27 RTD Discrete TTL Signal S D Differential 27 12a M2Ch01H 2 H M2Ch01 EX M2Ch01 M2Ch01 NC M2Ch01 51 M2Ch01H 8 13a M2ChO1L M2Cho1L M2Ch01EXL M2Ch02 M2Ch02 NC M2Ch01 53 M2Ch01L 28 14a M2Ch02H M2Ch01 SigH M2Ch03 M2Ch03 NC M2Ch01 82 M2Ch02H 9 15a M2Cho2L M2Ch01SigL M2Ch04 M2Ch04 NC M2Ch01S4 M2Ch02L 29 16a M2Ch03H NC M2Ch02 EXH 2 1 4 NC M2Ch01 RH M2Ch03 H 10 17a M2Ch03L NC M2Ch02 EXL M2Gndi 4 NC NC M2Ch01RL M2Ch03 L 30 18a M2Ch04H M2Ch02H M2Ch02 Sig M2Ch05 M2Ch05 M2Ch01 M2Ch0281 2 4 H 11 19 M2Ch04L M2Ch02L M2Ch02 SigL M2Ch06 M2Ch06 GND M2Ch02 53 M2Ch04L 31 20 M2Ch05 H NC M2Ch03 EX H M2Ch07 M2Ch07 NC M2Ch02 52 M2Ch05H 12 21a M2Ch05L NC M2Ch03 EXL M2Ch08 M2Ch08 NC M2Ch02 54 M2Ch05L 32 21d AGND NC NC M2Ch03 Sig H M2Vcc5 8 NC M2Ch02 M2Ch02 RH M2Ch06 H 13 224 NC NC M2Ch03SigL M2Gnd5 8 NC GND M2Ch02RL M2Ch06 L 66 23a M2Ch06H M2Ch03H M2Ch04 EX H M2Ch09 M2Ch09 NC M2Ch03 51 M2GND 47 24a M2Ch06L M2Ch03L M2Ch04 EXL M2Ch10 M2Ch10 NC M2Ch03 63 M2GND 67 8c M2Ch07H NC M2Ch04 Sig M2Ch11 M2Ch11 M2Ch03 M2Ch03 S2 M2Ch07 H 48 9c M2Ch07L M2Ch04 Sig L_ M2Ch12 M2Ch12 GND M2Ch03 54 M2Ch07 L 68 10c M2Ch08H NC M2Ch05 EX 2 9 12 NC NC M2
54. NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 43 of 74 Type 16 bit unsigned integer Range 0 or 1 Read Write RAW Initialized Value 0 Write 0 for a 0 655 ohm output range 0 01 Q bit Write 1 for a 1 2000 ohm output range 0 03 Q bit REGISTER 015 014 013 012011 010 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION RANGE D DI DIDID D D DID D D 3 or 4 Wire Mode Consult Factory Module Design Version Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design version in ASCII For example ASCII 1 in upper byte and ASCII space in lower byte for Module Design Version 1 is together 3120h REGISTER 015 014 013 012 011 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE SPECIAL SPEC D D D DID 000 00 0 D DATA BIT ASCII 1 ASCII Module Design Revision Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design revision code in ASCII For example ASCII B in upper byte and ASCII space in lower byte for Module Design Revision B is together 4220h
55. Program Reference Voltage where LSB is 0 1 Vrms For Example 26 1 Vrms 0000 0001 0000 0101 Reference Module is Optional REGISTER 015 014 1013 012 011 0 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 125 6 12 8 6 4 3 2 1 6 8 4 2 approximate value VOLTAGE D DATA Vrms 64_C1_A001_Rev_6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 60 of 74 Design Version ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design version in ASCII For example ASCII 1 in upper byte and ASCII space in lower byte for Module Design Version 1 is together 3120h REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE SPECIAL SPEC D D D DID 0 0 0 0 0 0 D DATA ASCII 1 ASCII Module Design Revision Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design revision code in ASCII For example ASCII B in upper byte and ASCII spac
56. Specify voltage to be applied by DO test to A D module under test DO test is performed only on A D modules If using bi polar mode write 16 bit 25 complement word 7FFFh FS 8000h FS If using uni polar mode write 16 bit binary word range 0 to FFFFh FS Example 1 if using uni polar mode with 10v range enter 8000h for 5v test voltage Example 2 if using bi polar mode with 10v range enter 4000h for 5v test voltage Enter 000 for 5v D A Reset to Zero Write 1 to drive all D A outputs to zero When complete D A Reset to Zero register will be automatically set to 0 D A Retry Overload Write 1 to D A Retry overload register to enable all channels board wide whose outputs were previously set to zero because of an overload condition If and overload condition still exists the channel output s will again be set to zero While enabled all overloaded channel outputs will be again be reset approximately every second Default is 0 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 65 of 74 D A Reset Overload This register is used to reset all channels whose outputs were previously set to zero because of an overload If an overload condition still exists channel output s will again be set to zero Channel output reset will occur one time only D A Reset overload regi
57. a current source in groups of 4 that user programs to a desired current level When programmed for Output each channel can be set for either High side Lo side or Push Pull operation Modules K2 and K4 add diode clamping useful for inductive loads such as User Interface Discrete IO Module Block Diagram 44 16 Protective Circuits Threshold 1 IN OUT 1 OUT 1 IN 1 Module Bus State Machine 1 INMOUT 16 lt 1 ouT16 Threshold 16 IN 16 Wrap Around 16 MUX Test Channel relays and thermal protection Module K2 is signal isolated from the VME bus while both module K2 and 4 are power isolated from the VME bus There are 4 user provided Vcc inputs for each 16 channel module There is one Vcc input for each four channel bank Vcc must be wired for proper operation Module K6 K6 is recommended for new designs Similar to K2 operation with enhanced features Each channel is programmable for either Input or Output When programmed for Input they can be used for either voltage or contact sensing Voltage sensing covers the range of 0 to 80 VDC and offers four levels of switching thresholds Channels set for contact sensing can be programmed for either pull up or pull down Our unique design eliminates the need for pull up resistors or mechanical jumpers Instead we offer a current source in groups of 4
58. channels to be reset by either an automatic retry or by a control port command 10 20 microseconds channel Designed to meet the testing requirements of IEC 801 2 Level 2 4 transient with a peak current of 7 5A and a time constant of approximately 60 ns 12 at 145 ma typical 192 ma max 5 VDC at 91 ma typical 150 ma max 1 oz 28g 10 D A Outputs 22 5 VDC VME ISOLATED 2 5 VDC or 0 to 2 5 VDC programmable For other ranges contact factory Output is set to 0 at reset or Power on 16 bits channel for either output range 0 05 FS lt 1 mV over temperature Optically isolated in groups of ten 250 V to VME power 350 hs max 20 ma channel max Source or Sink Can drive a capacitive load of 0 1 mfd 5 KQ min Short circuit protected When current exceeds 20 ma for any channel for gt 50ms that channel is set to zero and a flag is set Card is programmable to allow all channels to be reset by either an automatic retry or by a control port command 10 20 microseconds per channel Designed to meet the testing requirements of IEC 801 2 Level 2 4KV transient with a peak current of 7 5A and a time constant of approximately 60 ns 12 VDC at 145 ma typical 192 ma max 5 VDC at 91 ma typical 150 ma max 1 oz 28g 64 C1 A001 6 3 do 631 567 1100 631 567 1823 fax 7 14 5 Cage Code OVGU1 Page 13 of 74 D A Module 47 Output range Returns Resolution Accuracy Settling time Load Outpu
59. connected to the I O Each channel will be checked to a test accuracy of 0 296 FS Test cycle is completed within 45 seconds and results can be read from the Status registers when D3 changes from 1 to 0 The test can be stopped at any time This test requires no user programming and can be enabled or disabled via the bus CAUTION D A Outputs are active during this test Check connected loads for interaction D A Over Current short circuit monitoring is disabled during D3 testing MODULE MEMORY MAP 000 Data 1 R W 014 Polarity 1 R W 028 Wrap around 1 R W 0 0 Module Design Version R 002 Data 2 R W 016 2 R W 02 Wrap around 2 R W 0 2 Module Design Revision R 004 Data 3 R W 018 R W 02C Wrap around R W 0 4 Module DSP1 R 006 Data 4 R W 4 R W 02 Wrap around 4 R W 0 6 Module FPGA 11 R 008 Data 5 R W 01C 5 R W 030 Wrap around 5 R W 8 FPGA 21 R 00A Data 6 R W 01E 6 R W 032 6 R W Module ID R 00C Data 7 R W 020 7 R W 034 Wrap around 7 R W 000 Status Ch 1 10 R OOE Data 8 R W 022 8 R W 036 Wrap around 8 R W 004 Over Current Status Ch 1 10 R 010 Data 9 R W 024 9 R W 038 Wrap around 9 R W 0 8 Stat Interrupt Enable Ch 1 10 R W 012 Data 10 R W 026 Polarit
60. dB min at 60 Hz Roll off to 50 dB min at 10 KHz Signal voltage plus Common mode equals 10 5 volts Bipolar output in two s complement 7FFF is max positive 8000 is max negative Unipolar output range from 0 to FFFF full scale Designed to meet the testing requirements of IEC 801 2 Level 2 4 transient with a peak current of 7 5A and a time constant of approximately 60 ns 12 25ma typical 50 ma max As of 4 5 05 no 12 VDC requirement 5 VDC at 320 ma typical 500 ma max As of 4 5 05 500ma typical 750ma max 1 oz 28g 64 C1 A001 Rev 6 3 do 7 14 5 Cage Code OVGU1 Page 8 of 74 631 567 1100 631 567 1823 fax www naii com e mail sales naii com A D Module C2 Resolution Input format Input scaling Over voltage protected Input Impedance Accuracy Linearity error Sampling rate Bandwidth Group delay Programmable filter Common mode rejection Output Logic ESD protection Power Weight A D Module Resolution Input format Input scaling Input voltage Input Impedance Accuracy Linearity error Sampling rate Bandwidth Group delay Programmable filter Common mode rejection Common mode voltage Output Logic ESD protection Power Weight North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 Ten 10 A D 40VDC Uni or bipolar 16 bit A D converters One per channel Differential may be used as single ended by grounding
61. is 179 99 The synthetic reference circuit automatically compensates for phase shifts between transducer excitation and output up to 60 16 bit resolution Linearity 0 1 Scalable to 0 1 sec resolution The three different powerful test methods are detailed in the Description section and further described in the Programming Instructions 5 VDC 11mW at 26VLL 31mW at 90VL L 1 oz 28g Include as Required 2 0 28Vrms programmable resolution 0 1Vrms or 115Vrms Fixed 2 360Hz to 10kHz 1 with 1Hz resolution 10 max No load to full load 5VA max 40 min inductive 190mA RMS 2 26VAC or 45mA RMS 0 115VAC Note Power is reduced linearly as the Reference Voltage 64 C1 001 6 3 do 631 567 1100 631 567 1823 fax 7 14 5 www naii com e mail sales naii com Cage Code OVGU1 Page 17 of 74 Power Dissipation 5VA Load peak Weight 2 oz 28g S D Module 52 Four 4 60 400Hz Synchro Measurement Same as Module S1 Except Tracking Rate 13 5 RPS for 60 400Hz Referred to the Fine input for two speed configuration Bandwidth 10 Hz Frequency Input 47 400 2 64 C1 001 6 3 0 North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7114 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 18 of 74 SOFTWARE SUPPORT The VxWorks Software Support Kit SSK is supplied with all VME platform based board level products This
62. of July 2005 Write D A Output If using bi polar mode write 16 bit 2 s complement word to the channel s Data register 7 FFFh FS 8000h FS If using unipolar mode write 16 bit binary word to the channel s Data register range 0 to FFFFh FS Because output resolution is 12bits enter LSBs DO through D3 as zero At power on output is initialized to 0 volts REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D D5 D4 D3 D2 01 DO FUNCTION MODULE ID D DATA 64 C1 001 6 3 0 North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 711415 c 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 40 of 74 D A Output Range Program voltage range for channel pairs 1 amp 2 or 3 amp 4 from 20 to 80 volts For 20 volts enter integer 20 Resolution is 10 volts 10 ma channel maximum source or sink for up to 80VDC REGISTER 015 014 01301210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 64 32 16 8 4 2 1 value volts LSB 1volt D D D DATA 1 0 1 0 0 20 volts 1 1 1 1 0 30 volts 1 0 1 0 0 0 40 volts 11 0 0 1 0 50 volts 11111111010 60 volts 110
63. on the operation of this card and can be enabled or disabled via the bus In addition all channels are monitored for open input except for Current Measurement Module C3 applications The D3 test starts an initiated test that disconnects all A D s from the and then connects them across an internal stimulus Each channel will be checked to a test accuracy of 0 2 FS and monitored for open inputs Test cycle is completed within 45 seconds and results can be read from the Status registers when changes from 1 to 0 The test can be stopped at any time and requires no user programming and can be enabled or disabled via the bus A DO test is used to check the card and VME interface Write 1 to DO of Test enable register to disconnect all A D channels from the I O and connects them across an internal D A Test parameters are controlled by the user and are entered in the DO Test Voltage and DO Test Range registers The outputs from the A D channels are monitored by an internal D A for proper conversion External reference voltage is not required A D Open Circuit monitoring is disabled during D3 testing Signal anc Reference Transformer e State Machine User Interface Module Bus MODULE MEMORY MAP 000 Data 1 R 014 Range amp Polarity 1 R W 028 Filter Break Freq 1
64. programming is accurate to spec at a programmed frequency of more than or equal to 10 Hz E1 output regulation is 796 Updates DA J7 Output Range programming LSB is 10v J7 Bit tests to 296 accuracy 48 Adds Module R2 R3 and R4 J7 is 10ma max channel up to 80V output Current reduced GS 1 4 5 up to 90VDC Reference module is for SD or RD applications only Removes When phase locked phase is reset when channel 1 frequency is changed If phase is NOT GS 1 25 5 4 9 locked phase remains unchanged when frequency is changed AD module C1 is over voltage protected to 12v continuous Module J3 J5 F1 and J7 are VME ISOLATED Unipolar bipolar bit is D4 Appends RTD GS 2 14 5 5 0 interface to include interface to any RTD in the operating range of 0 2000ohms J7 output is from 20 to 80 volts 54 K3 output is 0 VDC to 40 VDC Output logic is defined by the user provided Vcc voltage gt GS 3 2 5 8 volts to that channel bank There are four channels per bank 5 2 All D modules debounce LSB is 1 28 microseconds GS 3 29 5 5 3 Module input voltage Not to exceed 3 volts GS 3 31 5 5 4 Range and Polarity to C1 module programs up to 10 volt range GS 4 11 5 55 Update AD power requirements As of 4 5 05 5 is 500ma typ 750ma max no 12V GS 4 26 5 For 5V Discrete applications use D1 Adds Module Special Spec DSP 8 registers 5 6 Replaces Module Special Spec with Module Design Revision Adds Module Design Version GS 5
65. without current pull down X NO current source 0 1 Output Ch1 4 High Side Drive 170 Ch1 4 with current pull down 14 1 ma 10 1 Output Ch5 8 High Side Drive 43520 Ch5 8 with current pull down 13 2ma 20 1 Output Ch1 8 High Side Drive 43690 Ch1 8 with current pull down 12 2ma 20 2 Output Ch1 Low Side Drive 1 without current pull up X NO current source 0 2 Output Ch1 4 Low Side Drive 85 Ch1 4 with current pull 1 1 10 2 Output Ch1 8 Side 21845 Ch1 8 with current pull 3 2 ma 20 3 Output Ch1 Push Pull 3 Not Applicable DON T CARE X Not Applicable DON T CARE X Note 1 Use current source for Wired OR or other related applications OUTPUT CONFIGURATIONS m High Side VCC Low Side Drive Push Pull Drive H gt VO Pin LOAD i IO Pin P VO Pin e Zin gt LOAD Szin 4 ry zx 4 L Figure 1 Figure 2 Figure 3 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 51 of 74 Input Programming Examples INPUT OUTPUT PULL UP DOWN Configuration CURRENT FOR SOURCE SINK integer igu 2 bits pe
66. 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 25 6 12 8 6 4 3 2 1 6 0 8 0 4 0 2 0 1 value in volts LSB 100mv VCC VALUE D DATA BIT Over Current Write integer 1 to reset all sixteen channels module This register is used to reset disabled channel s set to tri state following an over current condition When reset process is complete processor will write a 0 back to the Reset Over Current register Card will respond to a Reset command after one second REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION RESET OVER CURRENT X X X X X X X D DATA BIT Module Design Version Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design version in ASCII For example ASCII 1 in upper byte and ASCII space in lower byte for Module Design Version 1 is together 3120h REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE SPECIAL SPEC 0 000 0 D DATA ASCII 1 ASCII Module Design Revision Type ASCII character in each upper and lower byte Range
67. 0 14 bit Encoder Resolution Integer 3 0 0 1 1 13 bit Encoder Resolution Integer 4 0 1 0 0 12 bit Encoder Resolution Integer 32768 1 0 0 0 4 Pole Commutation Integer 32769 1 0101 6 Pole Commutation Integer 32770 1 0 1 0 8 Pole Commutation Synchro Resolver binary word Range N A Read Write RAW Initialized Value N A Individually configure each channel for Synchro 1 Resolver 0 measurement REGISTER 015 014 013 012011 010 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION SYNCHRO RESOLVER X X X X X X J Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 CHANNEL BIT Reference Frequency Type 16 bit unsigned integer Range 360 to 10 000 Hz Read Write R W Initialized Value N A S R or L R module Dependant Program Reference Frequency where LSB is 1 Hz For Example 400 Hz 0000 0001 1001 0000 Reference Module is Optional REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 FUNCTION 8192 4096 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 approximate value FREQUENCY D DATA BIT Hz Reference Voltage Type 16 bit unsigned integer Range 2 0 to 28 0 Vrms Read Write R W Initialized Value N A S R or L R module Dependant
68. 01 2 Level 2 4KV transient with a peak current of 7 5A and a time constant of approximately 60 ns 5 VDC at 30 A then add power for each individual module C 0 C to 70 C 40 C to 85 C see part number 55 C to 105 C Each board is cycled from 40 C to 85 C for 24 hrs option E or see part number 6U 9 2 height 4HP 0 8 width 233 4 mm x 20 3 mm x 160 mm deep 16 oz 454g unpopulated add weight for each module typically 1 each add 2 oz 57g for reference supply add 2 oz 57g for wedgelocks Ten 10 A D 1 25 VDC to 10 0 VDC FS Uni or bipolar 16 bit A D converters One per channel Differential may be used as single ended by grounding one input Ten 10 bipolar or unipolar channels Programmable per channel as F S inputs of 10 00 5 00 2 50 or 1 25 volts where range is FS or 0 to FS VDC The ability to set lower voltages for Full Scale assures the utilization of the full resolution No damage up to 12 V continuous 30 V momentary This module will sense and report unconnected Inputs 1 MO min 0 05 FS over temperature no missing codes to 16 bits 1 25 LSB s max over temperature 50 KHz per channel 20 KHz 770 microseconds time for data sample to propagate to data register Each channel incorporates a fixed second order anti aliasing filter and a post filter that has a digitally adjustable break point programmable from 10 Hz to 10 KHz in 10 Hz steps 70
69. 06 M6Vcc13 16 NC NC Not Used M6Ch11 H 78 C4 NC NC M6Ch06 Sig M6Gnd13 16 NC NC Not Used M6Ch11 L 59 N A Control Hi Control Control Hi Control Hi NOTE 1 Contact Factory AGND NC is AGND for A D Module and NO CONNECT for D A Module ALL D A Low signals MxChxx Sig L are connected to AGND Common within that module isolated from all other modules and isolated from the VME bus For DISCRETE Modules where n 1 to 6 MnGnd1 4 MnGnd5 8 MnGnd9 12 and McGnd13 16 are all common for that module However each pin should be individually wired for optimal power current distribution throughout that module MnGnd and MnVcc MUST be wired for proper operation 64 C1 A001 Rev 6 3 do 7 14 5 Cage Code OVGU1 Page 71 of 74 North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 631 567 1100 631 567 1823 fax www naii com e mail sales naii com Encoder Commutation Output Connection PO Connector PO MODULE 4 2 MODULE 5 A1 AHI CH1 C5 AHI CH1 A2 ALO CH1 A6 ALO CH1 BHI CH1 B6 BHI CH1 A4 BLO CH1 C6 BLO CH1 A5 IDXHI CH1 D6 IDXHI CH1 B5 IDXLO CH1 IDXLO CH1 B1 2 E7 AHI CH2 B2 ALO CH2 D7 ALO CH2 B3 2 2 4 BLO CH2 B7 BLO CH2 C1 IDXHI CH2 A7 IDXHI CH2 C2 IDXLO CH2 A8 IDXLO CH2 D1 AHI CH3 9 AHI CH3 021 ALO CH3 10 ALO C
70. 1 in lower byte for Module S1 together 5331h Slot 4 will be populated with an S1 module for 4 or 8 channel applications Slot 5 will be populated with an S1 only in 8 channel applications Slot 6 will be unused ZO REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE ID D DI DIDID D D D D D D ASCII 5 ASCII 1 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 61 of 74 Status binary Range 0 to 15 Read Write R Initialized Value 0 Check the corresponding bit for a channel s Built In Test BIT Status Channel Status Data bit Chn where n is 1 2 3 or 4 is fail high true and indicates that the channel is not operating spec compliant Status is latched Reading any status bit will unlatch the entire register BIT Status is part of background testing and the status register may be checked or polled at any given time REGISTER 015 014 013 012011 010 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION BIT STATUS X X X Xi X X X X ICh8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 CHANNEL STATUS BIT Sig
71. 10 D A Outputs 2 5 VDC VME ISOLATED D A Module J7 Four 4 D A Outputs 20 to 80 VDC VME ISOLATED Module D1 Module D2 I O Module K2 Module Module K6 RTD Module G1 R D Module R2 Sixteen 16 TTL 5V System Logic Supply Programmable for Input or Output Eleven 11 Differential Multi Mode Transceivers Sixteen 16 Discrete 0 40V ISOLATED Programmable for Input or Output K6 recommended for new designs Sixteen 16 Discrete 0 40V NON ISOLATED Programmable for Input or Output Sixteen 16 Discrete 0 80V ISOLATED Programmable for Input or Output Six 6 four wire Platinum RTD Four 4 400Hz 11 8Vgnys 11 8V Resolver Measurement R D Module R3 Four 4 400Hz Auto ranging Resolver Measurement Module R4 Four 4 1200Hz 26Vnys 11 8V Resolver Measurement S D Module S1 Four 4 400Hz Synchro Measurement S D Module S2 Four 4 60 400Hz Synchro Measurement ON BOARD REFERENCE MODULE USE FOR S D OR R D APPLICATIONS ONLY 0 No On Board Reference Module 1 2 28Vrms 360 10kHz Programmable On Board Reference Module 2 Reserved for future use 3 115Vrms Fixed 360 10kHz Programmable On Board Reference Module MECHANICAL F Front Panel J1 amp J2 and P2 amp PO I O S Front Panel J1 J2 and P2 I O No PO P P2 amp PO I O only G P2 I O only No PO W P With Wedgelocks VME64 Blank Front Panel and P2 amp PO I O only R VM
72. 11 D A MODULE F1 TEN 10 D A OUTPUTS 10 VDC VME 12 D A MODULE TEN 10 D A OUTPUTS 5 VDC 12 RTD MODULE G1 SIX 6 FOUR WIRE 13 D A MODULE J3 TEN 10 D A OUTPUTS 1 25 VDC 13 D A MODULE 75 TEN 10 D A OUTPUTS 2 5 VDC 13 D A MODULE J7 FOUR 4 D A OUTPUTS 20 TO 80 VDC VME ISOLATED 14 MODULE K1 SIXTEEN 16 DISCRETE NON ISOLATED PROGRAMMABLE FOR INPUT OR OUTPUT SUPERSEDED BY MODULE K2 14 Discrete NPU Am 14 Discrete OUI Ub ER PE laste Oued tap iter S b 14 V O MODULE K2 SIXTEEN 16 DISCRETE ISOLATED PROGRAMMABLE FOR INPUT OR OUTPUT 15 IM ES 15 Discrete Output Er 15 SIGNAL 15 0 15 MODULE K4 SIXTEEN 16 DISCRETE NON ISOLATED PROGRAMMABLE FOR INPUT OR OUTPUT 15 DISCRETE MODULE SIXTEEN 16 DISCRETE PROGRAMMABLE I O CHANNELS ISOLATED 0 TO 80 16 INPUT CHARACTERISTICS dee eed uu evade uua dau dete o Ret 16 OUTPUT CHARACTERISTICS eret
73. 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 23 of 74 Read Write Initialized Value Read register as 16 bt binary word to determine Module DSP revision For example 0x000B is revision 12 REGISTER 015 014 013 012 011 D10 D9 D8 D7 D6 05 D4 D3 D2 D1 DO FUNCTION MODULE DSP D D DATA Module FPGA Type binary word Range 1 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module FPGA revision For example 0x000B is revision 12 REGISTER 015 014 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 DO FUNCTION MODULE FPGA D DATA ID ASCII character in each upper and lower byte Range N A Read Write R Initialized Value 4331h Read register to determine Module ID in ASCII For example find ASCII C in upper byte and ASCII 1 in lower byte for Module C1 together 4331h REGISTER 015 014 013 012 11 D10 D9 D8 D7 D6 D5 D3 D2 D1 DO FUNCTION MODULE ID D D D D DATA BIT ASCII ASCII 1 Status
74. 2kQ across its inputs Interrupt can be selected for each channel to indicate transition on rising edge transition on falling edge or both De bounce circuits for each channel offer a selectable time User Interface delay to eliminate false signals resulting from contact bounce commonly experienced with mechanical relays and switches All inputs are continually scanned and the data is double buffered for immediate availability The D2 test initiates automatic background BIT testing which tests and validates channel processing data read or write logic tests for circuit over current conditions and fault status Any failure triggers an Interrupt if enabled with the results available in status registers The testing is totally transparent to the user requires no external programming and has no effect on the operation of this card It can be enabled or disabled via the bus MODULE MEMORY MAP 4 11 4 Differential Module Block Diagram F IN OUT 1 Dee OUT 1 Ifrterentia Buffer 1 IN 1 S a Protective e State Machine gt 1 IN OUT 11 OU Demi OUT 11 Ifrterentia Buffer 11 INT Wrap Arounc 11 MUX Test Channel 000 Write Output Ch 1 11 R W 05C Debounce time Ch 9 R W 0C8 FPGA 21 R 002 Read Ch 1
75. 4 Design Version ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design version in ASCII For example ASCII 1 in upper byte and ASCII space in lower byte for Module Design Version 1 is together 3120h REGISTER 015 014 013 012011 010 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE DESIGN VERSION D D D D 1 D D ID ID ID ID D ID ID D D D D DATA BIT ASCII 1 ASCII Module Design Revision Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design revision code in ASCII For example ASCII B in upper byte and ASCII space in lower byte for Module Design Revision B is together 4220h REGISTER 015 014 013 012 011 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULEDESIGNREVISION D D D DATA ASCII ASCII DSP Type binary word Range 0 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module DSP revision For example 0x000B is revision 12
76. 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 BIT Status Interrupt Enable Set the bit to enable interrupts for the corresponding channel When enabled a non compliant channel will trigger an interrupt Default is 001 to disable all channels D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 00 BIT Status Interrupt Enable X X X X X X Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Open Status Interrupt Enable Set the bit to enable interrupts for the corresponding channel monitored for Open Status D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Open Status Interrupt Enable X X X X X X Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 64_C1_A001_Rev_6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 15 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 45 of 74 DiscRETE MODULE Discrete LSI channels are programmable for either Input or Output When programmed for Input they can be used for either voltage or contact sensing Channels set for contact sensing can be programmed for either pull up or pull down Our unique design eliminates the need for pull up resistors or mechanical jumpers Instead we offer
77. 6 5 5 7 J7 range is 20 80 GS 5 17 5 58 Following soft reset 200ms before polling Board Ready GS 6 8 5 59 Module 02 Read corresponds to 11 channels Adds Reference Design Version and GS 6 28 5 Revision registers 6 0 Updated Encoder Pin Out GS 7 14 5 6 1 Updated with K6 module specifications and P N AS 8 23 06 6 2 Corrected front panel pin out pictorial pg 67 AS 11 6 06 6 3 New Address KL 04 24 07 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 75 of 74
78. 9240 96 20 48 10 24 5 12 2 56 1 28 value in mSec 188 1 28 8 DE BOUNCE TIME X X D D D D DD Dj D D DATA BIT Input Output Format Configure channels in groups of 8 Write integer O for input 3 for output Default is configured for Input REGISTER 015 0141013 1012011 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION INPUT OUTPUT CH 01 08 Ch 08 Ch 07 Ch 06 05 Ch 04 Ch 03 Ch 02 Ch 01 Channel INPUT OUTPUT CH 09 16 Ch 16 15 Ch 14 Ch 13 Ch 12 Ch 11 ch 10 09 Channel INPUT OUTPUT Du Di Du De Du DL Du De Du DL Dy Da Du Di D DATA BIT Integer Du DL 0 0 0 Input 3 1 1 Output Reset Over Current Write integer 1 to reset all sixteen channels per module Used to reset disabled channel s following an over current condition When reset process is complete processor will write a O back to the Reset Over Current register REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION RESET OVER CURRENT X X 1X X X X X D DATA Module Design Version Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design version in ASCII For example ASCII 1 in upper byte and ASCII space in lower byte for Modu
79. A J7 RTD Discrete TTL Signal S D Differential 1 16c M4Ch01 H M4Ch01 H M4Ch01 EX H_ M4Ch01 M4Ch01 NC M4Ch01 51 M4Ch01 H 21 17c M4Ch01 L M4Ch01 L 1 EXL MAChO2 M4Ch02 NC MACh01 S3 M4ChO1 L 2 18 MACh02 H NC M4Ch01 Sig M4Ch03 M4Ch03 NC M4Ch01 52 MACh02 H 22 19c M4Ch02 L NC M4Ch01 SigL M4Ch04 M4Ch04 NC MACh01 54 M4Ch02 L 3 20c MACh03 NC M4Ch02 M4Vcc1 4 NC NC M4Ch01 RH MACh03 H 23 21 MAChO3 L NC MACh02 EX L M4Gnd1 4 NC NC M4Ch01 RL MAChO3L 4 23c M4Ch04 H M4Ch02 M4Ch02 Sig M4Ch05 M4Ch05 M4Ch01 4 02 51 M4Ch04 H 24 24 M4Ch04 L M4Ch02 L M4Ch02 Sig L M4Ch06 M4Ch06 GND MACh02 53 M4Ch04 L 5 M4Ch05 NC M4Ch03 EX H M4Ch07 M4Ch07 NC MACh02 52 MACh05 H 25 2 M4Ch05 L NC M4Ch03 EXL MACh08 M4Ch08 amp NC MACh02 54 M4ChO5L 6 25dJAGND NC NC MACh03 Sig MaVcc5 8 NC M4Ch02 M4Ch02 MACh06 H 26 264 NC M4Ch03 Sig M4Gnd5 8 NC GND M4Ch02 RL M4Ch06 L 40 3al M4Ch06 H M4Ch03 M4Ch04 4 09 M4Ch09 NC MACh03 S1 M4GND 60 4a M4Ch06 L M4Ch03 L M4Ch04 EXL M4Ch10 M4Ch10 NC 53 M4GND 41 5al M4Ch07 H NC M4Ch04 Sig M4Ch11 M4Ch11 M4Ch03 M4Ch03 52 M4Ch07 H 61 M4Ch07 L NC M4Ch04 Sig L M4Ch12 M4Ch12 GND M4Ch03 54 M4Ch07 L 42 1c MACh08 H NC 5 EX H M4Vcc9 12 NC NC M4Ch03 RH MACh08 H 62 2 MACh08 L NC M4Ch05 EX L M4Gnd9 12 NC NC MACh03 RL M4Ch08L 43 3c MACh09 M4Ch04 H M4Ch05 Sig M4Ch13 M4Ch13 M4
80. A 21 R 32E Ch 4 Angle A R W 36E Reserved 4CE Module ID Slot 5 R 330 Ch 5 Angle A R W 370 Reserved 5C6 Module Design Revision R 332 Ch 6 Angle A R W 372 Reserved 5C8 Module Design Revision R 334 Ch 7 Angle A R W 374 Reserved Module DSP R 336 Ch 8 Angle A R W 376 Reserved 5CC Module FRGA R 338 Angle Init RAW 378 Reference Frequency 5CE Module ID Slot 6 R 33A DO Test Angle 37 Reference Voltage R Note 1 As of July 2005 Data Date Hi Type 16 bit unsigned integer Date Hi amp Lo Type 24 bit unsigned integer Multi Speed Applications Range 0 to 359 9945 degrees Read Write R For Single Speed 1 applications read Data High register of that channel For Multi Speed applications read Data High register of the even channel 2 or 4 for that pair where 16 bit resolution is required LSB is approximately 0 0055 degrees For better than 16 bit resolution Multi Speed requirements use Data High and Data Low registers combined to determine measured angle with up to 24 bit resolution First read Data High word then Data Low word Data high word when read latches low word Data Low word when read unlatches data LSB is dependant upon Ratio A gear ratio of 256 provides for a 24 bit resolution a ratio of 128 provides for a 23 bit resolution and so on The N speed information Multi Speed Fine from the synchro should be connected to the even chan
81. CER EPOR EL ARE RE EVENT Re EUREN o HN EIE bese ERR 43 MODULE DESIGN REVISION ee 43 MODUEE DS Bias 43 MODULE FPGA 43 No 44 STATUS E 44 OPEN 44 BIT STATUS INTERRUPT ENABLE ee 44 OPEN STATUS INTERRUPT ENABLE ccessccesssscecsssececsnseecessaeeecsnsaeeeceseeeeeesaeeecsssaeeeceaeeseesaeeecseaaeescueeessesuececseaeesesaeeesseaeeeeseaaees 44 VO DISCRETE MODULE K C 45 VO DISCRETE MODULE 4 46 WRITE OUEFPUT x orn ent citer PI Wem rd a Da DO oe RR ea ded S 47 aspi mc CELL 47 THRESHOLD PROGRAMM ING cessere eene ener nnne nennen sese sas ss 47 FAVES PERE GIS cece E A E O EE couse IE E 47 MAX HIGH THRESHOLD 47 UPPER THRESHOLD s 33 3 30555654 48 LOWER THRESHOLD ssecsccsscsseevsconeeseceves
82. Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 11 Ch 10 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 11 Ch 10 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 11 Ch 10 Ch 9 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 64_C1_A001_Rev_6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 1415 c 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 30 of 74 Status Fault Status Over Current Status Lo Hi Transition Status Hi Lo Transition Interrupt Fault Enable Interrupt Over Current Enable Interrupt Lo Hi Enable gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt Interrupt Hi Lo Enable X X X X X Ch 11 Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 631 567 1100 631 567 1823 fax www naii com e mail sales naii com 7 14 5 Cage Code OVGU1 64_C1_A001_Rev_6 3 do 31 of 74 SIGNAL GENERATOR MODULE E Signal Generator mod
83. Ch03 RH M2Ch08 H 49 11c M2Ch08L NC M2Ch05 EXL M2Gnd9 12 NC NC M2Ch03 RL M2Ch08 L 69 12c M2Ch09H M2Ch04 H M2Ch05 Sig H M2Ch13 M2Ch13 M2Ch04 M2Ch04 51 M2Ch09 H 50 13c M2Ch09L M2Ch04 L M2Ch05SigL 2 14 M2Ch14 GND M2Ch04 53 M2Ch09 L 70 14 M2Ch10H NC M2Ch06 M2Ch15 M2Ch15 NC M2Ch04 S2 M2Ch10H 51 15c M2Ch10L NC M2Ch06 EXL M2Ch16 M2Ch16 NC M2Ch04 54 M2Ch10L 71 23d NC NC M2Ch06 Sig H M2Vcc13 16 NC NC M2Ch04 RH M2Ch11H 52 24d NC NC M2Ch06 Sig L M2Gnd13 16 NC NC M2Ch04 RL M2Ch11L 64 C1 001 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 711415 c 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 69 of 74 SLOT 3 J1 2 AD DA DA J7 RTD Discrete TTL Signal S D Differential 14 14 M3Ch01 H M3Ch01 H M3Ch01 EXH M3Ch01 M3Ch01 NC Not Used M3Ch01 H 34 3z M3Ch01 L M3Ch01 L M3Ch01 EXL M3Ch02 M3Ch02 NC Not Used M3Ch01 L 15 5z M3Ch02 H NC M3Ch01 Sig M3Ch03 M3Ch03 NC Not Used M3Ch02 H 35 72 M3Ch02 L NC M3Ch01 Sig L M3Ch04 M3Ch04 NC Not Used M3Ch02 L 16 92 M3Ch03 NC M3Ch02 EXH M3Vcc1 4 NC NC Not Used M3Ch03 36 1921 M3Ch03 L NC M3Ch02 EX L M3G
84. Ch04 M4Ch04 51 MACh09 H 63 4 MAChO9 L M4Ch04 L M4Ch05 Sig L M4Ch14 M4Ch14 GND M4Ch04 S3 MAChO9 L 44 5c MACh10 H NC M4Ch06 EXH M4Ch15 M4Ch15 NC M4Ch04 52 M4Ch10 H 64 6c M4Ch10 L NC M4ChO6 EXL M4Ch16 M4Ch16 NC M4Ch04 54 M4Ch10L 45 274 NC M4Ch06 Sig M4Vcc13 16 NC NC M4Ch04 M4Ch11H 65 284 NC NC M4Ch06 Sig L M4Gnd13 16 NC NC M4Ch04 RL M4Ch11L 64_C1_A001_Rev_6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 70 of 74 SLOT 5 J2 P2 AD DA DA J7 RTD Discrete TTL Signal S D Differential 27 M5Ch01 H M5Ch01 M5Ch01 EXH M5Ch01 M5Ch01 NC M5Ch01 S1 M5Ch01 H 8 7 M5Ch01 L M5Ch01L M5Ch01 EXL 5 2 M5Ch02 NC M5Ch01 S3 M5Ch01L 28 22 5 2 H NC M5Ch01 Sig 5 M5Ch03 NC M5Ch01 S2 M5Ch02 H 9 22c MBChO2L NC M5Ch01 SigL M5Ch04 M5Ch04 NC M5Ch01 S4 5 2 L 29 19 M5Ch03 M5Ch02 EX H M5Vcc1 4 NC NC M5Ch01 RH M5Ch03 H 10 2d M5Ch03 L NC M5Ch02 EX L M5Gnd1 4 NC NC M5Ch01 RL M5Ch03 L 30 3d M5Ch04 H M5Ch02 H M5Ch02 Sig H M5Ch05 M5Ch05 M5Ch01 M5Ch02 51 M5Ch04 H 11 4 M5Ch04 L M5Ch02 L M5Ch02 Sig L M5Ch06 M5Ch06 GND M5Ch02 S3
85. Ch3 Ch2 Ch1 INTERRUPT ENABLE 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 63 of 74 GENERAL USE REGISTER MEMORY The registers of this memory map apply to the complete card The Test Enable and related registers affect all modules unless otherwise specified BIT tests are module dependant See module description for details MEMORY MAP 600 Part number R 61A Test D2 verify R W 636 Generation R 602 Serial number 61E Latch All A Ds R W 638 Special Spec R 604 Date Code R 620 A D DO Test Range R W 63A Interrupt Level R W 606 Rev Level PCB R 622 A D DO Test Voltage R W 63C Interrupt Vector BIT R W 608 Rev Level Processor 1 R 624 D A Reset to Zero R W 63E Interrupt Vector Open R W 60A Level Processor 2 R 626 D A Retry Overload R W 640 Interrupt Vector Over current R W 60C Rev Level FPGA R 628 D A Reset Overload R W 642 Interrupt Vector Max High Threshold R W 60E Rev Level FPGA 1 62A D A Override R W 644 Interrupt Vector Min Low Threshold R W 610 Rev Level FRGA 2 R 62C Reference Design Version R 646 Interrupt Vector Mid Range R W 612 Board Ready R 62E Reference Design Revision R 648
86. DC requirement 5 VDC at 320 ma typical 500 ma max As of 4 5 05 500ma typical 750ma max 1 oz 28g Sixteen 16 TTL Programmable for Input or Output TTL and CMOS compatible single ended inputs Each channel incorporates a 100 KO pull down resistor Vint 0 8 V 0 V inh 2 0 V 1 V in max 5 0 V iN 50uA 1 02 seconds Programmable per bit from 0 to 255 microseconds LSB 1 microsecond TTL CMOS single ended outputs V out L 0 5 V max sink 32 mA max V out H 3 8 V min source 32 mA max Channel will withstand a current of 50ma for 4 microseconds and will then be turned off 10 ns into a 50pf load 1 02 useconds 5 VDC System Logic Supply at 40mA per module 1 oz 28g 64 C1 A001 Rev 6 3 do 7 14 5 Cage Code OVGU1 Page 10 of 74 631 567 1100 631 567 1823 fax www naii com e mail sales naii com Module D2 Mode of Operation Input Receiver Input Levels Receiver Input Resistance Receiver Input Sensitivity Read Delay Filtering Output Driver Output Voltage Driver Output Signal Level Loaded minimum Driver Output Signal Level Unloaded maximum Driver Load Impedance Max Driver Current in Hi Z State Power ON Max Driver Current in Hi Z State Power OFF Write Delay Protection Rise Fall time Power Per 11 channel module Weight Signal Module E1 Output Signal Output Frequency Output Voltage Accuracy Load Regulation
87. DULE FEGA sires et 24 MODUEE ID conn M MENACE M EIE 24 STATUS m 24 OPEN TA TUS M M 24 BIT STATUS INTERRUPT ENABLE 24 OPEN STATUS Coe ER Ce e sn 24 VO DIGITAL MODULE UI 25 WRITE OUTPUT E 25 RADIO 25 SENS 26 INPUI OUTPUT FORMA Tossen ue vun 26 RESET OVER EC ORR EIN S 26 MODULE DESIGN VERSION es 26 MODULE DESIGN REVISION csesessssecececessssueceeececsesseaececececeeseauesecececsessussseseeecceeaaeaeeecececeesasaececscceseauaaesecececeesseeeeceseseasaeaeeses 26 MODULE DNS 26 MODULE FPGA 27 MODULE IDD 27 AUTOMATIC BACKGROUND BIT TESTING 27 STATUS INDICATIONS Ho ie ie des eH CERERI e a O EAE EEA SE E NEEE 27
88. E2 Read Write R W Initialized Value 0 Value determines DC offset of selected waveform in 0 30 millivolt resolution Enter as per formula DC Offset Voltage 10 Value 32768 Volts DC for Module E1 DC Offset Voltage 15 Value 32768 Volts DC for Module E2 Out of range data will be changed to the maximum allowable value REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION AMPLITUDE DID D DATA 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 o 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 33 of 74 Mode binary Range 0 1 or2 Read Write R W Initialized Value 0 Sine Wave This register is used to select desired waveform using bits DO and D1 Use bit D2 to enable phase lock function L 1 to enable L 0 to disable When phase lock is enabled channel 2 3 and 4 are phase locked to the master signal channel 1 When phased locked the signal of channels 2 3 and 4 will be identical to channel 1 in frequency and type sine triangular or square When phase locked phase is reset when frequency is changed REGISTER 015 014 013 D12 D11 D10 D9 D8 D7 D6 D5 D4
89. E64 Blank Front Panel and P2 only No PO B VME64 Front Panel unshielded with Front Panel J1 amp J2 P2 8 POI O T VME64 Front Panel unshielded with Front Panel J1 amp J2 and P2 I O No PO D VME64 Blank Front Panel Low profile extractors and P2 amp PO T O only PO connector is required for slots 3 and 6 module I O for Rear Panel I O PO is NOT required for slots 3 and 6 module I O if using J1 and J2 Front Panel I O ENVIRONMENTAL 70 E 40 85 H E WITH REMOVABLE COATING C WITH REMOVABLE COATING SPECIAL OPTION CODE OR LEAVE BLANK Note 1 functions and other frequency ranges see 64CS3 64SD3 and or contact factory 2 Unshielded front panel to accommodate 78 pin connector 64 C1 A001 Rev 6 3 do 7 14 5 Cage Code OVGU1 Page 73 of 74 North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 631 567 1100 631 567 1823 fax www naii com e mail sales naii com REVISION PAGE Revision Description of Change Engineer Date 1 0 Initial Release GS 11 12 02 1 1 Adds Modules K2 and K4 GS 11 14 02 1 2 Clarifies S R and LVDT RVDT bay population 1 Adds Range registers GS 11 15 02 1 3 Corrects TTL Memory Map and its Automated description GS 11 19 02 1 4 Appends RTD BIT desc and Memory Map and TTL Memory Map GS 11 22 2 1 5 Adds C3 E2 to Appendix
90. Each bit of 16 bit binary word corresponds to one of 16 channels REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 16 15 14 13 12 11 1019 8 7 6 5 4131211 D D DATA North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com 64 C1 001 6 3 do 7 14 5 C Cage Code OVGU1 Page 25 of 74 De bounce time Enter required de bounce time into appropriate channel registers Enter time in 1 28 5 increments up to 326 40 usec LSB 1 28 us Value is 8 bits MSBs don t care Once a signal level is a logic voltage level period longer than the De bounce time Logic High gt 2 0 v and Logic Low lt 0 6 v a logic transition is validated Signal pulse widths less than De bounce time are filtered or ignored Once valid the interrupt transition register channel flag is set and the output logic changes state Enter a value of 0 to disable De bounce filtering De bounce defaults to 00 upon reset REGISTER 15 014 013 012 011 010 D9 D8 D6 D5 D4 D3 D2 D1 DO FUNCTION 163 8481
91. H3 BHI CH3 A11 BHI CH3 D4 BLO CH3 A12 BLO CH3 05 IDXHI CH3 13 IDXHI CH3 E5 ipxLO cH3 14 IDXLO CH3 E1 AHI CH4 15 AHI CH4 E2 ALO CH4 A16 ALO CH4 BHI CH4 A17 BHI CH4 E4 BLO CH4 A18 BLO CH4 IDXHI CH4 12 IDXHI CH4 C4 IDXLO CH4 3z IDXLO CH4 NOTE For commutation A B C outputs A Hi becomes A B Hi becomes B and Index Hi becomes C When encoder outputs are required module slots 3 and 6 must remain unpopulated North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com 631 567 1100 631 567 1823 fax 7 14 5 Cage Code OVGU1 64_C1_A001_Rev_6 3 do 72 of 74 PART NUMBER DESIGNATION 64C1 XX XX XX XX XX XX 6 Slot 1 2 3 4 5 MODULE SLOT DEFINITION Enter Modules A through Y A D Module C1 A D Module C2 Module A D Module C4 Signal Module E1 D A Module F1 for each of Slots 1 through 6 ZO if slot not used A D 1 25 VDC to 10 0 VDC FS Uni or bipolar A D 40VDC Uni or bipolar Ten 10 4 20ma Current Measurement Module Ten 10 A D 50VDC Uni or bipolar Four 4 Programmable Function Generators Ten 10 D A Outputs 10 VDC VME ISOLATED Ten 10 Ten 10 D A Module 10 D A Outputs 5 VDC VME ISOLATED D A Module J3 10 D A Outputs 1 25 VDC VME ISOLATED D A Module 95
92. Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 22 of 74 AID Range amp Polarity Format input for range and polarity Range is dependent upon Module Encode range using data bits DO through D3 Program polarity using data bit D4 Enter per table Does not apply to Current Measurement Module is fixed unipolar 0 25mA FS REGISTER 015 D1 D1 1011 1010 D9 D amp D7 D6 D5 D4 D3 D2 D1 DO RANGE amp POLARITY X X X X X X X X X X D D D D D MODULE C4 C2 C1 Unipolar RANGE 0 50 0V 0 40 0V N A 0 1 0 1 0 0 250 0 20 0V 0 1 0 0 1 0 125V 0 10 0V 0 10 0V 0 0 0 0 0 0 6 25 0 5 00V 0 5 00V 0 0 0 0 1 0 3 125V 0 2 50V 0 2 50V 0 0 0 1 0 0 1 5625 0 1 25V 0 125 1 0 0 0 1 1 0 78125 0 0 625V 0 0 625V 0 0 1 0 0 Bipolar RANGE 50 0 V 40 0 V 40 0 V 25 0 V 20 0 V 20 0 V 12 5 V 10 0 V 10 0 V 6 25 V 5 00 V 5 00 V 3 125V 2 50 V 2 50 V 1 5625 V 1 25 V 1 25 V 0 78125 V 0 625V 0 625V a m Oj 9 o oj oj o AID Filter Break Frequency The break frequency is the 3 db point of a single pole low pass filter Enter desired frequency f
93. NC Not Used M6Ch02 35 4 M6Ch02 L NC M6Ch01 SigL M6Ch04 M6Ch04 NC Not Used M6Ch02L 16 5 NC M6Ch02 EXH M6Vcc1 4 NC NC Not Used M6Ch03 H 36 B5 M6ChO3 L NC M6Ch02 EX L M6Gnd1 4 NC NC Not Used M6Ch03 L 17 B1 M6Ch04 H M6Ch02 H M6Ch02 Sig 6 05 M6Ch05 M6Ch01 Not Used M6Ch04 H 37 B2 M6Ch04 L M6Ch02 L M6Ch02 Sig L 6 06 M6Ch06 GND Not Used M6Ch04 L 18 M6Ch05 NC M6Ch03 M6Ch07 M6Ch07 NC Not Used M6Ch05 H 38 B4 M6Ch05 L NC M6Ch03 EXL 6 M6Ch08 NC Not Used M6Ch05 L 19 C1 AGND NC NC M6Ch03 Sig M6Vcc5 8 NC M6Ch02 Not Used M6Ch06 H 39 2 NC NC M6Ch03 Sig L M6Gnd5 8 NC GND Not Used M6Ch06 L 20 N A Control Lo Control Lo Control Lo Control Lo 53 D1 M6ChO6 H M6Ch03 M6Ch04 EXH M6Ch09 M6Ch09 NC Not Used M6GND 73 D2 M6ChO6 L M6Ch03 L M6Ch04 EXL M6Ch10 M6Ch10 NC Not Used M6GND 54 D3 M6Ch07 H NC M6Ch04 Sig H M6Ch11 M6Ch11 M6Ch03 Not Used M6Ch07 74 D4 M6Ch07 L NC M6Ch04 Sig L M6Ch12 M6Ch12 GND Not Used M6Ch07 L 55 D5 M6Ch08 H NC M6Ch05 EXH M6Vcc9 12 NC NC Not Used M6Ch08 H 75 E5 M6ChO8 L NC M6Ch05 EX L M6Gnd9 12 NC Not Used M6Ch08 L 56 E1 M6ChO9 H M6Ch04 H M6Ch05 Sig M6Ch13 M6Ch13 M6Ch04 Not Used M6Ch09 H 76 E2 M6Ch09 L M6Ch04 L M6Ch05 Sig L M6Ch14 M6Ch14 GND Not Used M6Ch09 L 57 M6Ch10 H NC M6Ch06 EXH M6Ch15 M6Ch15 NC Not Used M6Ch10 H 77 E4 M6Ch10 L NC M6Ch06 EXL M6Ch16 M6Ch16 NC Not Used M6Ch10L 58 NC M6Ch
94. REVISION D D D DATA ASCII ASCII DSP Type binary word Range 1 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module DSP revision For example 0x000B is revision 12 REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE DSP D DATA 64 C1 001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 41 of 74 Module FPGA Type binary word Range 1 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module FPGA revision For example 0x000B is revision 12 REGISTER 015 014 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 DO FUNCTION MODULE FPGA D DATA BIT Module ID ASCII character in each upper and lower byte Range N A Read Write R Initialized Value 4A37h Read register to determine Module ID in ASCII For example find ASCII J in upper byte and ASCII 1 in lower byte for Module J7 together 4A37
95. Range 1 R W 3 or 4 Wire Mode 21 R W 0C4 Module DSP2 R OEA Stat INTR Enable Ch 1 6 R W Note 1 For 3 or 4 Wire Modes Consult Factory 2 As of July 2005 Resistance Type binary word Range N A Read Write R W Initialized Value N A Resistance measurement is a binary word and is dependant upon range For example if the 0 01 ohms per count range is selected 2710h x 0 01 10000 x 0 01 100 ohms The resistance temperature relationship varies among RTDs and is function of its composite material ex Platinum Copper Nickel lron Nickel etc An RTD s Alpha Temperature Coefficient and its nominal resistance at say 0 while operating within its applicable resistance range provide for a first order approximation For best accuracy use resistance temperature relationship provided by the RTD manufacture Select associated Range 0 655 or 1 2000 Read Resistance and scale accordingly 0 01 Q bit or 0 03 Q bit Calculate temperature using RTD manufacture provided resistance temperature relationship a quadratic equation REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 DO FUNCTION RESISTANCE D D D D D D D D D D D D D D D D D DATA BIT 64_C1_A001_Rev_6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 1415 c 110 Wilbur Place Bohemia
96. TA 10 ASCII character in each upper and lower byte Range N A Read Write R Initialized Value 4E37h Read register to determine Module ID in ASCII For example find ASCII J in upper byte and ASCII 7 in lower byte for Module J7 together 4E37h REGISTER 015 014 013 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE ID ASCII J ASCII 7 64_C1_A001_Rev_6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 38 of 74 Status Check the corresponding bit for a channel s Status 0 Normal 1 Non compliant D A conversion outside 0 2 FS accuracy spec Reading any status bit will cause that bit to be unlatched BIT Status is part of background testing and the status register may be checked or polled at any given time D15 D14 D13 D12 D11 D10 D8 D D5 D4 D3 D1 DO BIT Status X X x X X X Ch7 Ch6 Ch5 Ch4 Ch 3 Ch2 Ch 1 Over Current Status Check the corresponding bit of the Over Current Status registers for o
97. V minimum recommended Software selectable per bit Programmable per bit from O to 0 655 seconds LSB 20 microseconds Each channel is updated every 20 microseconds to 50 VDC 5 VDC to 50 VDC Output logic is defined by the provided Vcc voltage to that channel bank There are four channels per bank 0 5 A max Short circuit protected Total current per module not to exceed 2 A Channel will withstand a current of 0 75A for 80us and will then be turned off For relay applications use clamping diodes across the output stage Low side switched high side switched or push pull Programmable per bit 20 us Each channel is updated every 20 microseconds to 50 VDC at 0 073 typical 0 103 max For contact sensing add 1 24 x Iset Vcc x 16 38000 1 oz 28g 64 C1 A001 Rev 6 3 do 7 14 5 Cage Code OVGU1 Page 14 of 74 631 567 1100 631 567 1823 fax www naii com e mail sales naii com Module K2 Discrete Input Input Range Input Pulse Detection Input Impedance Switching Threshold Accuracy of Set Point ON OFF Differential Voltage Contact Sensing De bounce Update Rate Over Voltage Protection Discrete Output Output Range Output Current Output Load Output Format Write Delay Update Rate Over Voltage Protection Thermal protection Power Per 16 channel module Weight Signal Power Vcc Ground Isolation Vcc to VME Ground Module to VME Power Si
98. address bits for example 02h Write to address 57FF6B h the A15 8 base address bits for example 04h Write to address 57FF6F h the address modifier you wish to respond to shifted up 2 bits for example 28h 0A 2 Then Write to address 57FFFBh 10h to enable the card The card will now respond to the base address 010204 in the example and address modifier 0A in example programmed The base address and address modifier can be changed at any time 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 o 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 20 of 74 PRODUCT CONFIGURATION AND MEMORY This design provides multiple functions on a single VME card When ordering the customer selects an assortment of up to 6 modules to populate this 6 slot mother board The memory map follows the order of modules specified in the part number To address the register of any module use the Base address to the entire card add the Module Offset depending upon its slot 000 100 200 or 500 and then add the Register Offset of interest see module memory map The memory map of each selected module counts from or is superimposed over its respective module offset Thus Address Base Module Offset Register Offset For example if a Digital MO module were selected to populate module 1 and a Discrete module were selected to pop
99. alue as per formula Peak to Peak Voltage 10 Value 65535 Volts Peak for module E1 Peak to Peak Voltage 15 Value 65535 Volts Peak for module E2 where Volts Peak is half Peak to Peak Voltage REGISTER D15 D14 013012 011 010 09 08 07 06 05 04 D3 D2 D1 DO FUNCTION AMPLITUDE D D D D D D D D D D D D D D DATA BIT Wrap around DC Offset Type 16 bit signed integer Range 32767 to 32767 10 volts E1 15 volts E2 Read Write R Initialized Value N A Read Wrap around DC Offset for D2 BIT test value to verify DC offset of selected waveform in 0 30 millivolt resolution Decode value as per formula DC Offset Voltage 10 Value 32768 Volts DC for Module E1 DC Offset Voltage 15 Value 32768 Volts DC for Module E2 Out of range data will be changed to the maximum allowable value REGISTER D15 D14 013012 011 010 09 08 07 06 05 04 D3 D2 D1 DO FUNCTION AMPLITUDE D D D D D D D D D D D D D DATA BIT North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 631 567 1100 631 567 1823 fax www naii com e mail sales naii com 7 14 5 Cage Code OVGU1 64 C1 A001 Rev 6 3 do 34 of 7
100. and will then be turned off Directly drive inductive loads relays Reverse current protection diode is incorporated 0 12 ohms Low side switched high side switched or push pull Programmable per bit 20 us Each channel is updated every 20 microseconds 100 VDC max Provided Vcc to VME Ground 500 volts Module to VME Power 500 volts I O Signal 500 volts Digital I O is opto isolated from VME bus Two outputs can be connected in parallel only one output set on The output that is turned off will not pull down the signal of the active output Vcc to VME Ground 500 volts Module to VME Power 500 volts Signal 500 volts Digital I O is opto isolated from VME bus 5VDC at 100 mA For contact sensing add Vcc x Iset x4 per bank of 4 0 55 oz 25gms 4 Ground pins per module All Grounds are common but isolated from VME ground 64 C1 A001 Rev 6 3 do 7 14 5 Cage Code OVGU1 Page 16 of 74 631 567 1100 631 567 1823 fax www naii com e mail sales naii com R D Module R2 Same as Module S1 Input format Input voltage Reference Input Bandwidth Frequency Input R D Module R3 Same as Module S1 Input format Input voltage Reference Input Bandwidth Frequency Input R D Module R4 Same as Module S1 Input format Input voltage Reference Input Bandwidth Frequency Input S D Module S1 Resolution Accuracy VME Data transfer Tracking Rate Bandwidth Input format Input volta
101. ant safe 0 to 80 VDC for level sensing For contact sensing Vcc per channel bank must be between 3 VDC min and 80 VDC max There are 4 channels per bank Software selectable per bit Input is self contained and requires no Vcc However if Input is used as a current source to detect switch closures Vcc will be required A pulse of 5hs min width will be sensed and indicated by the appropriate Hi Lo or Lo Hi Transition Interrupt 105 with or without power applied to module Four levels are programmable from 0 to 80 VDC with 10 bit resolution 0 9896 FS On Off Short to V Short to ground The greater of 596 signal value or 0 25 volts 0 25 V minimum recommended Programmable per bit from 0 to 0 655 seconds LSB 20 microseconds Each channel is updated every 20 microseconds 100 VDC max Four Ground pins per module one for each group of 4 channels Grounds are common but are isolated from VME ground New protective circuits are incorporated that avoid damage should an Input Signal be applied when Vcc is missing 0 to 80 Output logic is defined by the user provided Vcc voltage to that channel bank There are four banks with four channels per bank Four Ground pins per module one for each group of 4 channels All Grounds are common but are isolated from VME ground 0 5 A max per channel Short circuit protected Total current per module not to exceed 2 A Channel will withstand a current of 0 75A for 20ms
102. ays and switches Each TTL channel has an internal 110KQ pull down resistor All inputs are continually scanned and the data is double buffered for immediate availability The D2 test initiates automatic background BIT User Interface 16 TTL Module Block Diagram IN OUT 1 OUT 1 TTL Buffer 1 IN 1 Protective State Circuits Machine 1 IN OUT 16 lt 1 OUT 16 TTL Buffer 16 IN 16 Wrap Around 16 MUX Test Channel testing which tests and validates channel processing data read or write logicj tests for circuit over current conditions and provides status for threshold signal transitioning Any failure triggers Interrupt if enabled with the results available in status registers The testing is totally transparent to the user requires no external programming and has no effect on the operation of this card It can be enabled or disabled via the bus MODULE MEMORY MAP Module Bus 000 Write Output Ch 1 16 R W 070 Debounce time Ch 11 R W 0 6 FPGA 11 R 002 Read Ch 1 16 R W 07A Debounce time Ch 12 R W 0C8 Module FPGA 21 R 00C Debounce time Ch 1 R W 084 Debounce time Ch 13 R W Module ID R 016 Debounce time Ch 2 R W 08E Debounce time 14 R W 000 Status Fault Ch 01 16 R 020 Debounce time Ch 3 R W 098 Debo
103. bility Output current Rise Fall time Write Delay Power Weight North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 Ten 10 A D 50VDC Uni or bipolar 16 bit A D converters One per channel Differential may be used as single ended by grounding one input Ten 10 bipolar or unipolar channels Programmable per channel as full scale inputs of 50 00 25 00 12 50 or 6 25 volts where range is FS or 0 to FS VDC The ability to set lower voltages for Full Scale Input assures the utilization of the full resolution This module will not sense open Inputs 100 Volts 500 kO min Differential 0 1 96 FS over temperature no missing codes to 16 bits 1 25 LSB s max over temperature 50 KHz per channel 20 KHz per channel 770 microseconds Time for data sample to propagate to data register Each channel incorporates a fixed second order anti aliasing filter and a post filter that has a digitally adjustable break point programmable from 10 Hz to 10 KHz in 10 Hz steps 70 dB min at 60 Hz Roll off to 50 dB min at 10 KHz Signal voltage plus Common mode equals 80 volts Bipolar output in two s complement 7FFF is max positive 8000 is max negative Unipolar output range from 0 to FFFF full scale Designed to meet the testing requirements of IEC 801 2 Level 2 4 transient with a peak current of 7 5A and a time constant of approximately 60 ns 12 VDC 25ma typical 50 ma max As of 4 5 05 no 12 V
104. c 631 567 1100 631 567 1823 fax 7 14 5 C 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 36 of 74 D A MODULE or J DA Module Block Di Ten 10 D A channels are provided per P module and includes extensive DA 1 Current Limit diagnostics Overloaded outputs will 88 detected with results displayed gt 8 status This module incorporates 2 1 State 5 Protective major diagnostic capabilities offer 3 Machine Circuits substantial improvements to system 5 i 9 reliability because is alerted to malfunctions within 5 seconds Two DA 10 I 10 different tests one off line D2 and one 10 on line be selected Wrap Around MUX 1 The D2 test initiates automatic AD MUX 10 background BIT testing where each channel is checked to atest accuracy of 0 2 FS and monitored for shorted output Any failure triggers an Interrupt if enabled with the results available in status registers The testing is totally transparent to the user requires no external programming has no effect on the operation of this card and can be enabled or disabled via the bus The D3 test uses an internal A D that measures all D A channels while they remain
105. condition or threshold such as a Short to Ground as it applies to input measurement as well as contact sensing applications REGISTER 015 1014013 012 011 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 FUNCTION 256 128 64 32 16 8 4 2 1 value in Volts LSB 100mV MIN LOW THRESHOLD X X X X X X X DID D D D DATA BIT De bounce time Enter required de bounce time into appropriate channel registers Enter time 20us increments to 0 655 seconds LSB 20 Value is 15 bits MSB don t care De bounce defaults to 0 upon reset For contact sensing De bounce time is much like a glitch filter Signal pulse widths less than the De bounce time are filtered or ignored Once a signal level is stable for a period longer than the De bounce time see Upper and Lower Threshold described above a logic transition is validated For voltage sensing the input signal level must exceed its associated threshold for a time greater then the De bounce time for the logic transition to be validated see Upper and Lower Threshold described above Once valid the interrupt transition register channel flag is set and the output logic changes state Enter a value of 0 to disable De bounce filtering CONTACT SENSE VOLTAGE SENSE Upper Threshold Input Signal Input Signal Debounce Time Debounce Time Output Output
106. configures for voltage sensing REGISTER 015 014 01301210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 3 2 1 6 0 8 0 4 0 2 0 1 value mA LSB 100pA CURRENT XXIX X D D D D DID D DATA BIT Input Output format Configure channels in groups of 8 Write integer O for input 1 2 or 3 for output While each channel may be programmed for either input or output individually Pull up down Current Configuration must be programmed in four channel banks REGISTER 015014013 1012011 01009 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION INPUT OUTPUT CH 01 08 Ch 08 Ch 07 Ch 06 Ch 05 Ch 04 Ch 03 Ch 02 Ch 01 Channel INPUT OUTPUT 09 16 Ch 16 Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 09 Channel INPUT OUTPUT Du Di Di Da Di Do Di Du Di Du DL Du Di Du Di D DATA BIT Integer Du DL 0 0 0 Input 1 0 1 Output Low side switched with without current pull up 2 1 0 Output High side switched with without current pull down 3 1 1 Output push pull 64_C1_A001_Rev_6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 711415 c 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 52 of 74 Pull up down Current Configuration Set bit 1 to configure Bank to Pull up or clear bit 0 to con
107. curacy of 2 FS Test cycle is completed within 45 seconds and results can be read from Status registers when changes from 1 to 0 The test can be stopped at any time This test requires no user programming and can be enabled or disabled via the bus CAUTION D A Outputs are active during this test Check connected loads for interaction D A Over Current short circuit monitoring is disabled during D3 testing MODULE MEMORY MAP Module Bus 4 High Voltage DA Module Block Diagram Current Limit DA 1 Circuit 1 1 State Protective Machine Circuits c 1 5 Current Limit DA4 4 a 4 Wrap Around MUX 4 Test AID MUX 4 000 Data 1 R W 010 Polarity 3 0C4 Module DSP R 002 Data2 R W 012 Polarity 4 R W 0C6 Module FGPA 11 R 004 Data 3 R W 014 Wrap around 1 R W 0C8 Module FPGA 21 R 006 Data 4 R W 016 Wrap around 2 R W OCE Module ID R 008 Range 1 amp 2 R W 018 Wrap around 3 R W 1000 Status Ch 1 4 R 00A Range 3 amp 4 R W 01A Wrap around 4 R W 1004 Over Current Status Ch 1 4 R 00 1 Module Design Version 0 8 Stat Interrupt Enable Ch 1 4 R W OOE 2 R W OC2 Module Design Revision R OEC Over Current Interrupt Enable Ch 1 4 R W Note 1 As
108. d fault is latched until read To Status Indication Discrete and TTL section Also added Vcc must be wired for proper operation to Discrete Vcc Value description 24 Combination D A module J4 Removed Power added to D2 Transceiver spec GS 2 5 3 2 5 Adds to Discrete threshold hysteresis and other input output configurations descriptions GS 3 12 3 Added high voltage Module J7 amp Module S1 Address switches A9 amp A10 are ignored Any address NOT SPECIFIED within 2048 byte block up to 7FFh is reserved specified in two locations Reference contact factory instead of contact factory service Added special consideration for S R amp L R modules in S section Appended TTL and Discrete De Bounce Register Definitions also is R W in Memory Map Edited Discrete IO Pictorals added Z input impedance Added user proved to Vcc references throughout document Appended A D Range and Polarity and A D DO Test Range descriptions 2 6 Added Voltage Sensing Circuit GS 4 1 3 2 7 Adds Phase register to Signal Generator modules module G1 is NOT isolated GS 4 10 3 Adds Synchro Module S2 2 8 Updates Current Measurement Module C3 as fixed unipolar 0 25ma FS 100 inp imped GS 5 7 3 Module K2 is signal isolated from the VME bus while both module K2 and K4 are power isolated from the VME bus Sorted Spec by Module ID Added Software Support section Added Function Block Diagrams K2 Zin is 40k Updates SD Module Group Memory
109. d and can be disabled on a per channel basis See Operational Instructions for further detail within this specification North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 64 C1 001 6 3 do 7 14 5 Cage Code OVGU1 631 567 1100 631 567 1823 fax www naii com e mail sales naii com 2 of 74 TABLE OF CONTENTS lg 07 WO OCC M M 1 DESCRIPTION p 2 TABLE OF CONTENTS 3 S l KOT A LO U A LO ra 8 GENERAL FOR THE CARRIER CARD MOTHER 8 A D MODULE C1 TEN 10 A D 1 25 VDC TO 10 0 VDC FS UNI OR 8 A D MODULE C2 TEN 10 A D 40VDC UNI OR BIPOLAR Ne 9 A D MODULE TEN 10 4 20MA CURRENT MEASUREMENT MODULE Ne 9 A D MODULE TEN 10 A D SOVDC UNI OR BIPOLAR Ne 10 I O MODULED 1 SIXTEEN 16 TTL PROGRAMMABLE FOR INPUT OR 10 7 70 OA 70 MODULE D2 ELEVEN 11 DIFFERENTIAL MULTI MODE TRANSCEIVERS Ne 11 EE uie 11 FE 11 SIGNAL MODULE E1 FOUR 4 PROGRAMMABLE FREQUENCY GENERATORS Ne
110. e 12 R W JOCE Module ID R 030 Lower Threshold Ch 05 R W 07 High Threshold Ch 13 R W JODO Status Fault Ch 01 16 R 032 Min Low Threshold Ch 05 R W 07E Upper Threshold Ch 13 R W 1004 Status Over Current Ch 01 16 R 034 De bounce time Ch 05 R W 080 Lower Threshold Ch 13 R W 1006 Status Max Hi Threshold Ch 01 16 R 036 Max High Threshold Ch 06 R W 082 Min Low Threshold Ch 13 R W 1008 Status Min Lo Threshold Ch 01 16 R 038 Upper Threshold 06 R W 084 De bounce time Ch 13 R W Status Mid Range Ch 01 16 R 03A Lower Threshold Ch 06 R W 086 High Threshold 14 R W 0DC Status Lo Hi Transition Ch 01 16 R 03C Min Low Threshold 06 R W 088 Upper Threshold 14 R W JODE Status Hi Lo Transition Ch 01 16 R De bounce time Ch 06 R W 8A Lower Threshold 14 R W JOE8 Interrupt Fault Enable 01 16 R W 040 Max High Threshold Ch 07 R W 08 Min Low Threshold 14 R W JOEC Interrupt Over Current Enable Ch 01 16 R W 042 Upper Threshold Ch 07 R W O8E De bounce time Ch 14 R W OEE Interrupt Max Hi Threshold EnableCh 01 16 R W 044 Lower Threshold 07 R W 090 High Threshold Ch 15 R W 0 Interrupt Min Lo Threshold EnableCh 01 16 R W 046 Min Low Threshold Ch 07 R W 092 Upper Threshold 15 R W 0 2 Interrupt Mid Range Fault Enable 01 16 R W 048 De bounce time Ch 07 R W 094 Lower Threshold Ch 15 R W 0 4 Interrupt Lo Hi Transition Enable 01 16 R W 04A Max High Thre
111. e 0 Check the corresponding bit for a channel s Built In Test BIT Status Channel Status Data bit Chn where n is 1 2 3 or 4 is fail high true and indicates that the channel is not operating spec compliant Passing BIT status indicates that channel Frequency Amplitude and DC Offset is as programmed Status is latched Reading any status bit will unlatch the entire register BIT Status is part of background testing and the status register may be checked or polled at any given time BIT is operating at all times and cannot be enabled or disabled using the General use Test Enable register REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION BIT STATUS X X Ch4 Ch3 Ch2 Ch1 CHANNEL STATUS BIT Status Interrupt Enable Type binary word Range 0 to 15 Read Write R W Initialized Value 0 Set the bit to enable interrupts for the corresponding channel When enabled a non compliant channel will trigger an interrupt Default is 0 to disable all channels REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION BIT STATUS INTRENA X X X EX X X X X jCh4 Ch3 Ch2 Ch1 INTERRUPT ENABLE 64 C1 A001 6 3 do North Atlantic Industries In
112. e in lower byte for Module Design Revision B is together 4220h REGISTER 015 014 013 012 011 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULEDESIGNREVISION D D D DATA ASCII ASCII Module DSP Type binary word Range 1 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module DSP revision For example 0x000B is revision 12 REGISTER 015 014 013 012 011 D10 09 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE DSP D DATA BIT Module FPGA binary word Range 1 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module FPGA revision For example 0x000B is revision 12 REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 DO FUNCTION MODULE FPGA D DATA 10 ASCII character in each upper and lower byte Range N A Read Write R Initialized Value 5331h Read register to determine Module ID in ASCII For example find ASCII S in upper byte and ASCII
113. ensing add 1 24 x Iset Vcc x 16 38000 1 oz 28g 4 Vcc input pins per module each powers an individual 4 channel bank Vcc 2 8 volts For 5V applications use module D1 K6 When configured for input Vcc Z Input signal voltage level 4 Ground inputs pins per module All Grounds inputs are common but isolated from VME ground 500 volts 500 volts 500 volts Digital I O is opto isolated from VME bus Sixteen 16 Discrete NON ISOLATED Programmable for Input or Output Except is NON ISOLATED where all grounds are tied to VME ground 64 C1 A001 Rev 6 3 do 7 14 5 Cage Code OVGU1 Page 15 of 74 631 567 1100 631 567 1823 fax www naii com e mail sales naii com Discrete Module K6 INPUT CHARACTERISTICS Input range Voltage Contact Sensing Input Pulse Detection Input Impedance Switching Threshold Accuracy of Set Point ON OFF Differential De bounce Update Rate Over Voltage Protection Ground Protective circuits OUTPUT CHARACTERISTICS Output Range Output Current Output Load Output impedance Output Format Write Delay Update Rate Over Voltage Protection Thermal protection Isolation Redundant applications Isolation Power Weight Ground North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 Sixteen 16 Discrete Programmable I O Channels ISOLATED 0 to 80 volt Isolated from VME ground Programmable for Input or Output Redund
114. er description for details MSB 180 minimum differential is 0 05 REGISTER 015 D14 D13 D12 D11 010 D9 08 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 180 90 45 22 5 11 2 5 62 2 81 1 401 703 352 176 088 044 022 011 0055 approximate value ANGLE A D D D DATA BIT Degrees Angle A Initiate Type binary word Range N A Read Write R W Initialized Value 0 Set the bit corresponding to each channel to be monitored for angle change alert Set bit to 1 for monitoring channels and clear bit to 0 for those not used REGISTER 015 014 013 012011 010 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION ANGLE INTIATE xX X X X X X Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 CHANNEL ENABLE Active Channels Type binary word Range N A Read Write R W Initialized Value N A Set the bit corresponding to each channel to be monitored during BIT testing in the Active Channel register Set bit to 1 for active channels and clear bit to O for those not used Omitting this step will produce false alarms because unused channels will set faults REGISTER D15 D14 D13 D12 D11 D10 D8 D7 D D5 D4 D3
115. ess space on 256 byte boundaries A16 mode Responds to address modifiers 2A 2D 2E and 29 Base address can be set anywhere in the 64 K byte address space on 256 byte boundaries Geographical Addressing Enable Geographical Addressing by removing jumper from JP2 Disable Geographical Addressing b adding jumper to JP2 See card layout pictorial below Address switches A8 A9 amp A10 are ignored Card requires 2048 byte boundaries For detail examples see 64 VME Board Addressing document on our website http www naii com MODULE 1 MODULE 2 MODULE 3 MODULE 4 MODULE 5 MODULE 6 Disable GEO 16 Select 24 This card will respond to address modifier 2Fh for A24 Address mode where the 5 Msb s of the A24 address are the 5 bits defined by the slot in VME back plane The Card can optionally be interrogated at 2Fh to determine resource requirements and available functionally Using the address modifier 2Fh the following need to be written to the card 2 the base address the card should to respond to 2 the address modifier A16 A24 A32 3 then enable the card For example If the card is in slot 10 the 5 Msb s are 01010 so the address of the CSR registers 0101 0 111 1111 1111 57FFxx h xx is CSR register offset Write to address 57FF63 h the A31 A24 base address bits for example 01h Write to address 57FF67 h the A23 A16 base
116. f July 2005 Frequency Type 32 bit unsigned integer Range 0 130 000 from 1 to 9 Hz amplitude is functional but not to accuracy specification Read Write R W Initialized Value 1000 Frequency High and Frequency Low registers combined to determine desired frequency in 1 Hz resolution LSB is 1 Hz Frequency is updated on write to Low register Out of range data will be changed to the maximum allowable value When phase locked phase is reset when channel 1frequency is changed If phase is NOT locked phase remains unchanged when frequency is changed FREQUENCY HIGH REGISTER FREQUENCY LOW REGISTER 0150140130121011100908 07 06 05 0403102 D1 DO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO XXXIX X D D D D D 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 32 of 74 16 bit signed integer 180 degrees Read Write RAV Initialized Value 0 Enter the desired phase offset relative to channel 1 LSB is approximately 0 0889 When phase locked phase is reset when channel 1frequency is changed If phase is NOT locked phase remains unchanged when frequency is changed Enter as per formula Phase Register Value 32768 x 180 Degrees
117. fax 7 14 5 C 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 67 of 74 FRONT AND REAR PANEL CONNECTORS Front Panel Connectors J1 J2 748483 5 Mate 748368 1 Rear P2 and PO In row Z of P2 all even numbered pins are connected to analog ground DO NOT CONNECT TO ANY UNDESIGNATED NC PINS REFERENCE OUTPUT Front Panel for Synchro Resolver Measurement Rhi Out J2 pin 33 Out J2 pin 72 Rear Panel for Synchro Resolver Measurement Rhi Out P2 pin 25z Out P2 pin 27z 59 20 78 39 60 21 40 1 59 20 78 39 60 21 40 1 J1 J2 Front Panel Connector See pinout following North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 64 C1 A001 Rev 6 3 do 68 of 74 SLOT 1 2 AD DA J7 Discrete TTL Signal S D Differential 1 25al M1Cho1H M1Cho1 H M1Ch01 EX H M1Ch01 M1Ch01 NC M1Cho1 51 M1Ch01H 21 26 M1ChO1L M1Cho1L M1ChoT EXL 1 02 M1Ch02 NC M1Ch01S3 M1ChO1L 2 27 1 02 NC 1 01 Sig H M1Ch03 M1Ch03 NC M1Ch01S2 M1Ch02H 22 28a M1ChO2L M1Ch01SigL M1Cho4 M1Ch04 NC M1Ch01S4 1
118. figure Bank to Pull down Each data bit configures entire bank of 4 channels Defaults to 1 pull up configuration Register data bits D4 through 015 are don t XXXX XXXX D3D2D1Do REGISTER 015 014 01301210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION VCC VALUE 1 Pull Up 0 Pull Down DO configures bank 1 channels 1 4 of that module D Configure Ch 01 04 D1 configures bank 2 channels 5 8 of that module D Configure Ch 05 08 D2 configures bank 3 channels 9 12 of that module D Configure Ch 09 12 D3 configures bank 4 channels 13 16 of that module D Configure Ch 13 16 Examples Register value is integer Register Data Bits Channel Configuration Module 1 Value D15 D2 D1 DO Ch 9 16 Ch 5 8 Ch 1 4 0 0000 0000 0000 00 0 0 Pull Down Pull Down Pull Down 1 0000 0000 0000 00 0 1 Pull Down Pull Down Pull Up 2 0000 0000 0000 00 1 0 Pull Down Pull Up Pull Down 3 0000 0000 0000 00 1 1 Pull Down Pull Up Pull Up Vcc Value Read Vcc voltage at input pin per four channel bank Value is binary 10 bit word where LSB 100 mv Whether configured for input or output user provided Vcc must be wired for proper operation REGISTER D15 D14 D13 D12 D11 D1
119. ge Input Impedance Reference Input Reference Zin Frequency Input Angle change alert Phase shift Velocity Digital Wrap around Self Test Power Weight Reference Supply Voltage Accuracy Frequency Regulation Output power North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 Four 4 400Hz Resolver Measurement Except Resolver Resolver 11 8VL L Transformer isolated 11 8 Vrms Transformer isolated 40Hz 400Hz Four 4 400Hz Resolver Measurement Except Resolver Resolver 2 28VL L Transformer isolated 2 28 Vrms Transformer isolated 40Hz 400Hz Four 4 1200Hz Resolver Measurement Except Resolver Resolver 11 8 Transformer isolated 26 Vrms Transformer isolated 100Hz 1200Hz Four 4 400Hz Synchro Measurement 16 bits up to 24 bits for two speed configuration 1 arc minute for single speed inputs 1 arc minute divided by the gear ratio for two speed inputs Data transfers within 200 ns 150 RPS Referred to the Fine input for two speed configuration 40 Hz Synchro Synchro 90VL L Transformer isolated 60 min at 26VL1 260 min at 9OVL L 115 Vrms Transformer isolated 100 min 400Hz 40Hz Each channel can be set to a different angle differential When that differential is exceeded an interrupt if enabled is triggered Default Ch Disabled MSB 180 Min differential is 0 05 Max differential that can be programmed
120. gnal Module K4 Same as Module K2 North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 Sixteen 16 Discrete ISOLATED Programmable for Input or Output K6 module is recommended for new designs 0 40 VDC Note User provided Vcc must be greater than or equal to any input signal or current limited to 10ma A signal pulse width 40us or greater will be sense and indicated by the appropriate Lo or Lo Hi Transition Interrupt 40 Four levels are programmable from 0 to 40 VDC with 10 bit resolution 0 9896 FS On Off Short to V Short to ground The greater of 596 signal value or 0 25 volts 0 25 V minimum recommended Software selectable per bit Programmable per bit from 0 to 0 655 seconds LSB 20 microseconds Each channel is updated every 20 microseconds to 40 VDC 0 VDC to 40 VDC output logic as defined by user provided Vcc input voltage 2 8 volts to that channel bank There are four channels per bank For 5V applications use module D1 0 5 A max Short circuit protected Total current per module not to exceed 2 A Channel will withstand a current of 0 75A for 80us and will then be turned off Directly drive inductive loads relays Reverse current protection diode is incorporated Low side switched high side switched or push pull Programmable per bit 20 us Each channel is updated every 20 microseconds to 40 VDC is provided 5VDC at 0 073 A typical 0 103 A max For contact s
121. h REGISTER 015 014 013 0121011 010 09 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE ID D DATA ASCII J ASCII 7 BIT Status Check the corresponding bit for a channel s BIT Status A 0 Normal 1 Non compliant D A conversion outside 2 FS accuracy spec Reading any status bit will cause that bit to be unlatched BIT Status is part of background testing and the status register may be checked or polled at any given time 015 D14 D13 D12 D11 D10 DB D7 06 D5 D4 D3 D2 DO BIT Status X X X X X X X X X X X ch 4 Ch 3 Ch 2 Ch 1 Over Current Status Check the corresponding bit of the Over Current Status registers for over current draw for each active channel A 0 zNormal 1 Over Current An over current draw from the output of any D A channel is detected within 2 seconds and will latch the corresponding bit in the Over Current Status register Reading any status bit will cause unlatch the entire register Over Current Status is part of background testing and the status register may be checked or polled at any given time 015 014 D13 D12 D11 D10 DB D7 De D5 D4 D3 D2 D1 DO Over Current Status X X X X X X X X X X X X Ch 4 Ch 3
122. has reached the specified difference The use of Type II servo loop processing techniques enables tracking at full accuracy up to the specified rate A step input will not cause any hang up condition Intermediate transparent latches on all angle and velocity outputs assure that valid data is always available Our synthetic reference compensates for 60 phase shifts thus eliminating the need for individual compensation networks The D2 Test initiates automatic background BIT testing Each channel is checked every 5 to a testing accuracy of 0 05 and each Signal and Reference is always monitored Any failure triggers an Interrupt if enabled and the results are available in Status Registers The testing is totally transparent to the user requires no external programming has no effect on the standard operation of the card and can be enabled or disabled via the bus The 03 Test initiates a test that disconnects all channels from the outside world and connects them across an internal stimulus that generates and tests 72 different angles to a test accuracy of 0 05 Results can be read from registers and external reference is not required Any failure triggers an Interrupt if enabled The testing requires no external programming and can be initiated or stopped via the bus The DO Test is used to check the card and the VME interface All channels are disconnected from the outside world allowing the user to write any number of input a
123. ic High 1 when its value exceeds the Upper threshold and does not consequently fall below the Lower threshold in less than the programmed De bounce time REGISTER 015 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 256 128 64 32 16 8 4 2 1 value in Volts LSB 100mV UPPER THRESHOLD D JD D D D D D D DATA BIT Lower Threshold Lower Threshold is programmable per channel from 0 VDC to 40 VDC Binary 10 bit word LSB 100 mv A signal is considered logic Low 0 when its value falls below the Lower threshold and does not consequently rise above the Upper Threshold in less than the programmed De bounce time REGISTER 015 0141013 1012011 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 FUNCTION 25 6112 8 6 4 3 2 1 61 8 4 2 1 value in Volts LSB 100mV LOWER THRESHOLD X X X XIX X X D D D D D D D D D D DATA BIT Min Low Threshold Minimum Low Threshold is programmable per channel 0 VDC to 40 VDC Binary 10 bit word LSB 100 mv Assumes that the programmed level is the maximum voltage used to indicate a Min Low Threshold If a signal is less then the Min Low Threshold value a flag is set in the Min Low Threshold Status register The Min Low Threshold register may be used to monitor any type of low signal voltage
124. ign Version 1 is together 3120h REGISTER 015 014 013 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE DESIGN REVISION D D ID 00 0 0 ASCII 1 ASCII Module Design Revision Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design revision code in ASCII For example ASCII B in upper byte and ASCII space in lower byte for Module Design Revision B is together 4220h REGISTER 015 014 013 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE DESIGN REVISION D 00 0 D DATA BIT ASCII ASCII 64 C1 A001 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 29 of 74 Module DSP Type binary word Range 0 to 65535 Read Write R Initialized Value N A Read register as 16 bt binary word to determine Module DSP revision For example 0x000B is revision 12 REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION
125. impedance Update rate ESD protection Power Weight D A Module F3 Output range Resolution Accuracy Offset Non linearity Gain error Output format Settling time Load Output impedance Update rate ESD protection Power Weight North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com 10 D A Outputs 10 VDC VME ISOLATED 10 VDC or 0 to 10 VDC programmable For other ranges contact customer service Output is set to 0 at reset or Power on 16 bits channel for either output range 0 05 FS lt 1 mV over temperature 0 01 FS over temperature 0 02 over temperature Optically isolated in groups of ten 250 V to VME power 10 max 20 ma channel max Source or Sink Can drive a capacitive load of 0 1 mfd Short circuit protected When current exceeds 20 ma for any channel for 50ms that channel is set to zero and a flag is set Card is programmable to allow all channels to be reset by either an automatic retry or by a control port command 10 20 microseconds per channel Designed to meet the testing requirements of IEC 801 2 Level 2 4KV transient with a peak current of 7 5A and a time constant of approximately 60 ns 12 VDC at 145 ma typical 192 ma max 5 VDC at 91 ma typical 150 ma max 1 oz 28g Ten 10 D A Outputs 5 VDC VME ISOLATED 5 VDC or 0 to 5 VDC programmable For other ranges contact customer service Out
126. ion Generator 10 130 KHz 0 15Vpp 5 3 Vrms TTL 5V System Logic Supply Programmable for Input or Output Differential Multi Mode Transceivers Discrete 0 40 VDC Programmable for Input or Output Isolated or Non Isolated Discrete 0 80 VDC Programmable for Input or Output LVDT to Digital 2 3 or 4 wire LVDT and one optional excitation per card Resolver to Digital and one optional reference per card 3 or 4 wire Platinum Resistance Temperature Device Measurement RVDT to Digital and one optional excitation per card Function Module Channels Details AID C1 C2 C4 C3 10 D A 3 45 F1 10 J7 4 Signal Generator E1 4 Digital D1 16 D2 11 Discrete I O K2 K4 16 K6 16 LVDT D L 4 R D R2 R3 R4 4 RTD G1 6 RVDT D 4 50 1 52 4 Synchro to Digital and one optional reference per card Note 1 For these functions and other frequency ranges see 64CS3 64SD3 and or contact factory Automatic background BIT testing an important feature is always enabled and continually checks the health of each channel There is no need to guess or make assumptions about system performance A fault is immediately reported and the specific channel is identified This capability is of tremendous benefit because it identifies and reports a failure without the need to shut down the equipment for troubleshooting Testing is totally transparent to the user requires no external programming has no effect on the standard operation of the car
127. is maintained until the input signal falls below Upper Threshold Lower Threshold Input Signal the Lower Threshold n Conversely the same is Logic High 1 true as the signal changes from low to high or high to low Logic State Logic Low 0 Max High Threshold Maximum High Threshold is programmable per channel from 0 VDC to 40 VDC Binary 10 bit word LSB 100 mv Assumes that the programmed level is the minimum voltage used to indicate a Max HighThreshold If a signal is greater then the Max High Threshold value flag is set in the Max High Threshold Status register The Max High Threshold register may be used to monitor any type of high signal voltage condition or threshold such as a Short to V as it applies to input measurement as well as contact sensing applications REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 DO FUNCTION 256 128 64 32 16 8 4 2 1 value in Volts LSB 100mV MAX HIGH THRESHOLD X X X X X D D D D D D DATA BIT 64 C1 001 6 3 0 North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 711415 c 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 48 of 74 Upper Threshold Upper Threshold is programmable per channel from 0 VDC to 40 VDC Binary 10 bit word LSB 100 mv A signal is considered log
128. ister D15 D14 D13 D12 011 D10 DB D7 06 D5 D4 D3 01 DO 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 54 of 74 Status Fault 16 Ch 15 14 Ch 13 Ch 12 Ch 11 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Over Current 16 15 14 Ch 13 Ch 12 Ch 11 10 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Max Hi Threshold 16 Ch 15 14 Ch 13 Ch 12 Ch 11 10 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Min Lo Threshold 16 15 14 Ch 13 Ch 12 Ch 11 10 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Mid Range 16 15 14 Ch 13 Ch 12 Ch 11 10 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Lo Hi Transition 16 15 14 Ch 13 12 Ch 11 10 Ch 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Status Hi Lo Transition 16 15 14 Ch 13 12 11 10 9 Ch 8 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Interrupt Fault Enable 16 Ch 15 14 Ch 13 Ch 12 11 Ch 10
129. ister When it detects that a code has been received that code will be inverted within 100 uSec The inverted code stays in the register until replaced by a new code After 100 Sec elapse look for the inverted code to confirm that the processor is operating Soft reset Soft Reset is Level sensitive Writing a 1 initiates and holds software in reset state then writing 0 initiates reboot depending upon configuration takes up to 3 seconds This function is equivalent to a power on reset where all parameters are reset to their default condition 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 64 of 74 Enable Set to enable associated Built In Self Test D3 D2 or DO Each test affects each Module Type differently See the individual module section for test description s Write 1 to D2 to initiate automatic background BIT testing Card will every 30 seconds write 55h at Test D2 verification register when D2 is enabled User can periodically clear to 00h and then read Test D2 verification register again after 30 seconds to verify that background bit testing is activated D3 test cycle is completed within 45 seconds and results can be read from the associated status registers when changes from 1 to 0 Any failure triggers an Interrupt if enabled All testi
130. lantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 o 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 74 of 74 at all times and cannot be enabled or disabled using the General User Test Enable register 3 5 AD module Range and Polarity descriptions details all polarity ranges GS 21414 3 6 Corrects E2 Range in Spec is 0 130 2 Adds Reference output pins GS 2 27 04 3 7 Module K2 Vcc gt 8 Volts Output is 8 to 40Vdc GS 3 3 4 3 8 Adds reference Rhi OUT for AND rear panel connectors Signal module E1 GS 3 17 4 Power 5 VDC at 0 6A per module Changed nomenclature from D A to Polarity register FOR COMMERCIAL AND GS 4 6 4 3 9 MILITARY APPLICATIONS SD module power is 5 VDC 11mW at 26VL L 31mW 90VL L 4 0 Adds Interrupt Enable Register Adds S1 R1 Encoder Resolution Description GS 6 16 4 4 1 Conducted cooled versions available GS 71714 4 2 Updates J7 ID register contents GS 8 9 4 4 3 Appends A D spec where range is FS or 0 to FS VDC GS 8 12 4 4 4 Adds Commutation Programming to S module GS 8 18 4 4 5 Module D1 0x0A4 Input Output Format is for Ch 01 8 not 1 16 GS 8 25 4 4 6 Adds TOC GS 10 18 4 D1 Power requirement is 40mA on 5V supply D1 is TTL 5V System Logic Supply GS 11 2 4 47 J5 is 2 5 VDC Adds F3 5 VDC D A module E1
131. le Design Version 1 is together 3120h REGISTER 015 014 013 012 011 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE DESIGN VERSION D D D D 1D D ID ID ID ID D ID ID D D D D DATA BIT ASCII 1 ASCII Module Design Revision Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design revision code in ASCII For example ASCII B in upper byte and ASCII space in lower byte for Module Design Revision B is together 4220h REGISTER 015 014 D13 D12 D11 D10 09 08 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULEDESIGNREVISION D D D DATA ASCII ASCII DSP binary Range 0 to 65535 64 C1 001 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 711415 c 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 26 of 74 Read Write Initialized Value Read register as 16 bt binary word to determine Module DSP revision For example 0x000B is revision 12 REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION
132. ll not sense open Inputs Not to exceed 3 volts 100 O min 0 1 96 FS over temperature no missing codes to 16 bits 8 LSB s max over temperature 50 KHz per channel 20 KHz per channel 770 microseconds Time for data sample to propagate to data register Each channel incorporates a fixed second order anti aliasing filter and a post filter that has a digitally adjustable break point programmable from 10 Hz to 10 KHz in 10 Hz steps 70 dB min at 60 Hz Roll off to 50 dB min at 10 KHz Signal voltage plus Common mode equals 80 volts Unipolar output range from 0 to FFFF full scale Designed to meet the testing requirements of IEC 801 2 Level 2 4 transient with a peak current of 7 5A and a time constant of approximately 60 ns 12 VDC 25ma typical 50 ma max As of 4 5 05 no 12 VDC requirement 5 VDC at 320 ma typical 500 ma max As of 4 5 05 500ma typical 750ma max 1 oz 28g 64 C1 A001 Rev 6 3 do 7 14 5 Cage Code OVGU1 Page 9 of 74 631 567 1100 631 567 1823 fax www naii com e mail sales naii com A D Module C4 Resolution Input format Input scaling Over voltage protected Input Impedance Accuracy Linearity error Sampling rate Bandwidth Group delay Programmable filter Common mode rejection Common mode voltage Output Logic ESD protection Power Weight Module D1 TTL Input Input levels Read Delay De bounce TTL Output Output levels Drive Capa
133. n upper byte and ASCII 1 in lower byte for Module G1 together 4731h REGISTER D15 D14 D13 D12 D11 D10 D9 D7 D6 05 D4 D3 D2 D1 DO FUNCTION MODULE ID D D D D DATA BIT ASCII G ASCII 1 BIT Status Check the corresponding bit for a channel s BIT Status A 0 Normal 1 Non compliant A D conversion outside 0 2 FS accuracy spec Reading any status bit will unlatch the entire register BIT Status is part of background testing and the status register may be checked or polled at any given time 015 D14 D13 D12 D11 D10 D9 D8 D7 D6 05 D4 D3 D2 D1 DO BIT Status X X X X X X Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Open Status Check the corresponding bit of the Open Status registers for open disconnected RTD for each active channel A 0 zNormal 1 Open detected after 2 seconds Reading any status bit will cause that bit to be unlatched Open Status is part of background testing and the status register may be checked or polled at any given time D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Open Status X X X X X X 10 Ch 9 Ch 8 Ch 7 Ch
134. nal Status Type binary word Range N A Read Write R Initialized Value 0 Check the corresponding bit for a channel s Signal Status Status data bit is fail high true and indicates each a Signal input loss to that channel Signal Loss is indicated after 2 seconds Signal input monitoring is disabled during D3 or DO Test Any Signal Status failure transient or intermittent will latch the Signal Status register Reading any status bit will unlatch the entire register Signal Status is part of background testing and the status register may be checked or polled at any given time When Status Interrupt is enabled Status Interrupt is reported through the Open Status Interrupt Vector in the General Use Memory Map REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION SIGNAL STATUS X Ch8 Ch7 Ch6 4 2 1 CHANNEL STATUS Reference Status Type binary word Range N A Read Write Initialized Value 0 Check the corresponding bit for a channel s Reference Status Status data bit is fail high true and indicates each a Reference input loss to that channel Signal and or Reference Loss is indicated after 2 seconds Signal and Reference input monitoring is disabled during D3 or DO Test Any Reference Status failure transient or intermittent will latch the Reference Status register
135. nd1 4 NC NC Not Used M3Ch03 L 17 11z M3Ch04 H M3Ch02 H M3Ch02 Sig M3Ch05 M3Ch05 M3Ch01 Not Used M3Ch04 H 37 13z M3Ch04 L M3Ch02 L M3Ch02 Sig L M3Ch06 M3Ch06 GND Not Used M3Ch04 L 18 1521 M3Ch05 NC M3Ch03 EX M3Ch07 M3Ch07 NC Not Used M3Ch05 H 38 1721 M3Ch05 L NC M3Ch03 EXL M3Ch08 M3Ch08 NC Not Used M3Ch05 L 19 21z AGND NC NC M3Ch03 Sig M3Vcc5 8 NC M3Ch02 Not Used M3Ch06 H 39 23z NC NC M3Ch03 Sig L M3Gnd5 8 NC GND Not Used M3Ch06 L 20 Control Control 10 Control Control 53 A8 M3Ch06 H M3Ch03 H M3Ch04 EXH M3Ch09 M3Ch09 NC Not Used M3GND 73 A9 M3Ch06 L M3Ch03 L M3Ch04 EXL M3Ch10 M3Ch10 NC Not Used M3GND 54 A10 M3Ch07 H NC M3Ch04 Sig H M3Ch11 M3Ch11 M3Ch03 Not Used M3Ch07 H 74 A11 M3Ch07 L NC M3Ch04 Sig L M3Ch12 M3Ch12 GND Not Used M3Ch07 L 55 A12 M3Ch08 H NC M3Ch05 EXH M3Vcc9 12 NC NC Not Used M3Ch08 75 A17 M3Ch08 L NC M3Ch05 EX L M3Gnd9 12 NC NC Not Used M3Ch08 L 56 A13 M3Ch09 M3Ch04 H M3Ch05 Sig M3Ch13 M3Ch13 M3Ch04 Not Used M3Ch09 H 76 A14 M3Ch09 L M3Ch04 L M3Ch05 Sig L M3Ch14 M3Ch14 GND Not Used M3Ch09 L 57 A15 M3Ch10 H NC M3Ch06 EXH M3Ch15 M3Ch15 NC Not Used M3Ch10 77 A16 M3Ch10L NC M3Ch06 EXL M3Ch16 M3Ch16 NC Not Used M3Ch10 L 58 A18 NC NC M3Ch06 Sig M3Vcc13 16 NC NC Not Used M3Ch11 H 78 A19 NC NC M3Ch06 SigL M3Gnd13 16 NC NC Not Used M3Ch11L 59 N A Control Hi Control Hi Control Hi Control Hi NOTE 1 Contact Factory SLOT 4 J2 P2 AD DA D
136. nel of that pair The pairs are defined as Ch 1 amp 2 and Ch 3 amp 4 NOTE Per bit angle values in below table are approximate DATA HIGH REGISTER DATA LOW REGISTER 015 014 013012011010109108107 D6 D5 DA D3 D2 D1 DO D15 D14 D13 D12 D11 010 D9 D8 0706050403020100 180 90 45 22 5111 215 62 2 81 1 40 703 352 176 088 044 022 011 0055 00274 00137 00068 00034 00017 00008 00004 00002 X X X X X X D D D D D D D D D x Xx X X X X X IX X XIXIXIX XX D D D D D D D D D D D X X XIXIXIX XX Velocity Type 16 bit 2 s complement word Range Ox7FFF maximum CW rotation to 0x8000 maximum CCW Read Write R Initialized Value N A 64_C1_A001_Rev_6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 57 of 74 Read Velocity Registers of each channel as 25 complement word with 7FFFh being maximum CW rotation and 8000h being maximum CCW rotation When max velocity is set to 152 5878 RPS an actual speed of 10 RPS CW would be read as 0863h When max velocity is set to 152 5878 RPS an actual speed of 10 RPS CCW would be read as F79Ch When max velocity is set to 50 8626 RPS an actual s
137. ng requires no external programming and is initiated by writing 1 or terminated by writing 0 015 D14 D13 012 D11 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Test Enable X X X X X X X X X X X X D3 D2 X DO Test D2 Verify Card will every 30 seconds write 55h at Test D2 Verification register when D2 is enabled User can periodically clear to 00h and then read again after 30 seconds to verify that background bit testing is activated Latch A Ds Latch all A D channels by writing 1 to D1 of Latch register Write 0 to unlatch all channels AID 00 Test Range Specify voltage range for A D module under test DO test is performed only on A D modules Enter per table NOTE for Current Measurement Module C3 enter up to 2 5V for 25mA FS unipolar selection only REGISTER 015 D1 D1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO A D DO TEST RANGE X X X X X X X X X X X D D D D D MODULE 4 C1 amp C2 RANGE 50 0 V 40 0V 1 0 1 0 25 0 V 20 0V 1 0 0 1 12 5 V 100 0 0 0 0 6 25 V 5 00 0 0 0 1 3 125 2 50 0 0 1 0 1 5625 1 25 0 0 1 1 0 78125 0 625 0 1 0 0 For bipolar unipolar selection program D4 as 0 for unipolar and 1 for bipolar A D DO Test Voltage
138. ngles to the card and then to read the data from the interface External reference is not required NOTE Special consideration must be exercised when Synchro Resolver S R or LVDT RVDT L R measurement functions are required In either case if S R or L R measurement is required slots 4 5 and 6 must be dedicated to that particular function S R or L R measurement cannot be mixed together or mixed with any other module type For 4 channel requirements slot 4 will be populated For 8 channel requirements slot 4 and 5 will be populated The remaining third slot must remain unused The other three slots 1 2 and 3 can be used for a mix of A D D A I O or other but never S R or L R function 64 C1 A001 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 C 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 56 of 74 S D FIXED SLOTS 4 5 AND 6 MEMORY 300 Ch 1 Data Hi R 33C Two Speed Lock Loss R 380 Ch 2 Data Lo R 302 Ch 2 Data Hi R Synchro Resolver R W 382 Ch 4 Data Lo R 304 Ch 3 Data Hi 340 Active Channels R W 384 Ch 6 Data Lo R 306 Ch 4 Data Hi R 346 Latch W 386 Ch 8 Data Lo R 308 Ch 5 Data Hi R 348 Ch 1 Velocity Scale R W 3C0 Module Design Version R 30A Ch 6 Data Hi R 34A Ch 2 Velocity Scale R W 3C2
139. nnel will trigger an interrupt Default is 00h to disable all channels D15 D14 D13 D12 D11 D10 D9 D8 D7 06 D5 D4 D3 D2 D1 00 BIT Status Interrupt Enable X x x x x X Ch 10 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Open Status Interrupt Enable Set the bit to enable interrupts for the corresponding channel monitored for Open Status Open Status does NOT apply to high voltage 20V to 80V or current measurement modules 015 014 D13 D12 D11 D10 DB D7 06 D5 D4 D3 D1 DO Status Interrupt Enable X X X X X X ch 10 ch 9 ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 24 of 74 I O DIGITAL TTL MODULE 01 Digital TTL I O channels in banks of 16 are programmable for either Input or Output and include extensive diagnostics Interrupt can be selected for each channel to indicate transition on rising edge transition on falling edge or both De bounce circuits for each channel offer a selectable time delay to eliminate false signals resulting from contact bounce commonly experienced with mechanical rel
140. one input Ten 10 bipolar or unipolar channels Programmable per channel as full scale inputs of 40 00 20 00 10 00 5 00 volts where range is FS or 0 to FS VDC The ability to set lower voltages for Full Scale Input assures the utilization of the full resolution This module will not sense open Inputs 100 Volts 500 kO min Differential 0 1 96 FS over temperature no missing codes to 16 bits 1 25 LSB s max over temperature 50 KHz per channel 20 KHz per channel 770 microseconds Time for data sample to propagate to data register Each channel incorporates a fixed second order anti aliasing filter and a post filter that has a digitally adjustable break point programmable from 10 Hz to 10 KHz in 10 Hz steps 70 dB min at 60 Hz Roll off to 50 dB min at 10 KHz Bipolar output in two s complement 7FFF is max positive 8000 is max negative Unipolar output range from 0 to FFFF full scale Designed to meet the testing requirements of IEC 801 2 Level 2 4 transient with a peak current of 7 5A and a time constant of approximately 60 ns 12 VDC 25ma typical 50 ma max As of 4 5 05 no 12 VDC requirement 5 VDC at 320 ma typical 500 ma max As of 4 5 05 500ma typical 750ma max 1 oz 28g Ten 10 4 20ma Current Measurement Module 16 bit A D converters One per channel Differential may be used as single ended by grounding one input 0 25ma Ten 10 unipolar channels 0 25ma full scale This module wi
141. or each channel between 10 Hz to 10 kHzas a 16 bit binary number Zero disables filter Module Design Version Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design version in ASCII For example ASCII 1 in upper byte and ASCII space in lower byte for Module Design Version 1 is together 3120h REGISTER 015 014 013 012011 010 0 9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE DESIGN VERSION D D 1 D D ID ID ID ID D ID ID D D D DATA BIT ASCII 1 ASCII Module Design Revision Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design revision code in ASCII For example ASCII B in upper byte and ASCII space in lower byte for Module Design Revision B is together 4220h REGISTER 015 014 D13 D12 D11 D10 09 D8 D7 D6 D5 D4 D3 D2 01 DO FUNCTION MODULE DESIGN REVISIONI D D DATA ASCII ASCII Module DSP Type binary word Range 1 to 65535 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY
142. orth Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Six 6 four wire Platinum RTD 16 bits Interfaces with 1000 and 5000 RTDs RTD whose operating resistance is up to 20000 under the required operating conditions This module will sense unconnected Inputs Only one open wire out of four will set flag 1 milliamp channel 0 80 for 2kO range over temperature and with 3 75 Hz bandwidth 0 270 for 6550 range over temperature and with 3 75 Hz bandwidth Each input has a separate return but all are common and connected to VME ground Each channel is updated seven times per second Resistance Designed to meet the testing requirements of IEC 801 2 Level 2 4 transient with a peak current of 7 5A and a time constant of approximately 60 ns 12 VDC at 25 ma typical 50 ma max 5 VDC at 320 ma typical 500 ma max 1 oz Ten 10 D A Outputs 1 25 VDC VME ISOLATED 1 25 VDC or 0 to 1 25 VDC programmable For other ranges contact factory Output is set to 0 at reset or Power on 16 bits channel for either output range 0 05 FS lt 1 mV over temperature Optically isolated in groups of ten 250 V to VME power 350 max 20 ma channel max Source or Sink Can drive a capacitive load of 0 1 mfd 5 KQ min Short circuit protected When current exceeds 20 ma for any channel for gt 50ms that channel is set to zero and a flag is set Card is programmable to allow all
143. peed of 10 RPS CW would be read as 192Ah When max velocity is set to 50 8626 RPS an actual speed of 10 RPS CCW would be read as E6D5h To convert a velocity word to RPS Velocity in RPS Maximum x Output Full Scale If Velocity Output were E6D5h and maximum velocity were 50 8626 RPS then Velocity in RPS 50 8626 x E6D5h 32 768 50 8626 x 6 442 32 768 10 RPS REGISTER 015 014 013 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION VELOCITY DIDiIDI DIDIDIDIDIDIDIDIDIDIDID D D DATA BIT 2s Complement Ratio Type 16 bit unsigned integer Range 1 to 255 Read Write R W Initialized Value 1 Single Speed Enter the desired ratio as an integer number in the Ratio Register corresponding to the pair of channels to be used for a two speed or multi speed configuration Example 36 1 integer 36 Default is for single speed applications where Ratio 1 REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Do FUNCTION RATIO D DATA BIT Angle Type 16 bit unsigned integer Range 0 05 to 180 degrees Read Write R W Initialized Value 0 Enter the minimum differential angle to associated channel Angle A register required to trigger an angle change alert See Angle A Alert regist
144. played in a status word All inputs are double buffered for immediate availability External excitation not required User Interface RTD Module Block Diagram AD amp Wrap Protective Circuits Around Test Circuit 1 AD amp Wrap Around Test State Machine Module Bus Circuit 6 The D2 test initiates automatic background BIT testing where each channel is checked to a test accuracy of 0 2 FS and monitored for open input Any failure triggers an Interrupt if enabled with the results available in status registers The testing is totally transparent to the user requires no external programming and has no effect on the operation of this card It can be enabled or disabled via the bus RTD Open Circuit monitoring is disabled during D3 testing MODULE MEMORY MAP 000 Resistance 1 R 00 Range 2 R W 01C 3 or 4 Wire Mode 3 R W 0C6 Module FPGA 12 R 002 Resistance 2 010 Range 3 R W 01E 3 or 4 Wire Mode 4 R W 0C8 Module FPGA 21 R 004 Resistance 3 R 012 Range 4 R W 020 3 or 4 Wire Mode 5 R W OCE Module ID R 006 Resistance 4 014 Range 5 R W 022 3 4 Wire Mode 6 R W 000 Status Ch 1 6 R 008 Resistance 5 R 016 Range 6 R W 0C0 Module Design Version 002 Open Status Ch 1 6 R Resistance 6 R 018 or 4 Wire Mode 11 R W 0 2 Module Design Revision R 0 8 Stat Interrupt Enable Ch 1 6 R W 00C
145. programmed for Output each channel can be set for either High side Lo side or Push Pull operation Diode clamping useful for inductive loads such as relays and thermal protection are incorporated Power isolated from the VME bus There are 4 user provided Vcc inputs for each 16 channel module There is one Vcc input for each four channel bank Module Memory Map 000 Write Output 01 16 R W 04C Upper Threshold Ch 08 R W 1098 De bounce time 15 R W 002 Read I O Ch 01 16 R 04 Lower Threshold Ch 08 R W 09A High Threshold 16 R W 004 High Threshold Ch 01 R W 050 Min Low Threshold 08 R W 109 Upper Threshold 16 R W 006 Upper Threshold Ch 01 R W 1052 De bounce time 08 R W O9E Lower Threshold Ch 16 R W 008 Lower Threshold Ch 01 R W 054 High Threshold Ch 09 R W 0 0 Min Low Threshold Ch 16 R W 00A Min Low Threshold Ch 01 R W 056 Upper Threshold Ch 09 R W 0 2 time 16 R W 00 De bounce time Ch 01 R W 058 Lower Threshold Ch 09 R W 0A4 Input Output Format Ch 01 08 R W 00 High Threshold 02 R W 0 Min Low Threshold Ch 09 R W 0 6 Input Output Format 09 16 R W 010 Upper Threshold 02 R W 05C De bounce time Ch 09 R W 0A8 Current For Sink Source Bank 1 01 04 R W 012 Lower Threshold 02 R W 05
146. put is set to 0 at reset or Power on 16 bits channel for either output range 0 05 FS 1 mV over temperature 0 0196 FS over temperature 0 0296 over temperature Optically isolated in groups of ten 250 V to VME power 10 us max 20 ma channel max Source or Sink Can drive a capacitive load of 0 1 mfd Short circuit protected When current exceeds 20 ma for any channel for 50ms that channel is set to zero and a flag is set Card is programmable to allow all channels to be reset by either an automatic retry or by a control port command 10 20 microseconds per channel Designed to meet the testing requirements of IEC 801 2 Level 2 4 transient with a peak current of 7 5A and a time constant of approximately 60 ns 12 VDC at 145 ma typical 192 ma max 5 VDC at 91 ma typical 150 ma max 1 oz 28g 64 C1 A001 Rev 6 3 do 631 567 1100 631 567 1823 fax 7 14 5 Cage Code OVGU1 Page 12 of 74 1 Resolution RTD Interface Open Input sense Excitation Accuracy Grounds Update rate Output Format ESD protection Power Weight D A Module J3 Output range Resolution Accuracy Offset Output format Settling time Load Output impedance Update rate ESD protection Power Weight D A Module J5 Output range Resolution Accuracy Offset Output format Settling time Load Output impedance Update rate ESD protection Power Weight N
147. r Output logic write of the operational channel and test comparator must agree or a fault is indicated with the results available in the associated status register Low to High and High to Low logic transitions are indicated Additional testing of output logic indicates Over current condition when output logic is invalid for a period greater than 80us Status indications Fault processing data read or write logic is inconsistent with redundant test circuit Status is indicated within 15 seconds A fault is latched until read Testing takes approx 1 second per channel Lo Hi Transition If a Lo to High transition is sensed status is indicated within 40us Hi Low Transition If a High to Low transition is sensed status is indicated within 40us Over current If over current or overload condition is sensed status is indicated bit is set within 80ps Output is however immediately disabled at time of over current condition Over current is re checked every 6ms If applicable output is re enabled and channel is reset A 0 indicates Passing and 1 Failing status Reading will reset or unlatch Status Register 015 D14 D13 D12 D11 D10 DB D7 De D5 D4 D3 D2 D1 DO Ch 11 Ch 10 Ch 9 jch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 11 jch 10 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 11 Ch 10 Ch 9 jch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 11 Ch 10
148. r channel 9 1 bit per 4 channel bank 9 T One register per 4 channel bank 9 4 Input Ch1 8 voltage sensing 0 without current source sink X NO current source 0 default default 5 Input Ch1 8 contact sensing 0 Ch1 8 with current pull up 3 1 10 6 Input Ch1 8 contact sensing 0 Ch1 8 with current pull down 12 2ma 20 7 Input Ch1 8 OPEN line detect 0 Ch1 8 with current pull up 3 0 5 ma 5 load is current sink Program Max Upper Threshold 6 Input Ch1 8 OPEN line detect 0 Ch1 8 with current pull down 12 0 5 ma 5 load is current source Program Min Lower Threshold Notes 1 Figure 6 with 10k ohm resistor nearest load as in figure 7 2 Vcc gt Tmu gt where load is current sinking 3 lt Vcc logRog where load is current sourcing INPUT CONFIGURATIONS Voltage Sensing Contact Sensing VCC RECOMMENDED CIRCUIT EB to detect OPEN Wire VCC Add 10k Ohm resister nearest to Current VO Pin load just before contact switch Source e o 0 5 mA Source 0 5 mA current Input Output Threshold input levels accordingly Voltage Sensing Circuit Pin i VO Pin Zin Current T ed defined by Threshold values Sink I O Pin Zin Zin Zin 2 10k Figure 4 Figure 5 Figure 6 Figure 7 Current for Source Sink Program any current from 0 to 5 ma Programs entire bank there are 4 channels per bank For 5ma enter integer 50 Resolution is 100pa per bit _5 100 A current value of zero disables the current source sink circuits and
149. shold Ch 08 R W 096 Min Low Threshold Ch 15 R W OF6 Interrupt Hi Lo Transition Enable Ch 01 16 R w Note 1 As of July 2005 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 47 of 74 Write Output When channel is configured for Output write logic level High 1 or Low 0 to associated channel bit in 16 bit binary word Each bit corresponds to one of 16 channels See Register Bit Map Output logic is defined by the provided Vcc voltage to that channel bank There are four channels per bank See J1 amp J2 or P2 amp PO pin out REGISTER 015 014 D13 D12 D11 D10 D9 D7 D6 05 D4 D3 D2 D1 DO FUNCTION 16 15 14 13 12 11 10 9 8 7 6 514 312 1 Channel WRITE OUTPUT D D D D D D DATA Read I O Independent of channel configuration Input or Output read logic state High 1 or Low 0 as defined by channel threshold values Each bit of 16 bit binary word corresponds to one of 16 channels REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 16 15 14 13 12 11 1019 8 7 6 5 4131211
150. sistors or hardware is required to provide for current flow current value of zero disables the current source sink circuits and configures for voltage sensing Default is voltage sensing All four threshold levels must be programmed For input threshold levels define logic state For output threshold levels are used in BIT test wrap around signal monitoring INPUT OUTPUT INTERFACE OUTPUT CONFIGURATIONS INPUT CONFIGURATIONS VCC High Side Drive Voltage Sensing T C Input Output Voltage Sensing Circuit Pin a e 0to 5 ma defined by Threshold values x Pin Ky Enable Drive Szin LOAD Input Output Pin d VCC Contact Sensing Enable VCC Low Side Drive gt VCC Pe 21 0 Current VO Pin i EM 0 OFF LOAD Source 94 IO Pin zin Current Sink Zin Zin Voltage Sensing Circuit defined by Threshold values NOTE CLAMP DIODES NOT INCLUDED IN MODULE K1 VCC Push Pull Drive VCC RECOMMENDED CIRCUIT to detect OPEN Wire Input Output Pin Add 10k Ohm resister nearest to e um load just before contact switch 0 5 mA Source 0 5 mA current Pin LOAD Threshold input levels accordingly om o Pin m4 Zin Zin 10k 22 2 Equivalent Circ
151. sscseenscescsesecnncssceecessenscensesseaseaseceseseceseesconeessesseasecuseseesseesconessesseesconeesses 48 MIN LOW THRESHOLD ec tte eed een reete ve cet ee teenies 48 DE BOUNCE TIME 48 INPUT OUEZPUTINTEBEAGCE rene eerte et to c ha 49 CURRENT FOR SOURCE SINK i oeseri ror re HP oce EHE ERI EET ED REN EE ETE ERE ERE FREE PE HEFT EE 51 JINPUTOUTPUT FORMAT 4 51 PULL UP DOWN CURRENT CONFIGURATION 4 52 64 1 001 6 3 North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7114 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 5 of 74 RESET OVER CURRENT es eet ecu vae eg S DECR edd EE vas 52 MODULE DESIGN VERSION RR 52 MODULEJDESIGN REVISION 25 25 II ME EL E 52 hue mul NC 53 MODULE PRGA WPCC E m 53 UD coitu rrr ee ety 53 AUTOMATIC BACKGROUND BIT TESTING 53 STATUS 53 STATUS INTERRUPT ENABLE cire i cete erect rte e e t eee EIE vete
152. ster is be automatically reset to 0 after channel output reset activity is complete Card will attempt to reset channel output s once for every time 1 is written to the register D A Override Write 1 at Override register to turn ON all overloaded outputs short life condition Reference Design Version The register holds reference design version in ASCII For example design version 1 would be ASCII 1 is in upper byte and ASCII space in lower byte together 3120h REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODEL 0 ASCII 1 ASCII Reference Design Revision The register holds reference design revision in ASCII For example design revision A1 would be ASCII 1 is in upper byte and ASCII space in lower byte together 4131h REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODEL 0 D DATA ASCII ASCII 1 Design Version The register holds product design version in ASCII For example design version 1 would be ASCII 1 is in upper byte and ASCII space in lower byte together 3120h
153. t impedance Update rate Output control Power Weight Module K1 Discrete Input Input Range Input Pulse Detection Input Impedance Switching Threshold Accuracy of Set Point ON OFF Differential Voltage Contact Sensing De bounce Update Rate Over Voltage Protection Discrete Output Output Range Output Current Output Load Output Format Write Delay Update Rate Over Voltage Protection Power Per 16 channel module Weight North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 Four 4 D A Outputs 20 to 80 VDC VME ISOLATED 20 to 80 VDC Output is set to 0 at reset or Power on Programmable in pairs from 20V to 80V Each D A return has separate pins that are common within each module These returns are isolated from VME ground 12 bits channel 0 15 FS 10 us 10 ma channel max Source or Sink up to 80VDC Short circuit protected 10 20 us per channel via software Enable Disable of DC DC converter 5 VDC 250ma max per module 1 oz 28g Sixteen 16 Discrete NON ISOLATED Programmable for Input or Output Superseded by Module K2 0 to 50 VDC A signal pulse width 40us or greater will be sense and indicated by the appropriate Hi Lo or Lo Hi Transition Interrupt 100 KO Four levels are programmable from 0 to 40 VDC with 10 bit resolution 0 9896 FS On Off Short to V Short to ground The greater of 596 signal value or 0 25 volts 0 25
154. that user programs to a desired current level When programmed for Output each channel can be set for High side Lo side or Push Pull operation Diode clamping useful for inductive loads such as relays and thermal protection are incorporated Power isolated from the VME bus There are 4 user provided Vcc inputs for each 16 channel module There is one Vcc input for each four channel bank North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com 7 14 5 Cage Code OVGU1 64_C1_A001_Rev_6 3 do 46 of 74 DISCRETE MODULE Discrete IO Module Block Diagram Each channel is programmable for either Input or Output When programmed for Input they can be 1 4 used for either voltage or contact sensing Voltage T Threshold IN 1 sensing covers the range of 0 to 80 VDC and E offers four levels of switching thresholds Protective State 9 Channels set for contact sensing can be USA E programmed for either pull up or pull down Our e 1 IN OUT 16 unique design eliminates the need for pull up 16 OUT 16 resistors or mechanical jumpers Instead we offer a current source in groups of 4 that user Wrap Arounc programs to a desired current level When T MUX
155. uit Input Impedance Zin 40k ohms To detect an OPEN line when contact sensing add 10k ohm resistor R nearest to load Program open detect current loa and calculate open contact condition drop voltage Vopen at I O pin Select sourcing current loa such that drop voltage AV is about 80 of Vcc If open detect resistance Rog is the parallel combination of the near load resistance Rn and the circuit input impedance Zin Then Rog Ru Zin 10k 40k 8k If user provided Vcc is 10v la 20 8 Vcc Rog 0 8 x 10 8k 1ma If log Ima we get open contact condition drop voltage Vopen at the I O pin Vopen x 8 0 volts If load is current sink Program Maximum Upper Threshold some 20 greater then maintaining 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 50 of 74 gt gt Vopen gt Tut er 1 2 Vopen 1 2x8 9 6 volts Program Upper Threshold Tu 20 less then Vopen 0 8 Vopen 0 8x8 6 4 volts Accordingly program Lower Threshold at 20 Vcc and Minimum Lower Threshold Tm at 10 Vcc Te 0 2Vcc 0 2 x 10 2 volts Tm 0 1 Vcc 0 1x 10 1 volts To detect a line SHORT when contact sensing and continuing with this example user needs to add series resistance nearest to load Rs and calc
156. ulate closed contact condition drop voltage Vaosea at I O pin Resistance nearest to load Rs should be negligible as compared to the near load resistance Ru but at least a magnitude greater than any resistance due to wire length A value of 150 ohms would be appropriate for Rs Then Volosed odR 1ma x 0 1kO 0 15 volts Program Lower Threshold Tmu greater then Vaosea maintaining Vcc gt gt Tit 2 Vaosed e Tmi gt 0 Tr gt 1 2 Vaosea gt 1 2 x 0 1 0 2 volts Program Minimum Lower Threshold Tut 2090 less then 0 8 Vaosea lt 0 8 x 0 15 lt 0 1 volts In general Vcc gt Tmu gt Vopen gt gt Tit gt Vaosea gt Tmi gt 0 gt 0 25mV for hysteresis configuration To detect a Short to Vcc Program Maximum Upper Threshold where Vcc gt Tmu gt Visadmax where Vioadmax is the maximum voltage potential on the I O To detect a Short to Ground Program Minimum Lower Threshold Tm where Vcc gt gt Vioadmin gt where Vioadmin is the minimum voltage potential on the I O pin Consider the following programming options Output Programming Examples Figure INPUT OUTPUT FORMAT itede PULL UP DOWN Configuration integer CURRENT FOR SOURCE SINK 9 2 bits 9 1 bit per 4 channel bank 9 One register per 4 channel bank 9 1 Output Ch1 High Side 2
157. ulate module 4 Address Base Module 1 Offset 010 Digital I O Mother Board Block Diagram o VME Interface gt FPGA gt 5 t Optional Reference Supply z register 000 Base 010 hex Address Base Module 4 Offset 300 Discrete register 022 Base 322 hex MEMORY MAP 000 Module 1 Register 200 Module 3 Register 400 Module 5 Register 002 202 402 004 204 404 006 206 406 Module 1 2 Module 3 Module 5 Offset 000 Offset 200 Offset 400 OFC 2FC 2FE 4FE 100 Module 2 Register 300 Module 4 Register 500 Module 6 Register 102 302 502 104 304 504 106 306 506 w Module 2 2 Module 4 Module 6 Offset 100 Offset 300 Offset 500 1FE ADDRESS SPECIFIED WITHIN 2048 BYTE BLOCK UP 7 18 RESERVED The memory map of each module type is described hereafter North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 631 567 1100 631 567 1823 fax www naii com e mail sales naii com 7 14 5 Cage Code OVGU1 DSP o N Module o 1 3 FPGA a
158. ules generate one of a selection of waveforms sine triangular or square wave per channel programmable in frequency and amplitude Use of an individual A D self test channel on a rotating basis verifies that the channel is operating properly in frequency amplitude and DC offset See wrap around test registers for BIT data Operating at all times is a background Built In Test BIT where each channel is checked to a test accuracy of 2 FS Any failure triggers an Interrupt if Signal Module Block Diagram Output Amp FG 1 Circuit 1 1 o State e e Diode 9 E Machine Protection E 2 4 Output FG 4 Circuit 4 4 Wrap Around 4 1 Test MUX A D enabled with the results available in status registers BIT is intended for use with steady state signals any change in channel configuration amplitude frequency etc requires up to 12 seconds before wrap data reflects that change Multiple changes in channel configuration in less than 12 seconds may trigger false BIT failures The testing is totally transparent to the user requires no external programming and has no effect on the operation
159. unce time 15 R W 004 Status Over Current Ch 01 16 R 02A Debounce time Ch 4 R W 0A2 Debounce time 16 R W ODC Status Lo Hi Transition Ch 01 16 R 034 Debounce time Ch 5 R W 0A4 Input Output Format Ch 01 8 R W ODE Status Hi Lo Transition Ch 01 16 R 03E Debounce time Ch 6 R W 0A6 Input Output Format Ch 09 16 R W 0E8 Interrupt Fault Enable Ch 01 16 R W 048 Debounce time Ch 7 R W OBC Reset Over Current Ch 1 16 R W OEC Interrupt Over Current Enable Ch 01 16 R W 052 Debounce time Ch 8 R W 0 0 Module Design Version R 0 4 Interrupt Lo Hi Transition Enable 01 16 R W 05C Debounce time Ch 9 R W 0 2 Module Design Revision R OF6 Interrupt Hi Lo Transition Enable 01 16 R W 066 Debounce time Ch 10 R W 0C4 Module DSP R Note 1 As of July 2005 Write Output When a channel is configured for Output write logic level High 1 or Low 0 to associated channel bit in 16 bit binary word Each bit corresponds to one of 16 channels REGISTER 015 014 013 0121011 010 D9 D8 D7 D6 D5 D3 D2 D1 DO FUNCTION 16 15 14 13 12 11 10 9 8 7 6 5 14 32 1 Channel WRITE OUTPUT 0 D DATA BIT Read I O Independent of channel configuration Input or Output read logic state High 1 or Low 0 as defined by channel threshold values
160. ver current draw for each active channel A 0 Normal 1 Over Current An over current draw from the output of any D A channel is detected within 2 seconds and will latch the corresponding bit in the Over Current Status register Reading any status bit will cause unlatch the entire register Over Current Status is part of background testing and the status register may be checked or polled at any given time D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Over Current Status X X X X X X Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 BIT Status Interrupt Enable Set the bit to enable interrupts for the corresponding channel When enabled non compliant channel will trigger an interrupt Default is 001 to disable all channels 015 D14 013 012 D11 D10 D9 D7 06 05 D3 D2 D1 DO Status Interrupt Enable x x x x X X Ch 10 Ch7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Over Current Status Interrupt Enable Set the bit to enable interrupts for the corresponding channel monitored for Over Current Status 015 D14 D13 D12 D11 D10 D9 07 D6 D5
161. x Xx xilxlxl xlxilD D IDIDiD D ID D D DATA BIT Input Termination Control Each differential input pair can be programmed to have an input termination of 120 or gt 12k Write logic 1 to select 120 for each individual channel Default is 12k REGISTER 015 0141013 1012011 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 11110 7 6 5 4 2 1 INPUT TERMINATION X X D D D D D Input Output Format Write integer O for input 3 for output Default is configured for Input REGISTER 015 014 013 012011 010 D9 D8 D7 D D5 D4 D3 D2 D1 DO FUNCTION INPUT OUTPUT CH 01 08 Ch 08 Ch 07 Ch 06 Ch 05 Ch 04 Ch 03 Ch 02 Ch 01 Channel INPUT OUTPUT CH 09 11 Ch 11 Ch 10 Ch 09 Channel INPUT OUTPUT Du DL Du De Du DL Du De Du DL Dy De Du Di D DATA BIT Integer Du Di 0 0 0 Input 3 1 1 Output Module Design Version Type ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design version in ASCII For example ASCII 1 in upper byte and ASCII space in lower byte for Module Des
162. y 10 R W Wrap around 10 R W OEC Current Interrupt Enable Ch 1 10 RAW Note 1 As of July 2005 Write D A output If using bi polar mode write 16 bit 2 s complement word to the channel s Data register 7FFFh FS 8000h FS If using unipolar mode write 16 bit binary word to the channel s Data register range 0 to FFFFh FS D A Output Polarity Write integer 4 to the channel s D A Polarity register for unipolar mode Write integer 0 to the channel s D A range register for bi polar mode D A Wrap Around Read D A wrap around data register 16 bit 25 complement word 7FFFh FS 8000h FS bipolar mode or 16 bit binary word range 0 to FFFFh FS 64 C1 A001 Rev 6 3 do North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 7 14 5 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 37 of 74 Design Version ASCII character in each upper and lower byte Range N A Read Write R Initialized Value N A This register holds module design version in ASCII For example ASCII 1 in upper byte and ASCII space in lower byte for Module Design Version 1 is together 3120h REGISTER 015 014 013101210111010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MODULE SPECIAL SPEC D D D DID 0 0 0 0 0 0 D DATA ASCII 1 ASCII

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