an ahb-pci bridge intellectual property core with aes-128
Contents
1. SSRAM Figl1 Block diagram of PCIP core C Operation Flow For PCI to AHB flow data of PCI host is stored into SSRAM It is loaded to PCI FIFO before is read by AHB master If the encryption mode is active data will be enciphered before is gotten by AHB master Fig 3 Pow PCI FIFO completed m optional Tian dnia iais Samia iay gai sae S a ar ajai e a G PCI host writes to e a p gt SECIN SSRAM Te OPR ee ves Read enable sianal PCI host sets the PCI host sets the start ssel 9 read range ofthe lt read address of PCI PCI FIFO FIFO No Data is loaded into completed encipher O COMPLETE eO AHB master is able to read data Fig 3 PCI to AHB flow For AHB to PCI flow the data transfer is shown asFig 4 BEGIN fo ao AHB master writes to SSRAM Read enable signal is set AHB master sets the read range of the AHB FIFO completed ves lt AHB master sets the start read address of AHB FIFO Data is loaded into AHB FIFO completed optional COMPLETE o gt completed 2 Fig 4 AHB to PCI YES S decipher ae PCI host is able to read data flow Ill ANALYSIS2. So you are able to use a processor core to build a private application systemand connect to computer by PCI slot Additionally the exchange data can be protected by AES 128 encryption mechanism IV CONCLUSION This IP core has two outstanding features First it is the data exchange bridge between PCI 2 3 bus and AHB bus Second if the encryption mode is active data from PCI master will be enciphered with AES 128 algorithm before sending and data from AHB master will be deciphered before is received by PCI master The second feature supports to the security applications Up to now the PCI AHBbridge IP core was tested on FPGA board after had been simulated by VCS tool REFERENCES 1 PCI Special Interest Group PCI local bus specification revision 2 3 March 29 2002 2 PCI Special Interest Group PCI to PCI bridge architecture specification revision 1 1 December 18 1998 3 ARM Ltd AMBATM specification revision 2 0 May 13 1999 4 Federal Information Processing Standards Publications Announcing the ADVANCED ENCRYPTION STANDARD AES November 26 2001 5 ICDREC VN1632 RISC microprocessor user s manual 2010
3. key 0 Add Round Key A bo Q y y Inverse Sub Bytes Z Substitute Bytes Expand A key O v Inverse Shift Rows OC Q Shift Rows A Z gt Y Q Mix Columns oo Inverse Mix Cols 3 e Add Round Key lt key P Add RoundKey Q A Z D v Inverse Sub Bytes O A am Inverse Shift Rows y A Substitute Bytes O Yv Q Shift Rows A Z 2 O Mix Columns Inverse Mix Cols A v b m Add Round Key key 9 AddRoundKey Q A Z D Inverse Sub Bytes O Substitute Bytes A o oO Inverse Shift Rows D a v A Shift Rows Inverse Q Expand Z ke 2 Po O an A Add Round Key lt key 10 gt Add Round Key v Ciphertext Ciphertext a Encryption b Decryption Fig 7 AES 128 encryption and decryption algorithm E Demo and application The demo system which is used to test IP core is built as follows VN1632 DMA processor core controller t t t AMBA AHB Boot loader ASRAM FLASH Memory controller 4 AMBA APB gt SSRAM gt ioe UART GPIO ML555 N computer ENN Fig 8 Demo system of PCI AHB bridge IP core At AHB bus side the components are load into Xilinx FPGA board ML555 and a VN1632 5 processor is used to control all operations ThisML555 board is plugged in PCI slot of computer which is installed the suitable driver to identify PCI card and access data from SDCARD
4. AN AHB PCI BRIDGE INTELLECTUAL PROPERTY CORE WITH AES 128 ENCRY PTOR DECRY PTOR Nguyen Hung Quan Do Ngoc Quynh Tran Kien Cuong PhamThanh Hung and Bui Quang Tung IC Design Research amp Education Center 6th quarter LinhTrung ward Thu Duc district HCM city Vietnam E mail quan nguyenhung quynh dongoc cuong trankien hung phamthanh tung buiquang icdrec edu vn Abstract An AHB PCI bridge which is able to connect both Peripheral Component Interconnection PCI local bus version 2 3 and Advanced High performance Bus AHB is integrated the AES 128 encryptor and decryptor to apply the security data exchange card The encryptor enables to encipher data from PCI bus and the decryptor enables to decipher data from AHB bus This design was implemented on Field Programmable Gate Array FPGA cardML555of Xilinx Inc Index Terms PCI2 3 specification AMBA Advanced Encryption Standard FIPS 197 specification I INTRODUCTION CIlocal bus is a high performance bus with multiplexed address and data lines It is usedto connectthe highlyintegrated peripheral controller components peripheral add in cards and processor memory systems 1 2 Network card Processor core Audio card menn A f2 ae Cache PCI Bridge Memory Peripheral Component Interconnection PCI Local bus 2 e gt Graphic card Expanded bus interface SCSI bus Convert card F
5. OF FUNCTION AND APPLICATION A PCI Target f ICDREC_PCI_Target PCI Target Subcircuit PCI Target Ports Qpenicraln output PCI Tri State ouput P_SE_siTarget Control signal decoder lt B gt cin lt i Interface input pad e eee O Port TS DH j PCI Target FSM PCI Target Cfgreg IDLE ADDRESS i A 2 BACKOFF ey Fig 5 PCI target block diagram The PCI target responds toall requests of PCI initiator when this device is selected It can process these following commands e configuration read write memory read write memory read multiple dual address cycle memory read line memory write and invalidate The request can be in single data or burst data mode In the burst data mode many consecutive addresses will be satisfied that doesn t need to send request signals again This helps to increase the system performance for large data block transfer B Arbiter There are two FIFO modules which can read from the corresponding memory AHBSSRAM and PCI SSRAM These FIFO only read data from the memories This data can be encrypted or decrypted before any transaction Besides the AHB bus can also access the data from AHBSSRAMand the PCI bus can also access data from PCI SSRAM When the FIFO reads from its memory it maybe disputed with the bus access to the corresponding memory if they read or write at th
6. e same time The control arbiter module is designed to handle and arbitrate when the bus and the FIFO access from the same memory So when any bus or FIFO wants to access data from the memory it must sample its corresponding signals that the arbiter grants Any address and control phase are true and can be handled when they havethe permission from the arbiter There are some rules of arbitration as following 1 If there are no subjects access data all of the bus and the FIFO are allowed have the permissions 2 If there is only one subject accesses data the arbiter always allows it and doesn t lock the others 3 If there is the disputation we have three rules a If the address of the bus and the address of the FIFO aren t the same the winner is the one which is waiting wait for lost but not wait for the other reasons b At the beginning of the arbitration if the address of the bus and the address of the FIFO aren t the same the winner is always the bus access c Ifthe address of the bus and the address of the FIFO are the same the winner is always the FIFO access C AHBSlave The AHB Slave is designed to communicate between AHB Master and the AHB memory space There are two AHB memory spaces the SSRAM memory and the functional register field Both of them have the same offset address The AHB bus must have two decode selection signals to access to them At one time only one select signal is active to acces
7. ig 1 PCI bus system The AHB bus is used to connect the processor cores and peripherals which require the high performance and high system clock frequency 3 Processor TFT LCD APB bus core controller Advanced High performance Bus AHB y Memory DMA master Fig 2 AHB bus system The Advance Encryption Standard AES is a symmetric block cipher algorithm that is approved by Federal Information Processing Standards Publications FISP can be used to protect electronic data 4 The PCI AHB bridge intellectual property IP core not only connects to PCI 2 3 bus but also connects to AHB bus to exchange data between them Besides it is added encryption and decryption capabilityto support the security applications In order to test this IP core a demo system is implemented on Virtex 5 FPGAboardMLS555of Xilinx Inc after is simulated and verified by VCS tool of Synopsys The features main functions and structures of IP core will be described in 2 and 3 If PCI AHB BRIDGE IP CORE ARCHITECTURE A The Features The PCI AHBBridge has the basic following basic features e PCI specification 2 3 compliant o Zero wait state burst mode 33 66 MHz performance 32 64 bit data path Dual address cycle Memory Read Memory Write commands Configuration Read and Write commands Fast Back to Back Transactions Type 0 Configuration space Parity ge
8. neration and parity error detection e AHB2 0 interface compliant e Synchronous AMBA and PCI clocks e SSRAM accessible from both PCI and AHB bus the memory spaces are separately e Enable configuration of SSRAM capacity and FIFO depth e Output encryption and input decryption with AES 128 e DMA handshaking interface O O O O OOOO B Block Diagram The blocks of IP core are designed to exchange data between PCI 2 3 bus and AHB 2 0 bus The function of some basic modules is showed as follows e PCI TARGET receives and responses requests of PCI initiator e AHB SLAVE receives and responses requests of AHB master e ARBITER arbitrates the read write accesses from to Synchronous Static Random Access Memory SSRAM e AES 128 encryptor enciphers data which is plaintext from PCI bus before transferring to AHB bus e AES 128 decryptor deciphers data which is ciphertext from AHB bus before transferring to PCI bus SSRAM PCI SSRAM FIFO controller PCI FIEO C gt PCI FIFO BUFFER gt AES 128 read enable __encryptor PCI ARBITER AHB TARGET SLAVE AES 128 read enable __ decryptor E AHB FIFO AHB FIFO BUFFER AHB SSRAM PCI AHB FIFO controller Bridge
9. s the AHBSSRAM or the functional register field 00h MEM_ADDR_WIDTH AHB SSRAM PCI function registers reserved AHB function registers reserved Alias field hsel_mem AHB bus Fig 6 AHB memory space About the functional registers the AHB bus only writes into the AHB register region 80h BOh but it can read all of the functional regions the configuration registers the AHB registers and the PCI registers When the AHB bus wants to access the AHBSSRAM it must have the permission from the arbiter We can use the AHB interface to communicate with the AHB master to transfer the data We also use the DMA slave to transfer data directly Note that the DMA slave only request the read command the write command isn t supported D AES 128 encryptor decryptor If the security mode is active the output data from PCI bus to AHB bus will be enciphered with a 128 bit key and the input data from AHB bus to PCI bus will be deciphered with the same key The encryption algorithm is shown as follows PCI configuration registers Plaintext KEY Plaintext A Vv Add Round Key lt
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