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DM35425 - User`s Manual - RTD Embedded Technologies, Inc.

1. essere Table 9 IDAN DM35425 68 Pin Subminiature D Connector senes Table 10 IDAN DM35425 62 Pin High Density D Connector smsraravrsraverrsrararrsreresrrverrsrererrrvenesrenennn Table 11 IDAN DM35425 62 Pin High Density D Connector sosravavrsnaverrsvororrsrerrsrrvenrsrererrrrenenrenennn Table 12 ADC Bipolar Code 5 V Input Range senes Table 13 ADC Bipolar Code 10 V Input Range ccssssssessssssscscsssssescesssseeecessssseesesssaseterseses Table 14 ADC Unipolar Code 0 to 10 V Input Range serene Table EO S L C RR m Table 16 DMA Registers P v Table 17 Multi Channel ADC Functional Block sss Taboo ADE Full Scale E 111 erae demones uirtus utens EE Table 19 Multi Channel DAC Functional Block orrrrerrrrrrorrsrororrrrenrsrerarrrreresrerenrrnenesrrvenrsrenesrrnenesrenennn RTD Embedded Technologies Inc www rtd com vi Accessing the Analog World DM35425HR User s Manual EEE 44 Table 21 Digital lO Functional BOK bek katon ik katolik sil al ode rad daki kis kai daun e kk pdi ft epa pe d Si Ha aes 46 Table 22 External Clocking Functional Block cccccccsccssssssssssscscsssscsesscscsesecsssesecscsesessesessssesassesesassesessssesessesesassesasaesesassesasaesesassesasaesesassusasaseesas 51 Table 23 Data Values for Calibrating Bipolar 10 V Rang
2. x 212 Count x 212 10 10 Refer to Table 20 on page 44 for full scale ranges for both unipolar and bipolar modes Each DAC converter has a 511 sample FIFO for DMA Each sample is packed into 32 bits right justified and sign extended 5 5 Advanced Digital I O The DM35425 features 32 digital I O line with DMA parallel bus mode and advance interrupts DMA The DM35425 has three DMA channels for Digital I O input output and direction Each channel has a 511 sample FIFO for DMA Each sample is packed into 32 bits Advanced Interrupts The DM35425 has an advanced interrupt block that can generate an interrupt on a match or event The interrupts are across all 32 digital I O The bits can be individually selected When an interrupt is generated the data on all of the ports is latched into the Capture registers Bits are tested regardless of if a pin is an input or output A Match interrupt is generated when all un masked bits in the Compare register match the input value of the port An Event interrupt is generated when any un masked input port bit changes Parallel Bus Mode The DM35425 also features parallel bus mode for the digital I O lines In this mode the 3 MSB lines of the Digital I O are switched to control signals Ready Valid and Clock The remaining lines are used as a data bus When the clock pin is set to output a high clock pulse 50ns will be sent every Digital I O pacer clock Also at the
3. DM35425HR PCI Express Data Acquisition Board User s Manual BDM 610010047 Rev D ot E EE EE T udo Na 5 Had TrA to E pon ki m tiiis sitir TT Accessing the Analog World Revision History Rev A Initial Release Rev B Add Parallel Bus set up note Add Power Consumption Updated IDAN Dimensions Picture Added a Channel Delay Section Added Equation 1 Rev C Corrected Signal Names in IDAN Pin Out Rev D Update Register Map to FPGA Rev C i ADC Function Block changed to 0x01031000 li DAC Function Block changed to 0x01032000 iii ADIO Function Block changed to 0x01003001 iv Add CH_FIFO_ACCESS register to ADC DAC and ADIO Add Section 5 6 External Clocking Add Clock Source description RTD Embedded Technologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com V AS9100 _ V 18509001 Advanced Analog I O Advanced Digital I O aAIO aDIO a2DIO Autonomous SmartCal Catch the Express couModule dspFramework dspModule expressMate ExpressPlatform HiDANplus MIL Value for COTS prices multiPort PlatformBus and PC 104EZ are trademarks and Accessing the Analog World dataModule IDAN HiDAN RTD and the RTD logo are registered trademarks of RTD Embedded Technologies Inc formerly Real Time Devices Inc PS 2 is a trademark of International Business Machines Inc PCI
4. sp naje Relative Humidit _Non Condensing 0 90 Telcordia Issue 2 MTBF Mean Time Before Failure 30 C Ground benign controlled 2 2 Electrical Characteristics Table 3 Electrical Characteristics Symbol P Test Condition Min Typical Max Unit p Power Consumption Ves ag DW lcs 5V Input Supply Current Active o 08 JA PCle 104 Bus Differential Output Voltage O 1 11 08 121V DC Differential TX Impedance 1 80 1290 0 9 Differential Input Voltage o 0475 121V X DCDifeeniaRXImpdace 80 12010 gt Electrical Idle Detect Threshold 1 65 po 1 5 mV Analog to Digital Converter Linear Input Voltage IN or IN 901 OOOO 5 FSR Full Scale Differential Input Vin IN IN lei 4 99878 Voltage G PGA Gain F G Resolution its pf DataRate 25 MSPS Input Impedance 26 MO O Single Ended 5V gt Od e Single Ended 5V gt e Single Ended 5V e gt wp Single Ended 5V eee Je Single Ended 5V Third Order Intermodulation Fin1 0 8dBFS Fin2 0 8dBFS Q 39 0625Khz Differential Inputs 5V Channel to Channel Cross Talk Been SampleDelay 1 MP BO SampeDely 1 A B 2SampeDeay 1 6641 BO G Gan 1 GID J 051248 Digital to Analog Converter Full
5. P2 Connector 68 pin Subminiature D Female Connector 5 117 in Connector Part Amp 749070 7 Sample Mating Connector Amp 786090 7 IDC Crimp Table 8 IDAN DM35425 68 Pin Subminiature D Connector Table 8 IDAN DM35425 68 Pin Subminiature D Connector Sigal DM35425 Pin IDAN Pin Signa DM35425 Pin AINO AINO 1 DIO1 AINO AIN8 CN3 Dog CN CN3 CN3 7 7 CN3 10 10 ti 12 4 18 16 CN3 32 DIO8 CN N CN3 CN N AV JON OT N D 1 1 1 17 1 OJO GO CO dd 3 O o 5 Co C2 7 DID 2 4 6 8 9 0 1 2 4 6 8 9 0 IDAN Pin 35 39 O T 8 MENN 40 O 42 OB 4 4 46 EF EM 48 EE NN 10 5 Lo v7 Lt 18 52 Lo 109 5 20 3 A n 5 2 59 3 2 59 gt O a J 58 5 2 o Lo 2 6 28 P 8 2 68 o amp 05 66 O T 68 1 2 2 2 2 2 2 2 2 2 2 3 3 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 91 52 53 54 55 56 57 58 59 61 62 63 64 65 67 ND 5V ND IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC RTD Embedded Technologies Inc www rtd com 19 DM35425HR User s Manual P3 Connector 68 pin Subminiature D Female Connector Connector Part 4 Amp 749070 7 Table 9 IDAN DM35425 68 Pin Subminiature D Connector DANPinf Signal DWG
6. 6 2 5 FB DMAm Stat Invalid Read Write 34 6 2 6 FB DMAm Stat Overflow Read Write 34 6 2 7 FB DMAm Stat Underflow Read Write 34 6 2 8 FB DMAm Stat Complete Read Write 34 6 2 9 FB DMAm Current Buffer Read Only 34 6 2 10 FB DMAm COUNT Read Only 34 6 2 11 FB DMAm RD FIFO CNT Read Only 34 6 2 12 FB DMAm WR FIFO CNT Read Only 35 6 2 13 FB DMAm ADDRESSn Read Write 35 6 2 14 FB DMAm SIZEn Read Write 35 6 2 15 FB DMAm CTRLn Read Write 35 6 2 16 FB DMAm STATn Read Clear 35 6 3 BAR ADC Functional Block uses 36 6 3 1 FB ID Read Only 36 6 3 2 FB DMA CHANNELS Read Only 37 6 3 3 FB DMA BUFFERS Read Only 37 6 3 4 Mode Status Read Write Read Only 37 6 3 5 CLK_SRC Read Write 37 6 3 6 START TRIG Read Write 37 6 3 7 STOP TRIG Read Write 37 6 3 8 CLK DIV Read Write 37 6 3 9 CLK DIV CNTR Read Only 38 6 3 10 PRE TRIGGER CAPTURE Read Write 38 6 3 11 POST STOP CAPTURE Read Write 38 6 3 12 SAMPLE CNT Read Only 38 6 3 13 INT ENA Maskable Read Write 38 6 3 14 INT STAT Read Clear 38 6 3 15 CLK SRC GBLn 38 6 3 16 CHn FRONT END CONFIG Maskable Read Write 39 6 3 17 CHn FIFO DATA CNT Read 39 6 3 18 CHn FILTER Read Write 39 RTD Embedded Technologies Inc www rtd com IV DM35425HR User s Manual 6 3 19 CHn THRESH STAT Read Clear 6 3 20 CHn THRESH ENA Read Write 6 3 31 CHn THRESH LOW Read Write 6 3 22 CHn THRESH HIGH Read Write 6 3 22 CHn LAST SAM
7. writing a value larger than the FIFO size will have indeterminate results 6 3 11 POST STOP CAPTURE READ WRITE Number of samples to collect after the Stop Trigger 6 3 12 SAMPLE CNT READ ONLY Total number of samples collected This only increment while in the Filling Pre Trigger buffer Sampling Waiting for stop trigger and Filling Post Stop buffer state It also continues counting after a Re Arm 6 3 13 INT ENA MASKABLE READ WRITE Each bit corresponds to an interrupt source A value of 1 enables the source and a value of 0 disables it See below for a description of the sources 6 3 14 INT STAT READ CLEAR Each bit corresponds to an interrupt source Reading a value of 1 indicates that an event has occurred Reading a value of 0 indicates that the event has not occurred Writing a 1 will clear that bit BO Sample A sample has been taken B1 Channel Threshold One of the channels has exceeded the High or Low threshold Check the CH THRESH STAT registers B2 Pre Start Buffer Filled B3 Start Trigger B4 Stop Trigger B5 Post Stop Buffer Filled B6 Sampling has completed and the FIFO is empty all data transferred to host B7 Pacer The pacer clock has ticked 6 3 15 CLK SRC GBLN NOTE If a CLK SRC GBL is unassigned in all function blocks it defaults to System Clock Immediate Selects the source to drive onto Clock Bus signal N B 7 0 0x00 0x80
8. 0000 0010 0000 0000 0001 0000 _ 0000 0000 1000 0000 0000 0100 0000 0000 0010 0000 0000 0001 0000 0010 0000 0000 0001 0000 0000 0000 1000 0000 0000 0100 0000 0000 0010 0000 0000 0001 000000000000 5000 00 0 00 10000 00 000 _ Table 30 Trimpots for Calibrating DAC Gain AOUO TRIP AOUT1 TR12 AOUT2 TR13 AOUT3 TR14 RTD Embedded Technologies Inc www rtd com 56 DM35425HR User s Manual Q Accessing the Analog World 8 Troubleshooting If you are having problems with your system please try the following initial steps e Simplify the System Remove modules one at a time from your system to see if there is a specific module that is causing a problem Perform you troubleshooting with the least number of modules in the system possible e Swap Components Try replacing parts in the system one at a time with similar parts to determine if a part is faulty or if a type of part is configured incorrectly If problems persist or you have questions about configuring this product contact RTD Embedded Technologies via the following methods Phone 1 814 234 8087 E Mail techsupport rtd com Be sure to check the RTD web site http www rtd com frequently for product updates including newer versions of the board manual and application software RTD Embedded Technologies Inc www rtd com 57 DM35425HR User s Manual Q Accessing the Analog World 9 Additional Informati
9. Each DMA channel has a block of registers associated with it to configure the DMA channel as well as set up the descriptors for the buffers in system memory In the sections below m is used to enumerate the DMA channels and n is used to enumerate the buffer descriptors within a channel Table 16 DMA Registers et Offset 0x03 0x02 A o oa 0x00 0x00 FB DMAm Stat Underflow FB DMAm Stat FB DMAm Setup FB DMAm Action Overflow D 0x04 FB DMAm Current Buffer FB DMAm Count D 0x08 FB DMAm RD FIFO CNT FB DMAm WR FIFO CNT D 0x0C FB DMAm Last Action FB DMAm Stat FB DMAm Stat FB DMAm Stat Complete Invalid Used D 0x10 FB DMAm CTRLO FB DMAm STATO Reserved D 0x14 FB DMAm SIZEO D 0x18 FB DMAm ADDRESSO D 0x1C D 0x20 FB DMAm CTRL1 FB DMAm STAT1 Reserved D 0x24 Reserved B DMAm SIZE1 D 0x28 FB DMAm ADDRESS1 D 0x2C 0x10 n 0x10 n FB DMAm ADDRESSn 0x10 n 0x10 n 6 2 1 FB DMAM ACTION READ WRITE This register is the overall control for this DMA channel After writing to the Action register the driver should poll the Last Action register below until it reads the same value This shows that the action has been performed by the DMA state machine This is especially important when entering and exiting the Clear state 0x00 7 Clear Clear the Current Buffer field the internal offset counters and the FIFO DMA is stopped 0x01 Go Starts DMA 0x02 Pause DMA transfers ar
10. Mode o 0x04 Uninitialized This is the power on state No converter initialization has taken place Sampling is stopped and all counters are reset and the triggering state machine is reset Transition to any of the other Modes will start converter initialization Sampling will not start until initialization is complete o 0x00 Reset Sampling is stopped All counters are reset and the triggering state machine is reset o 0x01 Paused Sampling is stopped but the counters and triggering state machine maintain their state o 0x02 Go Single Shot After filling the buffer with the Post Stop samples capturing stops The Mode must be set back to RESET in order to capture more samples o 0x03 Go Re arm After filling the buffer with the Post Stop samples and the FIFO is empty the triggering state machine is restarted i e FIFO is filled with Pre Start samples and waits for a start trigger B 7 4 Status o Ox08 Uninitialized The status when in the Uninitialized mode and the converter requires initialization o 0x09 Initializing o 0x00 Stopped The status when in the Reset mode or in the Uninitialized mode and the converter does not require initialization o 0x01 Filling Pre Trigger buffer o 0x02 Waiting for start trigger o 0x03 Sampling Waiting for stop trigger o 0x04 Filling Post Stop buffer o 0x05 Wait to re arm Waiting until local FIFO is empty so the pre trigger buffer can be filled o 0x07 Done capt
11. PCI Express and PCIe are trademarks of PCI SIG PC 104 PC 104 Plus PCI 104 PCle 104 PCI 104 Express and 104 are trademarks of the PC 104 Embedded Consortium All other trademarks appearing in this document are the property of their respective owners Failure to follow the instructions found in this manual may result in damage to the product described in this manual or other components of the system The procedure set forth in this manual shall only be performed by persons qualified to service electronic equipment Contents and specifications within this manual are given without warranty and are subject to change without notice RTD Embedded Technologies Inc shall not be liable for errors or omissions in this manual or for any loss damage or injury in connection with the use of this manual Copyright 2015 by RTD Embedded Technologies Inc All rights reserved RTD Embedded Technologies Inc www rtd com ji DM35425HR User s Manual Table of Contents 1 Introduction 1 1 Product OVEIrViOW scsessssssssssssssscsssssssscscssessesscsssssesasscsssesesacacessesasacessesesacaceeersavacasensesas 1 2 Board features een 1 3 Ordering Information cccccccscssscsssssssssssescssesssssssessssessesssessesecsssececsesesessesesaesesasseeesaseeses 1 4 Contact Information 00 ccecescssssssssesssssesscscssssseeecscssseecscssassesesesssseeeecesaseeeecesasaseeeesesaseteess 1 4 1 Sales Support 1 4 2 Technical Support 2 Specification
12. 0x03 1002 1004 000 O 0x04 GBC BUILD GBC IRQ STATUS GBC DIRQ STATUS bet PFG GE 6 1 1 GBC BRD RST READ WRITE This register is used to send a reset command to the board Write OxAA to this register to reset the board 6 1 2 GBC EOI READ CLEAR This register is used to acknowledge an interrupt It is used to safeguard against missing an interrupt At the end of the Interrupt Service Routines ISR write a 0x01 to this register If there is another interrupt pending in the status registers the interrupt line is toggled Legacy Mode or another interrupt is sent MSI Mode 6 13 GBC REV READ ONLY This register contains the FPGA revision for this board A 1 B 2 etc 6 14 GBC_FMT READ ONLY This register contains the format ID that is used in this board The current value is 0x01 6 1 5 GBC_PDP READ ONLY This register contains the PDP number for this board 6 1 6 GBC_BUILD READ ONLY This register contains a unique 32 bit build number for the FPGA code RTD Embedded Technologies Inc www rtd com 31 DM35425HR User s Manual Q Accessing the Analog World 6 1 7 GBC_SYS_CLK_FREQ READ ONLY This register contains the measured frequency of the system clock Units are 10 kHz i e Frequency in Hertz GBC SYS CLK FREQ 10 kHz This value is not available will read 0 until 100us after a Board Reset and is continually updated 6 1 8 GBC IRQ STATUS READ CLEAR This is a 64 bit interr
13. 6 6 9 EXT CLKN CFG READ WRITE Selects clocking method B 7 0 0x00 Disables External Clocking 0x80 Not Gated CLK SRC GLBn will be inputted outputted independent of the CLK GBLn corresponding gate value 0x81 Clock Gated High CLK SRC GLBn will be inputted when the CLK GBLn corresponding gate value is high this doesn t affect when outputting a clock 0x82 Clock Gated Low CLK_SRC_GLBn will be inputted when the CLK GBLn corresponding gate value is low this doesn t affect when outputting a clock RTD Embedded Technologies Inc www rtd com 52 DM35425HR User s Manual Q Accessing the Analog World 7 Calibration This section describes how to calibrate the DM35425HR using the trimpots on the module The trimpots calibrate the A D converter gain and offset The D A converter does not need to be calibrated The offset and full scale performance of the module s A D converter is factory calibrated Any time you suspect inaccurate readings you can check the accuracy of your conversions using the procedure in this section and make adjustments as necessary Calibration is done with the module installed in your system Power up the system and let the DM35425HR circuitry stabilize for 15 minutes before calibration 7 1 Required Equipment The following equipment is required for calibration e Precision voltage source 10 to 10 V e Digital voltmeter 5 digits e Small screwdriver for trimpot adjustment The
14. 7 4 Status o Ox08 Uninitialized The status when in the Uninitialized mode and the converter requires initialization o 0x09 Initializing o 0x00 Stopped The status when in the Reset mode or in the Uninitialized mode and the converter does not require initialization o 0x01 Filling Pre Trigger buffer o 0x02 Waiting for start trigger o 0x03 Sampling Waiting for stop trigger o 0x04 Filling Post Stop buffer o 0x05 Wait to re arm Waiting until local FIFO is empty so the pre trigger buffer can be filled o 0x07 Done capturing 6 5 5 CLK_SRC READ WRITE Selects the source for CLK_DIV from the clock bus Refer to Clock Source on page 30 for list of valid values 6 5 6 START TRIG READ WRITE Selects the start trigger from the clock bus CLK DIV will start counting after the start trigger Refer to Clock Source on page 30 for list of valid values 6 5 7 STOP TRIG READ WRITE Selects the stop trigger from the clock bus Refer to Clock Source on page 30 for list of valid values 6 5 8 CLK DIV READ WRITE Divider for the pacer clock Pacer Clock Frequency CIk Src Frequency 1 CLK DIV If synchronizing with the pacer clock from another Function Block by using one of the CLK GBL signals this is typically set to 0 NOTE The max clock frequency for the ADIO FB is 4 MHz CLK DIV needs set to a minimum of 9 for this FB to work properly 6 5 9 CLK DIV CNTR READ ONLY The current value of
15. Buffer Filled B3 Start Trigger B4 Stop Trigger B5 Post Stop Buffer Filled B6 Sampling has completed and the FIFO is empty all data transferred to host B7 Pacer The pacer clock has ticked B8 CN3 5V Over Current B9 CN4 5V Over Current 6 9 15 CLK SRC GBLN NOTE If a CLK SRC GBL is unassigned in all function blocks it defaults to System Clock Immediate Selects the source to drive onto Clock Bus signal N B 7 0 0x00 Disables Clock Source 0x80 Sample A sample has been taken 0x81 Advanced Int 0x82 Pre Start Buffer Filled 0x83 Start Trigger 0x84 Stop Trigger 0x85 Post Stop Buffer Filled 0x86 sampling has completed and the FIFO is empty all data transferred to host RTD Embedded Technologies Inc www rtd com 48 DM35425HR User s Manual Q Accessing the Analog World 6 5 16 DIO INPUT READ ONLY This register provides the current value on the Digital I O lines regardless of pin direction The bits in the register correspond with the Digital I O pins as follows This is the same value that is written to the DMA INPUT FIFO When P BUS EN is enabled and the P_BUS_CLK pin direction is set to high this Register and DMA INPUT FIFO will only be updated when receives a high clock pulse and P_BUS_VALID is high t CN3 Pin Signal Name Number P_BL BUS EN ELI FRI A 4 N 1 NI C IG EN f JO LIN T U L IA PAI r In a pa I TN Der IQ IN A ALLIN G
16. CNT READ ONLY Total number of conversions This only increment in while in Converting Waiting for stop trigger and Output Post Stop buffer state It also continues counting after a Re Arm RTD Embedded Technologies Inc www rtd com 43 DM35425HR User s Manual Q Accessing the Analog World 6 4 12 INT ENA MASKABLE READ WRITE Each bit corresponds to an interrupt source value of 1 enables the source and a value of 0 disables it See below for a description of the sources 6 4 13 INT STAT READ CLEAR Each bit corresponds to an interrupt source Reading a value of 1 indicates that an event has occurred Reading a value of 0 indicates that the event has not occurred Writing a 1 will clear that bit B 0 Conversion A value has been sent B 1 Channel Marker One of the channels has an enabled marker B 2 Reserved B 3 Start Trigger B 4 Stop Trigger B 5 Post Stop Conversions Completed 6 4 14 CLK_SRC_GBLN NOTE If a CLK_SRC_GBL is unassigned in all function blocks it defaults to System Clock Immediate Selects the source to drive onto Clock Bus signal N Values are B 7 0 Clock Source Select 0x00 Disable Clock Source 0x80 Conversion A value has been sent 0x81 Channel Marker One of the channels has an enabled marker 0x82 Reserved 0x83 Start Trigger 0x84 Stop Trigger 0x85 Post Stop Conversions Completed 6 4 15 CH FRONT END C
17. DIO23 24 DIO31 DIO23 123 DIO31 26 DO 30 DOZ Do 31 132 DIO DIOf9 DiOf8 38134 X DIO 34 DIO 36 DIO25 38 DIO24 DOM EXT CLK GATE2 3040 GND EXT CLK GATE EXT CLK GATE3 41 42 EXT CLK GATE4 12 EXT CLK GATE4 EXT CLK GATES 43 44 EXT CLK GATE6 _ EXT CLK GATES 43 44 EXT CLK GATE6 EXT CLK GATE 45 Reserved 47 48 5V Other Connectors CN5 and CN6 are for Factory Use only 3 3 3 JUMPERS There are no jumpers on the board RTD Embedded Technologies Inc www rtd com 16 DM35425HR User s Manual JUI Accessing the Analog World 3 4 Steps for Installing Always work at an ESD protected workstation and wear a grounded wrist strap Turn off power to the PC 104 system or stack Select and install stand offs to properly position the module on the stack Remove the module from its anti static bag Check that pins of the bus connector are properly positioned Check the stacking order make sure all of the busses used by the peripheral cards are connected to the cpuModule Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack Gently and evenly press the module onto the PC 104 stack 9 If any boards are to be stacked above this module install them 10 Attach any necessary cables to the PC 104 stack 11 Re connect the
18. RTD Embedded Technologies Inc www rtd com 59 DM35425HR User s Manual RTD Embedded Technologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com Represents all cpu s pre In systems capable of hotp as new cpu s are detected method such as ACPI for ud cpumask t cpu present map EXPORT SYMBOL cpu present i mA ifndef CONFIG SMP Represents all cpu s that e gt ee gt cpumask t cpu online map v AS9100 V 180 9001 Copyright 2015 by RTD Embedded Technologies Inc All rights reserved
19. figure below shows the DM35425HR layout with the trimpots located along the top TR2 TR3 TR8 Hi 25 s mag MUI 116 o as SIS UI nn 2 as H 23 ss m Ss O THN e a H Ar onn onn www rtd com RTD Embedded Technologies Inc Figure 10 DM35425HR Trimpots RTD Embedded Technologies Inc www rtd com 53 DM35425HR User s Manual Q Accessing the Analog World 7 2 ADC Calibration Two procedures are used to calibrate the ADC for all input voltage ranges The first procedure calibrates the converter for the bipolar ranges 5 10 V and the second procedure calibrates the unipolar range 0 to 10 V Table 25 shows the ideal input voltage for each bit weight for the bipolar ranges and Table 27 shows the ideal voltage for each bit weight for the unipolar ranges 7 2 1 BIPOLAR CALIBRATION Bipolar Range Adjustment 5 to 5 V Two adjustments are made to calibrate the ADC for the bipolar range of 5 to 5 V One is the offset adjustment and the other is the full scale or gain adjustment Trimpot TR4 is used to make the offset adjustment and trimpot TR5 is used for gain adjustment Before making these adjustments make sure that the board is programmed for a range of 5 V Use AINO and set it for a gain of 1 while calibrating the board Connect you precision voltage source to AINO Set the voltage source to 1 22070 mV start a conversion and read the resulting data Adj
20. generated each time a sample is taken and the value is above the high threshold or below the low threshold 6 3 21 CHN THRESH LOW READ WRITE Signed 32 bit value indicating the low threshold If the input signal drops below this value an interrupt or clock can be generated until the signal goes above this value The 3 least significant bits are ignored from the actual threshold value RTD Embedded Technologies Inc www rtd com 40 DM35425HR User s Manual Q Accessing the Analog World NOTE The threshold value should not exceed the ADC range If the threshold value exceeds the ADC range unexpected results will occur 6 3 22 CHN THRESH HIGH READ WRITE Signed 32 bit value indicating the high threshold If the input signal goes above this value an interrupt or clock can be generated until the signal goes below this value The 3 least significant bits are ignored from the actual threshold value NOTE The threshold value should not exceed the ADC range If the threshold value exceeds the ADC range unexpected results will occur 6 3 23 CHN LAST SAMPLE READ ONLY The last sample read from the ADC Converter after filtering This is the same value that is written to the DMA FIFO 6 3 24 CH FIFO ACCESS READ WRITE This register provides direct access to the DMA FIFO It can be used to access the data without the use of the DMA engine The DMA engine for this channel must be set to Pause Each register access adva
21. power cord and apply power to the stack 12 Bootthe system and verify that all of the hardware is working properly o NDN ee Goo NS rx Figure 5 Example 104 Stack RTD Embedded Technologies Inc www rtd com 17 DM35425HR User s Manual Q Accessing the Analog World 4 IDAN Connections 4 1 Module Handling Precautions To prevent damage due to Electrostatic Discharge ESD keep your module in its antistatic bag until you are ready to install it into your system When removing it from the bag hold the module by the aluminum enclosure and do not touch the components or connectors Handle the module in an antistatic environment and use a grounded workbench for testing and handling of your hardware 4 2 Physical Characteristics e Weight Approximately 0 33 Kg 0 72 Ibs e Dimensions 151 972 mm L x 129 978 mm W x 34 011 mm H 5 983 in L x 5 117 in W x 1 339 in H Figure 6 IDAN Dimensions 43 Connectors 4 3 1 BUS CONNECTORS CN1 Top amp CN2 Bottom PCle Connector The PCle connector is the connection to the system CPU The position and pin assignments are compliant with the PCI 104 Express Specification See PC 104 Specifications on page 58 The DM35425 is a Universal board and can connect to either a Type 1 or Type 2 PCle 104 connector RTD Embedded Technologies Inc www rtd com 18 DM35425HR User s Manual Q Accessing the Analog World 44 Connectors 4 4 1 EXTERNAL l O CONNECTORS
22. the Clock Divide Counter This counter starts at a value of CLK DIV and counts down When it reaches zero a sample is taken This is useful when using a slow sample clock RTD Embedded Technologies Inc www rtd com 47 DM35425HR User s Manual Q Accessing the Analog World 6 5 10 PRE TRIGGER CAPTURE READ WRITE Number of samples to collect before the Start Trigger The length is limited by the FIFO size writing a value larger than the FIFO size will have indeterminate results 6 5 11 POST STOP CAPTURE READ WRITE Number of samples to collect after the Stop Trigger 6 9 12 SAMPLE CNT READ ONLY Total number of samples collected This only increment while in the Filling Pre Trigger buffer Sampling Waiting for stop trigger and Filling Post Stop buffer state It also continues counting after a Re Arm While in Parallel Mode samples collected is only accurate when P_BUS_ CLK is low 6 5 13 INT_ENA MASKABLE READ WRITE Each bit corresponds to an interrupt source A value of 1 enables the source and a value of 0 disables it See below for a description of the sources 6 5 14 INT STAT READ CLEAR Each bit corresponds to an interrupt source Reading a value of 1 indicates that an event has occurred Reading a value of 0 indicates that the event has not occurred Writing a 1 will clear that bit B0 Sample A sample has been taken B1 Advanced Int B2 Pre Start
23. 0 DAC Data If the current Mode is Reset or the associated DMA engine is set to Clear a write to this register will immediately update the DAC Converter 6 4 20 CH FIFO ACCESS READ WRITE This register provides direct access to the DMA FIFO It can be used to access the data without the use of the DMA engine The DMA engine for this channel must be set to Pause Each register access advances to the next sample RTD Embedded Technologies Inc www rtd com 45 DM35425HR User s Manual Q Accessing the Analog World 65 BAR2 Advanced Digital I O Functional Block This function block is for 32 bi directional digital I O The Advanced Digital I O ADIO Function block has multiple channels There are 3 channels in this functional block IN OUT and DIRECTION Each channel has its own FIFO and DMA channel Table 21 Digital I O Functional Block Offset FB 0x00 FB ID FB 0x04 FB DMA BUFFERS FB DMA CHANNELS FB 0x0C FB 0x28 CLK SRC_GBL3 CLKSRCGB2 Reseved P BUS READY EN FB 0x50 CH FIFO ACCESS DIO IN FB 0x54 CH FIFO ACCESS DIO OUT FB 0x58 CH FIFO ACCESS DIO DIR 65 1 FB ID READ ONLY This is the functional block ID This register should read 0x01003001 for the Advanced Digital I O functional block Digital I O Control Digital I O Channels Digital I O FIFO 6 5 2 FB DMA CHANNELS READ ONLY This register contains the number of DMA Channels in this Function B
24. 0 IDAN DM35425 62 Pin High Density D Connector O A GND N 50 O 6 enn enn CN N N Dog om CNS CN3 CN3 800 DM35425HR User s Manual Q Q Accessing the Analog World P3 Connector 62 pin High Density D Female Connector Connector Part 4 VALCONN HDB 62S Sample Mating Connector VALCONN HDB 62P Table 11 IDAN DM35425 62 Pin High Density D Connector Table 10 IDAN DM35425 62 Pin High Density D Connector IDANPinf Signa DM35425Pm IDANPin Signal DW3SE5Pinf 3 4 13 44 16 3 4 9 3 GND 5 2 3 Reserved 5 4 Reserved 8 4 Reserved 11 1 Reserved 4 13 7 1 GND 0 15 EXT CLK GATES CN4 3 AINI5 AIN23 CNA AGND CM AGND CM DIO CM DIO CM DIO CM DIOBB OM DIOQ25 CM 4 4 5V 48 16 Reserved CN4 6 9 1 Reserved Reserved Reserved Reserved 11 6 14 2 17 2 29 RTD Embedded Technologies Inc www rtd com 22 DM35425HR User s Manual Q Accessing the Analog World 4 5 _ Steps for Installing Always work at an ESD protected workstation and wear a grounded wrist strap Turn off power to the IDAN system Remove the module from its anti static bag Check that pins of the bus connector are properly positioned Check the stacking order make sure all of the busses used by the peripheral cards are connected to the couModule Hold the module by its edges and orient it so the bus connector p
25. 0 Out ADC 12 Bit 1 25 MSPS CHn_Front_End_Config SE_DIFF In this mode your signal source may or may not have a separate ground reference In differential mode the high side input is measured in reference to the low side input In this mode you connect the high side of the input signal to the analog input AINO through AIN16 and connect the low side to corresponding ADC pin In most cases the board ground must still be attached to the device that is generating the input signal When using the differential mode you should install a 10 kQ resistor pack at locations RN2 and RN18 on the DM35425HR to provide a reference to ground for signal sources without a separate ground reference Full Scale Input Range The DM35425 has a programmable gain input per channel This gain can be programed for 1 2 4 8 to achieve input ranges 5V 2 5V 1 25V 0 625V RTD Embedded Technologies Inc www rtd com 25 DM35425HR User s Manual Q Accessing the Analog World The DM35425 also features an attenuator in the front end This allows for additional input range of 10V This feature can only be used in bipolar mode Refer to Table 18 on page 39 for full scale ranges for both unipolar and bipolar modes Bipolar Unipolar Mode In bipolar mode the data is collected in two s complement format In this format the MSB of the data is the sign bit If the MSB is 0 the output data is positive value If the MSB is 1 t
26. 0x81 0x82 Disables Clock Source Sample A sample has been taken Channel Threshold One of the channels has exceeded the High or Low threshold Check the CH THRESH STAT registers Pre Start Buffer Filled RTD Embedded Technologies Inc www rtd com 38 DM35425HR User s Manual Q Accessing the Analog World 0x83 Start Trigger 0x84 Stop Trigger 0x85 Post Stop Buffer Filled 0x86 sampling has completed and the FIFO is empty all data transferred to host 0x87 Pacer The pacer clock has ticked 6 3 16 CHn FRONT END CONFIG MASKABLE READ WRITE Refer to Analog input on page 24 for more information about the front end circuit This provides up to 16 bits to configure the Front End for this ADC Channel to allow adjustment of gains ranges B 7 6 CH DELAY o CH DELAY 1 0 00 No Channel to Channel Delay o CH DELAY 1 0 01 Half Sample Clock Channel to Channel Delay o CH DELAY 1 0 10 Full Sample Clock Channel to Channel Delay o CH DELAY 1 0 11 2 Full Sample Clock Channel to Channel Delay B 5 CH ENABLE 0 Channel Disabled 1 Channel Enabled B 4 2 GAINSEL o GAINSEL 2 0 000 Gain of 1 o GAINSEL 2 0 001 Gain of 2 o GAINSEL 2 0 010 Gain of 4 o GAINSEL 2 0 011 Gain of 8 o GAINSEL 2 0 100 Gain of 0 5 B 1 BIP UNI 0 Bipolar operation 1 Unipolar operation B O SE DIFF 0 Single Ended Input 1 Differential Input Table 18 ADC Full Scale
27. 2 FB DMA CHANNELS READ ONLY This register contains the number of DMA Channels in this Function Block Each Channel contains a control register and a set of Buffer Descriptor Registers 64 3 FB DMA BUFFERS READ ONLY This register contains the number of Buffer Descriptors in each DMA Channel 6 4 4 MoDE STATUS READ WRITE READ ONLY Selects the current mode of operation and indicates its triggering status RTD Embedded Technologies Inc www rtd com 42 DM35425HR User s Manual Q Accessing the Analog World B 3 0 Mode o 0x04 Uninitialized This is the power on state No converter initialization has taken place Sampling is stopped and all counters are reset and the triggering state machine is reset Transition to any of the other Modes will start converter initialization Sampling will not start until initialization is complete o 0x00 Reset Sampling is stopped All counters are reset and the triggering state machine is reset o 0x01 Paused Sampling is stopped but the counters and triggering state machine maintain their state o 0x02 Go Single Shot After converting the Post Stop number of values converting stops The Mode must be set back to RESET in order to convert more values o 0x03 Go Re arm After converting the Post Stop number of values the triggering state machine is restarted DAC data is resumed from that last value sent B 7 4 Status o Ox08 Uninitialized The status when in the Uniniti
28. ADV INT MASK Read Write 6 5 21 ADV INT COMP Read Write 6 5 22 ADV INT CAPT Read Write 6 5 23 P BUS EN Read Write 6 5 24 P BUS READY EN Read Write 6 5 25 CH FIFO ACCESS Read Write 6 6 BAR2 External Clocking Functional Block 6 6 1 FB ID Read Only 6 6 2 FB DMA CHANNELS Read Only 6 6 3 FB DMA BUFFERS Read Only 6 6 4 EXT CLK IN Read Only 6 6 5 EXT CLK GATE IN Read Only 6 6 6 EXT CLK DIR Read Write 6 6 7 EXT CLK EDGE Read Write 6 6 8 EXT CLK PWn Read Write 6 6 9 EXT CLKn CFG Read Write RTD Embedded Technologies Inc www rtd com V Q Accessing the Analog World DM35425HR User s Manual 7 Calibration 7 1 FEE QUI DMI NE I E EO E T 7 2 DENN 1 2 1 Bipolar Calibration Bipolar Range Adjustment 5 to 5 V Bipolar Range Adjustment 10 to 10 V Bipolar Range Ideal Bit Weight 1 2 2 Unipolar Calibration Unipolar Range Ideal Bit Weight 1 2 3 Gain Adjustment T 3 PGS UIE UO TT n F l a tk a tek ne ab a tak ak ab kb EEA 8 Troubleshooting 9 Additional Information 9 1 PC 104 Specifications a axnanaiainasasasasnananannanananannananananananananannananananaanananaaaanananaaaana 9 2 PCI and PCI Express Specification seen 10 Limited Warranty Table of Figures Figure 1 Channel FFU rmsesesnoronrsroronrsvonesvononrsronesrenanrsnonenrsnanesnenenrsnanesnenenrsnenesnenanesnenesrnnanesnenssrsnenesnenennr FOUR 2 TG UO ONAN EE E MEM ME IMMA
29. GBL7 CLK_SRC_GBL7 CLK_SRC_GBL6 CLK_SRC_GBL5 CLK_SRC_GBL4 Ec S FB 0x30 Reserved FB 0x34 FB 0x38 FB 0x3C FB 0x40 CHO THRESH LOW FB 0x44 CHO_THRESH_HIGH FB 0x48 CHO LAST SAMPLE FB 0x4C CH1 FRONT END CONFIG Maskable register 16 bit FB 0x50 CH1 FIFO DATA CNT FB 0x54 FB 0x58 CH1 THRESH LOW FB 0x5C CH1_THRESH_HIGH FB 0x60 CH1_LAST_SAMPLE ADC Channel 1 ADC Channel 0 ADC Control Header FB 0x34 CHn FRONT END CONFIG Maskable register 16 bit 0x18 n 0x18 n 0x18 n 0x18 n 0x18 n 0x18 n FB 0x334 CH FIFO ACCESS ADC Channel 0 FB 0x338 CH FIFO ACCESS ADC Channel 1 FB 0x334 CH FIFO ACCESS ADC Channel n 0x04 n ADC Channel FIFO ADC Channel n 6 3 1 FB ID READ ONLY This is the functional block ID This register should read 0x01031000 for the ADC functional block RTD Embedded Technologies Inc www rtd com 36 DM35425HR User s Manual Q Accessing the Analog World 6 3 2 FB DMA CHANNELS READ ONLY This register contains the number of DMA Channels in this Function Block Each Channel contains a control register and a set of Buffer Descriptor Registers 6 3 3 FB DMA BUFFERS READ ONLY This register contains the number of Buffer Descriptors in each DMA Channel 6 3 4 MODE_STATUS READ WRITE READ ONLY Selects the current mode of operation and indicates its triggering status B 3 0
30. I JOD P BUS CLK P BUS READY P BUS VALID P BUS DATA28 DIO9 gt DIO8 P BUS DATA8 DIO7 P BUS DATA7 25 DIO6 IP BUS DATA6 37 DIOO PBUSDATA0 6 5 17 DIO OUTPUT READ WRITE The last value sent to the Digital I O Output If the current Mode is Reset or the associated DMA engine is set to Clear a write to this register will immediately update the Digital I O Output Bit assignments are the same as above When P BUS EN is enabled B 31 29 Reserved B 28 0 P BUS DATA 6 5 18 DIO DIRECTION READ WRITE The last value sent to the Digital I O Direction If the current Mode is Reset or the associated DMA engine is set to Clear a write to this register will immediately update the Digital I O Direction Bit assignments are the same as above Selects the direction of the I O bit 0 input 1 output All pins default to inputs at power up When P BUS EN is enabled B 31 P BUS CLK When set high data in the Digital O DMA OUTPUT FIFO and high clock pulse 50ns will be sent every Digital I O pacer clock When set low DIO INPUT Register and DMA INPUT FIFO will be updated every high clock pulse received B 30 P BUS READY When set high this will output high ready signal once the Digital I O DMA INPUT FIFO is setup and started When using the module to send data set this bit low to receive the ready signal RTD Embedded Technologies Inc www rtd com 49 DM35425HR User s Manual Q Acce
31. NE FIGUR BNP Figure 4 Board Connections eterne dik kav aaa i ak kb kana ka dE su kosa Figure 5 Example 104 Stack tnnt nnn nnn nnns Figure 6 IDAN Dimensions cccccecsscessssscsssscsesscsscsssesessesecsesacsesscsessesacsesaesecsesaesesaeseseesacsesacseseesaseesansess Figure 7 Example IDAN Bo ENN menue Posi ios o ee neers tet tee Serene inn a n Erud tee DEED Figure 8 DM35425 Block Diagram eese nennen tnnt nnne Figure 9 Filter Response with each ORDER Value sese Figure 10 DIMI 942 SA FE l ANN POUS denda ktm Ra eara tl p Re ER eR a RD eer i ett Table of Tables Table 1 Ordering Options eese nennen nn nnn nnn nnne nina natns Table 2 Operating Conditions eese nnne rnnt nnn nnne nnn nennt nnns Table 3 Electrical Characteristics run kase etan event eh needed Table 4 CN3 Differential Mode Pin 0ut osasnaronrsreronrsreresrrerrsrenenrrvenesrenanrsnenesrenenrsnenasrrnenesrenasssvensssenennn Table 5 CN3 Single Ended Mode Pin o0ut asaanasaiaaaanasasaasanansaasananaaaauananaaanananaaaaanaaaaaaanaaaaaaaanaaa Table 6 CN4 Differential Mode Pin out aiaiasaananasaasanansaananananaananananaananannaaanananaaananaaaaaaanaaaaaaaanaaa Table 7 CN4 Single Ended Mode Pin out sse tnn nnn nnns Table 8 IDAN DM35425 68 Pin Subminiature D Connector
32. ONFIG MASKABLE READ WRITE This provides configuration to the Front End for this DAC Channel to allow adjustment of gains ranges B 2 DAC ENABLE 0 Output Disabled 1 Output Enabled B 1 DABIP UNI 0 Unipolar operation 1 Bipolar operation B 0 GAIN 0 Gain of 1 1 Gain of 2 Table 20 DAC Full Scale Settings GER NOTE The Front End may take up to 100us to settle after writing to this register 6 4 16 CHN FIFO DATA CNT READ This register shows the current sample count that is available in the DAC channel FIFO RTD Embedded Technologies Inc www rtd com 44 DM35425HR User s Manual Q Accessing the Analog World 6 4 17 CH MARKER STAT READ CLEAR This is the status register for the Data Markers Reading a 1 indicates that the Data Marker has been asserted Writing a 1 will clear the bit The upper eight bits of the DAC value can be used for Markers These Markers can be used to generate an interrupt when a certain part of the waveform is sent to the DAC This allows an automated indication to the application software as to the state of the data being sent to the DAC Marker bit 7 corresponds to bit 31 of the DAC data and Marker bit 0 corresponds to bit 24 of the DAC data 6 4 18 CH MARKER ENA READ WRITE These are interrupts enables for the Data Markers Bit defines are above 6 4 19 CH LAST CONVERSION READ WRITE The last value sent to the DAC Converter B 31 24 DAC Markers B 12
33. PLE Read Only 6 3 24 CH FIFO ACCESS Read Write 6 4 BAR2 DAC Functional Block sse 6 4 1 FB ID Read Only 6 4 2 FB DMA CHANNELS Read Only 6 4 3 FB DMA BUFFERS Read Only 6 4 4 Mode_Status Read Write Read Only 6 4 5 CLK_SRC Read Write 6 4 6 START_TRIG Read Write 6 4 7 STOP_TRIG Read Write 6 4 8 CLK_DIV Read Write 6 4 9 CLK_DIV_CNTR Read Only 6 4 10 POST STOP CONVERSIONS Read Write 6 4 11 CONVERSION CNT Read Only 6 4 12 INT ENA Maskable Read Write 6 4 13 INT STAT Read Clear 6 4 14 CLK SRC GBLn 6 4 15 CH FRONT END CONFIG Maskable Read Write 6 4 16 CHn FIFO DATA CNT Read 6 4 17 CH MARKER STAT Read Clear 6 4 18 CH MARKER ENA Read Write 6 4 19 CH LAST CONVERSION Read Write 6 4 20 CH FIFO ACCESS Read Write 6 5 BAR2 Advanced Digital I O Functional Block 6 5 1 FB_ID Read Only 6 5 2 FB_DMA_CHANNELS Read Only 6 5 3 FB_DMA_BUFFERS Read Only 6 5 4 Mode_Status Read Write Read Only 6 5 5 CLK_SRC Read Write 6 5 6 START_TRIG Read Write 6 5 7 STOP_TRIG Read Write 6 5 8 CLK_DIV Read Write 6 5 9 CLK_DIV_CNTR Read Only 6 5 10 PRE TRIGGER CAPTURE Read Write 6 5 11 POST STOP CAPTURE Read Write 6 5 12 SAMPLE CNT Read Only 6 5 13 INT_ENA Maskable Read Write 6 5 14 INT STAT Read Clear 65 15 CLK SRC GBLn 6 5 16 DIO INPUT Read Only 6 5 17 DIO OUTPUT Read Write 6 5 18 DIO DIRECTION Read Write 6 5 19 ADV INT MODE Read Write 6 5 20
34. SZSPid 1 1 1 AIN13 AIN29 CN4 AIN14 AIN22 4 AINT4 AIN30 CN4 AINISJAINS1 CN4 CN4 CN4 1 CN4 1 1 CN4 1 CN4 CN4 CN4 CN4 CN4 CN4 CN4 CN4 CN4 CN4 CN4 CN4 CN4 CN4 CN4 N4 2 2 2 2 2 2 2 2 2 2 34 0 1 2 9 6 7 8 CM 9 CM 0 CM CM 2 CM 3 CM 4 CM 5 po com 6 CM 7 ON 8 OM 9 OM 0 CM CM 2 CM 3 CM 1 3 3 3 3 po 8 o n RTD Embedded Technologies Inc www rtd com 20 Accessing the Analog World Sample Mating Connector Amp 786090 7 IDC Crimp Table 8 IDAN DM35425 68 Pin Subminiature D Connector IDAN Pin Signal DM35425 Pin N 39 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 99 06 57 58 62 63 65 67 s 5 N C NO f n N C NC n NC n NIC EM Ne f n N C NC NC T D V D C C C C C C C C C 6 C C 6 N N N N N N N NC N N N N N N DM35425HR User s Manual Q P2 Connector 62 pin High Density D Female Connector ne Connector Part VALCONN HDB 62S Table 10 IDAN DM35425 62 Pin High Density D Connector IDANPiK Signa DMSSESPRE EXT CLK 5 CN CN3 RTD Embedded Technologies Inc www rtd com 21 Accessing the Analog World 5 117 in Sample Mating Connector VALCONN HDB 62P Table 1
35. Scale Analog Output Voltage G 1 8 amp 409186 RTD Embedded Technologies Inc www rtd com 10 DM35425HR User s Manual Q Accessing the Analog World Table 3 Electrical Characteristics Resolution Relative Accurac Gain Error Settling Time Slew Rate Output Impedance Mi InputHigh Voltage J Vw InputLowVoltage P SV Output CNS CNA REN aS p Output Current NENNEN Digital I O RTD Embedded Technologies Inc www rtd com 11 DM35425HR User s Manual Accessing the Analog World 2 2 1 ANALOG INPUT FFT PLOTS In Figure 1 a coherent 10 kHz sine wave signal was attached to input Channel 0 in the 5V Single ended mode The FFT absolute value was Calculated using 8192 data sample ADC Noise Floor ALL m ly I T All m yi Uli M Hl l dad Li m MIMI at li nhi M m TNT tg m fiw Ma MM Jill 300 400 Frequency kHz Figure 1 Channel FFT 2 2 2 ANALOG INPUT HISTOGRAMS In Figure 2 you can see a histogram of samples from sampling a grounded input in 10 V differential input range The number of samples is 32768 Frequency Figure 2 Histogram RTD Embedded Technologies Inc www rtd com DM35425HR User s Manual Q Accessing the Analog World 3 Board Connection 3 1 Board Handling Precautions To prevent damage due to Electrostatic Discharge ESD keep your board in its antistatic bag until you are ready to instal
36. TS r UNI E 99 1 a 0 2 5V 1 28V ot 8 01 250 0 625V NOTE The Front End may take up to 800ns to settle after writing to this register 6 3 17 CHN_FIFO_DATA_CNT READ This register shows the current sample count that is available in the ADC channel FIFO 6 3 18 CHN FILTER READ WRITE The programmable digital filter provides a single pole Infinite Impulse Response IIR filter on each channel This a unity gain filter The filtered data has a value of Dn 1 x 20RDER 1 NewSample Dn JORDER RTD Embedded Technologies Inc www rtd com 39 DM35425HR User s Manual Q Accessing the Analog World The response of the filter is shown in the Figure 9below The Table below shows the 3dB cutoff for each of the filter settings Both the figure and the table are relative to the sample rate fs 0 Filter Gain dB 0 0001 0 001 0 01 0 1 1 Frequency Relative to FS Figure 9 Filter Response with each ORDER Value 0 114791 f 0 045995 f 7 6 3 19 CHN_THRESH_STAT READ CLEAR This is the status register for the Threshold Detection Reading a 1 indicates that the threshold has been crossed Writing a 1 will clear the bit BO 1 Low Threshold has been crossed B1 1 High Threshold has been crossed 6 3 20 CHN THRESH ENA READ WRITE This is the interrupts enable for the threshold detection Bit defines are above An interrupt is generated if not already
37. alized mode and the converter requires initialization o 0x09 Initializing o 0x00 Stopped The status when in the Reset mode or in the Uninitialized mode and the converter does not require initialization o 0x01 Reserved o 0x02 Waiting for start trigger o 0x03 Converting Waiting for stop trigger o 0x04 Output Post Stop buffer o 0x05 Wait to re arm o 0x07 Done capturing 6 4 5 CLK SRC READ WRITE Selects the source for CLK DIV from the clock bus Refer to Clock Source on page 30 for list of valid values 64 6 START TRIG READ WRITE Selects the start trigger from the clock bus CLK DIV will start counting after the start trigger Refer to Clock Source on page 30 for list of valid values 6 4 7 STOP TRIG READ WRITE Selects the stop trigger from the clock bus Refer to Clock Source on page 30 for list of valid values 6 4 8 CLK DIV READ WRITE Divider for the pacer clock Pacer Clock Frequency CIk Src Frequency 1 CLK DIV If synchronizing with the pacer clock from another Function Block by using one of the CLK GBL signals this is typically set to 0 6 4 9 CLK DIV CNTR READ ONLY The current value of the Clock Divide Counter This counter starts at a value of CLK DIV and counts down When it reaches zero a sample is taken This is useful when using a slow sample clock 6 4 10 POST_STOP_CONVERSIONS READ WRITE Number of conversions to send after the Stop Trigger 6 4 11 CONVERSION
38. atures e PCle x 1 Interface o Universal Board can be used with a PCle 104 Type 1 or Type 2 host o Dedicated DMA channel per I O for maximum efficiency e Analog inputs o 16 Differential or 32 Single ended analog input channels 1 25 MSPS maximum input sampling rate 12 bits resolution Programmable single ended or differential inputs per channels Threshold detection can generate an interrupt or be used as a start or stop trigger o Configurable IIR filter on each channel e Analog outputs o 4channels high speed o 12 bit D A converters o 6 5 10 amp 10V output ranges o 7 ps full scale settling time e Advanced Digital I O o 32 bit port of digital I O o Bit programmable direction o Advanced digital interrupts o Parallel Bus Mode e External Clocking o Provides 6 external clocking pins that can be used as inputs or outputs o Provides external triggering o External gate for each clock pin O OOO 1 3 Ordering Information The DM35425 is available with the following options Table 1 Ordering Options Part Number _ Description DM35425HR PCle 104 Analog I O dataModule IDAN DM35425HR 62S PCle 104 Analog I O dataModule in IDAN enclosure with 62 pin D Sub Connector IDAN DM35425HR 68S PCle 104 Analog I O dataModule in IDAN enclosure with 68 pin High Density Connector The Intelligent Data Acquisition Node IDAN building block can be used in just about any combination with other IDAN building blocks to create a simple but ru
39. buffer is full If the last buffer is reached and the HALT and LOOP bits are both 0 the DMA engine will loop If the last buffer is reached and the HALT and LOOP bits are both 1 the DMA engine will halt and the Current Buffer will be set to 0 6 2 16 FB DMAM STATN READ CLEAR B0 Used R C DMA engine sets to 1 to indicate that it has completely used this descriptor The driver must clear this bit when it is ready to be used again The DMA engine will set the error bit and PAUSE if it is ready to use this descriptor and the Used bit is set unless the IgnoreUsed bit is set The bits are cleared by writing 0x00 to the byte RTD Embedded Technologies Inc www rtd com 35 DM35425HR User s Manual Q Accessing the Analog World 63 BAR2 ADC Functional Block This Function Block is for an Analog to Digital converter This ADC Function block has multiple channels There are 32 channels in this functional block however all channels must use the same pacer clock Each channel has its own FIFO and DMA channel In the sections below n is used to enumerate the channels of the ADC function block Table 17 Multi Channel ADC Functional Block FB 0x00 FB ID FB 0x04 FB DMA BUFFERS FB DMA CHANNELS FB 0x0C FB 0x10 FB 0x14 FB 0x18 FB 0x1C FB 0x20 INT_ENA Sample Start Stop Threshold Pacer Tick etc FB 0x24 INT STAT FB 0x28 CLK SRC GBL3 CLK SRC GBL2 Reserved n FB 0x2C CLKSRC
40. e cccccescsssscscsesscsssscscsesscscsecscscsesecsesesseseseseesesessesesaesesassesesassesasaesesassesasaesesassesasaseesas 54 Table 24 Data Values for Calibrating Bipolar 20 V Range cccceccsssesssssscsessesssssscscsesecsssssecsesesacsesessesesassesesassesessusesassesesausesassesesausesassesesasensas 54 Table 295 ADC Bit Weights BI NO EEE EEE een e t a eee eee eee ee e kabann 54 Table 26 Data Values for Calibrating Bipolar 20 V Range cccccccscsssscscsssscssssescsssecsssececsesecessesessssesessesesessesesaesesasaesesassesasaesesassesasaeeesassesesaneasas 55 Table 27 ADC Bit Weights Unipolar aiaiaiaiaanasasaasanansaananananananaanauananaaaananannaaananannaaananannaaananannaaananaaaaaananaaauananaaaaaanaaaaaaaanaaaaaaaanaaaaaaaaaaaaaa 55 Table 28 TINN 55 Table 29 DAC Bit VS Sene aan lautan 56 Table 30 Trimpots for Calibrating DAC Gain kon kk tmm 56 Q Accessing the Analog World RTD Embedded Technologies Inc www rtd com vil DM35425HR User s Manual Q Accessing the Analog World 1 Introduction 1 1 Product Overview The DM35425 is a software configurable high speed 12 bit data acquisition module in the PCle 104 format This module provides 16 differential or 32 single ended analog input channels with programmable gain and input ranges The DM35425 also features four 12 bit high speed analog outputs with programmable output ranges and a 32 bit port of digital I O 1 2 Board fe
41. e to have all function blocks start the same time as ADC you would set ADC to drive CLK_GBL2 with its start trigger You would then set all other function blocks to use CLK GBL2 as their start trigger and then start them They will wait for the start trigger on CLK_GBL2 before they actually start Start ADC and all of the function blocks will start with it Below is the list of clock sources and the register value needed to select the source 0x00 System clock immediate 0x01 Never 0x02 CLK GBL2 0x03 CLK GBL3 0x04 CLK GBL4 0x05 CLK GBL5 0x06 CLK GBL6 0x07 CLK_GBL7 0x08 Channel Threshold One of the channels has exceeded the High or Low threshold 0x09 Channel Threshold Inverted All of the channels are within the High and Low threshold Ox0A CLK_GBL2 Inverted 0x0B CLK_GBL3 Inverted 0x0C CLK_GBL4 Inverted 0x0D CLK GBL5 Inverted 0x0E CLK GBL6 Inverted Ox0F CLK GBL7 Inverted RTD Embedded Technologies Inc www rtd com 30 DM35425HR User s Manual Q Accessing the Analog World 6 1 BARO General Board Control The BARO region is a Memory Mapped register space which contains some global registers It also contains a table describing the different Function Blocks of the board and the offsets into BAR2 of the registers for that Function Block For maximum flexibility the driver must read the table in BARO to calculate the offset to each Function Block in BAR2 Table 15 BARO Registers Offset
42. e input ports when an interrupt is generated All values are latched regardless of the ADV INT MASK register or DIO DIRECTION This register can be written to when ADV INT MODE is set to Disabled 6 5 23 P BUS EN READ WRITE The P BUS EN register is used to enable the parallel bus feature of the digital I O 0 Disabled 1 Enabled 6 5 24 P BUS READY EN READ WRITE The P BUS READY EN register is used to enable the parallel bus ready signal check of the digital I O When this bit is enabled the P BUS CLK will not be outputted until P BUS READY is high 0 Disabled 1 Enabled 6 9 25 CH FIFO ACCESS READ WRITE This register provides direct access to the DMA FIFO It can be used to access the data without the use of the DMA engine The DMA engine for this channel must be set to Pause Each register access advances to the next sample RTD Embedded Technologies Inc www rtd com 90 DM35425HR User s Manual Q Accessing the Analog World 6 6 BAR2 External Clocking Functional Block This function block provides an interface to the External Clocking It is used to input or output the source of the CLK SRC GLBn Table 22 External Clocking Functional Block FB 0x00 FB ID e D L FB Ox04 FB DMA BUFFERS FB DMA CHANNELS 6 6 1 FB ID READ ONLY This is the functional block ID This register should read 0x00000002 for the External Clocking functional block 6 6 2 FB DMA CHANNELS READ ONLY Has no DMA cha
43. e stopped but all internal registers maintain their state During PAUSE you will still receive Stat Underflow and Stat Overflow interrupts After PAUSE you may transition to GO or CLEAR 0x03 Halt Buffer has been filled that has the HALT bit set attempted to use a buffer with the Valid bit cleared After HALT you must transition to CLEAR NOTE The DMA engine also writes to this register when a buffer is completed with the HALT bit set or it encounters an invalid buffer When changing this register from the Go to the Clear state be sure to read it back to make sure the DMA engine did not change it to the Halt state 6 2 2 FB DMAM LAST ACTION READ WRITE The DMA Engine writes the value of FB DMAm Action to this register after it has completed the action This indicates to the user that the last command has been processed It specifically aids the transition to the Clear state When transitioning to Clear the user should wait until FB DMAm Last Action indicates that the Clear has been processed before initiating any other Action changes RTD Embedded Technologies Inc www rtd com 33 DM35425HR User s Manual Q Accessing the Analog World The user may also write a value to this register and then poll the register to see when the value changes This method can be used to detect when the DMA engine services the channel without an Action change 6 2 3 FB DMAM SETUP READ WRITE BO IntEna Set to 1 to enable the DMA
44. el sampling The channel delay bits of the CHn FRONT END CONFIG Maskable Read Write register on page 39 provide a way to delay sampling between channels This is used to reduce cross talk between channels Refer to Electrical Characteristics on page 10 to see typical channel to channel cross talk Effective Sampling Rate The DM35425 uses a multiplexed input to allow a max of 32 single end 16 differential channels using one ADC This module burst samples all enabled channels after each pacer clock pulse starting at the first enabled channel and sequentially every enabled channel afterwards Due to RTD Embedded Technologies Inc www rtd com 26 DM35425HR User s Manual Q Accessing the Analog World the multiplexed input the sampling rate is limited to the number of channels enabled and summation of channel delay Refer to the equation below to calculate the max sample rate per channel Equation 1 Max Sampling Rate 1 25MHz M R mr TE ETR PE Aa EET ve Number of Channels Enabled XY Channel Delay 9 4 Analog output The DM35425 feature 4 independent 12 bit analog output channels with individually programmable output ranges of 5V and 10V Each channel supports a maximum update rate 200 kHz and a maximum operating load of 5mA 5 4 1 INITIALIZING THE DAC CONVERTER The following is a list of the typical steps needed to initialize the DAC converter and begin sampling 1 Set the DAC to the Uninitialized state MODE Uninitiali
45. engine to generate interrupts on completion of a buffer B1 ErrintEna Set to 1 to enable the DMA engine to generate interrupts on error B2 Direction Set to 1 to transfer from the board to the PCI bus Clear to 0 to transfer from the PCI bus to the board Note that although the DMA channel always supports both directions the Function Block that the channel is associated with may only support one direction B3 IgnoreUsed Set to 1 to prevent an error condition when accessing a buffer with the Used bit set Examples are continuous output from a DAC or very large Pre trigger buffering using system memory 6 2 4 FB DMAM STAT USED READ WRITE This register is used to determine the source of a DMA interrupt The bits are cleared by writing 0x00 to the byte Stat Used will be set regardless of having ErrintEna set to 1 B0 Used Desc Set to 1 by the DMA engine if it attempting to use a descriptor with the Used bit set 6 2 5 FB DMAM STAT INVALID READ WRITE This register is used to determine the source of a DMA interrupt The bits are cleared by writing 0x00 to the byte Stat Invalid will be set regardless of having ErrintEna set to 1 BO Invalid Desc Set to 1 by the DMA engine if it attempting to use a descriptor with the Valid bit cleared 6 2 6 FB DMAM STAT OvERFLOW READ WRITE This register is used to determine the source of a DMA interrupt The bits are cleared by writing 0x00 to the by
46. es that there are 1020 or more bytes of data available B15 RD EMPTY 1 indicates that the read FIFO is empty RTD Embedded Technologies Inc www rtd com 34 DM35425HR User s Manual Q Accessing the Analog World 6 2 12 FB DMAM WR FIFO CNT READ ONLY B 9 0 This is the amount of space available in the write FIFO in bytes Software can use this to determine when the FIFO is full A value of OX3FC indicated that there are 1020 or more bytes of space available B15 WR_FULL 1 indicates that the write FIFO is full 6 2 13 FB DMAM ADDRESSN READ WRITE This is the 64 bit PCI address for DMA Channel m buffer n It must be double word aligned i e b 1 0 are reserved 6 2 14 FB DMAM SIZEN READ WRITE This is the size in bytes of the buffer for DMA Channel m buffer n It must be an integer number of double words i e b 1 0 are reserved The actual size is FB DMAm SIZEn 4 Bytes The maximum buffer size is 16MB 6 2 15 FB DMAM CTRLN READ WRITE BO Valid Driver sets to 1 to indicate that this contains valid information The DMA engine will set the error bit and halt if it is ready to use this descriptor and it is not valid B1 Halt Driver sets to 1 to halt the DMA engine after this buffer is full B2 Loop Driver sets to 1 to start back at descriptor 0 after this buffer is full This has a higher priority than the HALT bit B3 Interrupt Driver sets to 1 to generate an interrupt after this
47. gged 104 stack This module can also be incorporated in a custom built RTD HIDAN or HiDANplus High Reliability Intelligent Data Acquisition Node Contact RTD sales for more information on our high reliability systems 14 Contact Information 1 4 1 SALES SUPPORT For sales inquiries you can contact RTD Embedded Technologies sales via the following methods RTD Embedded Technologies Inc www rtd com 8 DM35425HR User s Manual Q Accessing the Analog World Phone 1 814 234 8087 Monday through Friday 8 00am to 5 00pm EST E Mail sales Qrtd com 1 4 2 TECHNICAL SUPPORT If you are having problems with you system please try the steps in the Troubleshooting section of this manual on page 57 For help with this product or any other product made by RTD you can contact RTD Embedded Technologies technical support via the following methods Phone 1 814 234 8087 Monday through Friday 8 00am to 5 00pm EST E Mail techsupport rtd com RTD Embedded Technologies Inc www rtd com 9 DM35425HR User s Manual Q Accessing the Analog World 2 Specifications 2 1 Operating Conditions Table 2 Operating Conditions Symbol Parameter Test Condition Min Max Unit Ves SVSupplyVoltage 14751 5 25 V Ves 33V Supply Voliage MAN Veo 12V Supply Voltage pop maj ma vee 12V Supply Volage o mel ma V Operating Temperature o 401 S0 C Ts Storage Temperature
48. he output code is negative The 12 bits of data are sign extended into a 32 bit word before transferring to the FIFO In unipolar mode there is no sign bit since all values are positive When the output code is all 0 the input voltage is 0 volts When the output code is all 1 the input voltage is 10 volts when the gain is set to 1 Voltage values for each bit will vary depending on input range For example if the input is set for 5V the formula for calculating voltage is as follows Input Range Voltage 9 x Conversion Data 1 Voltage 1 x 212 x Conversion Data Voltage 2 44mV x Conversion Data Table 12 ADC Bipolar Code 5 V Input Range Table 13 ADC Bipolar Code 10 V Input Range 4 998 V MSB 0111 1111 1111 LSB MSB 0111 1111 1111 LSB 9 995 V 0 000 V MSB 0000 0000 0000 LSB 0 000 V MSB 0000 0000 0000 LSB 0 00244 V MSB 1111 111 1111 LSB 0 00488 V 1 MSB 1111 111 1111 LSB 5 000 V MSB 1000 0000 0000 LSB 10 000 V MSB 1000 0000 0000 LSB Table 14 ADC Unipolar Code 0 to 10 V Input Range 9 99756 V MSB 1111 1111 1111 LSB 2 500 V d MSB 0100 0000 000 LSB 5 000 V M MSB 0100 0000 000 LSB 5 000 V M MSB 1000 0000 000 LSB 0 000 V M MSB 0000 0000 0000 LSB Channel Delay The DM35425 uses a 32 single ended 16 differential channel multiplexed input when ADC is sampling which iterates through each enabled channels after the pervious channel has finished sampling By default there is no delay between chann
49. implified block diagram of analog input Single Ended Input Mode Differential Input Mode Full Scale Input Range Bipolar Unipolar Mode RTD Embedded Technologies Inc www rtd com ii Q Accessing the Analog World DM35425HR User s Manual Q Accessing the Analog World Channel Delay 26 Effective Sampling Rate 26 5 4 Variae jio et sitt la aw tk 217 9 4 1 Initializing the DAC Converter 27 5 4 2 Simplified block diagram of analog output 27 50 Dresd OE EN 28 DMA 28 Advanced Interrupts 28 Parallel Bus Mode 28 5 6 FN 29 6 Register Address Space 30 Register Types 30 Clock Source 30 6 1 BARO General Board CODD cec cott a a a a a ME MEI ME 31 6 1 1 GBC BRD RST Read Write 31 6 1 2 GBC_EOI Read Clear 31 6 1 3 GBC REV Read Only 31 6 1 4 GBC FMT Read Only 31 6 1 5 GBC PDP Read Only 31 6 1 6 GBC BUILD Read Only 31 6 1 7 GBC SYS CLK FREQ Read Only 32 6 1 8 GBC IRQ STATUS Read Clear 32 6 1 9 GBC DIRQ STATUS Read Clear 32 6 1 10 FBn ID Read Only 32 6 1 11 FBn Offset Read Only 32 6 1 12 FBn Offset DMA Read Only 32 6 2 BAR2 Functional Block Standard DMA ccccccccscsscscsssscsssssscsesecscsesecsesesecsesesscsesesscsesassesesaesesessesasaesesassesesaesesasatasassesasates 33 6 2 1 FB DMAm Action Read Write 33 6 2 2 FB DMAm LAST ACTION READ WRITE 33 6 2 3 FB DMAm Setup Read Write 34 6 24 FB DMAm Stat Used Read Write 34
50. ins line up with the matching connector on the stack Gently and evenly press the module onto the IDAN system If any boards are to be stacked above this module install them Finish assembling the IDAN stack by installing screws of an appropriate length Attach any necessary cables to the IDAN system Re connect the power cord and apply power to the stack Boot the system and verify that all of the hardware is working properly tO oo St RR que cx _ r Figure 7 Example IDAN System RTD Embedded Technologies Inc www rtd com 23 DM35425HR User s Manual Q Accessing the Analog World 5 Functional Description 5 1 Block Diagram The Figure below shows the functional block diagram of the DM35425 The various parts of the block diagram are discussed in the following sections AIN 0 Analog input PGA ECL I AN Q125MSPS MEEMII Input Multiplexer vo PCle x1 a Control Interface With DMA Engine Analog Output gt 12 bit Q A 200KHz I O Connector DIOO DIO31 Figure 8 DM35425 Block Diagram 5 2 Control Interface with DMA Engine The DM35425 features a FPGA with a built in PCI Express interface and DMA engine The FPGA controls all communication between the bus and the control logic on the board The FPGA also features small FIFOs for use with DMA
51. ital I O Connector is a 2 x 25 0 1 spacing right angle connector The pin assignments are shown in Tables below Table 4 CN3 Differential Mode Pin out Table 5 CN3 Single Ended Mode Pin out ANO ANO ANO 12 AN ANT ANT AN 34 AN AN 5 6 AN AN 5 6 ANO ANS ANS ANS 7 8 AN AlN4 AN ANA 9 10 AN2 ANS ANS ANS 11 12 AN3 AN6 ANN ANG 13 14 AN4 ANT 15 16 ANT ANT 15 16 AN AOUT AGND AOUTO 17 18 AGND AOUM AGND AOUT 149120 AGND AGND I AGND AGND AGND DIO7 E DIO15 DIO7 23 DIO15 DIO14 Doc 25 26 DIO DIO13 DIO13 DIO12 29 DIO12 Do EXT CLK EXT_CLK 2 39 EXT CLK 3 41 42 EXT CLK 4 EXT CLK 3 41 42 EXT CLK4 EXT CIK 5 EXLOLK 6 EXT CLK5 48144 EXT CLK 6 EXT CLK 7 45 46 Reserved EXLCLK 7 45 46 Reserved Reserved O N Reserved 47148 v Reserved 49 50 GND Reserved _ 49 50 GND RTD Embedded Technologies Inc www rtd com 15 DM35425HR User s Manual Q Accessing the Analog World Table 6 CN4 Differential Mode Pin out Table 7 CN4 Single Ended Mode Pin out 2 ANG 6 ANIO 10 AIN12 AIN13 11 12 ANS 11 12 ANG A14 13 14 AIN14 gt AN2 M314 ANO 20 AGND AGND
52. l it into your system When removing it from the bag hold the board at the edges and do not touch the components or connectors Handle the board in an antistatic environment and use a grounded workbench for testing and handling of your hardware 3 2 Physical Characteristics e Weight Approximately 55 g 0 12 Ibs e Dimensions 90 17 mm L x 95 89 mm W 3 550 in L x 3 775 in W Figure 3 Board Dimensions RTD Embedded Technologies Inc www rtd com 13 DM35425HR User s Manual UJ Accessing the Analog World 3 3 Connectors and Jumpers AREE TEE bat La ANS t An ALL PIS HH Cr EN Fa Ca Er FG 44 CN3 Analog Digital I O CN3 Analog Digital I O nardi _ jJ uA medl Ld c _ 2l CN1 amp CN2 PCle Connector Figure 4 Board Connections 3 9 1 BUS CONNECTORS CN1 Top amp CN2 Bottom PCle Connector The PCle connector is the connection to the system CPU The position and pin assignments are compliant with the PCI 104 Express Specification See PC 104 Specifications on page 58 The DM35425 is a Universal board and can connect to either a Type 1 or Type 2 PCle 104 connector RTD Embedded Technologies Inc www rtd com 14 DM35425HR User s Manual Q Accessing the Analog World 3 3 2 DM35425 EXTERNAL I O CONNECTORS CN3 amp CN4 Analog Digital I O Connector The Dig
53. lock Each Channel contains a control register and a set of Buffer Descriptor Registers 6 5 3 FB DMA BUFFERS READ ONLY This register contains the number of Buffer Descriptors in each DMA Channel 6 5 4 MODE_STATUS READ WRITE READ ONLY Selects the current mode of operation and indicates its triggering status B 3 0 Mode o 0x04 Uninitialized This is the power on state No converter initialization has taken place Sampling is stopped and all counters are reset and the triggering state machine is reset Transition to any of the other Modes will start converter initialization Sampling will not start until initialization is complete o 0x00 Reset Sampling is stopped All counters are reset and the triggering state machine is reset o 0x01 Paused Sampling is stopped but the counters and triggering state machine maintain their state o 0x02 Go Single Shot After converting the Post Stop number of values converting stops The Mode must be set back to RESET in order to convert more values RTD Embedded Technologies Inc www rtd com 46 DM35425HR User s Manual Q Accessing the Analog World o 0x03 Go Re arm After converting the Post Stop number of values the triggering state machine is restarted ADIO data is resumed from that last value sent NOTE In Parallel Bus Mode unexpected results may occur when setting Mode to GO before setting the VALID CLK and READY bits on both the Transmitter and Receiver B
54. low the operating instructions that are provided by RTD Embedded Technologies acts of God or other contingencies beyond the control of RTD Embedded Technologies or as a result of service or modification by anyone other than RTD Embedded Technologies Except as expressly set forth above no other warranties are expressed or implied including but not limited to any implied warranties of merchantability and fitness for a particular purpose and RTD Embedded Technologies expressly disclaims all warranties not stated herein All implied warranties including implied warranties for merchantability and fitness for a particular purpose are limited to the duration of this warranty In the event the product is not free from defects as warranted above the purchaser s sole remedy shall be repair or replacement as provided above Under no circumstances will RTD Embedded Technologies be liable to the purchaser or any user for any damages including any incidental or consequential damages expenses lost profits lost savings or other damages arising out of the use or inability to use the product Some states do not allow the exclusion or limitation of incidental or consequential damages for consumer products and some states do not allow limitations on how long an implied warranty lasts so the above limitations or exclusions may not apply to you This warranty gives you specific legal rights and you may also have other rights which vary from state to state
55. nces to the next sample RTD Embedded Technologies Inc www rtd com 41 DM35425HR User s Manual Q Accessing the Analog World 6 4 BAR2 DAC Functional Block This Function Block is for a Digital to Analog converter This DAC Function block has multiple channels There are 4 channels in this functional block however all channels must use the same pacer clock Each channel has its own FIFO and DMA channel Table 19 Multi Channel DAC Functional Block Offset FB 0x00 FB ID FB 0x04 FB DMA BUFFERS FB DMA CHANNELS FB 0x28 CLK SRC_GBL3 CIKSRCGBL2 BOOKMARKKTRIG J FB 0x38 CHO FIFO DATA ENT ee FB 0x3C_ CHO MARK_INT_ENA CHO MARK INT STAT Reserved Reserved FB 0x40 Reseved o tf FB 04C CH1_FIFO_DATA CNT gt gt S St FB 0x50 CH1_MARKINT_ENA CH1_MARK_INT_STAT Reserved Reserved FB 0x54 Reseved AAA FB 0x60 CH2 FIIO DATA CNT gt gt FB 0x64 CH2_MARK_INT_ENA CH2 MARK INT STAT Reserved Reserved FB 0x68 Reseved o CH3 FRONT END CONFIG Maskable register 16 bit FB 0x74 ME FB 0x78 CH3 MARK INT ENA CH3 MARK INT STAT Reserved Reserved FB 0X7C nn Q d FB 0x88 CHFIFO ACCESS DACChamel 1 n FB 0x90 CH FIFO ACCESS DAC Channel 3 DAC Control 64 1 FB ID READ ONLY This is the functional block ID This register should read 0x01032000 for the DA functional block 6 4
56. nnels reads 0 6 6 3 FB DMA BUFFERS READ ONLY Has no DMA buffers reads 0 6 6 4 EXT CLK IN READ ONLY This register provides the current value on the External Clocking lines The bits in the register correspond with the External Clocking pins as follows EXT CLK 7 4 4 6 EXTCIKG EXT CLK 5 EXT CLK 4 EXT CLK 3 0 39 2 X EXTCLK2 6 6 5 EXT CLK GATE IN READ ONLY This register provides the current value on the External Clocking Gates lines External Clocking Gates can only be used when inputting an external clock The bits in the register correspond with the External Clocking Gates pins as follows EXT CLK GATE EXT CLK GATES 0139 2 EXT CLK GATE2 6 6 6 EXT CLK DIR READ WRITE Selects the direction of the External Clocking bits 0 input 1 output All pins default to inputs at power up RTD Embedded Technologies Inc www rtd com 51 DM35425HR User s Manual Q Accessing the Analog World 6 6 7 EXT CLK EDGE READ WRITE Selects which edge detect to trigger on This is a bit settable register 0 Rising Edge Detect 1 Fall Edge Detect 6 6 8 EXT CLK PWN READ WRITE This register is used to increase the pulse width of the clock When set to 0x00 the pulse width is high for 25ns By incrementing this register by 0x01 the pulse width stays high for additional 25ns NOTE If EXT CLK PWn is set to be wider than the EXT CLKn CFG Clock Frequency the signal will just stay high
57. on 9 1 PC 104 Specifications A copy of the latest PC 104 specifications can be found on the webpage for the PC 104 Embedded Consortium WWW pc104 org 9 2 PCI and PCI Express Specification A copy of the latest PCI and PCI Express specifications can be found on the webpage for the PCI Special Interest Group www pcisig com RTD Embedded Technologies Inc www rtd com 58 DM35425HR User s Manual Q Accessing the Analog World 10 Limited Warranty RTD Embedded Technologies Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from RTD Embedded Technologies Inc This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period RTD Embedded Technologies will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to RTD Embedded Technologies All replaced parts and products become the property of RTD Embedded Technologies Before returning any product for repair customers are required to contact the factory for a Return Material Authorization RMA number This limited warranty does not extend to any products which have been damaged as a result of accident misuse abuse such as use of incorrect input voltages improper or insufficient ventilation failure to fol
58. programmed properly and has been calibrated for bipolar ranges RTD Embedded Technologies Inc www rtd com 54 DM35425HR User s Manual Q Accessing the Analog World Use AINO and set it for a gain of 1 while calibrating the board Connect your precision voltage source to AINO Set the voltage source to 1 22070 mV start a conversion and read the resulting data Adjust trimpot TR6 until the data flickers between the values listed in the table below Table 26 Data Values for Calibrating Bipolar 20 V Range 0000 0000 0000 ADC Converted Data 0000 0000 0001 Unipolar Range Ideal Bit Weight Below is a table listing the ideal input voltage for each bit weight for the unipolar ranges Table 27 ADC Bit Weights Unipolar O 111111111111 9997 60 0 000000000000 00 7 2 3 GAIN ADJUSTMENT Should you find it necessary to check any of the programmable gain settings the following table will show the proper trimpot to adjust Table 28 Trimpots for Calibrating ADC Gain RTD Embedded Technologies Inc www rtd com DU DM35425HR User s Manual Q Accessing the Analog World 7 3 DAC Calibration The DAC circuit requires gain calibration TR11 TR14 adjust the DAC gain The table below provides for your reference a list of the input bits and their corresponding ideal output voltages for each of the three output ranges Table 29 DAC Bit Weights 100000000000 O 2500 00 0000 00 5000 00
59. rd The configuration space is generally handled by the operating system For more information on how to use the configuration space consult the PC Local Bus Specification Revision 3 0 from the PCI SIG Register Types There are several different types of registers that are referred to in this section A description of each type is below e Read Write Registers The value that is written to this register can also be read back e Maskable Registers This is a 32 bit register that consists of 16 bit data field in the upper word and a 16 bit mask value in the lower word For each bit in the data field it is only written to the register if the corresponding bit in the mask field is 1 e Sticky Registers This is a status read register When bit in this register has a value of 1 a 1 needs written to that bit to reset the register to 0 This is typically used for interrupt status registers e Read Only This register can only be read NOTE Writing to Read Only registers may have unexpected results Clock Source Clock sources can serve as either sample clocks for function blocks or triggers for starting and stopping them Function blocks can drive a CLK_GBLn with a CLK SRC GBLn see the register descriptions for details on the possible values for CLK SRC GBLn and other function blocks then trigger from that clock This is what lets multiple function blocks start at the same time or stop on the same trigger For exampl
60. reased using EXT CLK PWn Read Write on page 52 The following example show to capture ADC samples using an external and the external clocking function block e External Clocking Function Block Setup 1 Set the CLK SRC GLB2 as input EXT_CLK_DIR 2 Set the edge detect of CLK_SRC_GLB2 EXT_CLK_EDGE 3 Set CLK SRC GLB2 clocking method EXT_CLK2_CFG 4 Provide clock on CN3 pin 39 e ADC Function Block Setup 1 Set the ADC to the Uninitialized state MODE Uninitialized 2 Setup the DMA for the channel 3 Setthe input mode CH FRONT END CONFIG 4 Set the start and stop triggers START TRIG STOP TRIG 5 Set the clock source CLK SOURCE CLK GBL2 6 _ Set the sample rate CLK DIV CNTR 7 Setthe Pre and or Post Capture counters PRE TRIGGER CAPTURE POST STOP CAPTURE 8 Set the ADC to the Reset state MODE Reset 9 Start the DMA 10 Start the ADC MODE Go RTD Embedded Technologies Inc www rtd com 29 DM35425HR User s Manual Q Accessing the Analog World 6 Register Address Space The DM35425 FPGA code was built as a modular design which allows each board function to have its own Functional Block FB Each functional block was designed to work independent of each other For this reason we provide individual DMA channels interrupts clocks and FIFOs to each functional block The registers are described by their PCle Base Address Register BAR which is defined in the PCI configuration space for this boa
61. rising edge of each clock pulse data in the OUT FIFO will be outputted on all digital I O set to output The Valid pin is set high when the valid pin is set to an output and the Out FIFO is not empty When the clock pin is set to input when the clock pin receives a rising edge and the valid pin is high all 32 bits on data will be written to the IN FIFO RTD Embedded Technologies Inc www rtd com 28 DM35425HR User s Manual 5 6 Q Accessing the Analog World The Ready pin is set high when the Ready pin is set to output and the IN FIFO is not full External Clocking The DM35425 features an external clocking function block This feature allows the user to input a clock to drive a CLK SRC GLBn signal or output a CLK SRC GLBn signal The CLK_SRC_GLBn are used to drive the CLK_GLBn signal which are part of the FPGA function block Clock Source Clock sources are used as either sample clocks for function blocks or triggers for starting and stopping them There are 6 available CLK GBLn each is associated with a pin on CN3 Each pin can be configured to be either an input or an output As an input to a CLK_SRC_GLBn the max input clock frequency is 1 2 system clock frequency This value can be found in GBC SYS CLK FREQ Read Only on page 32 As an output CLK_SRC_GLBn will generated on the associated pin By default this signal will be a pulse that is high for 25ns when the CLK SRC GLBn signal goes high The width of this pulse can be inc
62. s 2 1 Operating Conditions essere nnne nnne nnne nnn nnne nnns 2 2 ESCH es CAPAC OL SINC bi kan va SSi ti ou e PROS e Det r 2 2 1 Analog Input FFT plots 2 2 2 Analog input histograms 3 Board Connection 3 1 Board Handling Precautions sse 3 2 Physical Characteristics nennen nnne nnn nnns 3 3 Connectors and JUMPESS cccccccccssescsessessseessesesecsssesseseeessesessssesesacsesecsesesaesesassusesaseeses 3 3 1 Bus Connectors CN1 Top amp CN2 Bottom PCle Connector 3 3 2 DM35425 External I O Connectors CN3 8 CN4 Analog Digital I O Connector Other Connectors 3 3 3 Jumpers 3 4 SED TOU ANS LAN M EE EE 4 IDAN Connections 4 1 Module Handling Precautions rnt tette tint eoi 4 2 m eei edis sta 4 3 ello m a H asye 4 3 1 Bus Connectors CN1 Top amp CN2 Bottom PCle Connector 44 COMME GIONS 4 4 1 External I O Connectors P2 Connector 68 pin Subminiature D Female Connector P3 Connector 68 pin Subminiature D Female Connector P2 Connector 62 pin High Density D Female Connector P3 Connector 62 pin High Density D Female Connector 4 5 Steps for Installing Se 5 Functional Description 5 1 PT 22161 ARNAR E A 5 2 Control Interface with DMA Engine 5 3 Analog MN POUN NR ai a kan a ab 9 3 1 Initialization 5 3 2 S
63. ssing the Analog World B 29 P BUS VALID When set high this will output high valid signal once the Digital I O DMA OUTPUT FIFO is setup and started When using the module to receive data set this bit low to receive the valid signal B 28 0 P BUS DATA Sets the direction of the I O bit 0 input 1 output 6 5 19 ADV INT MODE READ WRITE Set the current mode for the advance interrupts B 1 0 Mode o 0x0 Disabled This is the power on state In this mode no advanced interrupts will occur o 0x1 Match A Match interrupt is generated when all un masked bits in the Compare register match the input value of the port This is when the following expression is true DIO INPUT xor ADV INT COMP and not ADV INT MASK 0 o 0x2 Event Mode An Event interrupt is generated when any un masked input port bit changes This is when the following expression is DIO INPUT xor ADV INT CAPT and not ADV INT MASK 1 The ADV INT CAPT register is updated at every advanced interrupt or event 6 5 20 ADV INT MASK READ WRITE This register determines if a bit is checked for the advanced interrupts 0 Bit is used for match event 1 Bit is ignored 6 5 21 ADV INT COMP READ WRITE The compare register is used for the Match interrupt When all selected bits in this register match all selected bits on the DIO INPUT register an interrupt is generated 6 5 22 ADV INT CAPT READ WRITE The Capture register latches th
64. te Stat Overflow will be set regardless of having ErrintEna set to 1 If an overflow occurs the DMA engine will PAUSE BO Overflow R C Set to 1 by the DMA engine if an overflow occurred on the FIFO 6 2 7 FB DMAM STAT UNDERFLOW READ WRITE This register is used to determine the source of a DMA interrupt The bits are cleared by writing 0x00 to the byte Stat Underflow will be set regardless of having ErrintEna set to 1 If an underflow occurs the DMA engine will PAUSE BO Underflow R C Set to 1 by the DMA engine if an underflow occurred on the FIFO 6 2 8 FB DMAM STAT COMPLETE READ WRITE This register is used to determine the source of a DMA interrupt The bits are cleared by writing 0x00 to the byte B0 Buffer Complete R C Set to 1 by the DMA engine when a buffer is filled that has the Interrupt bit set 6 2 9 FB DMAM CURRENT BUFFER READ ONLY This is the ID for the buffer that will be used for the next access The driver may use this to track the progress of the DMA activity This value is displayed in Bytes 6 2 10 FB DMAM COUNT READ ONLY This is the offset in the DMA buffer for the next access The driver may use this to track the progress of the DMA activity This value is displayed in Bytes 6 2 11 FB DMAM RD FIFO CNT READ ONLY B 9 0 This is the amount of data available in the read FIFO in bytes Software can use this to determine when the FIFO is empty A value of OX3FC indicat
65. upt status register for non DMA interrupts Each bit in this register corresponds to one of the Function Blocks bit 0 corresponds to FBO whose ID and OFFSET are at 0x020 etc Bits 60 through 63 are reserved This is a Sticky Register so the driver clears it by writing a 1 to the appropriate bit 6 1 9 GBC DIRQ STATUS READ CLEAR This is a 64 bit interrupt status register for DMA interrupts Each bit in this register corresponds to one of the Function Blocks bit 0 corresponds to FBO whose ID and OFFSET are at 0x020 etc Bits 60 through 63 are reserved This is a sticky register and the driver Clears it by writing a 1 to the appropriate bit 6 1 10 FBN ID READ ONLY This is a 32 bit value that identifies the type of Function Block in slot n 0x01031000 ADC 0x01032000 DAC 0x01003001 Digital I O 0x00010001 External Clocking 6 1 11 FBN OFFSET READ ONLY This is the offset from the beginning of BAR2 that this Functional Block resides in 6 1 12 FBN_OFFSET_DMA READ ONLY This is the offset from the beginning of BAR2 that the Functional Block DMA Registers reside in RTD Embedded Technologies Inc www rtd com 32 DM35425HR User s Manual Q Accessing the Analog World 6 2 BAR2 Functional Block Standard DMA This section describes a standard DMA implementation is used by the Functional Blocks There is a single DMA engine that services all of the DMA channels used by the Function Block
66. uring 6 3 5 CLK_SRC READ WRITE Selects the source for CLK_DIV from the clock bus Refer to Clock Source on page 30 for list of valid values 6 3 6 START TRIG READ WRITE Selects the start trigger from the clock bus CLK DIV will start counting after the start trigger unless PRE TRIGGER CAPTURE is non zero in which case CLK DIV will start counting immediately Refer to Clock Source on page 30 for list of valid values 6 3 7 STOP TRIG READ WRITE Selects the stop trigger from the clock bus Refer to Clock Source on page 30 for list of valid values 6 3 8 CLK DIV READ WRITE Divider for the pacer clock Pacer Clock Frequency CIk Src Frequency 1 CLK DIV If synchronizing with the pacer clock from another Function Block by using one of the CLK GBL signals this is typically set to 0 RTD Embedded Technologies Inc www rtd com 37 DM35425HR User s Manual Q Accessing the Analog World NOTE Pacer Clock Frequency should equal desired sampling rate of enabled channels The max sampling rate can be calculated by using Equation 1 on page 27 6 3 9 CLK DIV CNTR READ ONLY The current value of the Clock Divide Counter This counter starts at a value of CLK DIV and counts down When it reaches zero a sample is taken This is useful when using a slow sample clock 6 3 10 PRE_TRIGGER_CAPTURE READ WRITE Number of samples to collect before the Start Trigger The length is limited by the FIFO size
67. ust trimpot TR4 until the reading flickers between the values listed in the table below Next set the voltage to 4 99878 V and repeat the procedure this time adjusting TR5 until the data flickers between the values in the table below Table 23 Data Values for Calibrating Bipolar 10 V Range 0000 0000 0000 NN 100000000000 ADC Converted Data 44111111 1111 1000 0000 0001 Bipolar Range Adjustment 10 to 10 V To adjust the bipolar 20 V range 10 to 10 V program the board for 10 V input range Then set the input voltage to 5 0000 V and adjust TR2 until the output matches the data in the table below Table 24 Data Values for Calibrating Bipolar 20 V Range ADC Converted Data 0100 0000 0000 Bipolar Range Ideal Bit Weight Below is a table listing the ideal input voltage for each bit weight for the bipolar ranges Table 25 ADC Bit Weights Bipolar 1111 1111 1111 1 1000 0000 0000 5000 00 10000 00 0100 0000 0000 2500 00 5000 00 0010 0000 0000 1250 00 2500 00 0001 0000 0000 625 00 1250 00 0000 1000 0000 312 50 625 00 0000 0100 0000 156 25 312 50 0 000000000000 000 000 7 2 2 UNIPOLAR CALIBRATION One adjustment is made to calibrate the ADC for the unipolar range of 0 to 10 V Trimpot TR6 is used to make the offset adjustment This calibration procedure is performed with the module programmed for a 0 to 10 V input range Before making these adjustments make sure that the module is
68. which is needed for continuous data transfer Each DAC and ADC is provided with its own FIFO and DMA channel allowing them to transfer data independent of one another Each DMA channel can be programmed to transfer data from FPGA to PCle bus or from the PCle bus to the FPGA Each DMA channel also features a 64 bit PCI addressing and can access a maximum 16MB of memory for buffers 9 3 Analog input The DM35425 has 16 differential or 32 single end channel inputs muxed to a single 12 bit SAR ADC converter to provide high speed and high digital resolution of the analog input The ADC converter has a max throughput of 1 25MHz 1 Channel Refer to Equation 1 below to calculate max sampling rate The high input impedance low distortion low noise operation design give you accurate results The DM35425 also provides 12V overvoltage input protection to the analog connector The DM35425 has a programmable input This provides the user the ability to select single ended differential input full scale input range unipolar bipolar input and channel sampling delay RTD Embedded Technologies Inc www rtd com 24 DM35425HR User s Manual Q Accessing the Analog World Each ADC channel supports a 511 sample FIFO for DMA Each sample packed into a 32 bits word 5 3 1 INITIALIZATION There are several steps to initialize the Analog to Digital converter The initialization prepares the converter and the front end to capture samples Following the e
69. xample programs and using the drivers provided by RTD will ensure that these steps are followed in the correct order Initialization of the ADC is performed as follows EEG OU se CM ES A Set the ADC to the Uninitialized state MODE Uninitialized Setup the DMA for the channel Set the input mode CH_FRONT_END_CONFIG Set the start and stop triggers START_TRIG STOP_TRIG Set the clock source CLK_SOURCE Set the sample rate CLK_DIV_CNTR Set the Pre and or Post Capture counters PRE_TRIGGER_CAPTURE POST_STOP_CAPTURE Set the ADC to the Reset state MODE Reset Start the DMA Start the ADC MODE Go 9 3 2 SIMPLIFIED BLOCK DIAGRAM OF ANALOG INPUT The following figure shows the front end circuit for the DM35425 It also shows the names of the FPGA registers in bold and the different ways the front end can be configured for different modes of operation Refer to section 6 3 16 for more information about FPGA registers AINO AINO AINT AIN1 AIN2 AIN2 AIN3 AIN3 AIN28 AIN12 AIN29 AIN 134 AIN30 AIN 14 AIN31 AIN15 Mux Single Ended Input Mode In single ended mode the input signal is measured in reference to the boards GND In this mode the input signal is connected to input AINO through AIN31 and the low side to any of the GND pins available on the Analog Connector Differential Input Mode CHn Front End Config BIP UNI N CHn Front End Config GAINSEL 2 0 To FPGA Data 1
70. zed 2 Setup the DMA for the channel 3 Set the input mode CH FRONT END CONFIG 4 Set the start and stop triggers START TRIG STOP TRIG 5 Set the clock source CLK SOURCE 6 Set the sample rate CLK DIV CNTR 7 Set the Post Capture counter POST STOP CAPTURE 8 Set the DAC to the Reset state MODE Reset 9 Start the DMA 10 Start the DAC MODE Go 5 4 2 SIMPLIFIED BLOCK DIAGRAM OF ANALOG OUTPUT The following figure shows the front end circuit for the DM35425 It also shows the names of the FPGA registers in bold and the different ways the front end can be configured for different modes of operation Refer to section 6 4 15 for more information about FPGA registers CHn Front End Config DABIP UNI Pr ST EIL E F Refout CHn Front End Config i GAIN Offset From FPGA e AOUT Vout DAC 12 Bit CHn Front End Config DAC Enable RTD Embedded Technologies Inc www rtd com 2 DM35425HR User s Manual Q Accessing the Analog World The following table list the key digital codes and corresponding output voltages for the DAC converters DAC Bit Weiaht Supu E MV Ma 100000000000 0 2500 00 0000 00 5000 00 000000000000 5000 00 0 00 10000 00 0 00 Voltage values for each bit will vary depending mode and gain The formula for calculating count value as follows Bipolar Range Unipolar Range Voltage Voltage Gain 5 Gain Count

DM35425 - User`s Manual - RTD Embedded Technologies, Inc.

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