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Stellaris LM3S9D96 Development Kit User`s Manual

Contents

1. 5 4 3 1 Primary EM header 3V 32KHz clock for BT boards an _ gt ks 3 3V 1 CC P2 43 3V Bt p 12 mm J2 SDIO DO B2 02 2 125 INSTALL RESISTOR 7 WHEN 2nd RFMON SDIO MOD MART STS ES E DS 4 LI 1 MODI 5010 D1 B4 D4 MOD1 AUD ANA L MOD1 AUD 2 MODULE NEEDS EON CIK 32KHz Clock 27007 SDIO MOD_SLOWCLK B5 Be 04 05 MODI AUD FSYNC 3 je e MODI SDIO CLK MODI SDIO D2 85 De 06 MOD1 AUD ANA MODI AUD DATA IN 34 SEC MOD R7 0 4MOD1 5010 D3 MOD UART B7 D7 AUD DATA OUT 5 9 D 48 8V MOD1_SDIO_D3 B8 87 x D ps 7 MOD1 AUD DATA OUT ul D 0861 MOD_UART_1X B6 88 4 X 08 DS MOD SLOWCLK 8 0 1 Tour vec i 5 MODI GPIOD Bo Dann Di0 MOD AUD DATA Header 1x6 100 430L GND EN MOD 122 SDA B11 HPA_MB_MODULE_ASSY_RF 8 D11 MOD1_AUD_FSYNC 32 768kHz Header 1x8 100 4301 MODI GPIOT Big B 8 011 512 p c4 MOD 12C SCL Bis 812 RF MODULE PORT
2. 1 2 3 4 5 6 12 Debugger USB Interface 0140 D 5 SN7ALVCI25A aA 54819 0572 R52 13 10K 6 SN74LVC125A 3 3y USB Device Controller 9 8 TDI DBG45V u12 R51 10K Ul4C C70 24 FT TCK STEEN GNSS 6 ADBUSDN ES FTCTDUDI L_5 3V30UT ADBUSI s ADBUS2 2 C67 ABUS a FT_TMS OUTEN 5 0 01UF 7 17 DBGENn 2 3 TMS SWDIO AW USBDP ADBUS6 42 DRCCTTAG ER ADBUS 15 UISA ACBUSO ACBUSI B SN7ALVCI26A ACBUS2 R44 x ACBUS3 3 i SVWUA BDBUSO S VCP TX SWO R3 3 45V 45V BDBUSI 152 10K 5 6 BDBUS2 5 I3D SN74LVC125A ou R39 BDBUS3 SN74LVC125A 5 i 10K Jr BDBUS4 INI E UISB Hve cH 1 5 BDBUSS SN7ALVCI26A 1 5 5 2 EESK BDBUS6 35 117 EEDATA BDBUS7 GND DO 1 1 C TEST 2 l BCBUSO 1 5K 53 XTN gt TDO SWO 24 28 _ XTOUT BCBUS2 55 BCBUS3 _ Ube Holes RESET a SN74LVCI26A CORE RSTOUT PWREN C68 C69 45V 9 27PF 27PF 18 one es 1 1 5 GND VCCIOA GND VCCIOB cn C73 C75 UI4B SN7ALVCI25A GOD ENG 0 1UF 0 1UF 0 1UF 0 1U
3. baa dde elev dee lle 55 Test FON does he o Sta diete ARTE ORE 55 Camera Connector x eins ee ein ied ed ape Pe ne TE 55 5 NV tint ata ators ih let t coe E 55 24 de ettet 55 External Peripheral Interface EPI 8 55 Using the Widget 55 Writing Your Own Stellaris Application 56 endive nae Ante 56 Register Descriptions pan debut eb 57 Loading a New Image to the sn 63 Installing the SoftWafe o aen e heb eie eei E ener Pace d es eux ince uie 64 Modifying the Default Image A EENET EEEE EEN 64 Default FPGA Image 64 EPI Signal Descriptions dti a n ae ee eae eee 66 Component LOCATIONS 67 LUE 68 Appendix
4. CLKO INO CLK2 IN2 CLK3 IN3 CPLD TCK CPLD TMS TP1 TP2 CPLD TDI TDI CPLD 5 3 TMS TPS TDO GNDO0I GNDII GNDI C2 C3 e C7 5 C13 GND2 0 tuF 0 tuF 0 1uF LC4032V 5V U4 l vN vour B8 3 2 GND NR 4JuF TPS73033 GREEN LED SMT Socket 2x17 LCD I F Texas INSTRUMENTS Drawing Title FLASH SRAM LCD IF board for DK LM3S9B96 Page Title LCD Interface Size Document Numbei Rev B B Date 7 18 2009 Sheet 2 o 2 6 Stellaris LM3S9B96 Flash and SRAM Memory Expansion Board 50 July 3 2011 APPENDIX Stellaris LM3S9B96 FPGA Expansion Board This chapter describes the Flash and SRAM memory expansion board for the Stellaris LM3S9B96 LM3S9D96 Development Boards The Flash and SRAM memory expansion board provides a quick start platform to evaluate the capabilities of the Stellaris External Peripheral Interface EPI using the highly integrated DK LM3S9D96 development platform This combination adds full screen motion video to the powerful easy to use StellarisWare amp GUI tools Figure F 1 shows a photo of the Flash and SRAM memory expansion board Figure 1 FPGA Ex
5. Z C50 100 Mil Mask 100 Mil Mask 100MilMask SCLI SCL2 IO 1023 1 13 SNCT SDAI SDA2 28VD 33V IO LO3P 1 A12 e 4 IO LO3N e 04 EN 10K 10 IO VREF 1 VREF2H 4 T 10_L04P_1 A10 RHCLKO E cm 10_LO4N_1 A9 RHCLK1 iducials PCA9306 _ 023 024 LL o any 10_LOSP_1 A8 RHCLK2 5 4 10_LOSN_I A7 RHCLK3 TRDY1 GND VDD ie 10_LO6P_1 A6 RHCLK4 IRDY 1 IO 1063 I AS RHCLKS 10_LO7P_1 A4 RHCLK6 10_LO7N_1 A3 RHCLK7 IO LO8P 1 A2 IO LORN 1 1 IO AO 10_L09P_1 HDC 10_LO9N_I LDCO UIE 10_L10P_1 LDC1 1O_L10N_1 LDC2 IP_LO6N_O GCLK9 35100 4 00144 LOGP 0 GCLKS Uie IP LO3N 0 wan IP LO3P 0 a IO LOIP 2 CSO B IP IO LOIN 2 INIT B CHE XINITB gt IP E IO LO2P 2 DOUT BUSY oe IP 2 10_L02N_2 MOSI CSI_B HE E IO 04 2 D7 GCLK12 1 10_LO4N_2 D6 GCLK13 L D6 IP 10 D5 E IP 10_LOSP_2 D4 GCLK14 IO LOSN 2 D3 GCLKIS RS gt IP IO L07P 2 D2 GCLK2 XVCLKR H LO7N 2 DI GCLKG LD be 56 IP VREF_2 LO8P 2 MO 65 PXLCLK 37 P IO LOSN 2 DIN DO t 5 36 IP LOGN_2 M2 GCLK1 10_LO9P_2 VS2 A19 EN TP8 TES S IP_LO6P_2 RDWR_B GCLKO 10_LO9N_2 VSI AI8 M TP7 PEAT IP LONN 2 VREF 2 10 LIOP 2 0 17 a SMT Socket 2x17 TP6 pea IP LO3P 2 LION 2 CCLK gt LCD VF 185 as 35100 2 06142 1 0K R5
6. 30 EASES PB3 95 P WADCIU EPIZ 2 6 9 PA4 SSIORX 317 PAAISSIORX PBA EPIOS23 02 PAS SSIOTX 21 PASISSIOTX PBS EPIOS22 ae PAG USBEPE CANORX PAG USBOEPEN PBO AVREF lt PBO TXSCK AVREF gt PRAE lt PAT USBPFLT CANOTX PAT USBOPFLT PB7 NMI PB7 NMI use PESEPDS 13 45V PCO TCK gt 50 pQU TCK SWCLK fal lt PDO I2SRXSCK Q 79 n PCI TMS PCI TMS SWDIO PDI PDI DSRXWS 78 12 PDZEPDO PBS EPD2 16 35 PJJ EPIIS PC2 TDI PC2 TDI PD2 EPIOS20 ae 77 13 PD3 EPI21 7 17 34 PES EPIIS 4 PC3TDO PC3 TDO SWO PD3 EPIOS21 PCAEPIO2 25 97 06 18 33 PFA EPII2 D2 PCA EPIOSO2 lt PD4 I2SRXSD r PCS EPIO3 0 pps 98 SDSDSRXMCLES PHI EPIO7 19 32 ul 2 1 1 2 PCO EPIO4 23 RS EPIDSOA pps 299 PH2 EPIO 20 31 PEI EPIO9 4 05 22 pp 100 bp 00 21 B72590D0050H160 B72590D0050H160 22 Fie 0508 pro E C PE gt 3H DEDIEPDA 955 PEI EPIOSO9 PFI PFI TXMCLK LED1 x PEPIS Je 0524 PFI LEDI 35 oo VBUS EM 0825 PEYLEDO PF3 LEDO PBI USBVBUS 1 PEA DSTXWS PEAADC3 PE EPIOSI2 22 Ds PES DSTXSD 3 PES ADC2 PFS EPIOS15 LED2 ae OTGID 2j PEG ADCI 15 PESIADCI A
7. LRSTn 2920 7 SDCSn 0 9 S BACKLIGHT 10 Srg 25 RIS RM RIG C24 Clocking The development board uses 16 0 MHz Y2 crystal to complete the LM3S9D96 microcontroller s main internal clock circuit An internal PLL configured in software multiples this clock to higher frequencies for core and peripheral timing A 25 0 MHz Y1 crystal provides an accurate timebase for the Ethernet PHY 14 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual Reset The RESETn signal into the LM3S9D96 microcontroller connects to the reset switch SW2 and to the ICDI circuit for a debugger controlled reset External reset is asserted active low under any one of the three following conditions Power on reset filtered by an R C network Reset push switch SW2 held down By the ICDI circuit U12 FT2232 U13D 74LVC125A when instructed by the debugger this capability is optional and may not be supported by all debuggers The LCD module has special Reset timing requirements requiring a dedicated control line from the microcontroller Power Supplies The development board requires a regulated 5 0 V power source Jumpers JP34 36 select the power source with the default source being the ICDI USB connector Only one 5 V source should be selected at any time to avoid conflict between the power sources When using USB in Host mode the power source should be set to either ICDI or to EXT if a 5 V p
8. 13 MA4 S29GL064N MADS i4 MAS 64Mbit MAD6 17 MAG MAD7 _ 18 u2 SRAM n 54 A0 MADO T 33V RT Al Dal MADI MA2 en 43 MAD2 2 14 MAD3 10 A3 MA4 1 pos 21 Lata 441 5 pos 152 MADS 0 tuF MAG __43 1 25 MADS MA 22 36 MAD7 E AT 39 A d 9 28 7 gt 9 NC 5 5 27 8 3 A10 NC MAT 26 15 mata 252 NC H6 mats 2 12 NC 29 23 413 NC 30 7 H MAIS 22 37 7 gt 15 NC AL 16 21 38 16 17 _ 20 A17 CERT gt MAI8 19 18 MAIS 18 io Decode Table MA26 6 ipti MA27 30 Device MA 27 26 Description 2 MOEn _ 41 GF FLASH 0X Flash memory MWEn 17 WE SRAM 10 SRAM memory 12 vss 4 4 vss AEC Austin LCD 11 LCD Latch Port TEXAS I 108 Wild Basin Rd Suite 350 CY62158EV30 NSTRUMENTS Austin TX 78746 8Mbit Designer Drawing Title Araldo Cruz FLASH SRAM LCD IF board for DK LM3S9B96 Drawn by Page Title Arnaldo Cruz FLASH SRAM Approved Size Document Number Rev B 0001 B Date 7 21 2009 Sheet 1 of 2 N 6 6 LCD_DECODE CPLD 10 B10 All B11 A12 B12 A13 B13 14 B14 15 15 1
9. AGND TLV320AIC23BPW Analog 3 3V 50mA Power Supply 09 PQILA333MSPQ 5 4 VOUT Indicates factory default jumper position c49 m AS i C53 2 2UF C51 22UF S NSTRUMENTS Drawing Tite 1 N 3S9B96 T M3S9D96 Dev Board Page Title 125 Audio Expansion Board Size g Document Number 1 350896 Date Sheet Rev 6 13 2011 4 of 6 A 2 3 4 5 6 SDRAM Expansion Board 8 SDRAM ADO 23 2 __ 24 4 ADI AD2 255 5 pbo 261 43 7 J12 27 24 8 AD4 ADS 3012 5 Dos 10 ADS ae AD6 31 25 poe fii Abe 29 EP 32 22 boy AD2 28 3 BAO DI3 ADS ERN 27 4 BAIDI4 ADO 1 42 ADS EE ADIO RIE poo 44 AD9 6___ ADIL PRU 45 ADIO 7 Doll L4 jog BAODI3 20 Bao pop 4 DIZ 9 SDCKE BAIDI4 2L pois 20 BADIS 10 Dola 51 433V 1l WEn 9 pois 23 015 12 RASn WEn 16 WE 13 RASH I8 as 14 CASn 17 Gas c62 SDCLK 15 2 2UF Lie SDCLK 38 17 DOMI SDCKE 37 18 AD6 DOMI a DOMH 36
10. D1 RL 1 359896 Header dd LLL LT LLL LLL J6 1 5 R I B20 01 am TEXAS INSTRUMENTS INC 2010 REVC DK LM3S9B96 EM2 S N RFMOD2 I25 m i i e m GND ANAL ANAR GND GND DOUT DIN FSYN CLK VDD VDD CMD CLK 03 02 01 DO GND z ET o 5 ET ee ee we 2 VDD CLK FSYN DIN DOUT GND GND ANAR ANAL GND B2 2007 W3 0 0235 e e 02 FID3 e e e e ale D Bottom Schematics This section shows the schematics for the Flash and SRAM memory expansion board B 2 Expansion Board on page 85 July 3 2011 81 Stellaris LM3S9B96 EM2 Expansion Board 82 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual July 3 2011 83 Stellaris LM3S9B96 EM2 Expansion Board 84 July 3 2011
11. indicates factory default jumper position at GND rem 15 Apr 09 First production release z7 GND E 1 5 06 Jun 11 Add LM3S9D96 variant I TEXAS your VIN Sane INSTRUMENTS 82 GND VDDC stor c 8 mt Drawing Tile 1 M3S9B96 LM3S9D96 Dev Board GND VDDC 00109 0 1UF 22UF pra pA Page Title Micro EPI interface USB and Ethernd U16 Required only for LM3S9B96 LM3S9D96 LM3S9B96 Size Document Number 11 359806 See errata su dn F ate 6 13 2011 VN 1 2 3 4 5 6 433V 433V QVGA LCD Panel dms microSD Card Slot 433V with touch interface 16 ion SIOK 8 bit 8080 mode SDCSn cane d Mi _ mu cm R19 Jo Reset 10K 1 sw2 Tene LED_K 2 PAS SSIOTX RESENS 3 SW B3S1000 100 E PA2 SSIOCLK EWES PES ADCI 3 1 TOUCH XP XR 6 TUE TOUCH YN 1 A YD 7 25
12. 1 012 Dis MOD GPIO2 10000pF TORE tue 5 651 Big 13 o 013 Dia J33 DNI MODI SDIO CLK B15 814 014 015 MOD1 nSHUTD RFMOD1_ ANALOG 1 1 SPI CLK Bie 815 gt 015 D16 ifa MODi SDIO CMD B17 EE 018 017 MOD1 AUD MOD AUD ANA R2 4 SPI MOSI BIB 817 017 MOD UART RIS MODi AUD ANA L3 19 D19 MOD1_nSHUTD 4 3 3V SPI MISO 1 820 819 019 D20 MOD1_GPIO3 B20 020 Header 1x4 100 4301 i T 3 Stellaris LM3S9B96 header 43 3V R13 R12 T J6 ise Sue 83V 1 359896 Header 38 T CC P1 CC P2 100K 50 1 B1 i D1 43 3V 02 49 2 9 ALS MOD GPIOO B2 01 52 J4 MOD1_nSHUTD 9 8 T 3 EPA 10 7 MOD2_GPIO1 MOD UART CTS Bs 82 D D3 RFMOD2 125 MOD UART TX 10 7 04 25 11 6 B3 83 04 MOD2 AUD L 16 1 6 05 16 12 5 MOD I2C SCL SEC MOD SCLK B5 D5 MOD2 AUD CLK za MOD2 GPIO2 12 5 4 E PB2 13 4 AD 120 SCLO B6 85 05 pe MOD2 AUD ANA R MODZ AUD FSYNC 3 MOD2 GPIO3 13 4 2 44 7 14 3 2 SDAO MOD_UART_RX B7 86 06 D7 MOD2 AUD DATA IN 4 SPI MOSI 14 3 PBS 22 E 15 2 MOD_UART_CTS B8 Sr lt p D8 T MOD2 AUD DATA OUT MOD2 OUT 5 je MISO 15 2 z 16 1 SPI 052 MOD UART TX 89 88 4 x 09 e SPI_CS1 16 1 3 3V a 16 28 MOD2_GPIOO Bio 59 5 DDT MOD2 AUD DATA IN 40 1 EPIS 27 B10 4 210 Header 1x6 100 4
13. 19 __ 7 DOMO 15 pow ne 22 20 ADI 333V 433V ADS 30 21 ADO 28 1 ADI 29 22 ADIO 41 TUE 14 ale 1 28 21 3 vss 2 L ce4 c65 c66 27 24 6 vssQ 0 01UF 1 5 1 12 VSSQ 4 32 VSSQ is DFI2A S0DS NSS MT4SLCAMIGA2 EPI Signal Breakout Board Expansion Connector JIS 50 1 1 49 2 X_PCA4 EPIO2 748 3 _ _ 5 47 4 X PGUEPII4 X_PCO EPIO4 46 5 2 X_PCT EPIOS 45 6 24 7 X PDYEPDI 43 8 XPDEPDO 42 9 _ 21 10 X PIEP 40 1l X PM EPDS o 39 12 X PIEP BV 13 X PEMEPDS oXy 37 14 X PE2JEPI24 o ____ 6_ __ 36 15 X PBA EPD3 OQ X PP EPIS 35 16 X PBSEPD2 X 5 34 17 7 o XP 35 18 X_PHOEPIO6 32 19 X PHUEPIO7 X PEUEPIOQ 3l 20 X PH2 EPIOI X PEO EPIOS 30 21 PHS EPHI 29 22 X PHAEPIIO TEXAS E INSTRUMENTS 2 2 Drawing Tile M3S9B96 LM3S9D96 Dev Board i Lage Tuo EPI and SDRAM Expansion Boards DFI2A S0DS Document Number DB LM3S9B96 Date 6 13 2011 Sheets A
14. PU rag TOUCH XN XL 8 PA4 SSIORX YU 9 PE2 EPI24 18 t 10 433V Ys 2v a T PETADCO 19 28 30 3 33S 12 0 01UF 1 R20 LCD RSTn 14 IUD 10K CSn 15 HSTR SPICLK 16 43 3V PB7 NMI gt SPISDI 7 R18 4 WW 12 19 330 100 LDO 20 1MB Serial Flash TA PDO DSRXSCK JEZ LCD DO LCD LDI 21 erial Flas Green Power LCD DI LD2 PDI DSRXWS LD3 23 A LD4 24 PD2 EPDO LD5 25 nHOLD VDD 26 PD3 EPI21 27 nWP ois LD6 28 FLCSn SCK C25 PD4 I2SRXSD LD7 29 0 1UF a 1 8 50 T PDS DSRXMCLK 3226 2 bu 4 PD6 TDI r J W2SX80AVSSIG ND PDT JP28 gt 5 gt LED RII PF3 LEDO HSYNC 42 1 5 330 aay VSYNC 43 T DCLK 24 3 3V User LED 27 x m AVDD LRDn PBS EPI22 JP30 swi LWRn PH6 EPI26 PI User Switch 1 6 SW B3S1000 433V i 029 ale 57 A CAN Transceiver 0 1UF 0 1UF OE 38 TXD 59 PAT USBPFLT CANOTX Us CAN Connector 60 CANH 15 TXD 4 120 pss 1 lt PA6 USBEPE CANORX RXD CANL E 4 34 CANL 3 5 VREF_3 0V RS 2 E T 1 FPC Socket 60 vec 219 OND G VREE S Indicates factory default jumper position POT RIZ 0 1UF PBA ADCIO EPI23 gt L SN65HVDIOS0D 8 TEXAS lt 23 mi INSTRUMENTS Drawing Tile I M3S9B96 LM3S9D96 Dev Board B Page Title LCD CAN Serial Memory User IO Thumbwheel
15. Stellaris LM3S9B96 FPGA Expansion Board Figure F 6 Component Placement Plot for Bottom fe 2070 00 MI CSA m m a eco 2775 00 mild A 430 00 Y 780 00 oe oo gt Schematics This section shows the schematics for the DK LM3S9B96 FPGA memory expansion board 68 m EPI LCD Camera I F on page 70 SRAM Power JTAG on page 71 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual July 3 2011 69 Revision History D 0 Revision Date Description He TIO LOIP 0 A 6 24 2009 Released for manufacturing ug 50 E pa EPH4 116 10 0130 35 2 EPH3 117 162 0 gt 8 19 2009 Changed camera connector 1 to vertical connector 2 Al SDA 4 45 3 _ 122 t0 104p Q G
16. Stellaris amp LM3S9B96 2 Expansion ennt nnne nnns 73 mtm 73 Discus 73 Installation of EM Modules onto the EM2 Expansion 76 Hardware Description ioo sat RE e eee eh E ees qae ee E eruit d 78 eterne pee e Deb ren bed pei Hebe a bh Deer 78 EE 79 2 aia inven ne veu ae 79 2S PEA OT 79 m eee DPI obe ite D Ro 79 SDIO HOACSN 79 EPI Signal Descriptions s eis 79 Component Locations 2 Pe bet ad aet te 81 aat 81 Appendix References cs 87 4 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual List of Figures Figure 1 1 Figure 1 2 Figure 2 1 Figure 4 1 Figure B 1 Figure E 1 Figure E 2 Figure E 3 Figure E 4 Figure F 1 Figure F 2 Figure F 3 Figure F 4 Figure 5 Figure F 6 Figure G 1 Figure G 2 Figure G 3 Figure G 4 Figure G 5 Figure G 6 Figure G 7 Figure G
17. Flash SRAM Schematic 1 on page 48 Page 1 of the schematics shows the EPI connector address latch and memory devices EPI Connector The EPI connector J1 is a 50 pin receptacle with 0 5 mm pitch that plugs into the EPI header on the DK LM3S9D96 board The 32 EPI signals and the 2 1260 signals from the LM3S9D96 are provided on this connector It also provides 5 V for the on board DC regulator Note that not all signals are used in this design July 3 2011 43 Stellaris LM3S9B96 Flash and SRAM Memory Expansion Board 8 bit Latch This 8 bit latch is used to store the lower 8 bits of the address which are transmitted during the address phase of an EPI transfer The EPI must be configured in Host bus 8 mode 0 mode HB8 ADMUX with EPI30 configured as an Address Latch Enable ALE signal to control this latch Flash Memory The Flash memory used is a 64 Mbit 90 nsec Spansion S29GLO64N90TFI040 This 8 16 bit memory is used in 8 bit mode Note that MA27 is used as a chip select signal for this memory SRAM The SRAM used is an 8 Mbit 45 nsec Cypress Semiconductor CY62158EV30LL 45ZSX which is an 8 bit memory Note that 27 and 26 are used as chip selects for this memory Memory This I C serial memory is used for storing configuration data This is a 1 kilobit On Semiconductor memory LCD I F Power Schematic 2 on page 49 Page 2 of the schematics shows the LCD DECODE CPLD LCD interface connector and th
18. JTAG SWD header For users who prefer an external debug interface ULINK JLINK etc with the Connecting an external debugger to the JTAG SWD header development board Debug In Considerations Debug Mode 3 supports board debugging using an external debug interface such as a Segger J Link or Keil ULINK Most debuggers use Pin 1 of the Debug connector to sense the target voltage and in some cases power the output logic circuit Installing the VDD PIN1 jumper will apply 3 3 V power to this pin in order to support external debuggers Debug USB Overview 16 An FT2232 device from Future Technology Devices International Ltd implements USB to serial conversion The FT2232 is factory configured to implement a JTAG SWD port synchronous serial on channel A and a Virtual COM Port VCP on channel B This feature allows two simultaneous communications links between the host computer and the target device using a single USB cable Separate Windows drivers for each function are provided on the Documentation and Software CD The In Circuit Debug Interface USB capabilities are completely independent from the LM3S9D96 s on chip USB functionality July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual small serial EEPROM holds the FT2232 configuration data The EEPROM is not accessible by the LM3S9D96 microcontroller For full details on FT2232 operation go to www ftdichip com USB to JTAG SWD The FT2
19. Points 2 207 2 User LED CON Potentiomete ails An 53355435333 LIEB EE zit LD User Switch 3 00 V Anal send Reference microSD Slot 1 MB Serial Flash Memory 3 5 LCD Touch Panel July 3 2011 9 Overview Development Kit Contents The Stellaris LM3S9D96 Development Kit contains everything needed to develop and run a range of applications using Stellaris microcontrollers DK LM3S9D96 development board 8 MB SDRAM expansion board EPI signal breakout board Retractable Ethernet cable USB Mini B cable for debugger use USB Micro B cable for OTG to PC connection USB Micro A to USB A adapter for USB Host USB Flash memory stick microSD Card 20 position ribbon cable CD containing A supported version of one of the following including a toolchain specific Quickstart guide e Keil RealView Microcontroller Development Kit MDK ARM IAR Embedded Workbench e Sourcery CodeBench development tools Code Red Technologies development tools Texas Instruments Code Composer Studio IDE Complete documentation Quickstart application source code Stellaris Firmware Development Package with example source code 10 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual Block Diagram Figure 1 2 DK LM3S9D96 Development Board Block Diagram 0X0 9 0
20. Potentiometer B Document Number DB LM3S9B96 Date 6 13 2011 Sheets 1 2 3 4 5 6 4 2 3 4 6 1 3 4 3 3V TP3 US 1 60 5 0V PQILA333MSPQ MAY DBG 5V 45V VBUS 4 5 M3V VIN VOUT 2 ON NR 1 LM V DC INPUT 2 2UF 32 zl 5V DC U 2208 pud GND GND J7 5 1 a 0 01UF JP59 3 C34 JP36 alee PJ 002BH SMT ULUR 5 5 E A RS Main 3 3V Supply Power Source Selection 4 3 3V U6 T TPS2051BDBV 4VBUS R23 45V OUT 1 PA6 USBEPE CANORX Le USBOEBE 4 JP37 oc 8 PFLT 6 e USBOPFLT C40 C41 lt PA7 USBPFLT CANOTX EU 22UF 2 2UF 22UF JP38 a C20 C36 R24 2208 10K VBUS Fault Protected Switch 3 3 VREF 3 0V R22 VREF 3 00V DE MES PB6 TXSCK AVREF CATHODE use 35 ILED Li D3 2402 45V NR4018T100M 10uH FYV0704SMTF D4 LM4040B30IDB R25 17 7152 24 VIN Sw 1 e ILED Backlight 3 0V 0 2 Voltage Reference BLON SHDN gt JP39 GND FANS333B R26 C44 C45 C46 2 15 UE TP 7 Indicates factory default jumper position I TEXAS INSTRUMENTS LED Backlight Controller Drawing Tite M3S9B96 LM3S9D96 Dev Board Page Tite
21. and RF ID evaluation modules on the Stellaris DK LM3S9D96 platform Figure G 1 EM2 Expansion Board Features The DK LM3S9B96 EXP FS8 expansion board has the following features 2 sets of EM connectors to support up to 2 RF evaluation modules 1 kilobit of C memory for storing configuration data and Flash and SRAM memory expansion board detection EM digital and analog audio signal headers EM MOD1 SDIO connection headers 32 Khz oscillator for slow clock source to primary Flash and SRAM memory expansion board connector Installation To install the Flash and SRAM memory expansion board on the DK LM3S9D96 development board do the following July 3 2011 73 Stellaris LM3S9B96 EM2 Expansion Board 1 On the DK LM3S9D96 board shown in Figure G 2 on 74 remove any installed board on EPI connector J2 A 2 Onthe DK LM3S9D96 board shown in Figure G 2 confirm that shunt jumpers on JP16 JP31 B are installed to enable the LCD touch screen JP39 C the leftmost jumper indicated should remain uninstalled Figure G 2 Removing EPI Board from DK LM3S9D96 Development Board 74 1 st d 4 1 Remove board C Leave JP39 B Confirm shunt jumpers uninstalled JP16 JP31 installed 3 Place the Flash and SRAM memory expansion board on top of the DK LM3S9D96 board while aligning the male EPI expansion connector on the bottom side of the Flash and SRAM memory expansion
22. board with the female EPI expansion connector on the DK LM3S9D96 development board J2 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual Figure G 3 EM2 Expansion Board Bottom side of EM2 module Male EPI expansion connector gt 2 3 x 4 Press firmly downward until the board snaps in place Figure G 4 Assembled DK LM3S9D96 Development Board with EM2 Expansion Board EM2 Expansion Board 4 5 INSTRUMENTS www ti com stellaris July 3 2011 75 Stellaris LM3S9B96 EM2 Expansion Board Installation of EM Modules onto the EM2 Expansion Board The Flash and SRAM memory expansion board has a primary EM header MOD1 and a secondary EM header MOD2 as indicated on the silk screen see Figure G 5 The secondary EM header is rotated 180 degrees from the primary EM header There are many types of EM modules that can be installed onto the Flash and SRAM memory expansion board See the README First document for the EM module you are installing to determine if there is a specific requirement or recommendation for which header the EM module should be installed in If installing a single module and if there is no specific requirement or recommendation in the module s README First document indicating which slot it should be installed in install the single module into the primary EM header MOD1 To install an EM module into the primary module EM slot of the Flash and SRAM memory expansion board
23. do the following 1 Attach any supplied antennas to the EM module 2 Locate the two 20 pin sockets on the back side of the EM module Note the tab on the side of each of the 20 pin sockets This tab denotes pin 1 and aligns with the 20 pin headers on the Flash and SRAM memory expansion board that contain slots near pin 1 for the tab See Figure G 5 for details Figure G 5 Connecting an EM Module to the EM2 Expansion Board Top side of EM2 expansion board Bottom side of EM module C 1B 189010 94 0 122 PRIMARY EM HEADER f Je MOD L 20 sockets EM module Primary EM header MOD1 20 pin headers Secondary EM header MOD2 20 pin headers 3 Align the two 20 pin sockets on the EM module over the 20 pin headers on the Flash and SRAM memory expansion board that are within the primary EM silkscreen 76 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual 4 Use aslight pressure to seat the EM module firmly on the Flash and SRAM memory expansion board See Figure G 6 on page 77 for fully assembled DK LM3S9D96 board with Flash and SRAM memory expansion board and wireless EM module Figure G 6 Fully Assembled DK LM3S9D96 Board with EM2 Expansion Board and Wireless EM Module Antenna for EM module EM module EM expansion board DK LM3S9D96 board www ti com stellaris Follow these same steps for installing a second module into the secondary EM header location
24. flash memory 80 MHz operation Ethernet USB EPI SAFERTOS in ROM and a wide range of peripherals See the LM3S9D96 Microcontroller Data Sheet order number DS LM3S9D96 for complete microcontroller details The LM3S9D96 microcontroller is factory programmed with a quickstart demo program The quickstart program resides in on chip flash memory and runs each time power is applied unless the quickstart has been replaced with a user program Jumpers and GPIO Assignments Each peripheral circuit on the development board is interfaced to the LM3S9D96 microcontroller through a 0 1 pitch jumper shunt Figure 2 1 on page 14 shows the factory default positions of the jumpers The jumpers must be in these positions for the quickstart demo program to function correctly The development board offers capabilities that the LM3S9D96 cannot support simultaneously due to pin count and GPIO multiplexing limitations For example as configured the board does not support SDRAM and 125 receive microphone or line input functions at the same time The jumpers associated with 125 receive are omitted in the default configuration Table 2 1 lists all features and peripherals that are disconnected in the factory default configuration Using these peripherals requires that other peripherals be disconnected Appendix D Microcontroller GPIO Assignments on page 37 lists alternative jumper configurations used in conjunction with some of the StellarisWare exampl
25. mode Divide system clock by 2 16 Bit data 12 Bit address Use Word Access Mode Use read and write strobe pins Reads take two cycles EPI outputs clock to peripheral Peripheral emits a ready signal Not using frame signal so ignore Not using clock enable so ignore 64kB memory space EPI base address is 0xA0000000 NOTE Ten bits are used for addressing but the EPI controller allocates a 12 bit address space The result is that 0x0A00 0000 is equivalent to 00 0400 0x0A00 0800 and 0x0AO0 Table F 1 FPGA Expansion Board Memory VERSION 000 15 0 Board and FPGA Design Version R 58 SYSCTRL 002 15 0 System Control R W 58 IRQEN 004 15 0 Interrupt Enable R W 59 IRQSTAT 006 15 0 Interrupt Status R W 60 MEMPAGE 008 10 0 Memory Page R W 60 TPAD 00 7 0 Test Pad R W 61 010 3 0 LCD Control Set R W LCTRL 61 012 3 0 LCD Control Clear R W CHRMKEY 022 15 0 Chroma Key R W 62 56 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual Table F 1 FPGA Expansion Board Memory Map Continued VCRM 026 8 0 Video Capture Row Match R W 62 VML 030 15 0 Video Memory Address Low R W 62 VMH 032 4 0 Video Memory Address High R W 62 VMS 034 11 0 Video Memory Stride R W 62 LRM 036 7 0 LCD Row Match R W 62 LVML 040 15 0 LCD Video Memory Add
26. 0 has no effect LTEI LCD transfer end interrupt Set to 1 to clear the corresponding bit Clear the interrupt by setting the corresponding bit to 1 Setting the bit to 0 has no effect LRMI LCD display row match interrupt Clear the interrupt by setting the corresponding bit to 1 Setting the bit to 0 has no effect Memory Page Register The Memory Page register selects to memory page to access 60 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual Test PadRegister The Test Pad register is used to access the on board test pads TP1 TP8 which are connected to unused FPGA pins Table F 6 Test Pad Register TXPAD 0xA000 000A 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 TP8 TP7 TP6 TP5 TP4 TP3 TP2 1 R W R W R W Bit Name Description TP1 TP3 Test Pins 1 3 These are connected to FPGA pins Writing a 1 sets the corresponding test pin output to 1 Writing a 0 sets the corresponding test pint output to 0 Reading these bits returns the value at the corresponding test pin input NOTE The FPGA output driver for these signals is always enabled TP4 TP8 Test Pins 4 8 These are connected to FPGA input pins Writing these bits has no effect Reading these bits returns the value at the corresponding test pin input LCD Control Register The LCD Control register is implemented as a set clear register and contains four bi
27. 01 p ETHERNET PFS f LED2 9 LED USER SWITCH LED ERIAL FLASH SDCARD swiTCH 34 3 2011 Connection Details This appendix contains the connection details for the DK LM3S9D96 development board including the following sections DC Power Jack see page 35 ARM Target Pinout see page 35 DC Power Jack The EVB provides a DC power jack for connecting an external 5 V regulated 5 power source Center Positive The socket is 5 5 mm dia with a 2 1 mm pin ARM Target Pinout In ICDI input and output mode the Stellaris amp amp LM3S9D96 Development Kit supports ARM s standard 20 pin JTAG SWD configuration The same pin configuration can be used for debugging over serial wire debug SWD and JTAG interfaces Table C 1 Debug Interface Pin Assignments Function Pin Number TDI 5 TDO SWO 13 TMS SWDIO 7 TCK SWCLK 9 System Reset 15 VDD 1 GND 4 6 8 10 12 14 16 18 20 No Connect 2 3 11 17 19 Insert Jumper VDD PIN1 Jumper JP57 only when using the development board with an external debug interface such as a ULINK or JLINK July 3 2011 35 Connection Details 36 July 3 2011 Microcontroller GPIO Assignments Table D 1 shows the pin assignments for the LM3S9D96 microcontroller Table D 1 Microcontroller GPIO Assignments LM3S9D96 G
28. 1 0K 24 31 x mis IPIVREF 3 2 MI 2 24 108 Wild Basin Rd ak Wis TEXAS INSTRUMENTS 2 127 IP RERO Austin TX 78746 ds Socket _ al Designer Drawing Title XC3ST00E ATQGI44C aki Amaldo Cruz FPGA board for DK EPI LLBL gt z MMBT3904 Drawn by Page Title M Arnaldo Cruz EPI LCD Camera Approved Size Document Number Rev B 0001 B Date 8 21 2009 Sheet 1 2 VCCO 0 VCCAUX UID VCCO 0 VCCAUX ONES 1 VCCAUX x IO LOIN 3 veco Z 10 MAD2 5 MAD3 vVCco3 VCCINT 3 VCCINT ME 10_LOSP_3 LHCLK2 vcco_2 IO LOSN 3 LHCLKS IRDY2 10_LO6P_3 LHCLK4 TRDY2 1O_LO6N_3 LHCLKS IO LO3P 3 i N IO LO3N 3 10 104 i IO LO4N 3 LECLKI XC3S100E 4TQGI44C 10 L07P NILHCLK6 10_LO7N_3 LHCLK7 10 108 3 MA
29. 2011 15 Hardware Description more than 1 Amp or if the switches thermal limits are exceeded by a device drawing more than 500 mA USBOPFLT indicates the over current status back to the microcontroller The development board can be either a bus powered USB device or self powered USB device depending on the power supply configuration jumpers When using the development board in USB host mode power to the EVB should be supplied by the In circuit Debugger ICDI USB cable or by a 5 V source connected to the DC power jack Note that the LM3S9D96 s USB capabilities are completely independent from the In Circuit Debug Interface USB functionality Debugging Stellaris microcontrollers support programming and debugging using either JTAG or SWD JTAG uses the TCK TMS TDI and TDO signals SWD requires fewer signals SWCLK SWDIO and optionally SWO for trace The debugger determines which debug protocol is used Debugging Modes The LM3S9D96 development board supports a range of hardware debugging configurations Table 2 3 summarizes these configurations Table 2 3 Hardware Debugging Configurations Mode Debug Function Use Selected by 1 Internal ICDI Debug on board LM3S9D96 Default mode microcontroller over Debug USB interface 2 ICDI out to SWD The development board is header used as a USB to SWD JTAG interface to an external target Remove jumpers on TCk TMS TDI TDO and PIN1 3 In from
30. 232 USB device performs JTAG SWD serial operations under the control of the debugger A simple logic circuit multiplexes SWD and JTAG functions and when working in SWD mode provides direction control for the bidirectional data line Virtual COM Port The Virtual COM Port VCP allows Windows applications such as HyperTerminal to communicate with UARTO on the LM3S9D96 over USB Once the FT2232 VCP driver is installed Windows assigns a COM port number to the VCP channel Table 2 4 shows the debug related signals Table 2 4 Debug Related Signals Microcontroller Pin Board Function Jumper Name Pin 77 TDO SWO JTAG data out or trace data out TDO Pin 78 TDI JTAG data in TDI Pin 79 TMS SWDIO JTAG TMS or SWD data in out TMS Pin 80 TCK SWCLK JTAG Clock or SWD clock TCK Pin 26 PAO UORX Virtual Com port data to LM3S9D96 VCPRX Pin 27 PA1 UOTX Virtual Com port data from LM3S9D96 VCPTX Pin 64 RSTn System Reset RSTn Serial Wire Out SWO The development board supports the Cortex M3 Serial Wire Output SWO trace capabilities Under debugger control on board logic can route the SWO datastream to the VCP transmit channel The debugger software can then decode and interpret the trace information received from the Virtual Com Port The normal VCP connection to UARTO is interrupted when using SWO Not all debuggers support SWO See the Stellaris LM3S9D96 Microcontroller Data Sheet for additional information on
31. 30L d n 38 MOD I2C SDA HPA MB MODULE ASSY RF p ED MOD2 AUD FSYNC e 125 HAES MOD2 1 1 12 811 0 EDIZ 88 s MOD 120 SCL RF_MODULE PORT_1A 7013 MOD2_GPIO2 EPIS 38 13 me 9 578 MOD UART RTS SPI 652 Bi4 13 D14 5 35 18 17 10 7 MOD 2 SDA Bip 814 014 pie MOD2 nSHUTD J5 2 5 n 06 11 6 MOD1_GPIOO SPI CLK Bie 815 gt 015 7016 RFMOD2 ANALOG J 07 12 5 MOD1_GPIOt B17 017 MOD2 AUD CLK ila EP109 32 19 EPIOT 18 4 MOD1 GPIO2 SPI MOSI Big 817 D17 DIS MOD UART RTS MOD2 AUD R e us 2 00 14 3 MODI GPIO3 19 818 Dis MOD2_nSHUTD MOD2 AUD ANAL 3 e EP111 15 2 SPI SPI MISO 1 820 D20 MOD2_GPIO3 41 29 22 16 1 MOD2_nSHUTD B20 D20 28 23 Header_1x4_100_430L 27 24 27 26 25 a E RECT_DF12A 50DS Be 100K PED Adapter Board Assignment PED Adapter Board Assignment 2 chip to enable adapterboard auto discovery 43 3V 10K SDIO_CLK R14 15 c5 zB 2 R11 lt 27K lt 27K Merl 1 8 2 0 VCC 7 we 3 Al WP 6 AD 2 SCLO 2 SDIO DO P A 4 A2 SCL 5 1 12 SDAO 4 SDIO_D1 1 LAS EXAS INSTRUMENTS CAT24C01 D3 42 GPIO1 LM3S9B96 2 Adapter Shunt 100 ize Document Number lev DK LM3S9B96_EM2 Monday July 12 2010 Bnet 1 of 1 5 4 3 2 1 Stellaris LM3S9B96 EM2 Expansi
32. 46 129 MADO PCG EPI4 46 5 27 27 2 24 DO 31 MADI MAD5 PC7 EPI5 45 6 PJO EPIIG 16 23 paz 53 MAD2 44 7 PDS EPI21 21 22 pe 535 MAD3 sc l I2CSCL 43 5 2 120 2l a4 pos 38 MAD4 5 12CSDA 42 9 PJ6 EPIB0 ALE MAG 20 40 MADS Al SDA AS do IN R al 5 29 19 A6 pos 52 MADS A 20 28 18 44 MAD7 WP A7 DQ7 8 Ri 0 339 MA9 8 GND 3 8 138 PES EPI2S 7 30 Note R1 is not fitted A9 24 01 37 PEQ EPI24 34 0 poo 52 1 128 8 7 PG7 EPIS1 36 PBA EPI23 33V 12 22 18 35 16 PBS EPI22 41 4 pon 1556 amp 15 PFS EPHS 34 17 7 4 3 pon 39 12 2 33 18 6 MAD6 dra MAIS 2 pais dl 32 19 1 17 MAD7 10K 16 TATS 43 MAQ 9 31 20 2 MADI 48 Aie 1541 1525 33V MAB 30 21 0 MADO MAIS 17 10 29 22 16 is 25 RP 10K MA26 26 28 23 10 MA20 __ 9 27 24 MAZ 10 ang a 726 22 __13 TP8 27 26 DFI2A 50DS CE 294 E MOEn _ 28 GF 10K MWEn I Wr 1 vP 5 BYTE MADO 3 vas MADi 4 37 MAD2 7 MA2 VSS veg MAD3 8 Te C11
33. 8 July 3 2011 DK LM3S9D96 Development Board c cccceceeceeneeeecceeeeeeeeeceaaeeeeeeeesesaeseseaeeeseaeeeseeeeseieeeenaeeeenes 9 DK LM3S9D96 Development Board Block 11 Factory Default Jumper Settings sse ener sene enn 14 ICD Interface ag inen Er en PEE Uv e te Er aere teeta 23 Component Placement Plot for 34 Flash and SRAM Memory Expansion Board sse nene 41 Removing EPI Board from DK LM3S9D96 Development 42 Flash SRAM LCD IF Expansion Board Block Diagram sse 43 Component Placement Plot for Top and 46 EPGAExparisior BOard teste tt M 51 Removing EPI Board from DK LM3S9D96 Development 53 FPGA Expansion Board Block Diagram ssssssssssssseseee seen nennen nennen 54 FPGA Boundary cure De a Ro Dae oce ee du ee 64 Component Placement Plot for nennen nnne nemen ensi nnn nennen 67 Component Placement Plot for 68 EM2 Expansi n Board ote pen e epe ba tenete fen Sad e tert 73 Removing EPI Board
34. 9 S 9 9 9 9 9 9 9 S 9 9 S S OV 99 9999 9 9 S S S S 9 QVGA Color LCD Module Stellaris LM3S9D96 Development Board Development Board Specifications W Board supply voltage 4 75 5 25 from one of the following sources Debugger ICDI USB cable connected to a PC USB Micro B cable connected to a PC DC power jack 2 1 x 5 5mm from external power supply Break out power output 3 3 Vdc 100 mA max July 3 2011 11 Overview Dimensions excluding LCD panel 4 50 x 4 25 x 0 60 LxWxH with SDRAM board 4 50 x 4 25 x 0 75 LxWxH with breakout board Analog Reference 3 0 V 0 2 ROHS status Compliant NOTE When the LM3S9D96 Development Board is used in USB Host mode the host connector is capable of supplying power to the connected USB device The available supply current is limited to 200 mA unless the development board is powered from an external 5 V supply with a 600mA rating 12 July 3 2011 Hardware Description In addition to an LM3S9D96 microcontroller the development board includes a range of useful peripheral features and an integrated in circuit debug interface ICDI This chapter describes how these peripherals operate and interface to the microcontroller Microcontroller Overview The Stellaris LM3S9D96 is an ARM Cortex M3 based microcontroller with 512 KB
35. 96 Flash and SRAM Memory Expansion Board This document describes the Flash and SRAM memory expansion board DK LM3S9B96 EXP FS8 plug in for the Stellaris LM3S9B96 and LM3S9D96 Development Boards This expansion board works with the External Peripheral Interface EPI port of the Stellaris microcontroller and provides Flash memory SRAM and an improved performance LCD interface Figure E 1 Flash and SRAM Memory Expansion Board FLASH SRAM LCD IF Features The DK LM3S9B96 EXP FS8 memory expansion board has the following features B 8 Megabytes of Flash memory 1 Megabyte of SRAM Memory mapped LCD I F for improved LCD performance 1 kilobit of IC memory for storing configuration data Power LED indicator Installation To install the expansion board on the DK LM3S9D96 development board do the following 1 Remove the DK LM3S9B96 EXP FS8 memory expansion board from the antistatic bag 2 Onthe DK LM3S9D96 board remove any installed board on EPI connector J2 July 3 2011 41 Stellaris amp LM3S9B96 Flash and SRAM Memory Expansion Board 3 the DK LM3S9D96 board remove the shunt jumpers on JP16 JP31 and the JP39 headers as shown in Figure E 1 on page 41 Figure E 2 Removing EPI Board from DK LM3S9D96 Development Board 1 iB 5 3 Remove board Remove jumpers 4 Install the two snap in nylon standoffs on mounting holes above the EPI connector J2 Place the expansion board on top
36. CLK4 5 Board width increased by 110mils Added test pads 27 4 PGI EPH4 EPE 1232 0 pant 46 5 PHT EPI27 EPI20 125 TOWRERD Released for manufacturing EPIS 5 45 6 PJO EPIT6 EPIS 125 TO 105 D GCLK6 24 T 21 EPI29 7126 iO LON L CAT24COi 43 8 PD2 EPI20 EPI20 1 128 8 1 I2CSDA 42 9 PJ6 EPI3O EPI30 PXLCLK 1 tig dau 21 10 PUS EPI29 29 28 io 20 1l 2 28 EPIO 29 12 9 EPO 25 TO LOEN ONREF 38 13 25 25 L RSTn TO LOPD dau sv 37 14 2 24 24 PWDN Sern 1 36 15 2 EPI23 XVCLK OLIO PJP EPIT8 16 5 22 22 TO LION SWAP 5 17 EPIT7 Breve 2 18 PHO EPIG EPI6 35100 2 00144 5 2 FID1 FID3 19 EHNE drei R22 2 1p 3 XVCLKR 40 Mil Pad 40 Mil Pad 40MilPad Beene on SI PHEEPI EB 5290 PWDNR 100MiMask 100 Mask 100 PEO EPIB 21 ui d ees e e e 22 PHWEPI0 EPIO gt 10 i PHG EPI26 po IO 101 A16 20E DN m EE U7 kd TO OINAS x 4 8 40 Pad 40 Mil Pad 40 Mil Pad 33V 10 102
37. Debugger Interface ICDI ICDI acts as a USB to the JTAG SWD adaptor allowing debugging of any external target board that uses a Stellaris microcontroller See Debugging Modes on page 16 for a description of how to enter ICDI Out mode Figure 4 1 ICD Interface Out Mode JTAG or SWD connects to the external microcontroller Stellaris MCU Remove jumpers to use ICDI Out Feature LM3S9D96 Dev Board Target Cable selsig FUEUEUEUS Stellaris 3 3V MCU PC with IDE debugger qoe The debug interface operates in either serial wire debug SWD or JTAG mode depending on the configuration in the debugger IDE The IDE debugger does not distinguish between the on board Stellaris microcontroller and an external Stellaris microcontroller The only requirement is that the correct Stellaris device is selected in the project configuration The Stellaris target board should have a 2x10 0 1 pin header with signals as indicated in Table C 1 on page 35 This applies to both an external Stellaris microcontroller target Debug Output mode and to external JTAG SWD debuggers Debug Input mode ICDI does not control RST device reset or TRST test reset signals Both reset functions are implemented as commands over JTAG SWD so these signals are usually not necessary 23 Using In Circuit Debugger Interface 24 July 3 2011 Schematics July 3 2011 This sectio
38. Development Kit User s Manual Memory Map The DK LM3S9B96 EXP FS8 expansion board memory map is shown Table E 1 and Table E 2 shows the LCD Latch register Table E 1 Flash and SRAM Memory Expansion Board Memory Map FLASH OX XXX Flash memory 8 Megabytes R W 0x6000 0000 SRAM 10 XXX SRAM 1 Megabyte R W 0x6800 0000 11 000 LCD latch set R W 0x6C00 0000 ace 11 001 LCD latch clear R W 0x6C00 0001 CD 11 010 LCD command port 0x6C00 0002 11 011 LCD data port 0x6C00 0003 11 110 LCD command port read start R 0x6C00 0006 11 111 LCD data port read start R 0x6C00 0007 a Forreads to the LCD Command and Data Port registers the corresponding LCD Port Read Start register must be read first followed by a 500 nsec delay before reading this register Table E 2 LCD Latch Register Reserved RST YN XN 0 0 0 0 0 R W RW R W The LCD Latch register is implemented as a set clear register To set a bit the corresponding bit must be set when writing to the LCD Latch Set register To clear a bit the corresponding bit must be set when writing to the LCD Latch Clear register XN When clear the L_XN signal is set to clear When set the signal is tri stated This signal is used for the X input to the touchscreen YN When clear the L_YN signal is set to clear When set the L_YN signal is tri stated This signal is used for the Y
39. F 433v 4 4 ROS Channel JTAG SW Debug m 10K Channel B Virtual Com Port TCK TCK ULSD ICI SN74LVC126A 1 50 UMS TMS SWDIO ySW lt PCI TMS IL JTAG SWD In Out 51 e J14 846 SRSTN TDI 9 _ PC2 TDI gt 19 52 17 us T 4 53 11 27 5 SN74LVC125A Indicates factory default jumper position 53 R48 RSTn 9 lt RESETn SRSIN 7 x HN I TEXAS 1854 5 Ra qU ur L INSTRUMENTS VCPTX 3 TMS_SWDIO SN74LVCI25A SN7ALVCI26A 2 5 540 7 PAI UOTX 1 es Drawing Tite M3S9B96 LM3S9D96 Dev Board JPSS pni 23V R50 lt c mum VCPRX 2X10 HDR SHRD TDI g 5 In circuit Debug Interface ICDI ANY 3 m JP56 we Pocument Number DK LM3S9B96 LM3S9D96 Date 6 13 2011 Schematics 32 July 3 2011 Component Locations This appendix contains details on component locations for the DK LM3S9D96 development board including Component placement plot for top Figure B 1 July 3 2011 33 Component Locations Figure B 1 Component Placement Plot for Top BD SDR9B96 BO EPISB96 A av HEADPHONE 29 OyT MICROPHONE 48 LINE IN E 38358525588 12S AUDIO pri P48 c57 652 SRE TEXAS INSTRUMENTS LM3S9D96 DEVELOPMENT BOARD PF2 15
40. FO is 64 elements deep This is contained within the vcapture v and async_fifo_64 v files July 3 2011 65 Stellaris LM3S9B96 FPGA Expansion Board EPI Signal Descriptions Table F 8 provides the EPI module s signal descriptions Table F 8 EPI Signal Descriptions PH1 PHO PC7 PC6 PC5 PC4 PH2 PH3 EPIOS 31 PG7 CLK In EPI Clock EPIOS 30 PJ6 E Out Interrupt Signal to Microcontroller EPIOS 29 PJ5 E RD In EPI Read Strobe EPIOS 28 PJ4 WR In EPI Write Strobe EPIOS 27 PH7 E RDY Out EPI Ready Signal EPIOS 26 PH6 E RSTn In FPGA Reset Signal b PE3 PE2 PB4 EPIOS 25 16 PB5 PD3 PD2 PJ3 E_ADDR 10 1 In EPI Address Bus PJ2 PJ1 PJO PF5 PG1 PGO PF4 EPIOS 15 0 mar EE E DATA 15 0 a Configure as Stellaris GPIO input with negative level sensitive interrupts During power up reset is used for PLL lock status b Configure as Stellaris GPIO output 66 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual Component Locations Figure F 5 shows the details of the component locations from the top view and Figure F 6 shows the details of the component locations from the bottom view Figure F 5 Component Placement Plot for Top _ 20 70 00 gt ome EE 2775 00 Cmil gt A NO 430 00 k 280 00 mil EM 00 9 July 3 2011 67
41. FPGA is an optional expansion board which connects directly to the External Peripheral Interface EPI port of the Stellaris DK LM3S9D96 development board to demonstrate the machine to machine M2M high bandwidth parallel interface capability of the Stellaris microcontroller Right out of the box users are able to control and display the FPGA expansion board s video on the DK LM3S9D96 development board s large 3 5 touchscreen display For more information on the FPGA Expansion Board sold separately see Appendix F Stellaris LM3S9B96 FPGA Expansion Board on page 51 EM2 Expansion Board The EM2 Expansion Board DK LM3S9B96 EM2 is an optional expansion board which connects directly to the External Peripheral Interface EPI port of the Stellaris DK LM3S9D96 development board The 2 Expansion Board provides a transition between the Stellaris External Peripheral Interface EPI connector and the RF Evaluation Module EM connector The DK LM3S9B96 EM2 enables wireless application development using Low Power RF and RF ID evaluation modules on the Stellaris DK LM3S9D96 platform For more information on the EM2 Expansion Board sold separately see Appendix G Stellaris LM3S9B96 2 Expansion Board on page 73 July 3 2011 21 External Peripheral Interface 22 July 3 2011 Using the In Circuit Debugger Interface July 3 2011 The Stellaris amp LM3S9D96 Development Kit can operate as an In Circuit
42. PCB Board Version Revision level of the Flash and SRAM memory expansion board RevC This bit is high if the FPGA believes it is communicating with Revision C of the silicon or higher This bit is only valid after being initialized as described above RTL Version Revision level of the code running in the Flash and SRAM memory expansion board System Control Register 58 The System Control register provides access to configuration bits for the video capture and display system It is implemented as a read modify write register and includes LCD and capture modes Table F 3 System Control Register SYSCTRL 0xA000 0002 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 PCBrA R R R R R R R R W 7 6 5 4 3 2 1 0 VCTES VCQV VSCAL CMKE 1 GA MPRI E N LGDEN LVDEN VCEN R W R W R W R W R W R W R W R W Bit Name Description July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual VCEN LVDEN LGDEN CMKEN VSCALE VCQVGA VCTEST PCBrA Video capture DMA enable Enables video capture to memory Disabling this bit captures the remainder of the current frame and then stops LCD Video DMA enable Enables DMA from the video memory region to the LCD LCD Graphics DMA enable Enables DMA from the graphics memory region to the LCD Chroma key enable Video scale control Scales the video during output to the LCD If set the LCD DMA engine skips every other pix
43. PD6 PD6 LCD Data 6 100 PD7 PD7 LCD Data 7 74 PEO 058 SDRAM D8 0508 75 1 059 SDRAM D9 EPIOSO9 95 PE2 PE2 Touch XN 0524 96 Touch YN 10525 6 4 125 5 125 Audio Out 5 PE5 I2STXSD 125 Audio Out 2 PE6 ADC1 ADC Touch XP 1 PE7 ADCO ADC Touch YP 47 PFO PFO Flash CSn 61 PF1 I2STXMCLK 125 Audio Out 60 PF2 LED1 Green Enet LED 59 PF3 User LED LEDO Yw Enet LED 42 PF4 EPI0S12 SDRAM D12 41 PF5 0515 SDRAM 015 19 EPIOS13 SDRAM D13 18 PG1 EPIOS14 SDRAM D14 36 PG7 EPIOS31 SDRAM CLK 86 PHO 0506 SDRAM D06 85 PH1 0507 SDRAM 007 84 2 0501 SDRAM 001 83 0500 SDRAM D00 76 PH4 EPIOS10 SDRAM D10 63 PH5 EPIOS11 SDRAM D11 July 3 2011 July 3 2011 Table D 1 Microcontroller GPIO Assignments Continued Stellaris amp LM3S9D96 Development Kit User s Manual LM3S9D96 GPIO Pin Development Board Use Number Description Default Function Default Use Alt Function Alternate Use 62 PH6 0526 LCD_WRn 0526 Breakout 15 7 10527 LCD_DC 10527 Breakout 14 0516 SDRAM DQM 87 PJ1 EPI0S17 SDRAM DQM 39 PJ2 EPIOS18 SDRAM CAS 50 PJ3 0519 SDRAM RAS 52 PJ4 0528 SDRAM WEn 53 PJ5 0529 SDRAM CSn 54 PJ6 0530 SDRAM SDCKE 55 PJ7 PJ7 User Switch 39 Microcontroller GPIO Assignments 40 July 3 2011 APPENDIX E Stellaris LM3S9B
44. PIO Pin Development Board Use Number Description Default Function Default Use Alt Function Alternate Use 26 PAO UORx Virtual Com Port 27 PA1 UOTx Virtual Com Port 28 PA2 SSIOCIk SPI 29 PA3 SSIOFss SD Card CSn 30 PA4 SSIORx SPI 31 PA5 SSIOTx SPI 34 PA6 USBOEPEN USB Pwr Enable CANORX 35 PA7 USBOPFLT USB Pwr Fault CANOTX 66 PBO USBOID USB OTG ID 67 1 USBOVBUS USB Vbus 72 PB2 I2COSCL Audio I2C 65 I2COSDA Audio 12 92 4 ADC10 Potentiometer 0523 Breakout 91 5 5 LCD RDn 0522 Breakout 90 6 6 125 5 AVREF Ext Volt Ref 89 PB7 PB7 LCD RST 80 PCO TCK SWCLK JTAG 79 TMS SWDIO JTAG 78 PC2 TDI JTAG 77 PC3 TDO SWO JTAG 25 PC4 052 SDRAM 002 10502 24 5 EPIOS3 SDRAM D03 EPIOSO3 23 PC6 EPIOSA SDRAM D04 0504 22 055 SDRAM 005 0505 10 PDO PDO LCD Data 0 I2SRXSCK 125 Audio In July 3 2011 37 Microcontroller GPIO Assignments 38 Table D 1 Microcontroller GPIO Assignments Continued LM3S9D96 GPIO Pin Development Board Use Number Description Default Function Default Use Alt Function Alternate Use 11 PD1 PD1 LCD Data 1 I280RXWS 125 Audio In 12 PD2 PD2 LCD Data 2 EPIOS20 EPI Breakout 13 PD3 PD3 LCD Data 3 0521 Breakout 97 PD4 PD4 LCD Data 4 I2SRXSD 125 Audio In 98 PD5 PD5 LCD Data 5 I2SRXMCLK 125 Audio In 99
45. Power Supplies Size p Document Number DB LM3S9B96 Sheet Date 6 13 2011 3 of 6 A J8 i R54 67 Line 2 47K ine Input 0470 JE STX 3000 ee A 0 47UF MU C 78 i 4 19 1 Microphone Input e Ms 4 7K R28 STX 3000 MAS 433V Audio Headphone Output RZ 1829 STX 3000 SDA 2 20 LLINEIN LHPOUT 1 40 MICBIAS 17 RLINEIN RHPOUT SCL MICBIAS C PB2 DCOSCL gt 4 MICIN 18 22008 R32 R34 41 A TXSD PES DSTXSD IXSD SDIN c 42 SCLK 12 E R36 1 Ju TXWS MODE LOUT AW PEA DSTXWS ROUT Nets 100 Audio Line Output 1 43 5 RXSD 555 5 C58 R3 STX 3000 PDA DSRXSD DIN AW aXWS AaS 0 47UF 10 3 PDI DSRXWS me 1 ders 1 45 5 PB6 BCLK PB6 TXSCK AVREP lt a BITCLK 35 CLKOUT 1 46 exce PDO BCLK VMID PDO DSRXSCK i TN wm PFI TXMCLK E 1 48 PD5 MCLK Ean PDS DSRXMCLK e 2 HPGND 5 1 49 4 28
46. R R R R R 7 6 5 4 3 2 1 0 0 0 LRMIE LTEIE LTSIE VRMIE VCFEIE VCFSIE R R R W R W R W R W R W R W Bit Name Description VCFSIE Video capture frame start interrupt enable VCFEIE Video capture frame end interrupt enable July 3 2011 59 Stellaris LM3S9B96 FPGA Expansion Board VRMIE LTSIE LTEIE LRMIE Video capture row match interrupt enable LCD transfer start interrupt enable LCD transfer end interrupt enable LCD display row match interrupt enable Interrupt Status Register The Interrupt Status register reports and clears interrupts from the camera and LCD systems An interrupt latches its corresponding bit high until cleared by writing a 1 to it Table F 5 Interrupt Status Register IRQSTAT 0xA000 0006 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 LRMI LTSI VRMI VCFEI VCFSI R R R W R W R W R W R W R W Bit Name Description VCFSI Video capture frame start interrupt Clear the interrupt by setting the corresponding bit to 1 Setting the bit to 0 has no effect VCFEI Video capture frame end interrupt Clear the interrupt by setting the corresponding bit to 1 Setting the bit to 0 has no effect VRMI Video capture row match interrupt Clear the interrupt by setting the corresponding bit to 1 Setting the bit to 0 has no effect LTSI LCD transfer start interrupt Clear the interrupt by setting the corresponding bit to 1 Setting the bit to
47. S 10 LORN 3 MAT 10 1 09 3 10_LOON 3 10 LI0P 3 10 LION 3 a MATI 0 2 MATS XC3ST00E ITQGI44C MATS 16 17 MATS MATS 20 MOS n 8 MOE n MWE n 15 C4 _ 5 e C6 ursi ISGIWVIO2S Mur IMx8 5 TMS NC P TCK NC 28VD TDI NC 3 3uH EN VCCINT 5v 28VA 4 3 3uH GND VCCI Ri XCFOIS 0 033 Mbit 28V 33V UIF DONE 1 nile Rd lt lt PROG B FEDN338P ie s 144 e 4 7uF 4 TDI LI 109 LIN 6 8uH Di 199 4 579228 D 10 C10 GREEN TMS 0 tuF XC3STO0E ATQGT44C 5v eas eue A TX 68u 8 ap 20 c2 ci cis eis 68uF plene i TEXAS INSTRUMENTS Drawing Title AD TR 68uF FPGA board for DK EPI Xilinx JTAG 6 C19 C20 C21 P Title 1500pF 1500 10uF age Title 4 SRAM Power JTAG Size Rev B B Date 8 20 2009 Sheet 7 o 32 Stellaris LM3S9B96 FPGA Expansion Board 72 July 3 2011 APPENDIX Stellaris LM3S9B96 2 Expansion Board This document describes the Stellaris EM2 Expansion Board DK LM3S9B96 EXP FS8 for the Stellaris amp LM3S9B96 and LM3S9D96 Development Boards The Flash and SRAM memory expansion board provides a transition between the Stellaris External Peripheral Interface EPI connector and the RF Evaluation Module EM connector The DK LM3S9B96 EXP FS8 enables wireless application development using Low Power RF LPRF
48. Stellaris LM3S9D96 Development User s Manual X TEXAS INSTRUMENTS DK LM3S9D96 00 Copyright 2009 2011 Texas Instruments Copyright Copyright 2009 2011 Texas Instruments Inc All rights reserved Stellaris and StellarisWare are registered trademarks of Texas Instruments ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited Other names and brands may be claimed as the property of others Texas Instruments 108 Wild Basin Suite 350 P Austin TX 78746 http www ti com stellaris T Cortex Intelligent Processors by w ARM 2 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual Table of Contents Chapter 1 7 TCI 7 Ss eo 10 Is oed ed IE To I A E EATER ORE 11 Development Board Specifications sss eee 11 Chapter 2 Hardware 13 Microcontroller OVerVIGW 1 5 3 10 i cn oen E en eh ehe hd uo eR Mya EN EE ERR FA Ra Een cals da anes XA EM EON EREKE 13 Jumpers and GPIO 13 eoe sje 14 acci LE 15 Power Supplies tte teat vada eiui uat ctetu 15 USB esu ob
49. ctor on the bottom side of the Flash and SRAM memory expansion board to the female EPI expansion connector on the DK LM3S9D96 development board J2 The LCD header pins should fit through the holes on the PCB Use the included jumper wire to provide 5 V power to J5 from any of the three upper pins immediately below and to the right of the EXT 5V connector on the development board When powering up the board verify that the power indicator LED D1 is lit July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual Figure F 2 Removing EPI Board from DK LM3S9D96 Development Board 5 V Power Lu Remove board B sait Remove 4 jumper Remove JP16 31 jumpers July 3 2011 53 Stellaris LM3S9B96 FPGA Expansion Board Hardware Description The Flash and SRAM memory expansion board is designed for use with the Stellaris module Figure F 3 shows a simplified system block diagram Components of the default FPGA board are shown in half tone outline Figure F 3 FPGA Expansion Board Block Diagram Stellaris 2 JTAG Memory Configuration Windower Registers e lc eT m 3 EO IESU UPON Memory Video Configuration NL Arbiter Compositer upon 525522 OT ITUR 1 pol evo Is E cami e
50. current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent Tl deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual prop
51. e dee D AM DEI mda M EHE 15 O 16 Color QVGA LCD Touch Panel sss nennen ensi inni inneren resin nne 17 RS rnm cC 19 User Switehand VE m 19 Chapter 3 External Peripheral Interface seen nnne nnnm nnn nnn snnt nnn 21 SDRAM Expansion BOSE teen ti trate erben e e Hee Ee eee re e RA eh Boa 21 Flash and SRAM Memory Expansion Board essen nennen nennen nnne nnn 21 FPGA Expansion BO amp IG iui deos edad tuit uda a atten ata tis ula dv ede 21 EM2 Expansion scs etd e ene ee apa d E Gu AER 21 Chapter 4 Using the In Circuit Debugger Interface eese eee eene nnne nnne nnn nnns 23 Xie uiui R 25 Appendix B Component 33 Appendix C Connection Details 35 DC zo Tele 35 ARM Targat Pinol t det cu otra T
52. e 3 3 V regulator LCD DECODE CPLD The LCD DECODE CPLD provides address latch and decode for the LCD interface The LCD Command and Data registers are mapped on the EPI memory space to streamline access to these registers The LCD panel control signals L RDn L RWn and L DC and the L D bus are controlled by decode logic on the CPLD with timing derived from EPI signals and do not require direct control from the microcontroller The LCD latch register is provided to control the XN and YN signals used for the touchscreen and also the reset signal to the LCD The LCD backlight signal L BL is controlled by the Stellaris GPIO PE2 24 PE2 can be programmed as a GPIO for ON OFF control of the LCD A second option is to configure PE2 for use as CCP2 or CCP4 with a PWM output for brightness control The TP1 TP4 testpoints connect to the CPLD JTAG signals and along with TP5 and TP6 provide an interface for test and programming of the CPLD LCD Interface Connector The LCD Interface Connector J2 is a 2x17 socket that connects to headers JP16 JP31 and JP39 on the DK LM3S9D96 All signals previously driven to the LCD from the Stellaris MCU are replaced by equivalent signals driven from the LCD DECODE CPLD DC Regulator DC regulator U4 receives 5 V from the EPI connector and provides 3 3 V for the board LED D1 provides a power indicator and lights when the regulator is providing power to the board 44 July 3 2011 Stellaris amp LM3S9D96
53. e applications for this board Table 2 1 Board Features and Peripherals that are Disconnected in Factory Default Configuration Peripheral Jumpers 25 Receive Audio Input JP44 45 47 49 Controller Area Network CAN JP14 15 Ethernet Yellow Status LED LED2 JP2 Analog 3 0V Reference See Appendix D Microcontroller GPIO Assignments on page 37 for a complete list of GPIO assignments The table lists all default and alternate assignments that are supported by the 0 1 jumpers and PCB routing The LM3S9D96 has additional internal multiplexing that enables additional configurations which may require discrete wiring between peripherals and GPIO pins July 3 2011 13 Hardware Description The ICDI section of the board has a GND GND jumper that serves no function other than to provide a convenient place to park a spare jumper This jumper may be reused as required Figure 2 1 Factory Default Jumper Settings 3 HEADPHONE as locika LINE 8 sgg peg ee 1 oe MCLK 8 uicROPHONE 2 sct 05 585 5 88 peo 4 w 2 ET TEXAS INSTRUMENTS LM3S9D96 DEVELOPMENT BOARD ETHERNET Lus JM DEBUG INTERFACE 50K POT USER POT LED Rn SWITCH RO LED 2 SERIAL FLASH orl et 188 3 00VREF 2 L04 425 4 SCLK CARD
54. ee rudi des E EE PER EM 35 Appendix D Microcontroller GPIO 37 Appendix E Stellaris amp LM3S9B96 Flash and SRAM Memory Expansion Board 41 Eealtules c 41 sti 41 Hardware DescrlptiOn eniti e et Hei qr en Mad dn A 43 Functional Description N de ERE de dee de dede dde Pepe E deed Pe euer ue aci Idi 43 c states eee EE E edet ERE T E E 45 Component locations 2 52 rete Eie b HB vate Eee ie A eros fuv 46 Schemalti6s antt ek tere den ee ee eee e 46 Appendix Stellaris amp LM3S9B96 FPGA Expansion Board eese 51 x 51 2 ETO mE TR 52 Hardware Desorption ee ek en aix as 54 gcc E 54 ne etude ERR E TAA 54 July 3 2011 3 Gontfig ration PROM ed t no ued of 54 Configuration gt 50 0 2 a itu at
55. el and every other row during LCD video DMA output Graphics DMA is not affected As a result the video object displays at 1 4 its normal size Memory port row increment If set to 0 any read or write to the memory port auto increments the MPC register at the end of the transfer by 1 If MPC is at the last column MPNR 1 then it sets to 0 and the MPR increments by 1 If the end of the row is reached then it increments by columns If set to 1 any read or write increments by rows Video Capture is QVGA VGA If set to 0 the video capture controller assumes that the camera is configured for VGA capture If set to 1 it assumes that the camera is configured for QVGA This only affects video capture the camera s 2 LCD settings must be reconfigured manually Video Capture Test When set to 1 the incoming pixel stream is ignored and replaced with a test pattern PCB is Revision A An early internal revision of the PCB had a different pin configuration for the camera data port Setting this bit to 1 provides backwards compatibility Interrupt Enable Register The Interrupt Enable register masks or enables interrupts from the FPGA to the Stellaris LM3S9D96 microcontroller Masked interrupts will not assert the IRQ line but they will still appear in the Interrupt Status Register Table F 4 Interrupt Enable Register IRQEN 0xA000 0004 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R
56. enerates an interrupt if enabled Video Memory Address Low Register The VML register provides a pointer to the start of video capture memory and contains the lower 16 bits of the address Video Memory Address High Register The VMH register provides a pointer to the start of video capture memory and contains the higher 16 bits of the address Video Memory Stride Register The VMS register specifies the number of locations in video memory between successive array elements stride and is measured in bytes Using stride enables better processing time LCD Row Match Register During LCD display DMA output at the start of each row the current row value is compared with the LRM register A match generates an interrupt if enabled LCD Video Memory Address Low Register The LVML register provides a pointer to the start of video data for transfer to the LCD This contains the lower 16 bits of the address LCD Video Memory Address High Register The LVMH register provides a pointer to the start of video data for transfer to the LCD This contains the higher 16 bits of the address LCD Video Memory Stride Register The LVMS register specifies the number of bytes between the first pixels on adjacent rows in LCD video memory Recommended to be either the length of a row in bytes or the next highest power of two LCD Graphics Memory Address Low Register The LGML register provides a pointer to the start of graphics memory for output to the LCD a
57. erty of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be pro
58. from DK LM3S9D96 Development 74 EM2 Expansion Board requete e RU tt eaa ir tetra linee oe te PE 75 Assembled DK LM3S9D96 Development Board with EM2 Expansion Board 75 Connecting an EM Module to the EM2 Expansion Board sss 76 Fully Assembled DK LM3S9D96 Board with EM2 Expansion Board and Wireless EM Module 77 EM2 Expansion Board Block 78 Component Placement Plot for Top and 81 5 List of Tables Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Table C 1 Table D 1 Table E 1 Table E 2 Table F 1 Table F 2 Table F 3 Table F 4 Table F 5 Table F 6 Table F 7 Table F 8 Table G 1 Board Features and Peripherals that are Disconnected in Factory Default Configuration 13 SB Related Signals no eere 15 Hardware Debugging Configurations 2 00 16 Debug Related erret n neto ri exte Do aite E e PE Pr i to 17 GD Related Signals 2 5 a a e ob E en ee re dier EE TUS 18 eS Audia RelatedGIghalsa obit tatur is de netos 19 Navigation Switch Related seen enne 19 Debug Interface Pin Assignme
59. h bandwidth parallel interface capability of the Stellaris microcontroller Allows users to control and display the FPGA expansion board s video on the DK LM3S9D96 development board s large 3 5 touchscreen display For more information on the DK LM3S9B96 FPGA expansion board see Appendix F Stellaris amp LM3S9B96 FPGA Expansion Board on page 51 Stellaris amp EM2 Expansion Board DK LM3S9B96 EM2 sold separately Provides a transition between the Stellaris External Peripheral Interface EPI connector and the RF Evaluation Module EM connector Enables wireless application development using Low Power RF and RF ID evaluation modules on the Stellaris DK LM3S9D96 platform For more information on the DK LM3S9B96 EM 2 expansion board see Appendix Stellaris amp LM3S9B96 2 Expansion Board on page 73 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual Figure 1 1 DK LM3S9D96 Development Board Headphone Output Audio Line Outp 5 VDC supply inpu Microphone Input USB Connector fo Audio Line Input Debug and or Power On board JTAG SWD Debug Interface CAN Bus Interface EPI Expansion a lt lt USB connector with Host Device and Go modes Reset switch JTAG SWD Im Out Connector Stellaris LM3S9D96 Microcontroller Power and 5 LI 10 100 Ethernet Ground Test m o
60. ilities such as 80 MHz clock speeds an External Peripheral Interface EPI and Audio 125 interfaces In addition to new hardware to support these features the DK LM3S9D96 board includes a rich set of peripherals found on other Stellaris boards The development board includes an on board in circuit debug interface ICDI that supports both JTAG and SWD debugging A standard ARM 20 pin debug header supports an array of debugging solutions The Stellaris amp LM3S9D96 Development Kit accelerates development of Firestorm class microcontrollers The kit also includes extensive example applications and complete source code Features July 3 2011 The Stellaris LM3S9D96 Development Board includes the following features Simple set up USB cable provides debugging communication and power Flexible development platform with a wide range of peripherals W Color LCD graphics display TFT LCD module with 320 x 240 resolution Resistive touch interface 80 MHz LM3S9D96 microcontroller with 512 Flash 96 K SRAM and integrated Ethernet USB and CAN communications 8MB SDRAM plug in EPI option board EPI break out board plug in option board 1 MB serial Flash memory Precision 3 00 V voltage reference SAFERTOS operating system in microcontroller ROM 125 stereo audio codec Line In Out Headphone Out Microphone In Controller Area Network CAN Interface 10 100 BaseT Ethe
61. input to the touchscreen RST When clear the L_RSTN signal is set to clear When set the L_RSTN signal is reset This signal is used to reset the LCD panel July 3 2011 45 Stellaris LM3S9B96 Flash and SRAM Memory Expansion Board Component Locations Figure E 4 shows the details of the component locations Figure E 4 Component Placement Plot for Top and Bottom 90 9 N N i d E 13 pmm c L 9 5 Ly E 1 780 aem ad Bottom Schematics This section shows the schematics for the DK LM3S9B96 EXP FS8 memory expansion board W Flash SRAM on page 48 LCD Interface on page 49 46 July 3 2011 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual 47 N 6 Revision History MAD 0 127 0 Revision Date Description Ti VF A 5 29 2009 Released for manufacturing 33V 1 FLASH B 7 17 2009 Changed 2 to top entry moved to bottom Added R9 R11 MAD2 PC4 EPI2 25 3 PGO EPI13 MA13 MAD3 47 4 25
62. interface ti com logic ti com power ti com microcontroller ti com www ti rfid com www ti com lprf Applications Communications and Telecom Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space Avionics and Defense Transportation and Automotive Video and Imaging Wireless TI E2E Community Page www ti com communications www ti com computers www ti com consumer apps www ti com energy www ti com industrial www ti com medical www ti com security www ti com space avionics defense www ti com automotive www ti com video www ti com wireless apps Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2011 Texas Instruments Incorporated
63. le 2 6 125 Audio Related Signals Microcontroller Pin Board Function Jumper Name I2COSDA CODEC Configuration Data SDA I2COSCL CODEC Configuration Clock SCL I2STXSD Audio Out Serial Data TXSD I2STXWS Audio Out Framing signal TXWS I2STXSCK Audio Out Bit Clock BCLK I2STXMCLK Audio Out System Clock MCLK I2SRXSD Audio In Serial Data RXSD l2SRXWS Audio In Framing signal Rxws I2SRXSCK Audio In Bit Clock BCLK I2SRXMCLK Audio In System Clock MCLK a Shares GPIO line with Analog voltage reference Jumper installed by default b Shares GPIO line with LCD data bus Port D Jumper omitted by default The Audio CODEC has a number of control registers which are configured using the 2 bus signals CODEC settings can only be written but not read using IC See the StellarisWare example applications for programming information and the TLV320AIX23B data sheet for complete register details The Headphone output can be connected directly to any standard headphones The Line Output is suitable for connection to an external amplifier including PC desktop speaker sets User Switch and LED The development board provides a user push switch and LED see Table 2 7 Table 2 7 Navigation Switch Related Signals Microcontroller Pin Board Function Jumper Name PJ7 User Switch SWITCH PF3 User LED a Shared with Ethernet Jack Yellow LED This jumper is installed by defa
64. list of the EPI signals NOTE Only 16 bit or 32 bit transfers are allowed for this interface Using the Widget Interface This section provides information about writing your own graphics using the widget interface for the Flash and SRAM memory expansion board July 3 2011 55 Stellaris LM3S9B96 FPGA Expansion Board Writing Your Own Stellaris Application The Stellaris microcontroller communicates with the default image through a memory mapped interface To get started you must first configure the EPI port by doing the Code Example F 1 following 1 Configure th e GPIO 2 Configure the port and map it into memory at 0 000 0000 Configuring the EPI Port EP IModeSet EPIO_BASE EPI MODE GENERAL EPIDividerSet EPIO_BASE 1 EPIConfigGPModeSet EPIO_BASE EPI_GPMODE_DSIZE_16 EPI_GPMODE_ASIZE_12 EPI GPMODE WORD ACCESS EPI GPMODE READWRITE EPI GPMODE READ2CYCLE EPI GPMODE CLKPIN EPI GPMODE RDYEN 0 0 EPIAddressMapSet EPIO BASE EPI ADDR PER SIZE 64KB EPI ADDR PER BASE A Memory Map The DK LM3S9B96 FPGA expansion board memory map is shown in Table F 1 The default Stellaris code maps this into the 0xA000 0XXX memory space Detailed descriptions for each register are provide in Register Descriptions on page 57 General Purpose
65. n contains the schematics for the DK LM3S9D96 development board Micro EPI connector USB and Ethernet on page 26 LCD CAN Serial Memory and User I O on page 27 Power Supplies on page 28 25 Audio Expansion Board on page 29 EPI and SDRAM Expansion Boards on page 30 In circuit Debug Interface ICDI on page 31 25 1 2 3 4 5 6 PE2 EPI24 EPI Expansion Connector 2 124 25 PDXEPDO gt 25 Stellaris Microcontroller PD3 EPDI gt ae 1 50 PBY ADCIOEPIDS 1 UL PBS EPI22 4 PGO EPII3 3 48 PCA EPIO2 USB On the Go PHO EPD6 s hc Eppe lt 4 47 PCS EPIO3 PAQ UORX 25 PBO USBOID L gt puT EPIZ7 gt woe 2 L USB Micro PAI UOTX 565 PAUUOTX PBI USBOVBUS 55 1 PBIUSBVBUS VPDSEPIST 7 PA2 SSIOCLK 507 2 58 PB2 CCPO 52 PB2 DCOSCL PDXEPDUAES
66. nal Descriptions Continued SSHTX PF5 SPI MOSI Out SPI Transmit U1RX PC6 MOD UART TX In Modulator UART TX LM3S9D96 RX U1TX PC7 MOD UART RX Out Modulator UART RX LM3S9D96 TX U1RTS PJ6 MOD UART CTS Out Modulator UART CTS LM3S9D96 RTS U1CTS PJ3 MOD UART RTS In Modulator UART RTS LM3S9D96 CTS I2C1SCL PJO MOD 12 SCL Out 2 Bus to EM Modules I2C1SDA PJ1 MOD 126 SDA 2 Bus to EM Modules I2COSCL PB2 AD I2C 5010 Out 2 Bus to Auto Discovery EEPROM I2COSDA PB3 AD 12 SDAO 2 Bus to Auto Discovery EEPROM PC4 PC4 MOD1_nSHUTD Out Shutdown Reset Signal for Primary EM Module PH5 PH5 MOD2_nSHUTD Out Shutdown Reset Signal for Secondary EM Module PHO PHO MOD1 GPIOO GPIO for Primary EM Module PH1 PH1 MOD1_GPIO1 GPIO for Primary EM Module PH2 PH2 MOD1 GPIO2 GPIO for Primary EM Module PH3 MOD1_GPIO3 GPIO for Primary EM Module PGO PGO MOD2 GPIOO GPIO for Secondary EM Module 1 1 MOD2 GPIO1 y o GPIO for Secondary EM Module 7 PG7 MOD2 GPIO2 GPIO for Secondary EM Module PJ2 PJ2 MOD2_GPIO3 GPIO for Secondary EM Module 80 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual Component Locations Figure G 8 shows the details of the component locations Figure G 8 Component Placement Plot for Top and Bottom BN m LI m B1 PRIMARY EM HEADER l MOD1
67. nd contains the lower 16 bits of the address 62 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual LCD Graphics Memory Address High Register The LGMH register provides a pointer to the start of graphics memory for output to the LCD and contains the higher 16 bits of the address LCD Graphics Memory Stride Register The LGMS register specifies the number of bytes between the first pixels on adjacent rows in LCD graphics memory Recommended to be either the length of a row in bytes or the next highest power of two Memory Port Number of Columns Register The MPNC register specifies the number of columns in pixels of the memory port Memory Port Current Row Register The MPR register identifies the selected row in the memory port Memory Port Current Column Register The MPC register identifies the selected column in the memory port Memory Port Address Low Register The MPML register contains the lower address bits of the memory region accessed by the memory port Memory Port Address High Register The MPMH register contains the upper address bits of the memory region accessed by the memory port Memory Port Stride Register The MPMS register specifies the number of bytes between the first pixels on adjacent rows in the memory port Recommended to be either the length of a row in bytes or the next highest power of two Memory Port Register The MPORT register allows sequential video graphics memory plane acce
68. nts essssssseeseneeeeeneene nennen nnne nennen enn 35 Microcontroller GPIO 37 Flash and SRAM Memory Expansion Board Memory 45 LGD Eaten REG 45 FPGA Expansion Board Memory 56 Version Register ten beeline nee At ed ene doe 58 System Control Register oianean 58 Interrupt Enable Register aa i 59 Interrupt Status Register oie eere re reet Aa teens 60 Test Pad Register 5 pee oo Reb e eed eno 61 LGD Conttol Register ceret o er e estet ed tan 61 EPI Signal Descriptions ete ne ie Pee ren E IE Le D eer ee Eee tpa ren rd 66 EPI Signal Descriptioris 2 eicit a Eat 79 July 3 2011 Overview The Stellaris amp LM3S9D96 Development Board provides a platform for developing systems around the advanced capabilities of the LM3S9D96 ARM Cortex M3 based microcontroller The LM3S9D96 is a member of the Stellaris Firestorm class microcontroller family Firestorm class devices include capab
69. of the DK LM3S9D96 board and align the standoffs the EPI connector and the 2x17 J2 header 6 Press firmly downward until the board snaps in then verify that the board is firmly seated on the EPI connector the 2x17 header and the standoffs 7 When powering up the board verify that the power indicator LED D1 is lit 42 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual Hardware Description The Flash and SRAM memory expansion board is designed for use with the Stellaris module configured in Host Bus 8 address data multiplexed mode This mode requires the use of an external 8 bit latch for storing the lower 8 address lines A 7 0 transmitted during the address phase of an EPI transfer This latch can be seen on the expansion board block diagram shown in Figure E 3 Figure E 3 Flash SRAM LCD IF Expansion Board Block Diagram EPI Connector i MA 7 EPI 7 0 MAD 7 0 Da 7 0 MA 27 8 EPI 27 8 dio 27 5 EPi2g 9En EE S Ep129 NEn NENNEN MA26 1 1 27 WE LCD DECODE CD Control ___ _____ ys LCD Functional Description The Flash and SRAM memory expansion board schematics are described in this section The first page of the schematics shows the memory devices and address latch part of the design The second page shows the LCD I F and regulator
70. on Board 86 July 3 2011 References In addition to this document the following references are included on the Stellaris DK LM3S9D96 Development Kit Documentation and Software CD and are also available for download at www ti com stellaris Stellaris LM3S9D96 Microcontroller Data Sheet m Kitronix LCD Data Sheet July 3 2011 StellarisWare Driver Library StellarisWare Driver Library User s Manual publication number SW DRL UG Additional references include FT2232D Dual USB UAHT FIFO IC Data sheet version 0 91 2006 Future Technology Devices International Ltd Texas Instruments TLV320AIC23BPM Audio CODEC Data Sheet Information on development tool being used RealView MDK web site www keil com arm rvmdkkit asp IAR Embedded Workbench web site www iar com Sourcery CodeBench development tools web site www codesourcery com gnu_toolchains arm Code Red Technologies development tools web site www code red tech com Texas Instruments Code Composer Studio IDE web site www ti com ccs 87 References 88 July 3 2011 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is
71. ower supply not included in the kit is available The development board has two main power rails A 43 3 V supply powers the microcontroller and most other circuitry 5 V is used by the OTG USB port and In circuit Debug Interface ICDI USB controller A low drop out LDO regulator U5 converts the 5 V power rail to 3 3 V Both rails are routed to test loops for easy access USB The LM3S9D96 s full speed USB controller supports On the Go Host and Device configurations See Table 2 2 for USB related signals The 5 pin microAB OTG connector supports all three interfaces in conjunction with the cables included in the kit The USB port has additional ESD protection diode arrays D1 D2 D5 for up to 15 kV of ESD protection Table 2 2 USB Related Signals Microcontroller Pin Board Function Jumper Name Pin 70 USBODM USB Data Pin 71 USBODP USB Data Pin 73 USBORBIAS USB bias resistor Pin 66 USBOID OTG ID signal input to microcontroller OTG ID Pin 67 USBOVBUS Vbus Level monitoring VBUS Pin 34 USBOEPE Host power enable active high EPEN Pin 35 USBOPFLT Host power fault signal active low PFLT U6 a fault protected switch controls and monitors power to the USB host port USBOEPEN the control signal from the microcontroller has a pull down resistor to ensure host port power remains off during reset The power switch will immediately cut power if the attached USB device draws July 3
72. pansion Board Features The DK LM3S9B96 EXP FS8 memory expansion board has the following features Xilinx Spartan FPGA with 100k system gates 1 13 CMOS 640 x 480 Color Camera Module 1 MB of asynchronous 10 nsec SRAM for graphics video buffers Standard 1 x 6 and 2 x 5 JTAG headers for FPGA programming 1 kilobit of memory for storing configuration data 8 FPGA test pads provide 5 inputs and 3 1 All necessary power regulation The default FPGA image adds the following features operation in GPM D16 A12 mode at 50 MHz up to 100 MB s W Graphical on screen display OSD overlaid on moving QVGA video July 3 2011 51 Stellaris LM3S9B96 FPGA Expansion Board Widget based touchscreen user interface Screen capture to SDCard or USB stick in Windows bitmap BMP format Brightness saturation tint nue and sharpness picture controls Mirror Flip Normal Picture controls Installation To install the expansion board on the DK LM3S9D96 development board do the following 52 1 2 3 Remove the DK LM3S9B96 EXP FS8 memory expansion board from the antistatic bag On the DK LM3S9D96 board remove any installed board on EPI connector 2 On the DK LM3S9D96 board remove the shunt jumpers on JP16 JP31 and the JP39 headers as shown in Figure F 1 on page 51 Place the expansion board on top of the DK LM3S9D96 board and press firmly downward until the board snaps in Connect the the male EPI expansion conne
73. per may be installed to disable the backlight by connecting it to GND Alternatively a wire may be used to control this signal from a spare microcontroller GPIO line Because the FAN5331 B operates a constant current mode its output voltage will jump up if the LCD should become disconnected To prevent over voltage failure of the IC or diode D3 a zener D4 clamps the voltage The current will limit to 20 mA but the total board current will be higher than when the LCD panel is connected To avoid over heating the backlighting circuit install the BLON jumper to completely shut down the backlighting circuit The LCD module has internal bias voltage generators and requires only a single 3 3 V dc supply Resistive Touch Panel 18 The 4 wire resistive touch panel interfaces directly to the microcontroller using 2 ADC channels and 2 GPIO signals See the StellarisWare source code for additional information on touch panel implementation July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual 125 Audio LM3S9D96 development board has advanced audio capabilities using an 25 Audio TLV320AIC23 CODEC The factory default configuration has Audio output Line Out and or Headphone output enabled Four additional 25 signals are required for Audio input Line Input and or Microphone All four audio interfaces are through 1 8 8 5mm stereo jacks Table 2 6 shows the 25 audio related signals Tab
74. portion of a frame buffer For example this can be used to pull macro cells for JPEG compression This is contained within the mport v file Memory Arbiter The memory arbiter negotiates access to the external SRAM The camera capture block is given highest priority This is contained within the arb v file Video Compositor The video compositor assembles the final image from the video and graphics frame buffers and passes it directly to the LCD Interface It also converts the camera s VGA resolution to the LCD s resolution by either downsampling This is contained within the vlcd v file LCD I F The LCD interface connects to the Kitronix 3 5 LCD display using an 8 bit parallel mode This is usually driven by the Video Compositor but can also be driven directly by the EPI interface This is contained within the vregs v file Camera I F The camera interface block captures pixel data from the Omnivision OV7690 s 8 bit digital video port and synchronization signals This is contained within vcapture v Camera FIFO The Camera FIFO serves two main purposes reclocking and flow control The camera and camera interface run in their own 12 24 MHz clock domain whereas the rest of the system runs off of the EPI clock or twice the EPI clock The FIFO bridges these difference clock domains The camera does not support any flow control functions once triggered it proceeds through an entire image In order to prevent loss of pixels this FI
75. rden M e PBO USBID 1 i 2 PE7 ADCO PHO EPIOSO6 pri JP2 JP 19 0807 37 PHO EPIOI 2 PGO EPIOS13 PH2 EPIOSO1 PGI EPII4 00 285 0 36 ER PHAEPI0S10 476 PHA EPIIO R60 61 10 Ohms for LM3S9B96 Rev see errata 2 63 eh R60 61 0 Ohms for LM3S9B96 Rev C and all LM3S9D96 revs PIO EPI16 14 PHS EPIOSII 1262 PHOEPDG Toy 7 05 6 PHG EPIOS26 5 PH7 EPD Ethernet 10 100baseT PJI EPIOS17 0827 PIZ EPIIS 39 M333V if PJ2 EPIOS18 R2 50 58 MDIO R4 566 Em PIA EPDS 52 hes 5102109 PIS EPIZ9 53 5 10 PIG EPI30 pie To PIT RESETn 64 RSTn TXON 4 433V LU 1 XTLN rxip 40 XTLP A PA SeT 2 08 0 37 gt OSCI RXIN 2 RS 87 4 ci7 Hi 8499 8499 10 10 R3 25 00MHz 16 00MHz 5 USROBBIASS d c2 RI 33 zi AM ERBIAS 124K pe 10PF fa uspope 21 WERE ale T USBODM vppA VDD M43 3V e VDD 1 0 1UF SD VDD 4 c6 8 c10 lt 12 lt 15 1 2208 History VDD Revision Description 2 S ENTE DD Oo
76. ress Low R W 62 LVMH 042 4 0 LCD Video Memory Address High R W 62 LVMS 044 11 0 LCD Video Memory Stride register in bytes R W 62 LGML 050 15 0 LCD Graphics Memory Address Low R W 62 LGMH 052 4 0 LCD Graphics Memory Address High R W 63 LGMS 054 11 0 LCD Graphics Memory Stride R W 63 MPNC 056 9 0 Memory Port Number of Columns R W 63 MPR 058 8 0 Memory Port Current Row R W 63 MPC 9 0 Memory Port Current Column R W 63 MPML 05C 15 0 Memory Port Address Low R W 63 MPMH 4 0 Memory Port Address High R W 63 MPMS 060 11 0 Memory Port Stride R W 63 MPORT 080 15 0 Memory Port R W 63 MEMWIN 400 15 0 Memory Window R W 63 Register Descriptions This section provides the detailed register information for the Flash and SRAM memory expansion July 3 2011 board 57 Stellaris LM3S9B96 FPGA Expansion Board Version Register The Version register communicates the revision numbers of the PCB the FPGA RTL and the Stellaris silicon A dummy write of 0x0000 to this register determines if the Stellaris silicon is revision C or higher and configures the EPI clocking circuit appropriately This is required during initialization for proper operation Table F 2 Version Register VERSION 0xA000 0000 15 14 13 12 11 10 9 8 PCB Board Version 0 0 RevC R R R R R R R R 7 6 5 4 3 2 1 0 RTL Major Version RTL Minor Version R R R R R R R R Bit Name Description
77. rnet USB On The Go OTG Connector Device Host and OTG modes Overview User LED and push button Thumbwheel potentiometer can be used for menu navigation MicroSD card slot Supports a range of debugging options Integrated In circuit Debug Interface ICDI JTAG SWD and SWO all supported Standard ARM 20 pin JTAG debug connector USB Virtual COM Port Jumper shunts to conveniently reallocate resources Develop using tools supporting Keil RealView Microcontroller Development Kit MDK ARM IAR Embedded Workbench Sourcery CodeBench development tools Code Red Technologies development tools or Texas Instruments Code Composer Studio IDE Supported by StellarisWare software including the graphics library the USB library and the peripheral driver library Optional expansion boards that work with the External Peripheral Interface EPI of the DK LM3S9D96 development board extend the capabilities of this development platform each board sold separately Stellaris amp Flash and SRAM Memory Expansion Board DK LM3S9B96 FS8 sold separately Provides Flash memory SRAM and an improved performance LCD interface For more information on the DK LM3S9B96 FS8 memory expansion board see Appendix E Stellaris amp LM3S9B96 Flash and SRAM Memory Expansion Board on page 41 Stellaris amp FPGA Expansion Board DK LM3S9B96 FPGA sold separately Provides machine to machine M2M hig
78. rs have a unique SPI chip select signal but share the data and clock signals The primary EM header contains four GPIO connections to the EPI connector These GPIOs can be used as inputs or outputs depending upon the EM module installed In addition four unique GPIOs are provided to each EM header July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual The primary EM header contains one GPIO connection used to shut down and or reset the EM module The actual function depends on the EM module installed The MODx nSHUTD signal is pulled up to 3 3 V on the EM2 adapter Each header has its own MODx nSHUTD signal The primary EM header contains additional features not found on the secondary EM header including a 32 KHz oscillator input and a header for a 4 bit SDIO module These features are not currently used by the EM modules available today but are available for future expansion Secondary EM Header The secondary EM header should only be used when two EM modules are installed in the system or when specifically indicated in the EM module s README First document CAT24C01 EEPROM The EM2 board contains 1 Kbit 2 EEPROM which connects to 2 bus separate from the one connected to the EM headers This EEPROM contains data that is used by the software drivers to auto detect that the EM2 expansion board is installed in the system The EEPROM is normally write protected To make the EEPROM writeable install a jumper bet
79. s Camera I F SRAMI F LCDIF 1 ae dir nm doe Pe 4kbit 1 Frame Buffers 1 The Flash and SRAM memory expansion board features Xilinx Spartan FPGA which interfaces to the Stellaris microcontroller through its EPI port and acts as a crossbar to the rest of the peripherals Camera The Omnivision OV7690 camera provides color VGA images at up to 30 frames per second to the FPGA over an 8 bit wide parallel interface It is configured by the Stellaris microcontroller via 1 C SRAM The 1 MB 8 bit wide 10 ns SRAM is nominally used as a set of frame buffers 16 bits of the 20 bit address space are latched and multiplexed with its data Access time may be dependent on the previous address Configuration PROM A Xilinx standard configuration PROM holds the default FPGA image and automatically uploads it at power on 54 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual Configuration Pushbutton To reload the configuration PROM image to the FPGA press the configuration pushbutton This allows you to load a new image via JTAG without resetting the rest of the system Test Port Eight uncommitted FPGA pins are brought to test pads Five of the FPGA pins can only be used as inputs The remaining three FPGA pins can be used as inputs or outputs Camera Connector The camera is hosted b
80. ss A write read to this port generates a memory write read to the memory location calculated as follows Mem address MPH MPL MPR x MPS MPC After the transfer if the MPC is not at the last pixel of the row it automatically increments by 1 If the MPC is at the last pixel of the row it sets to 0 and the MPR is incremented by MPS Memory Window Register Use the MEMPAGE register to select the active page 1 Kbyte page Loading a New Image to the FPGA The FPGA can be re imaged using any of the JTAG tool chains that support the Xilinx Spartan 3e XC3S100e Two standard JTAG interfaces are provided with the Flash and SRAM memory expansion board 2 x 7 with 2mm pitch and 1 x 6 with 1 pitch Once connected your JTAG scan chain should show an XC3S100e FPGA and an XCF01S PROM NOTE Images loaded into the PROM must be set to use CCLK as the startup clock Images loaded direct to the FPGA may use either CCLK or JTAG CLK July 3 2011 63 Stellaris LM3S9B96 FPGA Expansion Board Figure F 4 FPGA Boundary Scan ISE iMPACT Boundary Scan oo A 22 SlaveSerial Direct SPI Configuration amp SystemACE PROM File Formatter xe3st 00e xcf01s video fpga bypass Processes Available Operations are Program Get Device ID Get Device Signature Usercode Check Idcode umi Read Status Register One Step SYF Console Programmed successfull
81. the Trace Port Interface Unit TPIU Color QVGA LCD Touch Panel The development board features a TFT Liquid Crystal graphics display with 320 x 240 pixel resolution The display is protected during shipping by a thin protective plastic film which should be removed before use Features Features of the LCD module include Kitronix K350QVG V1 F display 320 x RGB x 240 dots 3 5 262 K colors July 3 2011 17 Hardware Description Wide temperature range White LED backlight Integrated RAM Resistive touch panel Control Interface The Color LCD module has a built in controller with a multi mode parallel interface The development board uses an 8 bit 8080 type interface with GPIO Port D providing the data bus Table 2 4 shows the LCD related signals Table 2 5 LCD Related Signals Microcontroller Pin Board Function Jumper Name PE6 ADC1 Touch X X PE3 Touch Y Y PE2 Touch X X PE7 ADCO Touch Y Y PB7 LCD Reset LRSTn PDO 7 LCD Data Bus 0 7 LDO 7 PH7 LCD Data Control Select LDC PB5 LCD Read Strobe LRDn PH6 LCD Write Strobe LWRn Backlight control BLON Backlight The white LED backlight must be powered for the display to be clearly visible U7 FAN5331B implements a 20 mA constant current LED power source to the backlight The backlight is not Power normally controlled by the microcontroller however the control signal is available on a header A jum
82. ts for LCD panel control To set a bit set the corresponding bit to 1 when writing to the LCD Control Set register To clear a bit set the corresponding bit when writing to the LCD Control Clear register Table F 7 LCD Control Register LCDCTRL 0xA000 0012 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 BL RST YN XN R R R R R 2 R W R W R W Bit Name Description LCD panel touchscreen X control When 0 the LCD Xn signal is set to 0 When set to 1 the LCD Xn signal is tri stated July 3 2011 61 Stellarise amp LM3S9B96 FPGA Expansion Board YN LCD panel touchscreen Y control When set to 0 the LCD Yn signal is set to 0 When set to 1 the LCD Yn signal is tri stated RST LCD panel reset control When set to 0 the LCD RSTn signal is set to 0 When set to 1 the LCD RSTn signal is set to 1 BL LCD backlight control When set to 0 the LCD panel backlight is turned off When set to 1 the LCD panel backlight is turned on Chroma Key Register The CHRMKEY register contains the RGB values to compare for graphics overlay operation During LCD screen updates data from graphics memory is compared with this register if a match occurs the corrsponding frame video pixel is sent to the output instead Video Capture Row Match Register During video capture at the start of a row the current row value is compared with the VCRM register A match g
83. ult 19 Hardware Description 20 July 3 2011 External Peripheral Interface The External Peripheral Interface EPI is a high speed 8 16 32 bit parallel bus for connecting external peripherals or memory without glue logic Supported modes include SDRAM SRAM and Flash memories as well as Host bus and FIFO modes The LM3S9D96 development kit includes an 8 MB SDRAM board in addition to an EPI break out board Other EPI expansion boards may be available SDRAM Expansion Board The SDRAM board provides 8 MB of memory 4M x 16 which once configured becomes part of the LM3S9D96 s memory map at either 0x6000 0000 or 0x8000 0000 The SDRAM interface multiplexes DQOO 14 and AD BAO 14 without requiring external latches or buffers Of the 32 EPI signals only 24 are used in SDRAM mode with the remaining signals used for non EPI functions on the board Flash and SRAM Memory Expansion Board The optional Flash and SRAM Memory Expansion Board DK LM3S9B96 F 8 is a plug in for the DK LM3S9D96 development board This expansion board works with the External Peripheral Interface EPI of the Stellaris microcontroller and provides Flash memory SRAM and an improved performance LCD interface For more information on the Flash and SRAM Memory Expansion Board sold separately see Appendix E Stellaris amp LM3S9B96 Flash and SRAM Memory Expansion Board on page 41 FPGA Expansion Board The FPGA Expansion Board DK LM3S9B96
84. vided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific products are designated by as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Audio Amplifiers Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF IF and ZigBee Solutions www ti com audio amplifier ti com dataconverter ti com www dlp com www ti com clocks
85. ween pins 2 and 3 of JPS1 25 Header The primary EM header and the secondary EM header each contain connections to separate 6 pin 25 headers J2 and J4 respectively These headers connect to the EM modules only and are not connected to the EPI header which connects to the DK LM3S9D96 See the EM module s documentation for more information on the functionality of this header Analog Audio Header The primary EM header and the secondary EM header each contain connections to separate 4 pin analog audio headers J3 and J5 respectively These headers connect to the EM modules only and not connected to the EPI header which connects to the DK LM3S9D96 See the EM module s documentation for more information on the functionality of this header SDIO Header The primary EM header contains a connection to 8 pin SDIO header J1 This header connects to the EM modules only and is not connected to the EPI header which connects to the DK LM3S9D96 See the EM module s documentation for more information on the functionality of this header EPI Signal Descriptions Figure G 1 provides the EPI module s signal descriptions Table G 1 EPI Signal Descriptions PE1 PE1 SPI CS1 Out SPI Chip Select for Primary EM Module PJ4 PJ4 SPI_CS2 Out SPI Chip Select for Secondary EM Module SSH CLK PH4 SPI_CLK Out SPI Clock SSHRx 4 SPI MISO In SPI Receive July 3 2011 79 Stellaris LM3S9B96 EM2 Expansion Board Table G 1 EPI Sig
86. which will be oriented 180 degrees from the primary EM header location NOTE The secondary EM header should only be used when two EM modules are installed in the system or when specifically indicated in the EM module s README First document July 3 2011 77 Stellaris LM3S9B96 EM2 Expansion Board Hardware Description The block diagram for the Flash and SRAM memory expansion board is shown in Figure G 7 Figure 7 EM2 Expansion Board Block Diagram 32 KHZ Osc Connector 33 V SDIO FOIE AE 6 0 Header UART1 4 14 on gt UART PRIMARY SPI 1 PI fs 10 MOD1 SPI_CS HEADER C WO MOD1 SHUTDOWN PO MOD 1 MOD1 GPIO 4 hhh cro Header 3 3V Ps 22 SECONDARY 6555 L p UART EM Header 8 SPI CS HEADER M gt Audio MOD2 SHUTDOWN MEN MOD2 Header MOD GPIO 4 GPIO AD I2C 4 24 01 EEPROM Primary EM Header 78 The primary EM header should always be used when only one EM module is installed unless otherwise indicated in the README First document for the EM module you are installing The primary EM header connects three buses to the EPI connector that are also shared with the secondary EM header These buses are 2 UART1 and SPI NOTE The primary and secondary EM heade
87. y PROGRESS END End Operation Elapsed time 0 sec lt Console Errors Warnings Configuration Platform Cable USB 6 MHz usb hs NOTE The DK LM3S9B96 EXP FS8 boots in JTAG mode but transitions to serial mode once configured by the PROM If your programmer is JTAG only you may need to clear the PROM and power cycle before you can directly program the FPGA via JTAG This issue is rare since most tools support both modes Check with your tool manufacturer for updates Installing the Software To install the software do the following 1 Plug the provided cable into J4 on the right side of the board taking care to ensure proper alignment and orientation The silk screened signal names should match with the exception that 2 5 V corresponds to VDD When correctly aligned the JTAG SPI Full Speed text should face in toward the FPGA Modifying the Default Image This section provides the descriptions for the default FPGA image blocks Default FPGA Image Blocks Configuration Registers The configuration registers are transparently mapped into the Stellaris microcontroller s memory and are used to control the flow of the video streams Register Descriptions on page 57 provides the detailed register maps This is contained within the vregs v file 64 July 3 2011 Stellaris amp LM3S9D96 Development Kit User s Manual Memory Windower The memory windower allows the Stellaris microcontroller to work with a rectangular
88. y the FPC Connector P1 located to the left of the FPGA To insert or remove the camera first open the latch by grasping either side of the connector and gently lifting straight up With the latch open the camera moves easily do not force The camera faces away from the FPGA Close the latch by pushing down on it gently before use Caution Handle the camera carefully when inserting or removing it from the board Never force the camera into a different position doing so could damage the camera 5 V Power Pin J5 is used to provide 5 V power to the Flash and SRAM memory expansion board s regulators This must be connected for successful board operation Connect the the male EPI expansion connector on the bottom side of the Flash and SRAM memory expansion board to the female EPI expansion connector on the DK LM3S9D96 development board J2 The LCD header pins should fit through the holes on the PCB 24 MHz Oscillator The camera and the camera interface portion of the FPGA are clocked by a 24 MHz external oscillator External Peripheral Interface EPI Module The External Peripheral Interface EPI module provides a slave interface for use with the Stellaris microcontroller s EPI controller configured in general purpose mode A12 D16 The direction of the signal allocation is in relation to the FPGA for example a signal labeled n is an input to the FPGA a signal labelled Outis an output from the FPGA See Table F 8 on page 66 for a

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