UMP2 User`s Manual
Contents
1. 2 USB to 8 bit Parallel FIFO Interface Module User s Manual CONTENTS Lc UMPZ 3 2 USAGE AANE 3 FIFO ROSQ FRUI 3 FIFO WAE s re TERI 4 2v FEATURES 6 4 TYPICAL UMP2 APPLICATION 6 USB CONNECTOR UE PM EI PILLE 6 5 TECHNICAL REFERENCE icsisnEEVRA EAE CER DR db abd RC E c D e uir 10 UMPZ INTERNAL SCHEMATICS YER ER 10 TOP VIEW kk tator vs vas ae dd d i e 11 11 PIN DESCRIPTION 12 6 DRIVER INSTALLATION 2 2 13 7 TECHNICAL SPECIFICATION i RR RR CR RR 13 ABSOLUTE RATINGS E SERERE I DICERET 13 TYPICAL RATING KEEPS RERO QUEEN 14 B CONIAC DPauitesieivosvbs EM REN REFER ERES VENE 14 Page 2 1 2 UMP2 is module based FT245BM integrated circuit manufactured by FTDI Ltd which provides with easy to use USB connectivity to PC without any need of additional knowledge about USB itself 2 USAGE UMP2 is a USB to 8 bit bidirectional parallel FIFO interface with simple flow control FIFO read cycle T6 4 T5 22. nd Page 3 RD Time Description Min Unit T1 RD Active Pulse Width 50 ns T2 RD to RD Pre Charge Time 50 ns RD Active to Valid Data 30 ns 14 Valid Data Hold Time from 10 ns inactive T5 RD Inactive to RXF 5 25 ns 6 RXF inactive after RD cycle 80 ns FIFO write cycle T12 T11 TXE gt 7 4 00 07 Time Description Min Unit T7 WR Active Pulse Width 50 ns T8 WR to WR Pre Charge Time 50 ns T9 Data Setup Time before WR 20 ns inactive T10 Data Hold Time from WR inactive 10 ns T11 Inactive to TXE 5 25 ns T12 TXE inactive after RD cycle 80 ns Page 4 module is capable of data transfer rates up to 1 MB sec using direct driver and up to 3 MBd using virtual COM port driver In addition there is an EEPROM memory which may be used to store VID and PID identifiers for OEM applications The module connects by 2 signals directly to USB connector while the application side provides 8 bidirectional signals plus flow control From mechanical standpoint the module is arranged as DIP28 with standard pin spacing of 0 1 inch 2 54 mm so it is possible to fit it into either common or precise DIP28 socket or to solder it directly to printed circuit board The USB connector is to be connected externally which allows the designer to choose the placement of the connector and its type
3. OUT High impedance for about 2 ms after power up and during RESET is active otherwise connected to output of internal 3 3 V voltage regulator This signal is not affected by USB Bus Reset 14 RST RESET IN External reset May be left unconnected if not used 15 VCC VCC PWR Power supply 4 4 V to 5 25 V 16 VIO PWR Power supply 3 0V to 5 25 for output drivers of pins 10 12 14 16 18 25 17 GND GND PWR Signal ground 18 ECS EECS I O EEPROM enable internal pull up of 200 kOhm during reset 19 ESK EESK OUT EEPROM clock high impedance during reset 20 EDT EEDATA I O EEPROM data high impedance during reset 21 PWREZ PWREN OUT PWREN switched to log O after the module is configured and held in log 1 during reset and sleep mode USB Suspend This signal may be used to drive P channel MOSFET which allows to connect applications draining more than 100 mA from USB 22 3V3OUT OUT 3 3V output from internal voltage regulator this pin can source up to 5 mA 23 RXF RXF OUT Data ready if this signal is 109 0 data may be read by 1 0 1 sequence on RD pin If the RXF signal is log 1 the Page 12 data is invalid 24 TXE IN Transmit enabled this signal is log O the data be written by 0 1 0 sequence on WR pin If the TXE signal is log 1 the buffer if full 25 WR WR IN Write signal falling edge of this signal wri
4. B or mini B or USB cable soldered directly to the board may be used This design sigificantly simplifies the development in small production series There is a separate power supply for IO pins VCCIO which allows the module to be connected to 3 0 V application easily The data transfer can be optimized by SI WU signal which controls two functions In suspend mode PWREN 1 if there is Remote WakeUp option in EEPROM turned on falling edge will wake up the device In normal operation falling edge will force immediate data transfer to PC regardless of the amount of data in the buffer otherwise the data is typically being sent in 64 byte blocks PWRENZ signal is designated to drive a P channel MOSFET for applications which drain more than 100 mA max 500 mA from USB In such case it is advisable to turn on enable pull down option in EEPROM configuration Module UMP2 can also operate in BitBang mode in which the data pins act as 8 bit parallel input output This mode can be used for example to configure field programmable logic array directly from PC over USB Further there is RSTOUTZ signal which stays in high impedance state for about 2 ms after power up and then it is connected to internal 3 3 V voltage regulator Signal RSTOUT is also in high inpedance state whenever signal RESET is active RESET log 0 but it is not affected by reset from USB USB Bus RESET The module is equipped with 93LC56 memory of 128x16 bits
5. Lower half of this memory is used for module s needs 64x16 bits Using EEDATA EESK and EECS the application may use upper 64x16 bits for its own purposes While the application is accessing module s EEPROM memory the RESET Z signal must be active RESET 1 09 0 Software drivers fow Windows 98 ME 2K XP CE Mac OS8 OS9 OS X and Linux are available for free on FTDI website http www ftdichip com Page 5 3 FEATURES Data inputs outputs 3 0 to 5 V CMOS compatible Powered from USB or external supply Data transfer rates up to 1 MB sec with direct driver and up to 3 MBd with virtual COM port driver Hardware flow control 384 byte receive buffer 128 byte transmit buffer Supports USB 1 1 protocol USB 2 0 compatible BitBang mode which allows the module to be used as 8 bit bidirectional I O signals RD WR TXE RXF are not used in this mode PWREN signal for driving P channel MOSFET for applications draining more than 100 mA from USB max 500 mA Support for OEM application VID and PID are stored in EEPROM memory which is part of the module Ability to use use free EEPROM capacity 64 16 bits Drivers for Windows 98 2K ME XP Mac OS8 OS9 OS X and Linux available for free DIP28 socket compatible PCB mountable 4 TYPICAL UMP2 APPLICATION SCHEMATICS PIH 3 2 1 YCC PIH 1 2 USBDM PIH 4 5 5 SHIELD USB CONNECTOR PIN 1 VCC 2 USBDM USBDP 4 GND 9 SHIELD Page 6 APPLICATION PO
6. USBOM 3 4 5 SHIELD CONNEC TOR Ji 00 O LT B PRSALS 93LC056 5N Yl TIN xT OUT GM amp MHz aa c2 2TP 2TP GND ZWzolT We cz os CF teg 100N 100N 100N 10N TidM 6 2 GAD Page 10 VIEW BOTTOM VIEW USBM USBP RAF 3U3 2 EDT ESK ECS GND VIO VCC UMP2 1 Top 1 GND USBH 28 UCC USBP 27 3 STWU RD 407 25 506 TRE 05 RAF amp 23 7 D4 SUS 22 s D3 PMER 21 20 10 D ESK his 11 DB _ Ecje 1 2 GND 17 13 RSO 14 RST Y 1 bose 18 Win ASIX RSIX Cz UMP2 1 Bottom Page 11 GND VCC SIHU D D amp 05 04 D3 D2 D1 Da GHD RSO 4 RST PIN DESCRIPTION Pin Label FTDI Typ Description 1 GND GND PWR Signal ground 2 VCC VCC PWR Power supply 4 4 V to 5 25 V 3 SIWU SI WU IN Send immediate WakeUp 4 07 D7 I O Bidirectional data bus bit 7 5 D6 06 I O Bidirectional data bus bit 6 6 D5 05 I O Bidirectional data bus bit 5 7 D4 D4 I O Bidirectional data bus bit 4 8 03 D3 I O Bidirectional data bus bit 9 02 D2 I O Bidirectional data bus bit 2 10 01 D1 I O Bidirectional data bus bit 1 11 DO DO I O Bidirectional data bus bit 0 12 GND GND PWR Signal ground 13 RSO RSTOUT
7. WER 545 LsSBV oc USEDF LOO For example LES2CD APPLICATION Because the VIO must not stay powered Wl 515 after the USBYCO is disconnected GAG GAG a 5 5 LOO stabilisator is needed 2 APPLICATION POWER 35 USB Wed um E It 15 not possible to leave the 505 power active When the 5 power is shutted off APPLICATION 5 TEM GND GND i00N 7 5 APPLICATION POWER 5 USB wie USE Or Sur APPLICATION ae GND GND 4b USB POHER Cmax 100 SY tolerant application JSE WoO 1 Page 8 USB POWER SOO m USB Woo 1 USEDOM 2 USB POWER Cueto SOO mnm tolerant tolerant application application Page 9 5 5 LOG For example Far example 2 10 a For example 210 5 TECHNICAL REFERENCE UMP2 INTERNAL SCHEMATICS ite 1 joes ll FEDATA ze 100N Ri RZ RESET USBDbPC M ZUZOoLT EJ 4708 1 5 R2 USEDM EE CNE 8 PHEEN 18 PHREN 27TR SIHO 11 SI izle 100 14 PE gt ui Pohled shora 1 VCC 2
8. e log 1 VOH min 2 8 V 15 Output voltage log O VOL max 0 3 V 1 5 Output current 109 1 IOH 4 mA VOH VCC 0 5 V Input current log O IOL 8 mA VOL 0 5 V 8 CONTACT Address ASIX s r o Staropramenna 4 150 00 Prague Czech Republic E Mail info asix tools com general information sales asix tools com sales inquiries ordering Support asix tools com technical support WWW www asix tools com development tools www asix info company website Tel 420 257 312 378 Fax 420 257 329 116 Copyright 1991 2007 ASIX s r o All trademarks used in this document are properties of their respective owners This information is provided in the hope that it will be useful but without any warranty We disclaim any liability for the accuracy of this information We are not responsible for the UMP2 EN PDF contents of web pages referenced by this document Page 14
9. tes data to FTDI buffer 26 RD RD IN Read data falling edge of this signal causes 1 byte of data to be read from FTDI buffer and sent to data pins 27 USBDP USBDP I O USB data signal plus It is necessary to connect resistor of 1 5 kOhm between USBDP and 3V3OUT or RSTOUT 28 USBDM USBDM I O USB data signal minus 6 DRIVER INSTALATION For Windows operating systems there are two types of drivers e Virtual COM port which be accessed as common COM port using Win32 API e Direct driver to gain full control of the chip a DLL to interface the driver is provided Detailed description of driver installation procedure can be found on FTDI website http www ftdichip com 7 TECHNICAL SPECIFICATION ABSOLUTE RATINGS Storage temperature TSTR min 65 C max 150 C Operational temperature TPWR min O 9C max 70 Power supply voltage VCCMAX min 0 5 V max 6 00 V Input voltage inputs VIN1 min 0 5 V max VCC 0 5 V Input voltage I O VIN2 min 0 5 V max VCC 0 5 V Output current outputs 01 24 Output current I O IO2 max 24 mA Power WPWR max 500 mW Page 13 TYPICAL RATINGS VCC Operating supply VCC min 4 4 V max 5 25 V voltage Operating supply current ICC1 50 mA Suspended supply current ICC2 max 250 uA Input voltage log 1 VIH min 2 0 V Input voltage log O VIL max 1 0 V Output voltag
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