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SPRU131 - Texas Instruments

1. 000 eee eee EMUO0 1 Configuration With Additional AND Gate to Meet Timing Requirements of Greater Than 25 nS 0 0 c cece tenes EMUO0 1 Configuration Without Global Stop 00 eee eee ee TBC Emulation Connections for n JTAG Scan Paths 0 0 0 0 ccc eee ee eee TMS320 DSP Device Nomenclature 00 00 c ccc ct e een n es TMS320 DSP ROM Code Submittal Flowchart 0 000 c ccc eee eee ees SPRU131G Figures XXV Tables Typical Applications for the TMS320 DSPs 0 0 cc cece eens Bus Usage for Read and Write Accesses 0 unuunu anrr nanan Program and Data Memory on the TMS320C54x Devices 0 cece eee eee Host Port Interfaces on the TMS320C54x Devices 00 Serial Port Interfaces on the TMS320C54x Devices 00 0 cece eee On Chip Program Memory Available on TMS320C54x Devices 005 On Chip Data Memory Available on the TMS320C54x Devices 005 CPU Memory Mapped Registers 00 ccc eee nee tenet nnees Memory Security Modes 0 00 c cece eect eee eens HPI Access in Memory Security Modes for Specific Devices 000008 Status Register 0 STO Bit Summary 0 cece cent ees Status Register 1 ST1 Bit Summary 0 nee nee ees Processor Mode Status Register PMST Bit Summary 2 00 cece eee ALU Input Selection for ADD Instructions 0 0c c
2. 0 00 eect eens TDM 4 Wi6 BUS soccc5ecrhe ried pie IEAA AEAEE ADNE TDM Serial Port Registers Diagram 0 0 cece eens Serial Port Timing TDM Mode 00 c cece eee teen eens TDM Example Configuration Diagram 0 0 cece teenies External Bus Interface Priority 00 0c cece eee tee neta Software Wait State Register SWWSR Diagram 00 cece Software Wait State Control Register SWCR Diagram 20222 00e eee Software Wait State Generator Block Diagram 0000 cece eee eee eee Bank Switching Control Register BSCR Diagram 2 000 c eee eee ee Bank Switching Between Memory Reads 000 cece eee eee eee Bank Switching Between Program Space and Data Space 202200005 Memory Interface Operation for Read Read Write 00 0 cece cece Memory Interface Operation for Write Write Read 00 0 ccc cece eee eee Memory Interface Operation for Read Read Write Program Space Wait States Parallel I O Interface Operation for Read Write Read 0 cee Parallel I O Operation for Read Write Read I O Space Wait States Memory Read and I O Write 000 c cece ene eens Memory Read and I O Read 00 cece eet eee e eee neae Figures SPRU131G 10 15 10 16 10 17 10 18 10 19 10 20 10 21 10 22 10 23 10 24 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A
3. 00ceee eee eee ees A 6 Connections Between the Emulator and the Target System A 7 Physical Dimensions for the 14 Pin Emulator Connector A 8 Emulation Design Considerations 020eeeeeeeeeee A 1 Designing Your Target System s Emulator Connector 14 Pin Header A 1 Designing Your Target System s Emulator Connector 14 Pin Header JTAG target devices support emulation through a dedicated emulation port This port is accessed directly by the emulator and provides emulation func tions that are a superset of those specified by IEEE 1149 1 To communicate with the emulator your target system must have a 14 pin header two rows of seven pins with the connections that are shown in Figure A 1 Table A 1 describes the emulation signals Although you can use other headers the recommended unshrouded straight header has these DuPont connector systems part numbers J 65610 114 J 65611 114 J 67996 114 J 67997 114 Figure A 1 14 Pin Header Signals and Header Dimensions TMS TDI PD Vcc TDO TCK_RET TRST GND Header Dimensions Pin to pin spacing 0 100 in X Y no pin key t Pin width 0 025 in square post GND Pin length 0 235 in nominal GND TCK GND EMUO EMU1 Tt While the corresponding female position on the cable connector is plugged to prevent improper connection the cable lead for pin 6 is present in the cable and is grounded as shown in the schematics and wiring d
4. 5 Executes the ISR until a return instruction concludes the ISR 6 Follows the stack pointer SP to the top of the stack and pops the return address off the stack and into PC 7 Continues executing the main program To determine which vector address has been assigned to each of the inter rupts refer to the table for your specific C54x device in section 6 10 10 Interrupt Tables on page 6 38 Interrupt addresses are spaced four locations apart so that a delayed branch instruction and two 1 word instructions or one 2 word instruction can be accommodated in those locations Program Memory Addressing 6 33 Interrupts 6 10 6 Interrupt Context Save When an interrupt service routine is executed certain registers must be saved onto the stack When the program returns from the ISR by an RC D RETE D or RETF D your software code must restore the contents of these registers Youcan manage stack storage as long as the stack does not exceed the memory space This stack is also used for subroutine calls the C54x DSP supports subroutine calls within the ISR Because the CPU registers and peripheral registers are memory mapped the PSHM and POPM instructions can transfer these registers to and from the stack In addition the PSHD and POPD instructions can transfer data memory values to and from the stack There are anumber of special considerations that you must follow when doing context saves and restores The first consideration is
5. 0 eet n nent eee n nes Far Call INSttGHONS cities eee hace di ie haan oh we Sealed Ee Oe dee tae daw wet oo ce eee oe oe Por Pattie tt OMAN ODOABRWNH HHOANDAAHKWANH WOAKRWNH UTHKWAN FWN HH LE tot ot to dodo bt to t tb bt tt bt ob ft Pe a Pe Se ee ee Se ae xxvi Tables SPRU131G Tables 6 10 Unconditional Return Instructions 2 0c sanansa anann nnana 6 11 Conditional Return Instruction 22 0 0 0c ce ence een n nee neee 6 12 Far Return Instructions 0 0 een ene eee enn eae 6 13 Conditions for Conditional Instructions sss sasse s esere cent nes 6 14 Grouping of Conditions for Multiconditional Instructions 0 0c eee 6 15 Conditional Store Instructions 0 0 cette tne neees 6 16 Conditions for Conditional Store Instructions sossar eranan rnrn nnr 6 17 Multicycle Instructions That Become Single Cycle Instructions When Repeated 6 18 Nonrepeatable Instructions 0 tenet neees 6 19 TMS320C541 Interrupt Locations and Priorities aaan cece cee eee 6 20 TMS320C542 Interrupt Locations and Priorities 0 0 cece eee 6 21 TMS320C543 Interrupt Locations and Priorities 0 0 cece eee 6 22 TMS320C545 Interrupt Locations and Priorities 0 0 cece eee 6 23 TMS320C546 Interrupt Locations and Priorities 0 cece ee eee 6 24 TMS320C548 Interrupt Locations and Priorities 0 0 cece eee 6 25 TMS
6. An external bus cycle may cause additional latency None None Category Any other store type instruction See Table 7 5 on page 7 39 for a list of store type instructions Interrupts cause an update of SP This update of SP can interfere with a previous write to SP Therefore special considerations must be made when using interrupts while executing instructions that update SP SPRU131G Pipeline 7 37 Pipeline Latencies Table 7 3 Recommended Instructions for Accessing Memory Mapped Registers Continued Catt Function Instruction s Latency Additional Restrictions 21 Reading AG AH AL Any instruction that The previous instruction None BG BH or BL as mem canreadfrom memory must not modify accu ory mapped registers mulator A or accumula tor B Category Any other store type instruction See Table 7 5 on page 7 39 for a list of store type instructions Interrupts cause an update of SP This update of SP can interfere with a previous write to SP Therefore special considerations must be made when using interrupts while executing instructions that update SP 7 5 2 Updating ARx BK or SP A Resolved Conflict Table 7 4 lists C54x DSP instructions that update data address generation logic DAGEN registers in the read stage of the pipeline The DAGEN regis ters are the auxiliary registers ARx the block size register BK and the stack pointer SP All other instructions that write to these re
7. External user interrupt 3 HPI interrupt McBSP 1 receive interrupt default or DMA channel 2 interrupt McBSP 1 transmit interrupt default or DMA channel 3 interrupt Program Memory Addressing 6 47 Interrupts Table 6 27 TMS320C5410 Interrupt Locations and Priorities Continued TRAP INTR Number K Priority Name 28 i5 DMAC4 SINT12 29 16 DMAC5 SINT13 120 127 Reserved Location Hex 70 74 78 7F Function DMA channel 4 interrupt DMA channel 5 interrupt Reserved Table 6 28 TMS320C5420 Interrupt Locations and Priorities 6 48 TRAP INTR Number K Priority Name 0 1 RS SINTR 1 2 NMI SINT16 2 SINT17 3 SINT18 4 SINT19 5 SINT20 6 SINT21 7 SINT22 8 SINT23 9 SINT24 10 SINT25 11 SINT26 2 SINT27 13 SINT28 14 SINT29 15 SINT30 16 3 INTO SINTO 17 4 INT1 SINT1 18 5 INT2 SINT2 Program Memory Addressing Location Hex 0 4 8 Cc 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 Function Reset hardware and software reset Nonmaskable interrupt Software interrupt 17 Software interrupt 18 Software interrupt 19 Software interrupt 20 Software interrupt 21 Software interrupt 22 Software interrupt 23 Software interrupt 24 Software interrupt 25 Software interrupt 26 Software interrupt 27 Software interrupt 28 Software interrupt 29 Software interrupt 30 External user interrupt 0 External user interrupt 1 Reserved SPRU131G In
8. 6 8 Repeating a Block of Instructions SPRU131G The repeat block instructions are used to repeat a block of code N 1 times where N is the value loaded into the block repeat counter register BRC This block of code can contain one or more instructions Unlike the repeat single operation which disables all maskable interrupts the repeat block operation can be interrupted The instructions used for this operation are RPTB and RPTBD a delayed instruction The RPTB instruction executes in four cycles RPTBD allows the execution of one 2 word instruction or two 1 word instructions following the RPTBD instruction instead of flushing the pipeline thus RPTBD effectively executes in 2 cycles When the RPTBD instruction is used delayed instruc tions cannot be in the two words following the RPTBD instruction The repeat block feature provides zero overhead looping Zero overhead looping is controlled by the block repeat active flag BRAF in ST1 and the following memory mapped registers J BRC contains the value N which is one less than the number of times the block is to be repeated _ The block repeat start address register RSA holds the address of the first instruction of the block of code to be repeated _j The block repeat end address register REA holds the address of the last instruction word of the block of code to be repeated BRAF is set to 1 to activate the block repeat The block repeat feature can be activated o
9. 8 4 On Chip Peripherals SPRU131G Peripheral Memory Mapped Registers Table 8 3 C543 Peripheral Memory Mapped Registers Address Hex 20 21 22 23 24 25 26 27 28 29 2A 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 5F SPRU131G Name BDRRO BDXRO BSPCO BSPCEO TIM PRD TCR SWWSR BSCR TRCV TDXR TSPC TCSR TRTA TRAD AXRO BKXO ARRO BKRO Description Buffered serial port data receive register Buffered serial port data transmit register Buffered serial port control register Buffered serial port control extension register Timer register Timer period register Timer control register Reserved Software wait state register Bank switching control register Reserved TDM serial port data receive register TDM serial port data transmit register TDM serial port control register TDM serial port channel select register TDM serial port receive transmit register TDM serial port receive address register Reserved ABU transmit address register ABU transmit buffer size register ABU receive address register ABU receive buffer size register Reserved On Chip Peripherals 8 5 Peripheral Memory Mapped Registers Table 8 4 C545 C545A Peripheral Memory Mapped Registers 8 6 Address Hex 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2F 30 31 32 33 37 38 39 3A 3B 3C 57 58 59 5F On Chip Peripherals Name BDRRO BDXRO BSPCO BSPCEO TIM PRD TCR DRR1 DXR1 SPC
10. Bit Name 12 TC 11 C 10 OVA 9 OVB 8 0 DP SPRU131G Reset Value 1 Function Test control flag TC stores the results of the arithmetic logic unit ALU test bit op erations TC is affected by the BIT BITF BITT CMPM CMPR CMPS and SFTC instructions The status set or cleared of TC determines if the conditional branch call execute and return instructions execute TEs 1 if the following conditions are true 1 Abit tested by BIT or BITT is a 1 A compare condition tested by CMPM CMPR or CMPS exists between a data memory value and an immediate operand ARO and another auxiliary register or an accumulator high word and an accumulator low word J Bit 31 and bit 30 of an accumulator tested by SFTC have different values from each other Carry is set to 1 if the result of an addition generates a carry it is cleared to 0 if the result of a subtraction generates a borrow Otherwise itis reset after an addition and it is set after a subtraction except for an ADD or SUB with a 16 bit shift In these cases the ADD can only set and the SUB only reset the carry bit but they cannot affect it otherwise Carry and borrow are defined at the 32nd bit position and are operated at the ALU level only The shift and rotate instructions ROR ROL SFTA and SFTL and the MIN MAX ABS and NEG instructions also affect this bit Overflow flag for accumulator A OVA is set to 1 when an overflow occurs in either the ALU or the m
11. transmitter reset XRST A bit in the serial port control register SPC buffered serial port control register BSPC and TDM serial port control register TSPC that resets the serial port transmitter TRCV TDM data receive register A register used to receive data through the TDM serial port TRINT See TDM receive interrupt TRN See transition register TRSR TDM data receive shift register A 16 bit register that holds serial data received from the TDM data TDAT line See also TRCV TRTA TDM receive transmit address register The lower half of this register specifies the receive address of the device the upper half of this register specifies the transmit address TSPC TDM serial port control register A 16 bit memory mapped register that contains status and control bits for the TDM serial port TXINT See TDM transmit interrupt TXM See transmit mode wait state A period of time that the CPU must wait for external program data or I O memory to respond when reading from or writing to that external memory The CPU waits one extra cycle one CLKOUT 1 cycle for every wait state warm boot The process by which the processor transfers control to the entry address of a previously loaded program Glossary D 19 Glossary D 20 XF A general purpose software controlled external flag output pin that allows for signalling external devices XF status flag A bitin status register ST1 that indicates the status o
12. 18 On Chip RAM Block Organization C541 C542 543 C545 546 C548 549 0000h 0000 03FF l 0000 07FF 0000 07FF 0000 07FF 0400 o7FF l 0800 0AFF 0800 OF FF 0800 OF FF 0800 OF FF 0B00 OFFF l l 1000h 1000 13FF 1000 17FF 1000 17FF 1000 17FF 1800 1 FFF 1800 1 FFF 2000h 2000 27FF 2000 3FFF 3000h 4000h 4000 5FFF 5000h 6000h 6000 7FFF 7000h C Dual access RAM C Single access RAM 3 24 Memory SPRU131G Data Memory Figure 3 19 On Chip RAM Block Organization C5402 C5410 C 5420 0060h 1FFFh 2000h 3FFFh C5402 C5420 subsystem A or B 0080h 07FFh 0800h OFFFh 1000h 17FFh 1800h 1FFFh 2000h 3FFFh 4000h 5FFFh 6000h 7FFFh ng000h n9FFFh nA000h nBFFFh ncoooh nDFFFh nE000h nFFFFh e e Dual RAM s C ARSS 2F000h ingle RAM pak Single access 2FFFFh n page where n 0 1 2 127 3 3 3 Memory Mapped Registers SPRU131G The 64K words of data memory space include the device s memory mapped registers which reside in data page 0 data addresses 0000h 007Fh Data page 0 consists of the following Lj The CPU registers 26 total are accessible with no wait states see Table 3 3 on page 3 27 Memory 3 25 Data Memory I Theperipheral registers are used as control and data registers in peripher al circuits These registers reside within addresses 0020h O05F and reside on a dedicated peripheral bus structure For a list of p
13. AR1 Int_RAM I 0 RSBX INTM Globally enable interrupts B MAIN_PG Return to foreground program J Square brackets and identify an optional parameter If you use an optional parameter specify the information within the brackets do not type the brackets themselves Information About Cautions This book contains cautions This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment The information in a caution is provided for your protection Please read each caution carefully SPRU131G Read This First V Related Documentation from Texas Instruments Related Documentation from Texas Instruments vi The following books describe the TMS320C54x DSP and related support tools To obtain a copy of any of these TI documents call the Texas Instru ments Literature Response Center at 800 477 8924 When ordering please identify the book by its title and literature number Many of these documents are located on the internet at http Awww ti com TMS320C54x DSP Reference Set Volume 1 CPU literature number SPRU131 describes the TMS320C54x 16 bit fixed point general purpose digital signal processors Covered are its architecture internal register structure data and program addressing and the instruction pipeline Also includes development support information parts lists and design considerations for using the XDS510 emulat
14. LJ Using the seven LSBs of the current auxiliary register value when indirect addressing is used cae Note In indirect addressing the nine MSBs of the auxiliary register are forced to O after the operation For example if AR1 is used to point to a memory mapped register in memory mapped register addressing mode and it contains a value of FF25h then AR1 points to the timer period register PRD since the seven LSBs of AR1 are 25h and the address of the PRD is 0025h After execution the value remaining in AR1 is 0025h Figure 5 15 Memory Mapped Register Addressing Block Diagram SPRU131G All bits Os 7 LSBs from instruction register IR or current auxiliary register 16 bit memory mapped register address Note In addition to registers any scratch pad RAM located on data page 0 can be modified by using memory mapped register addressing ee Data Addressing 5 25 Memory Mapped Register Addressing Only eight instructions can use memory mapped register addressing LDM MMR dst MVDM dmad MMR MVMD MMR dmad MVMM MMRx MMRy POPM MMR PSHM MMR STLM src MMR STM k MMR O O O O O O O L Note The following indirect addressing modes are not allowed for memory mapped register addressing Q ARx Ik ARx Ik ARx Ik Ly Ik In these cases the assembler issues a warning 5 26 Data Addressing SPRU131G Stack Addressing 5 7 Stack Addressing The system stack is
15. POPM STL This instruction modifies the ASM NOP field of ST1 SUB A ASM B SPRU131G Pipeline 7 71 Pipeline Latencies 7 5 8 Latencies in Repeat Block Loops The following status register fields and bits are affected by latency 1 BRC block repeat counter register 1 BRAF block repeat active flag 7 5 8 1 Updating Block Repeat Counter BRC Register A pipeline conflict can occur if two conditions are simultaneously met 1 An instruction writes to the BRC register O The next instruction is an RPTB D The conflict occurs because the second instruction reads BRC in a pipeline stage that occurs before the previous instruction updates it There are certain instructions which do not cause any pipeline conflicts when updating BRC Use these instructions wherever possible to avoid conflicts Table 7 23 Recommended Instructions for Writing to BRC Before an RPTB Loop To do this Use this instruction Write an immediate value to BRC STM lk BRC Copy a memory location to BRC MVDK Smem BRC Table 7 24 lists latencies between instructions that update BRC and an RPTB D instruction Notes 1 Donotplace instructions that modify BRC in the delay slots of a RPTBD instruction 2 You are responsible for rearranging instructions or inserting NOPS if necessary to accommodate latencies ee Table 7 24 Latencies for Updating BRC Before an RPTB Loop Latency if Second Instruction First Instruction Is RP
16. Serial port control register Reserved ABU transmit address register ABU transmit buffer size register ABU receive address register ABU receive buffer size register Reserved Clock mode register C546A only Reserved On Chip Peripherals 8 7 Peripheral Memory Mapped Registers Table 8 6 C548 Peripheral Memory Mapped Registers Address Hex 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 8 8 On Chip Peripherals Name BDRRO BDXRO BSPCO BSPCEO TIM PRD TCR TRCV TDXR TSPC TCSR TRTA TRAD AXRO BKXO ARRO BKRO Description Buffered serial port 0 data receive register Buffered serial port 0 data transmit register Buffered serial port 0 control register Buffered serial port 0 control extension register Timer register Timer period register Timer control register Reserved Software wait state register Bank switching control register Reserved Host port interface control register Reserved TDM serial port data receive register TDM serial port data transmit register TDM serial port control register TDM serial port channel select register TDM serial port receive transmit register TDM serial port receive address register Reserved ABU 0 transmit address register ABU 0 transmit buffer size register ABU 0 receive address register ABU 0 receive buffer size register SPRU131G Peripheral Memory Mapped Registers Table 8 6 C548 Per
17. TXM bit Index 4 XRDY bit XRST bit XSREMPTY bit D 19 buffered signals JTAG buffering burst mode serial port 9 18 D 5 bus devices bus usage table 2 4 butterfly definition BXE definition D 2 BXINT definition BXSR definition definition C address bus CAB definition C bus CB definition C compiler B 2 C16 definition cable target system to emulator A 1 to A 25 cable pod call instructions pipeline 7 8 calls conditional far 6 11 unconditional carry bit C definition central processing unit CPU memory mapped registers D14 circular addressing circular buffer _ 5 17 diagram rules for using circular buffer size register BK 3 27 3 28 definition definition CLKOFF definition CLKOUT off CLKOFF definition CLKP definition D 6 clock changing the multiplier ratio 8 33 CLKMD clock mode register CLKMD 8 29 considerations when using IDLE instruction operation following reset 8 34 operation in IDLE modes 8 34 sources crystal resonator circuit 8 26 external clock switching clock modes DIV to PLL PLL to DIV clock mode MCM definition clock mode register CLKMD bit summary 8 29 diagram PLLCOUNT bits PLLDIV bit PLLMUL bits PLLNDIV bit PLLON OFF bit PLLSTATUS bit clock modes mode configurations 8 27 settings at reset C5402 C541B 545A 546A 548 549 54 10 sources clock polarity CLKP definition CLOCKOUT off CLKOFF 4
18. definition transmit mode TXM definition transmit ready XRDY definition transmit reset XRST definition transmit shift register empty ma transition register i 3 28 ID 18 18 definition TRB definition TRCV definition TRINT D 19 definition TRN 3 27 B 28 D 19 definition TRSR definition D 19 TRST signal A 25 TRTA definition D 19 TSPC definition D 19 TSS definition TXINT pis definition TXM p 11 p 14 D 19 definition unconditional branches delayed instructions nondelayed 6 6l unconditional calls delayed 6 9 instructions 6 10 nondelayed 6 9 unconditional operations branch_ 6 6 call 6 9 far branch 6 8 far call 6 11 far return return Index 20 unconditional returns delayed instructions nondelayed updating accumulator no latency one cycle latency updating ARx instructions updating auxiliary registers updating BK instructions Viterbi operator 4 24 wait state generation conditions 8 48 wait state generator 10 5 to block diagram software 10 5 software wait state register format 10 5 wait state register SWWSR warm boot definition D 19 workshops XDS510 emulator JTAG cable See emulation xr definition pin XF status flag XF definition XH definition XINT definition XPC See also program counter extension register loading addresses XRDY a XRST pagead S XSR definition EN XSREMPTY 9 99
19. 0 ARP is not updated in indirect addressing mode with a single data memory operand ARP must always be set to 0 when the DSP is in this mode CMPT 1 ARP is updated in indirect addressing mode with a single data memory operand except when the instruction is selecting auxiliary register 0 ARO Accumulator shift mode The 5 bit ASM field specifies a shift value within a 16 through 15 range and is coded as a 2s complement value Instructions with a parallel store as well as STH STL ADD SUB and LD use this shift capability ASM can be loaded from data memory or by the LD instruction using a short immediate operand Central Processing Unit 4 5 CPU Status and Control Registers 4 1 2 Processor Mode Status Register PMST The PMST register is loaded with memory mapped register instructions such as STM The PMST bits are shown in Figure 4 3 and described in Table 4 3 Figure 4 3 Processor Mode Status Register PMST Diagram 15 7 6 5 4 3 2 1 0 T These bits are only supported on C54x devices with revision A or later or on C54x devices numbered C548 or greater Table 4 3 Processor Mode Status Register PMST Bit Summary Reset Bit Name Value Function 15 7 IPTR 1FFh Interrupt vector pointer The 9 bit IPTR field points to the 128 word program page where the interrupt vectors reside You can remap the interrupt vectors to RAM for boot loaded operations At reset these bits are all set to 1 the reset vector always
20. 13 Burst Mode Serial Port Receive at Maximum Packet Frequency DRR loaded from RSR loaded ead oade read from RSR As shown in Figure 9 12 and Figure 9 13 with the transfer of multiple data packets at maximum packet frequency in burst mode packets are transmitted at a constant rate and the serial port clock provides sufficient timing informa tion for the transfer which permits a continuous stream of data Therefore the frame sync pulses are essentially redundant Theoretically then only an initial frame sync signal is required to initiate the multipacket transfer The C54x DSP does support operation of the serial port in this fashion referred to as continuous mode which is selected by clearing the FSM bit in the SPC to 0 Continuous mode serial port operation is described in detail in section 9 2 5 Continuous Mode Transmit and Receive Operations 9 2 5 Continuous Mode Transmit and Receive Operations 9 24 Serial Ports In continuous mode a frame sync on FSX FSR is not necessary for consecu tive packet transfers at maximum packet frequency after the initial pulse Continuous mode is selected by setting FSM 0 Note that when FSM 0 frame sync pulses are not required but they are not ignored therefore im properly timed frame syncs may cause errors in serial transfers Serial port operation under various error conditions is described in detail in section 9 2 6 Serial Po
21. 27 Software interrupt 28 Software interrupt 29 reserved Software interrupt 30 reserved External user interrupt 0 External user interrupt 1 External user interrupt 2 Internal timer interrupt Buffered serial port receive interrupt Buffered serial port transmit interrupt Serial port receive interrupt Serial port transmit interrupt External user interrupt 3 Reserved SPRU131G Interrupts Table 6 24 TMS320C548 Interrupt Locations and Priorities TRAP INTR Number K 0 oO Oo NOOA ON p Ei p Brom n Bom nh EoI Bes Bee Be ee Be N Eo 0O E WO DY FD o po Nn DO O fF o NY Pa 28 31 SPRU131G Priority 1 2 oO oo N DOD oO FF WwW I a se es Aa WO YO O Name RS SINTR NMI SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INTO SINTO INT4 SINT1 INT2 SINT2 TINT SINT3 BRINTO SINT4 BXINTO SINT5 TRINT SINT6 TXINT SINT7 INT3 SINT8 HPINT SINT9 BRINT1 SINT10 BXINT1 SINT11 Location Hex 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 70h 7F Function Reset hardware and software reset Nonmaskable interrupt Software interrupt 17 Software interrupt 18 Software interrupt 19 Software interrupt 20 Software interrupt 21 Software interrupt 22 Software interrupt 23 Software interrupt 24 Software interrupt 25 Software interrupt 26 Software interrupt 27
22. 5 5 4 3 Dual Operand Circular Address Modifications Xmod or Ymod 3 and BK 0 When Xmod or Ymod 3 and BK 0 ARO is added to ARx using circular addressing after each access Otherwise dual operand circular addressing is exactly as described in section 5 5 3 4 on page 5 15 5 5 4 4 Single Operand Instructions That Use the Dual Operand Format Some instructions with only one data memory operand use dual data memory operand addressing so that they fit in a single word for single cycle execution In these instructions only Xmem is available and the Xmod and Xar fields define the addressing mode for the operand Four single operand instructions can be executed in a single cycle g BIT Xmem BITC J SACCD src Xmem cond Li SRCCD Xmem cond LJ STRCD Xmem cond 5 22 Data Addressing SPRU131G Indirect Addressing Five instructions with optional shift also support this type of addressing for single word single cycle execution ADD Xmem SHFT src LD Xmem SHFT dst STH sre SHFT Xmem STL src SHFT Xmem SUB Xmem SHFT src O O O O L 5 5 5 Compatibility ARP Mode ARP can be used in indirect addressing This allows the AR to be defined by ARP to ease code translation from the following DSP generations TMS320C20x TMS320C24x or TMS320C5x With CMPT 1 and ARF 0 ARP is used to determine which AR is used to address memory Figure 5 13 shows how the ARP indexes the auxiliary registers In using ARP the
23. 6 do not have any latency in updating ARx Use these instructions wherever possible to avoid pipeline conflicts SPRU131G Pipeline Latencies Table 7 6 Pipeline Protected Instructions for Updating ARx SPRU131G To do this Use this instruction Write an immediate value to ARx STM Ik MMRT Copy a memory location to ARx MVDK Smem MMRt Copy the contents of an ARx to another ARx MVMM MMR MMR t See Table 7 7 for one possible conflict with these instructions STM and MVDK do not conflict with the next instruction for two reasons J They are two word instructions O They update ARx when the first instruction word is in the read stage of the pipeline Table 7 7 shows the latencies between instructions that update and subse quently use ARx The second and third instructions must access the same auxiliary register or BK to cause a latency Any instruction not mentioned in the table has no latency Table 7 8 shows the latencies between instructions that update and subse quently use BK ee 0000000 Note You are responsible for rearranging instructions or inserting NOPs if necessary to accommodate latencies SS oS SX SSS SSS Pipeline 7 45 Pipeline Latencies Table 7 7 Latencies for Accessing ARx a Latencies based on third instruction category Second Instruction STM ST MVDK MVMD MVKD MVDM MVPD POPM POPD DELAY LTD MVDD lk auxreg lk auxreg Smem auxreg MMR auxreg
24. CLKMD switch to DIV mode LDM CLKMD A AND 01lb A poll STATUS bit BC TstStatu ANEQ STM 0b CLKMD reset PLLON_OFF when STATUS IDLE3 IDLE3 wake up switch the PLL from DIV mode to PLL X 3 mode STM 0010001000000111b CLKMD PLLCOUNT 64 decimal jis DIV mode PLL Considerations When Using the Bootloader SPRU131G The ROM on the C545A and C546A contains a bootloader program that can be used to load programs into RAM for execution following reset When using this bootloader with the software programmable PLL several considerations are important for proper system operation On the C545A and C546A for compatibility the bootloader configures the PLL to the same mode as would have resulted if the same CLKMD 1 3 input bits had been provided to the option 1 or option 2 hardware programmable PLL see Table 8 15 on page 8 27 according to whether the C545A or C546A is an option 1 or option 2 device Once the bootloader program has finished executing and control is transferred to the user s program the PLL can be reprogrammed to any desired configuration On Chip Peripherals 8 35 Host Port Interface 8 6 Host Port Interface The standard host port interface HPI is available on the C542 C545 C548 and C549 devices The HPI is an 8 bit parallel port that interfaces a host device or host processor to the C54x DSP Information is exchanged between the C54x DSP and the host device through
25. Covington Multiple Digital Signal Processor Environ ment for Intelligent Signal Processing Proceedings of the IEEE USA Volume 75 Number 9 pages 1246 1259 September 1987 Jackson Leland B Digital Filters and Signal Processing Hingham MA Kluwer Academic Publishers 1986 Jones D L and T W Parks A Digital Signal Processing Laboratory Using the TMS32010 Englewood Cliffs NJ Prentice Hall Inc 1987 Lim Jae and Alan V Oppenheim Advanced Topics in Signal Processing Englewood Cliffs NJ Prentice Hall Inc 1988 10 Lin K G Frantz and R Simar Jr The TMS320 Family of Digital Signal Processors Proceedings of the IEEE USA Volume 75 Number 9 pages 1143 1159 September 1987 11 Lovrich A Reimer J An Advanced Audio Signal Processor Digest of SPRU131G Technical Papers for 1991 International Conference on Consumer Elec tronics June 1991 Read This First ix Technical Articles 12 Magar S D Essig E Caudel S Marshall and R Peters An NMOS Digi tal Signal Processor with Multiprocessing Capability Digest of IEEE Inter national Solid State Circuits Conference USA February 1985 13 Oppenheim Alan V and R W Schafer Digital Signal Processing Engle wood Cliffs NJ Prentice Hall Inc 1975 and 1988 14 Papamichalis P E and C S Burrus Conversion of Digit Reversed to Bit Reversed Order in FFT Algorithms Proceedings of ICASSP 89 USA p
26. DSP platform there are three generations the TMS320C5x TMS320C54x and TMS320C55x Devices within the C5000 DSP platform use a similar CPU structure that is combined with a variety of on chip memory and peripheral configurations These various configurations satisfy a wide range of needs in the worldwide electronics market When memory and peripherals are integrated with a CPU onto a single chip overall system cost is greatly reduced and circuit board space is reduced Figure 1 1 shows the performance gains of the TMS320 DSP family of devices SPRU131G TMS320 DSP Family Overview Figure 1 1 Evolution of the TMS320 DSP Family C6000 C62x C64x C67x C5000 C54x C55x C2000 C20x C24x High performance C28x Power efficient performance Control optimized 1 1 2 Typical Applications for the TMS320 DSP Family Table 1 1 lists some typical applications for the TMS320 family of DSPs The TMS320 DSPs offer more adaptable approaches to traditional signal proces sing problems such as vocoding and filtering than standard microprocessor microcomputer devices They also support complex applications that often require multiple operations to be performed simultaneously SPRU131G Introduction 1 3 TMS320 DSP Family Overview Table 1 1 Typical Applications for the TMS320 DSPs Automotive Adaptive ride control Antiskid brakes Cellular telephones Digital radios Engine control Navigation and global p
27. DXR definition D 8 E address bus EAB definition E bus EB definition EAB address register EAR definition EMUO 1 configuration A 21 A 23 A 24 emulation pins IN signals rising edge modification EMUO 1 signals emulation JTAG cable timing calculations A 7 to A 9 A 18 to A 26 emulator connection to target system JTAG mechanical dimensions A taltolA 25 designing the JTAG cable A 1 emulation pins pod interface signal buffering tolA 13 target cable header design A 2 tofa 3 emulator pod timings enabling the timer execute conditional execute interrupt service routine ISR interrupt context save interrupt latency EXIO EXP encoder definition Index 7 Index exponent encoder 4 27 definition _ D 8 figure extended program memory paged 3 21 external bus hold mode IDLE3 wake up sequence interface interrupts prioritization reset 10 29 timing 10 14 I O access memory access reset external bus control registers 10 5 external bus interface 2 17 external bus operation introduction 10 1 external flag output XF pin external interface key signals table 10 2 far branches 6 8 instructions 6 8 unconditional 6 8 far calls instructions unconditional 6 11 far returns instructions unconditional 6 14 fast Fourier transform FFT fast return register RTN definition FE 9 39 D 9 definition D 9 FIG _ 9 38 D 9 definition D 9
28. Frame synchronization pulses as well as a programmable frequency serial clock can be provided by the BSP for transmission and reception The polarity of frame sync andclock signals are also programmable The maximum operat ing frequency is CLKOUT 40 Mbit s at 25 ns 50 Mbit s at 30 ns The BSP transmit section includes a pulse code modulation PCM mode that allows easy interface with a PCM line Operation of the BSP in standard nonbuffered mode is detailed in section 9 3 1 on page 9 35 The ABU has its own set of circular addressing registers each with corre sponding address generation units Memory for transmit and receive buffers resides within a special 2K word block of C54x DSP internal memory This memory can also be used by the CPU as general purpose storage however this is the only memory block in which autobuffering can occur Using autobuffering word transfers occur directly between the serial port section and the C54x DSP internal memory automatically using the ABU embedded address generators The length and starting addresses of the buffers within the 2K block are programmable and a buffer empty full interrupt can be generated to the CPU Buffering can easily be halted using the auto disabling capability ABU operation is detailed in section 9 3 2 on page 9 40 The BSP autobuffering capability can be separately enabled for the transmit and receive sections When autobuffering is disabled standard mode data transfers with
29. INTR and TRAP When asubroutine returns the return address is retrieved from the stack using a pop operation and loaded into the PC Instructions used for returns from sub routines are RET D RETE D RETEF D and RC D The FRAME instruction also affects the stack This instruction adds a short immediate offset to the stack pointer The stack is also used in SP referenced direct addressing see section 5 4 2 SP Referenced Direct Addressing on page 5 9 Data Addressing 5 27 Data Types 5 8 Data Types There are two basic data types for accessing memory in the C54x devices 16 bit and 32 bit Most instructions can access 16 bit data Accessing 32 bit data however requires the use of the special instructions listed in Table 5 11 Table 5 11 Instructions With 32 Bit Word Operands Instruction Description DADD Double precision add dual 16 bit add to accumulator DADST Double precision load with T add dual 16 bit load with T add subtract DLD Long word load to accumulator DRSUB Double precision subtract dual 16 bit subtract from long word DSADT Long load with T subtract dual 16 bit load with T subtract add DST Store accumulator in long word DSUB Double precision subtract dual 16 bit subtract from accumulator DSUBT Long load with T subtract dual 16 bit load with T subtract For a 16 bit operand access a 16 bit word is read from data memory through the D bus and written to data memory through the E bus For a 32 bit oper
30. Software interrupt 27 Software interrupt 28 Software interrupt 29 reserved Software interrupt 30 reserved External user interrupt 0 External user interrupt 1 External user interrupt 2 Internal timer interrupt Buffered serial port receive interrupt Buffered serial port transmit interrupt TDM serial port receive interrupt TDM serial port transmit interrupt External user interrupt 3 Reserved SPRU131G Interrupts Table 6 22 TMS320C545 Interrupt Locations and Priorities TRAP INTR Number K 0 oO O N OO on fF WO ND D Bie Pp Bios DO Boe Beas Baas Beas Baa ee 0 EEI Bis Bon Boy n Boy Oo Res Bye oO 26 31 SPRU131G Priority 1 2 Oo N o Oo Aa WwW i oOo 12 Name RS SINTR NMI SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INTO SINTO INT4 SINT1 INT2 SINT2 TINT SINT3 BRINTO SINT4 BXINTO SINT5 RINT1 SINT6 XINT1 SINT7 INT3 SINT8 HPINT SINT9 Location Hex 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 68 7F Function Reset hardware and software reset Nonmaskable interrupt Software interrupt 17 Software interrupt 18 Software interrupt 19 Software interrupt 20 Software interrupt 21 Software interrupt 22 Software interrupt 23 Software interrupt 24 Software interrupt 25 Software interrupt 26 S
31. The 16 bit stack pointer register SP contains the address of the top of the system stack The SP always points to the last element pushed onto the stack The stack is manipulated by interrupts traps calls returns and the PSHD PSHM POPD and POPM instructions Pushes and pops of the stack predecrement and postincrement respectively the 16 bit value in the stack pointer 3 3 4 8 Circular Buffer Size Register BK 3 28 Memory The ARAUs use16 bit circular buffer size register BK in circular addressing to specify the data block size For information on BK and circular addressing see section 5 5 3 4 Circular Address Modifications on page 5 15 SPRU131G Data Memory I O Memory 3 3 4 9 Block Repeat Registers BRC RSA REA The 16 bit block repeat counter BRC register specifies the number of times a block of code is to repeat when a block repeat is performed The 16 bit block repeat start address RSA register contains the starting address of the block of program memory to be repeated The 16 bit block repeat end address REA register contains the ending address of the block of program memory to be repeated For more information about repeating multiple instructions and the BRC RSA and REA see section 6 8 Repeating a Block of Instructions on page 6 23 3 3 4 10 Processor Mode Status Register PMST The processor mode status register PMST controls memory configurations of the C54x devices The PMST is described in
32. edged the C54x DSP executes the branch instruction you place at a predetermined address the vector location and performs the ISR 6 10 1 Interrupt Flag Register IFR SPRU131G IFR is amemory mapped CPU register that identifies and clears active inter rupts see Figure 6 2 An interrupt sets its corresponding interrupt flag in IFR until it is recognized by the CPU Any of the following four events clear an interrupt flag 1 The C54x DSP is reset RS is low _j An interrupt trap is taken J A 1 is written to the appropriate bit in IFR 1 The INTR instruction is executed using the appropriate interrupt number A 1 in any IFR bit indicates a pending interrupt To clear an interrupt write a 1 to the interrupt s corresponding bit in the IFR All pending interrupts can be cleared by writing the current contents of the IFR back into the IFR Program Memory Addressing 6 27 Interrupts Figure 6 2 Interrupt Flag Register IFR Diagram a C541 IFR 15 12 11 10 9 8 7 6 5 4 3 2 1 b C542 IFR 15 12 11 c C543 IFR 15 12 11 10 9 8 7 6 5 4 3 2 1 d C545 IFR 15 12 1 e C546 IFR 15 12 11 10 9 8 7 6 5 4 3 2 1 f C548 IFR 15 12 11 10 9 8 7 6 5 4 3 2 1 g C549 IFR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Resvd BMINT BMINTO BXINT1 BRINT1 HPINT INT3 TXINT TRINT BXINTO BRINTO TINT INT2 INT1 INTO 6 28 Program Memory Addressing SPRU131G Interrupts
33. incremented by PAGEN The repeated MACD instruction supports filtering constructs weighted running average While the sum of products is executed the sample data is shifted in memory to make room for the next sample and to throw away the oldest sample MAC and MACP instructions with circular addressing can also support filter implementation The FIRS instruction implements an efficient symmetric structure for the FIR filter when circular addressing is used 4 22 Central Processing Unit SPRU131G Multiplier Adder Unit The MPYU and MACSU instructions facilitate extended precision arithmetic operations The MPYU instruction performs an unsigned multiplication The unsigned contents of T are multiplied by the unsigned contents of the addressed data memory location and the result is placed in the specified accumulator The MACSU instruction performs a signed unsigned multiplication and addition The unsigned contents of one data memory location are multiplied by the signed contents of another data memory location and the result is added to the accumulator This operation allows operands greater than 16 bits to be broken down into 16 bit words and then processed separately to generate products that are larger than 32 bits The square add SQURA and square subtract SQURS instructions pass the same data value to both inputs of the multiplier to square the value The result is added to SQURA or subtracted from SQURS the accumulator at the a
34. on page 9 26 for information about serial port operation under various exception conditions FSM 1 Burst mode A frame sync pulse is required on FSX FSR for the transmission reception of each word Format This bit specifies the word length of the serial port transmitter and receiver FO 0 The data is transmitted and or received as 16 bit words ROSI The data is transferred as 8 bit words The data is trans ferred with the MSB first The BSP also allows the capability of 10 and 12 bit transfers For a detailed description of this feature see section 9 3 Buffered Serial Port BSP Inter face on page 9 33 Serial Ports 9 11 Serial Port Interface Table 9 5 Serial Port Control Register SPC Bit Summary Continued Reset Value Function Bit Name 1 DLB 0 0 Res 0 Reserved Bit DLB Bit 9 12 Serial Ports Digital Loopback Mode This bit can be used to put the serial port in digital loopback mode DLB 0 The digital loopback mode is disabled The DR FSR and CLKR signals are taken from their respective device pins DLB 1 The digital loopback mode is enabled The DR and FSR sig nals are connected to DX and FSX respectively through multiplexers as shown in Figure 9 4 a and b on page 9 13 Additionally CLKR is driven by CLKX if MCM 1 If DLB 1 and MOM 0 CLKR is taken from the CLKR pin of the device This configuration allows CLKX and CLKR to be tied together externally and supplied by a common exter
35. same clock cycle data address bus A group of connections used to route data memory addresses The C54x CPU has three 16 bit buses that carry data memory addresses CAB DAB and EAB data address generation logic DAGEN Logic circuitry that generates the addresses for data memory reads and writes See also program address generation logic PAGEN data bus A group of connections used to route data The C54x CPU has three 16 bit data buses CB DB and EB data memory A memory region used for storing and manipulating data Addresses 00h 1Fh of data memory contain CPU registers Addresses 20h 5Fh of data memory contain peripheral registers data page pointer DP A 9 bit field in status register 0 STO that specifies which of 512 128 x 16 word pages is currently selected for direct address generation DP provides the nine MSBs of the data memory address the dma provides the lower seven See also dma data ROM DROM A bit in processor mode status register PMST that determines whether or not part of the on chip ROM is mapped into data space DB Dbus A bus that carries operands that are read from data memory digital loopback mode A synchronous serial port test mode in which the DLB bit connects the receive pins to the transmit pins on the same device to test if the port is operating correctly digital loopback mode DLB bit A bit in the serial port control register SPC buffered serial port control register BS
36. shift arithmetically 4 14 shift conditionally shift logically shift operations ASM field shifter 2 9 4 17 to 4 19 block diagram connections definition used for short immediate addressing RPT addressing sign control logic definition sign extension definition sign extension mode SXM signal descriptions 14 pin header A 3 signals buffered A 10 buffering for emulator connections A 10 to A 13 description 14 pin header A 3 timing sign extension mode SXM definition D 16 single data memory operand addressing diagram direct addressing mode diagram indirect addressing mode assembler syntax diagram Eid instruction format __b 10 instruction format types of with 32 bit words single operands 5 13 single access RAM SARAM 2 6 definition single operand addressing SINT See software interrupt slave devices SMOD definition SMUL definition example 4 9 Soft bit software development tools assembler linker B 2 general linker software interrupt SINT definition D 16 software programmable PLL software wait state control register SWCR 10 6 software wait state generator block diagram 10 8 software wait state register SWWSR 2 13 definition diagram software wait state register SWWSR bit summary C548 549 5402 54 10 5420 SP compiler mode definition push pop return MVMM FRAME SP load one cycle latency 7 52 three cycle latency Index two cycle latency
37. space Some instructions such as FIRS MACD and MACP use the program bus to fetch a second multiplicand Program Memory Addressing 6 3 Program Counter PC 6 2 Program Counter PC The PC is a 16 bit register that contains the internal or external program memory address used when an instruction is fetched or when a 16 bit immedi ate operand or coefficient table in program memory is accessed To address program memory the address in the PC is put onto the PAB The PC can be loaded several ways Table 6 2 shows what is loaded into the PC according to the code operation performed Table 6 2 Loading Addresses Into PC 6 4 Code Operation Reset Sequential execution Branch Branch from accumulator Block repeat loop Subroutine call Subroutine call from accumulator Hardware interrupt soft ware interrupt or trap Program Memory Addressing Address Loaded to the PC PC is loaded with FF80h PC is loaded with PC 1 PC is loaded with the 16 bit immediate value directly following the branch instruction PC is loaded with the lower 16 bit word of accumulator AorB PC is loaded with the repeat start address RSA when PC 1 equals the repeat end address REA 1 provided that BRAF 1 PC 2 is pushed onto the stack and PC is loaded with the 16 bit immediate value directly following the call instruction mnemonic The return instruction pops the top of the stack back into PC to return to the cal
38. 1 Resolved Conflict Between Instruction Fetch and Operand Read 7 3 2 Resolved Conflict Between Operand Write and Dual Operand Read 7 3 3 Resolved Conflict Among Operand Write Operand Write and Dual Operand Read cece ete tee teen eae xviii Contents SPRU131G Contents 7 4 Single Access Memory and the Pipeline 00 0c cece eee ees 7 5 Pipeline Latencies 00 ccc eee eee eens 7 5 1 Recommended Instructions for Accessing Memory Mapped Registers 7 5 2 Updating ARx BK or SP A Resolved Conflict 000005 7 5 3 Rules to Determine DAGEN Register Access Conflicts 7 5 4 Latencies for ARX and BK 0 0 ccc nrnna 7 5 5 Latencies for the Stack Pointer 00 eee eee eee e eee aes 7 5 6 Latencies for Temporary Register T cee cece eee eee 7 5 7 Latencies for Accessing Status Registers 0 cece eee ee eae 7 5 8 Latencies in Repeat Block Loops 0 c cece eee teen eee eee 7 5 9 Latencies forthe PMST 0 ccc ccc ccc cnet ent eens 7 5 10 Latencies for Memory Mapped Accesses to Accumulators 8 On Chip Peripherals 000 ccc cece eee eee eee Describes the TMS320C54x DSP peripherals and how to control them Includes information about the general purpose I O pins timers clock and host port interface 8 1 Available On Chip Peripherals 0000 cece eee e eee eee 8 2 P
39. 1 word instruc tions prior to XC If no interrupts occur these instructions have no effect on XC However if an interrupt occurs it can trap between the instructions and XC affecting the condition before XC is executed See Chapter 7 Pipeline for information about pipeline latencies 6 6 3 Conditional Store Instructions Some CPU registers can be conditionally stored in data memory using the conditional store instructions listed in Table 6 15 The conditions used with conditional store instructions are listed in Table 6 16 In a conditional store instruction the address is modified and the memory operand is read regardless of the condition If the condition is met the corresponding register is stored in data memory If the condition is not met the operand is written into the same memory location from which it was read so the value of that memory location remains the same The conditional store instructions are single memory operand instructions but they use the dual memory operand indirect addressing mode to put the instruction into one 16 bit word Therefore these instructions execute in one cycle Conditionally storing the block repeat counter BRC allows you to store an index in a repeat block loop Table 6 15 Conditional Store Instructions Instruction CPU Register SACCD Accumulator A or B STRCD Temporary register T SRCCD Block repeat counter BRC 6 18 Program Memory Addressing SPRU131G Conditional Operat
40. 14 3 1 10 September October 1986 Read This First SPRU131G SPRU131G 9 Technical Articles Casale S R Russo and G Bellina Optimal Architectural Solution Us ing DSP Processors for the Implementation of an ADPCM Transcoder Proceedings of GLOBECOM 89 pages 1267 1273 November 1989 Cole C A Haoui and P Winship A High Performance Digital Voice Echo Canceller on a SINGLE TMS32020 Proceedings of ICASSP 86 USA Catalog Number 86CH2243 4 Volume 1 pages 429 432 April 1986 Cole C A Haoui and P Winship A High Performance Digital Voice Echo Canceller on a Single TMS32020 Proceedings of IEEE Internation al Conference on Acoustics Speech and Signal Processing USA 1986 Lovrich A and J Reimer A Multi Rate Transcoder Transactions on Consumer Electronics USA November 1989 Lovrich A and J Reimer A Multi Rate Transcoder Digest of Technical Papers for 1989 International Conference on Consumer Electronics June 7 9 1989 Lu H D Hedberg and B Fraenkel Implementation of High Speed Voice band Data Modems Using the TMS320C25 Proceedings of ICASSP 87 USA Catalog Number 87CH2396 0 Volume 4 pages 1915 1918 April 1987 Mock P Add DTMF Generation and Decoding to DSP uP Designs Electronic Design USA Volume 30 Number 6 pages 205 213 March 1985 Reimer J M McMahan and M Arjmand ADPCM on a TMS320 DSP Chip Proceedings of SPEE
41. 29 Serial Port Interface Figure 9 19 SP BSP Receiver Functional Operation Continuous Mode 9 30 Serial Ports FSR pulse occurs Ignore Receive in pulse since progress RSRFULL is active Abort current receive Start next reception No RSR to DRR copy thus current word is lost During a receive in continuous mode if a frame sync pulse occurs this causes areceive abort condition and one packet of data is lost this is caused because the frame sync pulse resets the RSR bit counter The data present on DR then begins being shifted into RSR starting again from the first bit Note that if a frame sync occurs after deactivating the RSRFULL flag by reading DRR but before the beginning of the next word boundary this also creates a receive abort condition Another cause for error is the appearance of extraneous frame syncs during a transmission After the initial frame sync in continuous mode no others are required if an improperly timed frame sync pulse occurs during a transmit the current transfer that is serially driving XSR data onto DX is aborted and data in XSR is lost A new transmit cycle is initiated and transfers continue as long as the DXR is updated once per transmission afterward Figure 9 20 shows continuous mode transmitter functional operation Note that if XSREMPTY is active in continuous mode and an external frame sync occurs the previous DXR data is transmitted as in
42. 32 During the lockup period the clock generator continues to operate in DIV mode after the PLL lock timer has decremented to 0 the PLL begins clocking the C54x DSP The decimal preset value PLLCOUNT is LockupTime PLLCOUNT gt 16 x Toxin where Tc kin is the input reference clock period and LockupTime is the required PLL lockup time as shown in Figure 8 5 Figure 8 5 PLL Lockup Time Versus CLKOUT Frequency 60 55 ll other NY 50 45 40 35 549 and 5410 30 25 Lockup Time us 25 10 20 30 40 50 60 70 80 100 CLKOUT frequency MHz SPRU131G On Chip Peripherals 8 31 Clock Generator Switching Clock Mode From DIV Mode to PLL Mode Several circumstances may require switching from DIV mode to PLL mode however note that if the PLL is not locked when switching from DIV mode to PLL mode the PLL lockup time delay must be observed before the mode switch occurs to ensure that only proper clock signals are sent to the device It is therefore important to know whether or not the PLL is locked when switching operating modes The PLL is unlocked on power up after changing the PLLMUL or PLLDIV values after turning off the PLL PLLON OFF 0 or after loss of input refer ence clock Once locked the PLL remains locked even in DIV mode as long as the PLL had been previously locked and has not been turned off PLLON OFF stays 1 and the PLLMUL and P
43. 4 5 6 7 8 9 Decode Access Read Execute IR SP RETFD Read RTN INTM 0 Fetch Decode Access Read Execute Ff fe Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute 7 18 Pipeline SPRU131G Pipeline Operation 7 1 4 Conditional Execute Instructions in the Pipeline Because XC is single word instruction it takes at least one instruction cycle to completely execute Example 7 13 shows pipeline behavior during the execution of XC Example 7 13 Execute Conditionally XC Instruction in the Pipeline Address Instruction al i1 a2 i2 a3 i3 a4 XC 2 cond a5 i5 a6 i6 1 2 3 4 5 6 7 8 9 10 11 Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute i2 i3 Prefetch Fetch Decode Access Read Execute XC PAB a4 PB XC IR XC Evaluate Prefetch Fetch Decode Access Read Execute i5 or NOP PAB a5 PB i5 Conditional execution of i5 Prefetch Fetch Decode Access Read Execute i6 or NOP PAB a6 PB i6 Conditional execution of i6 In Example 7 13 the following events occur Cycle 4 The PAB is loaded with the address of the XC instruction Cycle 5 The XC instruction opcode is fetched Cycle 7 When the XC instruction moves into the access stage of the pipe line in cycle 7 any conditions specified by the XC instruction are evaluated If the tested conditions are true the next two instruc tions i5 and i6 are decoded and a
44. 4 7 kQ x 16 x 15 pF 5 4 7x103Qx 16x15 no 12F 5 1128 x 10 9 5 64 us SPRU131G Design Considerations for Using XDS510 Emulator A 9 Connections Between the Emulator and the Target System A 6 Connections Between the Emulator and the Target System It is extremely important to provide high quality signals between the emulator and the JTAG target system You must supply the correct signal buffering test clock inputs and multiple processor interconnections to ensure proper emula tor and target system operation Signals applied to the EMUO and EMU1 pins on the JTAG target device can be either input or output In general these two pins are used as both input and output in multiprocessor systems to handle global run stop operations EMUO and EMU1 signals are applied only as inputs to the XDS510 emulator header A 6 1 Buffering Signals If the distance between the emulation header and the JTAG target device is greater than 6 inches the emulation signals must be buffered If the distance is less than 6 inches no buffering is necessary Figure A 4 shows the simpler no buffering situation The distance between the header and the JTAG target device must be no more than 6 inches The EMUO and EMU1 signals must have pullup resistors connected to Vcc to provide a signal rise time of less than 10 us A 4 7 kQ resistor is suggested for most applications Figure A 4 Emulator Connections Without Signal Buffering 6 inches or less
45. 40h Channel 5 TCSR 20h TA FEh RA 0th TA 01h RA 04h TA 02h RA 04h TA 04h RA 08h Device 4 Device 5 Device 6 Device 7 Channel 4 TCSR 10h Channel 3 TCSR 08h Channel 2 TCSR 04h Channel 1 TCSR 02h TA 08h RA 10h TA 10h RA 20h TA 20h RA 40h TA 40h RA 80h Table 9 14 Interprocessor Communications Scenario Transmitter Receiver Channel TADD Data Device Device s 0 EEN 0 1 7 1 40h 7 6 2 20h 6 5 3 10h 5 4 4 08h 4 3 5 04h 3 2 6 02h 2 1 7 Oth 1 0 Table 9 15 shows the TDM serial port register contents of each device that results in the scenario given in Table 9 14 Device 0 provides the clock and frame control signals for all channels and devices The TCSR and TRTA contents specify which device is to transmit on a given channel and which devices are to receive SPRU131G Serial Ports 9 65 Time Division Multiplexed TDM Serial Port Interface Table 9 15 TDM Register Contents 9 66 Serial Ports Device TSPC TRTA TCSR 0 xxF9h FEOth xx01h 1 xxC9h 0102h xx80h 2 xxC9h 0204h xx40h 3 xxC9h 0408h xx20h 4 xxC9h 0810h xx10h 5 xxC9h 1020h xx08h 6 xxC9h 2040h xx04h 7 xxC9h 4080h xx02h In this example the transmit address of a given device the upper byte of TRTA matches the receive address the lower byte of TRTA of the receiving device Note however that it is not necessary for the transmit and receive addresses to match exactly the matching operation implemented in the receiver is a bitwise AND operation Thus i
46. 7 CMPT definition code definition code generation tools B 2 cold boot definition compare select and store unit CSSU 4 24 to 4 26 See also CSSU definition compatibility ARP mode 2 le y Index compatibility mode indirect addressing mode instruction format instruction format 5 24 compatibility mode CMPT 4 5 definition compiler B 2 compiler mode latencies for SP SP compiler mode CPL 4 4 definition D 6 condition groupings table 6 17 conditional branches delayed instructions 6 8 nondelayed conditional calls delayed instruction nondelayed conditional execute conditional operations to 6 19 branch 6 7 call 6 10 conditions execute return store XC instruction conditional returns delayed 6 14 instruction nondelayed conditional store conditions for _ 6 19 instructions configuration multiprocessor A 13 connector 14 pin header A 2 dimensions mechanical consumer applications viii continuous mode serial port control applications vii k control registers external bus 10 5 counter down time PLL multiplication factors Index 5 Index CPL definition latencies CPU 2 8 to 2 10 accumulators ALU See also ALU arithmetic logic unit 2 8 See also ALU compare select and store unit CSSU 2 10 components 4 1 CSSU exponent encoder introduction multiplier adder shifter CPU components 4 1 CPU registers dia
47. 8 on page 8 42 shows the equivalent circuit of the HDS1 HDS2 and HCS inputs Host interrupt output Controlled by the HINT bit in the HPIC Driven high when the C54x DSP is being reset Placed in the high impedance state when EMU1 OFF is active low HPI ready output When high indicates that the HPI is ready for a transfer to be performed When low indicates that the HPI is busy completing the internal portion of the previous transaction Placed in high impedance when EMU1 OFF is active low HCS enables HRDY that is HRDY is always high when HCS is high Read write input Hosts must drive HR W high to read HPI and low to write HPI Hosts without a read write strobe can use an address line for this function The HCS input serves primarily as the enable input for the HPI and the HDS1 and HDS2 signals control the HPI data transfer however the logic with which these inputs are implemented allows their functions to be interchanged if de sired If HCS is used in place of HDS1 and HDS2 to control HPI access cycles HRDY operation is affected since HCS enables HRDY and HRDY is always high when HCS is high The equivalent circuit for these inputs is shown in Figure 8 8 The figure shows that the internal strobe signal that samples the HCNTLO 1 HBIL and HR W inputs when HAS is not used is derived from all three of the input signals as the logic illustrates Therefore the latest of HDS1 HDS2 or HCS is the one whi
48. A A lt lt T Central Processing Unit 4 27 Chapter 5 Data Addressing The TMS320C54x DSP offers seven basic addressing modes J mmediate addressing uses the instruction to encode a fixed value _j Absolute addressing uses the instruction to encode a fixed address J Accumulator addressing uses an accumulator to access a location in program memory as data _j Direct addressing uses seven bits of the instruction to encode an offset relative to DP or to SP The offset plus DP or SP determine the actual address in data memory _j ndirect addressing uses the auxiliary registers to access memory _j Memory mapped register addressing modifies the memory mapped registers without affecting either the current DP value or the current SP value J Stack addressing manages adding and removing items from the system stack Topic Page 5 1 Immediate Addressing e m E cece eee e ence eee eee e nee 5 2 5 2 Absolute Addressing rc cecccc icici sce sictevere evel ele avaleye eie erace sie ietefeva EE 5 3 Accumulator Addressing aq ncccocemann ss yeeee inean 5 4 Direct Addressing iran c cise cs ccs cjeysaisiclscers aleclsisials nA ninn 5 9 BINGIKFECtFACOKESS ING erar yereiereretatctets ele felavelerersicfelatelevelateralelateysratelelelaietsrer 5 6 Memory Mapped Register Addressing 0 seeeseeues 5 25 5 7 Stack Addressing ae aee e le erate ste ssveieve a etetatel yeeteyeyayeiey srs 5 8 Data Types vc
49. B equal to 0 Accumulator A not equal to 0 Accumulator B not equal to 0 Accumulator A less than 0 Accumulator B less than 0 Accumulator A less than or equal to 0 Accumulator B less than or equal to 0 Accumulator A greater than 0 Accumulator B greater than 0 Accumulator A greater than or equal to 0 Accumulator B greater than or equal to 0 Accumulator A overflow detected Accumulator B overflow detected No accumulator A overflow detected No accumulator B overflow detected ALU carry set to 1 ALU carry cleared to 0 Test control flag set to 1 Test control flag cleared to 0 BIO signal is low BIO signal is high Unconditional operation Operand AEQ BEQ ANEQ BNEQ ALT BLT ALEQ BLEQ AGT BGT AGEQ BGEQ AOV BOV ANOV BNOV C NC TC NTC BIO NBIO UNC SPRU131G Conditional Operations 6 6 1 Using Multiple Conditions Multiple conditions can be listed as operands of the conditional instructions If multiple conditions are listed all conditions must be met for the instruction to execute Only certain combinations of conditions are acceptable see Table 6 14 For each combination the conditions must be selected from Group 1 or Group 2 as follows J Group 1 You can select one condition from category A and one condi tion from category B The two conditions cannot be from the same catego ry For example you can test EQ and OV at the same time but you cannot test GT and NEQ at the same time The accumulator must be the s
50. BDRR is no longer being read and transferred to memory automatically by the ABU For explanation of how the serial port operates in standard mode when DRR is not being read refer to section 9 2 6 Serial Port Interface Exception Conditions on page 9 26 The sequence of events involved in the autobuffering process is summarized as follows 1 The ABU performs the memory access to the buffer 2 The appropriate address register is incremented unless the bottom of buff er has been reached in which case the address register is modified to point to the top of buffer address 3 Generate an BXINT or BRINT and update XH RH if the half buffer or bottom of buffer boundary has been crossed 4 Autodisable the ABU if this function has been selected and if the half buffer or bottom of buffer boundary has been crossed 9 3 3 System Considerations for BSP Operation This section discusses several system level considerations of BSP operation These considerations include initialization timing issues software initialization of the ABU and power down mode operation SPRU131G Serial Ports 9 49 Buffered Serial Port BSP Interface 9 3 3 1 Timing of Serial Port Initialization 9 50 Serial Ports The C54x device utilizes a fully static design and accordingly in both the serial port and the BSP serial port clocks need not be running between transfers or prior to initialization Therefore proper operation can still result if FSX FSR occurs
51. BMINT interrupt therefore indicates that one or more words may have been lost on the serial interface BMINT is useful for detecting buffer misalignment only when the buffer point er s are initially loaded with the top of the buffer address and a frame of data contains the same number of words as the buffer length These are the only conditions under which a frame sync occurring at a buffer address other than the top of the buffer constitute an error condition In cases where these condi tions are met a frame sync always occurs when the buffer pointer is at the top of the buffer address if the interface is functioning properly If BMINT is enabled under conditions other than those described interrupts can be generated under circumstances other than actual buffer misalignment In these cases BMINT should generally be masked in the IMR register so that the processor ignores this interrupt SPRU131G Buffered Serial Port BSP Interface BMINT is available when the device is operating in the auto buffering mode with continuous transfers the FIG bit cleared to 0 and with external serial clocks or frames 9 3 5 BSP Operation in Power Down Mode SPRU131G The C54x DSP offers several power down modes which allow part or all of the device to enter a dormant state and dissipate considerably less power than when running normally Power down mode may be invoked in several ways including either executing the IDLE instruction or driving th
52. BSCR A 16 bit register that defines the external memory bank size and enables or disables automatic insertion of extra cycles when accesses cross memory bank boundaries barrel shifter A unit that rotates bits in a word BDRR BDRRO BDRR1 BSP data receive register Two 16 bit registers used to receive data through the buffered serial ports BDRRO corresponds to buffered serial port 0 BDRR1 corresponds to buffered serial port 1 BDXR BDXRO BDXR1 BSP data transmit register Two 16 bit registers used to transmit data through the buffered serial ports BDXRO corresponds to buffered serial port 0 BDXR1 corresponds to buffered serial port 1 BG accumulator B guard bits An 8 bit register that contains bits 39 32 the guard bits of accumulator B BH accumulator B high word Bits 31 16 of accumulator B BIO A general purpose branch control input pin that can be used to moni tor the status of peripheral devices BK See circular buffer size register BKR BKRO BKR1 ABU receive buffer size register A 16 bit register that sets the size of the receive buffer for the autobuffering unit BKX BKX0 BKX1 ABU transmit buffer size register A16 bitregister that sets the size of the transmit buffer for the autobuffering unit BL accumulator B low word Bits 15 0 of accumulator B Glossary D 3 Glossary block repeat active flag BRAF A bit in status register 1 ST1 that indi cates whether or not a block repeat is cur
53. C54x device differs from the C5x device When the C54x device uses the AR pointed to by ARP the C54x device does not update the ARP with the same instruction Table 5 9 shows the assembler syntax comparing the C54x device to the following devices C20x C24x and C5x Figure 5 13 How ARP Indexes the Auxiliary Registers SPRU131G ARO0 16 index Syntax for devices Syntax for Syntax for devices Syntax for C20x C24x C5x C54x device C20x C24x C5x C54x device ARO 0 AR0 0 ARO O ARO 0 ARO BRO AR0 0B BRO ARO 0B Data Addressing 5 23 Indirect Addressing Figure 5 14 shows the indirect addressing instruction format for the ARP mode Table 5 10 describes the bits of the ARP mode instruction Figure 5 14 Indirect Addressing Instruction Format for Compatibility Mode 15 8 7 6 3 2 0 Table 5 10 Indirect Addressing Instruction Bit Summary Compatibility Mode Bit Name Function 15 8 Opcode This eight bit field contains the operation code for the instruction 7 1 the addressing mode used by the instruction is the indirect addressing mode 6 3 MOD This 4 bit modification field defines the type of indirect addressing section 5 5 3 Single Operand Address Modifications on page 5 13 describes the 16 ways to specify addressing types with the MOD field 2 0 ARF This 3 bit auxiliary register field defines the auxiliary register used for addressing ARF depends
54. CLKMD3 The modes corre sponding to the CLKMD pins are shown in Table 8 16 and Table 8 17 The VC5420 device does not have CLKMD pins Following reset the VC5420 operates in bypass mode PLL is off On Chip Peripherals 8 27 Clock Generator Table 8 16 Clock Mode Settings at Reset C54 1B C545A C546A C548 C549 C54 10 CLKMD1 0 0 0 1 0 CLKMD CLKMD2 CLKMD3 Reset Value Clock Mode 0 0 0000h Divide by 2 with external source 0 1 1000h Divide by 2 with external source 1 0 2000h Divide by 2 with external source 0 0 4000h Divide by 2 internal oscillator enabled 1 0 6000h Divide by 2 with external source 1 1 7000h Divide by 2 internal oscillator enabledt 0 1 0007h PLL x 1 with external source 1 1 Stop mode T Reserved on C549 and C5410 Table 8 17 Clock Mode Settings at Reset C5402 CLKMD1 0 0 0 8 28 CLKMD CLKMD2 CLKMD3 Reset Value Clock Mode 0 0 E007h PLL x 15 internal oscillator enabled 0 1 9007h PLL x 10 internal oscillator enabled 1 0 4007h PLL x 5 internal oscillator enabled 0 0 1007h PLL x 2 internal oscillator enabled 1 0 F007h PLL x 1 internal oscillator enabled 1 0000h 1 2 PLL disabled internal oscillator enabled 0 1 FOOOh 1 4 PLL disabled internal oscillator enabled 1 1 Reserved bypass mode Following reset the software programmable PLL can be programmed to any configuration desired The following clock mode pin combinations enable the PLL during reset CLKMD 3 1 000b
55. CMPM instruction Note that there is a latency of between 0 5 and 1 5 CLKOUT cycles in duration from CLKR CLKX switching to the new CLKR CLKX value being available in the SPC Note that even if the serial port is reset INO and IN1 can still be used as bit inputs and DRR and DXR as general purpose registers RRDY and XRDY Bits SPRU131G Bits 10 13 in the SPC are read only status bits that indicate various states of serial port operation Writes and reads of the serial port may be synchronized by polling RRDY bit 10 and XRDY bit 11 or by using the interrupts that they generate A transition from 0 to 1 of the RRDY bit indicates that the RSR contents have been copied to the DRR and that the received data may be read A receive interrupt RINT is generated upon this transition Serial Ports 9 15 Serial Port Interface XSREMPTY Bit RSRFULL Bit 9 16 Serial Ports A transition from 0 to 1 of the XRDY bit indicates that the DXR contents have been copied to XSR and that DXR is ready to be loaded with a new data word A transmit interrupt XINT is generated upon this transition Polling XRDY and RRDY in software may either substitute for or complement the use of serial port interrupts both polling and interrupts may be used together if so desired Note that with external FSX on the SP XSR is loaded directly as a result of loading DXR while on the BSP XSR is not loaded until an FSX occurs The XSREMPTY bit 12 indicates wh
56. CSSU The CSSU allows the C54x device to support various Viterbi butterfly algorithms used in equalizers and channel decoders The add function of the Viterbi operator see Figure 4 10 is performed by the ALU This function consists of a double addition function Meti D1 and Met2 D2 Double addition is completed in one machine cycle if the ALU is configured for dual 16 bit mode by setting the C16 bit in ST1 With the ALU configured in dual 16 bit mode all the long word 32 bit instructions become dual 16 bit arithmetic instructions T is connected to the ALU input as a dual 16 bit operand and is used as local storage in order to minimize memory access Table 4 6 shows the instructions that perform dual 16 bit ALU operations 4 24 Central Processing Unit SPRU131G Compare Select and Store Unit CSSU Figure 4 10 Viterbi Operator Old state New state D1 J New_Met1 2J Meti D2 If Met1 D1 gt Met2 D2 then New_Met1 Met1 D1 else New_Met1 Met2 D2 2J 1 Met2 J STNB 2 New_Met2 Old metrics New metrics Legend STNB Number of states Met Path metrics D Branch metrics Table 4 6 ALU Operations in Dual 16 Bit Mode Instruction Function Dual 16 Bit Mode DADD Lmenm src dst src 31 16 Lmem 31 16 dst 39 16 src 15 0 Lmem 15 0 dst 15 0 DADST Lmem dst Lmem 31 16 T gt dst 89 16 Lmem 15 0 T dst 15 0 DRSUB Lmenm src Lmem 31 16 s
57. D 17 TCSR definition D 17 TDDR definition TOL sianal A 434 p4 aSa A7 A 8 A 13 a18 TDM definition Index 18 TDM address TADD TDM channel select register TCSR 9 57 definition diagram TDM clock TCLk TDM data TDAT D 17 TDM data receive register TRCV 9 57 TDM data receive shift register TRSR 9 58 definition TDM data transmit register TDXR 9 57 definition TDM receive address register TRAD 9 57 diagram TDM receive interrupt TRINT definition TDM receive transmit address register TRTA Seer Bea diagram TDM cos content diagram me TDM serial port TDM 2 16 TDM serial por He register TSPC 9 57 definition diagram DLB bit FO bit Soft bit TDM bit TDM serial port data receive register TRCV definition TDM serial port interface 9 56 exception conditions operation 9 58 operation examples receive operation registers transmit operation TDM serial port receive address register TRAD definition TDM transmit interrupt TXINT definition D 17 TDO output TDO signal A 8 A 19 A 25 TDXR definition telecommunications applications temporary register T definition test bus controller test clock diagram A 12 test control TC definition third party support B 3 TIM definition time division multiplexed TDM definition time division multiplexing TDM basic operation definition timer EzE block diagram operation registers timer cont
58. DSP is in this mode CMPT 1 Compatibility mode In compatibility mode ARP selects the auxiliary register if ARF 0 Otherwise ARF selects the auxiliary register and the ARF value is loaded into ARP when the access is completed ARO in the assembly instruction indicates the auxiliary register selected by ARP in compatibility mode Te Note In some cases two data operands can be fetched at once This requires a different instruction format that is described in section 5 5 4 Dual Operand Address Modifications on page 5 19 5 5 2 ARAU and Address Generation Operation Two auxiliary register arithmetic units ARAUO and ARAU1 operate on the contents of the auxiliary registers The ARAUs perform unsigned 16 bit auxiliary register arithmetic operations Some addresses can be obtained by premodifying the auxiliary register The auxiliary registers can be _j Loaded with an immediate value using the STM instruction _j Loaded via the data bus by writing to the memory mapped auxiliary registers 1 Modified by the indirect addressing field of any instruction that supports indirect addressing _ Modified by the modify auxiliary register MAR instruction j Used as loop counters using the BANZ D instruction SPRU131G Data Addressing 5 11 Indirect Addressing Te Note Typically STM or MVDK is used to load auxiliary registers Both of these instructions allow the next instruction to use the new value in the reg
59. Execute Prefetch Fetch Decode Access Read Execute F i No No a ae A i4 or pipeline flush prefetch fetch IR i4 and conditional execution of i4 Prefetch Fetch Decode Access Read Execute i5 or pipeline flush PAB a5 IR i5 and conditional execution of i5 Prefetch Fetch Decode Access Read Execute Kari PAB PB IR er a GHEE SPRU131G Pipeline 7 21 Pipeline Operation Example 7 15 Delayed Conditional Call CCD Instruction in the Pipeline CCD Address al a2 a3 a4 a5 a6 b1 4 Prefetch Fetch 2 Instruction i1 CCD b1 cond i4 i5 i6 ji 3 4 5 6 7 8 9 10 11 12 Decode Access Read Execute Fetch Decode Access Read Pipeline flush Prefetch Fetch Prefetch Fetch Decode Access Read Execute Access Read Execute Prefetch Fetch Decode Access Read Execute No No pene Zz Es Decode PB i4 IR i4 PAB a4 i6 or j1 Prefetch Fetch PAB a5 PB i5 Prefetch Decode IR i5 Fetch Access Decode Read Access Execute HES Read Execute PAB PB IR 7 7 GOUE 7 22 Pipeline Example 7 16 and Example 7 17 show the pipeline s behavior during the execution of a conditional branch BC instruction and a delayed conditional branch BCD instruction The behavior of the conditional branch BC and the delayed conditional branch BCD instructions in the pipeline is similar to that of the CC and CCD instructio
60. For more details about the T register and the processes of multiplication see section 4 5 Multiplier Adder Unit on page 4 19 4 A dynamic execution time programmable shift count for instructions with shift operation such as the ADD LD and SUB instructions H A dynamic bit address for the BITT instruction O Branch metrics used by the DADST and DSADT instructions for ACS operation of Viterbi decoding In addition the EXP instruction stores the exponent value computed into T register and then the NORM instruction uses the T register value to normalize the number 3 3 4 5 Transition Register TRN The 16 bit transition TRN register holds the transition decision for the path to new metrics to perform the Viterbi algorithm The CMPS compare select max and store instruction updates the contents of TRN register on the basis of the comparison between the accumulator high word and the accumulator low word 3 3 4 6 Auxiliary Registers ARO AR7 The eight 16 bit auxiliary registers ARO AR7 can be accessed by the CPU and modified by the auxiliary register arithmetic units ARAUs The primary function of the auxiliary registers is to generate 16 bit addresses for data space However these registers can also act as general purpose registers or counters For information about the role the auxiliary registers play in data memory addressing see section 5 5 Indirect Addressing on page 5 10 3 3 4 7 Stack Pointer Register SP
61. INTR LD ARP LD DP MVMM ORM RC D RESET RET D Repeating a Single Instruction Description Add long constant to data memory AND data memory with long constant Unconditional branch Branch to accumulator address Branch on auxiliary register not 0 Conditional branch Call to accumulator address Unconditional call Conditional call Compare with auxiliary register Long word 32 bit store Far branch unconditionally Far branch to location specified by accumulator Far call subroutine at location specified by accumulator Far call unconditionally Far return Enable interrupts and far return from interrupt Idle instructions Interrupt trap Load auxiliary register pointer ARP Load data page pointer DP Move memory mapped register MMR to another MMR OR data memory with long constant Conditional return Software reset Unconditional return Program Memory Addressing 6 21 Repeating a Single Instruction Table 6 18 Nonrepeatable Instructions Continued 6 22 Instruction RETE D RETF D RND RPT RPTB D RPTZ RSBX SSBX TRAP XC XORM Program Memory Addressing Description Return from interrupt Fast return from interrupt Round accumulator Repeat next instruction Block repeat Repeat next instruction and clear accumulator Reset status register bit Set status register bit Software trap Conditional execute XOR data memory with long constant SPRU131G Repeating a Block of Instructions
62. Memory 3 2 3 Program Memory Address Map and On Chip ROM Contents At device reset the reset interrupt and trap vectors are mapped to the 128 word page starting at address FF80h in program memory space However these vectors can be remapped to the beginning of any 128 word page in program space after device reset This feature facilitates moving the vector table out of the boot ROM and then removing the ROM from the memory map For details on remapping the vectors see section 6 10 9 Remapping Interrupt Vector Addresses on page 6 36 Note In the on chip ROM 128 words are reserved for device testing purposes Application code written to be implemented in on chip ROM must reserve these 128 words at addresses FFOOh FF7Fh in program space 3 2 4 On Chip ROM Code Contents and Mapping 3 18 Memory The C54x devices provide a variety of ROM sizes 2K 4K 16K 28K or 48K words For device specific on chip ROM configurations see the device data sheet On C54x devices with on chip bootloader ROM the 2K words at F800h to FFFFh may contain one or more of the following depending on the specific device _j A bootloader program that boots from the serial ports external memory an I O port or the host port interface if present A 256 word u law expansion table A 256 word A law expansion table A 256 word sine look up table oo O O An interrupt vector table Figure 3 15 shows which of these items are on a par
63. NOP the stack Two NOPs are required to NOP use the new value of SP LD 50h A Example 7 35 SP Load With a 3 Cycle Latency in Compiler Mode CPL 1 DP 0 STLM A ARI This instruction does not affect pipeline latency STH A SP This SP update requires a three cycle NOP latency since the next instruction NOP uses SP when CPL is 1 NOP LD 50h A SPRU131G Pipeline 7 53 Pipeline Latencies 7 5 5 2 SP Used in Push Pop Call Return FRAME and MVMM Operations A pipeline conflict occurs if two conditions are simultaneously met _j An instruction updates SP J The next instruction uses the stack for a push pop call return FRAME or MVMM operation The conflict occurs because the second instruction tries to use SP in a pipeline stage that occurs before the stage in which the previous instruction updates SP Table 7 10 lists instructions that do not have any latency in updating SP when the CPU is notin compiler mode CPL 0 These instructions should be used wherever possible to avoid conflicts Table 7 10 Pipeline Protected Instructions to Update SP in Noncompiler Mode CPL 0 To do this Use this instruction Write an immediate value to SP STM lk SPT Copy a memory location to SP MVDK Smem SPT Copy the contents of an ARx or BK to SP MVMM MMR SP Move SP by a frame FRAME k t See Table 7 11 for one possible conflict with these instructions Table 7 11 lists the laten
64. Ne Ne ADD AR1 A SUB AR2 A STH A AR1 endloop SPRU131G Pipeline 7 73 Pipeline Latencies Example 7 56 SRCCD Instruction With a 3 Cycle Latency RPTB endloop 1 SRCCD AR3 ALEQ This ensures that current value of NOP BRC will be written to memory NOP NOP endloop There is also a 5 to 6 cycle latency when writing a new value to BRC from with ina RPTB loop The latencies described in Table 7 25 are relevant only if BRC is modified while a RPTB loop is active See Example 7 57 for details Table 7 25 Latencies for Updating BRC From Within an RPTB Loop Instruction Latency STM lk BRC The next 5 instruction words must not contain ST lk BRC the last instruction in the RPTB loop MVDK Smem BRC MVMD MMR BRC All other instructions that modify The next 6 instruction words must not contain BRC the last instruction in the RPTB loop Example 7 57 Modifying BRC From Within an RPTB Loop RPTB endloop 1 XC 2 Condition If Condition is evaluated as MVDK 5h BRC true write the new count value to BRC LD ARI A These six instructions provide ADD AR2 A sufficient latency for the new SUB AR3 A BRC value to take effect before LD AR4 T the next iteration begins MPYA A STL A AR3 endloop 7 5 8 2 Deactivating the Block Repeat Active Flag BRAF 7 74 Pipeline The C54x DSP sets the block repeat active flag BRAF to 1 to indic
65. No i i paa wje f e Prefetch Fetch Decode Access Read Execute PAB _ E F j pe esfe O e Prefetch Fetch Decode Access Read Execute A PAB PB IR i6 or j1 jes en tis O for 7 24 Pipeline SPRU131G Interrupts and the Pipeline 7 2 Interrupts and the Pipeline SPRU131G Example 7 18 shows the pipeline behavior when an interrupt is taken As shown in Example 7 18 if an interrupt is serviced at the end of cycle 3 an INTR instruction is automatically placed into the decode stage of the pipeline during the next cycle 4 The instruction i2 is not decoded because the INTR instruction is placed into the pipeline at that stage During the next three cycles the instructions that have already been decoded are executed Cycles 7 8 and 9 are taken by the INTR instruction The first instruction in the ISR RETFD is executed in cycle 10 Cycles 11 and 12 are consumed by the two 1 word instructions that constitute the two delay slots of the RETFD instruc tion In the following cycle instruction i2 is executed completing the return from the ISR As shown in the figure interrupt overhead the number of cycles required to branch to an ISR is only three cycles The return from the interrupt takes only one cycle because RETFD is a single cycle instruction Because only four words are reserved for each interrupt in the interrupt vector table if an ISR requires more than four instruction words it must be
66. Processing Unit SPRU131G 4 4 Barrel Shifter SPRU131G Barrel Shifter The barrel shifter is used for scaling operations such as Prescaling an input data memory operand or the accumulator value before an ALU operation Lj Performing a logical or arithmetic shift of the accumulator value 41 Normalizing the accumulator _ Postscaling the accumulator before storing the accumulator value into data memory The 40 bit shifter see Figure 4 7 on page 4 18 is connected as follows I The input is connected to m DB for a 16 bit data input operand m DB and CB for a 32 bit data input operand m Either one of the two 40 bit accumulators J The output is connected to E One of the ALU inputs m The EB bus through the MSW LSW write select unit The SXM bit controls signed unsigned extension of the data operands when the bit is set sign extension is performed Some instructions such as ADDS LDU MAC and SUBS operate with unsigned memory operands and do not perform sign extension regardless of the SXM value The shift count determines how many bits to shift Positive shift values corre spond to left shifts whereas negative values correspond to right shifts The shift count is specified as a 2s complement value in several ways depending on the instruction type An immediate operand the accumulator shift mode ASM field of ST1 or T can be used to define the shift count LJ A4or 5 bit immediate value specified in the
67. Robotics Security access Military Image processing Missile guidance Navigation Radar processing Radio frequency modems Secure communications Sonar processing Voice Speech Speaker verification Speech enhancement Speech recognition Speech synthesis Speech vocoding Text to speech Voice mail SPRU131G TMS320C54x DSP Overview 1 2 TMS320C54x DSP Overview SPRU131G The C54x DSP has a high degree of operational flexibility and speed It combines an advanced modified Harvard architecture with one program memory bus three data memory buses and four address buses a CPU with application specific hardware logic on chip memory on chip peripherals and a highly specialized instruction set Spinoff devices that combine the C54x CPU with customized on chip memory and peripheral configurations have been and continue to be developed for specialized areas of the electronics market The C54x devices offer these advantages m m Enhanced Harvard architecture built around one program bus three data buses and four address buses for increased performance and versatility Advanced CPU design with a high degree of parallelism and application specific hardware logic for increased performance A highly specialized instruction set for faster algorithms and for optimized high level language operation Modular architecture design for fast development of spinoff devices Advanced IC processing technology for increased
68. Routine 0 00 e eee eens Serial Port Interrupt Service Routine 00 cc eee BSP Transmit Initialization Routine 0 0 eee ee eens BSP Receive Initialization Routine 0 0 eee eens TDM Serial Port Transmit Initialization Routine 00 ee eee eee TDM Serial Port Transmit Interrupt Service Routine 0 cece eee eee TDM Serial Port Receive Initialization Routine 0 ccc eee eee eee TDM Serial Port Receive Interrupt Service Routine 00 ee cece eee eee Key Timing for a Single Processor System Without Buffers 000 0000s 2 Key Timing for a Single or Multiple Processor System With Buffered Input and Output ies si ti aati Bank tthe vein anda eens Ad Ea A AAEE A aA aaa alae ah AE A 8 A 3 Key Timing for a Single Processor System Without Buffering SPL A 19 A 4 Key Timing for a Single or Multiprocessor System With Buffered Input and Output SPL i scisevicce nro parni aa aea ee dwukeedierd bias ea eee eee A 19 ae ee eee se ae Oo NOOA ON l xxxii Examples SPRU131G Chapter 1 Introduction The TMS320C54x DSP is a fixed point digital signal processor DSP in the TMS320 DSP family The C54x DSP meets the specific needs of real time embedded applications such as telecommunications The C54x central processing unit CPU with its modified Harvard architec ture features minimized power consumption and a h
69. The TMS320C54x DSP is a fixed point digital signal processor DSP in the TMS320 DSP family This book serves as a reference for the C54x DSP and provides information for developing hardware and software applications using the C54x DSP This user s guide contains limited information about the enhanced peripherals available on some C54x devices For detailed information on the enhanced peripherals see TMS320C54x DSP Enhanced Peripherals Reference Guide literature number SPRU302 How to Use This Manual SPRU131G The following table summarizes the TMS320C54x DSP information contained in this book If you are looking for information about Turn to these chapters Addressing modes Chapter 5 Data Addressing Chapter 6 Program Memory Addressing Buffered serial port Chapter 9 Serial Ports Bus structure Chapter 2 Architectural Overview Clock generator Chapter 2 Architectural Overview Chapter 8 On Chip Peripherals CPU architecture Chapter 2 Architectural Overview Chapter 4 Central Processing Unit External bus Chapter 10 External Bus Operation Hold mode Chapter 10 External Bus Operation Host port interface Chapter 8 On Chip Peripherals How to Use This Manual If you are looking for information about Interrupts Memory On chip peripherals Overview of the C54x Parallel I O Ports Power down modes Program control Pipeline latencies Reset ROM code submission to TI Serial ports Status register
70. The accumulator contents remain unchanged during the operation See Example 4 2 on page 4 9 for examples of saturation on store operations t These bits are only supported on C54x devices with revision A or later or on C54x devices numbered C548 or greater 4 8 Central Processing Unit SPRU131G Example 4 1 Use of SMUL Bit MAC ARI A A T AR1 Data Memory 100h MAC ARI A A T AR1 Data Memory 100h CPU Status and Control Registers SMUL 1 FRCT 1 OVM 1 SXM Before Instruction FF FFFF FFF 8000h 100h 8000h 1 A T AR1 Data Memory 100h SMUL 0 FRCT 1 OVM 1 SXM Before Instruction FF FEFFFFFFF 8000h 101h 8000h Example 4 2 Use of SST Bit STHA 4 AR1 A AR1 Data Memory 100h DSTB AR3 B AR3 Data Memory 102h 103h SPRU131G SXM 1 SST 1 Before Instruction 7FFFFF 0000h 100h 5555h SXM 0 SST 1 Before Instruction 8F FFFF 0000h 103h 1234h 5678h A T AR1 Data Memory 100h A AR1 Data Memory 100h B AR3 Data Memory 102h 103h After Instruction 8000h 1 After Instruction 007FFFFFFFh 8000h 102h 8000h 7FFFFF0000h 101h 7FFFh 8F FFFF 0000h 101h OFFFFh OFFFFh gt b te te gt gt wo on O O ie o 5 5 Central Processing Unit 4 9 Arithmetic Logic Unit ALU 4 2 Arithmetic Logic Unit ALU The 40 bit ALU shown in Figure 4 4 implements a
71. Vcc Voc A Emulator header JTAG device EMUO PD EMUO EMU1 d EMU1 TRST TRST TMS TMS TDI TDI TDO TDO TCK i TCK TCK_RET V GND Figure A 5 shows the connections necessary for buffered transmission signals The distance between the emulation header and the processor is greater than 6 inches Emulation signals TMS TDI TDO and TCK_RET are buffered through the same device package A 10 Design Considerations for Using XDS510 Emulator SPRU131G Connections Between the Emulator and the Target System Figure A 5 Emulator Connections With Signal Buffering SPRU131G Greater than 6 inches Voc Voc JTAG device Emulator header A EMUO EMUO PD EMU1 l EMU1 TRST TRST TMS lt TMS TDI TDI TDO gt TDO TCK TCK gt TCK_RET v GND The EMUO and EMU1 signals must have pullup resistors connected to Vcc to provide a signal rise time of less than 10 us A 4 7 kQ resistor is suggested for most applications The input buffers for TMS and TDI should have pullup resistors connected to Vcc to hold these signals at a known value when the emulator is not connected A resistor value of 4 7 kQ or greater is suggested To have high quality signals especially the processor TCK and the emulator TCK_RET signals you may have to employ special care when routing the printed wiring board trace You also may have to use termination resistors to match the trace impedan
72. With Delayed Frame Sync in External Frame Sync Mode SP Tx f f 9 20 DX FO 1 XRDY SP XINT SP oo EOE CBX A h eaul XSREMPTY LA e 2 N a e 4 SP DXR loaded loaded withA with A Serial Ports A XSR t A DXR XSR loaded loaded with B with B On the BSP Figure 9 8 since DXR was reloaded with B shortly after being loaded with A when the delayed frame sync finally occurs B is transmitted on DX After the transmit the transmitter remains frozen until the next frame sync When frame sync finally occurs B is again transmitted on DX Note that when B is loaded into DXR a DXR to XSR copy of B does not occur immediately since the BSP requires a frame sync to initiate transmitting Any subsequent writes to DXR before the next delayed frame sync occurs overwrite B in the DXR SPRU131G Serial Port Interface Figure 9 8 Burst Mode Serial Port Transmit Operation With Delayed Frame Sync in External Frame Sync Mode BSP BPI PPP PPP PPS FSX TXM 0 J a i a XSREMPTY DX FO 1 C81 X B1 X_B2 MSB LSB XRDY Moe fe a a a i a a a BSP XINT Aaa a T aa cae DXR loaded with A A DXR XSR XSR loaded loaded loaded with B with B with B During a receive operation shifting into RSR begins on the falling edge of the CLKR cycle after frame sync has gone low as shown in Figure 9 9 Then
73. _ Buffered serial port interface J Multichannel buffered serial Port McBSP interface Lj Time division multiplexed serial port interface These peripherals are controlled through registers that reside in the memory map The serial ports are synchronized to the core CPU by way of interrupts Topic Page 9 1 Introduction to the Serial Ports 200c cece eee eee eeeee 8 9 2 Serial Port Interface 22 20 5005 c 002000 s ee nneeecw coma ses 9 3 Buffered Serial Port BSP Interface eeeeeeeeeeeee 9 33 9 4 Time Division Multiplexed TDM Serial Port Interface 9 56 9 1 Introduction to the Serial Ports 9 1 Introduction to the Serial Ports The C54x devices implement a variety of types of flexible serial port interfaces These serial port interfaces provide full duplex bidirectional communication with serial devices such as codecs serial analog to digital A D converters and other serial systems The serial port interface signals are directly compatible with many industry standard codecs and other serial devices The serial port may also be used for interprocessor communication in multiprocessing applications the time division multiplexed TDM serial port is especially optimized for multiprocessing Table 9 1 lists the serial ports available on various C54x devices Table 9 1 Serial Ports on the TMS320C54x Devices Standard MultiChannel Time Division Synchron
74. aca he arti oS ath ate tin asta a eed oc a aces aioe Ay at deten A Ath at a 6 4 1 Unconditional Cals simiri dnddadondhe patardw dhs baad ne Had o ind deed 6 4 2 Conditional GallS css c cid asirni se dinn a ada ad avewee sadn ERNE EERE 643 Far CAMS stoic se on 4 45 toi atanice Sadana n dea dint AAE i Contents 6 9 POUMES cscwdsessedeetaseeudssaneteete ieee AERE 6 5 1 Unconditional Returns 0 eee eee eee 6 5 2 Conditional Returns 00 cee eee 65 3 lt FarReuins s6siase sretecsetdesinetiiadestadigandiniadeagebeiaad eat 6 6 Conditional Operations ssteissi sieis iaasa nii ete eee e eens 6 6 1 Using Multiple Conditions 00 cece tees 6 6 2 Conditional Execute XC Instruction 0060 6 6 3 Conditional Store Instructions 0 0 cece eee 6 7 Repeating a Single Instruction 0 0 ccc eee 6 8 Repeating a Block of Instructions 0 0 e eee eens 6 9 Reset Operation s ts2 207 4evs dade Suieieeede dade ee Veda tiededs ceeds sadeeed 6 10 INtermUpts ccc Rie cei EAE ode mea dd ka ha doe eddie owen aidan 6 10 1 Interrupt Flag Register IFR 00 eee eee 6 10 2 Interrupt Mask Register IMR 00 eee 6 10 3 Phase 1 Receive Interrupt Request 0c c cece eee eee 6 10 4 Phase 2 Acknowledge Interrupt 0 00 cece eee 6 10 5 Phase 3 Execute Interrupt Service Routine ISR 6 10 6 Interrupt Context Save teens GIO IntermuptLa
75. analysis menu is used These seven important points apply to the circuitry shown in Figure A 11 and the timing shown in Figure A 12 _ Open collector drivers isolate each board The EMU0 1 pins are tied together on each board _j Atthe board edge the EMU0 1 signals are split to provide both input and output connections This is required to prevent the open collector drivers from acting as latches that can be set only once J The EMU0 1 signals are bused down the backplane Pullup resistors must be installed as required SPRU131G Design Considerations for Using XDS510 Emulator A 21 Emulation Design Considerations J The bused EMU0 1 signals go into a programmable logic array device PAL whose function is to generate a low pulse on the EMU0 1 IN signal when a low level is detected on the EMU0 1 OUT signal This pulse must be longer than one TCK period to affect the devices but less than 10 us to avoid possible conflicts or retriggering once the emulation software clears the device s pins During a RUNB debugger command or other external analysis count the EMU0 1 pins on the target device become totem pole outputs The EMU1 pin is a ripple carry out of the internal counter EMUO becomes a proces sor halted signal During a RUNB or other external analysis count the EMU0 1 IN signal to all boards must remain in the high disabled state You must provide some type of external input XCNT_ENABLE to the PAL to disable the P
76. and Control Registers Table 4 2 Status Register 1 ST1 Bit Summary Continued Bit Name 9 OVM 8 SXM 7 C16 6 FRCT 5 CMPT 4 0 ASM SPRU131G Reset Value Function 0 Overflow mode OVM determines what is loaded into the destination accumulator when an overflow occurs OVM 0 An overflowed result from either the ALU or the multiplier s adder overflows normally in the destination accumulator OVM 1 The destination accumulator is set to either the most positive value 00 7FFF FFFFh or the most negative value FF 8000 0000h upon encountering an overflow The SSBX and RSBxX instructions set and reset OVM respectively Sign extension mode SXM determines whether sign extension is performed SXM 0 Sign extension is suppressed SXM 1 Data is sign extended before being used by the ALU SXM does not affect the definitions of certain instructions the ADDS LDU MAC and SUBS instructions suppress sign extension regardless of SXM value The SSBX and RSBX instructions set and reset SXM respectively Dual 16 Bit double precision arithmetic mode C16 determines the arithmetic mode of the ALU s operation Ci6 0 The ALU operates in double precision arithmetic mode C16 1 The ALU operates in dual 16 bit arithmetic mode Fractional mode When FRCT is 1 the multiplier output is left shifted by one bit to compensate for an extra sign bit Compatibility mode CMPT determines the compatibility mode for the ARP CMPT
77. and that receptions are currently placing data in the second half of the buffer RH 1 The second half of the buffer has been filled and that recep tions are currently placing data in the first half of the buffer BRE 0 Autobuffering Receive Enable This control bit enables autobuffering receive BRE 0 Autobuffering is disabled and the serial port interface operates in standard mode BRE 1 Autobuffering is enabled for the receiver HALTX 0 Autobuffering Transmit Halt This control bit determines whether autobuffering transmit is halted when the current half of the buffer has been transmitted HALTX 0 Autobuffering continues to operate when the current half of the buffer has been transmitted HALTX 1 Autobuffering is halted when the current half of the buffer has been transmitted When this occurs the BXE bit is cleared to 0 and the serial port continues to operate in standard mode Serial Ports SPRU131G Buffered Serial Port BSP Interface Table 9 12 BSP Control Extension Register BSPCE Bit Summary ABU Control Bits Continued Bit Name 11 XH 10 BXE 9 0 Serial Port control Reset value Function 0 Transmit Buffer Half Transmitted This read only bit indicates which half of the transmit buffer has been transmitted Reading XH when the XINT interrupt occurs seen either as a program interrupt or by polling IFR is a convenient way to identify which boundary has just been crossed XH 0 The first half of the buffer
78. are allowed Table 10 6 on page 10 10 shows the relationship between BNKCMP and the address range 11 PS DS Program read data read access Inserts an extra cycle between consecutive accesses of program read and data read or data read and program read PS DS 0 No extra cycles are inserted by this feature except when banks are crossed PS DS 1 One extra cycle is inserted between consecutive accesses of program read and data read or data read and program read 10 9 Reserved These bits are reserved 8 IPIRQ Interprocessor interrupt request bit 7 3 Reserved These bits are reserved 2 HBH HPI bus holder bit SPRU131G External Bus Operation 10 9 External Bus Control Table 10 5 Bank Switching Control Register BSCR Bit Summary Continued Reset Bit Name Value Function 1 BH 0 Bus holder Controls the bus holder BH 0 The bus holder is disabled BES The bus holder is enabled The data bus D 15 0 is held in the previous logic level 0 EXIO 0 External bus interface off The EXIO bit controls the external bus off function EXIO 0 The external bus off function is disabled EXIO 1 The external bus off function is enabled The address bus data bus and control signals become inactive after completing the current bus cycle Table 10 7 on page 10 11 lists the state of the signals when the external bus interface is disabled The DROM MP MC and OVLY bits in PMST and the HM bit in ST1 cannot be modified Table 10 6 sum
79. are being performed on the same dual access memory block 7 3 1 Resolved Conflict Between Instruction Fetch and Operand Read If a dual access memory block is mapped in both program and data spaces an instruction fetch will conflict with a data operand read access if they are performed on the same memory block The C54x DSP resolves this conflict automatically by delaying the instruction fetch by one cycle as shown in Example 7 19 In the figure it is assumed that instructions i2 and i3 do not access the dual access memory block where the code resides SPRU131G Pipeline 7 29 Dual Access Memory and the Pipeline Example 7 19 Instruction Fetch and Operand Read LD AR2 A i2 i3 i4 LD AR2 A supposed to occur here Prefetch AR2 is pointing to the same DARAM block where the code resides Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute Read PB Prefetch Fetch Decode Access Read Execute suppose si our here a a AAS Pot fd i4 delayed instruction fetch Prefetch Fetch Decode Access Read Execute Legend Where a memory access actually Where instruction fetch is supposed to occur occurs 7 3 2 Resolved Conflict Between Operand Write and Dual Operand Read 7 30 Pipeline Another conflict arises if a single operand write instruction is followed by an instruction that does not perform a write access and this instruction is fo
80. are met The possible condi tions are given in Table 6 13 on page 6 16 If all the conditions are met PC is loaded with the second word of the branch instruction which contains the address to branch to and execution continues at this address By the time the conditions have been tested the two instruction words follow ing the conditional branch instruction have already been fetched and are in the pipeline How these two instruction words are handled depends in part on whether the branch is nondelayed or delayed LJ Nondelayed If all the conditions are met these two instruction words are flushed from the pipeline so that they are not executed and then execution continues at the branched to address If the conditions are not met the two instruction words are executed instead of the branch J Delayed The one 2 word instruction or two 1 word instructions following the branch instruction are executed This allows you to avoid flushing the pipeline which requires extra cycles The conditions tested are not affected by the instructions following the delayed branch Note The two words following a delayed instruction cannot be an instruction that causes a PC discontinuity a branch call return or software interrupt a Table 6 5 shows the conditional branch instructions and the number of cycles needed to execute these instructions Because conditional branches use conditions determined by the execution of the previous instruct
81. as the last data bit is being received the contents of the RSR are transferred to the DRR on the falling edge of CLKR and RRDY goes high generating a receive interrupt RINT Figure 9 9 Burst Mode Serial Port Receive Operation er f f f S S A VA VS VN VN DV EA a a ae a ae eS ee ee es a Somme eae DR FO 1 AZ XA AA KAS _XK_AG_K_AZ_X_AB_ B1 _B2 LSB MSB RRDY e c RINT 1 l L M aMsaMtlss SPRU131G DRR DRR loaded read from RSR If the DRR from a previous receive has not been read and another word is received no more bits can be accepted without causing data corruption since DRR and RSR are both full In this case the RSRFULL bit is set indicating this condition On the SP this occurs with the next FSR on the BSP RSRFULL is set on the falling edge of CLKR during the last bit received RSRFULL timing on both the SP and BSP is shown in Figure 9 10 Serial Ports 9 21 Serial Port Interface Figure 9 10 Burst Mode Serial Port Receive Overrun er KL RAPRARPLPEAP RSs FSR y J DR CA1 XX AB B19 5 MSB LSB SB 2 JSE RRDY RINT RSRFULL SP a ee a eS RSRFULL BSP i a es ee eee m 9 22 Serial Ports DRR loaded Read A with A from DRR Unlike transmit underflow overrun RSRFULL 1 constitutes an actual error condition While DRR contents are preserved in overrun its occurrence
82. because it implies that one device controls the other which is not the case and TCSR must be set to prevent slot contention Consequently the remaining devices in the TDM configuration use these signals as inputs Figure 9 31 b shows that TCLKX and TCLKR are externally tied together to form the TCLK line Also TFRM and TADD originate from the TFSX and TFSR pins respectively This is done to make the TDM serial port also easy to use in standard mode TDM port operation is controlled by six memory mapped registers The layout of these registers is shown in Figure 9 32 The TRCV and TDXR registers have the same functions as the DRR and DXR registers respectively described in section 9 2 Serial Port Interface The TSPC is identical to the SPC except that bit 0 serves as the TDM mode enable control bitin the TSPC This bit configures the port in TDM mode TDM 1 or stand alone mode TDM 0 In stand alone mode the port operates as a standard serial port as described in section 9 2 Refer to section 9 4 6 Examples of TDM Serial Port Interface Operation on page 9 64 for additional information about the function of the bits in these registers Serial Ports 9 59 Time Division Multiplexed TDM Serial Port Interface Figure 9 32 TDM Serial Port Registers Diagram TRCV 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Receive Data TDXR Transmit Data TSPC TCSR Free Soft X X X x xrpy RRDY N1 iNo ARST xRST Txu mc
83. bit or 16 bit data packets The continuous mode provides operation that once initiated requires no further frame synchronization pulses FSR and FSX when transmitting at maximum packet frequency The serial ports are fully static and thus will function at arbitrarily low clocking frequencies The maximum operating frequency for the standard serial port of one fourth of CLKOUT 10 Mbit s at 25 ns 12 5 Mbit s at 20 ns is achieved when using internal serial port clocks The maximum operating frequency for the BSP is CLKOUT When the serial ports are in reset the device may be configured to turn off the internal serial port clocks allowing the device to run in a lower power mode of operation SPRU131G Serial Port Interface 9 2 1 Serial Port Interface Registers The serial port operates through the three memory mapped registers SPC DXR and DRR and two other registers RSR and XSR that are not directly accessible to the program but are used in the implementation of the double buffering capability These five registers are listed in Table 9 3 Table 9 3 Serial Port Registers SPRU131G Address Register Description t DRR Data receive register t DXR Data transmit register t SPC Serial port control register RSR Receive shift register XSR Data transmit shift register t See section 8 2 Peripheral Memory Mapped Registers d Data receive register DRR The 16 bit memory mapped data receive register DRR holds the inco
84. buffered data registers independent framing and clocking for receive and transmit and a flexible clock generator that can be programmed for internal or external shift clocking multiplier A 17 bit x 17 bit multiplier that generates a 32 bit product The multiplier executes multiple operations in a single cycle and operates using either signed or unsigned 2s complement arithmetic nested interrupt A higher priority interrupt that must be serviced before completion of the current interrupt service routine ISR An executing ISR can set the interrupt mask register IMR bits to prevent being suspended by another interrupt nonmaskable interrupt An interrupt that can be neither masked by the interrupt mask register IMR nor disabled by the INTM bit of status register 1 ST1 OVA overflow flag A A bit in status registerO STO that indicates the overflow condition of accumulator A D 12 Glossary SPRU131G SPRU131G Glossary OVB overflow flag B A bit in status register 0 STO that indicates the overflow condition of accumulator B overflow Acondition in which the result of an arithmetic operation exceeds the capacity of the register used to hold that result overflow flag A flag that indicates whether or not an arithmetic operation has exceeded the capacity of the corresponding register OVLY See RAM overlay OVM overflow mode bit A bitin status register 1 ST1 that specifies how the ALU handles an overflow after a
85. buses four program data buses and four address buses 1 The program bus PB carries the instruction code and immediate operands from program memory _ Three data buses CB DB and EB interconnect to various elements such as the CPU data address generation logic program address generation logic on chip peripherals and data memory Mm The CB and DB carry the operands that are read from data memory m The EB carries the data to be written to memory J Four address buses PAB CAB DAB and EAB carry the addresses needed for instruction execution The C54x DSP can generate up to two data memory addresses per cycle using the two auxiliary register arithmetic units ARAUO and ARAU 1 The PB can carry data operands stored in program space for instance a coefficient table to the multiplier and adder for multiply accumulate operations or to a destination in data space for data move instructions MVPD and READA This capability in conjunction with the feature of dual operand read supports the execution of single cycle 3 operand instructions such as the FIRS instruction The C54x DSP also has an on chip bidirectional bus for accessing on chip peripherals This bus is connected to DB and EB through the bus exchanger in the CPU interface Accesses that use this bus can require two or more cycles for reads and writes depending on the peripheral s structure Table 2 1 summarizes the buses used by various types of access
86. can often result in loss of other received data Overrun is handled differently on the SP and on the BSP On the SP the contents of RSR are preserved on overrun but since RSRFULL is not set to 1 until the next FSR occurs after the overflowing reception incoming data usually begins being lost as soon as RSRFULL is set Data loss can only be avoided if RSRFULL is polled in software and the DRR is read immediately after RSRFULL is setto 1 This is normally possible only ifthe CLKR frequency is slow with respect to CLKOUT since RSRFULL is set on the falling edge of CLKR during FSR and data begins being received on the following rising edge of CLKR The time available for polling RSRFULL and reading the DRR to avoid data loss is therefore only half of one CLKR cycle On the BSP RSRFULL is set on the last valid bit received but the contents of RSR are never transferred to DRR therefore the complete transferred word in RSR is lost If the DRR is read clearing RSRFULL before the next FSR occurs subsequent transfers can be received properly Overrun and various other serial port exception conditions such as the occur rence of frame sync during a receive are discussed in further detail in section 9 2 6 Serial Port Interface Exception Conditions on page 9 26 If the serial port receiver is provided with FSR pulses significantly longer than one CLKR cycle timing of data reception is effected in a similar fashion as with long FSX pulses Wit
87. can also be inserted when an access cross es from program memory to data memory or on selected devices from one program memory page to another program memory page This extra cycle prevents bus contention by allowing memory devices to release the bus before other devices start driving the bus The size of memory bank for bank switch ing logic is defined by the bank switching control register BSCR See section 10 3 2 Bank Switching Logic on page 10 9 for more details 2 7 4 Hardware Timer The C54x device features a 16 bit timing circuit with a 4 bit prescaler The timer counter is decremented by 1 at every CLKOUT cycle Each time the counter decrements to 0 a timer interrupt is generated The timer can be stopped restarted reset or disabled by specific status bits See section 8 4 Timer on page 8 21 for more details 2 7 5 Clock Generator SPRU131G There are two basic options for clock generation on the C54x devices internal oscillator or aphase locked loop PLL circuit In the first option the CPU clock is generated by dividing the input clock provided as X2 CLKIN by 1 2 or 4 The second option uses a PLL circuit to generate a CPU clock that is a multiple of the frequency of the input clock The PLL method allows a high frequency internal CPU clock to be generated from a low frequency external clock Maintaining a low frequency clock off chip reduces system power consumption reduces clock generated EMI and facilitates the u
88. cycle after MSTRB changes The timing diagram illustrates these concepts 1 MSTRB goes high at the end of every write cycle to disable the memory while the address and or R W signal changes Each write takes two cycles A read following a write takes two cycles Figure 10 9 Memory Interface Operation for Write Write Read Data Write data Write data t Assuming that an I O write preceded the first memory write 10 16 External Bus Operation SPRU131G External Bus Interface Timing Figure 10 10 shows a read read write sequence using MSTRB active and one wait state Because the reads are normally one cycle they are extended by one additional cycle for the wait state However the write which is already two cycles is extended to three cycles Figure 10 10 Memory Interface Operation for Read Read Write Program Space Wait States Data Write data R W ea s i TT Tn Naan a Wait state lt _ _ gt 1 Wait state k j Wait state SPRU131G External Bus Operation 10 17 External Bus Interface Timing 10 4 2 I O Access Timing Figure 10 11 In I O accesses the active portion of reads and writes lasts two cycles with no wait states Otherwise the timing for these accesses is the same as for memory accesses During these cycles the address changes on the falling edge of CLKOUT except for a mem
89. detail in section 4 1 CPU Sta tus and Control Registers on page 4 2 3 3 4 11 Program Counter Extension Register XPC 3 4 I O Memory SPRU131G The program counter extension register XPC contains the upper 7 bits of the current program memory address See section 3 2 5 Extended Program Memory on page 3 20 for more information about extended memory The C54x devices offer an I O memory space in addition to the program memory and data memory spaces The I O memory space is a 64K word address space 0000h FFFFh and exists only external to the device Two instructions PORTR and PORTW are used to access this space Read timings vary from those of the program memory and data memory spaces to facilitate access to individual I O mapped devices rather than to memories For details of external bus operation and control for I O accesses see Chapter 10 External Bus Operation Memory 3 29 Program and Data Security 3 5 Program and Data Security The C54x devices have two staged security options on chip ROM security and ROM RAM security See Table 3 4 for a summary of the memory security modes See Table 3 5 for a summary of the HPI memory access while in the memory security modes Table 3 4 Memory Security Modes ROM ROM RAM Emulator cannot run Emulator cannot run Instructions from on chip ROM can read data from on chip ROM Instructions from on chip RAM or external program cannot read data from on
90. device these ports are identical but independent Each synchronous serial port can operate at up to one fourth the machine cycle rate CLKOUT The synchronous serial port transmitter and receiver are double buffered and individually controlled by maskable external interrupt signals Data is framed either as bytes or as words 2 8 2 Buffered Serial Ports SPRU131G A buffered serial port BSP is a synchronous serial port that is enhanced with an autobuffering unit and is clocked at the full CLKOUT rate It is full duplexed and double buffered to offer flexible data stream length The autobuffering unit supports high speed transfers and reduces the overhead of servicing interrupts Architectural Overview 2 15 Serial Ports 2 8 3 Multichannel Buffered Serial Ports McBSPs The McBSP is an enhanced buffered serial port that includes the following standard features buffered data registers full duplex communication and independent clocking and framing for receive and transmit In addition the McBSP includes the following enhanced features internal programmable clock and frame generation multichannel mode and general purpose I O For detailed information about the McBSPs see TMS320C54x DSP Enhanced Peripherals Reference Guide SPRU302 2 8 4 TDM Serial Ports 2 16 The time division multiplexed TDM serial port is a synchronous serial port thatis enhanced to allow time division multiplexing of the data with up to seven other C54x
91. devices with TDM ports It can be configured for either synchro nous operations or for TDM operations and is commonly used in multiproces sor applications Architectural Overview SPRU131G External Bus Interface IEEE Standard 1149 1 Scanning Logic 2 9 External Bus Interface The C54x DSP can address up to 64K words of data memory 64K words of program memory up to 8M words in some devices and up to 64K words of 16 bit parallel I O ports Accesses to either external memory or I O ports take place through the external interface Individual space select signals DS PS and IS allow the selection of physically separate spaces The interface s external ready input signal and software generated wait states allow the processor to interface with memory and I O devices of many different speeds The interface s hold modes allow an external device to take control of the C54x DSP buses in this way an external device can access the resources in the program data and I O spaces External memory can be accessed by most C54x DSP instructions However accessing I O ports requires the use of special instructions PORTR and PORTW See Chapter 10 External Bus Operation for more details about interfacing the C54x DSP to external devices 2 10 IEEE Standard 1149 1 Scanning Logic SPRU131G The IEEE Standard 1149 1 scanning logic circuitry is used for emulation and testing purposes only This logic provides the boundary scan to and from
92. dual operand instruction for example ADD points to the same auxiliary register with different addressing modes specified for both operands the mode defined by the Xmod field is used for addressing Data Addressing 5 19 Indirect Addressing Figure 5 11 shows the indirect addressing instruction format for a dual data memory operand Table 5 6 describes the bits of the instruction Because only two bits are available for selecting each auxiliary register in this mode only four of the auxiliary registers can be used AR2 AR5 Table 5 7 shows which Xar or Yar value selects which auxiliary registers Figure 5 11 Indirect Addressing Instruction Format for Dual Data Memory Operands 15 8 6 5 4 3 2 1 0 Table 5 6 Indirect Addressing Instruction Bit Summary Dual Data Memory Operands Bit Name Function 15 8 Opcode This eight bit field contains the operation code for the instruction 7 6 Xmod This 2 bit field defines the type of indirect addressing mode used for accessing the Xmem operand 5 4 Xar The 2 bit Xmem auxiliary register selection field defines the auxiliary register that contains the address of Xmem 3 2 Ymod This 2 bit field defines the type of indirect addressing mode used for accessing the Ymem operand 1 0 Yar The 2 bit Ymem auxiliary register selection field defines the auxiliary register that contains the address of Ymem Table 5 7 Auxiliary Registers Selected by Xar and Yar Field of Instruction
93. duration TCK_RET high 15 ns 3 tw TCKL Pulse duration TCK_RET low 15 ns 4 ta TMS Delay time TMS or TDI valid for TCK_RET low 6 20 ns 5 tsu TDO Setup time TDO to TCK_RET high 3 ns 6 th TDO Hold time TDO from TCK_RET high 12 ns A 6 Design Considerations for Using XDS510 Emulator SPRU131G Emulation Timing Calculations A 5 Emulation Timing Calculations Example A 1 and Example A 2 help you calculate emulation timings in your system For actual target timing parameters see the appropriate data sheet for the device you are emulating The examples use the following assumptions tsu TTMS Setup time target TMS or TDI to TCK high 10 ns td TTDO Delay time target TDO from TCK low 15 ns td bufmax Delay time target buffer maximum 10 ns td bufmin Delay time target buffer minimum ins toufskew Skew time target buffer between two de 1 35 ns vices in the same package ta bufmax td oufmin x 0 15 tTCKfactor Duty cycle assume a 40 60 duty cycle 0 4 clock 40 Also the examples use the following values from Table A 2 on page A 6 ta TMSmax Delay time emulator TMS or TDI from 20 ns TCK_RET low maximum tsu TDOmin Setup time TDO to emulator TCK_RET 3 ns high minimum There are two key timing paths to consider in the emulation design J TheTCK_RET to TMSorTDIpath calledtyg Tck_RET TMS TDI Propaga tion delay time _J The TCK_RET to TDO path called tog TCK_RET TDO In the examples the worst case path delay
94. eee ene eens Extended Program Memory for the C5402 2 0 0 cece eee Memory Maps for the C5410 1 eee etna Extended Program Memory Maps for the C5410 On chip RAM Not Mapped in Program Space and Data Space OVLY 0 Extended Program Memory Maps for the C5410 On chip RAM Mapped in Program Space and Data Space OVLY 1 Data Memory Map for the C5420 Relative to CPU Subsystems AandB Program Memory Maps for the C5420 Relative to CPU Subsystems A and B On Chip ROM Block Organization 0 0 0 cece eee On Chip ROM Program Memory Map High Addresses 000002 eee ee eee Extended Program Memory With On Chip RAM Not Mapped in Program Space OVLY 0 sii wacap diaaa piaia i dea ma t ee nee eae Extended Program Memory With On Chip RAM Mapped in Program Space and Data Space OVLY 1 sasini teata auaina giaa ddi a aa de ai db aaa aen E a ab aS On Chip RAM Block Organization 0 000 c cece cent e eee eeee On Chip RAM Block Organization C5402 C5410 C5420 0 0 eee eee eee Status Register 0 STO Diagram 0 2 eect ene Status Register 1 ST1 Diagram 0 0 06 teens Processor Mode Status Register PMST Diagram 0 06 e cece eee ees ALU Functional Diagram oc ssc saccades canes ds dade Yas Jacked wate donee ee PACCUMMUATON A errepasa nEn ata des Ste cede a etd E teas he Lats Bit dans Seg Sng Attia ae ACCUMUIALON B ic405 via San Pee Read
95. eens 8 10 HPIC Diagram Host Writes to HPIC 0 0c teens 8 11 HPIC Diagram TMS320C54x DSP Reads From HPIC 0c eee eee 8 12 HPIC Diagram TMS320C54x DSP Writes to HPIC 0 eee eee 8 13 HPI Timing DidQram e eener enatiincattaaradnagaanaee thane sass nates ekeS 9 1 One Way Serial Port Transfer 2 0 0 0 ccc cence cnet nent n ees 9 2 Serial Port Interface Block Diagram 0 ccc eee eee ees 9 3 Serial Port Control Register SPC Diagram 0 0 00 cece ees 9 4 Receiver Signal Multiplexers 000 cece eee teeta 9 5 Burst Mode Serial Port Transmit Operation 0000 e eens 9 6 Serial Port Transmit With Long FSX Pulse 00000 e cece eee eee eens SPRU131G Figures xxiii Figures 9 7 P l OQUOUOUOUOUOUONNDNNNNDNNNDN 2 2 a aa aaa FO FWNHH ITODAOANDAARPWNHIH OCOOAODANDOAARWNH OO arrrtrtrrttrtretererrerrTrtrer rer fre rr ct N 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 10 10 11 10 12 10 13 10 14 xx v Burst Mode Serial Port Transmit Operation With Delayed Frame Sync in External Frame Sync Mode SP 0 00 cece eet ee eee Burst Mode Serial Port Transmit Operation With Delayed Frame Sync in External Frame Sync Mode BSP 0 000 c cece eee eee eee Burst Mode Serial Port Receive Operation 0000 c cee eee eens Burst Mode Serial Port Receive Overrun 2 0 cece ete Se
96. example BOB is set to 0 and a read is requested of the first HPI memory location in this case 1000h which contains FFFEh 8 48 On Chip Peripherals SPRU131G Host Port Interface Table 8 26 Initialization of BOB and HPIA Event HD HR W HCNTL1 0 HBIL HPIC HPIA_ latch1 latch2 Host writes HPIC 1st byte 00 0 00 0 00xx XXXX XXXX XXXX Host writes HPIC 2nd byte 00 0 00 1 0000 XXXX XXXX XXXX Host writes HPIA 1st byte 10 0 10 0 0000 10xx XXXX XXXX Host writes HPIA 2nd byte 00 0 10 1 1000 XXXX XXXX Internal HPI RAM read complete 1000 FF FE Inthe cycle shown in Table 8 26 BOB and HPIA are initialized and by loading HPIA an internal HPI memory access is initiated The last line of Table 8 26 shows the condition of the HPI after the internal RAM read is complete that is after some delay following the end of the host write of the second byte to HPIA the read is completed and the data has been placed in the upper and lower byte data latches For the host to actually retrieve this data it must per form an additional read of HPID During this HPID read access the contents of the first byte data latch appears on the HD pins when HBIL is low and the content of the second byte data latch appears on the HD pins when HBIL is high Then the address is incremented if autoincrement is selected and the memory is read again into the data latches The sequence involved in this access is shown in Table 8 27 Table 8 27 Read Access to HPI With Auto
97. example configuration that allows any processor in the system to stop any other processor in the system Do not tie the EMU0 1 pins of more than 16 processors together in a single group without using buffers Buffers provide the crisp signals that are required during a RUNB run bench mark debugger command or when the external analysis counter feature is used Design Considerations for Using XDS510 Emulator SPRU131G Emulation Design Considerations Figure A 11 EMU0 1 Configuration to Meet Timing Requirements of Less Than 25 ns Target board 1 o gt Pullup Open resistor collector 4 e EMUO 1 drivers Backp ane lt Device Device XCNT_ENABLE 1 n l EEEE eS E E E EE J EMU0 1 IN hg PAL Pullup resistor p L EMU0 1 OUT i Target board m TCK To emulator EMUO Pullup Open resistor collector en EMUO 1 drivers iw oO a i oO oO a lt O oO Notes 1 The low time on EMU0 1 IN should be at least one TCK cycle and less than 10 us Software sets the EMU0 1 OUT pin to a high state 2 To enable the open collector driver and pullup resistor on EMU1 to provide rise fall times of less than 25 ns the modifi cation shown in this figure is suggested Rise times of more than 25 ns can cause the emulator to detect false edges during the RUNB command or when the external counter selected from the debugger
98. falls and rises for proper reset operation of the C54x DSP Once the host has finished downloading into HPI memory the host stops accessing the HPI and drives the C54x DSP reset line high At least 20 C54x CPU periods after the reset line rising edge the host can again begin acces sing the HPI This number of periods corresponds to the internal reset delay of the C54x DSP The HPI mode is automatically set to SAM upon exiting reset If the host writes a 1 to DSPINT while the C54x DSP is in reset the interrupt is lost when the C54x DSP comes out of reset The C54x DSP warm boot can use the HPI memory and start execution from the lowest HPI address Table 8 30 HPI Operation During RESET Host C54x CPU Mode C54x CLK Waits 6 C54x CPU clock periods Running X Running Brings RESET low and waits 4 clocks Goes into reset HOM Running Can stop C54x CPU clock In reset HOM Stopped or running Writes program and or data in HP memory In reset HOM Stopped or running Turns on DSP clock if it was stoppedt In reset HOM Running Brings RESET high In reset HOM Running Waits 20 C54x CPU clock periods Comes out of reset SAM Running Can access HPI Running SAM Running t Sufficient wake up time must be ensured when the C54x on chip PLL is used SPRU131G On Chip Peripherals 8 53 Chapter 9 Serial Ports This chapter discusses the four serial port interfaces connected to the TMS320C54x DSP core CPU J Standard synchronous serial port interface
99. frame sync pulse is generated by the transmitting device as a direct result of a write to DXR In the latter case there is no such direct effect Instead the transmitting device must write to DXR and wait for an exter nally generated frame sync If internal frame sync pulse generation is selected TXM 1 a frame sync pulse is generated on the second rising edge of CLKX following awrite to DXR For externally generated frame syncs the events described here will occur as soon as a properly timed frame sync pulse occurs see the data sheet for detailed serial port interface timings On the next rising edge of CLKX after FSX goes high the first data bit MSB first is driven onthe DX pin Thus if the frame sync pulse is generated internal ly TXM 1 there is a 2 CLKX cycle latency approximately after DXR is loaded before the data is driven on the line If frame sync is externally gener ated data transmission is delayed indefinitely after a DXR load until the FSX pulse occurs this is described in further detail later in this section With the falling edge of frame sync the rest of the bits are shifted out When all the bits are transferred DX enters a high impedance state Atthe end of each transmission if DXR was not reloaded when XINT was gen erated XSREMPTY becomes active low at this point indicating underflow With externally generated frame sync if XSREMPTY is active and a frame sync pulse is generated any old data in
100. have been stored in program memory Absolute addressing is described in Chapter 5 Data Addressing The PC which is used to fetch individual instructions is loaded by the program address generation logic PAGEN Typically the PAGEN increments the PC as sequential instructions are fetched However the PAGEN may load the PC with a non sequential value as a result of some instructions or other operations Operations that cause a discontinuity include branches calls returns conditional operations single instruction repeats multiple instruction repeats reset and interrupts For calls and interrupts the current PC is saved onto the stack which is referenced by the stack pointer SP When the called function or interrupt service routine is finished the PC value that was saved is restored from the stack via a return instruction For a detailed discussion of the hardware and software factors in program address generation see Chapter 6 Program Memory Addressing 2 6 Pipeline Operation SPRU131G An instruction pipeline consists of a sequence of operations that occur during the execution of an instruction The C54x DSP pipeline has six levels prefetch fetch decode access read and execute At each of the levels an independent operation occurs Because these operations are independent from one to six instructions can be active in any given cycle each instruction at a different stage of completion Typically the pipeline is ful
101. in shared access mode SAM the HRDY signal is used when in host only mode HOM HRDY is not active and remains high however there are exceptions to this which will be discussed For accesses utilizing the HRDY signal during the time when the internal por tion of the transfer is being performed either for a read or a write HRDY is low indicating that another transfer cannot yet be initiated Once the internal cycle is completed and another external cycle can begin HRDY is driven high by the HPI This occurs after a fixed delay following a cycle initiation refer to the TMS320C54x DSP data sheet for detailed timing information for HPI exter nal interface timings Therefore unless back to back cycles are being performed HRDY is normally high when the first byte of a cycle is transferred The external HPI cycle using HRDY is shown in the timing diagram in Figure 8 13 8 46 On Chip Peripherals SPRU131G Host Port Interface Figure 8 13 HPI Timing Diagram Byte 1 Byte 2 SA SOK vat RK vais REIDY HEIL RRR LESSER RRN po KIIR f use Foo fo NL o NL H D SETO y XXX s oy vad 8X vata _ HD HRDY J In a typical external access as shown in Figure 8 13 the cycle begins with the host driving HCNTLO 1 HRW HBIL and HCS indicating specifically what type of transfer is to occur and whether the cycle is to be read or a write Then the host asserts the HAS signal if us
102. instructions or inserting NOPs if necessary to accommodate latencies T Pipeline 7 69 Pipeline Latencies Table 7 22 Latencies for ASM Bit Field 7 70 Pipeline a Latencies based on second instruction category First Instruction MVKD dmad status MVDM dmaad status POPM status POPD status MVDD Xmen status Store type instruction see Table 7 5 SSBX STI asmbit RSBX STI asmbit b Category for the second instruction Category STH src ASM Smem STL src ASM Smem ST src Ymem LD ADD SUB MAC MAS MPY SACCD src Smem cond LD src ASM dst ADD src ASM dst SUB src ASM dst Second Instruction Category L Without a long offset modifier Legend asmbit Destination operand writing to a bit in ASM field of ST1 status Destination operand pointing at ST1 to update ASM in direct indirect or memory mapped addressing mode Note Any instruction that does not fit in either of the two categories has zero latency SPRU131G Pipeline Latencies Example 7 52 ASM Update With No Latency a LD 6 ASM This instruction loads ASM with no latency STH A ASM AR1 b LD 100h ASM This instruction loads ASM with no latency ADD A ASM B c STLM A ST1 This instruction modifies the ASM field of ST1 No latency is needed Since STL uses a long offset modifier STL A ASM AR5 100h Example 7 53 ASM Update With a 1 Cycle Latency
103. is calculated to determine the maximum system test clock frequency SPRU131G Design Considerations for Using XDS510 Emulator A 7 Emulation Timing Calculations Example A 1 Key Timing for a Single Processor System Without Buffers tod TCK_RET TD tad TCK_RET TMS TDI E TMSmax tsu mias tTCkfactor _ 20 ns 10 ns 0 4 75ns or 13 3 MHz E TTDO tsu oami o tTCekfactor 15ns 3 ns 0 4 45 ns or 22 2 MHz In this case because the TCK_RET to TMS TDI path requires more time to complete it is the limiting factor Example A 2 Key Timing for a Single or Multiple Processor System With Buffered Input and Output ty TMSmax tsu TTMS 2t tod TCK_RET TMS TDI 7 tTCkfactor 20 ns 10 ns 2 10 ns 0 4 54 ns or 18 5 MHz ts TTDO tsuctDOminy ta butskevn tod TCK_RET TDO t TCKfactor 15 ns 3ns 1 35 ns 0 4 58 4 ns or 20 7 MHz In this case also because the TCK_RET to TMS TDI path requires more time to complete it is the limiting factor A 8 Design Considerations for Using XDS510 Emulator SPRU131G Emulation Timing Calculations In a multiprocessor application it is necessary to ensure that the EMUO and EMU1 lines can go from a logic low level to a logic high level in less than 10 us this parameter is called rise time ty This can be calculated as follows ty 5 Rpullup x Ndevices X Cload_per_device 5
104. is in reset BDXR can be read any time The same precautions with regard to reads and writes to these registers apply as in serial port CLKOUT SPRU131G Buffered Serial Port BSP Interface Table 9 8 Differences Between Serial Port and BSP Operation in Standard Mode Continued Condition Serial Port BSP Initialization timing requirements On the serial port the serial port On the BSP exiting serial port may be taken out of reset at any reset under certain conditions must time with respect to FSX FSR precede FSX timing by one however if XRST RRST go high CLKOUT cycle in standard mode during or after the frame sync the and by six CLKOUT cycles in frame sync may be ignored autobuffering mode see section 9 3 3 System Considerations of BSP Operation on page 9 49 Operates in IDLE2 3 mode No Yes see section 9 3 3 System Considerations of BSP Operation on page 9 49 9 3 1 2 Enhanced BSP Features The enhanced features that the BSP offers include the capability to generate programmable rate serial port clocks select positive or negative polarities for clock and frame sync signals and to perform transfers of 10 and 12 bit words in addition to the 8 and 16 bit transfers offered by the serial port Additionally the BSP implements the capability to specify that frame sync signals be ignored until instructed otherwise and provides a dedicated operating mode which facilitates its use with PCM interfaces The B
105. may be used and therefore you should consult the appropriate device documentation Example 9 3 BSP Transmit Initialization Routine Action Reset and initialize the serial port by writing 0008h to BSPC Clear any pending serial port in terrupts by writing 0020h to IFR Enable the serial port interrupts by ORing 0020h with IMR Enable interrupts globally if nec essary by clearing the INTM bit in ST1 Initialize the ABU transmit by writing 1400h to BSPCE Write the buffer start address to AXR Write the buffer size to BKX Start the serial port by writing 0048h to BSPC SPRU131G Description This places both the transmit and receive portions of the serial port in reset and sets up the serial port to operate with externally gener ated FSX and CLKX signals and FSX required for transmit receive of each 16 bit word Eliminate any interrupts that may have occurred before initialization Enable transmit interrupts Interrupts must be globally enabled for the CPU to respond This causes the BSP to stop transmitting at the end of the buffer until another FSX is received Identify the first buffer address to the ABU Identify the buffer size to the ABU This takes the transmit portion of the serial port out of reset and starts operations with the conditions defined in steps 1 and 5 Serial Ports 9 53 Buffered Serial Port BSP Interface Example 9 4 BSP Receive Initialization Routine Action
106. o ee ey ee ee ee ee ee ee ee a or a E Figure 10 18 I O Write and Memory Read CLKOUT Address Data MSTRB IOSTRB 10 22 External Bus Operation NINA NS NS NS XK 1O write tity itt tN br Ne i ee ee a Se op EEEE SPRU131G External Bus Interface Timing Figure 10 19 I O Read and Memory Write CLKOUT a a ae a 22 ae a ae oe I O read R W f MSTRB N A IOSTRB Figure 10 20 I O Read and Memory Read i Sa ee os I O read l RW y MSTRB IOSTRB SPRU131G External Bus Operation 10 23 Start Up Access Sequences 10 5 Start Up Access Sequences 10 5 1 Reset The C54x DSP transitions between active and inactive states when entering or leaving one of four modes IDLE1 IDLE2 reset or IDLE3 Entering or leaving the first two modes IDLE1 or IDLE2 requires no special consideration because the clocks to both the CPU and the on chip peripherals remain active However special considerations are necessary when entering or leaving the other two modes _j Reset Hardware initialization takes place J IDLE3 The device makes a transition from a state where neither the CPU nor the on chip peripherals are being clocked to an active state Figure 10 21 shows the reset sequence of the external bus For proper reset operation the RS signal must be ac
107. on the compatibility mode bit CMPT in status register ST1 CMPT 0 Standard mode In standard mode ARF always specifies the auxiliary register regardless of the value in ARP ARP is not updated ARP must always be cleared to 0 when the DSP is in this mode CMPT 1 Compatibility mode In compatibility mode ARP selects the auxiliary register if ARF 0 Otherwise ARF selects the auxiliary register and the ARF value is loaded into ARP when the access is completed ARO in the assembly instruction indicates the auxiliary register selected by ARP in compatibility mode ae Note ARP must always be cleared to 0 when the DSP is in standard mode CMPT 0 At reset both ARP and CMPT are cleared to 0 automatically ee 5 24 Data Addressing SPRU131G Memory Mapped Register Addressing 5 6 Memory Mapped Register Addressing Memory mapped register addressing is used to modify the memory mapped registers without affecting either the current data page pointer DP value or the current stack pointer SP value Because DP and SP do not need to be modified in this mode the overhead for writing to a register is minimal Memory mapped register addressing works for both direct and indirect addressing Figure 5 15 shows how memory mapped addresses are generated Addresses are generated by J Forcing the nine most significant bits MSBs of data memory address to 0 regardless of the current value of DP or SP when direct addressing is used
108. one cycle to execute even if their operand is in single access memory Single access memory blocks are designed to allow a 32 bit read to occur in one cycle Instructions that write 32 bit operands take two cycles to execute DLD AR2 A This instruction only takes 1 cycle even if the operand is in single access memory Pipeline 7 33 Single Access Memory and the Pipeline 7 34 Pipeline D Read write conflict If an instruction that writes to a single access memory block is followed by an instruction that reads from the same single access memory block a conflict occurs because both instructions try to access the same memory block simultaneously In this case the read access is delayed automatically by one cycle For example STL A AR1 AR1 and AR3 points at the same SARAM block LD AR3 B This instruction takes 1 additional cycle due to a memory access conflict On the other hand a dual operand instruction that has a read operand and awrite operand does not cause this conflict because the two accesses are done in two different pipeline stages For example ST A AR2 This instruction does not take any ADD AR3 B extra cycles even if AR2 AR3 point at the same single access memory block Code data conflict Another type of memory access conflict can occur when SARAM or ROM is mapped in both program and data spaces In this case if instructions are fetched from a memory block and data accesses
109. operand of an instruction represents a shift count value in the 16 to 15 range For example ADD A 4 B Add accumulator A right shifted 4 bits to accumulator B one word one cycle SFTL A 8 Shift logical accumulator A eight bits left one word one cycle J The ASM value represents a shift count value in the 16 to 15 range and can be loaded by the LD instruction with an immediate operand or with a data memory operand For example ADD A ASM B Add accumulator A to accumulator B with a shift specified by ASM Central Processing Unit 4 17 Barrel Shifter G The six LSBs of T represent a shift count value in the 16 to 31 range For example NORM A Normalize accumulator A T contains the exponent value Figure 4 7 Barrel Shifter Functional Diagram DB15 DBO 4 CB15 CBO A 0 B 40 Sign control SXM T 16 through 31 range TC test bit pepe ASM 4 0 16 through 15 range Instruction register immediate 16 through 15 or 0 through 15 range ALU q re 40 MSW LSW CSSU Write select Legend A Accumulator A B Accumulator B C CB data bus D DB data bus T T register D EB15 EBO 4 18 Central Processing Unit SPRU131G Multiplier Adder Unit 4 5 Multiplier Adder Unit SPRU131G The C54x CPU has a 17 bit x 17 bit hardware multiplier coupled to a 40 bit dedicated adder This multiplier adder unit provides multiply and accumulate MAC cap
110. or without along FIRS offset modifier circind shift src dst Without a long offset modifier With an extended shift and without a long offset modifier With one operand using indirect ad dressing mode with or without a long offset modifier T Add one more cycle of latency if the first instruction meets the DAGEN register conflict criteria See section 7 5 3 Rules to Deter mine DAGEN Register Access Conflicts for more information The destination operand bkreg must point at BK in either direct or indirect addressing mode The operand circind must use circular addressing mode Shift value between 16 and 15 Notes 1 Any instruction that does not fit in either of the two categories has zero latency 2 The first instruction can be any C54x DSP instruction SPRU131G Pipeline 7 47 Pipeline Latencies Example 7 25 ARx Updated With No Latency a ADD A B STM 100h AR3 This instruction does not conflict with the previous instruction LD AR3 A No latency is required to use AR3 b ADD A B This instruction does not create a DAGEN conflict MVDK 200h AR7 This instruction has zero latency STH B AR7 c STLM A ARI This instruction updates AR1 in 7th xecute stage possibly creating a DAGEN conflict MVDK 200h AR2 However this instruction uses a long offset modifier Therefore it creates no DAGEN conflict MAR AR2 No latency is r
111. read or write are also performed on the same memory block the instruc tion fetch is delayed by one cycle For example LD ARI A This read data access delays a subsequent instruction fetch STH A AR2 This write data access delays a Subsequent instruction fetch This situation causes significantly higher pipeline latency than the cases described previously This is because each time there is a read or write access to the memory block the pipeline is stalled for one cycle It is generally recommended that each single access memory block be reserved for either data or program storage to avoid hits each time a data access is made to that block SPRU131G Pipeline Latencies 7 5 Pipeline Latencies The C54x DSP pipeline allows multiple instructions to access CPU resources simultaneously Because CPU resources are limited conflicts can occur when one CPU resource is accessed by more than one pipeline stage Some of these pipeline conflicts are resolved automatically by the CPU by delaying accesses Other conflicts are unprotected and must be resolved by the programmer In general unprotected conflicts are resolved by rearranging instructions or by inserting NOP instruction no operation performed They can also be avoided by using only instructions that do not create any pipeline conflicts or by observ ing necessary delays before certain registers are accessed 7 5 1 Recommended Instructions for Accessing Memory Mapped Re
112. shared access mode access rate up to the host only mode maximum access rate In both cases the HRDY pin provides a convenient way to automatically no software handshake needed adjust the host access rate to a faster C54x CPU clock rate or switch the HPI mode All of these features combined allow the HPI to provide a flexible and efficient interface to a wide variety of industry standard host devices Also the simplic ity of the HPI interface greatly simplifies data transfers both from the host and the C54x DSP sides of the interface Once the interface is configured data transfers are made with a minimum of overhead at a maximum speed On Chip Peripherals 8 39 Host Port Interface 8 6 2 Details of Host Port Interface Operation This section includes a detailed description of each HPI external interface pin function as well as descriptions of the register and control bit functions Logical interface timings and initialization and read write sequences are discussed in section 8 6 3 Host Read Write Access to HPI on page 8 45 The external HPI interface signals implement a flexible interface to a variety of types of host devices Devices with single or multiple data strobes and with or without address latch enable ALE signals can easily be connected to the HPI Table 8 21 gives a detailed description of the function of each of the HPI exter nal interface pins Table 8 21 HPI Signal Names and Functions HPI Pin Host Pin State
113. single cycle by an instruction using single data memory operand addressing including an instruction with a 32 bit long word operand In the dual memory operand addressing the access requires two cycles if both operands reside in the same block if the operands reside in different blocks the access requires a single cycle For the address bound aries of the ROM blocks see section 3 2 2 On Chip ROM Organization on page 3 17 Figure 3 1 through Figure 3 4 pages 3 3 through 3 6 show the data memory configurations on the individual C54x devices 3 3 2 On Chip RAM Organization SPRU131G On chip RAM is subdivided and organized in blocks to enhance performance For example the block organization enables you to fetch two operands from one block of DARAM and write to another block of DARAM in the same cycle Figure 3 18 on page 3 24 shows the RAM block organization for each C54x device The gray lines in the figure indicate block boundaries The organization of the first 1K of DARAM on all C54x devices includes the memory mapped CPU and peripheral registers 32 words of scratch pad DARAM and 896 words of DARAM Depending on the device the RAM is organized into 1K 2K or 8K blocks For 5K RAM devices typically the RAM block is 1K for 6K RAM and 10K RAM devices typically the RAM block is 2K for 16K RAM devices typically the RAM block is 8K other devices have a combination of RAM block sizes Memory 3 23 Data Memory Figure 3
114. stack and then loads PC from the stack allow ing program execution to resume at the previous point 1 FRETE loads XPC from the stack loads PC from the stack and enables maskable interrupts Program Memory Addressing SPRU131G Returns Table 6 12 shows the far return instructions nondelayed and delayed and the number of cycles needed to execute these instructions Note that delayed instructions need two cycles fewer than the corresponding nondelayed instructions Table 6 12 Far Return Instructions SPRU131G Number of Cycles Instruction Description Nondelayed Delayed FRET D Loads XPC with the value at the top of the 6 4 stack and loads PC with the next value on the stack FRETE D Loads XPC with the value at the top of the 6 4 stack loads PC with the next value on the stack and enables maskable interrupts Program Memory Addressing 6 15 Conditional Operations 6 6 Conditional Operations The C54x DSP includes instructions that execute only if one or more condi tions are met Table 6 13 lists the conditions that you can use with these instructions and their corresponding operand symbols Table 6 13 Conditions for Conditional Instructions 6 16 Condition A 0 B 0 Az 0 Bz 0 A lt 0 B lt 0O A lt 0 B lt 0 A gt 0 B gt 0 A20 B20 AOV 1 BOV 1 AOV 0 BOV 0 C 1 C 0 TC 1 TC 0 BIO low BIO high none Program Memory Addressing Description Accumulator A equal to 0 Accumulator
115. the interfacing devices Also it can be used to test pin to pin continuity as well as to perform operational tests on devices peripheral to the C54x DSP The IEEE Standard 1149 1 scanning logic is interfaced to internal scanning logic circuitry that has access to all of the on chip resources Thus the C54x DSP can perform on board emulation using the IEEE Standard 1149 1 serial scan pins and the emulation dedicated pins For more information see Appendix A Design Considerations for Using XDS510 Emulator Architectural Overview 2 17 Chapter 3 Memory This chapter describes the TMS320C54x DSP memory configuration and operation In general the C54x devices have a total memory space of 192K 16 bit words This space is divided into three specific memory segments 64K words of program 64K words of data and 64K words of I O In some C54x devices the memory structure has been modified through overlay and paging schemes to allow additional memory space The parallel nature of the C54x DSP architecture and the dual access capabili ty of the on chip RAM allow the C54x devices to perform four concurrent memory operations in any given machine cycle an instruction fetch two operand reads and an operand write There are several advantages of operating from on chip memory J Higher performance because no wait states are required _j Lower cost than external memory i Lower power than external memory The main advantage of operat
116. the instruction WRITA transfers a word from a data memory location specified by the Smem operand of the instruction to a program memory location specified by accumu lator A In repeat mode an increment may be used to increment accumulator A Ee ET aa Note The C54x devices have different number of address lines therefore the program memory location is specified by the lower bits of accumulator A See section 3 2 5 Extended Program Memory on page 3 20 5 6 Data Addressing SPRU131G Direct Addressing 5 4 Direct Addressing SPRU131G In direct addressing the instruction contains the lower seven bits of the data memory address dma The 7 bit dma is an address offset that is combined with a base address with the data page pointer DP or with the stack pointer SP to form a 16 bit data memory address Using this form of addressing you can access any of 128 locations in random order without changing the DP or the SP NS oe Note Direct addressing is not the only method of offset addressing However the advantage of this mode is that it encodes each instruction and address into a single word a Either DP or SP can be combined with the dma offset to generate the actual address The compiler mode bit CPL located in status register ST1 selects which method is used to generate the address _ When CPL 0 the dmafield is concatenated with the 9 bit DP field to form the 16 bit data memory a
117. the internal program address appears on the device s external address bus pins AG accumulator guard bits An 8 bit register that contains bits 39 32 the guard bits of accumulator A D 1 Glossary AH accumulator A high word Bits 31 16 of accumulator A AL accumulator A low word Bits15 0 of accumulator A ALU arithmetic logic unit The part of the CPU that performs arithmetic and logic operations analog to digital A D converter Circuitry that translates an analog signal to a digital signal ARO AR7 auxiliary registers 0 7 Eight 16 bit registers that can be accessed by the CPU and modified by the auxiliary register arithmetic units ARAUs and are used primarily for data memory addressing ARAU See auxiliary register arithmetic unit ARP See auxiliary register pointer ARR ARRO ARR1 ABU address receive register A 16 bit register that specifies the destination address at which the autobuffering unit begins storing received data ASM See accumulator shift mode field autobuffering receiver enable BRE A bit in the BSP control extension register BSPCE that enables disables the autobuffering receiver autobuffering receiver halt HALTR A bit in the BSP control extension register BSPCE that enables disables the autobuffer receiver when the current half of the buffer is received autobuffering transmitter enable BXE A bitin the BSP control extension register BSPCE that enables disables the
118. to 1 NOP These NOPs can be replaced by NOP other instructions that do not use NOP direct addressing mode to access operands LD 27h A The operand is read at an offset z Of 27h from SP 7 5 7 5 Updating SXM A pipeline conflict can occur if two conditions are simultaneously met J An instruction modifies SXM J The next instruction uses SXM to control sign extension The conflict occurs because the second instruction uses SXM in a pipeline stage that occurs before the previous instruction updates it Table 7 20 lists the latencies between instructions that update SXM and subsequently use it 7c TT Note You are responsible for rearranging instructions or inserting NOPs if necessary to accommodate latencies an SPRU131G Pipeline 7 67 Pipeline Latencies Table 7 20 Latencies for the SXM Bit a Latencies based on second instruction category Second Instruction First Instruction Category MVKD_ dmad status 1 MVDM_ dmaad status POPM status POPD status MVDD Xmen status Store type instruction see Table 7 5 1 SSBX SXM RSBX SXM b Category for the second instruction Category All instructions affected by the sign extension mode bit except those that require an Smem operand with a long offset modifier for example LD AR1 100h A Legend status Destination operand pointing at ST1 to update SXM in either direct indirect or memory mapped addressing mode Note
119. transmit interrupt BXINT BXINTO BXINT1 A bitin the interrupt flag register IFR that indicates the the BSP data transmit register BDXR contents has been copied to the BSP data transmit shift register BXSR BXINTO corresponds to buffered serial port 0 BXINT1 corresponds to buff ered serial port 1 BSPC BSPCO BSPC1 Buffered serial port control registers 0 and 1 A 16 bit register that contains status and control bits for the buffered serial port BSPCO corresponds to buffered serial port 0 BSPC1 corresponds to buffered serial port 1 D 4 Glossary SPRU131G SPRU131G Glossary BSPCE BSPCE0 BSPCE1 BSP control extension register A 16 bit register that contains status and control bits for the buffered serial port BSP interface The 10 LSBs of the BSPCE are dedicated to serial port interface control whereas the 6 MSBs are used for autobuffering unit ABU control buffer misalignment interrupt BMINT A C549 feature that detects potential error conditions and indicates lost words on a serial port interface burstmode Asynchronous serial port mode in which a single word is trans mitted following a frame synchronization pulse FSX and FSR butterfly A kernel function for computing an N point fast Fourier transform FFT where N is a power of 2 The combinational pattern of inputs resembles butterfly wings BXE See autobuffering transmitter enable BXSR BSP data transmit shift register A 16 bit register that ho
120. up or down whichever is appropriate external input pins which could spuriously cause serial port transfers or by putting the port in reset 9 2 2 Serial Port Interface Operation 9 6 Serial Ports This section describes operation of the basic standard serial port interface which includes operation of the TDM and BSP serial ports when configured in standard mode Table 9 4 lists the pins used in serial port operation Figure 9 1 shows these pins for two C54x DSP serial ports connected for a one way transfer from device 0 to device 1 Only three signals are required to connect from a serial port transmitter to a receiver for data transmission The transmitted serial data signal DX sends the actual data The transmit frame synchronization signal FSX initiates the transfer at the beginning of the packet and the transmit clock signal CLKX clocks the bit transfer The corre sponding pins on the receive device are DR FSR and CLKR respectively SPRU131G Serial Port Interface Table 9 4 Serial Port Pins Pin Description CLKR Receive clock signal CLKX Transmit clock signal DR Received serial data signal DX Transmitted serial data signal FSR Receive framing synchronization signal FSX Transmit frame synchronization signal Figure 9 1 One Way Serial Port Transfer SPRU131G C54x device 0 C54x device 1 DX gt DR gt gt Figure 9 2 shows how the pins and registers are configured in the serial port l
121. whether or not the data in an accumulator is saturated before storing it in memory The saturation is performed after the shift operation Saturation on store is available with ten instructions B L E m STH 3 ST ADD 3 ST MPY STL 3 ST LD J ST SUB STLM 3 ST MAC R DST J ST MAS R The following steps are performed when saturating upon accumulator store 1 3 The 40 bit data value is shifted right or left depending on the instruction The shift is the same as described in the SFTA instruction and depends on the value of the SXM bit The 40 bit value is saturated to a 32 bit value The saturation depends on the value of the SXM bit the number is always assumed to be positive m WhenSXM 0 FFFF FFFFh is generated if the 40 bit value is greater than or equal to FFFF FFFFh m When SXM 1 7FFF FFFFhis generated if the 40 bit value is greater than 7FFF FFFFh 8000 0000h is generated if the 40 bit value is less than 8000 0000h The data is stored in memory depending on the instruction either 16 bit LSB 16 bit MSB or 32 bit data The accumulator remains unchanged during this process 4 3 4 Application Specific Instructions SPRU131G Each accumulator is dedicated to specific operations in application specific instructions with parallel operations These include symmetrical FIR filter operations using the FIRS instruction adaptive filter operations using the LMS instruction Euclidean distanc
122. with a length of 16 bits so instruc tions that encode absolute addresses are always at least two words in length 5 2 1 dmad Addressing Data memory address damad addressing uses a specific value to specify an address in data space The syntax for dmad addressing uses a symbol or a number to specify an address in data space For example to copy the value contained at the address labeled SAMPLE in data space to the memory location in data space pointed to by AR5 you would write MVKD SAMPLE AR5 In this example the address referenced by SAMPLE is the dmad value 5 4 Data Addressing SPRU131G Absolute Addressing 5 2 2 pmad Addressing Program memory address pmad addressing uses a specific value to specify an address in program space The syntax for pmad addressing uses a symbol or a number to specify an address in program space For example to copy a word in the program memory location labeled TABLE to a data memory location specified by AR7 you would write MVPD TABLE AR7 In this example the address referenced by TABLE is the pmad value 5 2 3 PA Addressing Port address PA addressing uses a specific value to specify an external I O port address The syntax for PA addressing uses a symbol or a number to specify the port address For example to copy a value from the I O port at port address FIFO to a data memory location pointed to by AR5 you would write PORTR FIFO AR5 In the example F
123. 0 Input 1 This bit allows the CLKX pin to be used as a bit input IN1 reflects the current level of the CLKX pin of the device When CLKX switches levels there is a latency of between 0 5 and 1 5 CLKOUT cycles before the new CLKX value is represented in the SPC Input 0 This bit allows the CLKR pin to be used as a bit input INO reflects the current level of the CLKR pin of the device When CLKR switches levels there is a latency of between 0 5 and 1 5 CLKOUT cycles before the new CLKR value is represented in the SPC Receive Reset This signal resets and enables the receiver When a 0 is written to the RRST bit activity in the receiver halts RRST 0 The serial port receiver is reset Writing a 0 to RRST clears the RSRFULL and RRDY bits to 0 RRST 1 The serial port receiver is enabled Transmitter Reset This signal is used to reset and enable the transmitter When a 0 is written to the XRST bit activity in the transmitter halts When the XRDY bit is 0 writing a0 to XRST generates a transmit interrupt XINT XRST 0 The serial port transmitter is reset Writing a 0 to XRST clears the XSREMPTY bit to 0 and sets the XRDY bit to 1 XRST 1 The serial port transmitter is enabled SPRU131G Serial Port Interface Table 9 5 Serial Port Control Register SPC Bit Summary Continued Bit Name 5 TXM 4 MCM 3 FSM 2 AQ SPRU131G Reset Value 0 Function Transmit Mode This bit configures the FSX pin
124. 0 multiplier definition C5420 multiplier adder to 4 22 definiton P block diagram extended program input sources 4 20 4 21 C548 and C549 B g multiplier input CEAT ble 4 21 C5402 B 10 multiply accumulate MAC instructions C5410 B 12 multiply subtract MAS instructions C5420 B 14 square add SQRA instructions memory security square subtract SQRS instructions Index 11 Index nested interrupt D 12 nomenclature _ B 6 prefixes nonmaskable interrupt normalization of accumulator A example 4 27 on chip dual access RAM DARAM 2 6 peripherals 2 12 ROM security shared RAM single access RAM SARAM 2 6 on chip DARAM on chip data memory available table on chip memory _ 8 15 advantages available table on chip peripherals buffered serial port BSP 9 33 serial port interface TDM serial port on chip RAM organization on chip ROM figure a organization program memory map figure on chip ROM contents operand write and operand read conflict figure output modes external count signal event OVA definition OVB definition overflow definition overflow flag definition overflow flag A OVA definition overflow flag B OVB 4 3 definition overflow handling Index 12 overflow mode OVM 4 5 definition overview architecture TMS320 DSP family TMS320054x DSP 1 5 OVLY definition latencies table OVLY setup followed by a conditional branch followed by a return followed by an u
125. 0 ns CMOS VLSI Digi tal Signal Processor 1986 Workshop on Applications of Signal Processing to Audio and Acoustics September 1986 24 Texas Instruments Digital Signal Processing Applications with the TMS320 Family 1986 Englewood Cliffs NJ Prentice Hall Inc 1987 25 Treichler J R C R Johnson Jr and M G Larimore A Practical Guide to Adaptive Filter Design New York NY John Wiley and Sons Inc 1987 x Read This First SPRU131G SPRU131G Technical Articles Graphics Imagery 1 Reimer J and A Lovrich Graphics with the TMS32020 WESCON 85 Conference Record USA 1985 Speech Voice 1 DellaMorte J and P Papamichalis Full Duplex Real Time Implementa tion of the FED STD 1015 LPC 10e Standard V 52 on the TMS320C25 Proceedings of SPEECH TECH 89 pages 218 221 May 1989 Gray A H and J D Markel Linear Prediction of Soeech New York NY Springer Verlag 1976 Frantz G A and K S Lin A Low Cost Speech System Using the TMS320C17 Proceedings of SPEECH TECH 87 pages 25 29 April 1987 Papamichalis P and D Lively Implementation of the DOD Standard LPC 10 52E on the TMS320C25 Proceedings of SPEECH TECH 87 pages 201 204 April 1987 Papamichalis Panos Practical Approaches to Speech Coding Engle wood Cliffs NJ Prentice Hall Inc 1987 Pawate B I and G R Doddington Implementation of a Hidden Markov Model Based Layered Grammar Recogni
126. 01Eh At a hardware reset the XPC is initialized to 0 Program memory in the C548 C549 C5402 C5410 and C5420 is organized into 128 pages 16 pages in the C5402 and 4 pages in the C5420 that are each 64K words in length Figure 3 16 shows extended program memory to 128 pages When the on chip RAM is enabled in program space OVLY 1 each page of program memory is made up of two parts a common block of 32K words maximum and a unique block of 32K words The common block is shared by all pages and each unique block is accessible only through its assigned page Figure 3 17 shows the common and unique blocks of the extended program memory If the on chip ROM is enabled MP MC 0 it is enabled only on page 0 It is not mapped to any other page in program memory Figure 3 16 Extended Program Memory With On Chip RAM Not Mapped in Program Space OVLY 0 00 0000 00 FFFF XPC 0 Memory 01 0000 02 0000 7F 0000 Page 127 64K words 01 FFFF 02 FFFF XPC 1 XPC 2 XPC 127 7F FFFF SPRU131G Program Memory Figure 3 17 Extended Program Memory With On Chip RAM Mapped in Program Space and Data Space OVLY 1 xx 0000 xx 7FFF XPC xx 00 8000 01 8000 02 8000 7F 8000 Page 127 32K words 01 FFFF 02 FFFF TE FFFF XPC 0 XPC 1 XPC 2 XPC 127 00 FFFF Note When the on chip RAM is enabled in program space all accesses to the region xx 0000 xx 7FFF regardless of page n
127. 1 AXRO BKXO ARRO BKRO Description Buffered serial port data receive register Buffered serial port data transmit register Buffered serial port control register Buffered serial port control extension register Timer register Timer period register Timer control register Reserved Software wait state register Bank switching control register Reserved Host port interface control register Reserved Serial port data receive register Serial port data transmit register Serial port control register Reserved ABU transmit address register ABU transmit buffer size register ABU receive address register ABU receive buffer size register Reserved Clock mode register C545A only Reserved SPRU131G Peripheral Memory Mapped Registers Table 8 5 C546 C546A Peripheral Memory Mapped Registers Address Hex 20 21 22 23 24 25 26 27 28 29 2A 2F 30 31 32 33 37 38 39 3A 3B 3C 57 58 59 5F SPRU131G Name BDRRO BDXRO BSPCO BSPCEO TIM PRD TCR SWWSR BSCR DRR1 DXR1 SPC1 AXRO BKXO ARRO BKRO Description Buffered serial port data receive register Buffered serial port data transmit register Buffered serial port control register Buffered serial port control extension register Timer register Timer period register Timer control register Reserved Software wait state register Bank switching control register Reserved Serial port data receive register Serial port data transmit register
128. 1 and XINT1 serial port interrupts E TINT timer interrupt 1 Nonmaskable interrupts These interrupts cannot be blocked The C54x DSP always acknowledges this type of interrupt and branches from the main program to an ISR The C54x DSP nonmaskable interrupts include all software interrupts and two external hardware interrupts RS reset and NMI RS and NMI can also be asserted using software 6 26 Program Memory Addressing SPRU131G Interrupts RS is anonmaskable interrupt that affects all C54x DSP operating modes See section 6 9 Reset Operation on page 6 25 NMI is a nonmaskable interrupt Interrupts are globally disabled when NMI is asserted NMI is different from RS because it does not affect any of the C54x DSP modes The C54x DSP handles interrupts in three phases 1 Receive interrupt request Suspension of the main program is requested via software program code or hardware a pin or an on chip peripheral If the interrupt source is requesting a maskable interrupt the correspond ing bit in the interrupt flag register IFR is set when the interrupt is received 2 Acknowledge interrupt The C54x DSP must acknowledge the interrupt request If the interrupt is maskable predetermined conditions must be met in order for the C54x DSP to acknowledge it For nonmaskable hardware interrupts and for software interrupts acknowledgment is immediate 3 Execute interrupt service routine ISR Once the interrupt is acknowl
129. 11 A 12 A 13 A 14 A 15 B 1 Figures Memory Write and I O Write 0 0 0 Memory Write and I O Read 0 0 c nannan annnars aes I O Write and Memory Write 0 0000 cee ete eens I O Write and Memory Read 00 0c cece teen teen eens I O Read and Memory Write 20 00 ccc eee eee ees I O Read and Memory Read 00 cece ene eens External Bus Reset Sequence cece eee teen eet e teenies IDLE3 Wake Up Sequence in rss iures asori iaa nee teen E HOLD and HOLDA Minimum Timing for HM 0 00 0 aaan HOLD and RS Interaction ccs fos ice wd od andd sad davun det adeeindbeinedbindse 14 Pin Header Signals and Header Dimensions 000 cc eee eee eee eee Emulator Cable Pod Interface 0 c cette ete Emulator Cable Pod Timings 0 ccc cece eee eee tee eens Emulator Connections Without Signal Buffering 0 00 cece eee eee ee Emulator Connections With Signal Buffering 0 6c eee eee eee Target System Generated Test Clock nunnu 0 0 cece cence nce n eens Multiprocessor Connections 0c cee eee teen eens Pod Connector Dimensions 0 cee 14 Pin Connector Dimensions 000 c cece cette e eens Connecting a Secondary JTAG Scan Path to a Scan Path Linker EMUO0 1 Configuration to Meet Timing Requirements of Less Than 25 ns Suggested Timings for the EMUO and EMU1 Signals
130. 110b on C5402 and CLKMD 3 1 101b on all other devices When these clock mode pin com binations are used the internal PLL lock timer is not active therefore the system must delay releasing reset in order to allow for the PLL lock time delay On Chip Peripherals SPRU131G Clock Generator The programming of the PLL is loaded in the 16 bit memory mapped address 58h clock mode register CLKMD The CLKMD is used to define the clock configuration of the PLL clock module The CLKMD bit fields are shown in Figure 8 4 and described in Table 8 18 Note that upon reset the CLKMD is initialized with a predetermined value dependent only upon the state of the CLKMD 1 3 pins see Table 8 16 Figure 8 4 Clock Mode Register CLKMD Diagram 15 12 11 10 3 2 1 0 PLLMUL PLLDIV PLLCOUNT PLLON OFF PLLNDIV PLLSTATUS R wt R wt R wt R wt R W R T When in DIV mode PLLSTATUS is low PLLMUL PLLDIV PLLCOUNT and PLLON OFF are don t cares and their contents are indeterminate Table 8 18 Clock Mode Register CLKMD Bit Summary Bit Name Function 15 12 PLLMUL PLL multiplier Defines the frequency multiplier in conjunction with PLLDIV and PLLNDIV as shown in Table 8 19 on page 8 30 11 PLLDIV PLL divider Defines the frequency multiplier in conjunction with PLLMUL and PLLNDIV as shown in Table 8 19 on page 8 30 10 3 PLLCOUNT PLL counter value Specifies the number of input clock cycles in increments of 16 cycles forthe PL
131. 13 through Figure 10 20 show the various transitions between memory reads and writes and I O reads and writes over the external interface bus The timing diagrams illustrate these concepts _j I O reads and writes take at least three cycles when they follow a memory read or write J Memory reads take two cycles when they follow an I O read or write SPRU131G External Bus Operation 10 19 External Bus Interface Timing Figure 10 13 Memory Read and I O Write CLKOUT Address Data RW MSTRB IOSTRB TAA A A A 2 E Sa a ee Se ee ee Na 7 ee eee ee ee AO a Figure 10 14 Memory Read and I O Read CLKOUT Address Data R W MSTRB IOSTRB 10 20 External Bus Operation SPRU131G Figure 10 15 Memory Write and I O Write Address Data MSTRB IOSTRB CLKOUT Address Data RW MSTRB IOSTRB SPRU131G Write dat External Bus Interface Timing 1 0 Write es ee ee ee ee ew E ae oe ee a a ed ee oe ee ee ee ee re a hak tt a Figure 10 16 Memory Write and I O Read Ne ey ee ee a X se I O read Se ae ae a a ieee Oe ee ae ae ie eee ee Sy External Bus Operation 10 21 External Bus Interface Timing Figure 10 17 I O Write and Memory Write CLKOUT Address Data R W IOSTRB af NI NY NF NY T Se hee O write i a a A
132. 16 definition Index z zero detect See ZA and ZB zero detect A ZA definition ZA definition zero detect B ZB definition ZB definition zero fill definition Index 21
133. 17h The autobuffering process is activated upon request from serial port interface when XRDY or RRDY goes high indicating that a word has been received The required memory access is then performed following which an interrupt is generated if half of the defined buffer first or second has been processed The RH and XH flags in BSPCE indicate which half has been processed when the interrupt occurs SPRU131G Buffered Serial Port BSP Interface When autodisabling is selected HALTX or HALTR bit is set then when the next half first or second buffer boundary is encountered the autobuffering enable bit in the BSPCE BXE or BRE is cleared so that autobuffering is disabled and does not generate any further requests When transmit autobuf fering is halted transmission of the current XSR contents and the last value loaded in DXR are completed since these transfers have already been initi ated Therefore when using the HALTX function some delay will normally occur between crossing a buffer boundary and transmission actually stopping If it is necessary to identify when transmission has actually ended software should poll for the condition of XRDY 1 and XSREMPTY 0 which occurs after last bit has been transmitted In the receiver when using HALTR since autobuffering is stopped when the most recent buffer boundary is crossed future receptions may be lost unless software begins servicing receive interrupts at this point since
134. 2 2 On Chip ROM Organization aessa aaua 0c cece ee 3 2 3 Program Memory Address Map and On Chip ROM Contents 3 2 4 On Chip ROM Code Contents and Mapping 00000eee eee 3 2 5 Extended Program Memory Available on C548 549 5402 5410 5420 3 3 DaG MINON serasa s ARR A TEE AA 3 3 1 Data Memory Configurability 0 0c ntik 3 3 2 On Chip RAM Organization oeeie issis casis icseriarinioner ia nenian da 3 3 3 Memory Mapped Registers cece 3 3 4 CPU Memory Mapped Registers 0000 c cece eee eee eee eee S84 MWO MEMON cidsccad thaseecthtase te eet be state A E T adele sesere deed 3 5 Program and Data Security 0 c cece etna Central Processing Unit 000 e eee e eee eee eee eee eee eee Describes the TMS320C54x CPU operations Includes information about the arithmetic logic unit the accumulators the shifter the multiplier adder unit the compare select store unit and the exponent encoder 4 1 CPU Status and Control Registers 0 00 cece eects 4 1 1 Status Registers STO and ST1 0 eee eee 4 1 2 Processor Mode Status Register PMST 4 2 Arithmetic Logic Unit AL 2 2c 9eeeedoee cadence eineeeee titike tka 421 ALU INPUT x5 ceteins elas eared ioen dania De ene e heed Make a va 4 2 2 Overflow Handling 0 eee eens 42 3 The Carty Bit gregeten uaaa aa uai ya ia aad aE E A a AE D 42 4 Dual 16 Bit MOd6 aii sacs s
135. 2N boundary and offer the effect of circular addressing The effective base address EFB of the circular buffer is determined by zero ing the N LSBs of a user selected auxiliary register ARx The end of buffer address EOB of the circular buffer is determined by replacing the N LSBs of ARx with the N LSBs of BK The index of the circular buffer is simply the N LSBs of ARx and the stepis the quantity being added to or subtracted from the auxil iary register Follow these three rules when you use circular addressing g Place the first lowest address of the circular buffer on a 2N boundary where 2N is larger than the circular buffer size 1 Use a step less than or equal to the circular buffer size 1 The first time the circular queue is addressed the auxiliary register must point to an element in the circular queue The algorithm for circular addressing is as follows IfO lt index step lt BK index index step Else if index step BK index index step BK Else if index step lt 0 index index step BK Circular addressing can be used for single data memory or dual data memory operands When BK is zero the circular modifier results in no circular address modification This is especially useful when a dual operand must perform an address modification equivalent to ARx 0 Figure 5 9 illustrates the relationships among BK the auxiliary register ARx the bottom of the circular buffer the top of
136. 2is pushed onto the stack XPC is pushed onto the stack PC and XPC are loaded with bits 15 0 and bits 23 16 respectively of the immediate value specified by the call instruction PC 1 is pushed onto the stack XPC is pushed onto the stack and the PC and XPC are loaded with bits 15 0 and bits 23 16 respectively of accumulator A or B The return instruction pops the top of the stack into XPC and pops the next value into the PC to return to the call ing sequence of code aN Note The XPC is not loaded by instructions other than those listed in Table 6 3 eee Program Memory Addressing 6 5 Branches 6 3 Branches Branches break the sequential flow of instructions by transferring control to another location in program memory Therefore branches affect the program address generated and stored in PC The C54x DSP performs both unconditional and conditional branches and both of these types can be either nondelayed or delayed 6 3 1 Unconditional Branches An unconditional branch is always executed when it is encountered During the execution PC is loaded with the specified branch to program memory address and execution of the new section of code begins at that address The address loaded into PC comes from either the second word of the branch instruction or the lower 16 bits of an accumulator accumulator A or accumula tor B By the time the branch instruction reaches the execute phase of the pipeline the next t
137. 3 54 55 56 57T 58 59 5F 8 14 On Chip Peripherals Name DRR21 DRR11 DXR21 DXR11 SPSA1 SPSD1 DMPREC DMSA DMSDI DMSDN CLKMD Description McBSP1 data receive register 2 McBSP1 data receive register 1 McBSP1 data transmit register 2 McBSP1 data transmit register 1 Reserved McBSP1 serial port sub bank address register See Table 8 11 on page 8 17 McBSP1 serial port sub bank data register See Table 8 11 on page 8 17 Reserved DMA channel priority and enable control register DMA sub bank address register DMA sub bank data register with sub bank address auto increment See Table 8 12 on page 8 18 DMA sub bank data register See Table 8 12 on page 8 18 Clock mode register Reserved SPRU131G Peripheral Memory Mapped Registers Table 8 10 C5420 Peripheral Memory Mapped Registers For Each DSP Subsystem SPRU131G Address Hex 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2F 30 31 32 33 34 35 36 37 38 39 Name DRR20 DRR10 DXR20 DXR10 TIM PRD TCR SWWSR BSCR SWCR HPIC DRR22 DRR12 DXR22 DXR12 SPSA2 SPSD2 SPSAO SPSDO Description MCBSP 0 data receive register 2 MCBSP 0 data receive register 1 MCBSP 0 data transmit register 2 MCBSP 0 data transmit register 1 Timer register Timer period counter Timer control register Reserved Software wait state register Bank switching control register Reserv
138. 3 2 1 0 Effective memory address The SP points to any address in memory The dma points to the specific loca tion on the page allowing you to access a contiguous 128 word 27 1 block in memory from any base address SP can also add or remove items from the stack See section 5 7 Stack Addressing for more information Data Addressing 5 9 Indirect Addressing 5 5 Indirect Addressing 5 5 1 In indirect addressing any location in the 64K word data space can be accessed using the 16 bit address contained in an auxiliary register The C54x DSP has eight 16 bit auxiliary registers ARO AR7 Indirect addres sing is used mainly when there is a need to step through sequential locations in memory in fixed size steps When memory is addressed with indirect addressing the auxiliary register and the address can be optionally modified by a decrement an increment an offset or an index Special modes offer circular and bit reversed addressing A circular buffer size register BK is used with circular addressing The ARO register is used for indexed and bit reversed addressing modes in addition to being used to point to memory as the other auxiliary registers do Indirect addressing is flexible enough not only to read or write a single 16 bit data operand from memory with one instruction but also to access two data memory locations with one instruction Accesses of two data memory locations include reads of two independent memo
139. 3 Mode SPRU131G Power Down Modes C54x DSP enters the ISR when IDLE1 is terminated If INTM 1 the C54x DSP continues with the instruction following the IDLE 1 instruction All wake up interrupts must set to enable the corresponding bits in the IMR register regardless of the INTM value The only exceptions are the nonmask able interrupts RS and NMI The IDLE2 mode halts the on chip peripherals as well as the CPU Because the on chip peripherals are stopped in this mode they cannot be used to generate the interrupt to wake up the C54x DSP as with IDLE1 However power is significantly reduced because the device is completely stopped Use the IDLE 2 instruction to enter the IDLE2 mode To terminate IDLE2 activate any of the external interrupt pins RS NMI and INTx with a 10 ns minimum pulse If INTM 0 when the wake up interrupt takes place the C54x DSP enters the ISR when IDLE2 is terminated If INTM 1 the C54x DSP continues with the instruction following IDLE 2 instruction All wake up interrupts must be set to enable the corresponding bits in the IMR register regardless of the INTM value Reset all peripherals when IDLE2 terminates especially if they are externally clocked When RS is the wake up interrupt in IDLE2 a 10 ns minimum pulse of RS can activate the reset sequence The IDLE3 mode functions like IDLE2 but it also halts the PLL IDLE3 is used for acomplete shutdown of the C54x DSP This mode reduces power dissipa
140. 320C549 Interrupt Locations and Priorities 0 0 cece eee eee 6 26 TMS320C5402 Interrupt Locations and Priorities 0 cece cee eee ee 6 27 TMS320C5410 Interrupt Locations and Priorities 0 ccc eee eee 6 28 TMS320C5420 Interrupt Locations and Priorities 0 0 0 cece ee eee 6 29 Operation During the Four Power Down Modes 0 cece eee eee teens 7 1 DARAM BIOCKS 2 300 ctoseegesrnbodav nbdanndtander sanded owes iebawivaendewwed 7 2 Accessing DARAM Blocks 00000 cece cece een ete eens 7 3 Recommended Instructions for Accessing Memory Mapped Registers 7 4 Instructions That Access DAGEN Registers in the Read Stage 4 7 5 Store Type InstructionS ie isiat ai aaa iiaia y aiaia a a eaa a i paca a aea a eee 7 6 Pipeline Protected Instructions for Updating ARX 000 0c eee e eee eee T Latencies for Accessing ARX 0 cece eect teen nent EDENE KEEA Da 7 8 Latencies for Accessing BK 0c e eee eee ee eee eens 7 9 Latencies for SP in Compiler Mode CPL 1 000 c cee eee eee eee 7 10 Pipeline Protected Instructions to Update SP in Noncompiler Mode CPL 0 7 11 Latencies for SP in Noncompiler Mode CPL 0 0 00 e cece eee eens 7 12 Pipeline Protected Instructions for Updating T 0006s 7 13 Latencies for the T Register Based on Second Instruction Category 7 14 Recommended Inst
141. 37 describes how to install the TMS320C54x simulator and the C source debugger for the TMS320C54x DSP The installation for MS DOS PC DOS SunOS Solaris and HP UX systems is covered TMS320C54x Evaluation Module Technical Reference literature number SPRU135 describes the TMS320C54x evaluation module its features design details and external interfaces TMS320C54x Code Generation Tools Getting Started Guide literature number SPRU147 describes how to install the TMS320C54x assembly language tools and the C compiler for the TMS320C54x devices The installation for MS DOS OS 2 SunOS Solaris and HP UX 9 0x systems is covered TMS320C5xx C Source Debugger User s Guide literature number SPRUO099 tells you how to invoke the TMS320C54x emulator evaluation module and simulator versions of the C source debugger interface This book discusses various aspects of the debugger interface including window management command entry code execution data management and breakpoints It also includes a tutorial that introduces basic debugger functionality Read This First vii Related Documentation from Texas Instruments Technical Articles Technical Articles viii Read This First TMS320C54x Simulator Addendum literature number SPRU170 tells you how to define and use a memory map to simulate ports for the TMS320C54x DSP This addendum to the TMS320C5xx C Source Debugger User s Guide disc
142. 43 Data Memory 0000h 005Fh Memory mapped registers 0060h 007Fh Scratch pad DARAM 0080h 27FFh On chip DARAM 2000h 4000h 6000h 8000h 2800h FFFFh External A000h C000h E000h FFFFh SPRU131G Figure 3 3 Memory Maps for the C545 and C546 C545 C546 Program Memory 0000h 0000h OVLY 0 0000h 17FFh External OVLY 1 0000h 007Fh Reserved 0080h 17FFh On chip DARAM 2000h 2000h 1800h 3FFFh External 4000h 4000h 6000h 6000h 8000h 8000h MP MC 0 4000h FF7Fh On chip ROM FF80h FFFFh_ Interrupts internal A000h A000h MP MC 1 4000h FF7Fh External FF80h FFFFh Interrupts external C000h C000h E000h E000h FFFFh FFFFh SPRU131G Memory Space C545 C546 Data Memory 0000h 005Fh Memory mapped registers 0060h 007Fh Scratch pad DARAM 0080h 17FFh On chip DARAM 1800h BFFFh_ External DROM 0 COOOh FFFFh External DROM 1 COOOh FEFFh On chip ROM FFOOh FFFFh Reserved Memory 3 5 Memory Space Figure 3 4 Memory Maps for the C548 Hex Program 9000 Reserved OVLY 1 or External OVLY 0 007F 9080 On Chip DARAM OVLY 1 or External OVLY 0 1FFF 2009 On Chip SARAM OVLY 1 or External OVLY 0 7FFF 8000 External FF7F FF80 Interrupts and Reserved External FFFF MP MC 1 Microprocessor Mode 3 6 Memory Hex Program 0000 Reserved OVLY 1 or External OVLY 0 007
143. 7 Bit reversed addressing enhances execution speed and program memory for FFT algorithms that use a variety of radixes In this addressing mode ARO specifies one half of the size of the FFT The value contained in ARO must be equal to 2N 1 where Nis an integer and the FFT size is 2N An auxiliary regis ter points to the physical location of a data value When you add ARO to the auxiliary register using bit reversed addressing the address is generated in a bit reversed fashion with the carry bit propagating from left to right instead of the normal right to left The syntaxes for each of the two bit reversed addressing modes are shown in Table 5 4 for MOD 4 and 7 respectively Assume that the auxiliary registers are eight bits long that AR2 represents the base address of the data in memory 011000005 and that ARO contains the value 0000 10005 Example 5 1 shows a sequence of modifications of AR2 and the resulting values of AR2 Example 5 1 Sequence of Auxiliary Registers Modifications in Bit Reversed Addressing AR2 0B AR2 0110 0000 Oth value AR2 0B AR2 0110 1000 lst value AR2 0B AR2 0110 0100 2nd value AR2 0B AR2 0110 1100 3rd value AR2 0B AR2 0110 0010 4th value AR2 0B AR2 0110 1010 5th value AR2 0B AR2 0110 0110 6th value AR2 0B AR2 0110 1110 7th value Table 5 5 shows the relationship of the bit pattern of the index steps and the four LSBs of AR2 which contain the bi
144. A 10 368 MHz test clock source is provided You can also provide your own test clock for greater flexibility Figure A 2 Emulator Cable Pod Interface 5V m 74F175 180 Q 270 Q JP 74LVT240 10 368 MHz TMS pin 1 TDO pin 7 GND pins 4 6 8 10 12 TDI pin 3 EMUO pin 13 gt EMU1 pin 14 oo TCK pin 11 T Vv 270 Q TRST pin 2 TCK_RET pin 9 t pi i Do PD Vcc pin 5 p gt 10092 TL7705A t The emulator pod uses TCK_RET as its clock source for internal synchronization TCK is provided as an optional target system test clock source SPRU131G Design Considerations for Using XDS510 Emulator A 5 Emulator Cable Pod Signal Timing A 4 Emulator Cable Pod Signal Timing Figure A 3 shows the signal timings for the emulator cable pod Table A 2 defines the timing parameters illustrated in the figure These timing parame ters are calculated from values specified in the standard data sheets for the emulator and cable pod and are for reference only Texas Instruments does not test or guarantee these timings The emulator pod uses TCK_RET as its clock source for internal synchroni zation TCK is provided as an optional target system test clock source Figure A 3 Emulator Cable Pod Timings m 1 gt l TCK_RET LO O NO Z N 2 a ee TMS TDI X le 4 Table A 2 Emulator Cable Pod Timing Parameters 1 te TCK Cycle time TCK_RET 35 200 ns 2 tw TCKH Pulse
145. AL from driving EMU0 1 IN to a low state If you use sources other than TI processors such as logic analyzers to drive EMU0 1 their signal lines must be isolated by open collector drivers and be inactive during RUNB and other external analysis counts You must connect the EMU0 1 OUT signals to the emulation header or directly to a test bus controller Figure A 12 Suggested Timings for the EMUO and EMU1 Signals E VWF UF 7 VF EMUO0 1 OUT RRA EMU0 1 IN RRA A 22 Design Considerations for Using XDS510 Emulator SPRU131G Emulation Design Considerations Figure A 13 EMU0 1 Configuration With Additional AND Gate to Meet Timing Requirements of Greater Than 25 ns Pullup Open resistor collector See EMUO 1 drivers Backplane lt Device Device XCNT_ENABLE ie ae ESN E OES ET EE EETA NEE J EMU0 1 IN PAL Pullup EMU0 1 OUT 7 resistor rs a r a l TCK To Emulator EMUO Pullup Open resistor Circuitry required for gt 25 ns rise collector TE EMUO 1 fall time modification drivers 0 s O D 3 lt fe D EMU1 signal from other boards Notes 1 The low time on EMU0 1 IN should be at least one TCK cycle and less than 10 us Software will set the EMU0 1 OUT port to a high state 2 To enable the open collector driver and pullup resistor on EMU1 to provide rise
146. AM Single access RAM SPRU131G SPRU131G TMS320C54x DSP Key Features LJ Instruction set Single instruction repeat and block repeat operations Block memory move instructions for better program and data management Instructions with a 32 bit long operand Instructions with 2 or 3 operand simultaneous reads Arithmetic instructions with parallel store and parallel load Conditional store instructions Fast return from interrupt Lj On chip peripherals Software programmable wait state generator Programmable bank switching logic On chip phase locked loop PLL clock generator with internal oscilla tor or external clock source With the external clock source there are several multiplier values available from one of the following device options Option 1 Option2 Option 3 1 0 1 0 Software programmable PLLt 1 5 4 0 2 0 4 5 3 0 5 0 TThe C541B C545A C546A C548 C549 C5402 C5410 and C5420 have a software programmable PLL and two additional saturation modes The software programmable PLL is described in section 8 5 2 Software Programmable PLL on page 8 27 The saturation modes are described in section 4 1 2 Processor Mode Status Register PMST on page 4 6 Each device offers selection of clock modes from one option list only m External bus off control to disable the external data bus address bus and control signals Data bus with a bus holder feature m Programmable timer Introduction 1 7 TMS320
147. Addressing SPRU131G Interrupts For enabled interrupts when IACK occurs the interrupt number is indicated by address bits A6 A2 on the rising edge of CLKOUT If the interrupt vectors reside in on chip memory and you want to observe the addresses the C54x DSP must operate in address visibility mode AVIS 1 so that the interrupt number can be decoded If an interrupt occurs while the C54x DSP is on hold and HM 0 the address cannot be present when IACK becomes active 6 10 5 Phase 3 Execute Interrupt Service Routine ISR SPRU131G Interrupt After acknowledging the interrupt the CPU 1 Stores the program counter PC value the return address to the top of the stack in data memory We ee Note The program counter extension register XPC does not get pushed to the top of the stack that is it does not get saved on the stack Therefore if an ISR is located on a different page from the vector table you must push the XPC on the stack prior to branching to the ISR A FRET E can be used to return from the ISR a 2 Loads the PC with the address of the interrupt vector 3 Fetches the instruction located at the vector address If the branch is delayed and you also stored one 2 word instruction or two 1 word instruc tions the CPU also fetches these words 4 Executes the branch which leads it to the address of your ISR If the branch is delayed the additional instruction s are executed before the branch
148. Any instruction that does not fit in Category has zero latency Example 7 50 SXM Update With No Latency RSBX SXM This instruction modifies the SXM bit of Sl ADD AR1 100h A Example 7 51 SXM Update With a 1 Cycle Latency a RSBX SXM This SXM load requires one cycle of latency NOP LD AR5 A b POPM STI This instruction modifies the SXM bit of NOP S21 ADD AR2 A c STLM A ST1 This instruction modifies the SXM bit of a Oily NOP SUB AR2 A 7 68 Pipeline SPRU131G Pipeline Latencies 7 5 7 6 ASM Field Used for Shift Operations Table 7 21 SPRU131G A pipeline conflict can occur if two conditions are simultaneously met J An instruction modifies ASM _ The next instruction uses ASM as the shift count value The conflict occurs because the second instruction reads ASM in a pipeline stage that occurs before the previous instruction updates it Table 7 21 lists instructions that do not have any latency for writing to the ASM bit field Use these instructions wherever possible to avoid any conflicts Pipeline Protected Instructions for Writing to ASM To do this Use this instruction Load an immediate number to ASM LD k ASM Copy contents of a memory location to ASM LD Smem ASM Table 7 22 lists the latencies between instructions that write to ASM and those that subsequently use it Note You are responsible for rearranging
149. BX CPL CPL b Categories for the second instruction Category All instructions that use direct addressing mode except those listed in Category Il Legend Note 7 66 MMR Any memory mapped register Second Instruction Category Category Il 2 1 2 1 3 2 3 3 3 2 3 2 3 2 Category Il MVKD dmad dirmem MVPD pmad dirmem MACP dirmem pmad src MACD dirmem pmad src ADD dirmem shift src dst LD dirmem shift dst STH src shift dirmem hard raced STL arc shift dirmem SUB dirmem shift src dst dirmem A read or write operand using direct addressing mode when CPL 0 status Destination operand pointing to ST1 to modify CPL in either direct indirect or memory mapped addressing mode T Shift value between 16 and 15 Any instruction that does not fit in either of the two categories has zero latency Pipeline SPRU131G Pipeline Latencies Example 7 47 CPL Update With a 1 Cycle Latency STM k ST1 This instruction modifies the CPL gt bit of ST NOP MVKD 1000h 30h Data read from 1000h is written to SP 30h Example 7 48 CPL Update With a 2 Cycle Latency RSBX CPL CPL is changed from 1 to 0 NOP Two NOPs are required since a LD NOP with an extended shift is being used to access an operand LD 27h 1 A The operand is read from the current data page Example 7 49 CPL Update With a 3 Cycle Latency SSBX CPL CPL is changed from 0
150. Bits 9 13 TDM Serial Port Registers 0 0 cece ete eeeee ete nae 9 14 Interprocessor Communications Scenario 066 9 15 TDM Register Contents 0 00 c cee teens 10 1 Key External Interface Signals 00 0 c cece teen eee 10 2 Software Wait State Register SWWSR Bit Summary 0020000 cece eee 10 3 C548 C549 C5402 C5410 C5420 Software Wait State Register SWWSR BIPSUMMANY seserimi a ar e E New ae aes face Mae a aaa oars os ane 10 4 Number of CLKOUT1 Cycles Per Access for Various Numbers of Wait States 10 5 Bank Switching Control Register BSCR Bit Summary 0202 00 ee eee 10 6 Relationship Between BNKCMP and Bank Size 0 0 0 cece cee eee eee 10 7 State of Signals When External Bus Interface is Disabled EXIO 1 10 8 Counter Down Time With PLL Multiplication Factors at 40 MHz Operation A 1 14 Pin Header Signal Descriptions 0 c cece eee eae A 2 Emulator Cable Pod Timing Parameters 0c cece eee e eee eens B 1 Development Support Tools Part Numbers 0 0 0 c cece cece eee eee ees SPRU131G Tables Xxix Examples 4 1 7 6 7 8 7 9 7 10 7 11 7 12 7 13 7 14 7 15 7 16 7 17 7 18 7 19 7 20 7 21 7 22 7 23 7 24 7 25 7 26 7 27 7 28 7 29 7 30 XXX USO SMUL Bi is etc cao a tanaeed ined need ined ina ed teehee dbdagewh aad Use of SST Bilt fackiwtawis Sarai dayed s david lauds sa
151. C54x DSP Key Features 1 8 Introduction E Ports Device C541 C542 C543 C545 C546 C548 C549 C5402 C5410 C5420 Serial Ports Multi Host Port Channel Interface Synchronous Buffered Buffered 0 2 0 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 1 0 2 0 1 0 2 0 1 0 0 2 1 0 0 3 1 0 0 6 instruction 40 MIPS 50 MIPS 66 MIPS 80 MIPS 100 MIPS Device C541 C541B C542 C543 C545 C545A C546 C546A C548 C549 VC549 VC5402 Power Supply 5V 3V 3 3V 3V 3 3V 5V 3V 3 3V 3V 3 3V 3V 3 3V 3V 3 3V 3V 3 3V 3V 3 3V 3 3 V 3 3 V 3 3 V 2 5 core 3 3 V 1 8 core Speed 25 ns 25 ns 20 ns 15 ns 25 ns 25 ns 20 ns 25 ns 20 ns 25 ns 20 ns 15 ns 25 ns 20 ns 15 ns 20 ns 15 ns 15 ns 12 5 ns 10 ns 10 ns Package 100 pin TQFP 100 pin TQFP 100 pin TQFP 144 pin TQFP Time Division Multiplexed 0 1 1 D Oo D O QO 1 Speed 25 20 15 12 5 10 nst execution time for a single cycle fixed point 128 pin 144 pin TQFP 100 pin TQFP 128 pin TQFP 128 pin TQFP 100 pin TQFP 100 pin TQFP 144 pin TQFP 144 pin TQFP 144 pin Micro Star BGA 144 pin TQFP 144 pin Micro Star BGA 144 pin TQFP 144 pin Micro Star BGA SPRU131G TMS320C54x DSP Key Features Device Power Supply Speed Package VC5410 3 3 V 2 5 core 10ns 144 pin TQFP 176 pin Micro Star BGA vc5420 3 3 V 1 8 core 10ns 144 pin TQFP 144 pin Micro Star BGA J Power m Power consumption control with IDLE 1
152. C54x DSP dual access RAM to complete the transaction The C54x DSP can then access the data within its memory space The HPI RAM can also be used as general purpose dual access data or program RAM The HPI has two modes of operation shared access mode SAM and host only mode HOM In shared access mode the normal mode of operation both the C54x DSP and the host can access HPI memory In this mode asynchronous host accesses are resynchronized internally and in the case of a conflict between a C54x DSP and a host cycle where both accesses are reads or writes the host has access priority and the C54x DSP waits one cycle In host only mode only the host can access HPI memory while the C54x DSP is in reset or in IDLE2 with all internal and external clocks stopped The host can therefore access the HPI RAM while the C54x DSP is in its minimum power consumption configuration The HPI supports high speed back to back host accesses In shared access mode the HPI can transfer one byte every five CLKOUT cycles that is 64M bps with the C54x DSP running at a 40 MHz CLKOUT The HPI is designed so the host can take advantage of this high bandwidth and run at frequencies up to Fd n 5 where Fd is the C54x DSP CLKOUT frequency and nis the number of host cycles for an external access Therefore with a 40 MHz C54x DSP and common values of 4 or 3 for n the host can run at speeds of up to 32 or 24 MHz without requiring wait states In the host o
153. CH TECH 85 pages 246 249 April 1985 10 Troullinos G and J Bradley Split Band Modem Implementation Using the TMS32010 Digital Signal Processor Conference Records of Electro 86 and Mini Micro Northeast USA 14 1 1 21 May 1986 Automotive 1 Lin K Trends of Digital Signal Processing in Automotive nternational Congress on Transportation Electronic CONVERGENCE 88 October 1988 Consumer 1 2 Frantz G A J B Reimer and R A Wotiz Julie The Application of DSP to a Product Speech Tech Magazine USA September 1988 Reimer J B and G A Frantz Customization of a DSP Integrated Circuit for a Customer Product Transactions on Consumer Electronics USA August 1988 Read This First xiii Technical Articles Trademarks 3 Reimer J B P E Nixon E B Boles and G A Frantz Audio Customiza tion of a DSP IC Digest of Technical Papers for 1988 International Con ference on Consumer Electronics June 8 10 1988 Medical 1 Knapp and Townshend A Real Time Digital Signal Processing System for an Auditory Prosthesis Proceedings of ICASSP 88 USA Volume A page 2493 April 1988 2 Morris L R and P B Barszczewski Design and Evolution of a Pocket Sized DSP Speech Processing System for a Cochlear Implant and Other Hearing Prosthesis Applications Proceedings of ICASSP 88 USA Vol ume A page 2516 April 1988 Development Support 1 Mersereau
154. Compare Select and Store Unit CSSU on page 4 24 for more details about this unit The C54x DSP offers seven basic data addressing modes E m m Immediate addressing uses the instruction to encode a fixed value Absolute addressing uses the instruction to encode a fixed address Accumulator addressing uses accumulator A to access a location in program memory as data Direct addressing uses seven bits of the instruction to encode the lower seven bits of an address The seven bits are used with the data page point er DP or the stack pointer SP to determine the actual memory address Indirect addressing uses the auxiliary registers to access memory Memory mapped register addressing uses the memory mapped registers without modifying either the current DP value or the current SP value Stack addressing manages adding and removing items from the system stack During the execution of instructions using direct indirect or memory mapped register addressing the data address generation logic DAGEN computes the addresses of data memory operands For a detailed discussion of the data addressing modes see Chapter 5 Data Addressing Architectural Overview SPRU131G Program Memory Addressing Pipeline Operation 2 5 Program Memory Addressing Program memory is usually addressed on a C54x DSP with the program counter PC With some instructions however absolute addressing may be used to access data items that
155. DLE3 Host or Other Device C54x CPU Mode C54x clock Switches mode to HOM HOM Running Executes a NOP HOM Running Executes IDLE 2 or IDLE 3 HOM Running instruction May stop DSP clock In IDLE2 3 HOM Stopped or running Turns on DSP clock if it In IDLE2 3 HOM Running was stoppedt Sends an interrupt to In IDLE2 3 HOM Running DSP C54x CPU wakes up from HOM Running IDLE2 3 C54x CPU switches mode SAM Running to SAM f Sufficient wake up time must be ensured when the C54x on chip PLL is used 8 52 On Chip Peripherals SPRU131G Host Port Interface 8 6 6 Access of HPI Memory During Reset The C54x DSP is not operational during reset but the host can access the HPI allowing program or data downloads to the HPI memory When this capability is used it is often convenient for the host to control the C54x DSP reset input The sequence of events for resetting the C54x DSP and downloading a program to HPI memory while the C54x DSP is in reset is summarized in Table 8 30 and corresponds to the reset of the C54x DSP Initially the host stops accessing the HPI at least six C54x CPU periods before driving the C54x DSP reset line low The host then drives the C54x DSP reset line low and can start accessing the HPI after a minimum of four C54x CPU periods The HPI mode is automatically set to HOM during reset allowing high speed program download The C54x CPU clock can even be stopped at this time however the clock must be running when the reset line
156. DXR is updated once per transmission this mode will continue Over writes to DXR behave just as in burst mode the last data written will be transmitted XSR operation is the same as in burst mode A new external FSX pulse will abort the present transmission cause one data packet to be lost and initiate a new continuous mode transmit This is explained in more detail in sec tion 9 2 6 Serial Port Interface Exception Conditions on page 9 26 Figure 9 14 Continuous Mode Serial Port Transmit FSX TXM 1 A a a a ee ee ee ee ee DX FO 1 CA1 A A2 KAS KAS KAS _X_AG_K_A7_XK_AB_X_Bi X_B2 X_B3_X_B4 MSB LSB xapy pt tt tt tt SP XINT a i M XRDY ey ones ee ee ee BSP XINT BSP _ Ne aaa Ne aM t DXR loaded SPRU131G A XSR loaded SP a t a a XSR DXR XSR loaded reloaded reloaded xsr BSP reloaded SP Continuous mode reception is similar to the transmit operation After the initial frame sync pulse on FSR no further frame syncs are required This mode will continue as long as DRR is read every transmission If DRR is not read by the end of the next transfer the receiver will halt and RSRFULL is set indicating overrun See section 9 2 6 Serial Port Interface Exception Conditions Serial Ports 9 25 Serial Port Interface Overrun in continuous mode effects the SP and the BSP differently On the SP once overrun has occurred reading DRR will resta
157. Describes the JTAG emulator cable how to construct a 14 pin connector on your target system and how to connect the target system to the emulator A 1 Designing Your Target System s Emulator Connector 14 Pin Header A2 Bus Protocol ccc stan nevacsntan ae anes chee andes ead ena aR eee a AS Emulator Cable Pod 2 nett ett EEE nee nnes Contents SPRU131G Cc D Contents A 4 Emulator Cable Pod Signal Timing 0 cece eee teen teen eae A 5 Emulation Timing Calculations 0000 c eect eee A 6 Connections Between the Emulator and the Target System 2 0005 A 6 1 Buff ring Signals ici csdiae ede wee Oe eked eae dadew aiii eer ade A 6 2 Using a Target System Clock 00 cece eect eee A 6 3 Configuring Multiple Processors 00000 e cece eee eee A 7 Physical Dimensions for the 14 Pin Emulator Connector 22 2 0008 A 8 Emulation Design Considerations 2 0 000 cece eee eee A 8 1 Using Scan Path Linkers 000 cece eee ee eee A 8 2 Emulation Timing Calculations for a Scan Path Linker SPL A 8 3 Using Emulation Pins 0 0 00 c cece eee ete eens A 8 4 Performing Diagnostic Applications 0c cee eee Development Support and Part Order Information 0 0ee eee eee eee Provides device part numbers and support tool ordering information for the TMS320C54x DSP and development support information available fr
158. E 2 or IDLE 3 instruction Serial Ports 9 55 Time Division Multiplexed TDM Serial Port Interface 9 4 Time Division Multiplexed TDM Serial Port Interface The time division multiplexed TDM serial port allows the C54x DSP to communicate serially with up to seven other devices The TDM port therefore provides a simple and efficient interface for multiprocessing applications The TDM serial port is a superset of the serial port described in section 9 2 on page 9 4 By means of the TDM bit in the TDM serial port control register TSPC the port can be configured in multiprocessing mode TDM 1 or stand alone mode TDM 0 When in stand alone mode the port operates as described in section 9 2 When in multiprocessing mode the port operates as described in this section The port can be shut down for low power consumption via the XRST and RRST bits as described in section 9 2 Basic Time Division Multiplexed Operation Time division multiplexing is the division of time intervals into a number of sub intervals with each subinterval representing a communications channel according to a prespecified arrangement Figure 9 30 shows a 4 channel TDM scheme Note that the first time slot is labeled chan 1 channel 1 the next chan 2 channel 2 etc Channel 1 is active during the first communications period and during every fourth period thereafter The remaining three channels are interleaved in time with channel 1 Figure 9 30
159. Example 7 64 DROM Setup Followed by a Read Access DP 0 ORM 8h PMST This instruction sets DROM 1 NOP NOP NOP LD AR3 A Reads from on chip DROM Example 7 65 DROM Setup Followed by a Dual Read Access STM k PMST This instruction sets DROM 1 NOP NOP MPY AR3 AR4 A This instruction reads from on chip DROM 7 78 Pipeline SPRU131G Pipeline Latencies 7 5 10 Latencies for Memory Mapped Accesses to Accumulators Accumulators A and B can be addressed as memory mapped registers using memory mapped direct or indirect addressing modes Generally it is not useful to access accumulators as memory mapped registers because the C54x DSP instruction set supports direct accesses to the accumulators Some examples of the instructions that support direct access to accumulators are ADD SUB AND OR XOR LD STH STL MAC and MPYA When the two accumulators are accessed using instructions that do not access them as memory mapped registers no pipeline latencies occur In rare cases when you access the accumulators through the memory mapped regis ters AG AH AL BG BH and BL you can use any instruction that uses memory mapped direct or indirect addressing modes to access operands Examples of such instructions are POPM AL and PSHM AH Note that DP must be zero in order to access memory mapped registers via direct addres sing modes A pipeline conflict can occur when two conditions a
160. F 0080 On Chip DARAM OVLY 1 or External OVLY 0 1FFF 2 oog On Chip SARAM OVLY 1 or External OVLY 0 7FFF 8000 External EFFF F000 Reserved F7FF F800 On Chip ROM 2K Words FF7F FF80 Interrupts and Reserved On Chip FFFF MP MC 0 Microcomputer Mode Hex 0000 005F 0060 007F 0080 1FFF 2000 7FFF 8000 FFFF Data Memory Mapped Registers Scratch Pad RAM On Chip DARAM 8K Words On Chip SARAM 24K Words External SPRU131G Figure 3 5 Memory Maps for the C549 Hex Program poog Reserved OVLY 1 or External OVLY 0 007F 9080 On Chip DARAM OVLY 1 or External OVLY 0 1FFF 2009 On Chip SARAM OVLY 1 or External OVLY 0 7FFF 8000 External FF7F FF80 Interrupts and Reserved External FFFF MP MC 1 Microprocessor Mode SPRU131G Hex Program 9000 Reserved OVLY 1 or External OVLY 0 007F 0080 On Chip DARAM OVLY 1 or External OVLY 0 1FFF 2 009 On Chip SARAM OVLY 1 or External OVLY 0 7FFF 8000 External BFFF c000 On Chip ROM 16K Words FEFF FF00 Interrupts and Reserved On Chip FFFF MP MC 0 Microcomputer Mode Hex 0000 005F 0060 007F 0080 1FFF 2000 7FFF 8000 BFFF co00 FEFF FF00 FFFF Memory Space Data Memory Mapped Registers Scratc
161. FFF Page 0 Hex Program 010000 Mapped to Lower Page 0 OVLY 1 External OVLY 0 017FFF 018000 External 01FFFF Page 1 MP MC 1 Microprocessor Mode SPRU131G Hex 0000 007F 0080 1FFF 2000 7FFF 8000 BFFF coo0 FF7F FF80 FFFF Program Reserved OVLY 1 External OVLY 0 On Chip DARAM OVLY 1 External OVLY 0 On Chi SARAM1 OVLY 1 External OVLY 0 External 16K Words Interrupts and Reserved On Chip ROM Page 0 Hex Program 010000 Mapped to Lower Page 0 OVLY 1 External OVLY 0 017FFF 018000 On Chip SARAM2 01FFFF Page 1 MP MC 0 Microcomputer Mode Memory Space Hex Data 0000 Memory Mapped Registers 005F 0060 Scratch Pad RAM 007F 0080 On Chip DARAM 8K Words 1FFF 2000 On Chi SARAM1 24K Words 7FFF 8000 On Chip SARAM2 DROM 1 External DROM 0 FFFF Memory 3 11 Memory Space Figure 3 10 Extended Program Memory Maps for the C5410 On chip RAM Not Mapped in Program Space and Data Space OVLY 0 00 0000 01 0000 02 0000 7F 0000 Page 127 64K Words 00 FFFF 01 FFFF 02 FFFF 7F FFFF XPC 0 XPC 1 XPC 2 XPC 127 Figure 3 11 Extended Program Memory Maps for the C5410 On chip RAM Mapped in Program Space and Data Space OVLY 1 xx 0000 xx 7FFF XPC xx 00 8000 01 8000 02 8000 7F 8000 Page 0 Page 2 Page 127 32K 32K 32K Words Ex Wo
162. FO definition format FO definition format extension FE definition fractional mode FRCT 4 5 definition D 9 frame ignore FIG definition frame synchronization mode FSM definition Index 8 frame synchronization polarity FSP definition FRCT definition definition FSM 9 11 definition FSP 9 38 D 9 definition D 9 general purpose applications generator clock wait state graphics imagery applications ki half cycle accesses instruction performing dual operand write 7 28 instruction performing operand read write instruction performing single operand read instruction performing single operand write instruction word prefetch 7 28 half cycle accesses to dual access memory definition hardware block diagram timer AE Harvard architecture 1 5 header 14 pin dimensions 14 pin HINT definition HM definition HOLD and HOLDA minimum timing hold mode hold mode HM definition HOM host only mode host port interface 2 14 8 36 to B 54 block diagram control register bit descriptions definition details of operation functional description 8 37 generic block diagram host read write access input control signals memory access suring reset 8 53 memory access mode SAM HOM 8 51 operation during reset 8 53 register description signal names and functions 8 40 timing diagram host processor interrupt HINT definition D 10 host only mode HOM host only mode HO
163. Fh 1 Program space The field value 0 7 corresponds to the number of wait states for J XPA 0 xx8000 xxFFFFh g XPA 1 400000h 7FFFFF 1 Program space The field value 0 7 corresponds to the number of wait states for J XPA 0 xx0000 xx7FFFh J XPA 1 000000 3FFFFFh Figure 10 4 is a block diagram of the wait state generator logic for external program space When an external program access is decoded the appropri ate field of the SWWSR is loaded into the counter If the field is not 000 a not ready signal is sent to the CPU and the wait state counter is started The not ready condition is maintained until the counter decrements to 0 and the external READY line is set high The external READY and the wait state READY are ORed together to generate the CPU WAIT signal The READY line is machine sampled at the falling edge of CLKOUT The processor detects READY only if a minimum of two software wait states are programmed The external READY line is not sampled until the last wait state cycle External Bus Operation 10 7 External Bus Control Figure 10 4 Software Wait State Generator Block Diagram decoder External logic 3 bit counter READY At reset all fields in the SWWSR are set to 111b SWWSR 7FFFh the maximum number of wait states for external accesses This feature ensures that the CPU can communicate with slow external memories during processor initialization T
164. Figure 10 21 External Bus Reset Sequence RS Address Previous state FF80h R W Bank gt t switching Reset state _ gt Notes 1 RS is an asynchronous input and can be asserted at any point during a clock cycle If the specified timings are met the sequence shown occurs otherwise an additional delay of one clock cycle can occur 2 During reset the data bus is placed in high impedance and the control signals are de asserted 3 The reset vector is fetched with seven wait states 4 The bank switching cycle is inserted in the first access after reset SPRU131G External Bus Operation 10 25 Start Up Access Sequences 10 5 2 IDLE3 The execution of the IDLE 3 instruction initiates the IDLE3 power down mode In this power down mode the PLL is halted completely to reduce power consumption In the IDLE mode the input clock can be kept running without additional power consumption because a transfer gate inside the C54x DSP isolates the clock from the internal logic The PLL must be restarted and locked before the C54x DSP can resume processing when it exits IDLE3 This power down mode is terminated by activating the external interrupt pins INTn NMI and RS in a particular sequence Table 10 8 shows the wake up time of IDLE3 with the INTn and NMI signals These times are defined for the hardware configurable PLL The times for the software programmable PLL are given in sectio
165. HBIL if HAS is not used and HDS1 or HDS2 are already low this is explained in further detail later in this section Figure 8 8 on page 8 42 shows the equivalent circuit of the HCS HDS1 and HDS2 inputs Parallel bidirectional 3 state data bus HD7 MSB through HDO LSB are placed in the high impedance state when not outputting HDSx HCS 1 or when EMU1 OFF is active low SPRU131G Table 8 21 HPI Pin HDS1 HDS2 HRDY HR W Host Pin Statet Read strobe and l write strobe or data strobe Host interrupt O Z input Asynchronous O Z ready Read Write strobe l address line or multiplexed address data TI Input O Output Z High impedance SPRU131G Host Port Interface HPI Signal Names and Functions Continued Signal Function Data strobe inputs Control transfer of data during host access cycles Also when HAS is not used used to sample HBIL HCNTLO 1 and HRW when HCS is already low which is the case in normal operation Hosts with separate read and write strobes connect those strobes to either HDS1 or HDS2 Hosts with a single data strobe connect it to either HDS1 or HDS2 connecting the unused pin high Regardless of HDS connections HR W is still required to determine direction of transfer Because HDS1 and HDS2 are internally exclusive NORed hosts with a high true data strobe can connect this to one of the HDS inputs with the other HDS input connected low Figure 8
166. HPIC Host can read or write the HPI data latches HPIA is automatically postincremented each time a read is performed and preincremented each time a write is performed Host can read or write the address register HPIA This register points to the HPI memory Host can read or write the HPI data latches HPIA is not affected On the C54x DSP HPI memory is a 2K x 16 bit word block of dual access RAM that resides at 1000h to 17FFh in data memory space and optionally depending on the state of the OVLY bit in program memory space From the host interface the 2K word block of HPI memory can conveniently be accessed at addresses 0 through 7FFh however the memory can also be accessed by the host starting with any HPIA values with the 11 LSBs equal to 0 For example the first word of the HPI memory block addressed at 1000h by the C54x DSP in data memory space can be accessed by the host with any of the following HPIA values 0000h 0800h 1000h 1800h F800h On Chip Peripherals SPRU131G Host Port Interface The HPI autoincrement feature provides a convenient way of accessing consecutive word locations in HPI memory In the autoincrement mode a data read causes a postincrement of the HPIA and a data write causes a preincre ment of the HPIA Therefore if a write is to be made to the first word of HPI memory with the increment option due to the preincrement nature of the write operation the HPIA should first be loaded with any of th
167. IDLE 2 and IDLE 3 instruc tions for power down modes Control to disable the CLKOUT signal J Emulation IEEE Standard 1149 1 boundary scan logic interfaced to on chip scan based emulation logic SPRU131G Introduction 1 9 Od a T 0 Architectural Overview This chapter provides an overview of the architectural structure of the TMS320C54x DSP which comprises the central processing unit CPU memory and on chip peripherals The C54x DSPs use an advanced modified Harvard architecture that maxi mizes processing power with eight buses Separate program and data spaces allow simultaneous access to program instructions and data providing a high degree of parallelism For example three reads and one write can be performed ina single cycle Instructions with parallel store and application specific instructions fully utilize this architecture In addition data can be transferred between data and program spaces Such parallelism supports a powerful set of arithmetic logic and bit manipulation operations that can all be performed in a single machine cycle Also the C54x DSP includes the control mechanisms to manage interrupts repeated opera tions and function calling Figure 2 1 shows a functional block diagram of the C54x DSP which includes the principal blocks and bus structure Topic Page 2 1 Bus Structure erse sneis nnen cis Seen e ereieie EEEE pe ese 2 3 2 2 Internal Memory Organization 0 ee
168. IFO refers to the port address 5 2 4 Ik Addressing SPRU131G k addressing uses a specific value to specify an address in data space The syntax for Ik addressing uses a symbol or a number to specify an address in data space For example to load accumulator A with the value contained in address BUFFER in data space you would write LD BUFFER A The syntax for Ik addressing allows all instructions that use Smem addres sing to access any location in data space without changing the DP or initializing an AR When this form of absolute addressing is used the length of the instruc tion is extended by one word For example a 1 word instruction would become a 2 word instruction or a 2 word instruction would become a 3 word instruc tion The addition of one word to an instruction affects its usability in delay slots TE Note Instructions using the Ik form of absolute addressing cannot be used with repeat single instructions RPT RPTZ a Data Addressing 5 5 Accumulator Addressing 5 3 Accumulator Addressing Accumulator addressing uses the value in the accumulator as an address This addressing mode is used to address program memory as data Two instructions allow you to use the accumulator as an address Li READA Smem lL WRITA Smem READA transfers a word from a program memory location specified by accu mulator A to a data memory location specified by the single data memory Smem operand of
169. In PCM mode BDXR is transmitted only if its most significant 215 bit is set to 0 If this bit is set to 1 BDXR is not transmitted and BDX is put in high imped ance during the transmission period Frame Ignore This control bit operates only in transmit continuous mode with external frame and in receive continuous mode FIG 0 Frame sync pulses following the first frame pulse restart the transfer FIG 1 Frame sync pulses following the first frame pulse that initiates a transfer operation are ignored Format Extension The FE bit in conjunction with FO in SPC section 9 2 3 Setting the Serial Port Configuration on page 9 8 specifies the word length When FO FE 00 the format is 16 bit words when FO FE 01 the format is 10 bit words when FO FE 10 the format is 8 bit words and when FO FE 11 the for mat is 12 bit words Note that for 8 10 and 12 bit words the received words are right justified and the sign bit is extended to form a 16 bit word Words to transmit must be right justified See Table 9 10 for the word length configurations Clock Polarity This control bit specifies when the data is sampled by the receiver and transmitter CLKP 0 Data is sampled by the receiver on BCLKR falling edge and sent by the transmitter on BCLKX rising edge CLKP 1 Data is sampled by the receiver on BCLKR rising edge and sent by the transmitter on BCLKX falling edge Frame Sync Polarity This control bit specifies whether
170. L lock timer to count before the PLL begins clocking the processor after the PLL is started The PLL counter is a down counter which is driven by the input clock divided by 16 therefore for every 16 input clocks the PLL counter decrements by 1 See section Using the PLLCOUNT Programmable Lock Timer on page 8 31 for more information about PLLCOUNT The PLL counter can be used to ensure that the processor is not clocked until the PLL is locked so that only valid clock signals are sent to the device 2 PLLON OFF PLLon off Enables or disables the PLL part of the clock generator in conjunction with PLLNDIV PLLON OFF and PLLNDIV both force the PLL to operate when PLLON OFF is high the PLL runs independently of the state of PLLNDIV PLLON OFF PLLNDIV PLL State 0 0 off 0 1 on 1 0 on 1 1 on SPRU131G On Chip Peripherals 8 29 Clock Generator Table 8 18 Clock Mode Register CLKMD Bit Summary Continued Bit Name Function 1 PLLNDIV PLL clock generator select Determines whether the clock generator works in PLL mode or in divider DIV mode thus defining the frequency multiplier in conjunction with PLLMUL and PLLDIV PLLNDIV 0 Divider DIV mode is used PLLNDIV 1 PLL mode is used 0 PLLSTATUS PLL status Indicates the mode that the clock generator is operating PLLSTATUS 0 Divider DIV mode PLLSTATUS 1 PLL mode Table 8 19 PLL Multiplier Ratio as a Function of PLLNDIV PLLDIV and PLLMUL PLLNDIV PLLDIV PLLMUL Mul
171. LLDIV values have not been changed since the PLL was locked Switching from DIV mode to PLL mode setting PLLNDIV to 1 activates the PLLCOUNT programmable lock timer when PLLCOUNT is preloaded with a nonzero value and this can be used to provide a convenient method for imple menting the lockup time delay The PLLCOUNT lock timer feature should be used in the previously described situations where the PLL is unlocked unless a reset delay is used to implement the lockup delay or the PLL is not used Switching from DIV mode to PLL mode is accomplished by loading CLKMD The following procedure describes switching from DIV mode to PLL mode when the PLL is not locked When performing this mode switch with the PLL already locked the effect is the same as when switching from PLL mode to DIV mode but in the reverse order In this case the delays of when the new clock mode takes effect are the same When switching from DIV mode to PLL mode with the PLL unlocked or when the mode change will result in unlocked operation the PLLMUL PLLDIV and PLLNDIV bits are set to select the desired frequency multiplier as shown in Table 8 19 on page 8 30 and the PLLCOUNT bits are set to select the required lockup time delay Note that PLLMUL PLLDIV PLLCOUNT and PLLON OFF can only be modified when in DIV mode Once the PLLNDIV bit is set the PLLCOUNT timer begins being decremented from its preset value When the PLLCOUNT timer reaches 0 the switch to PLL mo
172. Latency in Noncompiler Mode CPL 0 2022 000 7 37 SP Load With and Without a 1 Cycle Latency in Noncompiler Mode CPL 0 7 38 SP Load With a 1 Cycle Latency in Noncompiler Mode CPL 0 7 39 T Load With No Latency 0 c cece eee tenet nae 7 40 T Load With a 1 Cycle Latency 0 ccc eee eee eae 7 41 ARP Load With No Latency in Compatibility Mode CMPT 1 2 5 7 42 ARP Load With a 2 Cycle Latency in Compatibility Mode CMPT 1 7 43 ARP Load With a 3 Cycle Latency in Compatibility Mode CMPT 1 7 44 DP Load With No Latency in Noncompiler Mode CPL 0 2222000005 7 45 DP Load With a 2 Cycle Latency in Noncompiler Mode CPL 0 7 46 DP Load With a 3 Cycle Latency in Noncompiler Mode CPL 0 7 47 CPL Update With a 1 Cycle Latency 0 cece cee 7 48 CPL Update With a 2 Cycle Latency 000 0 c cece eee aes 7 49 CPL Update With a 3 Cycle Latency 0 0 ecuun neuan 7 50 SXM Update With No Latency 0 cece eens 7 51 SXM Update With a 1 Cycle Latency 0 0 0 cece eee eee eens 7 52 ASM Update With No Latency 0 00 cece eee eee eens 7 53 ASM Update With a 1 Cycle Latency 0 0 cece eee ena 7 54 Loading BRC Before Executing a New Repeat Block Loop 2 2 0005 7 55 SRCCD Instruction With No Latency 0 c c
173. M D 10 host port interfaces table 2 14 HPI See host port interface HPI address register HPIA HPI control register HPIC C54x reads from HPIC C54x writes to HPIC DSPINT bit ae HINT bit D 10 host reads from heie Ba host writes to HPIC SMOD bit D 16 HPI modes host only o D 10 shared access SAM D 16 I O access timing pins_ 8 20 BIO pin branch control input BIO pin _ 8 20 external XF pin 8 20 XF pin ports parallel serial 2 15 I O memory Index I O pins BIO XF IDLE1 mode IDLE2 mode IDLE3 mode IDLE3 wake up sequence IEEE 1149 1 specification bus slave device rules IEEE standard 1149 1 2 17 ER f 26 27 0 10 definition immediate adie 2 10 5 1 5 4 instructions table s definition indirect addressing 5 1 address modifications address ea operation ARAU 5 11 assembler syntax 5 23 diagram ZE dual operand N ne instruction format compatibility mode 5 24 dual data memory operands 5 20 single data memory operand 5 10 instruction word fields Ymod a single operand addressing 8 24 initialization timer input O INO definition input 1 IN1 definition input sources ALU 4 10 multiplier 4 20 instruction fetch and operand read figure 7 30 Index 9 Index instruction register IR definition D 11 interrupts 10 29 instructions multiconditional 6 17 hardware D 10 interrupt flag register IFR 3 26 internalmemo
174. M A AR2 This instruction does not affect pipeline latency MVMM ARI SP This SP update requires a one cycl latency since the next instruction NOP uses SP when CPL 1 LD 50h A b ADD A B This instruction does not create a DAGEN conflict STM 100h SP This SP update requires a one cycl latency since the next instruction NOP uses SP when CPL 1 LD 50h A c ADD A B This instruction does not affect pipeline latency RETFD SP is incremented after popping the return address NOP LD 50h A This instruction cannot be placed in the first delay slot since it uses direct addressing mode with the new SP value 7 52 Pipeline SPRU131G Pipeline Latencies Example 7 33 SP Load With and Without a 2 Cycle Latency a SP Load With a Two Cycle Latency STLM A BK This instruction creates a DAGEN conflict MVDK 100h SP This SP update requires 2 cycles NOP of latency according to the above NOP table LD 50h A b SP Load With No Latency MVDK 100h SP This SP update requires 1 cycle of latency STLM A BK This instruction is placed after the MVDK instruction to prevent a DAGEN Conk lict LD 50h A No NOPs are required in this case Example 7 34 SP Load With a 2 Cycle Latency in Compiler Mode CPL 1 ADD A B This instruction does not affect pipeline latency POPM SP The new value of SP is popped from
175. M has 5K bytes of on chip program data RAM 28K bytes of on chip ROM two serial ports a timer access to 64K bytes each of external program and data RAM and an external analog interface for evaluation of the C54x family of devices for applications See the TMS320C54x Evaluation Module Technical Reference for detailed information about the C54x EVM B 1 2 Third Party Support SPRU131G The TMS320 family is supported by products and services from more than 100 independent third party vendors and consultants These support products take various forms both as software and hardware from cross assemblers simulators and DSP utility packages to logic analyzers and emulators The expertise of those involved in support services ranges from speech encoding and vector quantization to software hardware design and system analysis To ask about third party services products applications and algorithm development packages contact the third party directly Refer to the 7MS320 Third Party Support Reference Guide for addresses and phone numbers Development Support and Part Order Information B 3 Development Support B 1 3 Technical Training Organization TTO TMS320 DSP Workshops B 1 4 Assistance C54x DSP Design Workshop This workshop is tailored for hardware and software design engineers and decision makers who will be designing and utilizing the C54x generation of DSP devices Hands on exercises throughout the course give participants
176. N generates the address used to access instructions coefficient tables 16 bit immediate operands or other information stored in program memory and puts this address on the PAB PAGEN consists of five registers see Figure 6 1 Program counter PC Repeat counter RC Block repeat counter BRC Block repeat start address register RSA Block repeat end address register REA O O O O L One additional register is used in the C548 C549 C5402 C5410 and C5420 to address extended memory J Program counter extension register XPC 6 2 Program Memory Addressing SPRU131G Program Memory Address Generation Figure 6 1 Program Address Generation Logic PAGEN Registers SPRU131G The C54x devices fetch instructions by putting the value of the PC on the PAB and reading the appropriate location in memory While the memory location is read PC is incremented for the next fetch If a program address discontinuity occurs for example a branch a call a return an interrupt or a block repeat the appropriate address is loaded into the PC The instruction addressed through the PAB is then loaded into the instruction register IR To improve the performance of certain instructions the program address generation unit is also used to fetch operands from program memory Operands are fetched from program memory when the device reads from or writes to a coefficient table or when it transfers data between program and data
177. N NI NIL IL INI VI N I a Ss yo HOLDA hey _ _ Y Address yo ____ X FE80h Dp a pt PAW Fp IY AA sos TOE MSTRB 7 lOSTRB aa a a a a N T T O E a Ge a IACK Bank switching 4 10 32 External Bus Operation Vy N MP MC 1 SPRU131G Appendix A Design Considerations for Using XDS510 Emulator This appendix assists you in meeting the design requirements of the Texas Instruments XDS510 emulator with respect to IEEE 1149 1 designs and discusses the XDS510 cable manufacturing part number 2617698 0001 This cable is identified by a label on the cable pod marked JTAG 3 5V and supports both standard 3 V and 5 V target system power inputs The term JTAG as used in this book refers to TI scan based emulation which is based on the IEEE 1149 1 standard For more information concerning the IEEE 1149 1 standard contact IEEE Customer Service Address IEEE Customer Service 445 Hoes Lane PO Box 1331 Piscataway NJ 08855 1331 Phone 800 678 IEEE in the US and Canada 908 981 1393 outside the US and Canada FAX 908 981 9667 Telex 833233 Topic Page A 1 Designing Your Target System s Emulator Connector A PinHsadere a eens aie E oe ee eerie la 2 rs SUE eel eter E ASS Emulator Cable Pod s sess enesenn an A 5 A 4 Emulator Cable Pod Signal Timing 000eeeeeeeeeeee A 5 Emulation Timing Calculations
178. Noncompiler Mode CPL 0 a Latencies based on secona instruction category First Instruction STM ST MVDK MVMD MVKD MVDM MVPD POPM POPD MVDD lk status lk status Smem status MMR status dmad status dmad status pmad status status status status Store type instruction see Table 7 5 SSBX RSBX STO statbit STO statbit b Categories for the second instruction Category All instructions that use DP for direct addressing mode except those listed in Category Il Legend Note 7 64 Second Instruction Category Category Il 2 2 2 2 3 2 3 3 3 2 3 2 3 2 Category Il MVKD dmad dirmem MVPD pmad dirmem MACP dirmem pmad src MACD dirmem pmad src ADD dirmem shift src dst LD dirmem shift dst 3 E W h STH src shift dirmem be i en STL src shift dirmem SUB dirmem shift src dst status Destination operand pointing to STO to update DP in either direct or indirect addressing modes MMR Any memory mapped register statbit Destination operand writing to a bit in DP field of STO dirmem A read or write operand using direct addressing mode when CPL 0 T Shift value between 16 and 15 Any instruction that does not fit in either of the two categories has zero latency Pipeline SPRU131G Pipeline Latencies Example 7 44 DP Load With No Latency in Noncompiler Mode CPL 0 a LD 2h DP This DP load does not require a
179. P AR1 A This instruction creates a DAGEN conflict This instruction has a 2 cycle lat WO ncy due to the DAGEN conflict NOPs avoid this conflict b ARx updated with no latency after reordering instructions POPM STLM LD A AR1 SP AR1 A the POPM to avoid DAGEN conflicts and to eliminate the need for NOPs This instruction has a l1 cycle latency This instruction is placed after Example 7 29 ARx Updated With a 2 Cycle Latency ADDA B STLM A ARI NOP NOP MVMM ARI AR2 Thi latency This instruction does not create a DAGI EN conflict s instruction has a 2 cycle SPRU131G Pipeline 7 49 Pipeline Latencies Example 7 30 BK Updated With a 1 Cycle Latency This instruction does not create a DAGEN conflict ADD A B STM 100h BK NOP This instruction needs a 1 cycle ADD AR1 B This instruction uses BK for i leavtency i i circular addressing 7 5 5 Latencies for the Stack Pointer Stack pointer SP latencies discussed in this section occur when SP is used in one of two ways OJ As an offset in direct addressing when CPL 1 41 In a push pop call return FRAME or MVMM operation 7 5 5 1 SP Used in Compiler Mode CPL 1 A pipeline conflict occurs if two conditions are simultaneously met 1 One instruction writes to SP 1 The next instruction uses SP
180. P 64x DSP 67x DSP SPRU131G Part Order Information B 2 3 Development Support Tools Table B 1 lists the development support tools available for the C54x DSP the platform on which they run and their part numbers Table B 1 Development Support Tools Part Numbers Development Tool Platform Part Number Assembler Linker PC DOS TMDS324L850 02 C Compiler Assembler Linker PC DOS Windows OS 2 TMDS324L855 02 C Compiler Assembler Linker HP HP UX SPARC Sun OS TMDS324L555 08 C Source Debugger Conversion Software PC DOS Windows OS 2 TMDS32401L0 XDS510 C Source Debugger Conversion Software HP HP UX SPARC Sun OS TMDS32406L0 XDS510WS Evaluation Module EVM PC DOS Windows OS 2 TMDX3260051 Simulator C language PC DOS Windows TMDS324L851 02 Simulator C language HP HP UX SPARC Sun OS TMDS324L551 09 XDS510 Emulatort PC DOS Windows OS 2 TMDS00510 XDS510WS Emulatort a SPARC Sun OS TMDS00510WS SCSI 3 V 5 V PC SPARC JTAG Emulation Cable XDS510 XDS510WS TMDS3080002 T Includes XDS510 board and JTAG cable TMDS32401L0 C source debugger conversion software not included Includes XDS510WS box SCSI cable power supply and JTAG cable TMDS32406L0 C source debugger conversion software not included SPRU131G Development Support and Part Order Information B 7 Appendix C Submitting ROM Codes to TI The size
181. PC and TDM serial port control register TSPC that puts the serial port in digital loopback mode digital to analog D A converter Circuitry that translates a digital signal to an analog signal direct data memory address bus A 16 bit bus that carries the direct address for data memory direct memory address dma DMA The seven LSBs of a direct addressed instruction that are concatenated with the data page pointer DP to generate the entire data memory address See also data page pointer Glossary D 7 Glossary D 8 Glossary dma See direct memory address DP See data page pointer DRB direct data memory address bus A 16 bit bus that carries the direct address for data memory DROM See data ROM DRR DRRO DRR1 serial port data receive register Two 16 bit registers used to receive data through the synchronous serial ports DRRO corresponds to synchronous serial port 0 DRR1 corresponds to synchronous serial port 1 DSP interrupt DSPINT A bit in the HPI control register HPIC that enables disables an interrupt from a host device to the C54x DSP DXR DXRO DXR1 serial port data transmit register Two 16 bit registers used to transmit data through the synchronous serial ports DXRO corre sponds to synchronous serial port 0 DXR1 corresponds to synchronous serial port 1 EAB E address bus A bus that carries addresses needed for accessing data memory EAB address register EAR A register that ho
182. PU The C54x DSP barrel shifter has a 40 bit input connected to the accumulators or to data memory using CB or DB and a 40 bit output connected to the ALU or to data memory using EB The barrel shifter can produce a left shift of 0 to 31 bits and a right shift of 0 to 16 bits on the input data The shift require ments are defined in the shift count field of the instruction the shift count field ASM of status register ST1 or in temporary register T when it is designated as a shift count register The barrel shifter and the exponent encoder normalize the values in an accu mulator in a single cycle The LSBs of the output are filled with Os and the MSBs can be either zero filled or sign extended depending on the state of the sign extension mode bit SXM in ST1 Additional shift capabilities enable the processor to perform numerical scaling bit extraction extended arithmetic and overflow prevention operations See section 4 4 Barrel Shifter on page 4 17 for more details about the function and use of the shifter See section 4 7 Exponent Encoder on page 4 27 for more information about the encoder s accumulator normalizing function 2 3 4 Multiplier Adder Unit SPRU131G The multiplier adder unit performs 17 x 17 bit 2s complement multiplication with a 40 bit addition in a single instruction cycle The multiplier adder block consists of several elements a multiplier an adder signed unsigned input control logic fractional
183. PU clock u is the sum of the TDDR contents plus 1 and v is the sum of the PRD contents plus 1 The current value in the timer can be read by reading TIM PSC can be read by reading TCR Because it takes two instructions to read both registers there may be a change between the two reads as the counter decrements There fore when precise timing measurements are needed it is more accurate to stop the timer before reading these two values The timer can be stopped by setting the TSS bit and restarted by clearing it The timer can be used to generate a sample clock for peripheral circuits such as an analog interface This can be accomplished by using the TOUT signal to clock a device or by using the interrupt to periodically read a register Note that on the C5402 the timer1 output TOUT1 is only available when the HPI 8 is disabled and the TOUT1 bit is set in the GPIO control register The timer is initialized with the following steps 1 Stop the timer by writing a 1 to TSS in TCR 2 Load PRD 3 Start the timer by reloading TCR to initialize TDDR Enable the timer by setting TSS to 0 and TRB to 1 to reload the timer period 8 24 On Chip Peripherals SPRU131G Timer Optionally the timer interrupt may be enabled by assuming INTM 1 1 Clearing any pending timer interrupts by writing a 1 to TINT in the IFR 2 Enabling the timer interrupt by writing a 1 to TINT in the IMR 3 Enabling interrupts globally if necessary by c
184. PU interrupt vectors can be remapped into the HPI memory the host can instruct the C54x DSP to execute preprogrammed functions by simply writing the start address of a function to address xx65h in the HPI memory prior to interrupting the C54x CPU with a branch instruction located at address xx64h If the interrupts are remapped to the host port accessible on chip RAM you must use SAM and the host must not write to location xx00h to xx7Fh except for xx65h On Chip Peripherals SPRU131G Host Port Interface Host Port Interface C54x Using HINT to Interrupt the Host Device When the C54x DSP writes a 1 to the HINT bit in HPIC the HINT output is driv en low the HINT bitis read as a 1 by the C54x DSP or the host The HINT signal can be used to interrupt the host device The host device after detecting the HINT interrupt line can acknowledge and clear the C54x CPU interrupt and the HINT bit by writing a 1 to the HINT bit The HINT bit is cleared and then read as a 0 by the C54x DSP or the host and the HINT pin is driven high If the C54x DSP or the host writes a 0 the HINT bit remains unchanged While accessing the SMOD bit the C54x DSP should not write a 1 to the HINT bit unless it also wants to interrupt the host 8 6 5 Considerations in Changing HPI Memory Access Mode SAM HOM and IDLE2 3 Use SPRU131G The HPI host only mode HOM allows the host to access HPI RAM while the C54x CPU is in IDLE2 3 that is completely halte
185. Pin Emulator Connector A 7 Physical Dimensions for the 14 Pin Emulator Connector The JTAG emulator target cable consists of a 3 foot section of jacketed cable that connects to the emulator an active cable pod and a short section of jack eted cable that connects to the target system The overall cable length is approximately 3 feet 10 inches Figure A 8 and Figure A 9 page A 15 show the physical dimensions for the target cable pod and short cable The cable pod box is nonconductive plastic with four recessed metal screws Figure A 8 Pod Connector Dimensions 2 70 in nominal 4 50 in nominal L 9 50 in nominal amp 0 90in nominal Emulator cable pod A Connector EES Short jacketed cable lt Y See Figure A 9 Note All dimensions are in inches and are nominal dimensions unless otherwise specified Pin to pin spacing on the connec tor is 0 100 inches in both the X and Y planes A 14 Design Considerations for Using XDS510 Emulator SPRU131G Physical Dimensions for the 14 Pin Emulator Connector Figure A 9 14 Pin Connector Dimensions ia 0 20 i nch nominal Cable 0 66 inch nominal 2 y Connector side view 0 100 inch nominal pin spacing Key pin 6 A 0 87 inch Cable t nominal 0 100 inch nominal pin spacing y Connector front view 2 rows of pins SPRU131G Design Considerations for Using XDS510 Emulator A 15 Emulation Design Co
186. Pipeline Operation and section 7 2 Interrupts and the Pipeline are helpful in understanding the operation of PC discontinuities Power down modes halt program execution Topic Page 6 1 Program Memory Address Generation 00eeeeeeee 6 2 Program Counter PG yer yprrerresteieletereeeeie aE E RE 6 3 Leben nasndoapascnasoneunnesoneonenposedaennemcesomnapacone 6AE Calls seo see eet hee es eee en ene rere G4 IVINS m 6 6 Conditional Operations 15 2 6 tae ce se eee ees 6 7 Repeating a Single Instruction 00ce eee ee eee eee 6 8 Repeating a Block of Instructions 0 02ee eee eee eee 6 9 Reset Operation ess eriess sciences sone eteineieie re arene eters EEAS sus US m Gril POWE DON M Ode ate rsiersreterelevaierstel 6 1 Program Memory Address Generation 6 1 Program Memory Address Generation Program memory contains code for applications coefficient tables and immediate operands The TMS320C54x DSP can address a total of 64K words of program memory using the program address bus PAB Table 6 1 shows devices that have additional program memory address lines that provide external access to as many as 128 64K word pages Table 6 1 Devices With Additional Program Memory Address Lines Additional Provides Device Address Lines External Access To C548 C549 C5410 7 128 64K Word Pages C5402 4 16 64K Word Pages C5420 2 4 64K Word Pages The program address generation logic PAGE
187. R R Schafer T Barnwell and D Smith A Digital Filter Design Package for PCs and TMS320 MIDCON 84 Electronic Show and Conven tion USA 1984 2 Simar Jr R and A Davis The Application of High Level Languages to Single Chip Digital Signal Processors Proceedings of ICASSP 88 USA Volume 3 pages 1678 1681 April 1988 Trademarks TMS320 TMS320C2x TMS320C20x TMS320C24x TMS320C5x TMS320C54x C54x 320 Hotline On line Micro Star Tl XDS510 and XDS510WS are trademarks of Texas Instruments HP UX is a trademark of Hewlett Packard Company MS DOS and Windows are trademarks of Microsoft Corporation OS 2 and PC DOS are trademarks of International Business Machines Corporation PAL is a registered trademark of Advanced Micro Devices Inc Solaris and SunOS are trademarks of Sun Microsystems Inc SPARC is a trademark of SPARC International Inc but licensed exclusively to Sun Microsystems Inc xiv Read This First SPRU131G Contents 1 Introduction kasise eene a are sew E w te pees alsa a achive Serene caves wae ea Summarizes the features of the TMS320 family of products and presents typical applications Describes the TMS320C54x DSP and lists its key features 1 1 TMS320 DSP Family Overview 0 0 00 cece nett 1 1 1 History Development and Advantages of TMS320 DSPs 1 1 2 Typical Applications for the TMS320 DSP Family 20 1 2 TMS320C54x DSP O
188. R i3 Prefetch Fetch Decode Access Prefetch Fetch Decode ji Pano PB j1 IR j1 Execute E 10 In this case the pipeline behaves in the same manner as with the normal call instruction However in this case the following two instructions i3 and i4 are allowed to complete their execution Therefore only cycles 6 and 7 are consumed by the delayed call instruction making it a 2 cycle instruction 7 10 Pipeline SPRU131G Pipeline Operation The INTR instruction behaves like a CALL instruction However because INTR is a 1 word instruction it can compute the vector table address and prefetch it one cycle earlier As shown in Example 7 6 INTR takes only three cycles to execute Example 7 6 Interrupt INTR Instruction in the Pipeline Address Instruction al a2 INTRn a3 i2 a4 i3 vect jl 1 2 3 4 5 6 7 8 9 Prefetch Fetch Decode Access Read Execute IR INTR INTR PAB a1 PB INTR RTN a2 EAB SP EB RTN Prefetch Fetch Decode Access Read Execute Pipeline flush PAB a2 Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute SPRU131G Pipeline 7 11 Pipeline Operation 7 1 3 Return Instructions in the Pipeline Because a return is a single word instruction you would expect it to take at least one cycle to completely execute In reality a standard return instruction takes five cycles to execute Example 7 7 shows the pipeline s behavior dur
189. R TDM serial port data transmit register 32 TSPC TDM serial port control register 33 TCSR TDM serial port channel select register 34 TRTA TDM serial port receive transmit register 35 TRAD TDM serial port receive address register 36 37 gt Reserved 38 AXRO ABU 0 transmit address register 39 BKXO ABU 0 transmit buffer size register 3A ARRO ABU 0 receive address register 3B BKRO ABU 0 receive buffer size register 3C AXR1 ABU 1 transmit address register 3D BKX1 ABU 1 transmit buffer size register 3E ARR1 ABU 1 receive address register AF BKR1 ABU 1 receive buffer size register 40 BDRR1 Buffered serial port 1 data receive register 41 BDXR1 Buffered serial port 1 data transmit register 42 BSPC1 Buffered serial port 1 control register 43 BSPCE1 Buffered serial port 1 control extension register 44 57 SSS Reserved 58 CLKMD Clock mode register 59 5F Reserved 8 10 On Chip Peripherals SPRU131G Peripheral Memory Mapped Registers Table 8 8 C5402 Peripheral Memory Mapped Registers Address Hex 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2F 30 31 32 33 37 38 39 3A 3B 3C 3D SPRU131G Name DRR20 DRR10 DXR20 DXR10 TIM PRD TCR SWWSR BSCR SWCR HPIC TIM1 PRD1 TCR1 SPSAO SPSDO GPIOCR GPIOSR Description McBSPO0 data receive register 2 McBSPO data receive register 1 McBSPO data transmit register 2 McBSPO data transmit register 1 Timer0 register TimerO period coun
190. R copy No transmit interrupt Start transmit DXR to XSR copy Transmit interrupt Start transmit 1 word is lost Continuous Mode In continuous mode errors take on a broader meaning since data transfer is intended to occur at all times Thus underflow XSREMPTY 0 constitutes an error in continuous mode because data will not be transmitted As in burst mode overrun RSRFULL 1 is also an error and in continuous mode both overrun and underflow cause the serial port receive or transmit sections respectively to halt see section 9 2 3 Configuring the Serial Port Interface on page 9 8 for a description of these conditions Fortunately underflow and overrun errors may not be catastrophic they can often be corrected simply by reading DRR or writing to DXR The SP and the BSP are affected differently when overrun occurs in continu ous mode In the SP when DRR is read to deactivate RSRFULL a frame sync pulse is not required in order to resume continuous mode operation The receiver keeps track of the transfer word boundary even though it is not receiving data Therefore when the RSRFULL flag is deactivated by a read from DRR the receiver begins reading from the correct bit On the BSP since an FSR pulse is required to restart continuous reception this also reestablishes the proper bit alignment in addition to restarting reception Figure 9 19 shows receiver functional operation in continuous mode SPRU131G Serial Ports 9
191. RC is decremented during the instruction decode phase of the last repeat block instruction For this reason be careful when using the SRCCD instruc tion within a loop To save the current loop counter value the predecremented BRC the SRCCD instruction must be placed a minimum of three instructions before the end of the loop There is only one set of block repeat registers so multiple block repeats cannot be nested without saving the context of the outside loops The simplest way of establishing nested loops is to use the RPTB D instruction for the innermost loop only and use the BANZ D for all outer loops Program Memory Addressing SPRU131G Reset Operation 6 9 Reset Operation Reset RS is a nonmaskable external interrupt that can be used at any time to place the C54x DSP into a known state For correct system operation after power up RS must be asserted low for several clock cycles to ensure that the data address and control lines are configured properly Approximately five clock cycles after RS is de asserted goes high the processor fetches the instruction at FF80h and begins executing code See section 10 5 Start Up Access Sequences on page10 24 for the reset sequence The following actions occur during a reset operation IPTR is set to 1FFh RS is de asserted The MP NC bit in PMST is set to the value of the MP MC pin PC is set to FF80h XPC is cleared if applicable FF80h is driven on the address bus r
192. Reset and initialize the serial port by writing 0000h to BSPC Clear any pending serial port in terrupts by writing 0010h to IFR Enable the serial port interrupts by ORing 0010h with IMR Enable interrupts globally if nec essary by clearing the INTM bit in ST1 Initialize the ABU receive by writ ing 2160h to BSPCE Write the buffer start address to ARR Write the buffer size to BKR Start the serial port by writing Description This places the receive portion of the serial port in reset and sets up the serial port to operate in continuous receive mode with 16 bit words Eliminate any interrupts that may have occurred before initialization Enable receive interrupts Interrupts must be globally enabled for the CPU to respond This causes the BSP to receive continuously and not restart if a new FSR is received Identify the first buffer address to the ABU Identify the buffer size to the ABU This takes the receive portion of the serial port out of reset and starts 0080h to BSPC operations with the conditions defined in steps 1 and 5 9 3 4 Buffer Misalignment Interrupt BMINT C549 only 9 54 Serial Ports BMINT is generated when a frame sync occurs and the ABU transmit or receive buffer pointer is not at the top of the the buffer address This is useful for detecting several potential error conditions on the serial interface including extraneous and missed clocks and frame sync pulses A
193. Resolved Conflict Among Operand Write Operand Write and Dual Operand Read If the second instruction in the case described above is an operand write type instruction then the write access requested by the first instruction cannot be moved to the next cycle The CPU resolves the conflict by inserting a dummy cycle after the first instruction This is illustrated in Example 7 21 in which AR3 and AR5 point to the same dual access memory block SPRU131G Pipeline 7 31 Dual Access Memory and the Pipeline Example 7 21 Operand Write and Operand Read Conflict STLA AR3 STH A AR2 ADD AR4 AR5 A AR3 and ARS both point to the same dual access memory block Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute oe ff ff Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute Legend Where read or write occurs 7 32 Pipeline SPRU131G Single Access Memory and the Pipeline 7 4 Single Access Memory and the Pipeline SPRU131G The C54x DSP also features on chip single access memory that supports one access per cycle to each memory block There are two different types of single access memory that are available on C54x devices J Single access read write memory SARAM J Single access read only memory ROM or DROM Both types of single access memory behave similarly in terms of pipelined accesses with the exception that ROM and DROM cannot be wr
194. Rx this sum is then used to address the data memory operand addr Ik An unsigned 16 bit long offset Ik is used as the absolute address of data memory absolute addressing 81 Tt ARx is used as the data memory address unless otherwise specified Increment decrement value is 1 for 16 bit word access and 2 for 32 bit word access This mode is not allowed in memory mapped register addressing This mode is discussed in greater detail in section 5 2 4 k Addressing on page 5 5 This mode is allowed only for write accesses 5 5 3 1 Increment Decrement Address Modifications MOD 0 1 2 or 3 While an AR is being used you can modify the AR by incrementing or decre menting its value The syntaxes for using the AR without modification postdecrementing the AR by 1 postincrementing the AR by 1 and preincrementing the AR by 1 are shown in Table 5 4 for MOD 0 1 2 and 3 respectively Preincrementing ARx is supported only in instructions that access oper ands in a write operation 5 5 3 2 Offset Address Modifications MOD 12 or 13 5 14 Offset addressing is a type of indirect addressing in which a predetermined off set or step size is added to the contents of an auxiliary register There are two options for offset addressing In both cases a 16 bit long offset which is part of the instruction is added to the value in the auxiliary register and the result is used to address a location in data memo
195. S SINTR NMI SINT16 SINT17 SINT18 SINT19 6 46 Program Memory Addressing Location Hex 0 4 8 C 10 Function Reset hardware and software reset Nonmaskable interrupt Software interrupt 17 Software interrupt 18 Software interrupt 19 SPRU131G Interrupts Table 6 27 TMS320C5410 Interrupt Locations and Priorities Continued TRAP INTR Number K 5 6 7 21 22 23 24 25 26 27 SPRU131G Priority Name 10 12 13 14 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INTO SINTO INT1 SINT1 INT2 SINT2 TINT SINT3 BRINTO SINT4 BXINTO SINT5 BRINT2 DMACO BXINT2 DMAC1 INT3 SINT8 HPINT SINT9 BRINT1 DMAC2 SINT10 BXINT1 DMAC3 SINT11 Location Hex 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 68 6C Function Software interrupt 20 Software interrupt 21 Software interrupt 22 Software interrupt 23 Software interrupt 24 Software interrupt 25 Software interrupt 26 Software interrupt 27 Software interrupt 28 Software interrupt 29 Software interrupt 30 External user interrupt 0 External user interrupt 1 External user interrupt 2 TimerO interrupt McBSP 0 receive interrupt default McBSP 0 transmit interrupt default McBSP 2 receive interrupt default or DMA channel 0 interrupt MCBSP 2 transmit interrupt default or DMA channel 1 interrupt
196. SPCE contains the control and status bits that are used in the imple mentation of these enhanced BSP features and the ABU The 10 LSBs of BSPCE are dedicated to the enhanced features control whereas the 6 MSBs are used for ABU control which is discussed in section 9 3 2 Autobuffering Unit ABU Operation on page 9 40 Figure 9 22 shows the BSPCE bit posi tions and Table 9 9 summarizes the function of the BSPCE bits The value of the BSPCE upon reset is 3 This results in standard mode operation compat ible with the serial port Figure 9 22 BSP Control Extension Register BSPCE Diagram Serial Port Control Bits 15 10 T 5 4 0 9 8 6 ABU control rom Fic FE oke FSP ck RW RW RW RW R W R W Note R Read W Write SPRU131G Serial Ports 9 37 Buffered Serial Port BSP Interface Table 9 9 BSP Control Extension Register BSPCE Bit Summary Serial Port Control Bits Bit 15 10 9 38 Reset Name value ABU control PCM 0 FIG 0 FE 0 CLKP 0 FSP 0 Serial Ports Function Reserved for autobuffering unit control see section 9 3 2 Autobuffering Unit ABU Operation on page 9 40 Pulse Code Modulation Mode This control bit puts the serial port in pulse code modulation PCM mode The PCM mode only affects the transmitter BDXR to BXSR transfer is not affected by the PCM bit value PCM 0 Pulse code modulation mode is disabled PCM 1 Pulse code modulation mode is enabled
197. SPRU131G Chapter 4 Central Processing Unit This chapter describes the TMS320C54x DSP central processing unit CPU operations The CPU can perform high speed arithmetic operations within one instruction cycle because of its parallel architectural design The following CPU functional components are discussed in this chapter 40 bit arithmetic logic unit ALU Two 40 bit accumulator registers Barrel shifter supporting a 16 to 31 shift range Multiply accumulate block 16 bit temporary register T 16 bit transition register TRN Compare select and store unit CSSU Exponent encoder O O O C C C O L The CPU registers are memory mapped enabling quick saves and restores Topic Page 4 1 CPU Status and Control Registers ssseeeeeeeeeeeees 4 2 4 2 Arithmetic Logic Unit ALU ssasnssssssnnsnssnsnnnnnnn 4 10 4 3 Accumulators Avand BE 4 ASeBatreliohittenaemcmrtecri a rier erie eer E yet 4 17 45 Multiplier Adder Unit ma cea e 2 erect a ate ee eee a a 4 6 Compare Select and Store Unit CSSU uasssassnussnnnn AT Exponent Encoder ss ciicc cs nts nee cle lerenie vielsinlayeisle el iaysiave ele ER ESEA 4 27 4 1 CPU Status and Control Registers 4 1 CPU Status and Control Registers The C54x DSP has three status and control registers Lj Status register 0 STO Lj Status register 1 ST1 1 Processor mode status register PMST STO and ST1 contain the status of various
198. Software interrupt 28 Software interrupt 29 reserved Software interrupt 30 reserved External user interrupt 0 External user interrupt 1 External user interrupt 2 Internal timer interrupt Buffered serial port 0 receive interrupt Buffered serial port 0 transmit interrupt TDM serial port receive interrupt TDM serial port transmit interrupt External user interrupt 3 HPI interrupt Buffered serial port 1 receive interrupt Buffered serial port 1 transmit interrupt Reserved Program Memory Addressing 6 43 Interrupts Table 6 25 TMS320C549 Interrupt Locations and Priorities 6 44 TRAP INTR Number K Priority 0 1 o a N O oa A WO ND hy Boe Bes Bea Bae PS Pa Fan O co N FoG O cS o pug pS 22 23 24 25 1 2 o N e gt ol A wo l ok oOo 12 Name RS SINTR NMI SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INTO SINTO INT1 SINT1 INT2 SINT2 TINT SINT3 BRINTO SINT4 BXINTO SINT5 TRINT SINT6 TXINT SINT7 INT3 SINT8 HINT SINT9 Program Memory Addressing Location Hex 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 Function Reset hardware and software reset Nonmaskable interrupt Software interrupt 17 Software interrupt 18 Software interrupt 19 Software interrupt 20 Software interrupt 21 Software interrupt 22 Software
199. TB D MVDK Smem BRC 0 MVMD MMR BRC STM k BRC 0 ST k BRC All other instructions that modify BRC 1 7 72 Pipeline SPRU131G Pipeline Latencies Example 7 54 Loading BRC Before Executing a New Repeat Block Loop a STM 1k BRC There is no latency when BRC is RPTB endloop 1 loaded via STM before a new RPTB in loop endloop b MVDK count BRC There is no latency when BRC is RPTBD endloop 1 loaded using MVDK before a new ee RPTB loop endloop c STLM A BRC There is a 1 cycle latency when NOP BRC is loaded using an STIM RPTB endloop 1 instruction endloop a POPM BRC There is a 1 cycle latency when NOP BRC is loaded using a POPM RPTBD endloop 1 7 instruction endloop In a repeat block loop BRC is decremented when the last instruction in the loop is in the decode stage of the pipeline However the SRCCD instruction writes the BRC s contents in the execute stage of the pipeline This can result in an incorrect BRC value written by the SRCCD instruction The pipeline con flict can be avoided by placing the SRCCD instruction at least three instruction words from the bottom of the loop as shown in Example 7 55 and Example 7 56 Example 7 55 SRCCD Instruction With No Latency RPTB endloop 1 SRCCD AR3 ALEQ Placing the SRCCD instruction in this position ensures that current value of BRC will be written to memory Nee
200. TBP28S166 TBP28S86 O O O O L When code is submitted to TI for masking the code is reformatted to accom modate the TI mask generation system System level verification by the customer is therefore necessary to ensure the reformatting remains transpar ent and does not affect the execution of the algorithm The formatting changes involve the removal of address relocation information the code address begins at the base address of the ROM in the TMS320 DSP and progresses without gaps to the last address of the ROM and the addition of data in the reserved locations of the ROM for device ROM test Because these changes have been made a checksum comparison is not a valid means of verification With each masked device order the customer must sign a disclaimer that states The units to be shipped against this order were assembled for expe diency purposes on a prototype that is nonproduction qualified manufacturing line the reliability of which is not fully characterized Therefore the anticipated inherent reliability of these prototype units cannot be expressly defined and a release that states Any masked ROM device may be resymbolized as TI standard product and resold as though it were an unprogrammed version of the device at the convenience of Texas Instruments The use of the ROM protect feature does not hold for this release statement Additional risk and charges are involved when the ROM protect feature is selected Conta
201. TC rotate accumulator left with TC L E E E E In SFTA and SFTL the shift count is defined as 16 lt SHIFT lt 15 SFTA is affected by the SXM bit When SXM 1 and SHIFT is a negative value SFTA performs an arithmetic right shift and maintains the sign of the accumulator When SXM 0 the MSBs of the accumulator are zero filled SFTL is not affected by the SXM bit it performs the shift operation for bits 31 0 shifting Os into the MSBs or LSBs depending on the direction of the shift SFTC performs a 1 bit left shift when both bits 31 and 30 are 1 or both are 0 This normalizes 32 bits of the accumulator by eliminating the most significant nonsign bit ROL rotates each bit of the accumulator to the left by one bit shifts the value of the carry bit into the LSB of the accumulator shifts the value of the MSB of the accumulator into the carry bit and clears the accumulator s guard bits ROR rotates each bit of the accumulator to the right by one bit shifts the value of the carry bit into the MSB of the accumulator shifts the value of the LSB of the accumulator into the carry bit and clears the accumulator s guard bits The ROLTC instruction rotate accumulator left with TC rotates the accumula tor to the left and shifts the test control TC bit into the LSB of the accumulator 4 14 Central Processing Unit SPRU131G Accumulators A and B 4 3 3 Saturation Upon Accumulator Store The SST bit in PMST determines
202. The DRR has not been read since the last RSR to DRR transfer g RSR is full J anda frame sync pulse appears on FSR In continuous mode FSM 0 and on the BSP only the first two conditions are necessary to set RSRFULL J The DRR has not been read since the last RSR to DRR transfer Lj and RSR is full Therefore in continuous mode and on the BSP RSRFULL occurs after the last bit has been received When RSRFULL 1 the receiver halts and waits for the DRR to be read and any data sent on DR is lost On the SP the data in RSR is preserved on the BSP the RSR contents are lost Any one of the following three conditions causes RSRFULL to become inactive RSRFULL 0 _ The DRR is read J or the serial port is reset RRST 0 1 or the C54x device is reset RS 0 SOFT and FREE Bits Soft bit 14 and Free bit 15 are special emulation bits that determine the state of the serial port clock when a breakpoint is encountered in the high level language HLL debugger If the Free bit is set to 1 then upon a software breakpoint the clock continues to run free runs and data is still shifted out When Free 1 the Soft bit is a don t care If the Free bit is cleared to 0 then the Soft bit takes effect If the Soft bit is cleared to 0 then the clock stops immediately thus aborting any transmission If the Soft bit is set to 1 anda transmission is in progress the transmission continues until completion of the tr
203. This mode is especially useful for the Viterbi add compare select operation see section 4 6 Compare Select and Store Unit CSSU on page 4 24 4 12 Central Processing Unit SPRU131G Accumulators A and B 4 3 Accumulators A and B Accumulator A and accumulator B can be configured as the destination regis ters for either the multiplier adder unit or the ALU In addition they are used for MIN and MAX instructions or for the parallel instruction LD MAC in which one accumulator loads data and the other performs computations Each accumulator is split into three parts as shown in Figure 4 5 and Figure 4 6 Figure 4 5 Accumulator A Figure 4 6 Accumulator B 39 32 31 16 15 0 Guard bits High order bits Low order bits 39 32 31 16 15 0 Guard bits High order bits Low order bits The guard bits are used as a headmargin for computations Headmargins allow you to prevent some overflow in iterative computations such as autocorrelation AG BG AH BH AL and BL are memory mapped registers that can be pushed onto and popped from the stack for context saves and restores by using PSHM and POPM instructions These registers can also be used by other instructions that use memory mapped registers MMR for page 0 addressing The only difference between accumulators A and B is that bits 32 16 of A can be used as an input to the multiplier in the multiplier adder unit 4 3 1 Storing Accumulator Contents SPRU131G You can store a
204. Time Division Multiplexing e gt Full Interval frame k Word Transfer Interval chan 3 chan 2 chan 1 chan 4 chan 3 chan 2 chan 1 chan 4 chan 3 chan 2 chan 1 0 gt time The C54x TDM port uses eight TDM channels Which device is to transmit and which device or devices is are to receive for each channel may be indepen dently specified This results in a high degree of flexibility in interprocessor communications 9 4 2 TDM Serial Port Interface Registers The TDM serial port operates through six memory mapped registers and two other register TRSR and TXSR that are not directly accessible to the program but are used in the implementation of the double buffering capability These eight registers are listed in Table 9 13 SPRU131G Time Division Multiplexed TDM Serial Port Interface Table 9 13 TDM Serial Port Registers SPRU131G Address Register Description Ti TRCV TDM data receive register T TDXR TDM data transmit register ili TSPC TDM serial port control register T TCSR TDM channel select register Jj TRTA TDM receive transmit address register t TRAD TDM receive address register TRSR TDM data receive shift register TXSR TDM data transmit shift register t See section 8 2 Peripheral Memory Mapped Registers d TDM data receive register TRCV The 16 bit TDM data receive register TRCV holds the incoming TDM serial da
205. XC instruction pipeline latencies pipeline levels functions 7 2 access decode execute write program fetch program pre fetch read pipeline operation 2 11 pipeline stages figure 7 3 pipelined memory accesses instruction performing dual operand read instruction performing dual operand write instruction performing operand read and write instruction performing single operand read instruction performing single operand write 7 4 instruction word fetch pipeline protected instruction CPL 0 update ARP update DP 7 6 update T register _ 7 57 write to ASM 7 69 PLL changing the multiplier ratio 8 33 considerations when using IDLE instruction hardware configurable operation following reset operation in IDLE modes programmable lock timer programming considerations software programmable switching clock modes DIV to PLL 8 32 PLL to DIV 8 33 PLL lockup time versus CLKOUT frequency pmad definition pmad addressing PMST See also processor mode status register PMST definition latencies 7 75 polarity bit clock frame sync w Index 13 Index pop definition D 13 program data bus PB definition D 14 power down mode 6 50 to program memory _ 3 15 to 3 21 disabling external interface internal clock address map 3 18 hold mode configurabilit IDLE 1 instruction definition IDLE 2 instruction mapping the C542 IDLE 3 instruction on chip ROM code initiated using HOLD signal 6 52 pr
206. Xar or Yar Field 00 01 10 11 Auxiliary Register AR2 AR3 AR4 AR5 Figure 5 12 shows how an address is generated using dual data memory operand addressing Dual data memory operand addressing uses four auxiliary registers AR2 AR5 The ARAUs together with these registers provide the capability to access two operands in a single cycle 5 20 Data Addressing SPRU131G Indirect Addressing Table 5 8 lists the types of dual data memory operand addressing along with the value of the modification field either Xmod or Ymod the assembler syntax and the function for each type Figure 5 12 Indirect Addressing Block Diagram for Dual Data Memory Operands ARO BK Ik 1 ARP 3 0 DAB 16 ARO BK 1 read EAB 16 write or CAB 16 32 bit read Data bus DB 16 Data bus EB 16 Table 5 8 Indirect Addressing Types With Dual Data Memory Operands Xmod or Operand Ymod Field Syntax Function Descriptiont 00 0 ARx addr ARx ARx is the data memory address 01 1 ARx addr ARx After access the address in ARx is decremented ARx ARx 1 10 2 ARX addr ARx After access the address in ARx is incremented ARx ARx 1 11 3 ARx 0 addr ARx After access ARO is added to ARx using circular ARx circ ARx ARO addressing T ARx is used as the data memory address unless otherwise specified t The size of the c
207. _ 7 53 zero latency 7 52 SPC definition SP referenced direct addressing figure SRCCD instruction three cycle latency SST definition STO 8 26 See also status register 0 STO definition ST1 See also status register 1 ST1 definition stack definition stack addressing id p 5 27 pop instructions push instructions Eo stack pointer SP definition latencies stack stack pointer before and after push operation figure 5 27 start up access sequences status and control registers 4 2 to 4 9 status register 0 STO ARP field 4 24 bit summary C bit definition diagram status re 1 qa 4 2 definition diagram INTM bit OVM bit Index 17 Index SXM bit _ 4 5 D 16 XF bit 4 4 status register STO ST1 store conditional straight unshrouded 14 pin support tools development device B 7 support tools nomenclature prefixes B 5 SWCR software wait state control register SWWSR bit summary SXM definition D 16 latencies SXM update no latency 7 67 one cycle Ld bs 7 67 7 68 synchronous serial port interfaces three types 9 2 system stack system integration tools B 2 T definition T load one cycle latency 7 59 zero latency TADD definition target cable A 14 target system connection to emulator A 1 to A 25 target system clock A 12 TC oe D 17 TCK signal_ A 2 A 3 A 4 A 6 A 7 A 13 A 17 ial A 25 TCR definition
208. a rapid start in developing C54x DSP design skills Microprocessor assembly language experience is required Experience with digital design techniques and C language programming experience is desirable These topics are covered in the C54x DSP workshop J C54x DSP architecture instruction set Lj Use of the PC based software simulator g Use of the C54x DSP assembler linker i C programming environment 41 System architecture considerations O Memory and I O interfacing 1 Development support For registration information pricing or to enroll call 800 336 5236 ext 3904 For assistance to TMS320 DSP questions on device problems development tools documentation software upgrades and new products you can contact TI B 4 Development Support and Part Order Information SPRU131G Part Order Information B 2 Part Order Information This section describes the part numbers of C54x devices development support hardware and software tools B 2 1 Device and Development Support Tool Nomenclature Prefixes SPRU131G To designate the stages in the product development cycle TI assigns prefixes to the part numbers of all TMS320 DSP and support tools Each TMS320 device has one of three prefix designators TMX TMP or TMS Each support tool has one of two possible prefix designators TMDX or TMDS These prefixes represent evolutionary stages of product development from engineer ing prototypes TMX TMDX through fully qualif
209. ability in one pipeline phase cycle The multiplier adder unit is shown in Figure 4 8 on page 4 20 The multiplier can perform signed unsigned and signed unsigned multiplica tion with the following constraints _j For signed multiplication each 16 bit memory operand is assumed to be a 17 bit word with sign extension i For unsigned multiplication a 0 is added to the MSB bit 16 in each input operand i For signed unsigned multiplication one of the operands is sign extended and the other is extended with a 0 in the MSB zero filled The multiplier output can be shifted left by one bit to compensate for the extra sign bit generated by multiplying two 16 bit 2s complement numbers in frac tional mode Fractional mode is selected when the FRCT bit 1 in ST1 The adder in the multiplier adder unit contains a zero detector a rounder 2s complement and overflow saturation logic Rounding consists of adding 215 to the result and then clearing the lower 16 bits of the destination accumulator Rounding is performed in some multiply MAC and multiply subtract MAS instructions when the suffix R is included with the instruction The LMS instruc tion also rounds to minimize quantization errors in updated coefficients The adder s inputs come from the multiplier s output and from one of the accu mulators Once any multiply operation is performed in the unit the result is transferred to a destination accumulator A or B Ce
210. able 10 4 Number of CLKOUT1 Cycles Per Access for Various Numbers of Wait States Number of CLKOUT1 Cyclest Hardware Wait State Software Wait State _ Number of Wait States Read Write Read Write 0 NA NA 1 2n 1 NA NA 2 3n 2 3 4n 3 4n 3 4 5n 4 5n T Where n is the number of consecutive write cycles 10 8 External Bus Operation SPRU131G External Bus Control 10 3 2 Bank Switching Logic Programmable bank switching logic allows the C54x DSP to switch between external memory banks without requiring external wait states for memories that need several cycles to turn off The bank switching logic automatically inserts one cycle when accesses cross memory bank boundaries inside program or data space Bank switching is defined by the bank switching control register BSCR which is memory mapped at address 0029h Figure 10 5 shows the BSCR and its fields are described in Table 10 5 For more information about bank switching logic see the device specific datasheet Figure 10 5 Bank Switching Control Register BSCR Diagram 15 12 11 10 9 8 7 3 2 1 0 R W R W R W R W R W R W Table 10 5 Bank Switching Control Register BSCR Bit Summary Reset Bit Name Value Function 15 12 BNKCMP Bank compare Determines the external memory bank size BNKCMP is used to mask the four MSBs of an address For example if BNKCMP 1111b the four MSBs bits 12 15 are compared resulting in a bank size of 4K words Bank sizes from 4K words to 64K words
211. ace multichannel buffered serial port interface and time division multiplexed serial port interface 9 1 9 2 SPRU131G Introduction to the Serial Ports 2 0c cece eee teen ees Serial Port Interface ss derei nieta oiea onia a eee ent eens 9 2 1 Serial Port Interface Registers 0 9 2 2 Serial Port Interface Operation 00 cece ees Contents xix Contents 10 XX 9 2 3 Configuring the Serial Port Interface 0 0 cece cee eee 9 2 4 Burst Mode Transmit and Receive Operations 00020e2 eee 9 2 5 Continuous Mode Transmit and Receive Operations 9 2 6 Serial Port Interface Exception Conditions 0 cece eee eee 9 2 7 Example of Serial Port Interface Operation 00 cece ee eee 9 3 Buffered Serial Port BSP Interface 0 eee eens 9 3 1 BSP Operation in Standard Mode 0 0 00 cee cence eee 9 3 2 Autobuffering Unit ABU Operation 0 00 c cece eee 9 3 3 System Considerations for BSP Operation 00 cece eee eee 9 3 4 Buffer Misalignment Interrupt BMINT C549 only 9 3 5 BSP Operation in Power Down Mode 00 cece eee e eens 9 4 Time Division Multiplexed TDM Serial Port Interface 0 000 00 eee 9 4 1 Basic Time Division Multiplexed Operation 00 cee eee eee 9 4 2 TDM Serial Port Interface Registers 000 cece eee ee 9 4 3 TDM Serial Port Interface Op
212. ace on page 8 36 for more details about HPI operation Table 2 3 Host Port Interfaces on the TMS320C54x Devices Host Port Interface C541 C542 C543 C545 C546 C548 C549 C5402 C5410 C5420 Standard 8 bit HPI Enhanced 8 bit HPI Enhanced 16 bit HPI 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 2 14 Architectural Overview SPRU131G 2 8 Serial Ports Serial Ports The serial ports on the C54x DSP vary by device and are represented by four types synchronous buffered multichannel buffered McBSP and time division multiplexed TDM See Table 2 4 for the number of each type on the various C54x devices The sections that follow provide an introduction to the four types of serial ports For more details about these ports see Chapter 9 Serial Ports For detailed information about the McBSPs see TMS320C54x DSP Enhanced Peripherals Reference Guide SPRU302 Table 2 4 Serial Port Interfaces on the TMS320C 54x Devices Serial Ports C541 Synchronous 2 Buffered 0 Multichannel 0 Buffered TDM 0 C542 C543 C545 C546 C548 C549 C5402 C5410 C5420 0 0 1 1 0 0 0 0 0 1 1 1 1 2 2 0 0 0 0 0 0 0 0 0 2 3 6 1 1 0 0 1 1 0 0 0 2 8 1 Synchronous Serial Ports Synchronous serial ports are high speed full duplexed serial ports that provide direct communication with serial devices such as codecs analog to digital A D converters and other serial systems When more than one synchronous serial port resides on a C54x
213. active cycle when memory banks are switched Figure 10 6 Bank Switching Between Memory Reads R W PS or DS 10 12 External Bus Operation SPRU131G External Bus Control Figure 10 7 illustrates the insertion of the extra cycle between a consecutive program read and a data read Figure 10 7 Bank Switching Between Program Space and Data Space oor NY NL NS NS _ SPRU131G External Bus Operation 10 13 External Bus Interface Timing 10 4 External Bus Interface Timing All external bus accesses complete in an integral number of CLKOUT cycles One CLKOUT cycle is defined as the time from one falling edge to the next falling edge of CLKOUT Some external bus accesses with no wait states for example memory writes or I O writes and I O reads take two cycles Memory reads take one cycle however if a memory read follows a memory write or vice versa the memory read takes an additional half cycle The following sections discuss zero wait state accesses unless otherwise specified 10 4 1 Memory Access Timing The MSTRB signal is low for the active portion of reads and writes an active portion of a memory access lasts at least one CLKOUT cycle In addition a transition CLKOUT cycle occurs before and after the active portion for writes During this transition cycle O MSTRB is high ty RM changes on CLKOUT s rising edge when required The address changes on CLKOUT s rising edge i
214. ages 984 987 May 1989 15 Papamichalis P and R Simar Jr The TMS320C30 Floating Point Digi tal Signal Processor IEEE Micro Magazine USA pages 13 29 Decem ber 1988 16 Papamichalis P E FFT Implementation on the TMS320C30 Proceed ings of ICASSP 88 USA Volume D page 1399 April 1988 17 Parks T W and C S Burrus Digital Filter Design New York NY John Wiley and Sons Inc 1987 18 Peterson C Zervakis M Shehadeh N Adaptive Filter Design and Implementation Using the TMS320C25 Microprocessor Computers in Education Journal USA Volume 3 Number 3 pages 12 16 July Sep tember 1993 19 Prado J and R Alcantara A Fast Square Rooting Algorithm Using a Digital Signal Processor Proceedings of IEEE USA Volume 75 Number 2 pages 262 264 February 1987 20 Rabiner L R and B Gold Theory and Applications of Digital Signal Pro cessing Englewood Cliffs NJ Prentice Hall Inc 1975 21 Simar Jr R and A Davis The Application of High Level Languages to Single Chip Digital Signal Processors Proceedings of ICASSP 88 USA Volume D page 1678 April 1988 22 Simar Jr R T Leigh P Koeppen J Leach J Potts and D Blalock A 40 MFLOPS Digital Signal Processor the First Supercomputer on a Chip Proceedings of ICASSP 87 USA Catalog Number 87CH2396 0 Volume 1 pages 535 538 April 1987 23 Simar Jr R and J Reimer The TMS320C25 a 10
215. aha oe DAO RN Rae ee a br nee eeeS Barrel Shifter Functional Diagram 0 00 cece eee eee Multiplier Adder Functional Diagram 0 6000 c cece ete Compare Select and Store Unit CSSU 0 eee eee Viterb Operator iari nese gr td pehta bbe eee TAR ead Oded ed eee ee dee ee es EXPOMENLENCOER sesaria ideas ie die bees it de lade Ake de Be deeds Figures SPRU131G Figures 5 1 RPT Instruction With Short Immediate Addressing 2 ccce cece eee eee 5 2 RPT Instruction With 16 Bit lmmediate Addressing 02 cece eeee eens 5 3 Direct Addressing Instruction Format 0 c cece eee eee 5 4 Direct Addressing Block Diagram 0 cece ete EEN 5 5 DP Referenced Direct Address 000 cece aeaaaee aaeeea 5 6 SP Referenced Direct Address 0 0 cece cette net ete n eens 5 7 Indirect Addressing Instruction Format for a Single Data Memory Operand 5 8 Indirect Addressing Block Diagram for a Single Data Memory Operand 5 9 Circular Addressing Block Diagram 0c cece eee eee teens 5 10 Circular Buffer Implementation 00 cece eee eens 5 11 Indirect Addressing Instruction Format for Dual Data Memory Operands 5 12 Indirect Addressing Block Diagram for Dual Data Memory Operands 5 13 How ARP Indexes the Auxiliary Registers 0 c cece ees 5 14 Indirect Addressing Instruction Format for Compatib
216. ame for both conditions you cannot test conditions for both accumulators with the same instruction For example you can test AGT and AOV atthe same time but you can not test AGT and BOV at the same time I Group 2 You can select one condition from each of three categories A B and C No two conditions can be from the same category For example you can test TC C and BIO at the same time but you cannot test NTC C and NC at the same time Table 6 14 Grouping of Conditions for Multiconditional Instructions Group 1 Group 2 CategoryA CategoryB Category A CategoryB Category _ EQ OV TC C BIO NEQ NOV NTC NC NBIO LT LEQ GT GEQ 6 6 2 Conditional Execute XC Instruction SPRU131G Where code branches conditionally over a 1 or 2 word code segment you can replace the branch with a 1 cycle conditional execute instruction XC There are two forms for the XC instruction One form is a conditional execute of a 1 word instruction XC 1 cond The second form is a conditional execute of one 2 word instruction or two 1 word instructions XC 2 cond Conditions for XC are the same as the conditions for conditional branches calls and returns see Table 6 13 Program Memory Addressing 6 17 Conditional Operations The condition must be stable two full cycles before the XC instruction is executed This ensures that the decision is made before the instruction follow ing XC is decoded Avoid changing the XC condition in the two
217. an access a different block with out conflict Furthermore each memory block supports two accesses in a single cycle two instructions each in different stages of the pipeline can access the same block simultaneously However a conflict can occur when two simultaneous accesses are performed on the same block The C54x CPU resolves these conflicts automatically this is discussed later in this section Table 7 1 shows the block size and number of blocks for some C54x devices For more information about DARAM organization see section 3 3 2 On Chip RAM Organization on page 3 23 Table 7 1 DARAM Blocks SPRU131G Device BlockSizet_ Numberof Blocks C541 1K words 5 C542 2K words 5 C543 2K words 5 C545 2K words 3 C546 2K words 3 C548 2K words 4 C549 2K words 4 C5402 8K words 2 C5410 2K words 4 C5420 each subsystem 8K words 2 T Note that the first block is slightly smaller due to the memory mapped registers and the scratch pad RAM Each dual access memory block supports two accesses in one cycle by per forming one access in the first half cycle and the other in the next half cycle Table 7 2 lists the accesses performed in each half cycle and Figure 7 3 shows how the different types are performed Address bus loads are omitted from the diagram for simplicity Pipeline 7 27 Dual Access Memory and the Pipeline Table 7 2 Accessing DARAM Blocks This type of access Is performed in the Instructio
218. an advantage over offset addressing it does not require an additional word for the instruction The syntaxes for subtracting ARO from ARx and for adding ARO to ARx are shown in Table 5 4 for MOD 5 and 6 respectively 5 5 3 4 Circular Address Modifications MOD 8 9 10 11 or 14 SPRU131G Many algorithms such as convolution correlation and FIR filters require the implementation of a circular buffer in memory In these algorithms a circular buffer is a sliding window containing the most recent data As new data comes in the buffer overwrites the oldest data The key to the implementation of a circular buffer is the implementation of circular addressing Data Addressing 5 15 Indirect Addressing The circular buffer size register BK specifies the size of the circular buffer A circular buffer of size R must start on a N bit boundary that is the N LSBs of the base address of the circular buffer must be 0 where N is the smallest integer that satisfies 2N gt R The value R must be loaded into BK For example a 31 word circular buffer must start at an address whose five LSBs are 0 that is XXXX XXXX XXXO 00002 and the value 31 must be loaded into BK As a second example a 32 word circular buffer must start at an address whose six LSBs are 0 that is XXXX XXXX XX00 000092 and the value 32 must be loaded into BK In some applications however it may be possible to use bit reversed addressing to place a 2N buffer on a
219. and access both the C for most significant word and the D for least significant word buses are used for a read However because only the E bus is used for a write the write operation DST instruction is executed in two cycles With 32 bit accesses the first word accessed is treated as the most significant word MSW while the second word accessed is the least significant word LSW If the first word accessed is at an even address then the second word is at the next higher address If the first word accessed is at an odd address then the second word is at the previous lower address Figure 5 17 shows this effect 5 28 Data Addressing SPRU131G Data Types Figure 5 17 Word Order in Memory Accumulator MSW LSW DST 1000h DST 1001h Write order Write order when addr 1000h when addr 1001h 1000h MSW 1000h LSW 1001h LSW 1001h MSW SPRU131G Data Addressing 5 29 Chapter 6 Program Memory Addressing This chapter discusses how program memory addresses are generated and which addresses are loaded into the program counter PC This chapter also describes the following program control operations that affect the value loaded in the PC Branches Calls Returns Conditional operations Repeats of an instruction or a block of instructions Hardware reset Interrupts O O O C C O L These operations can cause a nonsequential address to be loaded into PC Section 7 1
220. and the BSP once XSR is loaded with the value from DXR XRDY goes high generating a transmit interrupt XINT and setting XSREMPTY to a 1 Figure 9 5 Burst Mode Serial Port Transmit Operation ex A NA VS NA NAI NIA NI NAINI ODOT TOOT FSX TXM 1 af W L DX FO 1 AIK _A2 KAS XK Aa XK A5 XAG XK AZ_X_ AB _B1 XRDY 7 fF fT i r a SaO a SP XINT SP a D cee Ce ees ee ee ee ee a cee XSREMPTY SP A S a an rr a a ee ae a BSP XINT a a a a a a a ee ee ee ee a a a XSREMPTY oy f wo i wes BSP ___ 9 18 Serial Ports A A a DXR XSR loaded loaded DXR ean rel reloaded eloaded BSP XSR reloaded SP Note that in both the SP and the BSP DXR to XSR transfers occur only if the XSR is empty and the DXR has been loaded since the last DXR to XSR trans fer If DXR is reloaded before the old DXR contents have been transferred to XSR the previous DXR contents are overwritten Accordingly unless overwrit ing DXR is intended the DXR should only be loaded if XRDY 1 This is assured if DXR writes are made only in response to a transmit interrupt or polling XRDY SPRU131G Serial Port Interface It should be noted that in the following discussions the timings are slightly different for internally TXM 1 FSX is an output and externally TXM 0 FSX is an input generated frame syncs This distinction is made because in the former case the
221. and the initial starting address within this buffer this is explained in detail below Often the initial starting address within the buffer is 0 indicating the start of the buffer the top of buffer address but the initial starting address may be any point within the defined buffer range Once initialized BKX R can be considered to consist of two parts the most significant or higher part BKH which corresponds to the all of the most signifi cant 0 bits of BKX R and the lower part BKL which is the remaining bits of which the most significant bit is a 1 and whose bit position is designated bit position N The N bit position also defines the two parts ARH and ARL of the address register The top of buffer address TBA is defined by the concatena tion of ARH with N 1 least significant 0 bits The bottom of buffer address BBA is defined by the concatenation of ARH and BKL 1 and the current address within the buffer is specified by the complete contents of ARX R A circular buffer of size BKX R must therefore start on an N bit boundary the N least significant bits of the address register are 0 where N is smallest integer that satisfies 2N gt BKX R or at the lowest address within the 2K memory block The buffer consists of two halves the address range for the first half is TBA gt BKL 2 1 and for the second half BKL 2 gt BKL 1 Figure 9 26 illustrates all of the relationships between the defined buffer and the BKX R an
222. and the time the XF pin is set or reset refer to the TMS320C54x DSP data sheet for timing specifications The XF timing shown is for a sequence of single cycle instructions Actual timing can vary with different instruction sequences Figure 8 1 External Flag Timing Diagram CLKOUT SSBX or RSBX instruction Delay__pl g prefetch fetch decode access read write D 8 20 On Chip Peripherals SPRU131G Timer 8 4 Timer The on chip timer is a software programmable timer that consists of three registers and can be used to periodically generate interrupts The timer resolu tion is the CPU clock rate of the processor The high dynamic range of the timer is achieved with a 16 bit counter with a 4 bit prescaler The C5402 and the C5420 have two on chip timers 8 4 1 Timer Registers The on chip timer consists of three memory mapped registers TIM PRD and TCR These three registers and their respective timer addresses are listed in Table 8 13 Table 8 13 Timer Registers Timer 1 Timer 0 Address Address C5402 only Register Description 0024h 0030h TIM Timer register 0025h 0031h PRD Timer period register 0026h 0032h TCR Timer control register _ Timer register TIM The 16 bit memory mapped timer register TIM is loaded with the period register PRD value and decremented _j Timer period register PRD The 16 bit memory mapped timer period reg ister PRD is used to reload the timer register TIM J Timer
223. andshake must be per formed prior to writing the first data value to DXR Description This places both the transmit and receive portions of the serial port in reset and sets up the serial port to operate with internally gener ated FSX and CLKX signals and FSX FSR required for transmit receive of each 16 bit word The alternative is used if another de vice will provide FSX and CLKX Eliminate any interrupts that may have occurred before initializa tion Enable both transmit and receive interrupts A common alterna tive when transmit and receive are synchronized to one another is to enable only one or the other by ORing 0080h or 0040h with IMR and performing both I O operations with the same interrupt service routine ISR Interrupts must be globally enabled for the CPU to respond This takes both the transmit and receive portions of the serial port out of reset and starts operations with the conditions defined in step 1 This initiates serial port transmit operations if FSX and CLKX are internally generated or prepares the serial port transmit for opera tion when the first FSX arrives Example 9 2 Serial Port Interrupt Service Routine 9 32 Action Save any context that may be modi fied on the stack Read the DRR or write the DXR or both The data read form DRR should be written to a predetermined location in memory The data written to DXR should be read from a prede termined location in memory Resto
224. andshake to notify the transmitting device that it is okay to send data Description This places both the transmit and receive portions of the TDM serial port in reset and sets up the serial port to operate with externally generated TFRM and TCLK signals in TDM mode Eliminate any interrupts that may have occurred before initialization Enable receive interrupts Interrupts must be globally enabled for the CPU to respond This sets up this device to not transmit in any time slot This sets up this device to not address any device It also sets up this device to receive data sent to address 01h For asingle device pair this could make use of BIO and XF For sever al devices this might mean that the device waits for a broadcast com mand and then returns an acknowledge Example 9 8 TDM Serial Port Receive Interrupt Service Routine 9 68 Action Save any context that may be modified on the stack Read TDRR and write the value to a predetermined location in memory Restore the context that was saved in step 1 Return from the ISR with an RETE to reenable interrupts Serial Ports Description The operating context of the interrupted code must be maintained Read the new received data for the ISR The operating context of the interrupted code must be maintained Interrupts must be reenabled for the CPU to respond to the next interrupt SPRU131G Chapter 10 External Bus Operation This chapter d
225. ansfer and then the clock halts These options are listed in Table 9 6 The receive side functions in a similar fashion Note that if an option other than immediate stop Soft Free 0 is chosen the receiver continues running and an overflow error is possible The default value for these bits is immediate stop Table 9 6 Serial Port Clock Configuration SPRU131G Free Soft Serial Port Clock Configuration 0 0 Immediate stop clocks are stopped Reset values 0 1 Transmitter stops after completion of the current word The receiver is not affected 1 X Free run Note X Don t care Serial Ports 9 17 Serial Port Interface 9 2 4 Burst Mode Transmit and Receive Operations In burst mode operation there are periods of serial port inactivity between packet transmits The data packet is marked by the frame sync pulse occurring on FSX see Figure 9 5 On the transmit device the transfer is initiated by a write to DXR The value in DXR is then transferred to XSR and upon a frame sync pulse on FSX generated internally or externally depending on TXM the value in XSR is shifted out and driven on the DX pin Note that on the SP the DXR to XSR transfer occurs on the second rising edge of CLKX after DXR is loaded while on the BSP this transfer does not occur until an FSX occurs when FSX is external When FSX is internal on the BSP the DXR to XSR trans fer and generation of FSX occur directly after loading DXR On both the SP
226. as a 0 4 TSS 0 Timer stop status Stops or starts the on chip timer At reset TSS is cleared and the timer immediately starts timing TSS 0 The timer is started TSS 1 The timer is stopped 3 0 TDDR 0000 Timer divide down ratio Specifies the timer divide down ratio period for the on chip timer When PSC is decremented past 0 PSC is loaded with the contents of TDDR 8 22 On Chip Peripherals SPRU131G Timer 8 4 2 Timer Operation The timer is an on chip down counter that can be used to periodically generate CPU interrupts The timer is driven by a prescaler that is decremented by 1 at every CPU clock cycle Each time the counter decrements to 0 a timer interrupt TINT is generated and the down counter is reloaded with the period value See section 6 10 Interrupts on page 6 26 for more details about interrupts Figure 8 3 shows a logical block diagram of the timer It consists of two basic blocks the main timer block consisting of PRD and TIM and a prescaler block consisting of TDDR and PSC bits in TCR The timer is clocked by the CPU clock Figure 8 3 Timer Block Diagram SPRU131G SRESET CPU clock PSC lt TSS gt TINT gt gt TOUT Under normal operation TIM is loaded with the contents of PRD when TIM decrements to 0 The contents of PRD are also loaded into TIM when the device is reset SRESET input in Figure 8 3 or when the timer is individually reset TRB input i
227. as an input TXM 0 or as an out put TXM 1 TXM 0 External frame sync The transmitter idles until a frame sync pulse is supplied on the FSX pin TXM 1 Internal frame sync Frame sync pulses are generated internally when data is transferred from the DXR to XSR to initiate data transfers The internally generated framing signal is synchronous with respect to CLKX Clock Mode This bit specifies the clock source for CLKX MCM 0 CLKX is taken from the CLKX pin MCM 1 CLKX is driven by an on chip clock source For the SP and the BSP in standard mode this on chip clock source is at a frequency of one fourth of CLKOUT The BSP also allows the option of generating clock frequencies at additional ratios of CLKOUT For a detailed description of this feature see section 9 3 Buffered Serial Port BSP Interface on page 9 33 Note that if MCM 1 and DLB 1 a CLKR signal is also supplied by the internal source Frame Sync Mode This bit specifies whether frame synchronization pulses FSX and FSR are required after the initial frame sync pulse for serial port operation See section 9 2 2 Serial Port Interface Operation on page 9 6 for more details on the frame sync signals FSM 0 Continuous mode Frame sync pulses are not required after the initial frame sync pulse but they are not ignored therefore improperly timed frame syncs may cause errors in serial transfers See section 9 2 6 Serial Port Interface Exception Conditions
228. as taken place for example the timer is finished counting The C54x DSP supports both software and hardware interrupts A software interrupt is requested by a program instruction INTR TRAP or RESET Lj A hardware interrupt is requested by a signal from a physical device Two types exist m External hardware interrupts are triggered by signals at external inter rupt ports E Internal hardware interrupts are triggered by signals from the on chip peripherals When multiple hardware interrupts are triggered at the same time the C54x DSP services them according to a set priority ranking in which 1 has the highest priority To determine the priorities for the hardware interrupts refer to the table for your particular C54x device in section 6 10 10 Interrupt Tables on page 6 38 Each of the C54x DSP interrupts whether hardware or software can be placed in one of the following two categories J Maskable interrupts These are hardware or software interrupts that can be blocked masked or enabled unmasked using software The C54x DSP supports up to 16 user maskable interrupts SINT15 SINTO Each device uses a subset of these 16 interrupts For example the C541 uses only nine of these interrupts the others are tied high internally Some of these have two names because they can be initiated by software or hardware for the C541 the hardware names for these interrupts are m INT3 through INTO E RINTO XINTO RINT
229. as the base address for direct addressing in compiler mode CPL 1 or an interrupt occurs Interrupts cause an update of SP This update of SP can interfere with a previous write to SP Therefore special considerations must be made when using interrupts while executing instructions that update SP The conflict occurs because the second instruction tries to use SP in a pipeline stage that occurs before the previous instruction updates it Table 7 9 lists the latencies between instructions that update and subse quently use SP in compiler mode NS Note You are responsible for rearranging instructions or inserting NOPs if necessary to accommodate for SP latencies 7 50 Pipeline SPRU131G Table 7 9 Latencies for SP in Compiler Mode CPL 1 a Latencies based on third instruction category Third Instruction Category Pipeline Latencies Category Il Second Instruction STM lk SP ST lk SP MVDK Smem SP MVMD MMR SP MVKD dmad SP MVDM_ dmad SP MVPD pmad SP MVDD Xmenm spind POPM SP POPD SP FRAME k MVMM MMR SP POPM MMR POPD Smem PSHM MMR PSHD Smem RETFD 1t 1t at ot ot it Store type instructions see Table 7 5 b Categories for the third instruction Category Category Il All instructions using SP in direct addressing mode except those listed in MVKD dmad dirmem MVDM dirmem MMR MVPD pmad dirmem Category Il MACP dirmem pmad src MACD di
230. ate that the repeat block loop is active BRAF is set or cleared in the decode stage of the first instruction of the repeat block loop during the last loop iteration BRC 0 BRAF is tested by the device at the end of each loop iteration to determine whether the next prefetch will be from the top of the loop or not SPRU131G Pipeline Latencies BRAF can be deactivated in software to terminate the repeat block premature ly This however must be done early enough in the pipeline so that BRAF is cleared prior to the prefetch of the instruction at the top of the loop Therefore an instruction that clears BRAF such as RSBX must be placed at least six instructions words before the end of the repeat block loop This is shown in Example 7 58 Example 7 58 BRAF Deactivation RPTB endloop 1 RSBX BRAF This ensures that the loop will NOP terminate after completing this NOP iteration NOP NOP These six NOPs may be replaced by NOP other instructions NOP endloop 7 5 9 Latencies for the PMST SPRU131G PMST fields OVLY DROM MP MC and IPTR configure the C54x DSP memory space When an instruction modifies one of these fields a certain number of pipeline cycles must pass before the new memory space can be accessed This latency is required because the PMST fields are updated in the read or execute stage of the pipeline while instructions in earlier pipeline stages may be accessing that memory space In the case
231. autobuffering transmitter autobuffering transmitter halt HALTX A bitin the BSP control extension extension BSPCE that enables disables the autobuffer transmitter when the current half of the buffer has been transmitted autobuffering unit An extension to the synchronous serial port that reads and writes data to the synchronous serial port independent of the CPU auxiliary register arithmetic unit An unsigned 16 bit arithmetic logic unit ALU used to calculate indirect addresses using auxiliary registers auxiliary register file The area in data memory containing the eight 16 bit auxiliary registers See also auxiliary registers auxiliary register pointer ARP A 3 bitfield in status register 0 STO used as a pointer to the currently selected auxiliary register when the device is operating in C5x C2xx compatibility mode D 2 Glossary SPRU131G SPRU131G Glossary auxiliary registers Eight 16 bit registers AR7 ARO that are used as pointers to an address within data space These registers are operated on by the auxiliary register arithmetic units ARAUs and are selected by the auxiliary register pointer ARP See also auxiliary register arithmetic unit AVIS See address visibility mode bit AXR AXRO AXR1 ABU address transmit register A 16 bit register that specifies the source address from which the autobuffering unit begins transmitting data B See accumulator B bank switching control register
232. b1 PB j1 IR j1 a ji For the branch instruction in Example 7 2 to execute completely the following events occur Cycle 1 The PAB is loaded with the address of a branch instruc tion Cycles 2 and 3 Two words of the branch instruction are fetched 7 6 Pipeline SPRU131G Cycles 4 and 5 Cycles 6 and 7 Cycles 8 and 9 Cycle 10 Pipeline Operation Two more instructions i3 and i4 are fetched Although the two instructions after the branch instruction i3 and i4 are fetched by the C54x CPU they are not allowed to move past the decode stage and are eventually discarded After the second word of the branch instruction represented by b1 in the left column is decoded PAB is loaded with this new value in cycle 5 The two word branch instruction enters the execution stage of the pipeline in cycles 6 and 7 Also j1 is fetched from address b1 in cycle 6 These cycles are also consumed by the same branch instruction since the next two instructions i3 and i4 were not allowed to complete their execution this is why a branch instruction takes four cycles to execute j1 completes execution Example 7 3 shows the pipeline s behavior for a delayed branch instruction Example 7 3 Delayed Branch BD Instruction in the Pipeline Address Instruction al a2 BD b1 a3 i3 a4 i4 b1 jl 1 2 3 4 5 6 7 8 9 10 Prefetch Fetch Decode Access Read Execute BD PAB ai PB BD IR BD BD Prefetch Fetch Decode A
233. bia ews deeds date de bea da wea was Accumulator Store With Shift 0 00 c cece een eee ees CMPS Instruction Operation 000 c inadai aa data aa aaa d E A ea a E E A Normalization of Accumulator A saaaa ananasa aaan anaana Sequence of Auxiliary Registers Modifications in Bit Reversed Addressing Sample Pipeline Diagram sesse snosinsadiiu ideni nadia aa da a D aa a D Aa a Branch B Instruction in the Pipeline 0 0 cee eee Delayed Branch BD Instruction in the Pipeline 0 0 eee eee eee Call Instruction in the Pipeline 0 0 cee eects Delayed Call CALLD Instruction in the Pipeline 0 00 cece eee eee Interrupt INTR Instruction in the Pipeline 0 0 0 cece eee Return RET Instruction in the Pipeline 00 cece Delayed Return RETD Instruction in the Pipeline ccc eee eee eee Return With Interrupt Enable RETE Delayed Return With Interrupt Enable RETED Instruction in the Pipeline Return Fast RETF Instruction in the Instruction in the Pipeline Pipeline 0 0 cece eects Delayed Return Fast RETFD Instruction in the Pipeline 2 005 Execute Conditionally XC Instruction in the Pipeline 00 e eee ee Conditional Call CC Instruction in th PIDGIING 22 2 duvawduvadduvetectat dees bee as Delayed Conditional Call CCD Instruction in the Pipel
234. bit 9 10 9 15 D 10 MCM bit 9 11 9 14 D 6 RRDY bit 9 10 9 15 D 14 RRST bit 9 10 9 141 c14 RSRFULL bit_ 9 9 9 16 D Soft bit 9 9 9 17 D 16 TXM bit 9 11 9 14 D 18 XRDY bit ID 19 XRST bit XSREMPTY bit 9 9 9 16 D 19 serial port data receive register DRR definition serial port data transmit register DXR definition serial port interface_ 9 41 block diagram configuring 9 8 error conditions 9 26 operation operation examples 9 31 pins receive operation burst mode 9 18 continuous mode 9 24 registers reserved bit Index 16 transmit operation burst mode continuous mode p 24 serial port interfaces three types serial port receive interrupt RINT definition serial port transmit interrupt XINT definition D 16 serial ports buffered serial port BSP 9 33 block diagram operation in sang mode 9 35 initialization timing 9 50 introduction oe on various C54x devices serial port interface table three types time division multiplexed TDM receive initialization routine 9 receive interrupt service routine 68 register contents transmit initialization routine 9 67 transmit interrupt service routine 67 where to find information shared access mode SAM shared RAM shared access mode SAM D 16 shared access mode SMOD definition shift and rotate operations 4 14 rotate accumulator left 4 14 rotate accumulator left with TC 4 14 rotate accumulator right_ 4 14
235. bits See also PMST ST1 ST1 A16 bit register that contains C54x CPU status and control bits See also PMST STO stack A block of memory used for storing return addresses for subroutines and interrupt service routines and for storing data stack pointer SP A register that always points to the last element pushed onto the stack SXM See sign extension mode TADD TDM address A single bidirectional address line that identifies which devices on the four wire serial bus should read in the data on the TDM data TDAT line TC tesi control flag A bitin status register O STO that is affected by test operations TCLK TDM clock A single bidirectional clock line for TDM operation TCR timer control register A 16 bit memory mapped register that contains status and control bits for the on chip timer TCSR TDM channel select register A 16 bit memory mapped register that specifies in which of the eight time slots channels a device on the four wire serial bus is to transmit TDAT TDM data A single bidirectional line from which all TDM data is carried TDM receive interrupt TRINT A bit in the interrupt flag register IFR that indicates the TDM data receive shift register TRSR contents have been copied to the TDM data receive register TRCV TDM transmit interrupt TXINT A bitin the interrupt flag register IFR that indicates the TDM data transmit register TDXR contents have been copied to the data transm
236. bly software development and has the capability to debug multiple processors This productis currently available for PCs DOS Windows OS 2 HP worksta tions and SPARC workstations This product includes the emulator board emulator box power supply and SCSI connector cables in the HP and SPARC versions the C54x DSP C source debugger and the JTAG cable B 2 Development Support and Part Order Information SPRU131G Development Support Because the C2000 C3x C4x and C5x XDS510 emulators also come with the same emulator board or box as the C54x emulator you can buy the C54x C Source Debugger Software as a separate product called the C54x C Source Debugger Conversion Software This enables you to debug C54x DSP applications with a previously purchased emulator board The emulator cable that comes with the C3x XDS510 emulator can not be used with the C54x DSP emulator You need the JTAG emulation conversion cable see section B 2 instead The emulator cable that comes with the C5x XDS510 emulator can be used with the C54x DSP emulator without any restriction See the TMS320C54x C Source Debug ger User s Guide for detailed information about the C54x DSP emulator LJ The TMS320C54x evaluation module EVM is a PC AT plug in card that lets you evaluate certain characteristics of the C54x DSP to see if it meets your application requirements The C54x EVM carries a C541 DSP on board to allow full speed verification of C54x DSP code The EV
237. burst mode operation SPRU131G Serial Port Interface Figure 9 20 SP BSP Transmitter Functional Operation Continuous Mode FSX pulse occurs XSREMPTY is low DXR to XSR copy occurs No transmit interrupt Start transmit Transmit in progress Aborttransmit New DXR since last transmit DXR to XSR copy No transmit interrupt Start transmit DXR to XSR copy Transmit interrupt Start new transmit Current word is lost 9 2 7 Example of Serial Port Interface Operation SPRU131G As an illustration of the proper operation of a standard serial port Example 9 1 and Example 9 2 define a sequence of actions This illustration is based on the use of interrupts to handle the normal I O between the serial port and CPU The C545 peripheral configuration has been used as a reference for these Serial Ports 9 31 Serial Port Interface Example 9 1 Serial Port Initialization Routine Action Reset and initialize the serial port by writing 0038h or 0008h to SPC Clear any pending serial port inter rupts by writing OOCOh to IFR Enable the serial port interrupts by ORing 00COh with IMR Enable interrupts globally if neces sary by clearing the INTM bitin ST1 Start the serial port by writing OOF8h or 0OC8h to SPC Write the first data value to DXR If the serial port is connected to the se rial port of another processor and this processor will be generating FSX a h
238. bus and the memory select signals program select PS data select DS and I O select IS maintain the previous state The MSTRB IOSTRB R W IAQ and MSC signals remain inactive If the address visibility mode AVIS bit located in the PMST is set to 1 the internal program address is placed on the address bus with an active IAQ When the CPU addresses external data or I O space the extended address lines are driven to logic 0 This is also the case when the CPU addresses inter nal memory with the AVIS address visibility set to 1 External Bus Operation 10 3 External Bus Priority 10 2 External Bus Priority The C54x CPU has one program bus PB three data buses CB DB and EB and four address buses PAB CAB DAB and EAB The CPU can access its buses simultaneously because of its pipelined structure however the external interface can support only one access per cycle A pipeline conflict occurs if in a single cycle the CPU accesses external memory twice to fetch an instruction adata memory operand or an external I O device This pipeline conflict is automatically resolved by a predetermined priority defined by the stage of the pipeline Figure 10 1 shows multiple CPU accesses to fetch an instruction and to write and read data operands over the external interface in one cycle Data accesses have a higher priority than program memory fetches the program memory fetch cannot begin until all CPU data accesse
239. caned s daei a innii anik EEEE EERE sa 4 3 AccumulatorsA andB 0 00 cece ttt teens 4 3 1 Storing Accumulator Contents 0 00 c ccc eee 4 3 2 Accumulator Shift and Rotate Operations 4 3 3 Saturation Upon Accumulator Store 6 0 cece 4 3 4 Application Specific Instructions 00 0 c cece eee Contents SPRU131G Contents 4 4 Barrel Shifters 2 ccccedeetnedenseeatapienveraRageerdawiebectitewdeh eed enedd 45 Multiplier Adder Unit 0 0 00 ccna 4 5 1 Multiplier Input Sources 0c cece eens 4 5 2 Multiply Accumulate MAC Instructions 0 00 c eee eee eee 4 5 3 MAC and MAS Saturation Upon Multiplication 4 6 Compare Select and Store Unit CSSU 0 cece eee eee 4 Exponent Encoder sse gaia gieiliecne dhe pea AEEA EAE ERR 5 Data Addressing 00ccce cece cece e eee eee eee e ee eee ee eee ee RENAA RENAA NA Describes the seven basic addressing modes of the TMS320C54x DSP 5 1 Immediate Addressing 2 2000 iiss ianiai eee enna 5 2 Absolute Addressing 00 cece eee haa nia ad hea eee 5 2 1 dmad Addressing riiai nanea p a a a aa inana ip da D22 spMad ACOIGSSING essneirnt danane RA EAA ERREA RARE 52 3 PA Addressing seiis erto neiaie i a aiaa aia edited a a a 52 4 1k ACOKOSSING sess reiden E Esra nade nase sane ead ed Rds ame eRe 5 3 Accumulator Addressing 0 0c cece pa ai aa aan a Aaa aoina 54 Direct Addressing ei
240. ccess Read Execute b1 PAB a2 PB b1 IR b1 b1 Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute ji SPRU131G Pipeline 7 7 Pipeline Operation In this case the pipeline behaves in the same manner as it did for the regular branch instruction However the two instructions following the branch i3 and i4 are allowed to complete their execution Therefore only cycles 6 and 7 are consumed by the delayed branch instruction making the delayed branch into a 2 cycle instruction 7 1 2 Call Instructions in the Pipeline A standard call instruction takes four cycles to execute Although a standard call is a two word instruction and seems to need only two cycles it actually flushes the pipeline for two cycles taking four cycles to execute Example 7 4 shows the pipeline s behavior during the execution of a call instruction Example 7 4 Call Instruction in the Pipeline Address Instruction al a2 CALL b1 a3 i3 a4 i4 b1 ji 1 2 3 4 5 6 7 8 9 10 Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute PAB Prefetch Fetch Decode Access Read Execute er PAB r a3 Prefetch Fetch Decode Access Read Execute peer PAB a4 Prefetch Fetch Decode Access Read Execute 7 8 Pipeline SPRU131G SPRU131G Pipeline Operation In Example 7 4 the following events occur Cycle 1 Cycles 2 and 3 Cycle 4 Cycl
241. ccumulator contents in data memory by using the STH STL STLM and SACCD instructions or by using parallel store instructions To store the 16 MSBs of the accumulator in memory with a shift use the STH SACCD and parallel store instructions For right shift operations bits from AG and BG shift into AH and BH For left shift operations bits from AL and BL shift into AH and BH respectively To store the 16 LSBs of the accumulator in memory with a shift use the STL instruction For right shift operations bits from AH and BH shift into AL and BL Central Processing Unit 4 13 Accumulators A and B respectively and the LSBs are lost For left shift operations the bits in AL and BL are filled with zeros Since shift operations are performed in the shifter the contents of the accumulator remain unchanged Example 4 3 shows the result of accumulator store operations with shift it assumes that accumulator A OFF 4321 1234h Example 4 3 Accumulator Store With Shift STH A 8 TEMP TEMP 2112h STH A 8 TEMP TEMP FF43h STL A 8 TEMP TEMP 3400h STL A 8 TEMP TEMP 2112h 4 3 2 Accumulator Shift and Rotate Operations The following instructions shift or rotate the contents of the accumulator through the carry bit SFTA shift arithmetically SFTL shift logically SFTC shift conditionally ROL rotate accumulator left ROR rotate accumulator right 1 ROL
242. ce The emulator pod provides optional internal paral lel terminators on the TCK_RET and TDO TMS and TDI provide fixed series termination Because TRST is an asynchronous signal it should be buffered as needed to ensure sufficient current to all target devices Design Considerations for Using XDS510 Emulator A 11 Connections Between the Emulator and the Target System A 6 2 Using a Target System Clock Figure A 6 shows an application with the system test clock generated in the target system In this application the emulator s TCK signal is left unconnected Figure A 6 Target System Generated Test Clock Greater than 6 inches Voc Vcc JTAG device Emulator header A EMUO EMUO EMU1 l EMU1 TRST TRST TMS lt e TMS TDI TDI TDO gt TDO TCK NC TCK gt TCK_RET v GND System test clock Note When the TMS and TDI lines are buffered pullup resistors must be used to hold the buffer inputs at a known level when the emulator cable is not connected There are two benefits in generating the test clock in the target system I The emulator provides only a single 10 368 MHz test clock If you allow the target system to generate your test clock you can set the frequency to match your system requirements J In some cases you may have other devices in your system that require a test clock when the emulator is not connected The system test clock also serves this purpose A 12 Design Con
243. cece s everday EnS AEDA NEE E O dae E E A a 5 4 1 DP Referenced Direct Addressing 0020 cece nennen 5 4 2 SP Referenced Direct Addressing 0 60 e cence eee eee 5 5 Indirect Addressing 00 cece eee teen eens 5 5 1 Single Operand Addressing 00 ccc eee eee eee e eee eee ane 5 5 2 ARAU and Address Generation Operation 00c eee ee eee eee 5 5 3 Single Operand Address Modifications 0 00 ccc e eee eee eee 5 5 4 Dual Operand Address Modifications 00 cece ences 5 5 5 Compatibility ARP Mode 22 0 0 cece eee eens 5 6 Memory Mapped Register Addressing 00 c cece eee eee eee eee 5 7 Stack Addressing 00 cece eee eee ees 5 8 Data TPES arrarir evi ee ieee ene eee eee yee A ANA 6 Program Memory Addressing 00ceee eee cece eee eee eee eee Describes the TMS320C54x DSP program control mechanisms Includes information about address generation the program counter the hardware stack reset interrupts and power down modes 6 1 6 2 6 3 6 4 SPRU131G Program Memory Address Generation Program Counter PC 0 0 cece eee eee teen e eee E eens Branches ahs Gotsa si daana aia an a e r a aa a wera e aa a n a a E A ean 6 3 1 Unconditional Branches 00 cece ccc ee tenes 6 3 2 Conditional Branches 0 0 ccc eee eens 6 3 3 Far BrancheS urreni ccc ce eee tte n ent e teen nee NS esas
244. ch Decode Access Read Execute STH A AR1 Suns to AR1 Prefetch Fetch Decode Access Read Execute STM 1 AR2 1st word Write Write to write delayed by 1 cycle to AR2 AR2 Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute to AR3 Prefetch Fetch Decode Access Read Execute Legend Where a write conflict occurs Where the write actually occurs SPRU131G Pipeline 7 41 Pipeline Latencies Example 7 23 Resolving Conflict When Updating ARx and BK STIM B BK This instruction updates BK in th xecute stag MVDK 200h AR1 This instruction tries to update AR1 in it read stage The CPU delays this update by one cycle to resolve the conflict 1 2 3 4 5 6 7 8 Prefetch Fetch Decode Access Read Execute STLM B BK Write to BK Prefetch Fetch Decode Access Read Execute MVDK 200h AR1 1st word Write to Write to write delayed by 1 cycle AR1 AR1 Prefetch Fetch Decode Access Read Execute Legend Where a write conflict Where the write actually occurs occurs 7 42 Pipeline SPRU131G Pipeline Latencies Example 7 24 Resolving Conflict When Updating SP BK and ARx STLM A SP This instruction updates SP in th xecute stag i POPM BK This instruction tries to update BK in its read stage The CPU delays this update by one cycle r STM 1 AR1 This instruction tries to update AR1 in its read stage conflicting with the previous instruct
245. ch actually controls sampling of the HCNTLO 1 HBIL and HR W inputs Because HDS1 and HDS2 are exclusive NORed both these inputs being low does not constitute an enabled condition On Chip Peripherals 8 41 Host Port Interface Figure 8 8 Select Input Logic D HDS2 _ Internal Strobe When using the HAS input to sample HCNTLO 1 HBIL and HRM this allows these signals to be removed earlier in an access cycle therefore allowing more time to switch bus states from address to data information facilitating interface to multiplexed address and data type buses In this type of system an ALE signal is often provided and would normally be the signal connected to HAS The two control pins HCNTLO and HCNTL1 indicate which internal HPI regis ter is being accessed and the type of access to the register The states of these two pins select access to the HPI address HPIA HPI data HPID or HPI control HPIC registers The HPIA register serves as the pointer into HPI memory the HPIC contains control and status bits for the transfers and the HPID contains the actual data transferred Additionally the HPID register can be accessed with an optional automatic address increment Table 8 22 describes the HCNTLO 1 bit functions Table 8 22 HPI Input Control Signals Function Selection Descriptions HCNTL1 0 0 8 42 HCNTLO Description 0 1 Host can read or write the HPI control register
246. chip ROM and will read FFFFh Instructions from on chip RAM or external program can branch to on chip ROM Can start from either microprocessor mode MP MC 1 or microcomputer mode MP MC 0 depending on the logic level of the MP MC pin Can change MP MC bit in PMST with software Instructions from on chip ROM can read data from on chip ROM Instructions from on chip RAM or external program cannot read data from on chip ROM and will read FFFFh Instructions from on chip RAM or external program can branch to on chip ROM Can start from only microcomputer mode MP MC 0 and not dependent on the logic level of the MP MC pin Can change MP MC bit in PMST with software Table 3 5 HPI Access in Memory Security Modes for Specific Devices HPI read availability for RAM and ROM RAM HPI write availability for RAM and ROM RAM security security TMS320C549 32K 2K Can read entire 2K Can read only 2K block 1000h 17FFh Cannot read Can read only 8K block Can write entire 2K Can write only 2K block 1000h 17FFh Can write entire 32K Can write entire 128K 4000h 5FFFh On chip RAM Device size HPI RAM size TMS320C5410 64K 64K TMS320C5409 32K 32K TMS320C5416 128K 128K TMS3205409A 32K 32K TMS3205410A 64K 64K Can read only 8K block 4000h 5FFF Can read only 8K block Can write only 8K block 4000h 5FFF Can write only 8K block 4000h 5FFF 4000h 5FFF 3 30 Memory
247. ciece nersjere niin Soan EE EE E EEEE EEE E E nye 5 1 Immediate Addressing 5 1 Immediate Addressing In immediate addressing the instruction syntax contains the specific value of the operand Two types of values can be encoded in an instruction J Short immediate values can be 3 5 8 or 9 bits in length g Long immediate values are always 16 bits in length Immediate values can be encoded in 1 word or 2 word instructions The 3 5 8 or 9 bit values are encoded into 1 word instructions 16 bit values are encoded into 2 word instructions The length of the immediate value encoded in an instruction depends on the type of instruction used Table 5 1 lists the C54x DSP instructions that can encode immediate values in their instruction word s The table also gives the bit value that can be encoded in the instruction Table 5 1 Instructions That Allow Immediate Addressing 3 and 5 Bit 8 Bit 9 Bit Constants Constant Constant 16 Bit Constant LD FRAME LD ADD ORM LD ADDM RPT RPT AND RPTZ ANDM ST BITF STM CMPM SUB LD XOR MAC XORM OR The syntax for immediate addressing uses a number sign immediately preceding the value or symbol to indicate that it is an immediate value For example to load accumulator A with the value 80 in hexadecimal you would write LD 80h A Figure 5 1 uses the RPT instruction to show how a short immediate K value is encoded in instructions that use immediate addressing The
248. cies between instructions that update and use SP in noncompiler mode CPL 0 aT Note You are responsible for rearranging instructions or inserting NOPs if necessary to accommodate SP latencies 7 54 Pipeline SPRU131G Table 7 11 a Latencies based on third instruction category Pipeline Latencies Latencies for SP in Noncompiler Mode CPL 0 Third Instruction Second Instruction Category Category Il STM lk SP ot 0 Si lk SP MVDK Smem SP ot 0 MVMD MMR SP MVKD dmad SP 1 0 MVDM_ dmad SP MVPD pmad SP MVDD Xmen spind 1t ot POPM SP POPD SP Store type instructions see Table 7 5 2 1 b Categories for the third instruction Category Category Il PSHM MMR PSHM MMR PSHD Smem Without a long offset PSHD Smem With a long offset POPM MMR modifier POPM MMR modifier PSHM Smem PSHM Smem CALL D address CALA D address CC D address FCALA D FCALL D FRET D FRETE D INTR k RC D RET D RETE D RETF D MVMM SP MMR FRAME k TRAP n Legend SP Destination operand pointing to the stack pointer in either direct or indirect addressing modes MMR Any memory mapped register except SP spind Destination operand pointing to the stack pointer using indirect addressing mode t Add one more cycle of latency if the first instruction meets the DAGEN register conflict criteria See section 7 5 3 Rules to Determine DAGEN Register Access Conflicts for more information Notes 1 Any instruction that does not fit in e
249. conditions and modes PMST contains memory setup status and control information Because these registers are memory mapped they can be stored into and loaded from data memory the status of the processor can be saved and restored for subroutines and interrupt service routines ISRs 4 1 1 Status Registers STO and ST1 The individual bits of the STO and ST1 registers can be set or cleared with the SSBX and RSBxX instructions For example the sign extension mode is set with SSBX 1 SXM or reset with RSBX 1 SXM The ARP DP and ASM bit fields can be loaded using the LD instruction with a short immediate operand The ASM and DP fields can be also loaded with data memory values by using the LD instruction The STO bits are shown in Figure 4 1 and described in Table 4 1 The ST1 bits are shown in Figure 4 2 and described in Table 4 2 on page 4 4 Figure 4 1 Status Register 0 STO Diagram 15 13 12 11 10 9 8 0 ee Te ow ore Table 4 1 Status Register 0 STO Bit Summary Reset Bit Name Value Function 15 13 ARP 0 Auxiliary register pointer This 3 bit field selects the auxiliary register to use in the com patibility mode of indirect single operand addressing see section 5 5 Indirect Ad dressing page 5 10 ARP must always be set to zero when the DSP is in standard mode CMPT 0 4 2 Central Processing Unit SPRU131G CPU Status and Control Registers Table 4 1 Status Register 0 STO Bit Summary Continued
250. consider in the emulation design 1 The TCK to DTMS DTDO path called tpd TCK DTMS The TCK to DTDI path called tpa TCK DTDI A 18 Design Considerations for Using XDS510 Emulator SPRU131G Emulation Design Considerations Of the following two cases the worst case path delay is calculated to deter mine the maximum system test clock frequency Example A 3 Key Timing for a Single Processor System Without Buffering SPL Perce taiotcKHmin tsu srs t x pa TCK DTMS ttc Kfactor 31 ns 2ns 10 ns 0 4 107 5 ns or 9 3 MHz ts 100 ta DTCKLmax su oro bie Kfactor 15 ns 16 ns 7 ns 0 4 tpa TCK DTDI 9 5ns or 10 5 MHz In this case the TCK to DTMS DTDL path is the limiting factor Example A 4 Key Timing for a Single or Multiorocessor System With Buffered Input SPRU131G and Output SPL te DTMSmax DTCKHmin tsu TTMS teutskew tod TCK TDMS ttcktactor 31 ns 2ns 10 ns 1 35 ns 0 4 110 9 ns or 9 0 MHz Il te TTDO ta DTCKLmax tsu DTDLmin ta T tpa TCK DTDI tTCkfactor _ 15ns 15ns 7ns 10 ns 0 4 120 ns or 8 3 MHz In this case the TCK to DTDI path is the limiting factor Design Considerations for Using XDS510 Emulator A 19 Emulation Design Considerations A 8 3 Using Emulation Pins A 20 The EMU0 1 pins of TI devices are bidirectional 3 state output pins W
251. continuity a branch call return or software interrupt a 6 10 Program Memory Addressing SPRU131G Calls Table 6 8 shows the conditional call instruction and the number of cycles needed to execute this instruction Because there is a wait cycle for conditions to become stable the conditional call instruction CC D requires one more cycle than the unconditional one Table 6 8 Conditional Call Instruction 6 4 3 Far Calls Number of Cycles Condition met Not met Instruction Description Nondelayed Delayed CC D Places the return address on the 5 3 3 3 stack and then loads the PC with the address specified by the instruction if the condition specified by the instruc tion is met To allow calls to extended memory there are two far call instructions J The FCALL instruction pushes XPC onto the stack pushes PC onto the stack and branches to the extended memory address specified by the the instruction J The FCALA pushes XPC onto the stack pushes PC onto the stack and branches to the extended memory address specified in the designated accumulator Table 6 9 shows the far call instructions nondelayed and delayed and the number of cycles needed to execute these instructions Note that delayed instructions need two cycles fewer than the corresponding nondelayed instructions Table 6 9 Far Call Instructions SPRU131G Number of Cycles Instruction Description Nondelayed Delayed FCALL D Places XPC an
252. control logic a zero detector a rounder 2s comple ment overflow saturation logic and a 16 bit temporary storage register T The multiplier has two inputs one input is selected from T a data memory operand or accumulator A the other is selected from program memory data memory accumulator A or an immediate value The fast on chip multiplier allows the C54x DSP to perform operations efficiently such as convolution correlation and filtering In addition the multi plier and ALU together execute multiply accumulate MAC computations and ALU operations in parallel in a single instruction cycle This function is used in determining the Euclidian distance and in implementing symmetrical and LMS filters which are required for complex DSP algorithms See section 4 5 Multiplier Adder Unit on page 4 19 for more details about the multiplier adder unit Architectural Overview 2 9 Central Processing Unit CPU Data Addressing 2 3 5 Compare Select and Store Unit CSSU 2 4 Data Addressing 2 10 The compare select and store unit CSSU performs maximum comparisons between the accumulator s high and low word allows both the test control flag bit TC in status register STO and the transition register TRN to keep their transition histories and selects the larger word in the accumulator to store into data memory The CSSU also accelerates Viterbi type butterfly computations with optimized on chip hardware See section 4 6
253. control register TCR The 16 bit memory mapped timer control register TCR contains the control and status bits of the timer The TCR bit fields are shown in Figure 8 2 and described in Table 8 14 SPRU131G On Chip Peripherals 8 21 Timer Figure 8 2 Timer Control Register TCR Diagram 15 12 11 10 9 6 5 4 3 0 Free psc rss Toor Table 8 14 Timer Control Register TCR Bit Summary Reset Bit Name Value Function 15 12 Reserved Reserved always read as 0 11 Soft 0 Used in conjunction with the Free bit to determine the state of the timer when a breakpoint is encountered in the HLL debugger When the Free bit is cleared the Soft bit selects the timer mode Soft 0 The timer stops immediately Soft 1 The timer stops when the counter decrements to 0 10 Free 0 Used in conjunction with the Soft bit to determine the state of the timer when a breakpoint is encountered in the HLL debugger When the Free bit is cleared the Soft bit selects the timer mode Free 0 The Soft bit selects the timer mode Free 1 The timer runs free regardless of the Soft bit 9 6 PSC Timer prescaler counter Specifies the count for the on chip timer When PSC is decremented past 0 or the timer is reset PSC is loaded with the contents of TDDR and the TIM is decremented 5 TRB Timer reload Resets the on chip timer When TRB is set the TIM is loaded with the value in the PRD and the PSC is loaded with the value in TDDR TRB is always read
254. ct the nearest TI Field Sales Office for more information on procedures leadtimes and cost associated with the ROM protect feature Submitting ROM Codes to TI C 3 Appendix D Glossary A See accumulator A ABU See autobuffering unit ABUC ABU control register A register that controls the operation of the autobuffering unit accumulator A register that stores the results of an operation and provides an input for subsequent arithmetic logic unit ALU operations accumulator A 40 bit register that stores the result of an operation and provides an input for subsequent arithmetic logic unit ALU operations accumulator B 40 bit registers that stores the result of an operation and provides an input for subsequent arithmetic logic unit ALU operations accumulator shift mode field ASM A 5 bit field in status register 1 ST1 that specifies a shift value from 16 to 15 used to shift an accumulator value when executing certain instructions such as instructions with parallel loads and stores adder A unit that adds or subtracts two numbers address The location of a word in memory address bus A group of connections used to route addresses The C54x CPU has four 16 bit address busses CAB DAB EAB and PAB addressing mode The method by which an instruction calculates the location of an object in memory address visibility mode AVIS A bit in processor mode status register PMST that determines whether or not
255. d Additionally the external clock input to the C54x CPU can be stopped for the lowest power consumption configuration Under these conditions random accesses can still be made without having to restart the external clock for each access and wait for its lockup time if the C54x on chip PLL is used The external clock need only be restarted before taking the C54x CPU out of IDLE2 3 The host cannot access HPI RAM in SAM when the C54x CPU is in IDLE2 3 because CPU clocks are required for access in this mode of operation There fore if the host requires access to the HPI RAM while the C54x CPU is in IDLE2 3 the C54x CPU must change HPI mode to HOM before entering IDLE2 3 When the HPI is in HOM the C54x CPU can access HPIC to toggle the SMOD bit or send an interrupt to the host but cannot access the HPI RAM block a C54x CPU access to the HPI RAM is disregarded in HOM In order for the C54x CPU to again access the HPI RAM block HPI mode must be changed to SAM after exiting IDLE2 3 To select HOM a 0 must be written to the SMOD bit in HPIC To select SAM a 1 must be written to SMOD When changing between HOM and SAM two considerations must be met for proper operation First the instruction immedi ately following the one that changes from SAM to HOM must not be an IDLE 2 or IDLE 3 This is because in this case due to the C54x CPU pipeline and delays in the SAM to HOM mode switch the IDLE2 3 takes effect before the mode switch occurs causi
256. d b However if RS is asserted while HOLD and HOLDA are active the CPU is reset and the data bus address bus and control signals remain in high impedance as shown in Figure 10 24 c and d If HOLD is deasserted while RS is active HOLDA is deasserted normally in response and the address data and control lines are driven according to the active reset state as shown in Figure 10 24 a and d However if RS is deasserted while HOLD and HOLDA are active the operation of the device depends on the state of the MP MC pin If MP MC is high the CPU begins fetching the reset vector when the hold mode is exited If MP MC is low the CPU fetches the reset vector internally and continues processing unless it requires an external access before the hold mode is exited Figure 10 24 b and c show examples of the case in which RS is de asserted while HOLD and HOLDA are active External Bus Operation 10 29 Hold Mode Figure 10 23 HOLD and HOLDA Minimum Timing for HM 0 aour J SNS NS NS NS NS NS NS NS NS NS NS NINN me a E E eer m a O a a a address e a Bal SS Se ee I Ia I a aa ee ee et sO OC ZCX or IS wm 7 IAM N sta TN se mN Bank Switching Notes 1 The timing shows the hold mode when HM 0 When HM 1 another cycle is required before HOLDA becomes inactive 2 The first cycle after releasing the hold mode is a cycle of bank swi
257. d ARX R registers the bottom of circular buffer address BBA and the top of circular buffer address TBA SPRU131G Buffered Serial Port BSP Interface Figure 9 26 Circular Addressing Registers TBA ARH 0 0 Top of Buffer FIRST HALF ARH ARL gt Current location in buffer ARH BKL gt gt 1 gt Second Half Start SECOND HALF BKH BKL Block size register BKX R BBA Bottom of Buffer 1 The minimum block size for an ABU buffer is two the maximum block size is 2047 and any buffer of 2047 to 1024 words must start at a relative address of 0x0000 with respect to the base address of the 2K block of ABU memory If either of the address registers AXR or ARR is loaded with a value specifying a location that is outside the range of the currently allocated buffer size as defined by BKX R improper operation may result Subsequent memory accesses will be performed starting at the location specified despite the fact that they will be to locations which are outside the range of the desired buffer and the ARX R will be incremented with each access until its contents reach the next permitted buffer start address Any further accesses are then per formed using the correct circular buffering algorithm with the new ARX R contents as the updated buffer start address It should be noted that any accesses performed with improperly loaded ARX Rs may therefore unexpect edly corr
258. d Instruction to Update ARP in Compatibility Mode CMPT 1 To do this Use this instruction Load ARP field of STO register LD k ARP Table 7 16 lists the latencies between instructions that update and use ARP or CMPT PA ATN Notes 1 You are responsible for rearranging instructions or inserting NOPs if necessary to accommodate latencies 2 In compatibility mode CMPT 1 ARP is automatically updated by instructions that use indirect addressing mode There is no pipeline conflict associated with such an ARP update 3 ARP must always be cleared to 0 when the DSP is in standard mode CMPT 0 At reset both ARP and CMPT are cleared to 0 automatically SPRU131G Pipeline 7 61 Pipeline Latencies Table 7 16 Latencies for ARP in Compatibility Mode CMPT 1 and CMPT bit a Latencies based on secona instruction category Second Instruction First Instruction Category STM lk status 2 ST lk status MVDK Smem status 2 MVMD MMR status MVKD dmad status 3 MVDM_ dmad status MVPD pmad status MVPD pmad status 3 POPM status 3 POPD status DELAY status LTD status MVDD status Store type instruction see Table 7 5 3 SSBX statbit 3 RSBX statbit b Categories for the second instruction Category Category Il MVKD dmad auxind MVKD dmad auxind MVDM dmad auxind With a long offset MVDM dmad auxind MVPD dmad auxind modifier MVPD pmad auxind MACP dmad auxind pmad src MACP au
259. d PC on the stack and 4 2 then loads XPC and PC with the address specified by the instruction FCALA D Places XPC and PC on the stack and 6 4 then loads XPC and PC with the address specified in the designated accumulator Program Memory Addressing 6 11 Returns 6 5 Returns Return instructions provide a way to resume processing of a sequence of instructions that was broken by a call to another function or an interrupt service routine When the called function or interrupt service routine has completed its execution it is necessary to resume processing at the point immediately following the call or the point at which the interrupt occurred Return instruc tions accomplish this by popping the top value of the stack which contains the address of the next instruction to be executed into the program counter PC The C54x DSP performs both unconditional and conditional returns and both of these types can be either nondelayed or delayed 6 5 1 Unconditional Returns An unconditional return is always executed when it is encountered When the return is executed PC is loaded with the return address from the stack and execution resumes at the instruction following the instruction that called the function or at the point at which the interrupt occurred By the time the unconditional return instruction reaches the execute phase of the pipeline the next two instruction words have already been fetched How these two instruction words are handl
260. data memory available on various C54x devices For device specific on chip data memory configura tions see the device data sheet Table 3 2 On Chip Data Memory Available on the TMS320C54x Devices Device Program Data ROM DARAM SARAM C541 8K 5K C542 10K z C543 10K C545 16K 6K C546 16K 6K C548 8K 24K C549 16K 8K 24K C5402 4K 16K C5410 16K 8K 56K C5420 32K 168K Accesses to the RAM and the data ROM when it is enabled are made when addresses fall within the bounds of the corresponding on chip memories When the data address generation logic DAGEN generates an address out side of the bounds of on chip memory the device automatically generates an external access For more information about data addresses generation see Chapter 5 Data Addressing 3 3 1 Data Memory Configurability Data memory can reside both on chip and off chip The on chip DARAM is mapped into data memory space For some C54x devices you can map a portion of the on chip ROM the amount shown in Table 3 2 into data space by setting the DROM bit located in the PMST register see section 4 1 CPU Status and Control Registers on page 4 2 This portion of on chip ROM is enabled both in the data space DROM bit and in the program space MP MC bit allowing an instruction to use the ROM area as a data ROM residing in data space At reset the processor clears the DROM bit to 0 3 22 Memory SPRU131G Data Memory The data ROM is accessed in a
261. data space 8000 FFFFh 8 6 Data 1 Data space The field value 0 7 corresponds to the number of wait states for data space 0000 7FFFh 5 3 Program 1 Program space The field value 0 7 corresponds to the number of wait states for program space 8000 FFFFh 2 0 Program 1 Program space The field value 0 7 corresponds to the number of wait states for program space 0000 7FFFh When SWWSM is set to 1 the wait states are multiplied by two extending the maximum number of wait states from 7 to 14 The C549 C5402 C5410 and C5420 have an extra bit software wait state multiplier SWSM that resides in SWCR Figure 10 3 which is memory mapped to address 002Bh in data space Figure 10 3 Software Wait State Control Register SWCR Diagram 15 1 0 xsi IE 10 6 External Bus Operation SPRU131G External Bus Control Table 10 3 C548 C549 C5402 C5410 C5420 Software Wait State Register SWWSR Bit Summary Bit Name 15 XPA 14 12 I O 11 9 Data 8 6 Data 5 3 Program 2 0 Program SPRU131G Reset Value Function 0 Extended program address control Selects the address ranges selected by the program fields l I O space The field value 0 7 corresponds to the number of wait states for I O space 0000 FFFFh 1 Data space The field value 0 7 corresponds to the number of wait states for data space 8000 FFFFh 1 Data space The field value 0 7 corresponds to the number of wait states for data space 0000 7FF
262. dder level The SQUR instruction squares a data memory value or the contents of accumulator A 4 5 3 MAC and MAS Saturation Upon Multiplication SPRU131G When saturate on multiply is set SMUL 1 the MAC instruction is equivalent to MPY ADD when OVM 1 The effect is that the multiplication 8000h x 8000h is saturated to 7FFF FFFFh in fractional mode before performing the subsequent addition MAC or subtraction MAS When saturate on multiply is not set SMUL 0 only the end results of MAC and MAS are saturated When OVM 1 and FRCT 1 the SMUL bit in PMST determines whether or not the result of a multiplication is saturated before the accumulation is performed in MAC and MAS instructions This feature allows the MAC and MAS operations to be consistent with the MAC and MAS basic operation defined in ETSI GSM specifications GSM specifications 6 06 6 10 and 6 53 Central Processing Unit 4 23 Compare Select and Store Unit CSSU 4 6 Compare Select and Store Unit CSSU The compare select and store unit CSSU is an application specific hard ware unit dedicated to add compare select ACS operations of the Viterbi operator Figure 4 9 shows the CSSU which is used with the ALU to perform fast ACS operations Figure 4 9 Compare Select and Store Unit CSSU From accumulator A From accumulator B By Avy mx From barrel shifter Sy COMP MSW LSW select TRN 16 y EB15 EBO
263. ddress _ When CPL 1 the dma field is added positive offset to SP to form the 16 bit data memory address The syntax for direct addressing uses a symbol or anumber to specify the off set value For example to add the contents of the memory location SAMPLE to accumulator B provided that the correct base address is in DP CPL 0 or SP CPL 1 you would write ADD SAMPLE B The lower seven bits of the address of SAMPLE are stored in the instruction word Figure 5 3 shows the opcode format for instructions that use direct addressing Table 5 2 describes the bits of the direct addressing instruction Figure 5 4 illustrates how the 16 bit data address is formed Data Addressing 5 7 Direct Addressing Figure 5 3 Direct Addressing Instruction Format 15 8 7 6 0 CO o e Table 5 2 Direct Addressing Instruction Bit Summary Bit Name Function 15 8 Opcode This eight bit field contains the operation code for the instruction 7 0 the addressing mode used by the instruction is the direct addressing mode 6 0 dma This seven bit field contains the data memory address offset for the instruction Figure 5 4 Direct Addressing Block Diagram 7 LSBs from IR dma SP 16 o DAB 16 read CPL cpL DAGEN 0 EA DP offset IR EAB 16 write 1 EA SP offset IR or CAB 16 32 bit read Data bus DB 16 Data bus EB 16 Legend EA Effective ad
264. ddress auto increment See Table 8 12 on page 8 18 DMA sub bank data register See Table 8 12 on page 8 18 Clock mode register Reserved SPRU131G Table 8 11 McBSPO Address Name Hex SPCR10 39 SPCR20 39 RCR10 39 RCR20 39 XCR10 39 XCR20 39 SRGR10 39 SRGR20 39 MCR10 39 MCR20 39 RCERAO 39 RCERBO 39 XCERAO 39 XCERBO 39 PCRO 39 SPRU131G Peripheral Memory Mapped Registers C5402 C5410 C5420 McBSP Subadaressed Registers McBSP1 Address Name Hex SPCR11 49 SPCR21 49 RCR11 49 RCR21 49 XCR11 49 XCR21 49 SRGR11 49 SRGR21 49 MCR11 49 MCR21 49 RCERA1 49 RCERB1 49 XCERA1 49 XCERB1 49 PCR1 49 McBSP2 c Sub Address address Name Hex Hex SPCR12 35 00 SPCR22 35 01 RCR12 35 02 RCR22 35 03 XCR12 35 04 XCR22 35 05 SRGR12 35 06 SRGR22 35 07 MCR12 35 08 MCR22 35 09 RCERA2 35 OA RCERA2 35 0B XCERA2 35 oC XCERA2 35 oD PCR2 35 OE Description Serial port control register 1 Serial port control register 2 Receive control register 1 Receive control register 2 Transmit control register 1 Transmit control register 2 Sample rate generator register 1 Sample rate generator register 2 Multichannel register 1 Multichannel register 2 Receive channel enable register partition A Receive channel enable register partition B Transmit channel enable register partition A Transmit channel enable register partition B Pin control register On Chip Peripherals 8 17 Peripheral Memory Ma
265. de takes effect after 6 CLKIN cycles plus 3 5 PLL cycles When the switch to PLL mode is completed the PLLSTATUS bit in CLKMD is read as 1 Note that during the PLL lockup period the C54x DSP continues operating in DIV mode The following code can be used to switch from DIV mode to PLL x 3 mode on the C549 with a CLKIN frequency of 13 MHz and PLLCOUNT 18 decimal which includes some safety margin STM 0010 0000 1001 0111b CLKMD 8 32 On Chip Peripherals SPRU131G Clock Generator Switching Clock Mode From PLL Mode to DIV Mode When switching from PLL mode to DIV mode the PLLCOUNT delay does not occur and the switch between the two modes takes place after a short transi tion delay The switch from PLL mode to DIV mode is also accomplished by loading CLKMD The PLLNDIV bit is cleared to 0 selecting DIV mode and the PLLMUL bits are set to select the desired frequency multiplier as shown in Table 8 19 on page 8 30 The switch to DIV mode takes effect in 6 CLKIN cycles plus 3 5 PLL cycles for all PLLMUL values except 1111b For a PLLMUL value of 1111b the switch to DIV mode takes effect in 12 CLKIN cycles plus 3 5 PLL cycles When the switch to DIV mode is completed the PLLSTATUS bit in CLKMD is read as 0 Example 8 1 shows a code sequence that can be used to switch from PLL x 3 mode to divide by 2 mode Note that the PLLSTATUS bit is polled to determine when the switch to DIV mode has taken effect and then the STM instructio
266. described in section 9 2 Serial Port Interface on page 9 4 except that some corresponding TDM registers are named differently The TDM receive register is TRCV and the TDM receive shift register is TRSR Data is transmitted on the bidirectional TDAT line Note that in Figure 9 31 b the device TDX and TDR pins are tied together externally to form the TDAT line Also note that only one device can drive the data and address line TDAT and TADD in a particular slot All other devices TDAT and TADD outputs should be in the high impedance state during that slot which is accomplished through proper programming of the TDM port control registers this is described in detail later in this section Meanwhile in that particular slot all the devices including the one driving that slot sample the TDAT and TADD lines to determine if the current transmission represents valid data to be read by any one of the devices on the bus this is also discussed in detail later in this section When a device recognizes an address to which it is supposed to respond a valid TDM read then occurs the value is transferred from TRSR to TRCV A receive interrupt TRINT is generated which indicates that TRCV has valid receive data and can be read All TDM port operations are synchronized by the TCLK and TFRM signals Each of them are generated by only one device typically the same device referred to as the TCLK and TFRM source s The word master is not used here
267. deza TMS320C54x DSP Reference Set Volume 1 CPU and Peripherals Literature Number SPRU131G March 2001 ki TEXAS INSTRUMENTS O een IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using TI components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards TI assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either ex
268. disabling capability that can be used to automati cally terminate autobuffering when either the half of buffer or bottom of buffer boundary is crossed These features are described in detail later in this section Serial Ports 9 41 Buffered Serial Port BSP Interface Figure 9 24 ABU Block Diagram C54x memory interface is Autobuffering unit module DATA BUS C54x CPU interface XRDY Control BCLKX BDXR BSPCE BFSX one BDX Serial port control logic Interrupt BDR WRINT control BCLKR BFSR BDRR BSPC Interrupt logic Serial port interface module Burst or continuous mode as described in section 9 2 Serial Port Interface can be used in conjunction with the autobuffering capability Note that due to the nature of autobuffering mode however if burst mode with internal frame sync is selected this will effectively result in continuous transmission with FSX generated by the BSP at the start of each transmission 9 42 Serial Ports SPRU131G Buffered Serial Port BSP Interface The internal C54x DSP memory used for autobuffering consists of a 2K word block of dual access memory that can be configured as data program or both as with other dual access memory blocks This memory can also be used by the CPU as general purpose storage however this is the only memory block in which autobuffering can occur Since the BSP is implemented on several different C54x devices the ac
269. dmad auxreg dmad auxreg pmad auxreg auxreg auxreg auxreg auxreg Xmem auxreg Store type instructions see Table 7 5 b Categories for the third instruction Category MVMM auxreg MMR CMPR CC auxreg MVKD dmad auxind MVDM dmad auxind MVPD pmad auxind MACP auxind pmad src MACD auxind pmad src With a long offset modifier Third Instruction Category ot ot it Category Il MVKD dmad auxind MVDM dmad auxind MVPD pmad auxind MACP auxind pmad src MACD auxind pmad src Category Il 0 ot Without a long offset modifier ADD auxind shift src dst ADD auxind shift src dst LD auxind shift dst With an extended LD auxind shift dst With an extended STH src shift auxind shiftf and a long STH sre shift auxind shift and without STL src shift auxind offset modifier STL src shift auxind a long offset SUB auxind shift src dst SUB auxind shift src dst modifier BANZ D auxind With one operand using indirect ad dressing mode with or without a long offset modifier 1 With or without along FIRS offset modifier Instructions not listed here that use ARx in indirect addressing mode t Add one more cycle of latency if the first instruction meets the DAGEN register conflict criteria See section 7 5 3 Rules to Deter mine DAGEN Register Access Conflicts for more information The destination operand auxreg must point at ARO AR7 in either direct or indirect ad
270. dress IR Instruction register 5 8 Data Addressing SPRU131G Direct Addressing 5 4 1 DP Referenced Direct Addressing In DP referenced direct addressing the 7 bit dma in the instruction register is concatenated with the 9 bit DP to form the address Figure 5 5 shows how the two values make up the resulting address Figure 5 5 DP Referenced Direct Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value from the DP Value from the IR dma DP referenced direct addressing divides memory into 512 pages because the DP s range is from 0 to 511 29 1 Each page has 128 addressable locations because the dma ranges from 0 to 127 27 1 In other words the DP points to one of 512 possible 128 word data memory pages the dma points to the specific location within that page The only differ ence between an access to location 0 on page 1 and to location 0 on page 2 is the value of the DP The DP is loaded by the LD instruction 5 4 2 SP Referenced Direct Addressing In SP referenced direct addressing the 7 bit dma in the instruction register is added as a positive offset to the SP to form the effective 16 bit data memory address Figure 5 6 shows how the two values combine to form the resulting address Figure 5 6 SP Referenced Direct Address SPRU131G 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Value from the SP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 Value from the IR dma 15 14 13 12 11 10 9 8 7 6 5 4
271. dressing mode The operand auxind must use indirect addressing mode T Shift value between 16 and 15 Notes 1 Any instruction that does not fit in either of the two categories has zero latency 2 The first instruction can be any C54x DSP instruction 7 46 Pipeline SPRU131G Table 7 8 Latencies for Accessing BK a Latencies based on third instruction category Second Instruction STM lk bkreg Sil lk bkreg MVDK MVMD MVKD MVDM MVPD POPM bkreg POPD bkreg DELAY bkreg LTD bkreg MVDD Xmenm bkreg Smem bkreg MMR bkreg dmad bkreg dmad bkreg pmad bkreg Third Instruction Category 1t it at Pipeline Latencies Category Il ot ot 1t Store type instructions see Table 7 5 b Categories for the third instruction Category MVKD dmad circind MVDM dmad circind MVPD pmad circind MACP circind pmad src MACD circind pmad src ADD circind shift src dst LD circind shift dst STH sre shift circind STL src shift circind SUB circind shift src dst BANZ D circind Instructions not listed here that use BK in circular addressing mode With a long offset modifier With an extended shift and a long offset modifier Category Il MVKD dmad circind MVDM dmad circind MVPD pmad circind MACP circind pmad src MACD circind pmad src ADD LD circind shift dst STH src shift circind STL src shift circind SUB circind shift src dst With
272. driven low or high under software control BIO and XF are often used for handshaking functions In addition to the above described pins other GPIO pins are available on selected devices Some GPIO pins are multiplexed with the McBSP HPI pin functions and some GPIO pins are dedicated The multiplexed pins can be used for a GPIO function or a McBSP HPI function under software control However the dedicated GPIO pins are always used for general purpose I O See section 8 3 General Purpose I O on page 8 20 for more details about BIO and XF 2 12 Architectural Overview SPRU131G On Chip Peripherals 2 7 2 Software Programmable Wait State Generator The software programmable wait state generator extends external bus cycles up to seven machine cycles 14 machine cycles in the C549 C5402 C5410 and C5420 to interface with slower off chip memory and I O devices The soft ware wait state generator is incorporated without any external hardware For off chip memory accesses from zero to seven wait states can be specified within the software wait state register SWWSR for each 32K word block of program and data memory and for the 64K word block of I O space See section 10 3 1 Wait State Generator on page 10 5 for more details 2 7 3 Programmable Bank Switching Logic The programmable bank switching logic can automatically insert one cycle when an access crosses memory bank boundaries inside program memory or data memory space One cycle
273. e 7 58 Pipeline Smem TS dst Smem TS src Without a long offset modifier Smem TS src src dst Xmem Lmem dst Lmem dst Lmem dst T Destination operand pointing at T in either direct or indirect addressing modes Ting Destination operand pointing at T using indirect addressing mode Any instruction that does not fit in Category I has zero latency SPRU131G Pipeline Latencies Example 7 39 T Load With No Latency a LD AR3 T This T update does not require LD AR5 1TS A any latency b STM 100h T This T update does not require LD ARS TS A any latency Example 7 40 T Load With a 1 Cycle Latency a POPM T This instruction requires a on NOP cycle latency BELT AR5 b EXP A This instruction requires a on NOP cycle latency NORM A SPRU131G Pipeline 7 59 Pipeline Latencies 7 5 7 Latencies for Accessing Status Registers The following status register fields and bits are affected by latency E m E E E m L ARP auxiliary register pointer CMPT compatibility mode bit CPL compiler mode bit DP data page pointer SXM sign extension mode bit ASM accumulator shift mode field BRAF block repeat activity flag 7 5 7 1 ST1 and a Repeat Block Loop Some instructions write to ST1 in the execute stage of the pipeline If any of these instructions is immediately followed by a RPTB D instructi
274. e The Hold mode is another power down mode It enables you to put the address data and control lines into the high impedance state Depending on the value of the HM bit you can also use this mode to halt the CPU This power down mode is initiated by the HOLD signal The effect of HOLD depends on the value of HM If HM 1 the CPU stops executing and address data and control lines go into the high impedance state for further power reduction If HM 0 the address data and control signals are put into the high impedance state but the CPU continues to execute internally You can use HM 0 with the HOLD signal when your system does not require external memory accesses The C54x DSP continues to operate normally unless an off chip access is required by an instruction then the processor halts until HOLD is released This mode does not stop the operation of on chip peripherals such as timers and serial ports they continue to operate regardless of the HOLD level or the condition of the HM bit This mode is terminated when HOLD becomes inactive 6 11 5 Other Power Down Capabilities The C54x DSP has two other functions that affect the power down operation external bus off and CLKOUT off J External bus off allows the C54x DSP to disable the internal clock of external interfaces thus placing the interface into a lower power consumption mode The external interface clock is disabled by setting bit 0 of the bank switch
275. e Consumer Medical Development Support O O O O O O O O O O O SPRU131G Technical Articles In the following list references appear in alphabetical order according to author The documents contain beneficial information regarding designs op erations and applications for signal processing systems all of the documents provide additional references Texas Instruments strongly suggests that you refer to these publications General Purpose DSP 1 Chassaing R Horning D W Digital Signal Processing with Fixed and Floating Point Processors COED USA Volume 1 Number 1 pages 1 4 March 1991 Defatta David J Joseph G Lucas and William S Hodgkiss Digital Sig nal Processing A System Design Approach New York John Wiley 1988 Erskine C and S Magar Architecture and Applications of a Second Generation Digital Signal Processor Proceedings of IEEE International Conference on Acoustics Speech and Signal Processing USA 1985 Essig D C Erskine E Caudel and S Magar A Second Generation Digital Signal Processor EEE Journal of Solid State Circuits USA Vol ume SC 21 Number 1 pages 86 91 February 1986 Frantz G K Lin J Reimer and J Bradley The Texas Instruments TMS320C25 Digital Signal Microcomputer EEE Microelectronics USA Volume 6 Number 6 pages 10 28 December 1986 Gass W R Tarrant T Richard B Pawate M Gammel P Rajasekaran R Wiggins and C
276. e X Any value can be written Figure 8 11 HPIC Diagram TMS320C54x DSP Reads From HPIC 15 4 3 2 1 0 pn soo _ Note X Unknown value is read Figure 8 12 HPIC Diagram TMS320C54x DSP Writes to HPIC 15 4 3 2 1 0 Note X Any value can be written Because the C54x DSP can write to the SMOD and HINT bits and these bits are read twice on the host interface side the first and second byte reads by the host may yield different data if the C54x DSP changes the state of one or both of these bits in between the two read operations The characteristics of host and C54x HPIC read write cycles are summarized in Table 8 24 Table 8 24 HPIC Host TMS320C54x DSP Read Write Characteristics Device Read Write Host 2 bytes 2 bytes Both bytes must be equal C54x DSP 16 bits 16 bits 8 6 3 Host Read Write Access to HPI The host begins HPI accesses by performing the external interface portion of the cycle that is initializing first the HPIC register then the HPIA register and then writing data to or reading data from the HPID register Writing to HPIA or HPID initiates an internal cycle that transfers the desired data between the HPID and the dedicated internal HPI memory Because this process requires several C54x DSP cycles each time an HPI access is made data written to the HPID is not written to the HPI memory until after the host access cycle and the data read from the HPID is the data from the previous cycle Th
277. e 5 Cycles 6 and 7 Cycles 8 and 9 Cycle 10 PAB is loaded with the address of the call instruction Two words of the call instruction are fetched SP is decremented represented by SP because the return address is placed on the stack The instruction i3 is fetched however it is not allowed to move past the decode stage The write address bus EAB is loaded with SP s contents and the on chip return register RTN is loaded with the return address a3 After the second word of the call instruction b1 is decoded PAB is loaded with the new value in cycle 5 shown in row j1 The RTN contents are written to the stack using EB in cycle 6 The instruction j1 at address b1 is fetched in cycle 6 The two word call instruction enters the execution stage of the pipeline in cycles 6 and 7 These cycles are consumed by the call instruction because the next two instructions are not allowed to com plete their execution j1 completes execution Pipeline 7 9 Pipeline Operation Example 7 5 shows the pipeline behavior for a delayed call instruction Example 7 5 Delayed Call CALLD Instruction in the Pipeline Address Instruction al a2 CALLD b1 a3 i3 a4 i4 b1 ji 1 2 3 4 5 6 7 Prefetch Fetch Decode Access Read Execute PB RS EAB SP CALLD PAB a1 caup CALLD aog ios Prefetch Fetch Decode Access Read Execute bi PAB a2 PB b1 IR b1 b1 Prefetch Fetch Decode Access Read i3 PAB a3 PB i3 I
278. e 8 12 on page 8 18 Clock mode register Reserved SPRU131G Peripheral Memory Mapped Registers Table 8 9 C5410 Peripheral Memory Mapped Registers SPRU131G Address Hex 20 2i 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2F 30 31 32 33 34 35 36 37 3A 3F 38 39 Name DRR20 DRR10 DXR20 DXR10 TIM PRD TCR SWWSR BSCR SWCR HPIC DRR22 DRR12 DXR22 DXR12 SPSA2 SPSD2 SPSAO SPSDO Description McBSP0 data receive register 2 McBSPO data receive register 1 McBSPO data transmit register 2 McBSP0 data transmit register 1 Timer register Timer period counter Timer control register Reserved Software wait state register Bank switching control register Reserved Software wait state control register HPI control register Reserved McBSP2 data receive register 2 McBSP2 data receive register 1 McBSP2 data transmit register 2 McBSP2 data transmit register 1 McBSP2 serial port sub bank address register See Table 8 11 on page 8 17 McBSP2 serial port sub bank data register See Table 8 11 on page 8 17 Reserved Reserved McBSPO serial port sub bank address register See Table 8 11 on page 8 17 McBSPO serial port sub bank data register See Table 8 11 on page 8 17 On Chip Peripherals 8 13 Peripheral Memory Mapped Registers Table 8 9 C5410 Peripheral Memory Mapped Registers Continued Address Hex 40 41 42 43 44 47 48 49 4A 5
279. e HOLD input low with the HM status bit set to 1 The BSP like other peripherals timer standard serial port can take the CPU out of IDLE using the transmit interrupt BXINT or receive interrupt BRINT When in IDLE or HOLD mode the BSP continues to operate as is the case with the serial port When in IDLE2 3 unlike the serial port and other on chip peripherals which are stopped with this power down mode the BSP can still be operated In standard mode if the BSP is using external clock and frame sync while the device is in IDLE2 3 the port will continue to operate and a transmit interrupt BXINT or receive interrupt BRINT will take the device out of IDLE2 3 mode if INTM 0 before the device executes the IDLE 2 or IDLE 3 instruction With internal clock and or frame sync the BSP remains in IDLE2 3 until the CPU resumes operation In autobuffering mode if the BSP is using external clock and frame sync while the device is in IDLE2 3 a transmit receive event will cause the internal BSP clock to be turned on for the cycles required to perform the DXR or DRR to memory transfer The internal BSP clock is then turned off automatically as soon as the transfer is complete so the device will remain in IDLE2 3 The device is awakened from IDLE2 3 by the ABU transmit interrupt BXINT or receive interrupt BRINT when the transmit receive buffer has been halfway or entirely emptied or filled if INTM 0 before the device executes the IDL
280. e MP MC OVLY and DROM bits are located in the processor mode status register PMST For more details see section 4 1 CPU Status and Control Registers on page 4 2 Figure 3 1 through Figure 3 4 show the C54x device s data and program memory maps and how the maps are affected by the MP MC OVLY and DROM bits SPRU131G Memory Space Figure 3 1 Memory Maps for the C541 C541 Program Memory C541 Data Memory 0000h 0000h 13FFh External 0000h 0000h 005Fh Memory mapped registers 0000h 007Fh Reserved 0060h 007Fh Scratch pad DARAM 0080h 13FFh On chip DARAM 0080h 13FFh On chip DARAM 2000h 2000h 4000h 4000h 1400h 8FFFh External 6000h 6000h 1400h DFFFh_ External 8000h 8000h A000h A000h 9000h FF7Fh On chip ROM FF80h FFFFh Interrupt vectors Co00h internal Co00h 9000h FF7Fh External FF80h FFFFh Interrupt vectors external E000h E000h DROM 0 EOOOh FFFFh External DROM 1 E000h FEFFh On chip ROM FFOOh FFFFh Reserved FFFFh FFFFh SPRU131G Memory 3 3 Memory Space Figure 3 2 Memory Maps for the C542 and C543 C542 C543 Program Memory 0000h 0000h 27FFh External 0000h 007Fh Reserved 0080h 27FFh On chip DARAM 2000h 4000h 6000h 8000h 2800h EFFFh External A000h C000h a FOOOh F7FFh Reserved F800h FF7Fh On chip ROM FF80h FFFFh Interrupt vectors FOOOh FF7Fh External FF80h FFFFh Interrupt vectors FFFFh 3 4 Memory jadh C542 C5
281. e autoincrement is selected An HPI write access is illustrated in Table 8 28 In this example after the inter nal portion of the write is completed location 1002h of HPI RAM contains 1234h If a read of the same address follows this write the same data just writ ten in the data latches 1234h is read back Table 8 28 Write Access to HPI With Autoincrement Event HD HRAV HCNTL1 0 HBIL HPIC HPIA latchi latch2 Host writes data 1st byte 12 0 01 0 0000 1002 12 FE Host writes data 2nd byte 34 0 01 1 0000 1002 12 34 Internal HPI RAM write complete 1002 12 34 8 6 4 DSPINT and HINT Function Operation The host and the C54x DSP can interrupt each other using bits in the HPIC register This section presents more information about this process Host Device Using DSPINT to Interrupt the C54x DSP 8 50 A C54x DSP interrupt is generated when the host writes a 1 to the DSPINT bit in HPIC This interrupt can be used to wake up the C54x CPU from IDLE The host and the C54x DSP always read this bit as 0 A C54x DSP write has no effect Once a1 is written to DSPINT by the host a 0 need not be written before another interrupt can be generated and writing a 0 to this bit has no effect The host should not write a 1 to the DSPINT bit while writing to BOB or HINT or an unwanted C54x CPU interrupt is generated On the C54x DSP the host to C54x interrupt vector address is xx64h This in terrupt is located in bit 9 of the IMR IFR Since the C54x C
282. e block repeat is active BRAF is automatically set when an RPTB instruction is executed 14 CPL 0 Compiler mode CPL indicates which pointer is used in relative direct addressing CPL 0 The relative direct addressing mode using the data page pointer DP is selected CPL 1 The relative direct addressing mode using the stack pointer SP is selected 13 XF 1 XF status XF indicates the status of the external flag XF pin which is a general purpose output pin The SSBxX instruction can set XF and the RSBX instruction can reset XF 12 HM 0 Hold mode HM indicates whether the processor continues internal execution when acknowledging an active HOLD signal HM 0 The processor continues execution from internal program memory but places its external interface in the high impedance state HM 1 The processor halts internal execution 11 INTM 1 Interrupt mode INTM globally masks or enables all interrupts INTM 0 All unmasked interrupts are enabled INTM 1 All maskable interrupts are disabled The SSBX instruction sets INTM and the RSBX instruction resets INTM INTM is set to 1 by reset or when a maskable interrupt trap is taken INTR or external interrupts INTM is cleared to 0 when a RETE or RETF instruction return from interrupt is executed INTM does not affect the nonmaskable interrupts RS and NMI INTM cannot be set by memory write operations 10 0 Always read as 0 4 4 Central Processing Unit SPRU131G CPU Status
283. e calculations using the SQDST instruction and other parallel operations m m FIRS performs operations for symmetric FIR filters by using multiply accumulates MACs in parallel with additions LMS performs a MAC and a parallel add with rounding to efficiently update the coefficients in an FIR filter SQDST performs a MAC and a subtract in parallel to calculate Euclidean distance Central Processing Unit 4 15 Accumulators A and B FIRS multiplies accumulator A 382 16 with a program memory value addressed by a program memory address and adds the result to the value in accumulator B At the same time it adds the memory operands Xmem and Ymem shifts the result left 16 bits and loads this value into accumulator A In the LMS instruction accumulator B stores the interim results of the input sequence convolution and filter coefficients accumulator A updates the filter coefficients Accumulator A can also be used as an input for MAC which con tributes to single cycle execution of instructions with parallel operations The SQDST instruction computes the square of the distance between two vectors Accumulator A 32 16 is squared and the product is added to accu mulator B The result is stored in accumulator B At the same time Ymem is subtracted from Xmem and the difference is stored in accumulator A The value that is squared is the value of the accumulator before the subtraction Ymem Xmem is executed 4 16 Central
284. e following values O7FFh OFFFh 17FFh FFFFh The HPIA is a 16 bit register and all 16 bits can be written to or read from although with a 2K word HPI memory imple mentation only the 11 LSBs of the HPIA are required to address the HPI memory The HPIA increment and decrement affect all 16 bits of this register HPI Control Register Bits and Function Four bits control HPI operation These bits are BOB which selects first or se cond byte as most significant SMOD which selects host or shared access mode and DSPINT and HINT which can be used to generate C54x DSP and host interrupts respectively and are located in the HPI control register HPIC A detailed description of the HPIC bit functions is presented in Table 8 23 Table 8 23 HPI Control Register HPIC Bit Descriptions Bit Host Access C54x DSP Access Description BOB Red Write SMOD Read DSPINT Write SPRU131G If BOB 1 first byte is least significant If BOB 0 first byte is most significant BOB affects both data and address transfers Only the host can modify this bit and it is not visible to the C54x DSP BOB must be initialized before the first data or address register access Read Write If SMOD 1 shared access mode SAM is enabled the HPI memory can be accessed by the C54x DSP If SMOD 0 host only mode HOM is enabled the C54x DSP is denied access to the entire HPI RAM block SMOD 0 during reset SMOD 1 after reset SMOD can be modif
285. e interrupt 23 SINT24 24 Software interrupt 24 SINT25 28 Software interrupt 25 SINT26 2C Software interrupt 26 SINT27 30 Software interrupt 27 SINT28 34 Software interrupt 28 SINT29 38 Software interrupt 29 SINT30 3C Software interrupt 30 Program Memory Addressing 6 45 Interrupts Table 6 26 TMS320C5402 Interrupt Locations and Priorities Continued TRAP INTR Number K 16 17 18 19 20 21 22 23 24 25 26 27 28 29 120 127 Priority 3 o o N o Oa gt ls 16 Name INTO SINTO INT1 SINT1 INT2 SINT2 TINTO SINT3 BRINTO SINT4 BXINTO SINT5 DMACO SINT7 TINT1 DMAC1 SINT7 INT3 SINT8 HPINT SINT9 BRINT1 DMAC2 SINT10 BXINT1 DMAC3 SINT11 DMAC4 SINT12 DMAC5 SINT13 Reserved Location Hex 40 44 48 4C 50 54 58 5C 60 64 68 6C 70 74 78 7F Function External user interrupt 0 External user interrupt 1 External user interrupt 2 TimerO interrupt McBSP 0 receive interrupt McBSP 0 transmit interrupt DMA channel 0 interrupt Timer1 interrupt default or DMA channel 1 interrupt External user interrupt 3 HPI interrupt McBSP 1 receive interrupt default or DMA channel 2 interrupt McBSP 1 transmit interrupt default or DMA channel 3 interrupt DMA channel 4 interrupt DMA channel 5 interrupt Reserved Table 6 27 TMS320C5410 Interrupt Locations and Priorities TRAP INTR Number K 0 1 2 3 4 2 Priority Name R
286. e multiplier can be made faster For some application specific instructions FIRS SQDST ABDST and POLY the contents of accumulator A can be computed by the ALU and then input to the multiplier without any overhead 4 5 2 Multiply Accumulate MAC Instructions MAC instructions use the multiplier s computational bandwidth to simulta neously process two operands Multiple arithmetic operations can be performed in a single cycle by the multiplier adder unit In the MAC MAS and MACSU instructions with dual data memory operand addressing data can be transferred to the multiplier during each cycle via CB and DB and multiplied and added in a single cycle Data addresses for these operands are generated by ARAUO and ARAU1 the auxiliary register arithme tic units For information about ARAUO and ARAU1 see section 5 5 2 ARAU and Address Generation Operation on page 5 11 In the MACD and MACP instructions data can be transferred to the multiplier during each cycle via DB and PB DB retrieves data from data memory and PB retrieves coefficients from program memory When MACD and MACP are used with repeat instructions RPT and RPTZ they perform single cycle MAC operations with sequential access of data and coefficients Data addresses are generated by ARAUO and the program address register PAR The data memory address is updated by ARAUO according to a single data memory operand in the indirect addressing mode the program memory address is
287. e operand pointing to AG AH AL BG BH or BL using memory mapped direct or indirect addressing modes t Shift value between 16 and 15 Example 7 68 Updating Accumulator With a 1 Cycle Latency LD Smem NOP PSHM BH 1 B B is updated directly by this instruction Conflict occurs because next instruction tries to read B as a memory mapped register A one cycle latency is required Reads BH as a memory mapped register Ne Ne Ne Ne Ne Ne Ne Ne SPRU131G Pipeline 7 81 Pipeline Latencies Example 7 69 Updating Accumulator With No Latency a MAC K A A is updated directly by this instruction No latency is required since MAC is a 2 word instruction PSHM AL This instruction reads A as a memory mapped register b ADD Smem A A is updated directly by this instruction No latency is required since the next instruction uses a long offset modifier LD AL ASM This instruction reads A as a memory mapped register 7 82 Pipeline SPRU131G Chapter 8 On Chip Peripherals On chip peripherals for the TMS320C54x DSP are specific to the individual device This chapter along with Chapter 9 Seria Ports and Chapter 10 External Bus Operation describes some of the available on chip peripherals however your device may contain only a subset of them Enhanced peripherals available on specific C54x devices are not dis cu
288. e subaddressed register and postincrement the subaddress contained in DMSBAR Accesses to 56h update the subaddressed register without modifying DMSBAR SPRU131G On Chip Peripherals 8 19 General Purpose I O 8 3 General Purpose I O The C54x DSP offers general purpose I O through two dedicated pins that are software controlled The two dedicated pins are the branch control input pin BIO and the external flag output pin XF 8 3 1 Branch Control Input Pin BIO BIO can be used to monitor the status of peripheral devices It is especially useful as an alternative to using an interrupt when time critical loops must not be disturbed A branch can be conditionally executed dependent upon the state of the BIO input Of the instructions that use BIO the execute conditional ly XC instruction samples the condition of BIO during the decode phase of the pipeline all other conditional instructions branch call and return sample BIO during the read phase of the pipeline 8 3 2 External Flag Output Pin XF XF can be used to signal external devices The XF pin is controlled using soft ware Itis driven high by setting the XF bit in ST1 and is driven low by clearing the XF bit The set status register bit SSBX and reset status register bit RSBX instructions can be used to set and clear XF respectively XF is also set high at device reset Figure 8 1 shows the relationship between the time the SSBX or RSBX instruction is fetched
289. e than one hardware interrupt is requested at the same time the C54x DSP services them according to a set priority ranking in which 1 indicates the highest priority Table 6 19 through Table 6 24 show the priorities for the hardware interrupts G INTM bit is 0 The interrupt mode bit INTM which is in ST1 enables or disables all maskable interrupts m When INTM 0 all unmasked interrupts are enabled m When INTM 1 all unmasked interrupts are disabled INTM is set to 1 automatically when an interrupt is taken If the program exits the interrupt service routine ISR using the RETE instruction return from interrupt with automatic reenable INTM is reenabled cleared INTM can also be set with a hardware reset RS or by executing an SSBX INTM instruction disable interrupt INTM is reset by executing the RSBX INTM instruction enable interrupt INTM does not actually modify IMR or IFR G IMR mask bitis 1 Each of the maskable interrupts has its own mask bit in the IMR To enable an interrupt set its mask bitto 1 See section 6 10 2 Interrupt Mask Register IMR on page 6 29 The CPU acknowledges a maskable hardware interrupt it jams the instruction bus with the INTR instruction This instruction forces PC to the appropriate address and fetches the software vector As the CPU fetches the first word of the software vector it generates the IACK signal which clears the appropriate interrupt flag bit 6 32 Program Memory
290. eas overlapping areas or the same area which allows transmitting from a buffer while receiving into the same buffer if desired Serial Ports 9 45 Buffered Serial Port BSP Interface 9 46 Serial Ports The autobuffering process utilizes a circular addressing mechanism to access buffers within the 2K word block of ABU memory This mechanism operates in the same fashion for transmit and receive For each direction transmit or receive two registers specify the buffer size and the current address in the buffer These registers are the block size and address register for transmit and receive BKX BKR ARX ARR respectively Each of the block size and address register pairs fully specify the top and bottom of buffer addresses for transmit and receive Note that this circular addressing mechanism only effects accesses into the 2K word block by the ABU Accesses to this memory by the CPU are performed strictly according to the addressing mode s selected in the assembly language instructions which perform the memory access The circular addressing mechanism automatically recirculates ABU memory accesses through the specified buffer returning to the top of the buffer each time the bottom of the buffer is reached The circular addressing mechanism is initialized by loading BKX R with the exact size of the desired buffer as opposed to size 1 and ARX R with a value which contains both the base address of the buffer within the 2K word block
291. ece eee eee 7 56 SRCCD Instruction With a 3 Cycle Latency 00 cece 7 57 Modifying BRC From Within an RPTB Loop 0000 c eee eee e ee eens 98 BRAF Deactivation sisrrsissr priti ade dedes eee e seen ee ede eevadwe eens ete 7 59 OVLY Setup Followed by an Unconditional Branch DP 0 22 0005 7 60 OVLY Setup Followed by a Conditional Branch 0 0 eens 7 61 OVLY Setup Followed by a Return DP 0 0 cece eee eee 7 62 MP MC Setup Followed by an Unconditional Delayed Call 0 e0e eee 7 63 IPTR Setup Followed by a Software Trap 10 cece cece ene 7 64 DROM Setup Followed by a Read Access DP 0 0 002 e cece eee eens 7 65 DROM Setup Followed by a Dual Read Access 0 0 cece cece etnies 7 66 Accumulator Access With a 1 Cycle Latency 0 0 c cece eee eee 7 67 Accumulator Access With No Conflict 0 0000 c cette eens 7 68 Updating Accumulator With a 1 Cycle Latency 0 000 cece eee eee 7 69 Updating Accumulator With No Latency 0 00 cee cece eee eee 8 1 Switching Clock Mode From PLL x 3 Mode to Divide by 2 Mode 8 2 Switching Clock Mode From PLL x X Mode to PLL x 1 Mode 8 3 Switching Clock From PLL x 3 Mode to Divide by 2 Mode Turning Off the PLL and Entering IDLE3 0 00 cece eee eee 8 35 SPRU131G Examples xxxi Examples Serial Port Initialization
292. ece eens Multiplier Input Selection for Several Instructions 0 0 00 c eee eee eee ALU Operations in Dual 16 Bit Mode 0 0 cece eee es Instructions That Allow Immediate Addressing 0000 cece e eee e eee eee Direct Addressing Instruction Bit Summary 0 00 cece teenies Indirect Addressing Instruction Bit Summary Single Data Memory Operand Indirect Addressing Types With a Single Data Memory Operand 4 Bit Reversed Addresses 0 ccc cee nent eee t eee enes Indirect Addressing Instruction Bit Summary Dual Data Memory Operands Auxiliary Registers Selected by Xar and Yar Field of Instruction Indirect Addressing Types With Dual Data Memory Operands 000005 Assembler Syntax Comparison to TMS320C54x DSP 0 eee Indirect Addressing Instruction Bit Summary Compatibility Mode Instructions With 32 Bit Word Operands 0 00 cece teeta Devices With Additional Program Memory Address Lines 0000eee renee Loading Addresses Into PC 1 0 cece tenet A Loading Addresses into XPG 2 0 cece eect eee ete eens Unconditional Branch Instructions 00 0 cece teens Conditional Branch Instructions 0 00 e ene EN Far Branch Instructions 0 0 00 ccc cece tenet EEEE EENE EEEE Unconditional Call Instructions 00 00 c ccc eee ni rini Conditional Call Instruction
293. ed Software wait state control register HPI control register Reserved MCBSP 2 data receive register 2 MCBSP 2 data receive register 1 MCBSP 2 data transmit register 2 MCBSP 2 data transmit register 1 MCBSP 2 serial port sub bank address register See Table 8 11 on page 8 17 MCBSP 2 serial port sub bank data register See Table 8 11 on page 8 17 Reserved MCBSP 0 serial port sub bank address register See Table 8 11 on page 8 17 MCBSP 0 serial port sub bank data register See Table 8 11 on page 8 17 On Chip Peripherals 8 15 Peripheral Memory Mapped Registers Table 8 10 C5420 Peripheral Memory Mapped Registers For Each DSP Subsystem Continued Address Hex 3A 3B ac 3D 3F 40 41 42 43 44 47 48 49 4A 53 54 55 56 57 58 59 5F 8 16 On Chip Peripherals DRR21 DRR11 DXR21 DXR11 SPSA1 SPSD1 DMPREC DMSA DMSDI DMSDN CLKMD Description Reserved General purpose I O register Reserved MCBSP 1 data receive register 2 MCBSP 1 data receive register 1 MCBSP 1 data transmit register 2 MCBSP 1 data transmit register 1 Reserved MCBSP 1 serial port sub bank address register See Table 8 11 on page 8 17 MCBSP 1 serial port sub bank data register See Table 8 11 on page 8 17 Reserved DMA channel priority and enable control register DMA sub bank address register See Table 8 12 on page 8 18 DMA sub bank data register with sub bank a
294. ed followed by one of the data strobe signals If HRDY is not already high it goes high when the previous internal cycle is complete allowing data to be transferred and the control signals are deasserted Following the external HPI cycle HRDY goes low and stays low for a period of approximately five CLKOUT cycles refer to the TMS320C54x DSP data sheet for HPI timing information while the C54x DSP completes the internal HPI memory access and then HRDY is driven high again Note how ever HRDY is always high when HCS is high As mentioned previously SAM accesses generally utilize the HRDY signal The exception to the HRDY based interface timings when in SAM occurs when reading HPIC or HPIA or writing to HPIC except when writing 1 to either DSPINT or HINT In these cases HRDY stays high for all other SAM accesses HRDY is active SPRU131G On Chip Peripherals 8 47 Host Port Interface Host access cycles when in HOM have timings different from the SAM timings described previously In HOM the CPU is not involved with one exception and the access can be completed after a short fixed delay time The exception to this occurs when writing 1s to the DSPINT or HINT bits in HPIC In this case the host access takes several CPU clock cycles and SAM timings apply Besides the HRDY timings and a faster cycle time HOM access cycles are logically the same as SAM access cycles A summary of the condi tions under which the HRDY signal is acti
295. ed Divide by 2 with oscillator enabled 1 0 1 PLL x 1 with external source PLL x 1 with external source 0 1 1 Stop mode Stop modet T An individual device is either an Option 1 or Option 2 clock mode device The PLL is disabled The system clock is not provided to CPU peripherals The function of the stop mode is equivalent to that of the power down mode of IDLE3 however the IDLE 3 instruction is recommended rather than stop mode to realize full power saving since IDLE3 stops clocks synchronously and can be exited with an interrupt 8 5 2 Software Programmable PLL SPRU131G The software programmable PLL features a high level of flexibility and includes a clock scaler that provides various clock multiplier ratios capability to directly enable and disable the PLL and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved Devices that have a built in software programmable PLL can be configured in one of two clock modes g PLL mode The input clock CLKIN is multiplied by 1 of 31 possible ratios from 0 25 to 15 These ratios are achieved using the PLL circuitry _j DIV divider mode The input clock CLKIN is divided by 2 or 4 When DIV mode is used all of the analog parts including the PLL circuitry are disabled in order to minimize power dissipation Immediately following reset the clock mode is determined by the values of the three external pins CLKMD1 CLKMD2 and
296. ed depends in part on whether the return is nondelayed or delayed 1 Nondelayed The two instruction words are flushed from the pipeline so that they are not executed the return address is taken from the stack or from the RTN register and then execution continues at that address in the calling function 1 Delayed The one 2 word instruction or two 1 word instructions following the return instruction are executed This lets you avoid flushing the pipe line which requires extra cycles The return address is taken from the stack or from the RTN register Note The two words following a delayed instruction cannot be an instruction that causes a PC discontinuity a branch call return or software interrupt ss Table 6 10 shows the unconditional return instructions in the C54x DSP and the number of cycles needed to execute these instructions nondelayed and delayed Delayed instructions need two cycles fewer than the corresponding nondelayed instructions 6 12 Program Memory Addressing SPRU131G Returns Table 6 10 Unconditional Return Instructions Number of Cycles Instruction Description Nondelayed Delayed RET D Load the PC with the return address at 5 3 the top of the stack RETE D Load the PC with the return address at 5 3 the top of the stack and enable mask able interrupts RETF D Load the PC with the return address in 3 1 the RTN register and enable maskable interrupts Enabling interrupts with
297. eed changing or upgrading the TMS320 DSP can once again be used in the microprocessor mode This shortens the field upgrade time and avoids the possibility of inventory obsolescence Figure C 1 illustrates the procedural flow for developing and ordering TMS320 DSP masked parts When ordering there is a one time nonrefund able charge for mask tooling A minimum production order per year is required for any masked ROM device ROM codes will be deleted from the TI system one year after the final delivery C 1 Submitting ROM Codes to TI Figure C 1 TMS320 DSP ROM Code Submittal Flowchart Customer TMS320 DSP Design Customer submits TMS320 New Code Release Form Print Evaluation and Acceptance Form PEAF Purchase order for mask prototypes TMS320 DSP code Texas Instruments responds Customer code input into TI system Code sent back to customer for verification Customer lt approves algorithm Customer No approves 4 prototypes minimum production order required TMS320 DSP production C 2 Submitting ROM Codes to TI SPRU131G SPRU131G Submitting ROM Codes to TI The TMS320 DSP ROM code may be submitted in one of the following forms 3 1 2 inch floppy COFF format from macro assembler linker preferred 5 1 4 inch floppy COFF format from macro assembler linker Modem BBS COFF format from macro assembler linker EPROM others TMS27C64 PROM
298. eeee ee eee eee p 5 2 3 Central Processing Unit CPU ssassanssnnsnnnnnnnnnnnnne 2 4 Data Addressing e sersrnasrsenrrennsrnssnen anassen 2 5 Program Memory Addressing 0ceeeee eee eee e eee 2 11 26am Pipeline Operationianecriecrr eer errr ee E tiy tar 2 11 2 7 On Chip Peripherals oee e e e ee e e e ayafat sayatateey at 2 12 243 SISTEM eG a E E 2 15 2 9 External Bus Interface sic is cece caecum nasina nese canescens 2 17 2 10 IEEE Standard 1149 1 Scanning Logic 20eeeeeeeeee 2 17 2 1 Block Diagram Figure 2 1 Block Diagram of TMS320C54x DSP Internal Hardware System control Program address generation Data address generation interface logic PAGEN logic DAGEN gt PC IPTR RC ARAUO ARAU1 BRC RSA REA AROARI i ARP BK DP SP A AA A A A PA E PE E and CAB K external interface CB DAB Peripheral DB interface EAB EB EXP encoder T register Barrel shifter Fractional Legend Accumulator A Accumulator B CB data bus Adder 40 EB dee Be MAC unit PB program bus Barrel shifter T register ALU ZERO SAT ROUND EACEA CAMNVEMIVODSY 2 2 Architectural Overview SPRU131G 2 1 Bus Structure SPRU131G Bus Structure The C54x DSP architecture is built around eight major 16 bit
299. efficiently used when the two CPUs are executing identical programs In this case the amount of program memory required for the application is effectively reduced by 50 since both CPUs can execute from the same RAM 2 2 5 On Chip Memory Security The C54x DSP maskable memory security option protects the contents of on chip memories When you designate this option no externally originating instruction can access the on chip memory spaces Not all C54x DSPs offer the security feature and some devices only offer partial security 2 6 Architectural Overview SPRU131G Internal Memory Organization 2 2 6 Memory Mapped Registers SPRU131G The data memory space contains memory mapped registers for the CPU and the on chip peripherals These registers are located on data page 0 simplify ing access to them The memory mapped access provides a convenient way to save and restore the registers for context switches and to transfer informa tion between the accumulators and the other registers Architectural Overview 2 7 Central Processing Unit CPU 2 3 Central Processing Unit CPU The CPU is common to all C54x devices The C54x CPU contains 40 bit arithmetic logic unit ALU Two 40 bit accumulators Barrel shifter 17 x 17 bit multiplier 40 bit adder Compare select and store unit CSSU Data address generation unit Program address generation unit O O O O O O O O 2 3 1 Arithmetic Logic Unit ALU The C54x DSP per
300. efined in steps 1 5 and 6 For asingle device pair this could make use of BIO and XF For sever al devices this might mean that the device generating TFRM and TCLK broadcasts a command to all other devices until each one returns an acknowledge This initiates serial port transmit operations since TADD and TDAT are not driven if new data is not written to TDXR Example 9 6 TDM Serial Port Transmit Interrupt Service Routine Action Save any context that may be modified on the stack Write TDXR with a new value from a predetermined location in memory Restore the context that was saved in step 1 Return from the ISR with an RETE to reenable interrupts SPRU131G Description The operating context of the interrupted code must be maintained Write the new transmit data for the ISR The operating context of the interrupted code must be maintained Interrupts must be reenabled for the CPU to respond to the next interrupt Serial Ports 9 67 Time Division Multiplexed TDM Serial Port Interface Example 9 7 TDM Serial Port Receive Initialization Routine Action Reset and initialize the TDM seri al port by writing 0009h to TSPC Clear any pending TDM serial port receive interrupts by writing 0040h to IFR Enable the TDM serial port inter rupts by ORing 0040h with IMR Enable interrupts globally if nec essary by clearing the INTM bit in ST1 Write 0000h to TCSR Write 0001h to TRTA Perform a h
301. egardless of the state of MP MC The data bus goes into the high impedance state The control lines are made inactive The IACK signal is generated INTM is set to 1 to disable all maskable interrupts IFR is cleared to clear the interrupt flags The single repeat counter RC is cleared A synchronized reset SRESET signal is sent to initialize the peripherals The following status bits are set to their initial values O O O O O C O O O O C C C L ARP 0 ASM 0 AVIS 0 BRAF 0 C 1 C16 0 CLKOFF 0 CMPT 0 CPL 0 DP 0 DROM 0 FRCT 0 HM 0 E SXM 1 INTM 1 mw TC 1 OVA 0 E XF 1 OVB 0 OVLY 0 OVM 0 a Notes 1 The remaining status bits are not initialized your code must initialize them appropriately 2 Reset does not initialize the stack pointer SP Your code must initialize it 3 IfMP MC 0 the device begins executing code from the on chip ROM Otherwise it begins executing code from off chip memory a SPRU131G Program Memory Addressing 6 25 Interrupts 6 10 Interrupts Interrupts are hardware driven or software driven signals that cause the C54x DSP to suspend its main program and execute another function called an interrupt service routine ISR Typically interrupts are generated by hardware devices that need to give data to or take data from the C54x DSP for example ADCs DACs and other processors Interrupts can also be used to signal that a particular event h
302. eline This generally does not affect the execution time of that instruction Example 7 22 Example 7 23 and Example 7 24 show this conflict SPRU131G Pipeline 7 39 Pipeline Latencies Example 7 22 Resolving Conflict When Updating Multiple ARxs a Updating AR1 in execute stage and AR2 in read stage STLM A ARI This instruction updates AR1 in the Execute stag STM 1 AR2 This instruction tries to update AR2 in its read stage creating a conflict with the previous instruction The AR2 update is delayed by one cycle 1 2 3 4 5 6 7 8 Prefetch Fetch Decode Access Read Execute STLM A AR1 Write to AR1 Prefetch Fetch Decode Access Read Execute STM 1 AR2 1st word Write to Write to write delayed by 1 cycle AR2 AR2 Prefetch Fetch Decode Access Read Execute Legend Where a write conflict Where the write actually occurs occurs 7 40 Pipeline SPRU131G Pipeline Latencies Example 7 22 Resolving Conflict When Updating Multiple ARxs Continued b Updating AR1 in execute stage AR2 in read stage and AR3 in read stage STH A AR1 This instruction updates AR1 in th xecute stag STM 1 AR2 This instruction tries to update AR2 in its read stage causing a conflict The update is delayed by one cycle STM 2 AR3 This instruction updates AR3 in its read stage It creates no conflict since the previous instruction was a two word instruction 1 2 3 4 5 6 7 8 9 10 Prefetch Fet
303. ential flow of instructions by transferring control to some other location in program memory However unlike branches this transfer is intended to be temporary When a subroutine or function is called the address of the next instruction following the call is saved in the stack This address is used to return to the calling program and resume execu tion The C54x DSP performs both unconditional and conditional calls and both of these types can be either nondelayed or delayed 6 4 1 Unconditional Calls SPRU131G An unconditional call is always executed when itis encountered When the call is executed the PC is loaded with the specified program memory address and execution of the called routine begins at that address The address loaded into PC can come from either the second word of the call instruction or the lower 16 bits of an accumulator accumulator A or accumulator B Before the PC is loaded the return address is saved in the stack After the subroutine or func tion is executed a return instruction loads the PC with the return address from the stack and execution resumes at the instruction following the call By the time the unconditional call instruction reaches the execute phase of the pipeline the next two instruction words have already been fetched How these two instruction words are handled depends in part on whether the call is nondelayed or delayed 1 Nondelayed The two instruction words are flushed from the pipeline
304. equencies at additional ratios of CLKOUT For a detailed description of this feature refer to section 9 3 Buffered Serial Port BSP Interface on page 9 33 Note that the CLKR pin is always configured as an input The transmit frame synchronization pulse source is set by TXM bit 5 Like MCM if TXM 1 FSX is configured as an output and generates a pulse at the beginning of every transmit If TXM 0 FSX is configured as an input and accepts an external frame sync signal Note that the FSR pin is always config ured as an input XRST and RRST Bits 9 14 Serial Ports The serial port transmitter and receiver are reset with XRST bit 6 and RRST bit 7 These signals are active low so that if XRST RRST 0 the serial port is ina reset state To reset and reconfigure the serial port a total of two writes to the SPC are required I The first write to the SPC should M write a0 tothe XRST and RRST bits write the desired configuration to the remainder of the bits SPRU131G INO and IN1 Bits Serial Port Interface J The second write to the SPC should M write 1 to the XRST and RRST bits mM resend the desired configuration to the remainder of the bits The second write takes the serial port out of reset Note that the transmitter and receiver may be reset individually if desired When a 0 is written to XRST or RRST activity in the corresponding section of the serial port stops This minimizes the switching and al
305. equired to use AR2 Example 7 26 ARx Updated With a 1 Cycle Latency a ADD A B This instruction does not create a DAGEN conflict POPM AR3 This instruction has a 1 cycle latency if AR3 is used in the next NOP instruction The NOP is inserted LD AR3 A to avoid the conflict b STLM A ARI This instruction updates AR1 in th xecute stag POPM BK This instruction tries to update BK in the read stage The CPU delays the update by one cycl STM 1 AR2 This instruction tries to update NOP AR2 in the read stage The CPU delays this update by one cycl LD AR2 B This is why one NOP is required 7 48 Pipeline SPRU131G Pipeline Latencies Example 7 27 ARx Updated With and Without a 1 Cycle Latency a ARx updated with a one cycle latency STLM MVDK NOP MAR AR2 A ARI 100h AR2 This instruction creates DAGEN conflict The cycle AR2 update is delayed by one b ARx updated with no latency after reordering instructions MVDK STLM MAR AR2 100h AR2 A ARI r any This instruction does not require This instruction is placed after MVDK to avoid a DAGEN conflict No latency is required now latency Example 7 28 ARx Updated With and Without a 2 Cycle Latency a ARx updated with a two cycle latency STLM POPM NOP NOP LD A AR1 S
306. er CC i4 and i5 are also fetched If the test conditions are evaluated to be false these two instructions proceed through the pipeline Otherwise they are discarded The instruction prefetch in cycle 7 is also dependent on the evaluated conditions If the conditions are true PAB is loaded with the call address b1 otherwise it is loaded with the next incremental address a6 If the evaluated conditions are true i4 and i5 do not execute in cycles 10 and 11 In this case the CC instruction becomes a 5 cycle instruction However if the evaluated conditions are false i4 and i5 execute making CC a 3 cycle instruction Example 7 15 shows pipeline behavior during the execution of a delayed conditional call CCD instruction The pipeline behaves in the same manner as it does for the CC instruction However the following two instructions i3 and i4 are allowed to complete their execution regardless of whether the tested conditions are true or not Only cycles 7 8 and 9 are consumed by the CCD instruction making it a 3 cycle instruction SPRU131G Pipeline Operation Example 7 14 Conditional Call CC Instruction in the Pipeline Address Instruction al i1 a2 a3 CC b1 cond a4 i4 a5 i5 a6 i6 b1 ji 1 2 3 4 5 6 7 8 9 10 11 12 Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute 2 a __ EAB SP EB RTN Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read
307. er halt hardware interrupt An interrupt triggered through physical connections with on chip peripherals or external devices HINT C54x to Host Processor Interrupt A bit in the HPI control register HPIC that enables disables an interrupt from the C54x DSP to a host device HM See hold mode hold mode HM A bitin status register ST1 that determines whether the CPU enters the hold state in normal mode or concurrent mode host only mode HOM The mode that allows the host to access HPI memory while the C54x CPU is in IDLE2 all internal clocks stopped or in reset mode host port interface HPI An 8 bit parallel interface that the CPU uses to communicate with a host processor HPI address register HPIA A 16 bit register that stores the address of the host port interface HPI memory block The HPIA can be preincrem ented or postincremented HPI control register HPIC A 16 bit register that contains status and control bits for the host port interface HPI IFR See interrupt flag register IMR See interrupt mask register INO inputO bit A bitin the serial port control register SPC buffered serial port control register BSPC and TDM serial port control register TSPC that allows the CLKR pin to be used as an input INO reflects the current level of the CLKR pin of the device IN1 input7 bit A bitin the serial port control register SPC buffered serial port control register BSPC and TDM serial port co
308. eration 0 000 c cece ee 9 4 4 TDM Mode Transmit and Receive Operations 000200000e 9 4 5 TDM Serial Port Interface Exception Conditions 2 005 9 4 6 Examples of TDM Serial Port Interface Operation 045 External Bus Operation 0c cece eee a Discusses the external bus interface and the timing of events involved in memory and I O accesses Describes the hold mode and the wake up sequence from IDLE3 mode 101 External Bus Interface 0 0 eee nes 10 2 External Bus Priority 0 0 06 cent eee 10 8 External Bus Control 2ccs2252 c20 Sor siedeiedesbiaawied a a a a E e E 10 3 1 Wait State Generator acci iseci iriiciidicianii ete ees 10 3 2 Bank Switching Logic iian aaa anaE R eee 10 4 External Bus Interface Timing 0 0 0 c cece teens 10 4 1 Memory Access Timing 0 cece tenes 10 4 2 I O Access Timing 0 000 c ioi n iini iaa eens 10 4 3 Memory and I O Access Timing 0 0 cece eee eee eee ees 10 5 Start Up Access Sequences 06 ct tenet nenes 10 5 1 RSC scene hans ends whens ead eid Pde ance ea pee ba dee aie f 10 5 2 IDLES x asnctncrecud ist horcnmiged Rae E E D E E E E 10 6 Hold ModE riisi a Nein a a E a aie ned 2 10 6 1 Interrupts During Hold 1 2 0 cee eee 10 6 2 Holdand Reset 0c cece tee eens Design Considerations for Using XDS510 Emulator 002cee eee ence eens
309. eration in Standard Mode BSP operation in standard mode is discussed in section 9 2 Serial Port Inter face on page 9 4 This section summarizes the differences between serial port operation and standard mode BSP operation and describes the enhanced features that the BSP offers The enhanced BSP features are available both in standard mode and in autobuffering mode ABU is discussed in section 9 3 2 on page 9 40 Information presented in this section assumes familiarity with standard mode operation as described in section 9 2 Serial Port Interface The BSP uses its own dedicated memory mapped data transmit data receive and serial port control registers BDXR BDRR and BSPC The BSP also utilizes an additional control register the BSP control extension register BSPCE inimplementing its enhanced features and controlling the ABU The BDRR BDXR and BSPC registers function similarly to their counterparts in the serial port as described in section 9 2 Serial Port Interface As with the serial port the BSP transmit and receive shift registers BXSR and BRSR are not directly accessible in software but facilitate the double buffering capability If the serial port is not being used the BDXR and the BDRR registers can be used as general purpose registers In this case BFSR should be set to an inactive state to prevent a possible receive operation from being initiated Note however that program access to BDXR or BDRR is limited when auto buffe
310. erefore when reading the data obtained is the data from the location specified in the SPRU131G On Chip Peripherals 8 45 Host Port Interface previous access and the current access serves as the initiation of the next cycle A similar sequence occurs for a write operation the data written to HPID is not written to HPI memory until after the external cycle is completed If an HPID read operation immediately follows an HPID write operation the same data the data written is read The autoincrement feature available for HPIA results in sequential accesses to HPI memory by the host being extremely efficient During random nonsequential transfers or sequential accesses with a significant amount of time between them it is possible that the C54x DSP may have changed the contents of the location being accessed between a host read and the previous host data read write or HPIA write access because of the prefetch nature of internal HPI operation If this occurs data different from the current memory contents may be read Therefore in cases where this is of concern in a system two reads from the same address or an address write prior to the read access can be made to ensure that the most recent data is read When the host performs an external access to the HPI there are two distinctly different types of cycles that can occur those for which wait states are gener ated the HRDY signal is active and those without wait states In general when
311. erflow has occurred resetting the transmitter XRST bit to 0 or resetting the device XSREMPTY 1 On the SP XSREMPTY is deactivated set to 1 directly as a result of writing to DXR on the BSP XSREMPTY is only deactivated after DXR is loaded followed by the occurrence of an FSX pulse Serial Ports 9 9 Serial Port Interface Table 9 5 Serial Port Control Register SPC Bit Summary Continued Bit 11 10 9 10 Name XRDY RRDY IN1 INO RRST XRST Reset Value Serial Ports 1 Function Transmit Ready A transition from 0 to 1 of the XRDY bit indicates that the DXR contents have been copied to XSR and that DXR is ready to be loaded with a new data word A transmit interrupt XINT is generated upon the transition This bit can be polled in software instead of using serial port interrupts Note that on the SP XRDY is generated directly as a result of writing to DXR while on the BSP XRDY is only generated after DXR is loaded followed by the occurrence of an FSX pulse At reset or serial port transmitter reset XRST 0 the XRDY bit is set to 1 Receive Ready A transition from 0 to 1 of the RRDY bit indicates that the RSR contents have been copied to the DRR and that the data can be read A receive interrupt RINT is generated upon the transition This bit can be polled in software instead of using serial port interrupts At reset or serial port receiver reset RRST 0 the RRDY bit is cleared to
312. eripheral Memory Mapped Registers 0 0c cece eee e teens 8 3 General Purpose I O 0 00 nent ee eens 8 3 1 Branch Control Input Pin BIO sas s lt nsascadescncasarcenckaraxncces sane 8 3 2 External Flag Output Pin XF serri strpi runiitarii nirt inanis 8 4 TIM esc dgaende dee eee eee dea a he dae chad ded madd atin end adits 8 4 1 Timer Registers 00 cece cece eee eee e ee eeee 8 4 2 Timer Operation 0c cece een eee eens 8 5 Clock Generator jcisida ecaa ieia nga ld hae eke Pate aaa ated eae a doe 8 5 1 Hardware Configurable PLL 0 ccc eee 8 5 2 Software Programmable PLL 00 cece eee eee 8 6 Host Port Intertace cee nerie eee es ge asiaa dak be Ea a aaa eed dee dee ea 8 6 1 Basic Host Port Interface Functional Description 0 005 8 6 2 Details of Host Port Interface Operation cc eee eee 8 6 3 Host Read Write Access to HPI 0 00 eee 8 6 4 DSPINT and HINT Function Operation 0c cece eee eee 8 6 5 Considerations in Changing HPI Memory Access Mode SAM HOM and IDL E2 3 USE iiaa n Obs hehe Biel e EEE weed barged EE E achiev E 8 6 6 Access of HPI Memory During Reset 20 0 cece e eee eee eee 9 Serial POMS cis cise ence cee catia E E casi ieee ne krackels Describes the TMS320C54x DSP serial ports Includes information about the standard serial port interface buffered serial port interf
313. eripherals on a particular C54x device see section 8 2 Peripheral Memory Mapped Registers on page 8 2 1 The scratch pad RAM block 60h 7Fh in data memory includes 32 words of DARAM for variable storage that helps avoid fragmenting the large RAM block 3 3 4 CPU Memory Mapped Registers Table 3 3 on page 3 27 lists the CPU memory mapped registers This sec tion gives a brief summary of one or more of the registers 3 3 4 1 Interrupt Registers IMR IFR The interrupt mask register IMR individually masks off specific interrupts at required times The interrupt flag register IFR indicates the current status of the interrupts Interrupts are described in detail in section 6 10 nterrupts on page 6 26 3 3 4 2 Status Registers STO ST1 The status registers STO and ST1 contain the status of the various conditions and modes for the C54x devices STO contains the flags OVA OVB C and TC produced by arithmetic operations and bit manipulations in addition to the DP and the ARP fields ST1 reflects the status of modes and instructions executed by the processor See section 4 1 CPU Status and Control Regis ters on page 4 2 for detailed information 3 3 4 3 Accumulaitors A B The C54x devices have two 40 bit accumulators accumulator A and accumu lator B Each accumulator is memory mapped and partitioned into accumula tor low word AL BL accumulator high word AH BH and accumulator guard bits AG BG See sect
314. es Architectural Overview 2 3 Bus Structure Table 2 1 Bus Usage for Read and Write Accesses Address Bus Data Bus Access Type PAB CAB DAB EAB PB CB DB EB oea a amp s 0 0 Program write V Ni Data single read V NI Data dual read V V y y Data long 32 bit read V hw V Iw V hw V Iw Data single write y Ni Data read data write V V y y Dual read coefficient read V V V y y y Peripheral read V N Peripheral write y Ni Legend hw high 16 bit word Iw low 16 bit word 2 4 Architectural Overview SPRU131G Internal Memory Organization 2 2 Internal Memory Organization The C54x DSP memory is organized into three individually selectable spaces program data and I O space The C54x devices can contain random access memory RAM and read only memory ROM Among the devices the following types of RAM are represented dual access RAM DARAM single access RAM SARAM and two way shared RAM The DARAM or SARAM can be shared within subsystems of a multiple CPU core device You can configure the DARAM and SARAM as data memory or program data memory Table 2 2 shows how much ROM DARAM and SARAM are avail able on some C54x devices The C54x DSP also has 26 CPU registers plus peripheral registers that are mapped in data memory space The C54x DSP memory types and features are introduced in the sections following this para graph For details about configuring and using the various memor
315. escribes the external bus operation and control for memory and I O accesses Some of the external bus operation and control features of the TMS320C54x DSP include software wait states bank switching logic and hold logic The C54x DSP supports a wide range of system interfacing requirements The C5410 enhanced external parallel interface XIO is not described in this chapter See the TMS320C5410 datasheet for details about the external memory interface Topic Page 10 1 ExternaliBus Interface Smaa ete elelareieie clalaletelere atersyer 10 2 External BUS Priority oon a a E a UES S4CGET ES CONtro Ik E 10 4 External Bus Interface Timing ssusnssssssunnnnnnnssnnne 10 5 Start Up Access Sequences cccceeeeeeeeeeeeeeees 10 6 Hold MOO ccsa saaa aE aaa aE sicteve EEE EEE EEEE EEE 10 28 External Bus Interface 10 1 External Bus Interface Table 10 1 Signal Name AO0 A15 DO D15 The C54x DSP external interface consists of data buses address buses and a set of control signals for accessing off chip memory and I O ports Table 10 1 lists key signals for the external interface Key External Interface Signals C541 C542 C543 C548 C549 C545 C546 C5410 C5402 15 0 22 0 19 0 15 0 15 0 15 0 y y y y va y y 1 y 1 1 va y v 1 v C5420 17 0 15 0 ed AS DS Description Address bus Data bus External memory access strobe P
316. essing words to be transferred between the C54x DSP internal memory and the BSP data transmit register BDXR and BSP data receive register BDRR in autobuffering mode The address and block size registers as well as circular addressing are also discussed in detail later in this section Note that the 11 bit memory mapped AXR BKX ARR and BKR registers are read as 16 bit words with the five most significant bits read as zeroes and the 11 bit register contents right justified in the least significant 11 bits If autobuf fering is not used these registers can be used for general purpose storage of 11 bit data The transmit and receive sections of the ABU can be enabled separately When either section is enabled access to its corresponding serial port data register BDXR or BDRR through software is limited The BDRR can only be read and the BDXR can only be written when the ABU is disabled The BDRR can only be written when the BSP is in reset The BDXR can be read any time When either transmit or receive autobuffering is disabled that section oper ates in standard mode and its portion of the ABU is transparent The ABU also implements CPU interrupts when transmit and receive buffers have been halfway or entirely filled or emptied These interrupts take the place of the transmit and receive interrupts in standard mode operation the receive interrupt is the CPU They are not generated in autobuffering mode This mechanism features an auto
317. ether the transmitter has experienced underflow XSREMPTY is an active low bit therefore when XSREMPTY 0 an underflow has occurred Any one of the following three conditions causes XSREMPTY to become active XSREMPTY 0 1 DXR has not been loaded since the last DXR to XSR transfer and XSR empties the actual transition of XSREMPTY occurs after the last bit has been shifted out of XSR 1 or the transmitter is reset XRST 0 g or the C54x device is reset RS 0 When XSREMPTY 0 the transmitter halts and stops driving DX the DX pin is ina high impedance state until the next frame sync pulse Note that under flow does not constitute an error condition in the burst mode although it does in the continuous mode error conditions are further discussed in section 9 2 6 Serial Port Interface Exception Conditions on page 9 26 The following condition causes XSREMPTY to become inactive KSREMPTY 1 1 A write to DXR occurs on the SP or on the BSP a write to DXR occurs followed by an FSX pulse see section 9 2 4 Burst Mode Transmit and Receive Operations on page 9 18 for further information about transmit timing The RSRFULL bit 13 indicates whether the receiver has experienced over run RSRFULLis an active high bit therefore when RSRFULL 1 RSRis full In burst mode FSM 1 all three of the following must occur to cause RSRFULL to become active RSRFULL 1 SPRU131G Serial Port Interface J
318. eturn address These cycles are consumed by the return instruction because the next two instructions i3 and i4 do not com plete their execution Because no instructions were fetched in cycles 4 and 5 cycles 9 and 10 are dummy cycles j1 completes execution Pipeline 7 13 Pipeline Operation Example 7 8 shows the pipeline s behavior during the execution of a delayed return instruction In a delayed return instruction the C54x DSP pipeline behaves in the same way as with the normal return instruction However the following two instruc tions i3 and i4 are allowed to complete their execution so only cycles 6 7 and 8 are consumed by the delayed return instruction making it a 3 cycle instruction as shown in Example 7 8 Example 7 8 Delayed Return RETD Instruction in the Pipeline Address al a2 a3 b1 1 2 Prefetch Fetch Pipeline flush jj Prefetch here PAB a Instruction RETD i2 i3 jl 3 4 5 6 T 8 9 10 11 Decode Access Read Execute Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute PAB 4 Prefetch Fetch Decode Access Read Execute No No Pewee E Ref Prefetch Fetch Decode Access Read Execute No No ee Prefetch Fetch Decode Access Read Execute PAB b1 PB j1 ji 7 14 Pipeline SPRU131G Pipeline Operation Example 7 9 and Example 7 10 show the pipeline behavior for a return with interrupt enable RETE instr
319. example DST A AR1 two cycles Prefetch Fetch Decode Access Read Execute Load EAB Write to EAB Prefetch Fetch Decode Access Read Execute Write i f Instruction performing operand read and operand write for example ST A AR2 LD AR3 B one cycle Prefetch Fetch Decode Access Read Execute Write Read from DB 7 4 Pipeline SPRU131G Pipeline Operation The following sections provide examples that demonstrate how the pipeline works while executing different types of instructions Unless otherwise noted all instructions shown in the examples are considered single cycle single word instructions residing in on chip memory The pipeline is depicted in these examples as a set of staggered rows in which each row corresponds to one instruction word moving through the stages of the pipeline Example 7 1 is a sample pipeline diagram Example 7 1 Sample Pipeline Diagram Address Instruction al a2 B b1 This is a four cycle two word branch instruction a3 i3 This is any one cycle one word instruction a4 i4 This is any one cycle one word instruction b1 jl 1 2 3 4 5 6 7 8 9 10 Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute b1 PAB a2 PB b1 IR b1 b1 Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute jt PAB b1 PB j1 IR j1 ji Each row in the example is labeled on the left as an instr
320. f the XF pin XH See transmit buffer half transmitted XINT XINTO XINT1 See serial port transmit interrupt XPC See program counter extension XRDY See transmit ready XRST See transmitter reset XSR data transmit shift register A 16 bit register that holds serial data to be transmitted from the DX pin or TDX pin when TDM 1 See also TDXR XSREMPTY See transmit shift register empty ZA zero detect A A signal that indicates when accumulator A contains a0 ZB zero detect B A signal that indicates when accumulator B contains a0 zero detect See ZA and ZB zero fill A method of filling the low or high order bits with zeros when load ing a 16 bit number into a 32 bit field SPRU131G Ik addressing 14 pin connector dimensions A 15 14 pin header header signals A 2 JTAG A A D converter definition absolute addressing ABU See autobuffering unit ABU control register definition ABU receive address register ARR definition ABU receive buffer size register BKR definition ABU transmit address register AXR definition ABU transmit buffer size register BKX definition accessing DRAM blocks accessing status registers latencies 7 60 accumulator definition accumulator A definition guard bits accumulator A high word AH definition accumulator A low word AL definition accumulator access no conflict one cycle latency Index accumulator addressing accu
321. fall time of greater than 25 ns the modification shown in this figure is suggested Rise times of more than 25 ns can cause the emulator to detect false edges during the RUNB command or when the external counter selected from the debugger analysis menu is used SPRU131G Design Considerations for Using XDS510 Emulator A 23 Emulation Design Considerations You do not need to have devices on one target board stop devices on another target board using the EMU0 1 signals see the circuit in Figure A 14 In this configuration the global stop capability is lost It is important not to overload EMU0 1 with more than 16 devices Figure A 14 EMUO0 1 Configuration Without Global Stop r ep E ge eT 7 Target board 1 Pullup resistor EMUO 1 Pullup resistor we n To emulator EMU0 1 Le e a a a a a a a a a a J oS aq Target board m Pullup resistor n EMUO 1 n bass 4 Note Theopen collector driver and pullup resistor on EMU1 mustbe able to provide rise fall times of less than 25 ns Rise times of more than 25 ns can cause the emulator to detect false edges during the RUNB command or when the external counter selected from the debugger analysis menu is used If this condition cannot be met then the EMU0 1 signals from the individual boards must be ANDed together as shown in Figure A 14 to produce an EMU0 1 signal for the emulator A 8 4 Performing Diag
322. for autobuffering mode operation In both cases assume that transmit and receive interrupts are used to service the ABU interrupts however polling of the interrupt flag register IFR could also be used Both the transmit and receive sections can be initialized at the same time or separately depending upon system requirements Example 9 3 initializes the serial port for transmit operations only with burst mode external frame sync and external clock selected The selected data format is 16 bits with frame sync and clock polarities selected to be high true Transmit autobuffering is enabled by setting the BXE bit in the ABUC section of BSPCE and HALTX has been set to 1 which causes transmission to halt when half of the defined buffer is transmitted SPRU131G Buffered Serial Port BSP Interface Example 9 4 initializes the serial port for receive operations only with continuous mode selected Frame sync and clock polarities are selected to be low true data format is 16 bits and frame ignore is selected so that two received data bytes are packed into a single received word to minimize memory requirements Receive autobuffering is enabled by setting the BRE bit in the ABUC section of BSPCE In Example 9 3 and Example 9 4 the transmit and receive interrupts used are those that the BSP occupies on the C542 C543 C545 C546 C548 and C549 the devices that include the BSP However on other devices that use the BSP different interrupts
323. forms 2s complement arithmetic with a 40 bit arithmetic logic unit ALU and two 40 bit accumulators accumulators A and B The ALU can also perform Boolean operations The ALU uses these inputs 16 bit immediate value 16 bit word from data memory 16 bit value in the temporary register T Two 16 bit words from data memory 32 bit word from data memory 40 bit word from either accumulator O O O O O L The ALU can also function as two 16 bit ALUs and perform two 16 bit operations simultaneously See section 4 2 Arithmetic Logic Unit ALU on page 4 10 for more details about ALU operation 2 3 2 Accumulators Accumulators A and B see Figure 2 1 on page 2 2 store the output from the ALU or the multiplier adder block They can also provide a second input to the ALU accumulator A can be an input to the multiplier adder Each accumulator is divided into three parts Lj Guard bits bits 39 32 LJ High order word bits 31 16 1 Low order word bits 15 0 Instructions are provided for storing the guard bits for storing the high and the low order accumulator words in data memory and for transferring 32 bit accumulator words in or out of data memory Also either of the accumulators can be used as temporary storage for the other See section 4 3 Accumulators Aand B on page 4 13 for more details about the features of these accumulators 2 8 Architectural Overview SPRU131G 2 3 3 Barrel Shifter Central Processing Unit C
324. frame sync pulses BFSX and BFSR are active high or low FSP 0 Frame sync pulses BFSX and BFSR are active high FSP 1 Frame sync pulses BFSX and BFSR are active low SPRU131G Buffered Serial Port BSP Interface Table 9 9 BSP Control Extension Register BSPCE Bit Summary Serial Port Control Bits Continued Reset Bit Name value Function 4 0 CLKDV 00011 Internal Transmit Clock Division factor When the MCM bit of BSPC is set to 1 CLKxX is driven by an on chip source having a frequency equal to 1 CLKDV 1 of CLKOUT CLKDV range is 0 31 When CLKDV is odd or equal to 0 the CLKX duty cycle is 50 When CLKDV is an even value CLKDV 2p the CLKX high and low state durations depend on CLKP When CLKP is 0 the high state duration is p cycles and the low state duration is p 1 cycles when CLKP is 1 the high state duration is p 1 cycles and the low state duration is p cycles Table 9 10 Buffered Serial Port Word Length Configuration FO FE Buffered Serial Port Word Length Configuration 0 0 16 bit words transmitted and received Reset values 0 1 10 bit words transmitted and received 1 0 8 bit words transmitted and received 1 1 12 bit words transmitted and received These enhanced features allow greater flexibility in serial port interface in a variety of areas In particular the frame ignore feature offers a capability which allows a mechanism for effectively compressing transferred data packets if they are not
325. from ARx using circular addressing T ARx is used as the data memory address unless otherwise specified Increment decrement value is 1 for 16 bit word access and 2 for 32 bit word access This mode is not allowed in memory mapped register addressing This mode is discussed in greater detail in section 5 2 4 k Addressing on page 5 5 This mode is allowed only for write accesses SPRU131G Data Addressing 5 13 Indirect Addressing Table 5 4 Indirect Addressing Types With a Single Data Memory Operand Continued MOD Field 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 Operand Syntax ARX ARx 0 ARx Ik 4ARx Ik ARXx Ik Ik Function Descriptiont addr ARx After access the address in ARx is incremented using ARx circ ARx 1 circular addressing addr ARx After access ARO is added to ARx using circular addressing ARx circ ARx ARO addr ARx Ik The sum of ARx and the 16 bit long offset Ik is used as the ARx ARx data memory address ARx is not updated addr ARx Ik Before its use the signed 16 bit long offset Ik is added to ARx ARx Ik ARx and this sum replaces the previous content of ARx this sum is then used to address the data memory operand addr circ ARx Ik Before its use the signed 16 bit long offset Ik is added to ARx circ ARx Ik ARx using circular addressing and this sum replaces the previous content of A
326. g or clearing the MP MC bit in the PMST register Figure 3 1 through Figure 3 4 pages 3 3 through 3 6 show the program memory configurations on the individual C54x devices SPRU131G Program Memory 3 2 2 On Chip ROM Organization The on chip ROM is subdivided and organized in blocks to enhance performance For example the block organization enables you to fetch an instruction from one block of ROM without sacrificing data accesses that come from a different block of ROM Figure 3 14 shows the way the ROM is organized in blocks for each C54x device The gray lines in the figure indicate block boundaries Depending on the device the ROM is organized into 2K 4K or 8K blocks For 2K ROM devices typically the ROM block is 2K for 4K ROM and 28K ROM devices typically the ROM block is 4K for 16K ROM and 48K ROM devices typically the ROM block is 8K Figure 3 14 On Chip ROM Block Organization C541 C542 543 c545 546t C548 c549 C5402 C5410 4000h 4000 4FFF 5000h 5000 5FFF 6000h 6000 6FFF 7000h 7000 7FFF 8000h 8000 8FFF 9000h f 9000 97FF 9000 9FFF 9800 9FFF A000h A000 AFFF B000h B000 BFFF oooh C000 CFFF Do00h D000 DFFF E000h E000 EFFF F000h F000 FFFF F000 FFFF F7FF FFFF F800 FFFF T ROM is organized in 8K blocks on these devices C000 DFFF C000 DFFF E000 FFFF E000 FFFF F000 FFFF SPRU131G Memory 3 17 Program
327. gement of the PLL is important The clock generator consumes the least power when operating in DIV mode with the PLL disabled Therefore if power dissipation is a significant consideration it is desirable to switch from PLL mode to DIV mode and disable the PLL before executing an IDLE 1 8 34 On Chip Peripherals SPRU131G Clock Generator IDLE 2 or IDLE 3 instruction This is accomplished as explained in section Switching From PLL Mode to DIV Mode on page 8 33 After waking up from IDLE1 IDLE2 IDLE8 the clock generator can be reprogrammed to PLL mode as explained in section Switching From DIV Mode to PLL Mode on page 8 32 Note that when the PLL is stopped during an IDLE state and the C54x device is restarted and the clock generator is switched back to PLL mode the PLL lockup delay occurs in the same manner as in a normal device startup There fore in this case the lockup delay must also be accounted for either externally or by using the PLL lockup counter timer Example 8 3 shows a code sequence that switches the clock generator from PLL x 3 mode to divide by 2 mode turns off the PLL and enters IDLE3 After waking up from IDLE3 the clock generator is switched from DIV mode to PLL x 3 mode using a single STM instruction with a PLLCOUNT of 64 decimal used for the lock timer value Example 8 3 Switching Clock From PLL x 3 Mode to Divide by 2 Mode Turning Off the PLL and Entering IDLE3 TstStatu After STM 0b
328. gister TtAccesses to address 57h update the subaddressed register and postincrement the subaddress contained in DMSBAR Accesses to 56h update the subaddressed register without modifying DMSBAR 8 18 On Chip Peripherals SPRU131G Peripheral Memory Mapped Registers Table 8 12 C5402 C5410 C5420 DMA Subaddressed Registers Continued DMA Address Name Hex t DMSFC4 56 57 DMMCR4 56 57 DMSRC5 56 57 DMDST5 56 57 DMCTRS5 56 57 DMSFC5 56 57 DMMCR5 56 57 DMSRCP 56 57 DMDSTP 56 57 DMIDX0O 56 57 DMIDX1 56 57 DMFRIO 56 57 DMFRI1 56 57 DMGSA 56 57 DMGDA 56 57 DMGCR 56 57 DMGFR 56 57 Sub address Hex 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 Description DMA channel 4 sync select and frame count register DMA channel 4 transfer mode control register DMA channel 5 source address register DMA channel 5 destination address register DMA channel 5 element count register DMA channel 5 sync select and frame count register DMA channel 5 transfer mode control register DMA source program page address common channel DMA destination program page address common channel DMA element index address register 0 DMA element index address register 1 DMA frame index register 0 DMA frame index register 1 DMA global source address reload register DMA global destination address reload register DMA global count reload register DMA global frame count reload register Tt Accesses to address 57h update th
329. gister T A pipeline conflict can occur when accessing T if two conditions are simulta neously met _j An instruction writes to T _j The next instruction uses T for a shift or bit test operation The conflict occurs because the second instruction tries to use T in a pipeline stage that occurs before the previous instruction updates it Table 7 12 lists instructions that do not have any latency in updating T Use these instructions wherever possible to avoid any conflicts Table 7 12 Pipeline Protected Instructions for Updating T SPRU131G To do this Use this instruction Write an immediate value to T STM lk T Copy a memory location to T MVDK Smem T Copy a memory location to T LD Smem T Copy a memory location to T ST src Ymem LD Xmem T Table 7 13 lists the latencies between instructions that update and use T Note You are responsible for rearranging instructions or inserting NOPs if necessary to accommodate T latencies eee Pipeline 7 57 Pipeline Latencies Table 7 13 Latencies for the T Register Based on Second Instruction Category a Latencies Based on Second Instruction Category Second Instruction First Instruction Category MVKD dmad T 1 MVDM_ dmad T POPM T 1 POPD T DELAY T MVDD Xmem Ting Store type instructions see Table 7 5 1 EXP src 1 b Categories for the Second Instruction Category LD ADD SUB NORM BITT DADST DSADT DSUBT Legend Not
330. gisters SPRU131G Unprotected pipeline conflicts can occur when any one of the following memory mapped registers is accessed Auxiliary registers ARO AR7 Block size register BK Stack pointer SP Temporary register T Processor mode status register PMST Status registers STO and ST1 Block repeat counter register BRC Memory mapped accumulator registers AG AH AL BG BH BL O O O C C C O L However certain instructions can access these registers without causing pipe line conflicts if you observe appropriate latency cycles Table 7 3 lists these instructions Table 7 3 is valid only if programmers limit themselves to those instructions that are listed in column 3 in order to perform functions listed in column 2 Otherwise refer to the following sections to find the latency of each individual instruction Furthermore this table is provided as a quick reference for pipeline latencies It does not describe all possible pipeline latencies nor does it provide detailed information about latencies Pipeline 7 35 Pipeline Latencies Table 7 3 Recommended Instructions for Accessing Memory Mapped Catt 1 Registers Function Writing to ARx BK with out using an accumulator Writing to ARx BK using an accumulator Popping ARx BK from stack Writing to SP without using an accumulator Writing to SP using an accumulator Writing to T without using an accumulator Writing to T using an acc
331. gisters perform their writes in the execute stage and are store type instructions They are listed in Table 7 5 Table 7 4 Instructions That Access DAGEN Registers in the Read Stage Instruction Type Instructions Constant initialization STM lk MMR ST lk Smemt t Move type 1 MVDD Xmem Ymemt POPM MMR POPD Smemt DELAY Smemt t Move type 2 MVDK Smem dmadt MVMD MMR dmadt T This operand must be pointing to one of the DAGEN registers DP must be 0 to access DAGEN registers 7 38 Pipeline SPRU131G Pipeline Latencies Table 7 5 Store Type Instructions Instruction Instruction Instruction MVKD dmad Smem STL src SHFT Xmem SRCCD Xmem cond MVDM dmad MMR STL src SHIFT Smem STRCD Xmem cond MVPD dmad Smem ST ADD CMPS src Smem STH src Smem ST LD ST T Smem STH src ASM Smem ST LT ST TRN Smem STH src SHFT Xmem ST MAC R ADDM Smem lk STH src SHIFT Smem ST MAS R ANDM Smem lk STLM src MMR ST MPY ORM lk Smem STL src Smem ST SUB XORM Smem lk STL src ASM Smem SACCD src Xmem cond When a store type instruction is immediately followed by an instruction that updates ARx BK or SP in the read stage a conflict can occur because both instructions try to access DAGEN registers The DAGEN register set can be written to only once in a given cycle so the CPU delays the read stage access by one cycle This access is performed when the second instruction is in the execute stage of the pip
332. gram functions using CMPS instruction 4 26 Viterbi operator 4 25 with ALU operations 4 25 D address bus DAB definition D bus DB definition DAB address register DAR definition DAGEN DAGEN register address conflicts rules 7 44 DAR See DAB address register DARAM blocks table 7 27 data address bus definition data address generation DAGEN instructions that access in read stage data addressing five modes introduction data bus definition data buses 2 3 data memory to accumulators auxiliary registers block repeat registers Index 6 circular buffer size register BK 3 28 configurability CPU registers definition interrupt registers on chip advantages processor mode status register PMST program counter extension XPC 3 29 stack pointer SP status registers table temporary register T transition register TRN data memory page pointer DP definition D 7 data receive register DRR data receive shift register RSR 9 5 definition data ROM DROM 4 7 definition D 7 data security data transmit register DXR data transmit shift register XSR 9 5 definition data types 16 bit 32 bit data address er logic DAGEN definition D 6 D 7 debug tools debugger See emulation delayed branch instruction in the pipeline 7 7 development support applications development tools device nomenclature B 6 diagram B 6 prefixes diagnostic a
333. gurations see the device data sheet When the memory cells are mapped into program space the C54x device automatically accesses these memory cells when addresses fall within the boundaries of the on chip memory When the program address generation unit PAGEN generates an address outside the boundaries of the on chip memory the device automatically generates an external access For more information about program address generation see Chapter 6 Program Memory Addressing Table 3 1 On Chip Program Memory Available on TMS320C54x Devices SPRU131G Device ROM DARAM SARAM C541 28K 5K C542 2K 10K C543 2K 10K C545 48K 6K C546 48K 6K C548 2K 8K 24K C549 16K 8K 24K C5402 4K 16K C5410 16K 8K 56K C5420 32K 168K Memory 3 15 Program Memory 3 2 1 3 16 Program Memory Configurability Memory The MP MC and OVLY bits determine which on chip memories are enabled in program space At reset the logic level present on the MP MC pin is transferred to the MP MC bit in the PMST register see section 4 1 CPU Status and Control Registers on page 4 2 The MP MC bit determines whether to enable the on chip ROM lf MP MC 1 the device is configured as a microprocessor and the on chip ROM is not enabled If MP MC pin 0 the device is configured as a microcom puter and the on chip ROM is enabled The MP MC pin is sampled only at reset however you can disable or enable the on chip ROM through software by settin
334. h C5402 IFR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Resvd DMAC5 DMAC4 i C5410 IFR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Resvd DMAC5 DMAC4 HPINT INT3 j C5420 IFR 5 14 13 12 5 4 3 2 1 BXINT2 BRINT2 Resvd IPINT DMAC5 DMAC4 _ or or HPINT RSVD or or BXINTO BRINTO TINT RSVD INT1 INTO DMAC1 DMACO 6 10 2 Interrupt Mask Register IMR Figure 6 3 shows how the C54x DSP uses a memory mapped IMR for masking external and internal interrupts If INTM 0 in ST1 a1 in any IMR bit enables the corresponding interrupt Neither NMI nor RS is included in the IMR because IMR has no effect on these interrupts You can read or write to the IMR Figure 6 3 Interrupt Mask Register IMR Diagram a C541 IMR 15 12 b C542 IMR 15 12 c C543 IMR 15 12 11 SPRU131G Program Memory Addressing 6 29 Interrupts d C545 IMR 15 12 e C546 IMR 15 12 1 f C548 IMR 15 12 1 g C549 IMR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Resvd BMINTI BMINTO BXINT1 BRINT1 HPINT INT3 TXINT TRINT BXINTO BRINTO TINT INT2 INT1 INTO h C5402 IMR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRINT1 TINTI Resvd DMAC5 DMAC4 or INT3 or DMACO BXINTO BRINTO TINTO INT2 INTL DMAC2 DMAC1 i C5410 IMR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRINT1 BXINT2 BRINT2 or or or BXINTO BRINTO TINT INT2 DMAC2 DMAC1 DMACO 5 4 3 2 BXINT2 BRINT2 RSVD or
335. h Pad RAM On Chip DARAM 8K Words On Chip SARAM 24K Words External On Chip ROM DROM 1 or External DROM 0 Reserved DROM 1 or External DROM 0 Memory 3 7 Memory Space Figure 3 6 Extended Program Memory Maps for the C548 and C549 xx 0000 010000 FF 020000 FT 7F 0000 rd e e e Page 0 Pagel Page2 Page 127 32K 3x 3x 3x Wordst Words Wordst a Wordst xx 7FFF O17FFF_ O27FFFy__ 7F7FFFy_ 00 8000 01 8000 02 8000 7F 8000 e e e Page 127 32K Words e e e 00 FFFF 01 FFFF 02 FFFF 7F FFFF XPC 0 XPC 1 XPC 2 XPC 127 t See Figure 3 4 and Figure 3 5 for more information about this on chip memory region These pages available when OVLY 0 when on chip RAM is not mapped in program space or data space When OVLY 1 the first 32K words are all on page 0 when on chip RAM is mapped in program space or data space NOTE When the on chip RAM is enabled in program space all accesses to the region xx 0000 xx 7FFF regardless of page number are mapped to the on chip RAM at 00 0000 00 7FFF 3 8 Memory SPRU131G Figure 3 7 Memory Maps for the C5402 Hex Page 0 Program 0000 Reserved OVLY 1 External OVLY 0 007F 0080 On Chip DARAM OVLY 1 External OVLY 0 3FFF 4000 External FF7F FF80 Interrupts External FFFF MP MC 1 Microprocessor Mode SPRU131G Hex Page 0 P
336. h long FSR pulses however the reception of all bits including the first one is simply delayed until FSR goes low Serial port receive operation with a long FSR pulse is illustrated in Figure 9 11 SPRU131G Serial Port Interface Figure 9 11 Serial Port Receive With Long FSR Pulse eo Kuss X mse 1 X MSE 2 Note that if the packet transmit frequency is increased the inactivity period between the data packets for adjacent transfers decreases to zero This corre sponds to a minimum period between frame sync pulses equivalent to 8 or 16 CLKX R cycles depending on FO that corresponds to a maximum packet frequency at which the serial port may operate At maximum packet frequency transmit timing is a compressed version of Figure 9 5 as shown in Figure 9 12 Figure 9 12 Burst Mode Serial Port Transmit at Maximum Packet Frequency FSX TXM 1 a a a a a ah a a ee aii ae Aaa a ae DX FO 1 XRDY SP a a t a a DXR XSR DXR XSR loaded loaded reloaded reloaded xsrR BSP XSR loaded reloaded SP SP At maximum packet frequency the data bits in consecutive packets are transmitted contiguously with no inactivity between bits The frame sync pulse overlaps the last bit transmitted in the previous packet Maximum packet frequency receive timing is similar and is shown in Figure 9 13 SPRU131G Serial Ports 9 23 Serial Port Interface Figure 9
337. has been transmitted and transmis sions are currently taking data from the second half of the buffer XH 1 The second half of the buffer has been transmitted and trans missions are currently taking data from the first half of the buffer Autobuffering Transmit Enable This control bit enables the autobuffering transmit BXE 0 Autobuffering is disabled and the serial port operates in standard mode BXE 1 Autobuffering is enabled for the transmitter Serial Port Interface Control bits see section 9 3 1 2 Enhanced BSP Features on page 9 37 9 3 2 2 Autobuffering Process SPRU131G The autobuffering process occurs between the ABU and the 2K word block of ABU memory Each time a serial port transfer occurs the data involved is auto matically transferred to or from a buffer in the 2K word block of memory under control of the ABU During serial port transfers in autobuffering mode inter rupts are not generated with each word transferred as they are in standard mode operation This prevents the overhead of having the CPU directly involved in each serial port transfer Interrupts are generated to the CPU only each time one of the half buffer boundaries is crossed Within the 2K word block of ABU memory the starting address and size of the buffers allocated is programmable using the 11 bit address registers AXR and ARR and the 11 bit block size registers BKX and BKR The transmit and receive buffers can reside in independent ar
338. he on chip timer timer stop status TSS A bit in the timer control register TCR that stops and restarts the on chip timer TINT See timer interrupt TRAD TDM receive address register A 16 bit memory mapped register that contains information about the status of the TADD line in the TDM serial port transition register TRN A 16 bit register that holds the transition decision for the path to new metrics to perform the Viterbi algorithm transmit buffer half transmitted XH A bit in the BSP control extension register BSPCE that indicates which half of transmit buffer transmitted transmit mode TXM A bitin the serial port control register SPC buffered serial port control register BSPC and TDM serial port control register TSPC that specifies the source of the frame synchronization transmit FSX pulse D 18 Glossary SPRU131G SPRU131G Glossary transmit ready XRDY A bit in the serial port control register SPC buffered serial port control register BSPC and TDM serial port control register TSPC that transitions from 0 to 1 to indicate the data transmit register DXR contents have been copied to the data transmit shift regis ter XSR and that data is ready to be loaded with a new data word transmit shift register empty XSREMPTY A bit in the serial port control register SPC and buffered serial port control register BSPC that indi cates if the serial port transmitter has experienced underflow
339. he conditions of the conditional return instruction have been tested the two instruction words following the return instruction have already been fetched in the pipeline How these two instruction words are handled depends in part on whether the return is nondelayed or delayed I Nondelayed If all the conditions are met these two instruction words are flushed from the pipeline so that they are not executed and then execution of the calling program continues If the conditions are not met the two instructions are executed instead of the return J Delayed The processor executes the two instructions that follow the return instruction This allows you to avoid flushing the pipeline which requires extra cycles The conditions tested are not affected by the instruc tions following the delayed return eT se nn nn nn es i Note The two words following a delayed instruction cannot be an instruction that causes a PC discontinuity a branch call return or software interrupt Table 6 11 shows the conditional return instruction and the number of cycles needed to execute this instruction Conditional Return Instruction Number of Cycles Condition met Not met Instruction Description Nondelayed Delayed RC D Load PC with the return address at 5 3 3 3 the top of the stack if the condition specified by the instruction is met To allow returns from extended memory there are two far return instructions 1 FRET loads XPC from the
340. he hold state ends However if the processor is in the concurrent hold mode HM 0 and the interrupt vector table is located in internal memory the CPU takes the interrupt regardless of HOLD 6 34 Program Memory Addressing SPRU131G Interrupts Interrupts cannot be processed between the RSBX INTM instruction and the next instruction in a program sequence If an interrupt occurs during the decode phase of RSBX INTM the CPU always completes RSBX INTM as well as the following instruction before the pending interrupt is processed Waiting for these instructions to complete ensures that a return RET can be executed in an ISR before the next interrupt is processed to protect against stack over flow If an ISR ends with an RETE instruction return from ISR with enable the RSBX INTM instruction is unnecessary Similar to an RSBX INTM instruction an SSBX INTM instruction and the instruction that follows it cannot be interrupted cca Note Reset RS is not delayed by multicycle instructions NMI can be delayed by multicycle instructions and by HOLD 6 10 8 Interrupt Operation A Quick Summary SPRU131G Once an interrupt has been passed to the CPU the CPU operates in the follow ing manner see Figure 6 5 on page 6 37 J If amaskable interrupt is requested 1 The corresponding bit in the IFR is set 2 The acknowledgment conditions INTM 0 and IMR bit 1 are tested If the conditions are true the CPU ac
341. he storing of the data from the input pin to the TRCV The TRSR has the same function as the RSR described on page 9 5 I TDM data transmit shift register TXSR The 16 bit TDM data transmit shift register TXSR controls the transfer of the outgoing data from the TDXR and holds the data to be transmitted on the data transmit TDX pin The TXSR has the same function as the XSR described on page 9 5 9 4 3 TDM Serial Port Interface Operation Figure 9 31 a shows the C54x TDM port architecture Up to eight devices can be placed on the four wire serial bus This four wire bus consists of a conventional serial port s bus of clock frame and data TCLK TFRM and TDAT wires plus an additional wire TADD that carries the device addressing information Note that the TDAT and TADD signals are bidirectional signals and are often driven by different devices on the bus during different time slots within a given frame of operation Figure 9 31 TDM 4 Wire Bus i a S TFRM st TADD e S o TCLK 4 TDAT TDAT TFSX TFRM TFSR TADD C54x DSP TCLKX TCLK TCLKR 9 58 Serial Ports SPRU131G SPRU131G Time Division Multiplexed TDM Serial Port Interface The TADD line which is driven by a particular device for a particular time slot determines which device s in the TDM configuration should execute a valid TDM receive during that time slot This is similar to a valid serial port read operation as
342. he transmit address The receive address RA7 RAO refer to Figure 9 32 is the 8 bit value that a device compares to the 8 bit value it samples on the TADD line in a particular slot to determine whether it should execute a valid TDM receive The receive address therefore establishes the slots in which that device may receive dependent on the addresses present in those slots as specified by the transmitting devices This process occurs on each device during every slot The transmit address TA7 TAO refer to Figure 9 32 is the address that the device drives onthe TADD line during atransmit operation on an assigned slot The transmit address establishes which receiving devices may execute a valid TDM receive on the driven data Only one device at a time can drive a transmit address on TADD Each processor bit wise logically ANDs the value it samples on the TADD line with its receive address RA7 RAO If this operation results in a nonzero value then a valid TDM receive is executed on the processor s whose receive addresses match the transmitted address Thus for one device to transmit to another there must be at least one bit in the upper half of the transmitting device s TRTA the transmit address with a value of 1 that matches one bit with a value of 1 inthe lower half of TRTA the receive address of the receiving device This method of configuration of TRTA allows one device to transmit to one or more devices and for any one de
343. hen in an inactive state these pins are at high impedance When the pins are active they provide one of two types of output J Signal Event The EMU0 1 pins can be configured via software to signal internal events In this mode driving one of these pins low can cause devices to signal such events To enable this operation the EMU0 1 pins function as open collector sources External devices such as logic analyz ers can also be connected to the EMU0 1 signals in this manner If such an external source is used it must also be connected via an open collector source J External Count The EMU0 1 pins can be configured via software as totem pole outputs for driving an external counter If the output of more than one device is configured for totem pole operation then these devices can be damaged The emulation software detects and prevents this condi tion However the emulation software has no control over external sources on the EMU0 1 signal Therefore all external sources must be inactive when any device is in the external count mode TI devices can be configured by software to halt processing if their EMUO 1 pins are driven low This feature combined with the signal event output allows one TI device to halt all other TI devices on a given event for system level debugging If you route the EMU0 1 signals between multiple boards they require special handling because they are more complex than normal emulation signals Figure A 11 shows an
344. hip Peripherals sarsii aia siaii ao aa a a ete eens 2 7 1 General Purpose I O Pins 000 cece een tenes 2 7 2 Software Programmable Wait State Generator 22 0000 eee 2 7 3 Programmable Bank Switching Logic 00 cece eee eee eee ee 2 7 4 Hardware Timer 0 c ee eee eee 2 7 5 Clock Generator parapis ete debe ai en pacha cea le h atiee 2 7 6 Direct Memory Access DMA Controller 0000 eee eee eens 2 7 7 Host Port Interface 1 2 0 2 een teens XV Contents xvi 28 paral POMS 00 seated dad dheadstaidincdodebadin dois adineades Maadd saat 2 8 1 Synchronous Serial Ports 0 000 2 8 2 Buffered Serial Ports 0 0 0 cc ccc nra 2 8 3 Multichannel Buffered Serial Ports McBSPs 28 4 TOM Serial PONS su iecnia tind niaii dads Dad Ma data EEE E da 2 9 External Bus Interface 0 annann eet tenes 2 10 IEEE Standard 1149 1 Scanning Logic 0 ccc eee MEMO Yasir sitios Se cect we rene wesc ee eaten eee eaten Poel oats ee ee ke ater Describes the TMS320C54x DSP memory configuration and operation Includes memory maps and descriptions of program memory data memory and I O space Also includes descriptions of the CPU memory mapped registers 3 1 Memory Space sssi riia haai a a aia a ai a a aE a E tenes 3 2 Program Memory sisses ss inini gani ae aeia aE A A A E A AA E E AN Aa 3 2 1 Program Memory Configurability 0 0 eee 3
345. iagrams in this appendix A 2 Design Considerations for Using XDS510 Emulator SPRU131G Designing Your Target System s Emulator Connector 14 Pin Header Table A 1 14 Pin Header Signal Descriptions Emulatort Targett Signal Description State State EMUO Emulation pin 0 l I O EMU1 Emulation pin 1 V0 GND Ground PD Vcc Presence detect Indicates that the emulation O cable is connected and that the target is powered up PD should be tied to Vcc in the target system TCK Test clock TCK is a 10 368 MHz clock O l source from the emulation cable pod This signal can be used to drive the system test clock TCK_RET Test clock return Test clock input to the emu O lator May be a buffered or unbuffered version of TCK TDI Test data input O l TDO Test data output O TMS Test mode select O l TRST Test reset O tI input O output Do not use pullup resistors on TRST it has an internal pulldown device In a low noise environment TRST can be left floating In a high noise environment an additional pulldown resistor may be needed The size of this resistor should be based on electrical current considerations SPRU131G Design Considerations for Using XDS510 Emulator A 3 Bus Protocol A 2 Bus Protocol A 4 The IEEE 1149 1 specification covers the requirements for the test access port TAP bus slave devices and provides certain rules summarized as follows 1 The TMS and TDI inputs are sampled on the r
346. ical speech voice kil applications TMS320 DSP family 1 3 application specific instructions 14 15 ARO AR7 registers definition ARAU See auxiliary register arithmetic unit ARAU and address generation operation ARAUs definition architectural overview architecture 2 1 to 2 12 block diagram 2 2 bus structure CPU internal memory arithmetic logic unit See ALU arithmetic logic unit ALU carry bit C _ 4 12 definition Index 2 X input source 4 10 Y input source 4 11 ARP See also auxiliary register pointer compatible mode 7 61 definition latencies ARP load three cycle latency two cycle latenc zero latency ARR definition ARx updated with no latency example 7 48 ARx updated with one cycle latency example 7 48 ARx updated with two cycle latency example 7 49 ASM See also accumulator shift mode field definition ASM bit field latencies ASM field shift operations 7 69 ASM update no latency one cycle latency assistance autobuffering receiver enable BRE definition autobuffering receiver halt HALTR definition autobuffering transmitter enable BXE definition autobuffering transmitter halt HALTX definition autobuffering unit ABU 9 40 block diagram control register 9 43 definition process circular addressing registers 9 47 auxiliary register file definition auxiliary register pointer ARP definition auxiliary register auxiliary register conflict example auxilia
347. idered an error An exception condition that causes errors in transmitted data occurs when frame sync pulses occur at inappropriate times during a transfer If a transmit is in progress that is XSR data is being driven on DX when a frame sync pulse occurs the transmission is aborted and the data in XSR is lost Then whatever data is in DXR at the time of the frame sync pulse is transferred to XSR DXR to XSR copy and is transmitted Note however that in this case an XINT is generated only if the DXR has been written to since the last transmit Also if XSREMPTY is active and a frame sync pulse occurs the old data in DXR is shifted out Figure 9 18 summarizes serial port transmit behavior under error and non error conditions Note that if an FSX occurs when no transmit is in progress and DXR has been reloaded since the last transmit the DXR to XSR copy and generation of transmit interrupt occur at this point only on the BSP On the SP these two events occur at the time the DXR was reloaded SPRU131G Serial Port Interface Figure 9 18 SP BSP Transmitter Functional Operation Burst Mode FSX pulse occurs New DXR XSREMPTY is low since last DXR to XSR copy transmit occurs No transmit interrupt Start transmit Transmit in progress Yes Abort DXR to XSR copy BSP only transmit Transmit interrupt BSP only Start transmit New DXR written since last transmit DXR to XS
348. ied only by the C54x DSP but can be read by both the C54x DSP and the host The host processor to C54x interrupt This bit can be written only by the host and is not readable by the host or the C54x DSP When the host writes a 1 to this bit an interrupt is generated to the C54x DSP Writing a 0 to this bit has no effect Always read as 0 When the host writes to HPIC both bytes must write the same value See this section for a detailed description of DSPINT function On Chip Peripherals 8 43 Host Port Interface Table 8 23 HPI Control Register HPIC Bit Descriptions Continued Bit Host Access C54x DSP Access Description HINT Read Write Read Write This bit determines the state of the C54x DSP HINT output which can be used to generate an interrupt to the host HINT 0 upon reset which causes the external HINT output to be inactive high The HINT bit can be set only by the C54x DSP and can be cleared only by the host The C54x DSP writes a 1 to HINT causing the HINT pin to go low The HINT bit is read by the host or the C54x DSP as a 0 when the external HINT pin is inactive high and as a 1 when the HINT pin is active low For the host to clear the interrupt however it must write a 1 to HINT Writing a 0 to the HINT bit by either the host or the C54x DSP has no effect See this section for a detailed description of HINT function Because the host interface always performs transfers with 8 bit bytes and the cont
349. ied production devices and tools TMS TMDS This development flow is defined below Device Development Evolutionary Flow TMX The partis an experimental device that is not necessarily representa tive of the final device s electrical specifications TMP The partis a device from afinal silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS The partis a fully qualified production device Support Tool Development Evolutionary Flow TMDX The development support product that has not yet completed Texas Instruments internal qualification testing TMDS The development support product is a fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped with the following disclaimer Developmental product is intended for internal evaluation purposes TMS devices and TMDS development support tools have been fully character ized and the quality and reliability of the device has been fully demonstrated Texas Instruments standard warranty applies to these products EE Note Itis expected that prototype devices TMX or TMP have a greater failure rate than standard production devices Texas Instruments recommends that these devices notbe used in any production system because their expected end use failure rate is still undefined Only qualified production devices should be used ee Development Suppor
350. igh degree of parallelism In addition to these features the versatile addressing modes and instruction set in the C54x improve the overall system performance Topic Page 1 1 TMS320 DSP Family Overview cceceeee eee ences 1 2 1 5 1 2 TMS320C54x DSP Overview 0 0 c0ceeeeeeeeeeeeeaeeees 1 3 TMS320C54x DSP Key Features 0 ceceeeeeeeeeeaees TMS320 DSP Family Overview 1 1 TMS320 DSP Family Overview 1 1 1 1 2 TMS320 DSP family consists of fixed point floating point and multiprocessor digital signal processors DSPs The TMS320 DSP architecture is designed specifically for real time signal processing The following characteristics make this family the ideal choice for a wide range of processing applications Very flexible instruction set Inherent operational flexibility High speed performance Innovative parallel architecture Cost effectiveness C friendly architecture E E E m E E History Development and Advantages of TMS320 DSPs Introduction In 1982 Texas Instruments introduced the TMS32010 the first fixed point DSP in the TMS320 DSP family Before the end of the year Electronic Prod ucts magazine awarded the TMS32010 the title Product of the Year The TMS32010 became the model for future TMS320 DSP generations Today the TMS320 DSP family consists of three supported DSP platforms TMS320C2000 TMS320C5000 and TMS320C6000 Within the C5000
351. igh impedance The HOLD is an external asynchronous input which is not latched The external device must keep HOLD low The external device can determine that the hold state has been entered when it receives a HOLDA signal from the C54x DSP 10 28 External Bus Operation SPRU131G Hold Mode If the C54x DSP is in the middle of a multicycle instruction it finishes the instruction before entering the hold state After the instruction is completed the buses are placed into high impedance This also applies to instructions that become multicycle because wait states are added After HOLD is de asserted program execution resumes at the same instruc tion from which it was halted HOLDA is removed synchronously with HOLD as shown in Figure 10 23 If the setup time is met the processor requires two machine cycles HM 0 or three machine cycles HM 1 before the buses and control signals become valid 10 6 1 Interrupts During Hold All interrupts are disabled while HOLD is active with HM 1 If an interrupt is received during this period the interrupt is latched and remains pending therefore HOLD does not affect any interrupt flags or registers When HM 0 interrupts function normally 10 6 2 Hold and Reset SPRU131G If HOLD is asserted while RS is active normal reset operation occurs internal ly but all buses and control lines remain or become high impedance and HOLDA is asserted as shown in Figure 10 24 a an
352. ility Mode 4 5 15 Memory Mapped Register Addressing Block Diagram 000 cece eens 5 16 Stack and Stack Pointer Before and After a Push Operation 2 0005 5 17 Word Order in Memory 0 0 c cece a e aa a Eea 6 1 Program Address Generation Logic PAGEN Registers 0000eee eee eee 6 2 Interrupt Flag Register IFR Diagram 0 000 c cece teens 6 3 Interrupt Mask Register IMR Diagram 0 0 00 cece eee 6 4 Interrupt Vector Address Generation a n nassu nnan ccc eee e eee 6 5 Flow Diagram of Interrupt Operation sosi sccsisicrisicrcsiirasiarori eini neieines 7 1 Pipeline Stages wince ccacelcneigace ca Hedge d sda pease TE Meee ES E EEE TER 7 2 Pipelined Memory Accesses 000 cece eee eet eee eens 7 3 Half Cycle Accesses to Dual Access Memory 00600 ee eee aee 8 1 External Flag Timing Diagram 0 cc eect eeN 8 2 Timer Control Register TCR Diagram 0 0 cee teens 8 3 Timer Block Diagrami ascen hy craic aca ceakaa sacra Sheet aan a4 Meee nae eee 8 4 Clock Mode Register CLKMD Diagram 000 anunn eects 8 5 PLL Lockup Time Versus CLKOUT Frequency 000 cece cence eee ee aee 8 6 Host Port Interface Block Diagram 0 8 7 Generic System Block Diagram 0 6 cece cette eee eens 8 8 Select Input Logic ss sa srianan anan aia et eee e eens 8 9 HPIC Diagram Host Reads from HPIC 2 keene
353. in RSR is lost If the DRR is read clearing RSRFULL before the next FSR occurs subsequent transfers can be received properly Another type of receive error is caused if frame sync occurs during a receive that is data is being shifted into RSR from DR If this happens the present receive is aborted and anew one begins Thus the data that was being loaded into RSR is lost but the data in DRR is not no RSR to DRR copy occurs Burst mode serial port receiver behavior under normal and error conditions for the SP is shown in Figure 9 16 and for the BSP is shown in Figure 9 17 Figure 9 16 SP Receiver Functional Operation Burst Mode SPRU131G FSR pulse occurs Receive in progress Start new data receive Yes Abort receive Start Set next reception RSRFULL 1 No RSR to DRR Ignore FSR pulse thus 1 word lost Serial Ports 9 27 Serial Port Interface Figure 9 17 BSP Receiver Functional Operation Burst Mode 9 28 Serial Ports FSR pulse occurs Receive in progress Start new data receive Abort receive Start next reception No RSR to DRR thus 1 word lost Ignore FSR pulse Transmitter exception conditions in burst mode may occur for several possible reasons Underflow which is described in section 9 2 3 Configuring the Serial Port Interface on page 9 8 is an exception condition that may occur in burst mode however underflow is not normally cons
354. increment Event HD HR W HCNTL1 0 HBIL HPIC HPIA_ latchi latch2 Host reads data 1st byte FF 1 01 0 0000 1000 AF FE Host reads data 2nd byte FE l 01 1 0000 1000 FF FE Internal HPI RAM read complete 1001 6A BC SPRU131G Inthe access shown in Table 8 27 the data obtained from reading HPID is the data from the read initiated in the previous cycle the one shown in Table 8 26 and the access performed as shown in Table 8 27 also initiates a further read this time at location 1001h because autoincrement was specified in this access by setting HCNTL1 0 to 01 Also when autoincrement is selected the increment occurs with each 16 bit word transferred not with each byte there fore as shown in Table 8 27 the HPIA is incremented by only 1 The last line of Table 8 27 indicates that after the second internal RAM read is complete the contents of location 1001h 6ABCh has been read and placed into the upper and lower byte data latches On Chip Peripherals 8 49 Host Port Interface During a write access to the HPI the first byte data latch is overwritten by the data coming from the host while the HBIL pin is low and the second byte data latch is overwritten by the data coming from the host while the HBIL pin is high At the end of this write access the data in both data latches is transferred as a 16 bit word to the HPI memory at the address specified by the HPIA register The address is incremented prior to the memory write becaus
355. ine 0005 Conditional Branch BC Instruction in the Pipeline 0 0 0 cece eee eee ee Delayed Conditional Branch BCD Instruction in the Pipeline Interrupt Response by the Pipeline Instruction Fetch and Operand Read Operand Write and Dual Operand Read Conflict 0 00 c cece eee eens Operand Write and Operand Read Conflict 0 0 ccc cece eee eens Resolving Conflict When Updating Multiple ARXS 000 0 c cece eee ee Resolving Conflict When Updating ARX and BK 00000 cece eee eee Resolving Conflict When Updating SP BK and ARX 00000 0c cece eee ee ARx Updated With No Latency ARx Updated With a 1 Cycle Latency 00 cece cece ees ARx Updated With and Without a 1 Cycle Latency 0 e eee ee ARx Updated With and Without a 2 Cycle Latency 00 00 e cence eee ARx Updated With a 2 Cycle Latency BK Updated With a 1 Cycle Latency Examples SPRU131G Examples 7 31 SP Load With No Latency in Compiler Mode CPL 1 0000 eee ee eee eee 7 32 SP Load With a 1 Cycle Latency in Compiler Mode CPL 1 2 0055 7 33 SP Load With and Without a 2 Cycle Latency 0 06 cece cece eee 7 34 SP Load With a 2 Cycle Latency in Compiler Mode CPL 1 0055 7 35 SP Load With a 3 Cycle Latency in Compiler Mode CPL 1 DP 0 7 36 SP Load With No
356. ine with the transmit address for each slot This information unlike that on TDAT is only one byte long and is transmitted with the LSB first for the first half of the slot During the second half of the slot that is the last eight TCLK periods the TADD line is driven high The TDM receive logic samples the TADD line only for the first eight TCLK periods ignoring it during the second half of the slot Therefore the transmitting device if not a C54x DSP could drive TADD high or low during that time period Note that like TDAT the first TADD bit transmitted lasts for only one half of one TCLK cycle If no device on the TDM bus is configured to transmit in a slot that is none of the devices has a 1 for the corresponding slot in their TCSR that slot is considered empty In an empty slot both TADD and TDAT are high impedance This condition has the potential for spurious receives however because TDAT and TADD are always sampled and a device performs a valid TDM reception if its receive address matches the address on the TADD line To avoid spurious reads a 1 kilohm pull down resistor mustbe tied to the TADD line This causes the TADD line to read low on empty slots Otherwise any noise on the TADD line that happens to match a particular receive address would result in a spurious read If power dissipation is a concern and the resistor is not desired then an arbitrary processor with transmit address equal to Oh can drive empty slots by wri
357. ing one operand is fed into the multiplier via DB The second operand may come from T as an immediate value or from program memory via PB or from accumulator A For instructions using dual data memory operand addressing DB and CB carry the data into the multiplier The last two cases are used with the FIRS instruction and the SQUR and SQDST instructions The FIRS instruction obtains inputs from PB and accu mulator A The SQUR and SQDST obtain both inputs from accumulator A Table 4 5 Multiplier Input Selection for Several Instructions SPRU131G X Multiplexer Y Multiplexer Case Instruction Type T DB A PB CB DB A 1 MPY 1234h A V V 2 MPY R AR2 A V y 3 MPYA B V V 4 MACP AR2 pmad A V V 5 MPY AR2 AR83 B V V 6 SQUR AR2 B V V 7 MPYA AR2 V N 8 FIRS AR2 AR3 pmad V V 9 SQUR A B V V Central Processing Unit 4 21 Multiplier Adder Unit T provides one operand for multiply and multiply accumulate instructions the other memory operand is a single data memory operand T also provides an operand for multiply instructions with parallel load or parallel store such as LD MAC LD MAS ST MAC ST MAS and ST MPY T can be loaded explicitly by instructions that support a memory mapped register addressing mode or implicitly during multiply operations Since bits A 82 16 can be an input to the multiplier some sequences that require storing the result of one computation in memory and feeding this result to th
358. ing control register BSCR to 1 At reset this bit is cleared to 0 and the external interface clock is enabled See section 10 3 2 Bank Switching Logic on page 10 9 for more information 1 CLKOUT off allows the C54x DSP to disable CLKOUT using software instructions The CLKOFF bit of PMST determines whether CLKOUT is enabled or disabled See section 4 1 2 Processor Mode Status Register PMST on page 4 6 At reset CLKOUT is enabled 6 52 Program Memory Addressing SPRU131G Chapter 7 Pipeline This chapter describes the TMS320C54x DSP pipeline operation and lists the pipeline latency cycles for operations with various registers Topic Page 7 1 Pipeline Operation lt essees cerra easa Sie ne celeeete ss ersisis sels ele isin 7 2 7 2 Interrupts and the Pipeline 0cceeeeeeee ee eeeneees 7 25 7 3 Dual Access Memory and the Pipeline 2 0ceeeeeees 7 4 Single Access Memory and the Pipeline 7 33 Om Pipeline latencies a e ster 7 35 7 1 Pipeline Operation 7 1 Pipeline Operation 7 2 Pipeline The C54x DSP has a six level deep instruction pipeline The six stages of the pipeline are independent of each other which allows overlapping execution of instructions During any given cycle from one to six different instructions can be active each at a different stage of completion The six levels and functions of the pipeline structure are i Program prefe
359. ing from off chip memory is the ability to access a larger memory space Topic Page chu Memory Space ee ee e e E e e B 2 cs Progra M MeMO 3 15 che Data Memory a E 3 22 34 VOMOMOLY ae ea e a E 3 5 Programiand Data Security Sae a a eee ieee le ate alee tere letcleral ete 3 1 Memory Space 3 1 Memory Space Memory The C54x DSP memory is organized into three individually selectable spaces program data and I O Within any of these spaces RAM ROM EPROM EEPROM or memory mapped peripherals can reside either on chip or off chip The program memory space contains the instructions to execute as well as tables used in execution The data memory space stores data used by instructions The I O memory space interfaces to external memory mapped peripherals and can also serve as extra data storage space Depending on the DSP version several on chip memory types are available on the C54x devices dual access RAM DARAM single access RAM SARAM two way shared RAM and ROM The RAMs are always mapped into data space but may also be mapped into program space The ROM may be activated and mapped into program space it can also be mapped in part into data space For device specific on chip memory configurations see the TMS320C54x DSP Functional Overview SPRU307 and the device data sheet There are three CPU status register bits that affect memory configuration The effects of these bits are device specific Th
360. ing of clearing XRST with respect to the clock Figure 9 29 illustrates autobuffering mode initialization timing requirements for the transmitter with external clock and frame sync The figure shows standard mode operation with external frame TXM 0 and clock MCM 0 active high frame sync FSP 0 and data sampled on rising edge CLKP 0 Serial Ports 9 51 Buffered Serial Port BSP Interface Figure 9 29 Autobuffering Mode Initialization Timing 9 3 3 2 9 52 lt _ _ _ 6 CLKOUT 1 2 Serial Port clock cycles XRST XRDY Initialization Examples Serial Ports In order to start or restart BSP operation in standard mode the same steps are performed in software as with initializing the serial port see section 9 2 Serial Port Interface on page 9 4 in addition to which the BSPCE must be initialized to configure any of the enhanced features desired To start or restart the BSP in autobuffering mode a similar set of steps must also be performed in addition to which the autobuffering registers must be initialized As an illustration of the proper operation of a buffered serial port Example 9 3 and Example 9 4 define a sequence of actions This illustration is based on the use of interrupts to handle the normal I O between the serial port and CPU The C545 peripheral configuration has been used as a reference for these examples The examples illustrate initializing the buffered serial port
361. ing the execution of a return instruction Example 7 7 Return RET Instruction in the Pipeline Address Instruction al RET a2 i2 a3 i3 b1 jl 1 2 3 4 5 6 7 8 Prefetch Fetch Decode Access Read Execute BBS RS SP RET PAB at RET DAB SP DB b1 BREI Prefetch Fetch Decode Access Read Execute Pipeline flush PAB a2 pse Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Prefetch Fetch Decode Access Prefetch Fetch Decode Pipeline flush pre a3 RBIS Execute No No Read Execute No No Access Read Execute 7 12 Pipeline SPRU131G SPRU131G Pipeline Operation In Example 7 7 the following events occur Cycle 1 Cycle 2 Cycles 3 and 4 Cycle 5 Cycle 6 Cycles 7 and 8 Cycles 9 and 10 Cycle 11 The PAB is loaded with the address of the return instruc tion The return instruction opcode is fetched Two more instructions i2 and i3 are fetched Although these two instructions are fetched by the device they are not allowed to move past the decode stage and are discarded In cycle 4 SP is incremented represented by SP and DAB is loaded with the contents of SP in order to read the return address from the stack The top of the stack is read using DB The return instruction enters the execution stage of the pipeline The address fetched from the stack is loaded onto PAB This allows for fetching the next instruction j1 from the r
362. inition regional technology centers B 4 program counter PC 6 4 to 6 5 register definition ABU address receive ARR loading address ABU address transmit AXR program counter extension XPC 3 27 3 29 ABU receive buffer size BKR definition ABU transmit buffer size BKX Index 14 autobuffering control 9 43 bank switching control BSCR D 3 BSP control extension BSPCE BSP data receive BDRR BSP data receive shift BRSR BSP data transmit BDXR D 3 BSP data transmit shift BXSR D 5 buffered serial port control BSPC data receive shift RSR data transmit shift XSR definition fast return RTN host port interface address HPIA D 10 host port interface control HPIC instruction IR interrupt flag IFR interrupt mask IMR D 11 processor mode status PMST D 13 repeat counter RC serial port a serial port control SPC D 16 serial port data receive DRR D 8 serial port data transmit DXR D 8 status status 0 STO status 1 ST1 TDM channel select TCSR TDM data receive TRCV D 19 TDM data receive shift TRSR TDM data transmit TDXR D 17 TDM receive address TRAD TDM receive transmit address TRTA D 19 TDM serial port TDM serial port control TSPC temporary T timer control TCR timer counter TIM timer period PRD transition TRN re mapping interrupt vector addresses 6 36 repeat block loops 7 72 repeat counter RC definition D 15 repeat operation See also block repeat opera
363. ins remain in the high impedance state This mode of operation prevents spurious transmits from occurring If a TFRM pulse occurs at an improper time during a frame the TDM port is not able to continue functioning properly since slot and bit numbers become ambiguous when this occurs Therefore only one TFRM should occur every 128 TCLK cycles Unlike the serial port the TDM port cannot be reinitialized with a frame sync pulse during transmission To correct an improperly timed TFRM pulse the TDM port must be reset 9 4 6 Examples of TDM Serial Port Interface Operation 9 64 Serial Ports The following is an example of TDM serial port operation showing the contents of some of the key device registers involved and explaining the effect of this configuration on port operation In this example eight devices are connected to the TDM serial port as shown in Figure 9 34 Table 9 14 shows the TADD value during each of the eight channels given the transmitter and receiver designations shown This example shows the config uration for eight devices to communicate with each other In this example device 0 broadcasts to all other device addresses during slot 0 In subsequent time slots devices 1 7 each communicate to one other processor SPRU131G Time Division Multiplexed TDM Serial Port Interface Figure 9 34 TDM Example Configuration Diagram Device 0 Device 1 Device 2 Device 3 Channel 0 TCSR 01h Channel 7 TCSR 80h Channel 6 TCSR
364. interrupt 23 Software interrupt 24 Software interrupt 25 Software interrupt 26 Software interrupt 27 Software interrupt 28 Software interrupt 29 Software interrupt 30 External user interrupt 0 External user interrupt 1 External user interrupt 2 Internal timer interrupt Buffered serial port 0 receive interrupt Buffered serial port 0 transmit interrupt TDM serial port receive interrupt TDM serial port transmit interrupt External user interrupt 3 HPI interrupt SPRU131G Interrupts Table 6 25 TMS320C549 Interrupt Locations and Priorities Continued TRAP INTR Number K 26 27 28 29 30 31 Table 6 26 TRAP INTR Number K 0 oO O nN O oO FF WO N eae Fe CO a fF o Pe Oo SPRU131G Priority 13 14 15 Location Name Hex Function BRINT1 SINT10 68 Buffered serial port 1 receive interrupt BXINT1 SINT11 6C Buffered serial port 1 transmit interrupt BMINTO SINT12 70 BSP 0 misalignment detection interrupt BMINT1 SINT13 74 BSP 1 misalignment detection interrupt 78 7F Reserved TMS320C5402 Interrupt Locations and Priorities Priority 1 2 Location Name Hex Function RS SINTR 0 Reset hardware and software reset NMI SINT16 4 Nonmaskable interrupt SINT17 8 Software interrupt 17 SINT18 C Software interrupt 18 SINT19 10 Software interrupt 19 SINT20 14 Software interrupt 20 SINT21 18 Software interrupt 21 SINT22 1C Software interrupt 22 SINT23 20 Softwar
365. ion The update is delayed by one cycle 1 2 3 4 5 6 T 8 9 10 Prefetch Fetch Decode Access Read Execute STLM Write to A SP SP Prefetch Fetch Decode Access Read Execute POPM BK write Write to Write to delayed by 1 cycle BK BK Prefetch Fetch Decode Access Read Execute STM 1 AR1 1st word Write to Write to write delayed by 1 cycle AR1 AR1 Prefetch Fetch Decode Access Read Execute Legend Where a write conflict Where the write actually occurs occurs These conflicts are automatically resolved by the C54x CPU This generally does not affect instruction execution behavior However there is one case in which resolution by the CPU can cause an unprotected pipeline conflict This is explained in section 7 5 3 Rules to Determine DAGEN Register Access Conflicts SPRU131G Pipeline 7 43 Pipeline Latencies 7 5 3 Rules to Determine DAGEN Register Access Conflicts Some instructions update DAGEN registers in the read stage This can result in conflict if the previous instruction tries to update a DAGEN register in its execute stage This conflict is automatically resolved by the CPU by delaying the read stage update by one cycle This delay can cause an additional cycle of latency between the instruction that writes to the DAGEN register in its read stage and the instruction that follows it The following set of conditions determines when such a conflict can occur I The first instruction is one of two types HM Store t
366. ion 4 3 Accumulators A and B on page 4 13 for more details about these accumulator features 3 26 Memory SPRU131G Table 3 3 CPU Memory Mapped Registers SPRU131G Address Hex 0 N mmoo 0 FO MN OF ee Ce es Ce Cs Ces Cs Coes Ce Ce moeoOwWwYrGDO DN DON FF WO N O 1E 1F Name IMR IFR STO ST1 AL AH AG BL BH BG T TRN ARO AR1 AR2 AR3 AR4 AR5 AR6 AR7 SP BK BRC RSA REA PMST XPC Data Memory Description Interrupt mask register Interrupt flag register Reserved for testing Status register 0 Status register 1 Accumulator A low word bits 15 0 Accumulator A high word bits 31 16 Accumulator A guard bits bits 39 32 Accumulator B low word bits 15 0 Accumulator B high word bits 31 16 Accumulator B guard bits bits 39 32 Temporary register Transition register Auxiliary register 0 Auxiliary register 1 Auxiliary register 2 Auxiliary register 3 Auxiliary register 4 Auxiliary register 5 Auxiliary register 6 Auxiliary register 7 Stack pointer Circular buffer size register Block repeat counter Block repeat start address Block repeat end address Processor mode status register Program counter extension register C548 C549 C5402 C5410 and C5420 Reserved Memory 3 27 Data Memory 3 3 4 4 Temporary Register T The temporary T register has many uses For example it may hold J One of the multiplicands for multiply and multiply accumulate instructions
367. ions Table 6 16 Conditions for Conditional Store Instructions SPRU131G Operand AEQ BEQ ANEQ BNEQ ALT BLT ALEQ BLEQ AGT BGT AGEQ BGEQ Condition A 0 B 0 Az 0 Bz 0 A lt 0O B lt 0 As0 B lt 0 A gt 0O B gt 0 A20 B20 Description Accumulator A equal to 0 Accumulator B equal to 0 Accumulator A not equal to 0 Accumulator B not equal to 0 Accumulator A less than 0 Accumulator B less than 0 Accumulator A less than or equal to 0 Accumulator B less than or equal to 0 Accumulator A greater than 0 Accumulator B greater than 0 Accumulator A greater than or equal to 0 Accumulator B greater than or equal to 0 Program Memory Addressing 6 19 Repeating a Single Instruction 6 7 Repeating a Single Instruction The C54x DSP includes two instructions RPT and RPTZ that cause the next instruction to be repeated The number of times for the instruction to be repeated is obtained from an operand of the instruction and is equal to this operand 1 This value is stored in the 16 bit repeat counter RC register You cannot program the value in the RC register it is loaded by the repeat instruc tions RPT or RPTZ only The maximum number of executions of a given instruction is 65 536 An absolute program or data address is automatically incremented when the single repeat feature is used Once a repeat instruction is decoded all interrupts including NMI but not RS are disabled until the completion of the repeat loop H
368. ions the conditional branch instruction BC D requires one more cycle than an unconditional one Program Memory Addressing 6 7 Branches Table 6 5 Conditional Branch Instructions Number of Cycles Condition met Not met Instruction Description Nondelayed Delayed BC D Load PC with the address specified by 5 3 3 3 the instruction if the condition speci fied by the instruction is met BANZ D Load PC with the address specified by 4 2 2 2 the instruction if currently selected auxiliary register not equal to 0 useful for loops 6 3 3 Far Branches To allow branches to extended memory there are two far branch instructions 41 FBJ D branches to the extended memory address specified by the the instruction 1 FBACC D branches to the extended memory address specified in the designated accumulator Table 6 6 shows the far branch instructions both nondelayed and delayed and the number of cycles needed to execute these instructions Delayed instructions use two cycles fewer than the corresponding nondelayed instructions Table 6 6 Far Branch Instructions Number of Cycles Instruction Description Nondelayed Delayed FB D Load the PC and the XPC with the 4 2 address specified in the instruction FBACC D Load the PC and the XPC with the 6 4 address specified by the lower 23 bits of the designated accumulator 6 8 Program Memory Addressing SPRU131G 6 4 Calls Calls Like branches calls break the sequ
369. ipheral Memory Mapped Registers Continued Address Hex 3C 3D 3E 3F 40 41 42 43 44 57 58 59 5F Name AXR1 BKX1 ARR1 BKR1 BDRR1 BDXR1 BSPC1 BSPCE1 Description ABU 1 transmit address register ABU 1 transmit buffer size register ABU 1 receive address register ABU 1 receive buffer size register Buffered serial port 1 data receive register Buffered serial port 1 data transmit register Buffered serial port 1 control register Buffered serial port 1 control extension register Reserved Clock mode register Reserved Table 8 7 C549 Peripheral Memory Mapped Registers SPRU131G Address Hex 20 21 22 23 24 25 26 27 28 29 2A 2B Name BDRRO BDXRO BSPCO BSPCEO TIM PRD TCR SWWSR BSCR XSWR Description Buffered serial port 0 data receive register Buffered serial port 0 data transmit register Buffered serial port 0 control register Buffered serial port 0 control extension register Timer count register Timer period register Timer control register Reserved External interface software wait state register External interface bank switching control register Reserved Extended software wait state register On Chip Peripherals 8 9 Peripheral Memory Mapped Registers Table 8 7 C549 Peripheral Memory Mapped Registers Continued Address Hex Name Description 2C HPIC Host port interface control register 2D 2F Reserved 30 TRCV TDM serial port data receive register 31 TDX
370. ircular buffer is specified in circular buffer size register BK SPRU131G Data Addressing 5 21 Indirect Addressing In each case the content of the auxiliary register is used as the data memory operand After using the address in the auxiliary register the ARAUs perform the specified mathematical operation By disabling circular modifications it is possible to perform indexed addressing or the equivalent of ARx 0 Clearing the BK to 0 disables circular modification In instructions that perform dual operand reads if the auxiliary register specified by the Yar field accesses one of the memory mapped registers the value read will not represent the contents of the register See the 7MS320C54x DSP Reference Set Volume 4 Applications Guide for examples of dual operand indirect addressing 5 5 4 1 Dual Operand Increment Decrement Address Modifications Xmod or Ymod 0 1 or 2 You can modify the AR by incrementing or decrementing its value When Xmod or Ymod 0 ARx is used as the data memory address with no incre menting or decrementing When Xmod or Ymod 1 ARx is decremented after the access is made When Xmod or Ymod 2 ARx is incremented after the access is made 5 5 4 2 Dual Operand Indexed Address Modifications Xmod or Ymod 3 and BK 0 When Xmod or Ymod 3 and BK 0 ARO is added to ARx after each access Otherwise dual operand indexed addressing is exactly as described in sec tion 5 5 3 3 on page 5 15
371. ising edge of the TCK signal of the device 1 The TDO output is clocked from the falling edge of the TCK signal of the device When these devices are daisy chained together the TDO of one device has approximately a half TCK cycle setup time before the next device s TDI signal This timing scheme minimizes race conditions that would occur if both TDO and TDI were timed from the same TCK edge The penalty for this timing scheme is a reduced TCK frequency The IEEE 1149 1 specification does not provide rules for bus master emula tor devices Instead it states that the device expects a bus master to provide bus slave compatible timings The XDS510 provides timings that meet the bus slave rules Design Considerations for Using XDS510 Emulator SPRU131G Emulator Cable Pod A 3 Emulator Cable Pod Figure A 2 shows a portion of the emulator cable pod The functional features of the pod are J TDO and TCK_RET can be parallel terminated inside the pod if required by the application By default these signals are not terminated _ TCK is driven with a 74LVT240 device Because of the high current drive 32 mA IQ IoH this signal can be parallel terminated If TCK is tied to TCK_RET you can use the parallel terminator in the pod _ TMS and TDIcan be generated from the falling edge of TCK_RET accord ing to the IEEE 1149 1 bus slave device timing rules J TMS and TDI are series terminated to reduce signal reflections Lj
372. ister Other instructions that load a new value into an AR produce a pipeline laten cy For further information on the pipeline and possible pipeline conflicts see Chapter 7 Pipeline Figure 5 8 shows the ARAUs used to generate an address in the indirect addressing mode using a single data memory operand As the figure shows the main components used for address generation in indirect addressing are the auxiliary register arithmetic units ARAUO and ARAU1 and the auxiliary registers ARO AR7 Figure 5 8 Indirect Addressing Block Diagram for a Single Data Memory Operand ARP 3 ARO BK Ik 1 ARO 16 index 0B 16 DAB 16 16 ARO BK 1 read 16 16 16 16 EAB 16 BK 16 CABUS 32 bit read Data bus DB 16 Data bus EB 16 5 12 Data Addressing SPRU131G Indirect Addressing 5 5 3 Single Operand Address Modifications You can modify the addresses you use in instructions before or after they are accessed or you can leave them unchanged You can modify them by incrementing or decrementing the address by 1 adding a 16 bit offset Ik or indexing with the value in ARO These three types of action combined with taking the action either before or after the access plus the ways of leaving the address unchanged make a total of 16 addressing types each assigned to a value of MOD the 4 bit modification field in the encodi
373. it shift register XSR TDXR TDM data transmit register A 16 bit register used to transmit data through the TDM serial port See also XSR Glossary D 17 Glossary temporary register T A 16 bit register that holds one of the operands for multiply and store instructions the dynamic shift count for the add and subtract instructions or the dynamic bit position for the bit test instruc tions TIM timer counter register A 16 bit memory mapped register that specifies the current count for the on chip timer time division multiplexed TDM A bit in the TDM serial port control register TSPC that enables disables the TDM serial port time division multiplexing The process by which a single serial bus is shared by up to eight C54x devices with each device taking turns to communicate on the bus There are a total of eight time slots channels available During a time slot a given device may talk to any combination of devices on the bus timer divide down register TDDR A4 bitfieldin the timer control register TCR that specifies the timer divide down ratio period for the on chip timer timer interrupt TINT A bitin the interrupt flag register IFR that indicates the timer counter register TIM has decremented past 0 timer prescaler counter PSC A 4 bit field in the timer control register TCR that specifies the count for the on chip timer timer reload TRB A bit in the timer control register TCR that resets t
374. ither of the two categories has zero latency 2 The first instruction can be any C54x DSP instruction SPRU131G Pipeline 7 55 Pipeline Latencies Example 7 36 SP Load With No Latency in Noncompiler Mode CPL 0 a ADD A B This instruction does not create a DAGEN conflict STM 100h SP This SP update does not require any latency according to the above table PSHM ARI b STH A 100h This instruction does not create a DAGEN conflict MVDK 200h SP This SP update does not require any latency according to the above table FRAME 10 Example 7 37 SP Load With and Without a 1 Cycle Latency in Noncompiler Mode CPL 0 a SP Load With a One Cycle Latency STLM A AR1 This instruction causes a DAGEN conflict with the next instruction r 7 MVDK 200h SP This SP update requires a one cycl NOP latency PSHM AR2 b SP Load With No Latency MVDK 200h SP This instruction requires no latency STLM A ARI This instruction was placed after MVDK to avoid a DAGEN conflict PSHM AR2 Example 7 38 SP Load With a 1 Cycle Latency in Noncompiler Mode CPL 0 STLM A ARI This instruction does not affect the pipeline latency for the next instruction STLM B SP This SP update requires a one cycl NOP latency CALA A 7 56 Pipeline SPRU131G Pipeline Latencies 7 5 6 Latencies for Temporary Re
375. itions is important for efficient use of the serial port Because the error conditions differ slightly in burst and continuous modes they are discussed separately SPRU131G Serial Port Interface Burst Mode In burst mode one type of error condition presented in section 9 2 2 Serial Port Interface Operation is receive overrun indicated by the RSRFULL flag This flag is set when the device has not read incoming data and more data is being sent If this condition occurs the processor halts serial port receives until DRR is read Thus any further data sent may be lost Overrun is handled differently on the SP and on the BSP On the SP the contents of RSR are preserved on overrun but since RSRFULL is not set to 1 until the next FSR occurs after the overflowing reception incoming data usually begins being lost as soon as RSRFULL is set Data loss can only be avoided if RSRFULL is polled in software and the DRR is read immediately after RSRFULL is setto 1 This is normally possible only if the CLKR frequency is slow with respect to CLKOUT since RSRFULL is set on the falling edge of CLKR during FSR and data begins being received on the following rising edge of CLKR The time available for polling RSRFULL and reading the DRR to avoid data loss is therefore only half of one CLKR cycle On the BSP RSRFULL is set on the last valid bit received but the contents of RSR are never transferred to DRR therefore the complete transferred word
376. itten to These memory blocks are contiguous in memory with the first block beginning at the start address of SARAM or ROM For more information about memory block ing see section 3 2 2 On Chip ROM Organization on page 3 17 and section 3 3 2 On Chip RAM Organization on page 3 23 Simultaneous accesses with no conflicts are supported by single access memory as long as the access are to different memory blocks while one instruction in a pipeline stage accesses one memory block another instruction can access a different memory block in the same cycle without any conflict A conflict can occur when two simultaneous accesses are performed on the same memory block In case of such a conflict only one access is performed in that cycle and the second access is delayed until the following cycle This results in a one cycle pipeline latency A pipeline conflict due to single access memory may occur in several different situations I Dual Operand instructions Many instructions have two memory oper ands to read or write data If both operands are pointing to the same single access memory block a pipeline conflict occurs The CPU automatically delays the execution of that instruction by one cycle to resolve the conflict For example MAC AR2 AR3 A B This instruction will take two cycles if both operands are in same SARAM or DROM block J 32 bit operand instructions Instructions that read 32 bit memory operands still take only
377. ive restart after overrun Sign extension in DRR on 8 10 or 12 bit transfers XSR load XSREMPTY clear XRDY XINT generation Program accessibility to DXR and DRR Maximum serial port clock rate 9 36 Serial Ports Serial Port RSRFULL is set when RSR is full and then an FSR occurs except in continuous mode where RSRFULL is set as soon as RSR is full RSR contents are preserved on overrun Receive restarts as soon as DRR is read see section 9 2 6 Serial Port Interface Exception Condi tions on page 9 26 No Occur when DXR is loaded DRR and DXR can be read or writ ten under program control at any time Note that caution should be exercised when reads and writes of the DRR may be close in time to serial port receptions In this case a DRR read may not yield the result that was previously written by the program Also note that rewrites of DXR may cause loss and therefore non transmission of previously written data depending on the relative timing of the writes and FSX see section 9 2 4 Burst Mode Transmit and Receive Operations on page 9 18 CLKOUT 4 BSP RSRFULL is set as soon as BRSR is full BRSR contents are not preserved on overrun Receive does not restart until BDRR is read and then a BFSR occurs Yes Occur when when a BFSX occurs after BDXR is loaded BDRR can only be read and BDXR can only be written when the ABU is disabled BDRR can only be written when the BSP
378. k Words Prog Data Prog Data OVL 1 OVL 1 External External OVLY 0 OVLY 0 EMIF t EMIF t 17FFF 27FFF 18000 28000 External EMIF t On Chip 2EFFF SARAM 3 2F000 32k Words External EMIF t 1FFFF extended On Chip SARAM 4 4k Words External EMIF t 2FFFF extended Hex Program Page 3 30000 On Chip DARAM 0 16k Words Prog Data OVLY 1 External OVLY 0 EMIF t 33FFF 34000 On Chip SARAM 1 16k Words Prog Data OVL 1 External OVLY 0 EMIF t 37FFF 38000 External EMIF t 3FFFF extended vo 64k External 1 0 Ports EMIF t t EMIF external memory mode is required for all external accesses EMIF mode is when XIO pin 1 and the MP MC bit is 1 A OVLY 1 overlays the data page and all program pages between addresses 0x0000 0x7FFF B DROM 1 overlays 0x8000 OxFFFF of program and data memory C All internal memory is divided into 8K blocks with the exception of the 4K W block on P2 0x2F000 0x2FFFF 3 14 Memory SPRU131G Program Memory 3 2 Program Memory The external program memory on most C54x devices can address up to 64K 16 bit words The C54x devices have on chip ROM dual access RAM DARAM single access RAM SARAM and two way shared RAM that can be mapped by software into the program memory space Table 3 1 shows the on chip program memory available on the various C54x devices For device specific on chip program memory confi
379. k when a breakpoint is encountered in the HLL debugger When the Free bit is cleared to 0 the Soft bit selects the emulation mode See Table 9 6 on page 9 17 for the serial port clock configurations Soft 0 The serial port clock stops immediately thus aborting any transmission Soft 1 The clock stops after completion of the current transmission Receive Shift Register Full This bit indicates whether the receiver has experi enced overrun Overrun occurs when RSR is full and DRR has not been read since the last RSR to DRR transfer On the SP when FSM 1 the occurrence of a frame sync pulse on FSR qualifies the generation of RSRFULL 1 When FSM 0 and on the BSP only the basic two conditions apply that is RSRFULL goes high with out waiting for an FSR pulse RSRFULL 0 Any one of the following three events clears the RSRFULL bit to 0 reading DRR resetting the receiver RRST bit to 0 or resetting the device RSRFULL 1 The port has recognized an overrun When RSRFULL 1 the receiver halts and waits for DRR to be read and any data sent on DR is lost On the SP the data in RSR is preserved on the BSP the contents of RSR are lost Transmit Shift Register Empty This bit indicates whether the transmitter has expe rienced underflow Underflow occurs when XSR is empty and DXR has not been loaded since the last DXR to XSR transfer XSREMPTY 0 Any one of the following three events clears the XSREMPTY bit to 0 und
380. knowledges the interrupt generating an IACK signal otherwise it ignores the interrupt and continues with the main program 3 When the interrupt has been acknowledged its flag bit in the IFR is cleared to 0 and the INTM bit is set to 1 to block other maskable inter rupts 4 The PC is saved on the stack 5 The CPU branches to and executes the interrupt service routine ISR 6 The ISR is concluded by a return instruction which pops the return address off the stack 7 The CPU continues with the main program J If anonmaskable interrupt is requested 1 The CPU immediately acknowledges the interrupt generating an IACK signal 2 Ifthe interrupt was requested by RS NMI or the INTR instruction the the INTM bit is set to 1 to block maskable hardware interrupts Program Memory Addressing 6 35 Interrupts If the INTR instruction has requested one of the maskable interrupts the corresponding flag bit is cleared to 0 The PC is saved on the stack The CPU branches to and executes the ISR The ISR is concluded by a return instruction which pops the return address of the stack Oo oO A Se TS aS 7 The CPU continues with the main program S SSa2_____VjjaqFaxu__a_1_ _ ____ a a a Se a a a a a a a eS Note The INTR instruction disables maskable interrupts by setting the interrupt mode bit INTM but the TRAP instruction does not affect INTM eee eee eee sss 6 10 9 Re mapping Inte
381. l Gia MCM CLKX The FO bit 2 specifies whether data is transmitted as 16 bit words FO 0 or 8 bit bytes FO 1 Note that in the latter case only the lower byte of what ever is written to DXR is transmitted and the lower byte of data read from DRR is what was received To transmit a whole 16 bit word in 8 bit mode two writes to DXR are necessary with the appropriate shifts of the value because the upper eight bits written to DXR are ignored Similarly to receive a whole 16 bit word in 8 bit mode two reads from DRR are required with the appropriate shifts of the value In the SP the upper eight bits of DRR are indeterminate in 8 bit receptions in the BSP the unused bits of DRR are sign extended Additionally in the BSP transfers of 10 and 12 bit words are provided for additional flexibility For a detailed description of this feature refer to section 9 3 Buffered Serial Port BSP Interface on page 9 33 The FSM bit 3 specifies whether or not frame sync pulses are required in consecutive serial port transmits If FSM 1 a frame sync must be present for every transfer although FSX may be either externally or internally generated depending on TXM This mode is referred to as burst mode because there are normally periods of inactivity on the serial port between transmits The frequency with which serial port transmissions occur is called packet frequency and data packets can be 8 10 12 or 16 bits long Therefore a
382. l with a sequential set of instructions each at one of the six stages When a PC discontinuity occurs such as during a branch call or return one or more stages of the pipe line may be temporarily unused For more details about the pipeline operation see Chapter 7 Pipeline Architectural Overview 2 11 On Chip Peripherals 2 7 On Chip Peripherals All the C54x devices have a common CPU but different on chip peripherals are connected to their CPUs The C54x devices may have these or other on chip peripheral options General purpose I O pins Software programmable wait state generator Programmable bank switching logic Clock generator Timer Direct memory access DMA controller Standard serial port Time division multiplexed TDM serial port Buffered serial port BSP Multichannel buffered serial port McBSP Host port interface 83 bit standard HPI E 8 bit enhanced HPI8 mM 16 bit enhanced HPI16 O O O O O O O O O O O For device specific on chip peripheral configurations see the device data sheet For more detailed information on the peripherals see TMS320C54x DSP Enhanced Peripherals Reference Guide SPRU302 2 7 1 General Purpose I O Pins The C54x device provides general purpose I O pins that can be read or written through software control All C54x devices support two GPIO pins g BIO A general input upon which conditional instructions can be based O XF An external flag output that can be
383. lator circuit the clock source is divided by 2 to generate the internal CPU clock If you are using the external clock the inter nal CPU clock is a factor of PLL x N The PLL has a maximum operating frequency of 40 MHz on a 25 ns C54x device The PLL requires a transitory locking time of 50 us The locking time is necessary during reset and recovery from the IDLE3 power down mode See section 6 11 Power Down Modes on page 6 50 and section 10 5 2 IDLE3 on page 10 26 for more information The clock mode is determined by the CLKMD1 CLKMD2 and CLKMD3 pins Table 8 15 shows how these pins select the clock mode For non PLL use the frequency of the CPU clock is half the crystal s oscillating frequency or the external clock frequency The clock mode must not be reconfigured with the clock mode pins during normal operation During IDLE3 mode the clock mode can be reconfigured after CLKOUT is set high 8 26 On Chip Peripherals SPRU131G Clock Generator Table 8 15 Clock Mode Configurations Mode Select Pins Clock Modet CLKMD1 CLKMD2 CLKMD3 Option 1 Option 2 0 0 0 PLL x 3 with external source PLL x 5 with external source 1 1 0 PLL x 2 with external source PLL x 4 with external source 1 0 0 PLL x 3 with oscillator enabled PLL x 5 with oscillator enabled 0 1 0 PLL x 1 5 with external source PLL x 4 5 with external source 0 0 1 Divide by 2 with external source Divide by 2 with external source 1 1 1 Divide by 2 with oscillator enabl
384. lds serial data to be transmitted from the BDX pin See also BDXR C See carry bit C16 A bit in status register 1 ST1 that determines whether the ALU operates in dual 16 bit mode or in double precision mode CAB Caddress bus Abus that carries addresses needed for accessing data memory carry bit C A bit in status register 0 STO used by the ALU in extended arithmetic operations and accumulator shifts and rotates The carry bit can be tested by conditional instructions CB C bus Abus that carries operands that are read from data memory circular buffer size register BK A 16 bit register used by the auxiliary register arithmetic units ARAUs to specify the data block size in circular addressing CLKDV See internal transmit clock division factor CLKP See clock polarity CLKOUT off CLKOFF A bit in processor mode status register PMST that enables disables the CLKOUT output Glossary D 5 Glossary D 6 Glossary clock generator A device consisting of an internal oscillator and a phase locked loop PLL circuit driven internally by a crystal resonator with the internal oscillator or externally by a clock source clock mode MCM A bit in the serial port control register SPC buffered serial port control register BSPC and TDM serial port control register TSPC that specifies the source of the clock for CLKX clock polarity CLKP A bitin the BSP control extension register BSPCE that indicate
385. lds the address to be put on the EAB to address data memory for reads via the EB EB Ebus A bus that carries data to be written to memory exponent encoder EXP A hardware device that computes the exponent value of the accumulator external interrupt A hardware interrupt triggered by a pin INTO INT3 fast Fourier transform FFT An efficient method of computing the discrete Fourier transform which transforms functions between the time domain and frequency domain The time to frequency domain is called the forward transform and the frequency to time domain is called the inverse transformation See also butterfly fast return register RTN A 16 bit register used to hold the return address for the fast return from interrupt RETF D instruction SPRU131G SPRU131G Glossary FE See format extension FIG See frame ignore format FO A bitin the serial port control register SPC buffered serial port control register BSPC and TDM serial port control register TSPC that specifies the word length of the serial port transmitter and receiver format extension FE A bitin the BSP control extension register BSPCE used in conjunction with the format bit FO to specify the word length of the BSP serial port transmitter and receiver frame ignore FIG A bit in the BSP control extension register BSPCE used only in transmit continuous mode with external frame and in receive continuous mode frame synchronization
386. learing INTM to 0 Atreset TIM and PRD are set to a maximum value of FFFFh The timer divide down ratio TDDR field of the TCR is cleared to 0 and the timer is started SPRU131G On Chip Peripherals 8 25 Clock Generator 8 5 Clock Generator The clock generator allows system designers to select the clock source The sources that drive the clock generator are J Acrystal resonator with the internal oscillator circuit The crystal resonator circuit is connected across the X1 and X2 CLKIN pins of the C54x DSP The CLKMD pins must be configured to enable the internal oscillator J An external clock The external clock source is directly connected to the X2 CLKIN pin and X1 is left unconnected The clock generator on the C54x devices consists of an internal oscillator and a phase locked loop PLL circuit Currently there are two different types of PLL circuits on C54x devices Some devices have hardware configurable PLL circuits while others have software programmable PLL circuits 8 5 1 Hardware Configurable PLL The PLL functions with a lower external frequency source than the machine cycle rate of the CPU This feature reduces high frequency noise from a high speed switching clock The internal oscillator or the external clock source is fed into the PLL The internal CPU clock is generated by multiplying the exter nal clock source or the internal oscillator frequency by a factor N PLL x N If you are using the internal oscil
387. ling sequence of code PC 1 is pushed onto the stack and PC is loaded with the lower 16 bit word of accumulator A or B The return instruction pops the top of the stack back into PC to return to the calling sequence of code PC is pushed onto the stack and PC is loaded with the address of the appropriate trap vector The return instruction pops the top of the stack back into PC to return to the interrupting sequence of code SPRU131G Program Counter PC The XPC is a 7 bit register that selects the extended page of program memory for the C548 C549 C5402 C5410 and C5420 For more information about extended program memory in these devices see section 3 2 5 Extended Program Memory on page 3 20 The XPC can be loaded in several ways in conjunction with the loading of the PC Table 6 3 lists operations that load XPC Table 6 3 Loading Addresses into XPC SPRU131G Code Operation Reset Sequential execution Far branch Far branch from accu mulator Far subroutine call Far subroutine call from accumulator Far return Address Loaded to the PC PC is loaded with FF80h XPC is loaded with Oh PC is loaded with PC 1 XPC is not automatically incremented PC is loaded with bits 15 0 of the immediate value direct ly following the branch instruction XPC is loaded bits 23 16 of that value PC is loaded with bits 15 0 of accumulator A or B XPC is loaded with bits 23 16 of accumulator A or B PC
388. llowed by a dual operand read instruction This is shown in Example 7 20 in which AR3 and AR5 point to the same dual access memory block There is aconflict between the operand write access EB bus and the second data read access CB bus This conflict is resolved automatically by delaying the write access by one cycle The actual execution time of these instructions does not increase because the delayed write access is performed while the second instruction is in the execute stage If any read access via DB or CB is from the same memory location in on chip memory where the write access should occur the CPU bypasses reading the actual memory location instead it reads the data directly from an internal bus This allows the pipeline to perform a write access in a later pipeline stage than that in which the next instruction reads from the same memory location SPRU131G Dual Access Memory and the Pipeline Example 7 20 Operand Write and Dual Operand Read Conflict STL A AR3 LD 0 A ADD AR4 AR5 A AR3 and AR5 both point to the same dual access memory block Prefetch Fetch Decode Access Read Execute STL A AR3 mig ai FRYER oes eer Pf tt SAS Prefetch Fetch Decode Access Read Execute LD 0 A write access of previous A eE ERAS ngre ef tt ieee Prefetch Fetch Decode Access Read Execute ADD AR4 AR5 A m TT 6h lc Legend Where an access is supposed to occur Where an access actually occurs 7 3 3
389. llowed to execute However if the tested conditions are false i5 and i6 are not decoded SPRU131G Pipeline 7 19 Pipeline Operation To execute XC in one cycle the CPU evaluates test conditions in the access stage of the pipeline This means that the two 1 word instructions or one 2 word instruction immediately prior to the XC instruction will not have com pletely executed before the conditions are tested Because the condition codes are affected only by instructions in the execute stage those two instruc tions have no effect on the operation of XC 7 1 5 Conditional Call and Conditional Branch Instructions in the Pipeline 7 20 Pipeline Because a call instruction consists of two instruction words you would expect it to take at least two cycles to execute completely A standard conditional call instruction actually takes either five cycles to execute if the call is taken or three cycles to execute if the call is not taken Example 7 14 shows pipeline behavior during the execution of a conditional call instruction CC A conditional call instruction is similar in its pipeline behavior to an unconditional call instruction The only exception is that the test conditions for aconditional call instruction are evaluated in the execute stage of the pipeline As shown in Example 7 14 when the test conditions are evaluated in cycle 7 the previous instruction i1 has completely executed Furthermore the next two instructions aft
390. located elsewhere In this case a branch type instruction in the interrupt vector table This would result in a slightly higher interrupt overhead Pipeline 7 25 Interrupts and the Pipeline Example 7 18 Interrupt Response by the Pipeline Address Instruction al i1 Interrupt taken after executing this instruction a2 i2 a3 i3 a4 i4 vecti RETFD First instruction in the interrupt vector table vect2 ji vect3 j2 4 2 3 4 5 6 7 8 9 10 1 12 13 Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute INTR 23 ip IR INTR eS x inserted PAB a2 RIN a2 SP EAB SP EB RTN Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute pe Fetch Decode Access Read Execute PAB PB IR SP RETFD RETFD RETED RdRTN INTM 0 Prefetch Fetch Decode Access Read Execute F PAB gt j Prefetch Fetch Decode Access Read Execute A PAB R o j Prefetch Fetch Decode Access Read Execute weee ee T Te 7 26 Pipeline SPRU131G Dual Access Memory and the Pipeline 7 3 Dual Access Memory and the Pipeline The C54x DSP features on chip memory that supports two accesses in a single cycle This dual access memory is organized as several independent memory blocks Simultaneous accesses to different blocks are supported with no conflicts while one instruction in the pipeline accesses one block another instruction at the same stage in the pipeline c
391. low flag OVA OVB in status register STO is set for the destina tion accumulator and remains set until one of the following occurs m A reset is performed A conditional instruction such as a branch a return a call or an execute is executed on an overflow condition The overflow flag OVA OVB is cleared ES _ lt o o aeooo So 00000000 oe MG hOr TTC Ch Note You can saturate the accumulator by using the SAT instruction regardless of the value of OVM fe The ALU has an associated carry bit C thatis affected by most arithmetic ALU instructions including rotate and shift operations The carry bit supports efficient computation of extended precision arithmetic operations The carry bit is not affected by loading the accumulator performing logical operations or executing other nonarithmetic or control instructions so it can be used for overflow management Two conditional operands C and NG enable branching calling returning and conditionally executing according to the status set or cleared of the carry bit Also the RSBX and SSBxX instructions can be used to load the carry bit The carry bit is set on a hardware reset ode For arithmetic operations the ALU can operate in a special dual 16 bit arith metic mode that performs two 16 bit operations for instance two additions or two subtractions in one cycle You can select this mode by setting the C16 field of ST1
392. lows the device to operate with lower power consumption When XRST RRST MCM 0 power requirements are further reduced since CLKX is no longer driven as an output In IDLE2 and IDLE3 mode SP operation halts as with other parts of the C54x device On the BSP however if the external serial port clock is being used operation continues after an IDLE2 3 is executed This allows power savings to still be realized in IDLE2 3 while still maintaining operation of critical serial port functions if necessary see section 9 3 Buffered Serial Port BSP Inter face on page 9 33 for further information about BSP operation It should also be noted that on the SP the serial port may be taken out of reset at any time Depending on the timing of exiting reset however a frame sync pulse may be missed On the BSP for receive and transmit with external frame sync a setup of at least one CLKOUT cycle plus 1 2 serial port clock cycle is required prior to FSX being sampled active in standard mode In autobuffering mode additional setup is required see section 9 3 Buffered Serial Port BSP Interface on page 9 33 for further information about BSP initialization timing requirements INO bit 8 and IN1 bit 9 allow the CLKR and CLKxX pins to be used as bit inputs INO and IN1 reflect the current states of the CLKR and CLKX pins The data on these pins can be sampled by reading the SPC This can be accomplished using the BIT BITF BITT or
393. lues used by the second instruction are correct LSB east significant bit The lowest order bit in a word maskable interrupts A hardware interrupt that can be enabled or disabled through software McBSP See multichannel buffered serial port MCM See clock mode memory map A map of the addressable memory space accessed by the C54x CPU partitioned according to functionality memory registers etc Glossary D 11 Glossary memory mapped register MMR The C54x CPU registers mapped into page 0 of the data memory space microcomputer mode A mode in which the on chip ROM is enabled and addressable for program accesses microprocessor microcomputer MP MC A bit in the processor mode status register PMST that indicates whether the processor is operating in microprocessor or microcomputer mode See also microcomputer mode microprocessor mode microprocessor mode A mode in which the on chip ROM is disabled for program accesses micro stack A stack that provides temporary storage for the address of the nextinstruction to be fetched when the program address generation logic is used to generate sequential addresses in data space MSB most significant bit The highest order bit in a word multichannel buffered serial port McBSP High speed full duplexed buffered serial ports that allow direct interface to other C54x devices codecs and other devices in a system The McBSPs provide full duplex communication multi
394. m x x x x x x cH7 cHe CH5 OAE TRTA aco TA5 TA4 Tas TA2 TAI TAO RAG RAS RA4 RA3 RAZ RAI ZEAE ESE aes eee Note 9 60 X Don t care Serial Ports When TDM mode is selected the DLB and FO bits in the TSPC are hard configured to 0 resulting in no access to the digital loopback mode and in a fixed word length of 16 bits a different type of loopback is discussed in the example in section 9 4 6 on page 9 64 Also the value of FSM does not affect the port when TDM 1 and the states of the underflow and overrun flags are indeterminate section 9 4 5 TDM Serial Port Interface Exception Conditions on page 9 64 explains how exceptions are handled in TDM mode If TDM 1 changes made to the contents of the TSPC become effective upon completion of channel 7 of the current frame Thus the TSPC value cannot be changed for the current frame any changes made will take effect in the next frame The source device for the TCLK and TFRM timing signals is set by the MCM and TXM bits respectively The TCLK source device is identified by setting the MCM bit of its TSPC to 1 Typically this device is the same one that supplies the TDM port clock signal TCLK The TCLKX pin is configured as an input if MCM 0 and an output if MCM 1 In the latter case internal C54x clock the device whose MCM 1 supplies the clock TCLK frequency one fourth of CLKOUT frequency for all devices on the TDM bus The clock can be sup
395. marizes the relationship between BNKCMP the address bits to be compared and the bank size BNKCMP values not listed in the table are not allowed Table 10 7 lists the state of the ports when the external bus inter face is disabled EXIO 1 Table 10 6 Relationship Between BNKCMP and Bank Size BNKCMP Bit1S Biti4 Bit13 Bit 12 MSBs to Compare 16 Bit Words 0 0 0 0 None 64K 1 0 0 0 15 32K 1 1 0 0 15 14 16K 1 1 1 0 15 13 8K 1 1 1 1 15 12 4K 10 10 External Bus Operation SPRU131G External Bus Control Table 10 7 State of Signals When External Bus Interface is Disabled EXIO 1 SPRU131G Signal State State A 22 0 Previous state High level D 15 0 High impedance High level PS DS IS High level High level MSTRB IOSTRB High level The EXIO and BH bits control the use of the external address and data buses These bits should be set to 0 for normal operation To reduce power dissipa tion especially if external memory is never or only infrequently accessed EXIO and BH can be set to 1 When the EXIO bit in BSCR is set to 1 the CPU cannot modify the the HM bit in ST1 and cannot modify the memory map by changing the value of the DROM MP MC and OVLY bits in PMST The C54x DSP has an internal register that contains the MSBs as defined by the BNKCMP field of the last address used for a read or write operation in program or data space If the MSBs of the address used for the current read do not match those contained in thi
396. memory serial port interface An on chip full duplex serial port interface that provides direct serial communication to serial devices with a minimum of external hardware such as codecs and serial analog to digital A D and digital to analog D A converters Status and control of the serial port is specified in the serial port control register SPC serial port receive interrupt RINT RINTO RINT1 A bit in the interrupt flag register IFR that indicates the data receive shift register RSR contents have been copied to the data receive register DRR RINTO corresponds to synchronous serial port 0 RINT1 corresponds to synchro nous serial port 1 Glossary D 15 Glossary serial port transmit interrupt XINT XINTO XINT1 A bit in the interrupt flag register IFR that indicates the the data transmit register DXR contents has been copied to the data transmit shift register XSR XINTO corresponds to synchronous serial port 0 XINT1 corresponds to synchro nous serial port 1 shared access mode SAM The mode thatallows both the C54x DSP and the host to access HPI memory In this mode asynchronous host accesses are synchronized internally and in case of conflict the host has access priority and the C54x DSP waits one cycle shared access mode SMOD A bitin the HPI control register HPIC that enables disables the shared access mode SAM See also shared access mode SAM and host only mode HOM shifter A hardware
397. ming serial data from the RSR to be written to the data bus At reset the DRR is cleared Data transmit register DXR The 16 bit memory mapped data transmit register DXR holds the outgoing serial data from the data bus to be loaded in the XSR At reset the DXR is cleared Serial port control register SPC The 16 bit memory mapped serial port control register SPC contains the mode control and status bits of the serial port Data receive shift register RSR The 16 bit data receive shift register RSR holds the incoming serial data from the serial data receive DR pin and controls the transfer of the data to the DRR Data transmit shift register XSR The 16 bit data transmit shift register XSR controls the transfer of the outgoing data from the DXR and holds the data to be transmitted on the serial data transmit DX pin During normal serial port operation the DXR is typically loaded with data to be transmitted on the serial port by the executing program and its contents read automatically by the serial port logic to be sent out when a transmission is initiated The DRR is loaded automatically by the serial port logic with data received on the serial port and read by the executing program to retrieve the received data Serial Ports 9 5 Serial Port Interface At times during normal serial port operation however it may be desirable for a program to perform other operations with the memory mapped serial port registers be
398. mode FSM A bitin the serial port control register SPC buffered serial port control register BSPC and TDM serial port control register TSPC that specifies whether frame synchronization pulses FSX and FSR are required for serial port operation frame synchronization polarity FSP A bit in the BSP control extension register BSPCE that determines the status of the frame synchroniza tion FSX and FSR pulses fractional mode FRCT A bit in status register 1 ST1 that determines whether or not the multiplier output is left shifted by one bit Free bit A bit in the serial port control register SPC buffered serial port control register BSPC timer control register TCR and TDM serial port control register TSPC used in conjunction with the Soft bit to determine the state of the serial port or timer clock when a breakpoint is encoun tered in the high level language debugger See also Soft bit FSM See frame synchronization mode FSP See frame synchronization polarity general purpose input output pins Pins that can be used to supply input signals from an external device or output signals to an external device These pins are not linked to specific uses rather they provide input or output signals for a variety of purposes These pins include the general purpose BIO input pin and XF output pin Glossary D 9 Glossary D 10 Glossary HALTR See autobuffering receiver halt HALTX See autobuffering transmitt
399. mory operands are accessed the C54x DSP enters the hold state externally but program execution continues internally Thus a program can continue executing while an external operation is performed This makes the system operation more efficient Program execution ceases until HOLD is removed if the C54x DSP is in a hold state with HM 0 and an internally executing program requires an external access or a branch to an external address Also if a repeat instruction that requires the use of the external bus is executing with HM 0 when a hold occurs the hold state is entered after the current bus cycle If a hold occurs when a repeat instruction is executing with HM 1 the C54x DSP halts the execution after the current bus cycle for either internal or external accesses Upon reset HM is cleared to 0 HM is set and reset by the SSBX and RSBX instructions respectively HOLD is not treated as an interrupt The hold is accepted while executing the IDLE1 instruction regardless of the HM values The hold is not accepted while executing the IDLE2 or IDLE3 instructions regardless of the HM value If HOLD is received the CPU continues to execute the IDLE instruction even though the external buses and the control signals are placed in high impedance Figure 10 23 shows the timing for HOLD and HOLDA If HOLD meets the set up time before CLKOUT is low a minimum of three machine cycles are needed before the buses and control signals go into h
400. mulator B definition guard bits 8 26 high word 3 27 low word accumulator B guard bits BG definition accumulator B high word BH definition D 3 accumulator B low word BL definition accumulator guard bits AG definition D 1 accumulator shift mode ASM 4 5 definition accumulator store with shift example accumulators 4 13 to 4 15 application specific instructions saturation shift and rotate operations rotate accumulator left K 14 rotate accumulator left with TC rotate accumulator right shift arithmetically 4 14 shift conditionally 4 14 shift logically f 14 storing contents adder definition address definition address modification bit reversed circular 5 15 increment decrement indexed offset address visibility mode AVIS definition addresses buses Index 1 Index addressing mode absolute addressing 5 4 accumulator addressing 5 6 definition direct addressing immediate addressing_ 5 2 indirect addressing memory mapped register addressing addressing modifications addressing program 3 18 to 3 20 AG register AH register 3 26 AL register 3 26 ALU BO E 10 t0 4 12 block diagram _ 4 10 carry bit C input sources 4 10 X input source Y input source ALU input selection example ADD instruction table analog to digital converter definition application s automotive _ viiil xiii consumer viiil Ixiii development support vil xiv general purpose ix med
401. n is used to turn off the PLL at this point Example 8 1 Switching Clock Mode From PLL x 3 Mode to Divide by 2 Mode STM 0b CLKMD switch to DIV mode TstStatu LDM CLKMD A AND 01b A poll STATUS bit BC TstStatu ANEQ STM 0b CLKMD reset PLLON OFF when STATUS is DIV mode Changing the PLL Multiplier Ratio SPRU131G When switching from one PLL multiplier ratio to another multiplier ratio is required the clock generator must first be switched from PLL mode to DIV mode before selecting the new multiplier ratio switching directly from one PLL multiplier ratio to another multiplier ratio is not supported In order to switch from one PLL multiplier ratio to another multiplier ratio the following steps must be followed 1 Clear the PLLNDIV bit to 0 selecting DIV mode 2 Poll the PLLSTATUS bit until a 0 is obtained indicating that DIV mode is enabled 3 Modify CLKMD to set the PLLMUL PLLDIV and PLLNDIV bits to the desired frequency multiplier as shown in Table 8 19 on page 8 30 4 Set the PLLCOUNT bits to the required lock up time On Chip Peripherals 8 33 Clock Generator Once the PLLNDIV bit is set the PLLCOUNT timer begins being decremented from its preset value When the PLLCOUNT timer reaches 0 the new PLL mode takes effect after 6 CLKIN cycles plus 3 5 PLL cycles Note that a direct switch between divide by 2 mode and divide by 4 mode is not possible To switch between these two m
402. n 8 5 2 When an interrupt pin goes low an internal counter counts the input clock cycles The initial value loaded in the counter depends on the PLL multiplication factor to ensure the counter down time is greater than 50 us for a 40 MIPS DSP Table 10 8 Counter Down Time With PLL Multiplication Factors at 40 MHz Operation PLL Equivalent Counter Counter Multiplication CLKOUT Down Time Start Value Factor Cycles N at 40 MHz us 2048 1 2048 51 2 2048 1 5 3072 76 8 1024 2 2048 S12 1024 2 5 2560 64 1024 S 3072 76 8 512 4 2048 51 2 512 4 5 2304 DAs 512 5 2560 64 The counter down times in Table 10 8 are valid when the input clock frequen cy is such that the CLKOUT frequency is 40 MHz when the PLL is locked After the counter counts down to 0 the output from the locked PLL is fed to the inter nal logic 10 26 External Bus Operation SPRU131G Figure 10 22 SPRU131G Start Up Access Sequences A low pulse minimum duration of 10 ns of an external interrupt causes the C54x CPU to wake up from IDLE3 see Figure 10 22 The locked PLL clock is fedinto the CPU after ncycles An additional three cycles are needed before the C54x CPU comes out of IDLE3 However the C54x CPU does not need an extra two cycles for interrupt synchronization because the interrupt pulse initializes the interrupt synchronization which is used to detect the interrupt immediately after the C54x CPU wake up When reset is used to wake up from IDLE3 the cou
403. n Figure 8 3 TIM is clocked by the prescaler block Each output clock from the prescaler block decrements TIM by 1 The output of the main timer block is the timer interrupt TINT signal that is sent to the CPU and to the timer output TOUT pin The duration of the TOUT pulse is equal to the period of CLKOUT Note that on the C5402 the timer1 output TOUT1 is only available when the HPI 8 is disabled and the TOUT1 bit is set in the GPIO control register On Chip Peripherals 8 23 Timer The prescaler block has two elements similar to the TIM and PRD These are the prescale counter PSC and timer divide down ratio TDDR Both PSC and TDDR are fields in the timer control register TCR Under normal opera tion PSC is loaded with the contents of TDDR when PSC decrements to 0 The contents of TDDR are also loaded into PSC when the device is reset or when the timer is individually reset PSC is clocked by the device CPU clock Each CPU clock decrements PSC by 1 PSC can be read by reading TCR but it can not be written to directly The timer can be stopped by making use of the TSS input to turn off the clock input to the timer Stopping the timer s operation allows the device to run ina low power mode when the timer is not needed The timer interrupt TINT rate is equal to the CPU clock frequency divided by two independent factors 1 1 TINTrate o xuxV to X TDDR 1 X PRD 1 In the equation te c is the period of C
404. n fetch using PAB PB First half cycle First data operand read using DAB DB First half cycle Second data operand read using CAB CB Second half cycle Data operand write using EAB EB Second half cycle Figure 7 3 Half Cycle Accesses to Dual Access Memory a Instruction word fetch Prefetch Fetch Decode Access Read Execute Read PB b Instruction performing single operand read Prefetch Fetch Decode Access Read Execute Read DB c Instruction performing dual operand read Prefetch Fetch Decode Access Read Execute Read Read CB DB d Instruction performing single operand write Prefetch Fetch Decode Access Read Execute Write EB 7 28 Pipeline SPRU131G Dual Access Memory and the Pipeline Figure 7 3 Half Cycle Accesses to Dual Access Memory Continued e Instruction performing dual operand write two cycles Prefetch Fetch Decode Access Read Execute Write EB Prefetch Fetch Decode Access Read Execute Write EB f Instruction performing operand read and operand write Prefetch Fetch Decode Access Read Execute Read Write DB EB Because two types of access are scheduled and only one access is performed in each half cycle conflicts can occur These conflicts are automatically resolved by the CPU either by rearranging the order of accesses or by delaying an access by one cycle The following sections describe these resolved memory access conflicts Keep in mind that these conflicts appear only if all accesses
405. n operation PAB See program address bus PAGEN See program address generation logic PAGEN PB See program data bus PC See program counter PCM See pulse coded modulation mode pipeline A method of executing instructions in an assembly line fashion pmad program memory address A 16 bit immediate program memory address PMST processor mode status register A 16 bit status register that controls the memory configuration of the device See also STO ST1 pop Action of removing a word from a stack PRD timer period register A 16 bit register that defines the period for the on chip timer program address bus PAB A 16 bit bus that provides the address for program memory reads and writes program address generation logic PAGEN Logic circuitry that gener ates the address for program memory reads and writes and the address for data memory in instructions that require two data operands This circuitry can generate one address per machine See also data address generation logic DAGEN Glossary D 13 Glossary program address register PAR A register that holds the address to be put on the PAB to address memory for reads via the PB program controller Logic circuitry that decodes instructions manages the pipeline stores status of operations and decodes conditional operations program counter PC A 16 bit register that indicates the location of the next instruction to be executed program counter ex
406. n the BSPCE constitute the ABU control register ABUC Some of these bits are read only while others are read write Figure 9 25 shows the ABUC bit positions and Table 9 12 summarizes the function of each ABUC bit in the BSPCE The value of the BSPCE upon reset is 3 Figure 9 25 BSP Control Extension Register BSPCE Diagram ABU Control Bits 14 13 12 11 10 9 0 15 HALTR BRE HALTX XH Serial Port control R W R R W R W R R W Note R Read W Write SPRU131G Serial Ports 9 43 Buffered Serial Port BSP Interface Table 9 12 BSP Control Extension Register BSPCE Bit Summary Bit 15 14 13 12 9 44 ABU Control Bits Reset Name value Function HALTR 0 Autobuffering Receive Halt This control bit determines whether autobuffering receive is halted when the current half of the buffer has been received HALTR 0 Autobuffering continues to operate when the current half of the buffer has been received HALTR 1 Autobuffering is halted when the current half of the buffer has been received When this occurs the BRE bit is cleared to 0 and the serial port continues to operate in standard mode RH 0 Receive Buffer Half Received This read only bit indicates which half of the receive buffer has been filled Reading RH when the RINT interrupt occurs seen either as a program interrupt or by polling IFR is a convenient way to identify which boundary has just been crossed RH 0 The first half of the buffer has been filled
407. n the following cases In all other instances the address changes on the CLKOUT falling edge The previous CLKOUT cycle was the active portion of a memory write A memory read is followed by a memory write A memory read is followed by an I O write A memory read is followed by an I O read g PS DS or IS changes if necessary when the address changes 10 14 External Bus Operation SPRU131G External Bus Interface Timing Figure 10 8 shows a read read write sequence with MSTRB active and no wait states The data is read as late in the cycle as possible to allow for maximum access time from a valid address Although the external writes take two cycles internally they require only one cycle if no accesses to the external interface are in progress This helps maintain processing throughput at the maximum level possible The timing diagram illustrates these concepts 41 Back to back reads from the same bank are single cycle accesses _ MSTRBB stays low during back to back reads 1 MSTRB goes high for one cycle during read to write transitions to frame the address and R W signal changes Figure 10 8 Memory Interface Operation for Read Read Write address XO XK R W f SPRU131G External Bus Operation 10 15 External Bus Interface Timing Figure 10 9 shows a write write read sequence with MSTRB active and no wait states The address and data written are held valid approximately one half
408. nal clock source The logic diagram for CLKR is shown in Figure 9 4 c on page 9 13 Note also that in DLB mode the FSX and DX signals appear on the device pins but FSR and DR do not Either internal or external FSX signals may be used in DLB mode as defined by the TXM bit Reserved Always read as a 0 in the serial port This bit performs a function in the TDM serial port discussed in section 9 4 Time Division Multiplexed TDM Serial Port Interface on page 9 56 Bit 0 is reserved and is read as 0 although it performs a function in the TDM serial port discussed in section 9 4 Time Division Multiplexed TDM Serial Port Interface on page 9 56 The DLB bit 1 selects digital loopback mode which allows testing of serial port code with a single C54x device When DLB 1 DR and FSR are connected to DX and FSX respectively through multiplexers as shown in Figure 9 4 When in loopback mode CLKR is driven by CLKX if on chip serial port clock generation is selected MCM 1 but if MCM 0 then CLKR is driven by the external CLKR signal This allows for the capability of external serial port clock generation in digital loopback mode If DLB 0 then normal operation occurs where DR FSR and CLKR are all taken from their respective pins SPRU131G Serial Port Interface Figure 9 4 Receiver Signal Multiplexers FO Bit FSM Bit SPRU131G a b DR FSR DR internal FSR internal DX FSX DLB a DLB CLKR interna
409. nconditional branch OVM definition D 13 PA addressing PAB D 13 definition PAL A 21 part order information PB definition PC definition PCM definition peripheral control 8 2 to 8 19 peripheral memory mapped registers C541 541B 8 3 C542 C543 8 5 E 3 6 C546 546A 8 7 peripherals 8 1 to 8 26 bank switching buffered serial port BSP 9 33 clock generator Baal clock modes control DMA controller 2 14 general purpose I O pins hardware timer 2 13 host port tne eg host port interface HPI 8 36 I O pins parallel I O ports programmable bank switching serial I O ports serial port interface 9 4 software programmable wait state generator 10 5 TDM serial port 9 56 timer B 21 wait state generator pins I O pipeline BC instruction BCD instruction call instruction call instructions CC instruction 7 21 CCD instruction conditional call branch instructions conditional execute instructions definition delayed call instruction delayed return instruction delayed return with interrupt enable instruction delayed return fast instruction 7 18 instructions interrupt response INTR instructions introduction latency in general V 34 precautions 7 35 store instructions V 39 types of levels operation return instruction return instructions 7 12 return with interrupt enable instruction 7 15 return fast instruction B Index six level structure
410. ndary JTAG scan paths are on add on boards if signal degradation is a problem you may need to buffer both the TRST and DTCK signals Although degradation is less likely for DTMSn signals you may also need to buffer them for the same reasons Design Considerations for Using XDS510 Emulator A 17 Emulation Design Considerations A 8 2 Emulation Timing Calculations for a Scan Path Linker SPL Example A 3 and Example A 4 help you to calculate the key emulation timings in the SPL secondary scan path of your system For actual target timing parameters see the appropriate device data sheet for your target device The examples use the following assumptions tsu TTMS td TTDO td bufmax td bufmin t bufskew t TCKfactor Setup time target TMS TDI to TCK high 10 ns Delay time target TDO from TCK low 15 ns Delay time target buffer maximum 10 ns Delay time target buffer minimum 1ns Skew time target buffer between two 1 35 ns devices in the same package ta bufmax td bufminy x 0 15 Duty cycle TCK assume a 40 60 clock 0 4 40 Also the examples use the following values from the SPL data sheet td DTMSmax tsu DTDLmin td DTCKHmin td DTCKLmax Delay time SPL DTMS DTDO from TCK low maximum Setup time DTDI to SPL TCK high minimum Delay time SPL DTCK from TCK high minimum Delay time SPL DTCK from TCK low maximum 31 ns 7 ns 2ns 16 ns There are two key timing paths to
411. ng of an instruction using indirect addressing Table 5 4 lists the types of single data memory operand addressing along with the value of MOD the assembler syntax and the function for each type Table 5 4 Indirect Addressing Types With a Single Data Memory Operand MOD Field 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 Operand Syntax ARX ARx ARX ARX ARx 0B ARx 0 ARx 0 ARx 0B ARx ARx 0 Function addr ARx addr ARx ARx ARx 1 addr ARx ARx ARx 1 addr ARx 1 ARx ARx 1 addr ARx ARx B ARx ARO addr ARx ARx ARx ARO addr ARx ARx ARx ARO addr ARx ARx B ARx ARO addr ARx ARx circ ARx 1 addr ARx ARx circ ARx ARO Descriptiont ARx contains the data memory address After access the address in ARx is decremented t After access the address in ARx is incremented Before its use the address in ARx is incremented this new address is used to address the data memory operand After access ARO is subtracted from ARx with reverse carry rc propagation After access ARO is subtracted from ARx After access ARO is added to ARx After access ARO is added to ARx with reverse carry rc propagation After access the address in ARx is decremented using circular addressing After access ARO is subtracted
412. ng the HPI to remain in SAM therefore no host accesses Can occur On Chip Peripherals 8 51 Host Port Interface The second consideration is that when changing from HOM to SAM the instruction immediately following the one that changes from HOM to SAM can not read the HPI RAM block This requirement is due to the fact that the mode has not yet changed when the HPI RAM read occurs and the RAM read is ignored because the mode switch has not yet occurred HPI RAM writes are not included in this restriction because these operations occur much later in the pipeline so itis possible to write to HPI RAM in the instruction following the one which changes from HOM to SAM On the host side there are no specific considerations associated with the mode changes For example it is possible to have a third device wake up the C54x CPU from IDLE2 3 and the C54x CPU changing to SAM upon wake up without a software handshake with the host The host can continue accessing while the HPI mode changes However if the host accesses the HPI RAM while the mode is being changed the actual mode change will be delayed until the host access is completed In this case a C54x CPU access to the HPI memory is also delayed Table 8 29 illustrates the sequence of events involved in entering and exiting an IDLE2 3 state on the C54x CPU when using the HPI Throughout the pro cess the HPI is accessible to the host Table 8 29 Sequence for Entering and Exiting IDLE2 and I
413. nly if the number of iterations is greater than 0 The following steps start a loop Step 1 You load BRC with a loop count in the 0 through 65 535 range Step 2 The instruction loads the address of the first instruction to be repeated This instruction is the one immediately following RPTB or the second instruction following RPTBD The repeat block RPTB or repeat block with delay RPTBD instruction automatically loads RSA with the address of the instruction following the RPTB instruc tion or with the address of the second instruction following the RPTBD instruction Program Memory Addressing 6 23 Repeating a Block of Instructions 6 24 Step 3 The instruction loads REA with the address following the last word of the last instruction to be repeated in the block which is also the long immediate operand given in the instruction This action also sets BRAF REA is loaded with the 16 bit immediate operand of the RPTB or RPTBD instruction and the BRAF bit is set The value for the 16 bit immediate operand of RPTB or RPTBD is L 1 where L is the address of the instruction following the last word of the last instruction in the loop Every time the PC is updated during loop execution REA is compared to the PC value If the values are equal BRC is decremented If BRC is greater than or equal to 0 RSA is loaded into the PC to restart the loop If not BRAF is reset to 0 and the processor resumes execution past the end of the loop B
414. nly mode the HPI supports even higher speed back to back host accesses on the order of one byte every 50 ns that is 160M bps independent of the C54x DSP clock rate refer to the TMS320C54x data sheet for specific detailed timing informa tion 8 6 1 Basic Host Port Interface Functional Description SPRU131G The external HPI interface consists of the 8 bit HPI data bus and control sig nals that configure and control the interface The interface can connect to a variety of host devices with little or no additional logic necessary Figure 8 7 shows a simplified diagram of a connection between the HPI and a host device On Chip Peripherals 8 37 Host Port Interface Figure 8 7 Generic System Block Diagram Host device TMS320C54x DSP Data HDO HD7 HCNTLO 1 address Address HBIL 1st 2nd byte Sampled by internal strobe or HAS Read Write Data strobe Internal strobe controls transfer Address Latch Enable Samples Address and Read Write if used signals if used Ready Interrupt HINT The 8 bit data bus HDO HD7 exchanges information with the host Because of the 16 bit word structure of the C54x DSP all transfers with a host must consist of two consecutive bytes The dedicated HBIL pin indicates whether the first or second byte is being transferred An internal control register bit determines whether the first or second byte is placed into the most significant byte of a 16 bit word The host mus
415. nostic Applications For systems that require built in diagnostics it is possible to connect the emulation scan path directly to a TI ACT8990 test bus controller TBC instead of the emulation header The TBC is described in the Texas Instruments Advanced Logic and Bus Interface Logic Data Book Figure A 15 shows the scan path connections of n devices to the TBC A 24 Design Considerations for Using XDS510 Emulator SPRU131G Emulation Design Considerations Figure A 15 TBC Emulation Connections for n JTAG Scan Paths SPRU131G TBC TCKI TDO Tp JTAG O TMSO s TMS TMS1 EMUO TMS2 EVNTO EMU1 TMS3 EVNT1 TRST TMS4 EVNT2 TCK TMS5 EVNT3 TDO TCKO TDIO TDI To JTAGN TMS EMUO e EMU1 TRST TCK TDO In the system design shown in Figure A 15 the TBC emulation signals TCKI TDO TMSO TMS2 EVNTO TMS3 EVNT1 TMS5 EVNT3 TCKO and TDIO are used and TMS1 TMS4 EVNT2 and TDI1 are not connected The target devices EMUO and EMU1 signals are connected to Vcc through pullup resis tors and tied to the TBC s TMS2 EVNT0 and TMS3 EVNT1 pins respectively The TBC s TCKI pin is connected to a clock generator The TCK signal for the main JTAG scan path is driven by the TBC s TCKO pin On the TBC the TMSO pin drives the TMS pins on each device on the main JTAG scan path TDO on the TBC connects to TDI on the fi
416. ns respectively The difference is that no return address is written to the stack in this case As shown in Example 7 16 a BC instruction takes either three or five cycles to execute depending on whether or not the branch is taken A BCD instruction executes in three cycles SPRU131G Pipeline Operation Example 7 16 Conditional Branch BC Instruction in the Pipeline BC b1 Pipeline f i4 or pipe i5 or pipe i6 or j1 Address Instruction al i1 a2 a3 BC b1 cond a4 i4 a5 i5 a6 i6 b1 ji 1 2 3 4 5 6 7 8 9 10 11 Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute eepe T Prefetch Fetch Decode Access Read Execute eepe TT Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute ine flush PAB a5 IR i and conditional execution of i5 Prefetch Fetch Decode Access Read PAB PB IR R ia een a O e 12 Execute SPRU131G Pipeline 7 23 Pipeline Operation Example 7 17 Delayed Conditional Branch BCD Instruction in the Pipeline Address Instruction al i1 a2 a3 BCD b1 cond a4 i4 a5 i5 a6 i6 b1 ji 1 2 3 4 5 6 7 8 9 10 11 12 Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute No
417. nsiderations A 8 Emulation Design Considerations This section describes the use and application of the scan path linker SPL which can simultaneously add all four secondary JTAG scan paths to the main scan path It also describes the use of the emulation pins and the configuration of multiple processors A 8 1 Using Scan Path Linkers A 16 You can use the TI ACT8997 scan path linker SPL to divide the JTAG emulation scan path into smaller logically connected groups of 4 to 16 devices As described in the Advanced Logic and Bus Interface Logic Data Book the SPL is compatible with the JTAG emulation scanning The SPL is capable of adding any combination of its four secondary scan paths into the main scan path A system of multiple secondary JTAG scan paths has better fault tolerance and isolation than a single scan path Since an SPL has the capability of adding all secondary scan paths to the main scan path simultaneously it can support global emulation operations such as starting or stopping a selected group of processors Tl emulators do not support the nesting of SPLs for example an SPL connected to the secondary scan path of another SPL However you can have multiple SPLs on the main scan path Scan path selectors are not supported by this emulation system The TI ACT8999 scan path selector is similar to the SPL but it can add only one of its secondary scan paths at a time to the main JTAG scan path Thus global emulati
418. nter is not used the output from the PLL is immediately fed to the internal logic and the CLKOUT pin is asserted The lock up time is 50 us for the PLL and CLKOUT to be stable Therefore it is necessary to keep the reset line low during this 50 us lock up time so that the C54x CPU does not start processing using an unstable clock IDLE3 Wake Up Sequence Normal X IDLE3 power down PLL lock and wake up Normal PLL operation CLKOUT UL LULI External Bus Operation 10 27 Hold Mode 10 6 Hold Mode Two signals HOLD and HOLDA allow an external device to take control of the processor s buses The processor acknowledges receiving a HOLD signal from an external device by bringing HOLDA low The C54x DSP enters the hold mode and places its external address buses data buses and control signals into high impedance The hold mode HM status bit located in ST1 determines the following oper ating modes for the hold function 1 Normal mode suspends program execution during a low HOLD signal Concurrent mode allows program execution to continue operating from internal memory ROM or RAM When HM 1 the C54x DSP operates in the normal mode When HM 0 the C54x DSP operates in the concurrent mode In this mode the C54x DSP enters the hold state only if program execution is from external memory or if an external memory operand is being accessed However if program execution is from internal memory and no external me
419. ntral Processing Unit 4 19 Multiplier Adder Unit Figure 4 8 Multiplier Adder Functional Diagram CB15 CBO 40 From accumulator A DB15 DBO 40 S From accumulator B PB15 PBO Legend Accumulator A Accumulator B CB data bus PB program bus B Cc D DB data bus P T T register Multiplier 17 x 17 Adder 40 OVA OVB ZA ZB 7 To accumulator A B 4 5 1 Multiplier Input Sources This section lists sources for multiplier inputs and discusses how multiplier inputs can be selected for various instructions The XM input source to the multiplier is any of the following values 4 The temporary register T 1 A data memory operand from data bus DB Lj Accumulator A bits 32 16 4 20 Central Processing Unit SPRU131G Multiplier Adder Unit The YM input source to the multiplier is any of the following values _ Adata memory operand from data bus DB _ Adata memory operand from data bus CB Lj Aprogram memory operand from program bus PB _j Accumulator A bits 32 16 Table 4 5 shows how the multiplier inputs are obtained for several instructions There are a total of nine combinations of multiplier inputs that are actually used For instructions using T as one input the second input may be obtained as an immediate value or from data memory via a data bus DB or from accumula tor A For instructions using single data memory operand address
420. ntrol register TSPC that allows the CLKX pin to be used as an input IN1 reflects the current level of the CLKX pin of the device SPRU131G SPRU131G Glossary internal transmit clock division factor CLKDV A 5 bit field in the BSP control extension register BSPCE that determines the internal transmit clock duty cycle interrupt A condition caused by internal hardware an event external to the CPU or by a previously executed instruction that forces the current program to be suspended and causes the processor to execute an inter rupt service routine corresponding to the interrupt interrupt flag register IFR A 16 bit memory mapped register that flags pending interrupts interrupt mask register IMR A 16 bit memory mapped register that masks external and internal interrupts interrupt mode INTM A bitin status register 1 ST1 that globally masks or enables all interrupts interrupt service routine ISR A module of code that is executed in response to a hardware or software interrupt IPTR interrupt vector pointer A 9 bit field in the processor mode status register PMST that points to the 128 word page where interrupt vectors reside IR instruction register A 16 bit register used to hold a fetched instruction latency The delay between when a condition occurs and when the device reacts to the condition Also in a pipeline the necessary delay between the execution of two instructions to ensure that the va
421. ny latency LD 27h A b LD 100h DP This DP load does not require any latency LD 27h A Example 7 45 DP Load With a 2 Cycle Latency in Noncompiler Mode CPL 0 TLM A STO The DP field of STO is updated here NZAwW 10 O B 3 27h The new DP value is used here Example 7 46 DP Load With a 3 Cycle Latency in Noncompiler Mode CPL 0 POPM STO The DP field of STO is updated here NOP NOP NOP LD 27h A The new DP value is used here 7 5 7 4 Updating CPL A pipeline conflict can occur if two conditions are simultaneously met J An instruction modifies CPL _j The next instruction uses direct addressing mode The conflict occurs because the second instruction reads CPL in a pipeline stage that occurs before the previous instruction updates it Table 7 19 lists the latencies between instructions that update CPL and subsequently use it CC CC Note You are responsible for rearranging instructions or inserting NOPs if necessary to accommodate latencies P SPRU131G Pipeline 7 65 Pipeline Latencies Table 7 19 Latencies for the CPL Bit a Latencies based on secona instruction category First Instruction STM ST MVDK MVMD MVKD MVDM MVPD POPM POPD MVDD lk status lk status Smem status MMR status dmad status dmad status pmad status status status status Store type instruction see Table 7 5 SSBX RS
422. odes the clock generator must first be set to PLL mode with an integer only nonfractional multiplier ratio and then set back to DIV mode in the desired divider configuration see section Switching From DIV Mode to PLL Mode on page 8 32 Example 8 2 shows a code sequence that can be used to switch the clock mode from PLL x X mode to PLL x 1 mode Example 8 2 Switching Clock Mode From PLL x X Mode to PLL x 1 Mode STM 0b CLKMD switch to DIV mode TstStatu LDM CLKMD A AND 01b A poll STATUS bit BC TstStatu ANEQ STM 0000001111101111b CLKMD switch to PLL X 1 mode PLL Operation Immediately Following Reset Immediately following reset the clock mode is determined by the values of the three external pins CLKMD1 CLKMD2 and CLKMD3 Switching from the initial clock mode to any other mode can easily be accomplished by changing the contents of CLKMD If use of the internal oscillator with an external crystal is desired the device CLKMD pins must be configured at reset to enable the internal oscillator See Table 8 16 and Table 8 17 on page 8 28 for external pin values and available modes on each device The internal oscillator option is not available on the C5420 The following code can be used to switch from divide by 2 mode to PLL x 3 mode STM 0010 0001 0100 1111b CLKMD PLL Considerations When Using IDLE Instruction When using one of the IDLE instructions to reduce power requirements proper mana
423. of a printed circuit board is a consideration in many DSP applications To make full use of the board space Texas Instruments offers this ROM code option that reduces the chip count and provides a single chip solution This option allows you to use a code customized processor for a specific applica tion while taking advantage of D Greater memory expansion Lower system cost _j Less hardware and wiring Lj Smaller PCB If a routine or algorithm is used often it can be programmed into the on chip ROM of a TMS320 DSP TMS320 DSP programs can also be expanded by using external memory this reduces chip count and allows for a more flexible program memory Multiple functions are easily implemented by a single device thus enhancing system capabilities TMS320 DSP developmenttools are used to develop test refine and finalize the algorithms The microprocessor microcomputer MP MC mode is avail able on all ROM coded TMS320 DSP devices when accesses to either on chip or off chip memory are required The microprocessor mode is used to develop test and refine a system application In this mode of operation the TMS320 DSP acts as a standard microprocessor by using external program memory When the algorithm has been finalized the code can be submitted to Texas Instruments for masking into the on chip program ROM At that time the TMS320 DSP becomes a microcomputer that executes customized programs from the on chip ROM Should the code n
424. of program memory control via OVLY IPTR and MP MC fields the prefetch stage of the pipeline evaluates these bits In the case of data memory control via the DROM field the access or read stage evaluates this bit If an external memory access occurs additional cycles are required for opera tions affected by the changing bit Any change in PMST fields is delayed until an in process external access is completed For example if an external memory access is occurring while an instruction in the execute stage of the pipeline tries to modify OVLY the update is delayed until the external bus cycle is completed This in turn requires additional cycles to those listed in the following tables Table 7 26 lists the latencies between instructions that write to the OVLY IPTR or MP MC bit fields and those instructions that are subsequently fetched from the new memory space NE Note You are responsible for rearranging instructions or inserting NOPs if necessary to accommodate latencies eee ee ee ee ee ee ee ee Pipeline 7 75 Pipeline Latencies Table 7 26 Latencies for OVLY IPTR and MP MC Bits a Latencies based on second instruction category Second Instruction First Instruction Category Categoryll Category Ill Category IV STM lk pmst 0 0 1 2 ST lk pmst MVDK dmad pmst MVMD MMR pmst All other instruc 0 1 2 3 tions that modify OVLY IPTR MP MC b Categories for the second instruction Category Catego
425. oftware interrupt 27 Software interrupt 28 Software interrupt 29 reserved Software interrupt 30 reserved External user interrupt 0 External user interrupt 1 External user interrupt 2 Internal timer interrupt Buffered serial port receive interrupt Buffered serial port transmit interrupt Serial port receive interrupt Serial port transmit interrupt External user interrupt 3 HPI interrupt Reserved Program Memory Addressing 6 41 Interrupts Table 6 23 TMS320C546 Interrupt Locations and Priorities 6 42 TRAP INTR Number K Priority 0 1 o oa N O aA A O ND es oOo 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 o N 0 gt ol A wo l oO 25 31 Name RS SINTR NMI SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INTO SINTO INT1 SINT1 INT2 SINT2 TINT SINT3 BRINTO SINT4 BXINTO SINT5 RINT1 SINT6 XINT1 SINT7 INT3 SINT8 Program Memory Addressing Location Hex 0 4 8 C 10 14 18 iC 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 7F Function Reset hardware and software reset Nonmaskable interrupt Software interrupt 17 Software interrupt 18 Software interrupt 19 Software interrupt 20 Software interrupt 21 Software interrupt 22 Software interrupt 23 Software interrupt 24 Software interrupt 25 Software interrupt 26 Software interrupt
426. ogic and how the double buffering is implemented Transmit data is written to the DXR while received data is read from the DRR A transmit is initiated by writing data to the DXR which copies the data to the XSR when the XSR is empty when the last word has been transmitted serially that is driven on the DX pin The XSR manages shifting the data to the DX pin thus allowing another write to DXR as soon as the DXR to XSR copy is completed During transmits upon completion of the DXR to XSR copy a 0 to 1 transition occurs on the transmit ready XRDY bit in the SPC This 0 to 1 transition generates a serial port transmit interrupt XINT that signals that the DXR is ready to be reloaded See section 6 10 nterrupts on page 6 26 for more information on C54x DSP interrupts The process is similar in the receiver Data from the DR pin is shifted into the RSR which is then copied into the DRR from which it may be read Upon completion of the RSR to DRR copy a 0 to 1 transition occurs on the receive ready RRDY bit in the SPC This O to 1 transition generates a serial port receive interrupt RINT Thus the serial port is double buffered because data Serial Ports 9 7 Serial Port Interface can be transferred to or from DXR or DRR while another transmit or receive is being performed Note that transfer timing is synchronized by the frame sync pulse in burst mode discussed in more detail in section 9 2 4 Burst Mode Transmit and Receive O
427. ogram space invoking 6 50 table other power down capabilities 6 52 program memory address pmad definition power down modes operation during program address generation logic PAGEN 2 11 PRD definition D 13 ba prioritization external bus 10 4 definition Ba processor mode status register PMST 3 27 programmable bank switching program memory address generation AVIS bit protocol bus bit summary 4 6 PSC CLKOFF bit D 5 definition definition PS DS diagram pulse coded modulation mode PCM DROM bit 4 7 definition push definition D 14 IPTR field 4 6 D 11 MP MC bit _ 4 6 D 121 OVLY bit 4 6 D 14 SMUL bit_ 4 7 D 15 SST bit 4 8 D 15 program address bus PAB definition D 13 RAM program address register PAR definition RAM overlay OVLY 4 6 program addressing 2 11 gL introduction i program bus 2 3 commen program control RCCD instruction no latency block repeat operations 6 23 REA conditional operations 6 16 receive buffer half received RH definition D 14 receive interrupt request hardware interrupt request interrupt flag register IFR 6 27 software interrupt request receive ready RRDY definition control registers hardware stack 5 27 interrupts 6 26 to 6 49 power down mode program counter PC repeat single operations receive shift register full RSRFULL reset definition status registers receiver reset RRST definition D 14 program controller def
428. om TI and third party vendors B 1 Development Support 0 0 eee teen eens Bat Development TONS 4 1 0021 veccesersreersteeesrueesevederbadeevebes B 1 2 Third Party Support 0 00 cece tenet eee B 1 3 Technical Training Organization TTO TMS320 DSP Workshops Bid ASSISIANCE asic ccc ctnnidarcatnaten emanated nad iawed naa nee ab eaees eee Oe B 2 Part Order Information iii aiiai eee eens B 2 1 Device and Development Support Tool Nomenclature Prefixes B 2 2 Device Nomenclature 0 0 c cece tte eens B 2 3 Development Support Tools 000 cee teens Submitting ROM Codes to Tl 20 eee eee eee eee C 1 Provides information for submitting ROM codes to Texas Instruments GIOSSANY ia ieee ena anae ee eee ia oe eee ba oe een aaeeee Defines terms and abbreviations used throughout this book SPRU131G Contents xxi Figures Pe eee ee ee ee ee OAN OOP WN HH Oo 3 11 4 10 4 11 xxii Evolution of the TMS320 DSP Family 000 cece eee eens Block Diagram of TMS320C54x DSP Internal Hardware 00 cece eee Memory Maps for the C541 0 keene Memory Maps for the C542 and C543 wo teens Memory Maps for the C545 and C546 eens Memory Maps for the C548 0 0 cece eens Memory Maps for the C549 0 keene eee Extended Program Memory Maps for the C548 and C549 0 eee eee Memory Maps for the C5402 1
429. omatic buffering feature which greatly reduces CPU overhead required in handling serial data transfers The C5402 C5410 and C5420 devices include multichannel buffered serial ports McBSPs See Table 9 1 for information about the features included in various C54x devices The BSP operates in either autobuffering or nonbuffered mode When oper ated in nonbuffered or standard mode the BSP functions the same as the basic standard serial port except where specifically indicated and is described in this section The TDM serial port operates in either TDM or non TDM mode When operated in non TDM or standard mode the TDM serial port also functions the same as the basic standard serial port and is described in this section The BSP also implements several enhanced features in standard mode These features together with operation of the BSP in autobuffering mode are described in section 9 3 Buffered Serial Port BSP Interface on page 9 33 Therefore when using the C542 C543 C545 C546 C548 and C549 devices you should consult section 9 3 Operation of the TDM serial port in TDM mode is described in section 9 4 Time Division Multiplexed TDM Serial Port Interface on page 9 56 Note that the BSP and TDM serial ports initialize to a standard serial port compatible mode upon reset In all C54x DSP serial ports both receive and transmit operations are double buffered thus allowing a continuous communications stream with either 8
430. on chip C54x DSP memory that is accessible by both the host and the C54x DSP Enhanced host port interfaces are available on the C5402 C5410 HPI 8 and C5420 HPI 16 devices This chapter does not describe these enhanced HPIs For more information on the HPI 8 and HPI 16 see TMS320C54x DSP Enhanced Peripherals Reference Guide SPRU302 The HPI interfaces to the host device as a peripheral with the host device as master of the interface facilitating ease of access by the host The host device communicates with the HPI through dedicated address and data registers to which the C54x DSP does not have direct access and the HPI control register using the external data and interface control signals see Figure 8 6 Both the host device and the C54x DSP have access to the HPI control register Figure 8 6 Host Port Interface Block Diagram control Data latch register HD 7 0 Address register Dat TE HPI memory block Interface HPI control control signals logic Host port interface 8 36 On Chip Peripherals DSP data DSP address SPRU131G Host Port Interface The HPI provides 16 bit data to the C54x DSP while maintaining the economical 8 bit external interface by automatically combining successive bytes transferred into 16 bit words When the host device performs a data transfer with the HPI registers the HPI control logic automatically performs an access to a dedicated 2K word block of internal
431. on operations are not assured with the scan path selector You can insert an SPL on a backplane so that you can add up to four device boards to the system without the jumper wiring required with nonbackplane devices You connect an SPL to the main JTAG scan path in the same way you connect any other device Figure A 10 shows how to connect a secondary scan path to an SPL Design Considerations for Using XDS510 Emulator SPRU131G Emulation Design Considerations Figure A 10 Connecting a Secondary JTAG Scan Path to a Scan Path Linker SPRU131G SPL DTCK Tp JAGO TDI DTDOO TMS TMS DTMS0 TCK TCK DTDIO TRST TRET papa TDO TDO DTMS1 DTDI1 DTDO2 DTMS2 DTDI2 DTDO3 DTMS3 DTDI3 The TRST signal from the main scan path drives all devices even those on the secondary scan paths of the SPL The TCK signal on each target device on the secondary scan path of an SPL is driven by the SPL s DTCK signal The TMS signal on each device on the secondary scan path is driven by the respec tive DTMS signals on the SPL DTDOO onthe SPL is connected to the TDI signal of the first device on the sec ondary scan path DTDIO on the SPL is connected to the TDO signal of the last device in the secondary scan path Within each secondary scan path the TDI signal of a device is connected to the TDO signal of the device before it If the SPLis on a backplane its seco
432. on that sets the BRAF flag in ST1 an incomplete repeat block loop results This occurs because RPTB D sets BRAF in the access stage of the pipeline and the previous instruction overwrites ST1 one cycle later To avoid this conflict it is recommended that only instructions listed in Table 7 14 be used to write to ST1 immediately prior to a RPTB D instruction Any other instruction that writes to ST1 must not be immediately followed by a RPTB D instruction Table 7 14 Recommended Instructions for Writing to ST1 To do this Use this instruction Store a value to ST1 STM k ST1 Si k ST1 Copy a value from data memory to ST1 MVDK k ST1 MVMD_ k ST1 Clear a bit in ST1 RSBX Set a bit in ST1 SSBX Load ASM with a value LD k ASM 7 60 Pipeline LD Smem ASM SPRU131G Pipeline Latencies 7 5 7 2 Updating ARP in Compatibility Mode CMPT 1 and CMPT bit A pipeline conflict can occur if two conditions are simultaneously met J An instruction updates ARP or CMPT J The next instruction uses ARP or CMPT to update the address pointer in indirect addressing mode The conflict occurs because the second instruction uses ARP or CMPT ina pipeline stage that occurs before the previous instruction updates ARP or CMPT Table 7 15 lists one instruction that does not have any latency in updating ARP when the CPU is in compatibility mode Use this instruction wherever possible to avoid any conflicts Table 7 15 Pipeline Protecte
433. ond word of the call instruction which contains the starting address of the function to be called Before branching to the called function the processor stores the address of the instruction following the call instruction to the stack The function must end with a return instruction which takes the address off the stack and loads PC allowing the processor to resume execution of the calling program By the time the conditions of the conditional call instruction have been tested the two instruction words following the call instruction have already been fetched in the pipeline How these two instruction words are handled depends in part on whether the call is nondelayed or delayed I Nondelayed If all the conditions are met these two instruction words are flushed from the pipeline so that they are not executed and then execution continues at the beginning of the called function If the conditions are not met the two instructions are executed instead of the call 1 Delayed The one 2 word instruction or two 1 word instructions following the call instruction are always executed This allows you to avoid flushing the pipeline which requires extra cycles The conditions tested are not affected by the instructions following the delayed call If the conditions are not met the processor executes the two instruction words instead of the call Note The two words following a delayed instruction cannot be an instruction that causes a PC dis
434. opcode of the instruction is encoded in the high half of the instruction bits 8 15 of a 1 word encoding The value of the constant is in the remaining instruction space Data Addressing SPRU131G Immediate Addressing Figure 5 2 uses the RPT instruction to show how along immediate Ik value is encoded in instructions that use immediate addressing The opcode of the instruction is encoded in the high half of the instruction bits 0 15 of the high word of a 2 word encoding The value of the constant is in the remaining instruction space Figure 5 1 RPT Instruction With Short lmmediate Addressing 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 instruction word 1 1 1 0 1 4 0 0 8 bit constant Figure 5 2 RPT Instruction With 16 Bit lmmediate Addressing 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 bit constant 2 instruction words SPRU131G Data Addressing 5 3 Absolute Addressing 5 2 Absolute Addressing There are four types of absolute addressing d m Data memory address dmad addressing m MVDK Smem dmad E MVDM dmad MMR E MVKD dmad Smem m MVMD MMR dmad Program memory address pomad addressing FIRS Xmem Ymem pmad MACD Smem pmad src MACP Smem pmad src MVDP Smem pmad MVPD pmad Smem Port address PA addressing m PORTR PA Smem E PORTW Smem PA k addressing is used with all instructions that support the use of a single data memory Smem operand Absolute addresses are always encoded
435. or TMS320C54x DSP Reference Set Volume 2 Mnemonic Instruction Set literature number SPRU172 describes the TMS320C54x digital signal processor mnemonic instructions individually Also includes a summary of instruction set classes and cycles TMS320C54x DSP Reference Set Volume 3 Algebraic Instruction Set literature number SPRU179 describes the TMS320C54x digital signal processor algebraic instructions individually Also includes a summary of instruction set classes and cycles TMS320C54x DSP Reference Set Volume 4 Applications Guide literature number SPRU173 describes software and hardware applications for the TMS320C54x digital signal processor Also includes development support information parts lists and design considerations for using the XDS510 emulator TMS320C54x DSP Reference Set Volume 5 Enhanced Peripherals literature number SPRU302 describes the enhanced peripherals avail able on the TMS320C54x digital signal processors Includes the multi channel buffered serial ports McBSPs direct memory access DMA controller interprocessor communications and the HPI 8 and HPI 16 host port interfaces TMS320C54x DSP Family Functional Overview literature number SPRU307 provides a functional overview of the devices included in the TMS320C54x DSP generation of digital signal processors Included are descriptions of the CPU architecture bus structure memory struc ture on chip peripherals and instruc
436. or BXINTO BRINTO TINT RSVD DMAC1 DMACO 6 30 Program Memory Addressing SPRU131G Interrupts 6 10 3 Phase 1 Receive Interrupt Request Interrupt An interrupt is requested by a hardware device or by a software instruction When an interrupt request occurs the corresponding flag if any is activated in the IFR see section 6 10 1 nterrupt Flag Register IFR on page 6 27 This flag is activated whether or not the interrupt is later acknowledged by the processor The flag is automatically cleared when its corresponding interrupt is taken SPRU131G J Hardware interrupt requests External hardware interrupts are requested by signals at external interrupt ports and internal hardware interrupts are requested by signals from the on chip peripherals For example on the C541 hardware interrupts can be requested by or through Pins INT3 through INTO Pins RS reset and NMI The serial ports interrupts RINTO and XINTO or RINT1 and XINT1 The timer interrupt TINT Table 6 19 through Table 6 24 pages 6 38 through 6 43 list the interrupt sources for some C54x devices J Software interrupt requests A software interrupt is requested by one of the following program instructions INTR This instruction allows you to execute any interrupt service rou tine The instruction operand K indicates which interrupt vector loca tion the CPU branches to Table 6 19 through Table 6 24 pages 6 38 through 6 43 show the operand K
437. ory access to I O access sequence IOSTRB is low from one rising edge to the next rising edge of the CLKOUT cycle Figure 10 11 shows a read write read sequence for IOSTRB with no wait states For IOSTRB accesses reads and writes require a minimum of two cycles Some off chip peripherals can change their status bits during reads or writes therefore it is important that addresses remain valid when communi cating with those peripherals For reads and writes with IOSTRB active IOSTRB is completely framed by the address to meet this requirement The timing diagram illustrates these concepts 1 Each I O access takes two cycles Q IOSTRB goes high at the end of each access to frame address and R W signal changes Parallel I O Interface Operation for Read Write Read adress KKK X 10 18 Data I O read I O read R W A Is f aa NN External Bus Operation SPRU131G External Bus Interface Timing Figure 10 12 shows the same I O space access with one wait state access Each read and write access is extended by an additional cycle Figure 10 12 Parallel I O Operation for Read Write Read l O Space Wait States I O read 1 0 write VO read R W A IS f IOSTRB A f A Wait state lt Wait state _ _ Wait state _ 10 4 3 Memory and I O Access Timing Figure 10
438. ositioning Vibration analysis Voice commands Anticollision radar General Purpose Adaptive filtering Convolution Correlation Digital filtering Fast Fourier transforms Hilbert transforms Waveform generation Windowing Instrumentation Digital filtering Function generation Pattern matching Phase locked loops Seismic processing Spectrum analysis Transient analysis Consumer Digital radios TVs Educational toys Music synthesizers Pagers Power tools Radar detectors Solid state answering machines Graphics Imaging 3 D rotation Animation digital maps Homomorphic processing Image compression transmission Image enhancement Pattern recognition Robot vision Workstations Medical Diagnostic equipment Fetal monitoring Hearing aids Patient monitoring Prosthetics Ultrasound equipment Telecommunications 1200 to 33 600 bps modems Adaptive equalizers ADPCM transcoders Cellular telephones Channel multiplexing Data encryption Digital PBXs Digital speech interpolation DSI DTMF encoding decoding Echo cancellation 1 4 Introduction Faxing Line repeaters Personal communications systems PCS Personal digital assistants PDA Speaker phones Spread spectrum communications Video conferencing X 25 packet switching Control Disk drive control Engine control Laser printer control Motor control Robotics control Servo control Industrial Numeric control Power line monitoring
439. ous Buffered Buffered Multiplexed Device Serial Ports Serial Ports Serial Ports Serial Ports C541 2 0 0 0 C542 0 1 0 1 C543 0 1 0 1 C545 1 1 0 0 C546 1 1 0 0 C548 0 2 0 1 C549 0 2 0 1 C5402 0 0 2 0 C5410 0 0 8 0 C5420 0 0 6 0 Table 9 2 lists the sections that should be consulted for the various serial ports and their modes 9 2 Serial Ports SPRU131G Introduction to the Serial Ports Table 9 2 Sections that Discuss the Serial Ports Serial Port Standard Buffered MCBSP TDM SPRU131G Mode Autobuffering Nonbuffered standard Multichannel TDM Non TDM standard See section 9 2 Standard Serial Port Interface on page 9 4 section 9 3 Buffered Serial Port BSP Interface on page 9 33 section 9 2 Standard Serial Port Interface on page 9 4 TMS320C54x DSP Enhanced Peripherals Reference Guide SPRU302 section 9 4 Time Division Multiplexed TDM Serial Port Interface on page 9 56 section 9 2 Standard Serial Port Interface on page 9 4 Serial Ports 9 3 Serial Port Interface 9 2 Serial Port Interface 9 4 Serial Ports Four different types of serial port interfaces are available on C54x devices The basic standard serial port interface is implemented on C541 C545 and C546 devices The TDM serial port interface is implemented on the C542 C543 C548 and C549 devices The C542 C543 C545 C546 C548 and C549 devices include a buffered serial port BSP that implements an aut
440. owever the C54x device does respond to the HOLD signal while executing an RPT RPTZ loop the response depends on the value of the HM bit of ST1 The repeat function can be used with some instructions such as multiply accumulate and block moves to increase the execution speed of these instructions These multicycle instructions see Table 6 17 effectively become single cycle instructions after the first iteration of a repeat instruction Single data memory operand instructions cannot be repeated if a long offset modifier or an absolute address is used for example ARn Ik ARn Ik ARn lk and Ik Instructions listed in Table 6 18 cannot be repeated using RPT Table 6 17 Multicycle Instructions That Become Single Cycle Instructions When Repeated Instruction Description Cyclest FIRS Symmetrical FIR filter 3 MACD Multiply and move result in accumulator with delay 3 MACP Multiply and move result in accumulator 3 MVDK Data to data move 2 MVDM Data to MMR move 2 MVDP Data to program move 4 MVKD Data to data move 2 MVMD MMR to data move 2 MVPD Program to data move 3 READA Program to data move 5 WRITA Data to program move 5 t Number of cycles when instruction is not repeated 6 20 Program Memory Addressing SPRU131G Table 6 18 Nonrepeatable Instructions SPRU131G Instruction ADDM ANDM B D BACC D BANZ D BC D CALAD CALL D CCID CMPR DST FB D FBAGCC D FCALA D FCALL D FRET D FRETE D IDLE
441. perations on page 9 18 Figure 9 2 Serial Port Interface Block Diagram k 16 16 y y DRR 16 DXR 16 A 16 16 RINT on T XINT on RSR DRR 4 gt gt DXR XSR transfer transfer ah a Clear Clear F Byte word Byte wor Yy FSR FSX Y y DR CLKR CLKX DX 9 2 3 Configuring the Serial Port Interface The SPC contains control bits which configure the operation of the serial port The SPC bit fields are shown in Figure 9 3 and described in Table 9 5 Note that seven bits in the SPC are read only and the remaining nine bits are read write Figure 9 3 Serial Port Control Register SPC Diagram 15 14 13 12 11 8 7 6 10 9 5 4 XRDY RRDY INO RRST XRST F R W R W R R R R R Note R Read W Write R R W RW RW RW RW RW RW 9 8 Serial Ports SPRU131G Serial Port Interface Table 9 5 Serial Port Control Register SPC Bit Summary Bit Name 15 Free 14 Soft 13 RSRFULL 12 XSREMPTY SPRU131G Reset Value Function 0 This bit is used in conjunction with the Soft bit to determine the state of the serial port clock when a breakpoint is encountered in the HLL debugger See Table 9 6 on page 9 17 for the serial port clock configurations Free 0 The Soft bit selects the emulation mode Free 1 The serial port clock runs free regardless of the Soft bit This bit is used in conjunction with the Free bit to determine the state of the serial port cloc
442. performance and low power consumption Low power consumption and increased radiation hardness because of new static design techniques Introduction 1 5 TMS320C54x DSP Key Features 1 3 TMS320C54x DSP Key Features This section lists the key features of the C54x DSPs I CPU 1 6 Introduction Advanced multibus architecture with one program bus three data buses and four address buses M 40 bit arithmetic logic unit ALU including a 40 bit barrel shifter and two independent 40 bit accumulators 17 bit x 17 bit parallel multiplier coupled to a 40 bit dedicated adder for nonpipelined single cycle multiply accumulate MAC operation Hm Compare select store unit CSSU for the add compare selection of the Viterbi operator Mm Exponent encoder to compute the exponent of a 40 bit accumulator value in a single cycle m Two address generators including eight auxiliary registers and two auxiliary register arithmetic units Multiple CPU core architecture on some devices I Memory Mm 192K words x 16 bit addressable memory space 64K words program 64K words data and 64K words I O with extended program memory in the C548 C549 C5402 C5410 and C5420 On chip configurations as follows in K words Program Program Data Device ROM ROM DARAMt SARAM C541 20 8 5 0 C542 2 0 10 0 C543 2 0 10 0 C545 32 16 6 0 C546 32 16 6 0 C548 2 0 8 24 C549 16 16 8 24 C5402 4 4 16 0 C5410 16 0 8 56 C5420 0 0 32 168 T Dual access R
443. plied by an external source if MCM 0 for all devices TFRM can also be supplied externally if TXM 0 An external TFRM however must meet TDM receive timing specifications with respect to TCLK for proper operation No more than one device should have MCM or TXM setto 1 at any giventime The specification of which device is to supply clock and framing signals is typically made only once during system initialization The TDM channel select register TCSR of a given device specifies in which time slot s that device is to transmit A 1 in any one or more of bits 0 7 of the TCSR sets the transmitter active during the corresponding time slot Again a key system level constraint is that no more than one device can transmit during the same time slot devices do not check for bus contention and slots SPRU131G SPRU131G Time Division Multiplexed TDM Serial Port Interface must be consistently assigned As in TSPC operation a write to TCSR during a particular frame is valid only during the next frame However a given device can transmit in more than one slot This is discussed in more detail in section 9 4 4 TDM Mode Transmit and Receive Operations on page 9 62 with an emphasis on the utilization of TRTA TDXR and TCSR in this respect The TDM receive transmit address register TRTA of a given device specifies two key pieces of information The lower half specifies the receive address of the device while the upper half of TRTA specifies t
444. port McBSP Time division multiplexed TDM serial port Software programmable wait state generator Programmable bank switching module O O O O O L Note Enhanced Peripherals For more detailed information on the enhanced peripherals see TMS320C54x DSP Enhanced Peripherals Reference Guide SPRU302 8 2 Peripheral Memory Mapped Registers Peripherals are operated and controlled by accessing memory mapped control and data registers These registers can also transfer data to and from the peripherals Setting and clearing bits in the control registers can enable disable initialize and dynamically reconfigure the peripherals The operations of the serial ports and the timer are synchronized to the CPU through interrupts or interrupt polling When peripherals are not in use the internal clocks are shut off thus the peripherals consume less power in normal run mode or in idle mode The peripheral registers are mapped into data page 0 Table 8 1 through Table 8 7 list the individual peripheral memory mapped registers for some C54x devices 8 2 On Chip Peripherals SPRU131G Peripheral Memory Mapped Registers Table 8 1 C541 541B Peripheral Memory Mapped Registers SPRU131G Address Hex 20 21 22 23 24 25 26 27 28 29 2A 2F 30 31 32 33 57 58 59 5F Name DRRO DXRO SPCO TIM PRD TCR SWWSR BSCR DRR1 DXR1 SPC1 Description Serial port 0 data receive register Serial port 0 data tran
445. pped Registers 0000 cece eee ee eees 8 5 C546 C546A Peripheral Memory Mapped Registers 0 000 cece e eee e eee 8 6 C548 Peripheral Memory Mapped Registers 00000 ce cece e eee eee eens 8 7 C549 Peripheral Memory Mapped Registers 000 cece cece eee eee ee 8 8 C5402 Peripheral Memory Mapped Registers 200 c cece eee eee eens 8 9 C5410 Peripheral Memory Mapped Registers 0 00 scence eee teens 8 10 C5420 Peripheral Memory Mapped Registers For Each DSP Subsystem 8 11 5402 C5410 C5420 McBSP Subaddressed Registers 0 eee eee eee 8 12 C5402 C5410 C5420 DMA Subaddressed Registers 0 cee eee eee 8 13 Timer Registers idnes yee hehe want etal i a Lantana nee need eee ne 8 14 Timer Control Register TCR Bit Summary 00 cee eee 8 15 Clock Mode Configurations 0 c ccc tenets 8 16 Clock Mode Settings at Reset C541B C545A C546A C548 C549 C5410 8 17 Clock Mode Settings at Reset C5402 0 eee eee 8 18 Clock Mode Register CLKMD Bit Summary 00 eee eee eee 8 19 PLL Multiplier Ratio as a Function of PLLNDIV PLLDIV and PLLMUL 8 20 HPI Registers Description 0 0 0 c ccc eee ene eee 8 21 HPI Signal Names and Functions 0 0 eens 8 22 HPI Input Control Signals Function Selection Descriptions 00005 8 23 HPI Control Register HPIC Bit Desc
446. pped Registers Table 8 12 C5402 C5410 C5420 DMA Subaddressed Registers DMA Sub Address address Name Hex t Hex Description DMSRCO 56 57 00 DMA channel 0 source address register DMDSTO 56 57 01 DMA channel 0 destination address register DMCTRO 56 57 02 DMA channel 0 element count register DMSFCO 56 57 03 DMA channel 0 sync select and frame count register DMMCRO 56 57 04 DMA channel 0 transfer mode control register DMSRC1 56 57 05 DMA channel 1 source address register DMDST1 56 57 06 DMA channel 1 destination address register DMCTRI1 56 57 07 DMA channel 1 element count register DMSFC1 56 57 08 DMA channel 1 sync select and frame count register DMMCR1 56 57 09 DMA channel 1 transfer mode control register DMSRC2 56 57 0A DMA channel 2 source address register DMDST2 56 57 0B DMA channel 2 destination address register DMCTR2 56 57 0C DMA channel 2 element count register DMSFC2 56 57 OD DMA channel 2 sync select and frame count register DMMCR2 56 57 OE DMA channel 2 transfer mode control register DMSRC3 56 57 OF DMA channel 3 source address register DMDST3 56 57 10 DMA channel 3 destination address register DMCTR3 56 57 11 DMA channel 3 element count register DMSFC3 56 57 12 DMA channel 3 sync select and frame count register DMMCR3 56 57 13 DMA channel 3 transfer mode control register DMSRC4 56 57 14 DMA channel 4 source address register DMDST4 56 57 15 DMA channel 4 destination address register DMCTR4 56 57 16 DMA channel 4 element count re
447. pplications A 24 digital loopback mode definition digital loopback mode DLB bit definition D 7 dimensions 12 pin header A 20 14 pin header A 14 mechanical 14 pin header direct addressing diagram DP referenced instruction format 5 8 instruction word fields SP referenced direct data memory address bus definition direct data memory address bus DRB definition direct memory access DMA controller 2 14 direct memory address definition direct addressing mode DP DLB definition dma DMA controller DMA subaddressed registers C5420 dmad addressing DP definition direct addressing mode 7 63 latencies 7 64 DP load three cycle latency two cycle latenc zero latency DP referenced direct addressing diagram DRAM blocks access 7 28 DROM definition DROM setup followed by a dual read scones 7al followed by a read access DRR definition DSP articles K ki DSP interrupt DSPINT definition DSPINT definition DSPINT and HINT function operation 8 50 dual 16 bit mode 4 12 dual 16 bit double precision arithmetic mode C16 dual access memory dual data memory operand addressing auxiliary registers diagram 5 Index indirect addressing mode diagram instruction format __b 20 instruction format types of using Xmem using Ymem dual operands circular 5 22 increment decrement indexed single operand instructions dual access RAM DARAM 2 6 definition DuPont connector A 2
448. press or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such products or services might be or are used TI s publication of information regarding any third party s products or services does not constitute Tl s approval license warranty or endorsement thereof Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service is an unfair and deceptive business practice and TI is not responsible nor liable for any such use Resale of Tl s products or services with statements different from or beyond the parameters stated by TI for that products or service voids all express and any implied warranties for the associated TI product or service is an unfair and deceptive business practice and TI is not responsible nor liable for any such use Also see Standard Terms and Conditions of Sale for Semiconductor Products www ti com sc docs stdterms htm Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2001 Texas Instruments Incorporated About This Manual Preface Read This First
449. pt 26 Software interrupt 27 Software interrupt 28 Software interrupt 29 reserved Software interrupt 30 reserved External user interrupt 0 External user interrupt 1 External user interrupt 2 Internal timer interrupt Buffered serial port receive interrupt Buffered serial port transmit interrupt TDM serial port receive interrupt TDM serial port transmit interrupt External user interrupt 3 HPI interrupt Reserved Program Memory Addressing 6 39 Interrupts Table 6 21 6 40 TRAP INTR Number K Priority 0 1 o oa N O aA A O ND es oOo 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 o N 0 gt ol A wo l oO 25 31 Name RS SINTR NMI SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INTO SINTO INT1 SINT1 INT2 SINT2 TINT SINT3 BRINTO SINT4 BXINTO SINT5 TRINT SINT6 TXINT SINT7 INT3 SINT8 Program Memory Addressing Location Hex 0 4 8 C 10 14 18 iC 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 7F TMS320C543 Interrupt Locations and Priorities Function Reset hardware and software reset Nonmaskable interrupt Software interrupt 17 Software interrupt 18 Software interrupt 19 Software interrupt 20 Software interrupt 21 Software interrupt 22 Software interrupt 23 Software interrupt 24 Software interrupt 25 Software interrupt 26
450. r SPC and buffered serial port control register BSPC that indicates if the serial port receiver has experienced overrun D 14 Glossary SPRU131G SPRU131G Glossary register A group of bits used for temporarily holding data or for controlling or specifying the status of a device repeat counter RC A 16 bit register used to specify the number of times a single instruction is executed reset A means of bringing the CPU to a known state by setting the registers and control bits to predetermined values and signaling execution to start at a specified address RH See receive buffer half received RINT RINTO RINT1 See serial port receive interrupt RRDY See receive ready RRST See receiver reset RSA See block repeat start address RSR data receive shift register A 16 bit register that holds serial data received from the DR pin See also data receive register DRR RSRFULL See receive shift register full RTN See fast return register SARAM single access RAM Memory that can be read written once during one clock cycle saturation on multiplication SMUL A bit in the processor mode status register PMST that determines whether saturation of a multiplication result occurs before performing the accumulation in a MAC or MAS instruction saturation on store SST A bit in the processor mode status register PMST that determines whether saturation of the data from the accumu lator occurs before storing in
451. r Prefetch Fetch Decode Access Read Execute No No Prefetch Fetch Decode Access Read Execute No No prefetch fetch IR i8 i3 Prefetch Fetch Decode Access Read Execute 7 16 Pipeline SPRU131G Pipeline Operation Example 7 11 and Example 7 12 show pipeline behavior for a return fast RETF instruction and for a delayed return fast RETFD instruction respec tively The RETF instruction unlike the RETE instruction does not read the return address from the stack Instead it reads it from the RTN register This allows the instruction to load PAB with the return address two cycles earlier than a RETE instruction can As shown in the examples the RETF instruction takes only three cycles to execute the delayed version of the instruction RETFD executes in one cycle Example 7 11 Return Fast RETF Instruction in the Pipeline Address Instruction al RETF a2 i2 a3 i3 b1 ji 1 2 3 4 5 6 7 8 9 Prefetch Fetch Decode Access Read Execute RETE Prefetch Fetch Decode Access Read Execute Pipeline flush PAB a2 PB i2 Prefetch Fetch Decode Access Read Execute Pipeline flush PAB a3 PB i3 Prefetch Fetch Decode Access Read Execute ji PAB b1 PB j1 ji SPRU131G Pipeline 7 17 Pipeline Operation Example 7 12 Delayed Return Fast RETFD Instruction in the Pipeline Address al a2 a3 b1 1 Prefetch PB RETFD PAB al petrp PAB a2 PB i2 Instruction RETFD i2 i3 jl 3
452. rc 31 16 src 39 16 Lmem 15 0 src 15 0 src 15 0 DSADT Lmem dst Lmem 31 16 T dst 39 16 Lmem 15 0 T dst 15 0 DSUB Lmenm src src 31 16 Lmem 31 16 src 39 16 src 15 0 Lmem 15 0 src 15 0 DSUBT Lmem dst Lmem 31 16 T gt dst 39 16 Lmem 15 0 T gt dst 15 0 Legend gt Is stored to Lmem Long 32 bit data memory value src Source accumulator A or B dst Destination accumulator A or B x n m Read as bits n through m of x SPRU131G Central Processing Unit 4 25 Compare Select and Store Unit CSSU The CSSU implements the compare and select operation via the CMPS instruction a comparator and the 16 bit transition register TRN This opera tion compares two 16 bit parts of the specified accumulator and shifts the decision into bit 0 of TRN This decision is also stored in the TC bit of STO Based on the decision the corresponding 16 bit part of the accumulator is stored in data memory Example 4 4 shows the compare and select operation executed by the CMPS instruction Example 4 4 CMPS Instruction Operation CMPS B AR3 jif B 31 16 gt B 15 0 then 7B 31 16 gt AR3 TRN lt lt 1 0 gt TRN 0 Q0 gt TC else B 15 0 gt AR3 TRN lt lt 1 1 gt TRN 0O 1 gt TC TRN contains information of the path transition decisions to new states This information can be used for a back tracking routine that finds
453. rds Words ternal External External 00 FFFF 01 FFFF 02 FFFF 7F FFFF XPC 0 XPC 1 XPC 2 XPC 127 t See Figure 3 9 for more information about this on chip memory region NOTE When the on chip RAM is enabled in program space all accesses to the region xx 0000 xx 7FFF regardless of page number are mapped to the on chip RAM at 00 0000 00 7FFF 3 12 Memory SPRU131G Memory Space Figure 3 12 Data Memory Map for the C5420 Relative to CPU Subsystems A and B Hex Data 0000 Memory 005F Mapped Registers 0060 Scratch Pad 007F DARAM 0080 On Chip DARAM 0 16k Words 3FFF 4000 On Chip SARAM 1 16k Words 7FFF 8000 On Chip SARAM 2 32k Words Prog Data DROM 1 External DROM 0 FFFF SPRU131G Memory 3 13 Memory Space Figure 3 13 Program Memory Maps for the C5420 Relative to CPU Subsystems A and B Hex Program Page 0 0000 On Chip DARAM 0 16k Words Prog Data OVLY 1 External OVLY 0 EMIF t 3FFF 4000 On Chip SARAM 1 16k Words Prog Data OVL 1 External OVLY 0 EMIF t 7FFF 8000 On Chip SARAM 2 32k Words Prog Data External EMIF t FFFF extended Hex Program Page 1 10000 Hex Program Page 2 20000 On Chip On Chip DARAM 0 DARAM 0 16k Words 16k Words Prog Data Prog Data OVLY 1 OVLY 1 External External OVLY 0 OVLY 0 EMIF t EMIF t 13FFF 23FFF 14000 24000 On Chip On Chip SARAM 1 SARAM 1 16k Words 16
454. re interrupt 25 Software interrupt 26 Software interrupt 27 Software interrupt 28 Software interrupt 29 reserved Software interrupt 30 reserved External user interrupt 0 External user interrupt 1 External user interrupt 2 Internal timer interrupt Serial port O receive interrupt Serial port 0 transmit interrupt Serial port 1 receive interrupt Serial port 1 transmit interrupt External user interrupt 3 Reserved SPRU131G Interrupts Table 6 20 TMS320C542 Interrupt Locations and Priorities TRAP INTR Number K 0 oO O N OO on fF WO NY Nh Biome po Bron r EAI Bes Bee Bes ee hl CUR ores FN Fo Fao No ors OPN Fo 26 31 SPRU131G Priority 1 2 Oo N o Oo Aa WwW k Oo 12 Name RS SINTR NMI SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INTO SINTO INT4 SINT1 INT2 SINT2 TINT SINT3 BRINTO SINT4 BXINTO SINT5 TRINT SINT6 TXINT SINT7 INT3 SINT8 HPINT SINT9 Location Hex 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 68 7F Function Reset hardware and software reset Nonmaskable interrupt Software interrupt 17 Software interrupt 18 Software interrupt 19 Software interrupt 20 Software interrupt 21 Software interrupt 22 Software interrupt 23 Software interrupt 24 Software interrupt 25 Software interru
455. re simultaneously met J One instruction modifies an accumulator either A or B directly _j The next instruction tries to read that accumulator as a memory mapped register The conflict occurs because the first instruction updates an accumulator at the same time when the next instruction tries to read it as a memory mapped register Example 7 66 Accumulator Access With a 1 Cycle Latency SPRU131G ADD Smem A A is updated directly by this instruction This conflict occurs because the F F NOP i next instruction tries to read A i F F i as a memory mapped register A one cycle latency required This instruction reads A as a memory mapped register PSHM AL Pipeline 7 79 Pipeline Latencies Example 7 67 Accumulator Access With No Conflict a ADD Smem A A is updated directly by this instruction No conflict occurs because the next instruction reads accumulator A directly NEG A This instruction reads A directly b STLM A BH BH is written using memory mapped addressing here No conflict occurs because the next instruction also accesses the same accumulator as a memory mapped register PSHM BH Reads BH as a memory mapped register STLM A BH BH is written using memory mapped addressing here No conflict occurs because the next instruction accesses the sam accumulator directly NEG B This instr
456. re the context that was saved in step 1 Return from the ISR with an RETE to reenable interrupts Serial Ports Description The operating context of the interrupted code must be maintained Read the received data for the receive ISR Write the new transmit data for the transmit ISR Or do both if the ISR is combined for transmit and receive The operating context of the interrupted code must be maintained Interrupts must be reenabled for the CPU to respond to the next interrupt SPRU131G Buffered Serial Port BSP Interface 9 3 Buffered Serial Port BSP Interface SPRU131G The buffered serial port BSP is made up of a full duplex double buffered serial port interface which functions in a similar manner to the C54x DSP standard serial port and an autobuffering unit ABU see Figure 9 21 The serial port section of the BSP is an enhanced version of the C54x DSP standard serial port The ABU is an additional section of logic which allows the serial port section to read write directly to C54x DSP internal memory indepen dent of the CPU This results in a minimum overhead for serial port transfers and faster data rates The full duplex BSP serial interface provides direct communication with serial devices such as codecs serial A D converters and other serial devices with a minimum of external hardware The double buffered BSP allows transfer of a continuous communication stream in 8 10 12 or 16 bit data packets
457. register Directly accessible only by the host Contains the address in the HPI memory at which the current access occurs HPI control register Directly accessible by either the host or by the C54x DSP Con tains control and status bits for HPI operations HPI data register Directly accessible only by the host Contains the data that was read from the HPI memory if the current access is a read or the data that will be written to HPI memory if the current access is a write The two data strobes HDS1 and HDS2 the read write strobe HR W and the address strobe HAS enable the HPI to interface to a variety of industry standard host devices with little or no additional logic required The HPI is easi ly interfaced to hosts with multiplexed address data bus separate address and data buses one data strobe and a read write strobe or two separate strobes for read and write This is described in detail later in this section The HPI ready pin HRDY allows insertion of wait states for hosts that support a ready input to allow deferred completion of access cycles and have faster cycle times than the HPI can accept due to C54x CPU operating clock rates If HRDY when used directly from the C54x CPU does not meet host timing requirements the signal can be resynchronized using external logic if neces sary HRDY is useful when the C54x CPU operating frequency is variable or when the host is capable of accessing at a faster rate than the maximum
458. rently active block repeat counter BRC A 16 bit register that specifies the number of times a block of code is to be repeated when a block repeat is performed block repeat end address register REA A 16 bit memory mapped register containing the end address of a code segment being repeated block repeat start address register RSA A 16 bit memory mapped register containing the start address of a code segment being repeated BMINT See buffer misalignment interrupt boot The process of loading a program into program memory bootloader A built in segment of code that transfers code from an external source to program memory at power up BRAF See block repeat active flag BRC See block repeat counter BRE See autobuffering receiver enable BRINT BRINTO BRINT1 See BSP receive interrupt BRSR BSP data receive shift register A 16 bit register that holds serial data received from the BDR pin See also BDRR BSCR See bank switching control register BSP buffered serial port An enhanced synchronous serial port that includes an autobuffering unit ABU that reduces CPU overhead in performing serial operations BSP receive interrupt BRINT BRINTO BRINT1 A bitin the interrupt flag register IFR that indicates the BSP data receive shift register BRSR contents have been copied to the BSP data receive register BDRR BRINTO corresponds to buffered serial port 0 BRINT1 corresponds to buff ered serial port 1 BSP
459. resides at address FF80h in program memory space The RESET instruction does not affect this field 6 MP MC MP MC Microprocessor microcomputer mode MP MC enables disables the on chip pin ROM to be addressable in program memory space MP MC 0 The on chip ROM is enabled and addressable MP MC 1 The on chip ROM is not available MP MC is set to the value corresponding to the logic level on the MP MC pin when sampled at reset This pin is not sampled again until the next reset The RESET instruction does not affect this bit This bit can also be set or cleared by software 5 OVLY 0 RAM overlay OVLY enables on chip dual access data RAM blocks to be mapped into program space The values for the OVLY bit are OVLY 0 The on chip RAM is addressable in data space but not in program space OVLY 1 The on chip RAM is mapped into program space and data space Data page 0 addresses Oh to 7Fh however is not mapped into program space 4 6 Central Processing Unit SPRU131G CPU Status and Control Registers Table 4 3 Processor Mode Status Register PMST Bit Summary Continued Bit Name 4 AVIS 3 DROM 2 CLKOFFT 1 SMULt Reset Value 0 0 0 N A Function Address visibility mode AVIS enables disables the internal program address to be visible at the address pins AVIS 0 The external address lines do not change with the internal program address Control and data lines are not affected and the address bus is driven
460. rial Port Receive With Long FSR Pulse 00 00 cee cece eee ee eens Burst Mode Serial Port Transmit at Maximum Packet Frequency Burst Mode Serial Port Receive at Maximum Packet Frequency 4 Continuous Mode Serial Port Transmit 0 00 cece eee eee eee Continuous Mode Serial Port Receive 00 cece eee eee SP Receiver Functional Operation Burst Mode 0 cece eee eee eens BSP Receiver Functional Operation Burst Mode 00 0cceeeeee eee eee SP BSP Transmitter Functional Operation Burst Mode 002220eeeeee SP BSP Receiver Functional Operation Continuous Mode 00000 SP BSP Transmitter Functional Operation Continuous Mode 00 BSP Block Diagram 05 2 2242 20ncadse Post O eda teadadeeatoeakdas Raed s BSP Control Extension Register BSPCE Diagram Serial Port Control Bits Transmit Continuous Mode with External Frame and FIG 1 Format Is 16 Bits ABU Block Diagram saciar aii Haka AAAA AA ATAA EARRA ARSAN TS BSP Control Extension Register BSPCE Diagram ABU Control Bits Circular Addressing Registers 00 cece nenun aeea Transmit Buffer and Receive Buffer Mapping Example 2 0000eeeeeee Standard Mode BSP Initialization Timing 00 0 e cece eee eee Autobuffering Mode Initialization Timing 00 00 cc cece eee eens Time Division Multiplexing
461. ring is enabled for transmit or receive respectively BDRR can only be read and BDXR can only be written when the ABU is disabled BDRR can only be written when the BSP is in reset BDXR can be read any time The buffered serial port registers are summarized in Table 9 7 The ABU utilizes several additional registers which are discussed in section 9 3 2 Auto buffering Unit ABU Operation on page 9 40 Table 9 7 Buffered Serial Port Registers Address Register Description ili BDRR 16 bit BSP data receive register t BDXR 16 bit BSP data transmit register t BSPC 16 bit BSP control register t BSPCE 16 bit BSP control extension register BRSR 16 bit BSP data receive shift register BXSR 16 bit BSP data transmit shift register t See section 8 2 Peripheral Memory Mapped Registers SPRU131G Serial Ports 9 35 Buffered Serial Port BSP Interface 9 3 1 1 Differences Between Serial Port and BSP Operation in Standard Mode The differences between serial port and BSP operation in standard mode are discussed in detail in the standard mode serial port operation section 9 2 on page 9 4 These differences relate primarily to boundary conditions how ever in some systems these differences may be significant The differences are summarized in Table 9 8 Table 9 8 Differences Between Serial Port and BSP Operation in Standard Mode Condition RSRFULL is set Preservation of data in RSR on overrun Continuous mode rece
462. rior to reading this section section 9 2 Serial Port Interface on page 9 4 and section 9 3 1 BSP Operation in Standard Mode on page 9 35 Also you should note that when operating in autobuffering mode the serial port control and status bits in BSPC and BSPCE function in the same fashion as in standard mode The ABU implements the capability to move data transferred on the serial port to and from internal C54x DSP memory independent of CPU intervention The ABU utilizes five memory mapped registers the address transmit register AXR the block size transmit register BKX the address receive register ARR and the block size receive register BKR along with the BSPCE These registers are summarized in Table 9 11 Table 9 11 Autobuffering Unit Registers Address Register Description Ti BSPCE 16 bit BSP control extension register t AXR 11 bit BSP address transmit register ABU Ti BKX 11 bit BSP transmit buffer size register ABU T ARR 11 bit BSP address receive register ABU Fp BKR 11 bit BSP receive buffer size register ABU t See section 8 2 Peripheral Memory Mapped Registers 9 40 Serial Ports SPRU131G SPRU131G Buffered Serial Port BSP Interface Figure 9 24 shows the block diagram of the ABU The BSPCE contains bits which control ABU operation and will be discussed in detail later in this section AXR BKX ARR and BKR along with their associated circular addressing logic allow address generation for acc
463. riptions 0 0 cee eee 8 24 HPIC Host TMS320C54x DSP Read Write Characteristics 0002000005 8 25 Wait State Generation Conditions 0 00 e eect eee eee 8 26 Initialization of BOB and HPIA 2 tenets 8 27 Read Access to HPI With Autoincrement 000 c cee ee 8 28 Write Access to HPI With Autoincrement 000 cece eee 8 29 Sequence for Entering and Exiting IDLE2 and IDLE3 0002020005 8 30 HPI Operation During RESET socas sinade nanai ee adina aaa i teeta 9 1 Serial Ports on the TMS320C54x Devices 000 eee eee eens 9 2 Sections that Discuss the Serial Ports 00 0 cece eee eee eens 9 3 Serial Port Registers 00 c cece aiai n ad aia oa eee eens 9 4 Senal Port PINS esse idrardan naaa ELAR ENEA 9 5 Serial Port Control Register SPC Bit Summary 000 cee eee eee 9 6 Serial Port Clock Configuration 00 eee eee ene eee 9 7 Buffered Serial Port Registers cece eee eee teens 9 8 Differences Between Serial Port and BSP Operation in Standard Mode 9 9 BSP Control Extension Register BSPCE Bit Summary Serial Port Control Bits 9 10 Buffered Serial Port Word Length Configuration 0000 0c c eee eee eee xxviii Tables SPRU131G Tables 9 11 Autobuffering Unit Registers 2 0 0 ccc teeta 9 12 BSP Control Extension Register BSPCE Bit Summary ABU Control
464. rmem pmad src ADD dirmem shift src dst LD dirmem shift dst STH src shift dirmem With an extended shiftt STL src shift dirmem SUB dirmem shift src dst Legend SP Destination operand pointing to the stack pointer in either direct or indirect addressing modes MMR Any memory mapped register except SP spind Destination operand pointing to the stack pointer using indirect addressing mode dirmem Operand using direct addressing mode in compiler mode CPL 1 t Add one more cycle of latency if the first instruction meets the DAGEN register conflict criteria See section 7 5 3 Rules to Determine DAGEN Register Access Conflicts for more information Shift value between 16 and 15 Notes 1 Any instruction that does not fit in either of the two categories has zero latency SPRU131G 2 The first instruction can be any C54x DSP instruction Pipeline 7 51 Pipeline Latencies Example 7 31 SP Load With No Latency in Compiler Mode CPL 1 a ADD A B This instruction does not create a DAGEN conflict MVDK 100h SP This SP update requires a zero latency according to the above table ADD 50h 3 A B b STLM A AR2 This instruction does not affect pipeline latency POPM ARI This SP update requires a zero latency according to the table MVKD 100h 1h Example 7 32 SP Load With a 1 Cycle Latency in Compiler Mode CPL 1 a STL
465. rogram 0000 Reserved OVLY 1 External OVLY 0 007F 0080 On Chip DARAM OVLY 1 External OVLY 0 3FFF 4000 EFFF F000 On Chip ROM 4K x 16 bits FEFF FFOO FF7F FF80 Interrupts On Chip FFFF MP MC 0 Microcomputer Mode Memory Space Hex Data 0000 Memory Mapped Registers 005F 0060 Scratch Pad RAM 007F 0080 On Chip DARAM 16K x 16 bits 3FFF 4000 EFFF F000 ROM DROM 1 or External DROM 0 FEFF FFOO Reserved DROM 1 or External DROM 0 FFFF Memory 3 9 Memory Space Figure 3 8 Extended Program Memory for the C5402 00 0000 1 0000 2 0000 F 0000 Page 1 Page 2 Page 15 Lower Lower Lower 32Kt 32Kt 32Kt External External External Page 0 1 7FFF 2 7FFF F 7FFF 64K 1 8000 2 8000 F 8000 Wordst Page 1 Page 2 Page 15 Upper Upper Upper 32K 32K 32K External External External 0 FFFF 1 FFFF 2 FFFF F FFFF t See DMA memory map The lower 32K words of pages 1 through 15 are available only when the OVLY bit is cleared to 0 If the OVLY bit is set to 1 the on chip RAM is mapped to the lower 32K words of all program space pages 3 10 Memory SPRU131G Figure 3 9 Memory Maps for the C5410 Program Hex 0000 Reserved OVLY 1 External OVLY 0 007F 0080 On Chip DARAM OVLY 1 External OVLY 0 1FFF 2000 On Chi SARAM1 OVLY 1 External OVLY 0 7FFF 8000 External FF7F FF80 Interrupts and Reserved External F
466. rogram space select Data space select I O access strobe I O space select Read write signal Data ready to complete cycle Hold request Hold acknowledge Micro state complete Instruction acquisition Interrupt acknowledge 10 2 The parallel interface consists of two mutually exclusive interfaces controlled by the MSTRB and IOSTRB signals MSTRB is activated for memory accesses program or data and IOSTRB is used to access I O ports The R W signal controls the direction of the accesses The external ready input signal READY and the software generated wait states allow the processor to interface with memory and I O devices of varying speeds When communicating with slower devices the CPU waits until the other device completes its function and sends the READY signal to continue execution External Bus Operation SPRU131G SPRU131G External Bus Interface In some cases wait states are needed only when transitions are made between two external memory devices The programmable bank switching logic provides automatic insertion of a wait state in these situations The hold mode allows an external device to take control of the C54x DSP external buses to access the resources in the C54x DSP external program data and I O memory spaces Two hold mode types normal mode and concurrent DMA mode are available When the CPU addresses internal memory the data bus is placed in the high impedance state However the address
467. rol register TCR 8 22 timer control register TCR 8 21 definition diagram PSC bits PSC field TDDR bits TDDR field timer counter register TIM definition timer divide down register TDDR definition timer enabling 8 25 timer initialization timer interrupt TINT definition D 18 timer interrupt rate equation timer operation timer period register PRD 8 21 definition Index timer prescaler counter PSC definition timer register TIM 8 21 timer registers 8 21 timer reload TRB definition timer stop status TSS definition timing XF timing calculations A 7 to A 9 to A 24 timing diagrams external bus interface priority external bus reset sequence hold and reset interaction IDLE3 wake up sequence 10 27 memory interface 10 15 to 10 23 TINT D 18 definition TMS signal mala a 4 fa 5 fa 6 A 7 A 8 A 13 SNS See TMS TDI inputs TMS320 DSP family applications to TMS320 DSPs applications table TMS320 DSP family 1 2 to 1 6 advantages 1 2 evolution figure history overview TMS320C54x DSP TMS320 DSP ROM code submittal figure C 2 TMS320C542 mapping code on chip ROM TMS320C54x DSP_ 1 5 to 1 8 emulation instruction set memory peripherals ports power speed internal block diagram overview 1 5 tools part numbers tools nomenclature prefixes B 5 TRAD definition Index 19 Index definition transmit buffer half transmitted XH
468. rol register is normally the first register accessed to set configuration bits and initialize the interface the HPIC is organized on the host side as a 16 bit register with the same high and low byte contents although access to certain bits is limited as described previously and with the upper bits unused on the C54x DSP side The control status bits are located in the least significant four bits The host accesses the HPIC register with the appropriate selection of HCNTLO 1 as described previously and two consecutive byte accesses to the 8 bit HPI data bus When the host writes to HPIC both the first and second byte written must be the same value The C54x DSP accesses the HPIC at 002Ch in data memory space The layout of the HPIC bits is shown in Figure 8 9 through Figure 8 12 In the figures for read operations if 0 is specified this value is always read if X is specified an unknown value is read For write operations if X is specified any value can be written On a host write both bytes must be identical Note that bits 4 7 and 12 15 on the host side and bits 4 15 on the C54x DSP side are reserved for future expansion Figure 8 9 HPIC Diagram Host Reads from HPIC 15 12 11 10 9 8 7 4 3 2 1 0 0_ svon Bos x Hint o smon Bos Note X Unknown value is read 8 44 On Chip Peripherals SPRU131G Host Port Interface Figure 8 10 HPIC Diagram Host Writes to HPIC 15 12 11 10 9 8 7 4 3 2 1 0 x HINT x x Not
469. rrupt Vector Addresses The interrupt vectors can be remapped to the beginning of any 128 word page in program memory except in reserved areas The interrupt vector address is generated by concatenating the interrupt pointer IPTR field of PMST with the interrupt vector number 0 31 shifted by 2 Consider the example of Figure 6 4 if INTO is asserted low and IPTR 0001h the interrupt vector is fetched from OOCOh The interrupt vector number for INTO is 16 or 10h Figure 6 4 Interrupt Vector Address Generation Vector 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 Bit 15 14 13 12 1110 9 8 7 6 5 4 3 2 Address 0 0 C 0 IPTR 0 0000 0001 a ee INT 40h INTO 4 lt O At reset the IPTR bits are set to 1 IPTR 1FFh this value maps the vectors to page 511 in program memory space Therefore the reset vector for hard ware resets always resides at location OFF80h The interrupt vectors can be mapped to another location by loading IPTR with a value other than 1FFh For example the interrupt vectors can be moved to start at location 0080h by load ing IPTR with 0001h a Note The hardware reset RS vector cannot be remapped because the hardware reset loads the IPTR with 1s Therefore the reset vector for hardware resets is always fetched at location FF80h in program space aAA AAA AAAA AAA Program Memory Addressing SPRU131G Interrupts Figure 6 5 Flow Diagram of Interrupt Operation Interrup
470. rst device on the main JTAG scan path TDIO on the TBC is connected to the TDO signal of the last device on the main JTAG scan path Within the main JTAG scan path the TDI signal of a device is connected to the TDO signal of the device before it TRST for the devices can be generated either by inverting the TBC s TMS5 EVNTS signal for software control or by logic on the board itself Design Considerations for Using XDS510 Emulator A 25 Appendix B Development Support and Part Order Information This appendix provides development support information device part numbers and support tool ordering information for the TMS320C54x DSP More than 100 third party developers offer products that support the TMS320 family of DSPs For more information refer to the TMS320 Third Party Support Reference Guide SPRU052 For information on pricing and availability contact the nearest TI Field Sales Office or authorized distributor See the list at the back of this book Topic Page B1 Development SUpport ceee eee a e a B 2 B20 Part Order Informationen e E E B 5 B 1 Development Support B 1 Development Support This section describes the development support provided by Texas Instruments B 1 1 Development Tools TI offers an extensive line of development tools for the C54x generation of DSPs including tools to evaluate the performance of the processors generate code develop algorithm implementations and fully in
471. rt If the TDM port is to be manipulated on Serial Ports 9 63 Time Division Multiplexed TDM Serial Port Interface a slot by slot basis changes must be made to appropriate registers quickly enough for the desired effect to take place at the desired time It is also important to take into account that the TCSR and the receive address lower half of TRTA take effect only at the start of a new frame while the transmit address upper half of TRTA and TDXR transmit data can take effect at the start of a new slot as mentioned previously Note that if the transmit address is being changed on the fly care should be exercised not to corrupt the receive address since both addresses are located in the TRTA thus maintaining the convention of allowing the transmitting device to specify which devices can receive 9 4 5 TDM Serial Port Interface Exception Conditions Because of the nature of the TDM architecture with the ability for one proces sor to transmitin multiple slots the concepts of overrun and underflow become indeterminate Therefore the overrun and underflow flags are not active in TDM mode In the receiver if TRCV has not been read and a valid receive operation is initiated because of the value on TADD and the device s receive address the present value of TRCV is overwritten the receiver is not halted On the other hand if TDXR has not been updated before a transmission the TADD or TDAT lines are not driven and these p
472. rt Interface Exception Conditions on page 9 26 In continuous mode transmission one frame sync is generated following the first DXR load and no further frame syncs are generated As long as DXR is reloaded once every transmission continuous transfers are maintained Fail ing to update DXR causes the serial port to halt as in the burst mode case XSREMPTY becomes asserted etc If DXR is reloaded after a halt the device begins continuous mode transmission again and generates a single FSX assuming that internal frame sync generation is selected SPRU131G Serial Port Interface The distinction between internal and external frame syncs for continuous mode is similar to that of burst mode as discussed in section 9 2 4 Burst Mode Transmit and Receive Operations on page 9 18 If frame sync is externally generated TXM 0 then when DXR is loaded the appearance of the frame sync pulse initiates continuous mode transmission Continuous mode trans mission may be discontinued and burst mode resumed only by reconfiguring and resetting the serial port see section 9 2 2 Serial Port Interface Operation on page 9 6 Simply changing the FSM bit during transmit or halt will not properly switch to burst mode Continuous mode transmit timing shown in Figure 9 14 is similar to maxi mum packet frequency transmission in burst mode as shown in Figure 9 12 The major difference is the lack of a frame sync pulse after the initial one As long as
473. rt continuous mode at the next word byte boundary after DRR is read no new FSR pulse is required On the BSP continuous mode reception does not resume until DRR is read and an FSR occurs Continuous mode reception may only be discontinued by reconfiguring and resetting the serial port Simply changing the FSM bit during a reception or halt will not properly switch to burst mode Continuous mode receive timing is shown in Figure 9 15 Figure 9 15 Continuous Mode Serial Port Receive DR FO 1 FSR KAT A2 KAS KAS KAS AG KA AAAS ABI K_B K_B3 XK _B4 K_BS MSB LSB RRDY RINT DRR DRR loaded read from RSR Figure 9 15 shows only one frame sync pulse otherwise it is similar to Figure 9 13 If a pulse occurs on FSR during a transfer an error then the receive operation is aborted one packet is lost and a new receive cycle is begun This is discussed in more detail in section 9 2 2 Serial Port Interface Operation on page 9 6 and in section 9 2 6 Serial Port Interface Exception Conditions 9 2 6 Serial Port Interface Exception Conditions 9 26 Serial Ports Exception or error conditions result from an unexpected event occurring on the serial port These conditions are operational aberrations such as overrun underflow or a frame sync pulse during a transfer Understanding how the serial port handles these errors and the state it acquires during these error cond
474. ructions are saturated See Example 4 1 on page 4 9 for examples of saturation on multiplication operations T These bits are only supported on C54x devices with revision A or later or on C54x devices numbered C548 or greater SPRU131G Central Processing Unit 4 7 CPU Status and Control Registers Table 4 3 Processor Mode Status Register PMST Bit Summary Continued Bit 0 Reset Name Value Function sstTt N A Saturation on store When SST 1 saturation of the data from the accumulator is enabled before storing in memory The saturation is performed after the shift operation Saturation on store takes place with the following instructions STH STL STLM DST ST ADD ST LD ST MACR R ST MAS R ST MPY and ST SUB The following steps are performed when using saturate on store 1 3 4 A 40 bit data value is shifted right or left depending on the instruction The shift is the same as described in the SFTA instruction and depends on the SXM bit The 40 bit data value is saturated to a 32 bit value the saturation depends on the SXM bit the number is always assumed to be positive If SXM 0 the following 32 bit value is generated E FFFF FFFFh if the value is greater than FFFF FFFFh If SXM 1 the following 32 bit value is generated E 7FFFFFFFMH if the value is greater than 7FFF FFFFh H 8000 0000h if the value is less than 8000 0000h The data is stored in memory depending upon instruction
475. ructions for Writing to ST1 0 0 2 0 eee eee 7 15 Pipeline Protected Instruction to Update ARP in Compatibility Mode CMPT 1 7 16 Latencies for ARP in Compatibility Mode CMPT 1 and CMPT bit 7 17 Recommended Instructions to Update DP in Noncompiler Mode CPL 0 7 18 Latencies for DP in Noncompiler Mode CPL 0 0 0 cece eee eens 7 19 Latencies for the CPL Bit 0 6 ccc tenet nee eens 7 20 Latencies for the SXM Bit 0 cette tne tenes 7 21 Pipeline Protected Instructions for Writing to ASM 02 cece eee eee 7 22 Latencies for ASM Bit Field 0 ccc cette ete n eee neees 7 23 Recommended Instructions for Writing to BRC Before an RPTB Loop 7 24 Latencies for Updating BRC Before an RPTB Loop 2 00 ccc eeee eee aes SPRU131G Tables xxvii Tables 7 25 Latencies for Updating BRC From Within an RPTB Loop 0002020005 7 26 Latencies for OVLY IPTR and MP MC Bits ccc cece eee cece eee eeuas 7 27 Latencies for the DROM Bit 0c ccc teens 7 28 Latencies for Accumulators A and B When Used as Memory Mapped Registers 8 1 C541 541B Peripheral Memory Mapped Registers 00 cece eee eens 8 2 C542 Peripheral Memory Mapped Registers 0000 cece eee teen eens 8 3 C543 Peripheral Memory Mapped Registers 0060 c cece eee eee eens 8 4 C545 C545A Peripheral Memory Ma
476. ry In the first option the auxiliary register is not updated In the second option the auxiliary register is updated with the new address Data Addressing SPRU131G Indirect Addressing This type of addressing is useful in accessing a specific element of an array or structure especially when the auxiliary register is not updated When the auxiliary register is updated this type of addressing is especially useful for stepping through an array in fixed size steps The syntaxes for offset addressing of an AR without and with updating the AR using offset addressing are shown in Table 5 4 in MOD 12 and 13 respectively EN Notes 1 Instructions using offset addressing cannot be repeated using the repeat single instruction 2 Premodification by a 16 bit word offset ARx Ik uses an extra cycle because the instruction code has two or three words The last word is the offset ESSSS_ _ _ anaannpa_ ms a _ S S 5 5 3 3 Indexed Address Modifications MOD 5 or 6 Indexed addressing is a type of indirect addressing in which the contents of ARO are added to or subtracted from any other auxiliary register ARx Indexed addressing differs from offset addressing in that the index or step size can be determined during code execution Because the index is determined during code execution you can easily make adjustments to the step size Indexed addressing also offers
477. ry Il Category Ill Category IV BACC D BC D B D INTR CALA D CCID BANZ D RETF D FRET D RC D CALL D TRAP FRETE D RET D FB D FBACC D RETE D FCALL D FCALA D Legend pmst Destination operand pointing at PMST to modify OVLY IPTR MP MC in either direct indirect or memory mapped addressing modes Notes 1 Additional latency cycles are required if an external memory access is in progress when an instruction is trying to modify OVLY IPTR or MP MC bit fields 2 The second instruction loads PC with a new value that points to the modified program address range Example 7 59 OVLY Setup Followed by an Unconditional Branch DP 0 ORM 20h PMST This instruction sets OVLY to 1 NOP NOP B onchip Branch to on chip dual access memory Example 7 60 OVLY Setup Followed by a Conditional Branch MVDK 5h PMST This instruction sets OVLY to 1 BC onchip AEQ Branch to on chip dual access memory 7 76 Pipeline SPRU131G Pipeline Latencies Example 7 61 OVLY Setup Followed by a Return DP 0 ANDM 0ffdfh PMST This instruction sets OVLY to 0 NOP RET Return to off chip memory Example 7 62 MP MC Setup Followed by an Unconditional Delayed Call STLM A PMST This instruction sets MP MC to 1 NOP NOP CALLD offchip Call a routine in external program memory after executing STM k AR1 this 2 word instruction Example 7 63 IPTR Setup Follo
478. ry interrupt mask register IMR 3 26 on chip latency time 6 34 dual access RAM DARAM p d ee ROM security nested 2 NMI 6 27 shared RAM p d kabl 26 D 12 single access RAM SARAM p d S eo organization RS interrupt internal transmit clock division factor CLKDV saving data 6 34 definition D 11 soft reset interrupt definition D 11 user maskable external interrupt flag register IFR interrupts phases BRINT bit acknowledge interrupt 6 32 BXINT bit execute interrupt service routine definition receive interrupt request diagram INTM definition RINT bit introduction to TINT bit features 1 6 TRINT bit TMS320 DSP family overview 1 2 TMS320C54x DSP overview 1 5 IPIRQ interprocessor interrupt request bit 10 9 IPTR definition latencies table 7 76 IPTR setup followed by a software trap IR definition TXINT bit JTAG interrupt mask register IMR 8 274 6 29 JTAG emulator definition buffered signals A 10 diagram connection to target system A 1 to A 25 interrupt mode INTM 4 4 no signal buffering definition interrupt operation 6 35 diagram interrupt phases 6 27 latencies interrupt service routine definition D 11 accessing ARx 7 46 accessing BK interrupt tables 6 38 ae auxiliary register interrupt vector address generation diagram 6 36 BK interrupt vector pointer IPTR 4 6 DROM bit table definition store instructions 7 39 Index 10 Inde
479. ry locations reads and writes of two consecutive memory locations and a read of one memory location combined with a write to a memory location Single Operand Addressing Figure 5 7 shows the indirect addressing instruction format for a single data memory Smem operand Table 5 3 describes the bits of the instruction Figure 5 7 Indirect Addressing Instruction Format for a Single Data Memory Operand 15 8 7 6 3 2 0 Table 5 3 Indirect Addressing Instruction Bit Summary Single Data Memory Bit ls 6 7 6 3 5 10 Operand Name Function Opcode This eight bit field contains the operation code for the instruction MOD 1 the addressing mode used by the instruction is the indirect addressing mode This 4 bit modification field defines the type of indirect addressing section 5 5 3 Single Operand Address Modifications on page 5 13 describes the 16 ways to specify addres sing types with the MOD field Data Addressing SPRU131G Indirect Addressing Table 5 3 Indirect Addressing Instruction Bit Summary Single Data Memory Operand Continued Bit Name Function 2 0 ARF This 3 bit auxiliary register field defines the auxiliary register used for addressing ARF depends on the compatibility mode bit CMPT in status register ST1 CMPT 0 Standard mode In standard mode ARF always specifies the auxiliary regis ter regardless of the value in ARP ARP is not updated ARP must always be cleared to zero when the
480. ry register memory mapped register conflict example auxiliary registers ARP indexes definition AVIS See also address visibility mode definition AXR definition B See accumulator B bank switching 1 0 9 to 10 13 adding a cycle BSCR control register 10 9 field description example _ 10 12 size 10 10 bank switching control register BSCR bit summary BNKCMP bits definition diagram EXIO bit PS DS bit BDRR definition BDXR definition BG register BH BH register BIO definition pin 8 20 0 9 bit reversed addressing auxiliary register modifications _ 5 1 step bit pattern relationship BK See also circular buffer size register BKR definition BKX definition BL register 3 26 block diagrams C54x internal architecture 2 2 arithmetic logic unit ALU 4 10 circular addressing circular buffer implementation compare select store unit CSSU aA Index direct addressing indirect addressing dual data memory operands 5 21 single data memory operand 5 12 memory mapped register addressing multiplier adder 4 20 shifter software wait state generator timer 8 23 block repeat counter register end address register start address register block repeat operation looping 6 23 block repeat active flag BRAF 4 4 definition block repeat counter BRC definition block repeat end address REA definition block repeat start address RSA definition boot loader defini
481. s Serial Ports 9 13 Serial Port Interface MCM Bit TXM Bit packet frequency increases it reaches a maximum that occurs when the time in serial port clock cycles from one packet to the next is equal to the number of bits being transferred If transmission occurs at the maximum rate for multiple transfers in a row however frame sync essentially becomes redundant Note that frame sync actually becomes redundant in burst mode only at maximum packet frequency with FSX configured as an output TXM 1 When FSX is an input TXM 0 its presence is required for trans missions to occur FSM 0 selects the continuous mode of operation which requires only an initial frame sync pulse as long as a write to DXR for transmit or aread from DRR for receive is executed during each transfer Note that when FSM 0 frame sync pulses are not required but they are not ignored therefore improperly timed frame syncs may cause errors in serial transfers The timing of burst and continuous modes is discussed in detail in sections 9 2 4 9 2 5 and 9 2 6 The serial port clock source is set by MOM bit 4 If MCM 0 CLKX is config ured as an input and thus accepts an external clock If MCM 1 then CLKX is configured as an output and is driven by an internal clock source For the SP and the BSP operating in standard mode this on chip clock is at a frequen cy of one fourth of CLKOUT The BSP also allows the option of generating clock fr
482. s TDM serial port Timer Wait state generator Read This First Turn to these chapters Chapter 6 Program Memory Addressing Chapter 2 Architectural Overview Chapter 3 Memory Chapter 8 On Chip Peripherals Chapter 1 Introduction Chapter 2 Architectural Overview Chapter 8 On Chip Peripherals Chapter 6 Program Memory Addressing Chapter 6 Program Memory Addressing Chapter 7 Pipeline Chapter 6 Program Memory Addressing Appendix C Submitting ROM Codes to TI Chapter 9 Serial Ports Chapter 4 Central Processing Unit Chapter 9 Serial Ports Chapter 2 Architectural Overview Chapter 8 On Chip Peripherals Chapter 2 Architectural Overview Chapter 8 On Chip Peripherals SPRU131G Notational Conventions Information About Cautions Notational Conventions This book uses the following conventions LJ The TMS320C54x DSP can use either of two forms of the instruction set amnemonic form or an algebraic form This book uses the mnemonic form of the instruction set For information about the mnemonic form of the instruction set see TMS320C54x DSP Reference Set Volume 2 Mnemonic Instruction Set literature number SPRU172 For information about the algebraic form of the instruction set see TMS320C54x DSP Reference Set Volume 3 Algebraic Instruction Set literature number SPRU179 Lj Program listings and program examples are shown ina special type face Here is a segment of a program listing STL A
483. s allows the device to run with lower power consumption The software programmable wait state generator is controlled by the 16 bit software wait state register SWWSR which is memory mapped to address 0028h in data space The program and data spaces each consist of two 32K word blocks the I O space consists of one 64K word block Each of these blocks has a correspond ing 3 bit field in the SWWSR These fields are shown in Figure 10 2 and described in Table 10 2 The SWWSR bit fields of the C548 C549 C5402 C5410 and C5420 are described in Table 10 3 The value of a 3 bit field in SWWSR specifies the number of wait states to be inserted for each access in the corresponding space and address range The minimum value which adds no wait states is O 000b A value of 7 111b provides the maximum number of wait states Figure 10 2 Software Wait State Register SWWSR Diagram 15 14 12 11 9 8 6 5 3 R R W R W Tt XPA bit on C548 C549 C5402 C5410 and C5420 only SPRU131G External Bus Operation 10 5 External Bus Control Table 10 2 Software Wait State Register SWWSR Bit Summary Reset Bit Name Value Function 15 Reserved 0 Reserved In the C548 and C549 this bit changes the operation of the program fields see Table 10 3 14 12 I O 1 I O space The field value 0 7 corresponds to the number of wait states for I O space 0000 FFFFh 11 9 Data 1 Data space The field value 0 7 corresponds to the number of wait states for
484. s are completed Figure 10 1 External Bus Interface Priority One WF TY FF EF TF PB Fetch CB DB Reads EB Write D 15 0 Feat Rat Fo Pipeline conflicts occur when the program and data are in external memory and a single operand write instruction is followed by a dual operand read or a 32 bit operand read The following sequence of instructions shows the pipe line conflict discussed SE T AR6 Smem write operation LD AR4 A Xmem and Ymem read operation IMAC AR5 B Chapter 7 Pipeline describes pipeline operation and conflicts in detail 10 4 External Bus Operation SPRU131G External Bus Control 10 3 External Bus Control Two units in the C54x DSP control the external bus the wait state generator and the bank switching logic These units are controlled by two registers the software wait state register SWWSR and the bank switching control register BSCR 10 3 1 Wait State Generator The software programmable wait state generator can extend external bus cycles by up to seven machine cycles 14 machine cycles on C5402 C5409 C5410 and C5420 devices providing a convenient means to interface the C54x DSP to slower external devices Devices that require more than seven wait states can be interfaced using the hardware READY line When all external accesses are configured for zero wait states the internal clocks to the wait state generator are shut off Shutting off these paths from the internal clock
485. s internal register the MSTRB memory strobe signal is not asserted for one CLKOUT cycle During this extra cycle the address bus switches to the new address The contents of the internal register are replaced with the MSBs for the read of the current address If the MSBs of the address used for the current read match the bits in the register a normal read cycle occurs If repeated reads are performed from the same memory bank no extra cycles are inserted When aread is performed from a different memory bank memory conflicts are avoided by inserting an extra cycle An extra cycle is inserted only if a read memory access is followed by another read memory access This feature can be disabled by clearing BNKCMP to 0 The C54x DSP bank switching mechanism automatically inserts one extra cycle in the following cases Lj Aprogram memory read followed by another program memory or data memory read from a different memory bank _ A program memory read followed by a data memory read when the PS DS bit is set to 1 _ Aprogram memory read followed by another program memory read from a different page with the C548 C549 C5402 and C5420 External Bus Operation 10 11 External Bus Control J A data memory read followed by another program memory or data memory read from a different memory bank Li A data memory read followed by a program memory read when the PS DS bit is set to 1 Figure 10 6 illustrates the addition of an in
486. s of 01h Example 9 7 shows the procedure for device 1 It has a receive address of 01h SPRU131G Time Division Multiplexed TDM Serial Port Interface Example 9 5 TDM Serial Port Transmit Initialization Routine Action Reset and initialize the TDM seri al port by writing 0039h to TSPC Clear any pending TDM serial port transmit interrupts by writing 0080h to IFR Enable the TDM serial port inter rupts by ORing 0080h with IMR Enable interrupts globally if nec essary by clearing the INTM bit in ST1 Write 0001h to TCSR Write 0100h to TRTA Start the serial port by writing 0049h to TSPC Perform a handshake to verify that the receiving device is ready to receive data Write the first data value to TDXR if not already done in step 8 Description This places both the transmit and receive portions of the TDM serial port in reset and sets up the serial port to operate with internally generated TFRM and TCLK signals in TDM mode Eliminate any interrupts that may have occurred before initialization Enable transmit interrupts Interrupts must be globally enabled for the CPU to respond This selects time slot 0 as the transmission time slot for this device This sets up this device to transmit data to the device receiving at address 01h It also sets up this device to ignore all received data This takes the transmit portion of the serial port out of reset and starts operations with the conditions d
487. s the six stages of the pipeline and the events that occur in each stage The first two stages of the pipeline prefetch and fetch are the instruction fetch sequence In one cycle the address of a new instruction is loaded In the following cycle an instruction word is read In case of multiword instructions several such instruction fetch sequences are needed SPRU131G Pipeline Operation Figure 7 1 Pipeline Stages Loads PAB with the PC s contents Loads IR with the contents Loads DB with the data1 of PB read operand Decodes the IR s contents Loads CB with the data2 read operand Loads EAB with the data3 write address if required Loads PB with the Loads DAB with the data1 read Executes the instruction fetched instruction address if required and loads EB with write word Loads CAB with the data2 read data address if required Updates auxiliary registers and stack pointer SPRU131G Time gt During the third stage of the pipeline decode the fetched instruction is decoded so that appropriate control sequences are activated for proper execution of the instruction The next two pipeline stages access and read are an operand read sequence If required by the instruction the data address of one or two oper ands are loaded in the access phase and the operand or operands are read in the following read phase Any write operation is spread over two stages of the pipeline the read and execute stages D
488. s the standard mode BSP initialization timing requirements for the transmitter The figure shows standard mode operation with external frame TXM 0 and clock MCM 0 active high frame sync FSP 0 and data sampled on rising edge CLKP 0 In this example if the BFSX pulse occurs during the first two BCLKXs after the transmit section is taken out of reset the transmit frame is ignored and BDX is placed in the high impedance state SPRU131G Buffered Serial Port BSP Interface Figure 9 28 Standard Mode BSP Initialization Timing BCLKX e rn ra o slis s ele BFSX BDX t _ _ _ 2CLKOUT 1 2 Serial Port clock cycles XRST SPRU131G In autobuffering mode for receive and transmit with external frame sync TXM 1 the BSP must be taken out of reset at least six CLKOUT cycles plus 1 2 serial port clock cycle prior to the edge of the clock which detects the active frame sync pulse whether the clock has been running previously or not for proper operation This is due to the time delay for the ABU logic to be activated See Figure 9 29 Transmit operations with internal clock and frame sync are not subject to this requirement since frame sync is internally generated automatically after XRST is cleared Note however that if external serial port clock is used with internal frame sync and if the clock is not running when XRST is cleared frame sync generation may be delayed depending on the tim
489. s used her Example 7 43 ARP Load With a 3 Cycle Latency in Compatibility Mode CMPT 1 POPM STO The ARP field of STO is updated here NOP NOP NOP LD ARO A The new ARP value is used here 7 5 7 3 Updating DP in Direct Addressing Mode CPL 0 A pipeline conflict can occur if two conditions are simultaneously met _j An instruction updates DP _ The next instruction uses DP as the base address for direct addressing in noncompiler mode CPL 0 The conflict occurs because the second instruction uses DP in apipeline stage that occurs before the previous instruction updates it Table 7 17 lists instructions that do not have any latency in writing to DP It is recommended that these instructions be used wherever possible to avoid conflicts Table 7 17 Recommended Instructions to Update DP in Noncompiler Mode CPL 0 To do this Use this instruction Load an immediate number to DP LD k DP Copy contents of a memory location to DP LD Smem DP Table 7 18 lists the latencies between instructions that update DP and subsequently use it _ enorrvwercereereeeewmwwrwreejrwrwreeererererevevveovwmnnawnwmwwj w vwwwvwemammannaanwwaaaawvwvnav vVwv vw wvveeer ws Note You are responsible for rearranging instructions or inserting NOPs if necessary to accommodate latencies eee eee eee ee SPRU131G Pipeline 7 63 Pipeline Latencies Table 7 18 Latencies for DP in
490. s when the data is sampled by the receiver and sent by the transmitter CMPT See compatibility mode code Asetof instructions written to perform a task a computer program or part of a program cold boot The process of loading a program into program memory at power up compare select and store unit CSSU An application specific hardware unit dedicated to add compare select operations of the Viterbi operator compatibility mode CMPT A bitin status register 1 ST1 that determines whether or not the auxiliary register pointer ARP is used to select an auxiliary register in single indirect addressing mode compiler mode CPL A bit in status register 1 ST1 that determines whether the CPU uses the data page pointer or the stack pointer to generate data memory addresses in direct addressing mode continuous mode A synchronous serial port mode in which only one frame synchronization pulse FSX and FSR is necessary to transmit several packets at maximum frequency CPL See compiler mode CSSU See compare select and store unit DAB D address bus A bus that carries addresses needed for accessing data memory DAB address register DAR A register that holds the address to be put on the DAB to address data memory for reads via the DB DAGEN See data address generation logic DAGEN SPRU131G SPRU131G Glossary DAR See DAB address register DARAM dual access RAM Memory that can be accessed twice in the
491. se of less expensive external crystals or oscillators The desired clock options are initially selected with the clock mode CLKMD pins Architectural Overview 2 13 On Chip Peripherals The clock options available vary depending on the C54x device however all C54x devices provide the divide by 2 clock capability On devices that provide a hardware PLL the desired multiplication factor is chosen by the state of CLKMD pins only For more details about the generator see section 8 5 Clock Generator on page 8 26 2 7 6 Direct Memory Access DMA Controller The direct memory access DMA controller transfers data between points in the memory map without intervention by the CPU The DMA allows move ments of data to and from internal program data memory on chip peripherals or external memory devices to occur in the background of CPU operation The DMA has six independent programmable channels allowing six different contexts for DMA operation 2 7 7 Host Port Interface The host port interface HPI is a parallel port that provides an interface to a host processor Information is exchanged between the C54x device and the host processor through C54x on chip memory that is accessible to both the host processor and the C54x device There are three basic options for an HPI on the C54x devices standard 8 bit HPI enhanced 8 bit HPI or enhanced 16 bit HPI Table 2 3 identifies the HPl equipped C54x devices See section 8 6 Host Port Interf
492. siderations for Using XDS510 Emulator SPRU131G Connections Between the Emulator and the Target System A 6 3 Configuring Multiple Processors Figure A 7 shows a typical daisy chained multiprocessor configuration that meets the minimum requirements of the IEEE 1149 1 specification The emulation signals are buffered to isolate the processors from the emulator and provide adequate signal drive for the target system One of the benefits of this interface is that you can slow down the test clock to eliminate timing problems Follow these guidelines for multiprocessor support _ The processor TMS TDI TDO and TCK signals must be buffered through the same physical device package for better control of timing skew _ The input buffers for TMS TDI and TCK should have pullup resistors connected to Vcc to hold these signals at a known value when the emula tor is not connected A resistor value of 4 7 KQ or greater is suggested J Buffering EMUO and EMU1 is optional but highly recommended to provide isolation These are not critical signals and do not have to be buffered through the same physical package as TMS TCK TDI and TDO Figure A 7 Multiprocessor Connections JTAG device JTAG device Emulator header EMUO PD EMU1 TRST TMS TDI TDO TCK TCK_RET SPRU131G Design Considerations for Using XDS510 Emulator A 13 Physical Dimensions for the 14
493. sides simply writing to DXR and reading from DRR On the SP the DXR and DRR may be read or written at any time regardless of whether the serial port is in reset or not On the BSP access to these regis ters is restricted the DRR can only be read and the DXR can only be written when autobuffering is disabled see section 9 3 2 Autobuffering Unit ABU Operation on page 9 40 The DRR can only be written when the BSP is in reset The DXR can be read at any time Note however that on both the SP and the BSP care should be exercised when reading or writing to these registers during normal operation With the DRR since as mentioned previously this register is written automatically by the serial port logic when data is received if a write to DRR is performed subsequent reads may not yield the result written if a serial port receive occurs after the write but before the read is performed With the DXR care should be exercised when this register is written since if previously written contents intended for transmission have not yet been sent these contents will be over written and the original data lost As mentioned previously the DXR can be read at any time Alternatively DXR and DRR may also serve as general purpose storage if they are not required for serial port use If these registers are to be used for general purpose storage the transmit and or receive sections of the serial port should be disabled either by tying off by pulling
494. simultaneously with CLKX CLKR starting Regardless of whether serial port clocks have been running previously however the timing of serial port initialization and most importantly when the port is taken out of reset can be critical for proper serial port operation The most significant consideration of this is when the port is taken out of reset with respect to when the first frame sync pulse occurs Initialization timing requirements differ on the serial port and the BSP On the serial port the serial port may be taken out of reset at any time with respect to FSX FSR however if XRST RRST go high during or after the frame sync the frame sync may be ignored In standard mode operation on the BSP for receive and for transmit with external frame sync TXM 0 the BSP must be taken out of reset at least two full CLKOUT cycles plus 1 2 serial port clock cycle prior to the edge of the clock which detects the active frame sync pulse whether the clock has been running previously or not for proper operation See Figure 9 28 Transmit operations with internal clock and frame sync are not subject to this requirement since frame sync is internally generated automatically after XRST is cleared set to 1 when BDXR is loaded Note however that if external serial port clock is used with internal frame sync frame sync generation may be delayed depending on the timing of clearing XRST with respect to the clock Figure 9 28 illustrate
495. smit register Serial port 0 control register Reserved Timer register Timer period register Timer control register Reserved Software wait state register Bank switching control register Reserved Serial port 1 data receive register Serial port 1 data transmit register Serial port 1 control register Reserved Clock mode register C541B only Reserved On Chip Peripherals 8 3 Peripheral Memory Mapped Registers Table 8 2 C542 Peripheral Memory Mapped Registers Address Hex Name Description 20 BDRRO Buffered serial port data receive register 21 BDXRO Buffered serial port data transmit register 22 BSPCO Buffered serial port control register 23 BSPCEO Buffered serial port control extension register 24 TIM Timer register 25 PRD Timer period register 26 TCR Timer control register 27 Reserved 28 SWWSR Software wait state register 29 BSCR Bank switching control register 2A 2B Reserved 2C HPIC Host port interface control register 2D 2F gt Reserved 30 TRCV TDM serial port data receive register 31 TDXR TDM serial port data transmit register 32 TSPC TDM serial port control register 33 TCSR TDM serial port channel select register 34 TRTA TDM serial port receive transmit register 35 TRAD TDM serial port receive address register 36 37 a Reserved 38 AXRO ABU transmit address register 39 BKXO ABU transmit buffer size register 3A ARRO ABU receive address register 3B BKRO ABU receive buffer size register 3C 5F Reserved
496. so that they are not executed the return address is stored to the stack and then execution continues at the beginning of the called function J Delayed The one 2 word instruction or two 1 word instructions following the callinstruction are executed This allows you to avoid flushing the pipe line which requires extra cycles Note The two words following a delayed instruction cannot be an instruction that causes a PC discontinuity a branch call return or software interrupt es Table 6 7 shows the unconditional call instructions in the C54x DSP and the number of cycles needed to execute these instructions both nondelayed and delayed Delayed instructions need two cycles fewer than the corresponding nondelayed instructions because they do not flush the pipeline Program Memory Addressing 6 9 Calls Table 6 7 Unconditional Call Instructions Number of Cycles Instruction Description Nondelayed Delayed CALLID Places the return address on the stack 4 2 and then loads the PC with the address specified by the instruction CALA D Places the return address on the stack 6 4 and then loads the PC with the address specified in the designated accumulator 6 4 2 Conditional Calls Conditional calls operate like unconditional calls but they execute only when one or multiple conditions are met The possible conditions are given in Table 6 13 on page 6 16 If all the conditions are met the PC is loaded with the sec
497. ssed in this chapter For detailed information about enhanced peripherals see TMS320C54x DSP Enhanced Peripherals Reference Guide SPRU302 All C54x devices have general purpose I O pins a timer a clock generator a software programmable wait state generator and a programmable bank switching module Different types of serial ports host port interfaces and clock generators are device specific peripherals The serial ports are discussed in Chapter 9 Serial Ports and the software programmable wait state generator and programmable bank switching module are discussed in Chapter 10 External Bus Operation Topic Page 8 1 Available On Chip Peripherals 0ceeeeeeeee eee eee B 2 8 2 Peripheral Memory Mapped Registers 0 0ceeeee eens b 2 8 3 General Purpose I O 5 2600 sccicccetec amin anem aaa a ma e aa 84 Timer a cate caater tan enn ne Copeman tu ecnimeteteor mneEee 8 21 8 5 Clock Generator 00 cece cece eee eee nena ene eneee 8 6 Host Port Interface cece eee eee eens 8 1 Available On Chip Peripherals Peripheral Memory Mapped Registers 8 1 Available On Chip Peripherals The following on chip peripherals are available on C54x devices g General purpose I O pins XF and BIO g Timer 41 Clock generator 1 Host port interface HPI 8 bit standard E 8 bit enhanced mM 16 bit enhanced Synchronous serial port Buffered serial port BSP Multichannel buffered serial
498. t Signal Function HAS Address latch Address strobe input Hosts with a multiplexed address and data bus HBIL HCNTLO HCNTL1 E n HDO HD7 enable ALE or Address strobe or unused tied high Address or control lines Address or control lines Address or control lines Data bus VO Z T 1 Input O Output Z High impedance 8 40 On Chip Peripherals connect HAS to their ALE pin or equivalent HBIL HCNTLO 1 and HR W are then latched on HAS falling edge When used HAS must precede the later of HCS HDS1 or HDS2 see TMS320C54x DSP data sheet for detailed HPI timing specifications Hosts with separate address and data bus can connect HAS to a logic 1 level In this case HBIL HCNTLO 1 and HR W are latched by the later of HDS1 HDS2 or HCS falling edge while HAS stays inactive high Byte identification input Identifies first or second byte of transfer but not most significant or least significant this is specified by the BOB bit in the HPIC register described later in this section HBIL is low for the first byte and high for the second byte Host control inputs Selects a host access to the HPIA register the HPI data latches with optional address increment or the HPIC register Chip select Serves as the enable input for the HPI and must be low during an access but may stay low between accesses HCS normally precedes HDS1 and HDS2 but this signal also samples HCNTLO 1 HR W and
499. t and Part Order Information B 5 Part Order Information B 2 2 Device Nomenclature Tl device nomenclature includes the device family name and a suffix Figure B 1 provides a legend for reading the complete device name for any TMS320 DSP family member Figure B 1 TMS320 DSP Device Nomenclature TMS 320 PREFIX _ TMX experimental device TMP prototype device TMS qualified device SMJ MIL STD 883C SM High Rel non 883C DEVICE FAMILY 320 TMS320 Family C 542 PGE L TECHNOLOGY C CMOS E CMOS EPROM F CMOS Flash EEPROM LC Low Voltage CMOS 3 3 V VC Low Voltage CMOS 3 V 2 5 V or 1 8 V core t DIP Dual In Line Package PGA Pin Grid Array CC Chip Carrier QFP Quad Flat Package TQFP Thin Quad Flat Package BGA Ball Grid Array B 6 Development Support and Part Order Information TEMPERATURE RANGE DEFAULT 0 C TO 70 C rP zZorLT O a O wu 0 C to 50 C 0 C to 70 C 55 C to 100 C 55 C to 125 C 40 C to 85 C PACKAGE TYPET N T N Hou uw wt tou wd wet DEVICE plastic DIP ceramic DIP ceramic DIP side brazed ceramic PGA ceramic CC plastic leaded CC ceramic leadless CC 100 pin plastic EIAJ QFP 100 pin plastic TQFP 128 pin plastic TQFP 132 pin plastic bumpered QFP 144 pin plastic TQFP 144 pin BGA 176 pin plastic TQFP 176 pin BGA 1x DSP 2x DSP 20x DSP 24x DSP 27x DSP 28x DSP 3x DSP 4x DSP 5x DSP 54x DSP 55x DSP 62x DS
500. t is only necessary that one bit in the field matches for a receive to occur The advantage of this scheme is that atransmitting device can select the device or devices to receive its transmitted data by simply changing its transmit address as long as each devices receive address is unique the receive address of the receiving device does not need to be changed In the example device 0 can transmit to any combination of the other devices by merely writing to the upper byte of TRTA Therefore if a transmitting device changed its TRTA to 8001h on the fly it would transmit only to device 7 A device may also transmit to itself because both the transmit and receive operations are executed on the rising edge of TCLK see the C54x DSP data sheet for TDM interface timings To enable this type of loopback it is necessary to use the standard TDM port interface connections as shown in Figure 9 31 Then if device 0 has a TRTA of 0101h it would transmit only to itself As an illustration of the proper operation of a TDM serial port Example 9 5 through Example 9 8 define a sequence of actions This illustration is based on the use of interrupts to handle the normal I O between the serial port and CPU The C542 peripheral configuration has been used as a reference for these examples In Example 9 5 the procedure for a one way transmit of a sequence of values from device 0 to device 1 is shown Device 0 transmits in slot 0 and has a transmit addres
501. t not break the first byte second byte HBIL low high sequence of an ongoing HPI access If this sequence is broken data can be lost and unpredictable operation can result The two control inputs HCNTLO and HCNTL1 indicate which internal HPI register is being accessed and the type of access to the register These inputs along with HBIL are commonly driven by host address bus bits or a function of these bits Using the HCNTLO 1 inputs the host can specify an access to the HPI control HPIC register the HPI address HPIA register which serves as the pointer into HPI memory or HPI data HPID register The HPID regis ter can also be accessed with an optional automatic address increment The autoincrement feature provides a convenient way of reading or writing to subsequent word locations In autoincrement mode a data read causes a postincrement of the HPIA and a data write causes a preincrement of the HPIA By writing to the HPIC the host can interrupt the C54x CPU and the HINT output can be used by the C54x CPU to interrupt the host The host can also acknowledge and clear HINT by writing to the HPIC 8 38 On Chip Peripherals SPRU131G Host Port Interface Table 8 20 summarizes the three registers that the HPI utilizes for commu nication between the host device and the C54x CPU and their functions Table 8 20 HPI Registers Description Name Address HPIA HPIC 002Ch HPID SPRU131G Description HPI address
502. t request received Interrupt maskable ty Interrupt acknowledged IACK generated Hardware interrupt or INTR instruction INTM set to 1 W PC saved on software stack fK W Interrupt service routine run J Return instruction restores PC W Main program continues Program Memory Addressing 6 37 SPRU131G Interrupts 6 10 10 Interrupt Tables Table 6 19 through Table 6 24 show the interrupt trap number priority and location for some C54x devices Table 6 19 TMS320C541 Interrupt Locations and Priorities 6 38 TRAP I NTR Number K Priority 0 oOo ON DO oa FW DYN moe ENI EDI Beas Bes Ba es HCP FOND FO oO DON DO A fF WO YH CO 1 2 oO AN DOO FW fk Oo 25 31 Name RS SINTR NMI SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INTO SINTO INT4 SINT1 INT2 SINT2 TINT SINT3 RINTO SINT4 XINTO SINT5 RINT1 SINT6 XINT1 SINT7 INT3 SINT8 Program Memory Addressing Location Hex 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 7F Function Reset hardware and software reset Nonmaskable interrupt Software interrupt 17 Software interrupt 18 Software interrupt 19 Software interrupt 20 Software interrupt 21 Software interrupt 22 Software interrupt 23 Software interrupt 24 Softwa
503. t reversed address See the 7MS320C54x DSP Reference Set Volume 4 Applications Guide for an application of the bit reversed addressing mode 5 18 Data Addressing SPRU131G Indirect Addressing Table 5 5 Bit Reversed Addresses Step Bit Pattern Bii Reversed Pattern Bit Reversed Step 0 0000 0000 0 1 0001 1000 8 2 0010 0100 4 3 0011 1100 12 4 0100 0010 2 5 0101 1010 10 6 0110 0110 6 7 0111 1110 14 8 1000 0001 1 9 1001 1001 9 10 1010 0101 5 11 1011 1101 13 12 1100 0011 3 13 1101 1011 11 14 1110 0111 7 15 1111 1111 15 5 5 4 Dual Operand Address Modifications SPRU131G Dual data memory operand addressing is used for instructions that perform two reads or a single read and a parallel store indicated by two vertical bars at the same time These instructions are all one word long and operate in indirect addressing mode only Two data memory operands are represented by Xmem and Ymem _ Xmem is a read operand with access through the D bus Store instruc tions for example STH and STL with shift operation change Xmem to a write operand Ymemis used as a readoperand in instructions with dual reads accessed through the C bus or as a write operand in instructions with a parallel store accessed through the E bus If the source operand and the destination operand point to the same location in instructions with a parallel store for example ST LD the source is read before writing to the destination If a
504. ta The TRCV has the same function as the DRR described on page 9 5 TDM data transmit register TDXR The 16 bit TDM data transmit register TDXR holds the outgoing TDM serial data The TDXR has the same function as the DXR described on page 9 5 TDM serial port control register TSPC The 16 bit TDM serial port control register TSPC contains the mode control and status bits of the TDM serial port interface The TSPC is identical to the SPC Figure 9 3 except that bit O serves as the TDM mode enable control bit in the TSPC The TDM bit configures the port in TDM mode TDM 1 or stand alone mode TDM 0 In stand alone mode the port operates as a standard serial port as described on page 9 4 TDM channel select register TCSR The 16 bit TDM channel select register TCSR specifies in which time slot s each C54x device is to transmit TDM receive transmit address register TRTA The 16 bit TDM receive transmit address register TRTA specifies in the eight LSBs RAO RA7 the receive address of the C54x device and in the eight MSBs TAO TA7 the transmit address of the C54x device TDM receive address register TRAD The 16 bit TDM receive address register TRAD contains various information regarding the status of the TDM address line TADD Serial Ports 9 57 Time Division Multiplexed TDM Serial Port Interface 3 TDM data receive shift register TRSR The 16 bit TDM data receive shift register TRSR controls t
505. tch Program address bus PAB is loaded with the address of the next instruction to be fetched i Program fetch An instruction word is fetched from the program bus PB and loaded into the instruction register IR This completes an instruction fetch sequence that consists of this and the previous cycle 1 Decode The contents of the instruction register IR are decoded to deter mine the type of memory access operation and the control sequence at the data address generation unit DAGEN and the CPU 1 Access DAGEN outputs the read operand s address on the data address bus DAB If a second operand is required the other data address bus CAB is also loaded with an appropriate address Auxiliary registers in indirect addressing mode and the stack pointer SP are also updated This is considered the first of the 2 stage operand read sequence J Read The read data operand s if any are read from the data buses DB and CB This completes the two stage operand read sequence At the same time the two stage operand write sequence begins The data address of the write operand if any is loaded into the data write address bus EAB For memory mapped registers the read data operand is read from memory and written into the selected memory mapped registers using the DB J Execute The operand write sequence is completed by writing the data using the data write bus EB The instruction is executed in this phase Figure 7 1 show
506. tching 10 30 External Bus Operation SPRU131G Figure 10 24 HOLD and RS Interaction a Hold is Asserted While Reset is Active and De asserted While Reset is Active Hold Mode error ADA AND DAD VVV VUV VV VVV VVV VVV e T MN ye oe horo j HOLDA w Address b Hold is Asserted While Reset is Active and De asserted While Reset is Inactive oios VVAV VVV VIVAI V VV VVV VVV HOLD LELLI moma o NA aaa a I a Address Data a a a a a a a a a a aaea a C a a N E O O a E a Pspsis a a a a a a aa maa aa op C S RAST i IAQ or TACK MP MC v SPRU131G FF80h PI a a a a A a a E E E PS DS IS D A A a a m TAQ or am a a a a a a a N A A IACK FF80h ee ee ce FF80h Bank switching FF80h Bank switching External Bus Operation 10 31 Hold Mode Figure 10 24 HOLD and RS Interaction Continued c Hold is Asserted and De asserted While Reset is Inactive CLKOUT AVA WA AW AW AWA V A DAW VIVIAN NI NINININI NINININI NIN rs T TT TT TT TTT INQ YT Ty or Plc nT TTT HOLD ye TP ee do FF80h Dal st OO ed Se Poss 1 C MSTRB YN Bank switching 4 Address IAQ or IACK MP MC 0 d Hold is Asserted While Reset is Inactive and De asserted While Reset is Active AVAVA VA TATATATA TATATATA INS NSN NI NI
507. tegrate and debug soft ware and hardware modules Code Generation Tools I The optimizing ANSI C compiler translates ANSI C language directly into highly optimized assembly code You can then assemble and link this code with the Tl assembler linker which is shipped with the compiler This product is currently available for PCs DOS DOS extended memory OS 2 HP workstations and SPARC workstations See the TMS320C54x Optimizing C Compiler User s Guide for detailed information about this tool J The assembler linker converts source mnemonics to executable object code This product is currently available for PCs DOS DOS extended memory OS 2 The C54x DSP assembler for HP and SPARC workstations is available only as part of the optimizing C54x DSP compiler See the TMS320C54x Assembly Language Tools User s Guide for detailed information about available assembly language tools System Integration and Debug Tools 1 The simulator simulates via software the operation of the C54x DSP and can be used in C and assembly software development This product is currently available for PCs DOS Windows HP workstations and SPARC workstations See the 7MS320C54x C Source Debugger User s Guide for detailed information about the debugger I The XDS510 emulator performs full speed in circuit emulation with the C54x DSP providing access to all registers as well as to internal and exter nal memory of the device It can be used in C and assem
508. tency ss itcantehar deeb ingae ts ole ie cali LARIE Saeed 6 10 8 Interrupt Operation A Quick Summary 066 0 ccc eee eens 6 10 9 Re mapping Interrupt Vector Addresses 2 00 cece eee eee 6 10 10 Interrupt Tables 2 222 c020 sacs tarde ante ohes dees ne pee ENAERE 6 1 Power Down Modos a2 c0nd sckousangadaageiensareime edna ee ERNER AENEA 61 DEE MOJE 2 2 04 00005 02 a ieia eee k oie ar a ote dee ea ee E a a ees 6 1122 IDLER Mde ais ioe csedn Risa anand weal ide Peon Dae a ee Dd Aes dee A 611 3 IDEES MOE a scx ceed de eetnaced heed aE EE E ad a E EE GATA Hold Mod er ttetecret oid tt penain cide a de te Sas ee nae 6 11 5 Other Power Down Capabilities 0 00 eee eee T Pipelin ice ccecew tone ereca ee eae tinal wee Oden Saeed teas PERER teed Pemex Describes the TMS320C54x DSP pipeline operation and lists the pipeline latency cycles for these types of latencies 7 1 Pipeline Operation 00 t NURE EENE 7 1 1 Branch Instructions in the Pipeline 0 0 c cece ee eee 7 1 2 Call Instructions in the Pipeline 0000s 7 1 3 Return Instructions in the Pipeline 0 0 c cece eee eee 7 1 4 Conditional Execute Instructions in the Pipeline 4 7 1 5 Conditional Call and Conditional Branch Instructions in the Pipeline 7 2 Interrupts and the Pipeline 0 2 0 cece eet ees 7 3 Dual Access Memory and the Pipeline 0 cece eee ee 7 3
509. tension register XPC A register that contains the upper 7 bits of the current program memory address program data bus PB Abus that carries the instruction code and immedi ate operands from program memory program memory A memory region used for storing and executing programs pulse coded modulation mode PCM A bit in the BSP control extension register BSPCE that enables disables the BSP transmitter push Action of placing a word onto a stack RAM overlay OVLY A bit in the processor mode status register PMST that determines whether or not on chip RAM is mapped into the program space in addition to data space RC See repeat counter REA See block repeat end address receive buffer half received RH Abit in the BSP control extension regis ter BSPCE that indicates which half of the receive buffer has been received receive ready RRDY A bit in the serial port control register SPC buffered serial port control register BSPC and TDM serial port control register TSPC that transitions from 0 to 1 to indicate the data receive shift register RSR contents have been copied to the data receive regis ter DRR and that data can be read receiver reset RRST A bit in the serial port control register SPC buffered serial port control register BSPC and TDM serial port control register TSPC that resets the serial port receiver receive shift register full RSRFULL A bitin the serial port control registe
510. ter Timer0 control register Reserved Software wait state register Bank switching control register Reserved Software wait state control register HPI control register Reserved Timer1 register Timer period register Timer1 control register Reserved McBSPO serial port sub bank address register See Table 8 11 on page 8 17 McBSPO serial port sub bank data register See Table 8 11 on page 8 17 Reserved General purpose I O pins control register General purpose I O pins status register On Chip Peripherals 8 11 Peripheral Memory Mapped Registers Table 8 8 C5402 Peripheral Memory Mapped Registers Continued Address Hex 3E 3F 40 41 42 43 44 47 48 49 4A 53 54 55 56 57 58 59 5F 8 12 On Chip Peripherals Name DRR21 DRR11 DXR21 DXR11 SPSA1 SPSD1 DMPREG DMSA DMSDI DMSDN CLKMD Description Reserved McBSP1 data receive register 2 McBSP1 data receive register 1 McBSP1 data transmit register 2 McBSP1 data transmit register 1 Reserved McBSP 1 serial port sub bank address register See Table 8 11 on page 8 17 McBSP1 serial port sub bank data register See Table 8 11 on page 8 17 Reserved DMA channel priority and enable control register DMA sub bank address register See Table 8 12 on page 8 18 DMA sub bank data register with sub bank address auto increment See Table 8 12 on page 8 18 DMA sub bank data register See Tabl
511. terrupts Table 6 28 TMS320C5420 Interrupt Locations and Priorities Continued TRAP INTR Number K 19 20 21 22 23 24 25 26 27 28 29 30 124 127 SPRU131G Priority Name 6 Oo oOo N 14 15 16 17 TINT SINT3 BRINTO SINT4 BXINTO SINT5 BRINT2 DMACO BXINT2 DMAC1 INT3 SINT8 HPINT SINT9 BRINT1 DMAC2 BXINT1 DMAC3 DMAC4 SINT12 DMAC5 SINT13 IPINT SINT14 Location Hex 4C 50 54 58 5C 60 64 68 6C 70 74 78 7C 7F Function External timer McBSP 0 receive interrupt default McBSP 0 transmit interrupt default McBSP 2 receive interrupt default or DMA channel 0 interrupt MCBSP 2 transmit interrupt default or DMA channel 1 interrupt Reserved HPI interrupt from DSPINT in HPIC McBSP 1 receive interrupt default or DMA channel 2 interrupt McBSP 1 transmit interrupt default or DMA channel 3 interrupt DMA channel 4 interrupt DMA channel 5 interrupt Interprocessor interrupt Reserved Program Memory Addressing 6 49 Power Down Modes 6 11 Power Down Modes The C54x DSP has power down modes in which it enters a dormant state and dissipates less power than normal operation while maintaining the CPU contents This allows operations to continue unaltered when the power down mode is terminated You can invoke one of the power down modes either by executing the IDLE 1 IDLE 2 or IDLE 3 instructions or by driving the HOLD signal low with
512. that when you use the stack to save the context you must perform the restore in the exact reverse order The second consideration is that BRC should be restored prior to restor ing the BRAF bit in ST1 If you fail to follow this order the BRAF bit will be cleared if BRC 0 before BRC is restored 6 10 7 Interrupt Latency The C54x DSP completes all instructions in the pipeline except the instructions in the prefetch and fetch stages before executing an interrupt so the maximum interrupt latency depends on the contents of the pipeline See section 7 2 Interrupts and the Pipeline on page 7 25 for more information about pipeline latencies associated with interrupts Instructions that are extended by wait states for slower memory access and repeated instructions require extra time to process an interrupt The single repeat instructions RPT and RPTZ require that all executions of the next instruction be completed before allowing an interrupt to execute to protect the context of the repeated instructions This protection is necessary because these instructions run parallel operations in the pipeline and the context of these operations cannot be saved in the ISR Since the hold function takes precedence over interrupts it can also delay an interrupt trap If an interrupt occurs when the CPU is on hold HOLD is asserted and the interrupt vector must be fetched from external memory the interrupt is not taken until HOLDA is de asserted after t
513. the DXR is transmitted This is explained in detail in section 9 2 6 Serial Port Interface Exception Conditions on page 9 26 Note that the first data bit transferred could have variable length if frame sync is generated externally and does not fall within one CLKX cycle this is illus trated in Figure 9 6 Internally generated frame syncs are assured by C54x DSP timings to be one CLKX cycle in duration Figure 9 6 Serial Port Transmit With Long FSX Pulse SPRU131G Serial Ports 9 19 Serial Port Interface Serial port transmit with external frame sync pulses is similar to that with inter nal frame sync with the exception that transfers do not actually begin until the external frame sync occurs If the external frame sync occurs many CLKX cycles after DXR is loaded however the double buffer is filled and frozen until frame sync appears On the SP Figure 9 7 when the delayed frame sync occurs Ais transmitted on DX after the transmit a DXR to XSR copy of B occurs XINT is generated and again the transmitter remains frozen until the next frame sync When frame sync finally occurs B is transmitted on DX Note that when B is loaded into DXR a DXR to XSR copy of B does not occur immediately because A has not been transmitted and no XINT is generated Any subsequent writes to DXR before the next delayed frame sync occurs overwrite B in the DXR Figure 9 7 Burst Mode Serial Port Transmit Operation
514. the HM status bit set to 1 Power down operation is summarized in Table 6 29 and described in detail in sections 6 11 1 through 6 11 5 Table 6 29 Operation During the Four Power Down Modes Operation Feature IDLA CED IDE HoD CPU halted Yes Yes Yes Yest CPU clock stopped Yes Yes Yes No Peripheral clock stopped No Yes Yes No Phase locked loop PLL stopped No No Yes No External address lines put in high impedance state No No No Yes External data lines put in high impedance state No No No Yes External control signals put in high impedance state No No No Yes Power down terminated by HOLD driven high No No No Yes Unmasked internal hardware interrupts Yes No No No Unmasked external hardware interrupts Yes Yes Yes No NMI Yes Yes Yes No RS Yes Yes Yes No t Depending on the state of the HM bit the CPU continues to execute unless the execution requires an external memory access 6 11 1 IDLE1 Mode The IDLE1 mode halts all CPU activities except the system clock Because the system clock remains applied to the peripheral modules the peripheral circuits continue operating and the CLKOUT pin remains active Thus peripherals such as serial ports and timers can take the CPU out of its power down state Use the IDLE 1 instruction to enter the IDLE1 mode To terminate IDLE1 use a wake up interrupt If INTM 0 when the wake up interrupt takes place the 6 50 Program Memory Addressing SPRU131G 6 11 2 IDLE2 Mode 6 11 3 IDLE
515. the RETE and RETF instructions ensures that the return executes before another interrupt is processed By using the RETF instruction loading the PC from the RTN register rather than the stack allows a quicker return This reduces the total number of cycles used by an interrupt routine which is particularly important for short frequently used interrupt routines 7 Note The RTN register is a CPU internal register that you cannot read from or write to ee 6 5 2 Conditional Returns SPRU131G By using the conditional return RC instruction you can give a function or interrupt service routine ISR more than one possible return path The path chosen depends on the data being processed In addition you can use a conditional return to avoid conditionally branching to around the return instruc tion at the end of the function or ISR Conditional returns operate like unconditional returns but they execute only when one or more conditions are met The possible conditions are given in Table 6 13 on page 6 16 If all the conditions are met the processor loads the return address from the stack to PC and resumes execution of the calling program The conditional return is a single word instruction however because of the potential PC discontinuity it operates with the same effective execution time as the conditional branch or call Program Memory Addressing 6 13 Returns Table 6 117 6 5 3 Far Returns 6 14 By the time t
516. the circular buffer and the index into the circular buffer Figure 5 10 shows how the circular buffer is implemented and illustrates the relationship between the generated values and the elements in the circular buffer 5 16 Data Addressing SPRU131G Indirect Addressing Figure 5 9 Circular Addressing Block Diagram First 1 at location N 1 15 N N 1 0 EOB 1 Circular addressing algorithm logic Base low address Legend EFB Effective base address H High order bits L Low order bits L New low order bits BL Low order bit of circular buffer size register Figure 5 10 Circular Buffer Implementation Address Data 15 N N i 0 Top of circular buffer Effective Element 1 15 N N 1 0 Last element LSBs BK gt Last element 1 SPRU131G Data Addressing 5 17 Indirect Addressing Circular addressing typically uses a decrement or an increment by one MOD 8 and 10 or a decrement or an increment by an index MOD 9 and 11 Premodification by a 16 bit word offset ARx Ik requires an extra code word so that the instruction code has two or three words The last word is the offset An instruction using indirect offset addressing cannot be repeated using a single repeat operation The syntaxes for each of the five types of circular addressing are shown in Table 5 4 for MOD 8 9 10 11 and 14 5 5 3 5 Bit Reversed Address Modifications MOD 4 or
517. the optimal path which results in decoding the code 4 26 Central Processing Unit SPRU131G Exponent Encoder 4 7 Exponent Encoder The exponent encoder is an application specific hardware device dedicated to supporting the EXP instruction in a single cycle see Figure 4 11 With the EXP instruction the exponent value in the accumulator can be stored in T as a 2s complement value within a 8 through 31 range The exponent is defined as the number of leading redundant bits 8 which corresponds to the number of shifts required in the accumulator to eliminate nonsignificant sign bits This operation results in a negative value when the accumulator value exceeds 32 bits Figure 4 11 Exponent Encoder From accumulator A From accumulator B EXP encoder To T register The EXP and NORM instructions use the exponent encoder to normalize the accumulator s contents efficiently NORM supports shifting the accumulator value by the number of bits specified in T in a single cycle A negative value in T produces a right shift of the accumulator s contents which normalizes any value beyond the 32 bit range of the accumulator Example 4 5 demonstrates the normalization of accumulator A Example 4 5 Normalization of Accumulator A SPRU131G Normalize accumulator A EXP A the number of leading bits 8 gt T ST T EXPONENT Store the exponent T into data memory NORM A Normalize accumulator
518. the serial port section occur under software control in the same fashion as with the standard C54x DSP serial port In this mode the ABU is transparent and the WXINT and WRINT interrupts generated each time a word is transmitted or received are sent to the CPU as transmit interrupt BXINT and receive interrupt BRINT When autobuffering is enabled the BXINT and BRINT interrupts are only generated to the CPU each time half of the buffer is transferred Serial Ports 9 33 Buffered Serial Port BSP Interface Figure 9 21 BSP Block Diagram 9 34 DATA BUS BCLKX BFSX Serial Ports C54x memory interface C54x CPU interface Autobuffering unit module Control XRDY RRDY BXINT BMINT BRINT Interrupt Serial port logic control logic Interrupt control WRINT Serial port interface module As mentioned previously most aspects of BSP operation are similar to that of the C54x DSP standard serial port section 9 2 Serial Port Interface on page 9 4 discusses operation of both the C54x DSP standard serial port and the BSP in standard mode Since standard mode BSP operation is a superset of standard serial port operation section 9 2 Serial Port Interface should first be studied before the rest of this section is read System considerations of BSP operation such as initialization and low power modes are discussed in section 9 3 3 on page 9 49 SPRU131G Buffered Serial Port BSP Interface 9 3 1 BSP Op
519. ticular C54x device and shows the addresses of each of the items The address range for the code F800h FFFFh is mapped to the on chip ROM if the MP MC bit is 0 Note You can submit code to Texas Instruments in object file format to program into the on chip ROM See Appendix C Submitting ROM Codes to TI for details on how to submit ROM code to Texas Instruments SPRU131G Program Memory Figure 3 15 On Chip ROM Program Memory Map High Addresses C541 545 546 C542 543 548 549 5402 5410 F800h User specified code Bootloader code F900h FAOOh FBOOh FCOOh u law expansion table FDOOh A law expansion table FEOOh Sine look up table FFOOh Reserved Reserved FF80h Interrupt vector table Interrupt vector table SPRU131G Memory 3 19 Program Memory 3 2 5 Extended Program Memory Available on C548 549 5402 541 0 5420 The C548 C549 C5402 C5410 and C5420 use a paged extended memory scheme in program memory space to allow access of up to 8192K words of program memory To implement this scheme the C548 C549 C5402 C5410 and C5420 include several additional features 23 address lines instead of 16 20 address lines in the C5402 and 18 in the C5420 J An extra memory mapped register the program counter extension register XPC Lj Six extra instructions for addressing extended program space The value of XPC defines the page This register is memory mapped into data space to address 0
520. ting to TDXR in those slots Slot manipulation is explained later in this section The 1 kilohm resistor is not required on the TDAT line An empty TDM slot can result in the following cases the first obvious case as mentioned above occurs when no device has its TCSR configured to transmit in that slot A second more subtle case occurs when TDXR has not been loaded before a transmit slot in a particular frame This may also happen when the TCSR contents are changed since the actual TCSR contents are not updated until the next TFRM pulse occurs Therefore any subsequent change takes effect only in the next frame The same is true for the receive address the lower half of TRTA The transmit address upper half of TRTA however and TDXR clearly may be changed within the current frame for a particular slot assuming that the slot has not yet been reached when the instruction to load the TRTA or TDXR is executed Note that it is not necessary to load the transmit address each time TDXR is loaded when a TDXR load occurs and a transmission begins the current transmit address in TRTA is transmitted on TADD The current slot number may be obtained by reading the X2 X0 bits in TRAD This affords the flexibility of reconfiguring the TDM port on a slot by slot basis and even slot sharing if desired The key to utilizing this capability is to understand the timing relationship between the instructions being executed and the frame slots of the TDM po
521. tion handling multicycle instructions _ 6 20 non repeatable instructions 6 21 reset clock modes definition RS interrupt Index sequence of events setting status bits reset sequence resolved conflict instruction fetch and operand read 7 29 operand write and dual operand read operand write operand write and dual operand read return in the pipeline 7 12 returns anton 6 13 far 6 14 unconditional RH definition RINT definition ROM RPT instruction long immediate addressing 5 3 short immediate addressing RPTB instruction RPTBD instruction RRDY 9 10 definition RRST definition RSA RSR definition RSRFULL 9 9 definition RTCs RTN definition run stop operation RUNB _ debugger command RUNB_ENABLE input A 22 SAM shared access mode sample pipeline diagram figure saturation on multiplication SMUL definition example saturation on store SST 4 8 definition example Index 15 Index scan path linkers A 16 secondary JTAG scan chain to an SPL A 17 suggested timings usage scan paths TBC emulation connections for JTAG scan paths scanning logic IEEE standard 2 17 security options on chip ROM ROM RAM seminars B 4 serial I O ports 2 15 serial port control register SPC 9 5 bit summary 9 9 definition diagram DLB bit 9 121 FO bit D 9 Free bit 9 91 9 17 FSM bit 9 13 D 9 INO bit ea eae PE IN1
522. tion bootloader considerations when using BRAF definition BRAF deactivation example branch control input BIO pin branch instructions pipeline branch instructions in the pipeline figure branches conditional far unconditional BRC See also block repeat counter definition D 2 BRINT definition BRSR definition BSCR definition BSP control extension register BSPCE bit summar BRE bit 9 44 D 2 Index 3 Index BXE bit CLKDV bits CLKP bit 9 38 definition diagram FE bit 9 38 D 9 FIG bit 9 38 D 9 FSP bit 9 38 HALTR bit HALTX bit PCM bit RH bit XH bit BSP data receive register BDRR definition D 3 BSP data receive shift register BRSR definition BSP data transmit register BDXR definition BSP data transmit shift register BXSR definition BSP operation system considerations 9 49 BSP receive interrupt BRINT definition BSP transmit interrupt BXINT definition BSPC definition BSPCE definition buffered serial port BSP 2 15 9 33 autobuffering control register autobuffering process 9 40 autobuffering unit ABU buffer misalignment interrupt BMINT 9 54 D 5 definition enhanced features 9 37 power down mode _ 9 55 registers system considerations buffered serial port control register BSPC definition DLB bit FO bit D 9 Free bit D 9 FSM bit INO bit IN1 bit MCM bit D 6 RRDY bit RRST bit RSRFULL bit Soft bit
523. tion more than IDLE2 Furthermore the IDLE3 state allows you to reconfigure the PLL externally if the system requires the C54x DSP to operate at a lower speed to save power Use the IDLE 3 instruction to enter the IDLE3 mode To terminate IDLES activate any of the external interrupt pins RS NMI and INTx with a 10 ns minimum pulse If INTM 0 when the wake up interrupt takes place the C54x DSP enters the ISR when IDLE3 is terminated If INTM 1 the C54x DSP continues with the instruction following the IDLE 3 instruction All wake up interrupts should be set to enable the corresponding bits on the IMR register regardless of the INTM value Reset all peripherals when IDLE3 terminates especially if they are externally clocked To terminate IDLE3 the external interrupt must be a minimum of 10 ns to activate the wake up sequence The C54x DSP can accept multiple interrupts during the wake up sequence the interrupt with highest priority is serviced first after IDLE3 See section 10 5 2 IDLE3 on page 10 26 and section 8 5 2 Software Programmable PLL Available on TMS320C545 546 548 on page 8 27 for more details on PLL lockup time requirements Program Memory Addressing 6 51 Power Down Modes When RS is the wake up interrupt in IDLE3 a 10 ns minimum pulse of RS can activate the reset sequence However RS should be kept active for 50 us so that the PLL can secure and provide stable system clock to internal logic 6 11 4 Hold Mod
524. tion set Read This First SPRU131G SPRU131G Related Documentation from Texas Instruments TMS320C54x DSKplus User s Guide literature number SPRU191 describes the TMS320C54x digital signal processor starter kit DSK which allows you to execute custom TMS320C54x DSP code in real time and debug it line by line Covered are installation procedures a description of the debugger and the assembler customized applications and initialization routines TMS320C54x Code Composer Studio Tutorial literature number SPRU327 introduces the Code Composer Studio integrated develop ment environment and software tools for the TMS320C54x Code Composer User s Guide literature number SPRU328 explains how to use the Code Composer development environment to build and debug embedded real time DSP applications TMS320C54x Assembly Language Tools User s Guide literature number SPRU102 describes the assembly language tools assembler linker and other tools used to develop assembly language code assembler directives macros common object file format and symbolic debugging directives for the TMS320C54x generation of devices TMS320C54x Optimizing C Compiler User s Guide literature number SPRU103 describes the TMS320C54x C compiler This C compiler accepts ANSI standard C source code and produces assembly language source code for the TMS320C54x generation of devices TMS320C54x Simulator Getting Started literature number SPRU1
525. tipliert 0 X 0 14 0 5 0 x 15 0 25 1 0 0 14 PLLMUL 1 1 0 15 1 bypass 1 1 0 or even PLLMUL 1 2 1 1 odd PLLMUL 4 tT CLKOUT CLKIN x Multiplier This is the default mode for the C5420 after reset Programming Considerations When Using the Software Programmable PLL The software programmable PLL offers many different options in startup configurations operating modes and power saving features Programming considerations and several software examples are presented here to illustrate the proper use of the software programmable PLL at start up when switching between different clocking modes and before and after IDLE 1 IDLE 2 IDLE 3 instruction execution 8 30 On Chip Peripherals SPRU131G Clock Generator Using the PLLCOUNT Programmable Lock Timer During the lockup period the PLL should not be used to clock the C54x DSP The PLLCOUNT programmable lock timer provides a convenient method of automatically delaying clocking of the device by the PLL until lock is achieved The PLL lock timer is a counter loaded from the PLLCOUNT field in the CLKMD register that decrements from its preset value to 0 The timer can be preset to any value from 0 to 255 and its input clock is CLKIN divided by 16 The resulting lockup delay can therefore be set from 0 to 255 x 16 CLKIN cycles The lock timer is activated when the clock generator operating mode is switched from DIV to PLL see section Switching From DIV Mode to PLL Mode on page 8
526. tive for at least two CLKOUT cycles How ever power up and IDLE3 power down mode require the reset signal to be active for more than two CLKOUT cycles See section 6 11 Power Down Modes on page 6 50 for more detailed information When the C54x CPU acknowledges a reset the CPU terminates program execution and forces the program counter to FF80h The address bus is driven with FF80h while RS is low The device enters its reset state in reference to the external bus according to three steps 1 Fourcycles after RS is asserted low PS MSTRB and IAQ are driven high 2 Five cycles after RS is asserted low R W is driven high the data bus if driven goes into the high impedance state and the address bus is driven with OOFF80h 3 The device enters its reset state When reset becomes inactive program execution starts from the program memory location FF80h The instruction acquisition signal IAQ and the inter rupt acknowledge signal IACK become active as shown in Figure 10 21 regardless of the state of the MP MC signal 10 24 External Bus Operation SPRU131G Start Up Access Sequences The device enters its active state in reference to the external bus according to three steps 1 Five cycles after RS is asserted high PS is driven low 2 Six cycles after RS is asserted high MSTRB and IACK are driven low 3 One half cycle later the device is ready to read data and the device moves into its active state
527. tor Drives Control Engineering February 1988 8 Matsui N and M Shigyo Brushless DC Motor Control Without Position and Speed Sensors IEEE Transactions on Industry Applications USA Volume 28 Number 1 Part 1 pages 120 127 January February 1992 9 Hanselman H LQG Control of a Highly Resonant Disc Drive Head Posi tioning Actuator IEEE Transactions on Industrial Electronics USA Vol ume 35 Number 1 pages 100 104 February 1988 10 Bose B K and P M Szczesny A Microcomputer Based Control and Simulation of an Advanced IPM Synchronous Machine Drive System for Electric Vehicle Propulsion Proceedings of IECON 87 Volume 1 pages 454 463 November 1987 11 Ahmed I and S Lindquist Digital Signal Processors Simplifying High Performance Control Machine Design September 1987 Multimedia 1 Reimer J DSP Based Multimedia Solutions Lead Way Enhancing Audio Compression Performance Dr Dobbs Journal December 1993 2 Reimer J G Benbassat and W Bonneau Jr Application Processors Making PC Multimedia Happen Silicon Valley PC Design Conference July 1991 Military 1 Papamichalis P and J Reimer Implementation of the Data Encryption Standard Using the TMS32010 Digital Signal Processing Applications 1986 Telecommunications 1 Ahmed l and A Lovrich Adaptive Line Enhancer Using the TMS320C25 Conference Records of Northcon 86 USA
528. transferred in 16 bit format This feature is used with continuous receptions and continuous transmits with external frame sync When FIG 0 if a frame sync pulse occurs after the initial one the transfer is restarted when FIG 1 this frame sync is ignored Setting FIG to 1 allows for example effec tively achieving continuous 16 bit transfers under circumstances where frame sync pulses occur every 8 10 or 12 bits Without using FIG each transfer of less than 16 bits requires an entire 16 bit memory word and each 16 bits transferred as two 8 bit bytes requires two memory words and two transfer operations rather than one of each Using FIG therefore can result in a signif icant improvement in buffer size requirement in both autobuffered and standard mode and a significant improvement in CPU cycle overhead required to handle serial port transfers in standard mode Figure 9 23 shows an example with the BSP configured in 16 bit format but with a frame sync after 8 bits SPRU131G Serial Ports 9 39 Buffered Serial Port BSP Interface Figure 9 23 Transmit Continuous Mode with External Frame and FIG 1 Format Is 16 Bits CLKR Frame ignored FSX FSR f a DX DR msBXY KX KX X A X HX RRDY XRDY y t DXR reloaded 9 3 2 Autobuffering Unit ABU Operation Since ABU functionality is a superset of standard mode serial port operation the following sections should be read p
529. tual base address of the ABU memory may not be the same in all cases The memory map for the particular device being used should be consulted for the actual base address of its ABU memory When the ABU is enabled this 2K word block of memory can still be accessed by the CPU within data and or program spaces Conflicts may therefore occur between the CPU and the ABU if the 2K word block is accessed at the same time by both If a conflict does occur priority is given to the ABU resulting in the CPU access being delayed by one cycle Accordingly the worst case situa tion is that a CPU access could be delayed one cycle each time the ABU accesses the memory block that is for every new word transmitted or received Note that when on chip program memory is secured using the ROM protection feature the 2K word block of ABU memory cannot be mapped to program memory For further information regarding the ROM protection feature see section 3 5 Program and Data Security on page 3 30 When the ABU is enabled for both transmit and receive if transmit and receive requests from the serial port interface occur at same time the transmit request takes priority over the receive request In this case the transmit memory access occurs first delaying the receive memory access by generating a wait state When the transmit memory access is completed the receive memory access takes place 9 3 2 1 Autobuffering Control Register The most significant six bits i
530. ubmitting ROM Codes to TI 2 2 2 On Chip Dual Access RAM DARAM The amount of on chip DARAM available on each device varies The DARAM is composed of several blocks Because each DARAM block can be accessed twice per machine cycle the CPU and peripherals such as a buffered serial port BSP and host port interface HPI can read from and write toa DARAM memory address in the same cycle The DARAM is always mapped in data space and is primarily intended to store data values It can also be mapped into program space and used to store program code 2 2 3 On Chip Single Access RAM SARAM The amount of on chip SARAM available on each device varies The SARAM is composed of several blocks Each block is accessible once per machine cycle for either a read or a write The SARAM is always mapped in data space and is primarily intended to store data values It can also be mapped into pro gram space and used to store program code 2 2 4 On Chip Two Way Shared RAM The amount of on chip two way shared RAM available on certain devices varies The devices with multiple CPU cores include two way shared RAM blocks that allow simultaneous program space access from two CPU cores Each CPU can perform a single access with zero states to any location in the two way shared RAM during each clock cycle All the shared memory is pro gram write protected or read only by the CPU only the DMA controller can write to the shared memory This shared RAM is most
531. uction an operand a multicycle instruction or a pipeline flush The numbers across the top repre sent single instruction cycles Some cycles do not show all pipeline stages this is done intentionally to avoid displaying unnecessary information Each box in the example contains relevant actions that occur at that pipeline stage The name of each pipeline stage is shown above the box in which the action occurs Shading represents all instruction fetches and pipeline flushes that are neces sary to complete the instruction whose operation is shown SPRU131G Pipeline 7 5 Pipeline Operation 7 1 1 Branch Instructions in the Pipeline Example 7 2 and Example 7 3 show the pipeline s behavior during the execution of a branch B instruction and a delayed branch BD instruction respectively Because a branch instruction consists of two instruction words it should take at least two instruction cycles to execute completely However a standard branch instruction actually takes four cycles to execute This is illustrated in Example 7 2 Example 7 2 Branch B Instruction in the Pipeline Address Instruction al a2 Bb1 a3 i3 a4 i4 b1 ji 1 2 3 4 5 6 7 8 9 10 Prefetch Fetch Decode Access Read Execute B PAB a1 PB B IR B B Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute Prefetch Fetch Decode Access Read Execute Pipeline flush PAB a4 PB i4 Prefetch Fetch Decode Access Read Execute ji PAB
532. uction and a delayed return with interrupt enable RETED instruction respectively The pipeline behavior for these instructions is similar to that of the standard return and delayed return instruc tions respectively and these instructions also take same number of cycles to execute The difference is that these two instructions enable interrupts globally by resetting the INTM bit during the execute stage of the pipeline Example 7 9 Return With Interrupt Enable RETE Instruction in the Pipeline Address Instruction al RETE a2 i2 a3 i3 b1 ji 1 2 3 4 5 6 7 8 9 10 11 Prefetch Fetch Decode Access Read Execute RETE DB b1 INTM 0 Prefetch Fetch Decode Access Read Execute ae PAB Pipeline flush a2 PB i2 Prefetch Fetch Decode Access Read Execute Pipeline flush He pace a3 Prefetch Fetch Decode Access Read Execute Dummy cycle Ne No V prefetch fetch Prefetch Fetch Decode Access Read Execute No No Dummy cycle prefetch fetch Prefetch Fetch Decode Access Read Execute jl PAB b1 PB j1 jt SPRU131G Pipeline 7 15 Pipeline Operation Example 7 10 Delayed Return With Interrupt Enable RETED Instruction in the Pipeline Address Instruction al RETED a2 i2 a3 i3 b1 ji 1 2 3 4 5 6 T 8 9 10 11 Prefetch Fetch Decode Access Read Execute PAB PBZ RS SP REVED RETED RETED DAB SRDE INTM 0 Prefetch Fetch Decode Access Read Execute a PAB 4 Prefetch Fetch Decode Access Read Execute 4 PAB
533. uction reads B directly Table 7 28 lists the latencies between instructions that update an accumulator directly and instructions that access the same accumulator as a memory mapped register AAAA Note You are responsible for rearranging instructions or inserting NOPs if necessary to accommodate latencies a 7 80 Pipeline SPRU131G Pipeline Latencies Table 7 28 Latencies for Accumulators A and B When Used as Memory Mapped Registers a Latencies based on second instruction category First Instruction All 1 word instructions that directly modify A or B without accessing them as memory mapped registers ADD Smem shiftT src dst LD Smem shiftT dst SUB Smem shiftt src dst All 2 word instructions that directly modify A or B without accessing them as memory mapped registers b Categories for the second instruction Category All instructions that read an accumulator as a memory mapped register AG AH AL BG BH and BL without using a long offset modifier Second Instruction Second Instruction Category Category Il 1 0 1 0 0 0 Category Il All instructions that read an ac cumulator as memory mapped register AG AH AL BG BH BL using a long offset modifier MVKD accum Smem MVDM accum MMR hif ADD accum shift ste det With extended shift LD accum shift dst value of 1616 15 SUB accum shift src dst Legend MMR Any memory mapped register accum Sourc
534. ugh 16 contain the data memory operand bits 15 through 0 are zero filled and bits 39 through 32 are either zero filled SXM 0 or sign extended SXM 1 Table 4 4 shows how the ALU inputs are obtained for the ADD instructions depending on the type of syntax used The ADD instructions execute in one cycle except for cases 4 7 and 8 that use two words and execute in two cycles Table 4 4 ALU Input Selection for ADD Instructions Case Instruction Syntax Words A B DB CB Shift 1 ADD FARIA 1 V V 2 ADD AR3 TS A 1 V 3 ADD AR2 16 B A 1 y V 4 ADD AR1 8 B A 2 V V 5 ADD AR2 8 B 1 V V 6 ADD AR2 AR3 A 1 V V 7 ADD 1234h 6 A B 2 V 8 ADD 1234h 16 A B 2 V 9 ADD A 12 B 1 V V 10 ADD B ASM A 1 V 11 DADD AR2 A B 1 V 4 2 2 Overflow Handling SPRU131G The ALU saturation logic prevents a result from overflowing by keeping the result ata maximum or minimum value This feature is useful for filter calcula tions The logic is enabled when the overflow mode bit OVM in status register ST1 is set Central Processing Unit 4 11 Arithmetic Logic Unit ALU 4 2 3 The Carry Bit 4 2 4 Dual 16 Bit M When a result overflows Lj If OVM 0 the accumulators are loaded with the ALU result without modification Lj If OVM 1 the accumulators are loaded with either the most positive 32 bit value 00 7FFF FFFFh or the most negative 32 bit value FF 8000 0000h depending on the direction of the overflow I The overf
535. ugh the next slot whether a valid receive is executed or not 9 4 4 TDM Mode Transmit and Receive Operations Figure 9 33 shows the timing for TDM port transfers The TCLK and TFRM signals are generated by the timing source device The TCLK frequency is one fourth the frequency of CLKOUT if generated by a C54x device The TFRM pulse occurs every 128 TCLK cycles and is timed to coincide with bit 0 of slot 7 which is the last bit of the previous frame The relationship of TFRM and TCLK allows 16 data bits for each of eight time slots to be driven on the TDAT line which also permits the processor to execute a maximum of 64 instructions during each slot assuming that a C54x DSP internal clock is used Beginning with slot 0 and with the MSB first the transmitter drives 16 data bits for each slot with each bit having a duration of one TCLK cycle with the exception of the first bit of each slot which lasts only half of one bit time Note that data is both clocked onto the TDAT line by the transmitting device and sampled from the TDAT line by receiving devices on the rising edge of TCLK see the data sheet for detailed TDM interface timings Figure 9 33 Serial Port Timing TDM Mode TCLK eT Nef Nf TDAT TEX GIT X BBX Ht 09 GETEX TADD aoo Xato a20 ana Xa TFRM 9 62 Serial Ports SPRU131G SPRU131G Time Division Multiplexed TDM Serial Port Interface Simultaneous with data transfer the transmitting device also drives the TADD l
536. ultiplier s adder and the destination for the result is accumulator A Once an overflow occurs OVA remains set until either a reset a BC D a CC D an RC D or an XC instruction is executed using the AOV and ANOV conditions The RSBxX instruction can also clear this bit Overflow flag for accumulator B OVB is set to 1 when an overflow occurs in either the ALU or the multiplier s adder and the destination for the result is accumulator B Once an overflow occurs OVB remains set until either a reset a BC D a CC D an RC D or an XC instruction is executed using the BOV and BNOV conditions This RSBX instruction can also clear this bit Data memory page pointer This 9 bit field is concatenated with the seven LSBs of an instruction word to form a direct memory address of 16 bits for single data memory operand addressing This operation is done if the compiler mode bit in ST1 CPL 0 The DP field can be loaded by the LD instruction with a short immediate operand or from data memory Central Processing Unit 4 3 CPU Status and Control Registers Figure 4 2 Status Register 1 ST1 Diagram 14 13 12 11 M 15 10 9 8 7 6 5 4 0 Table 4 2 Status Register 1 ST1 Bit Summary Reset Bit Name Value Function 15 BRAF 0 Block repeat active flag BRAF indicates whether a block repeat is currently active BRAF 0 The block repeat is deactivated BRAF is cleared when the block repeat counter BRC decrements below 0 BRAF 1 Th
537. umber are mapped to the on chip RAM at 00 0000 00 7FFF t See Figure 3 4 on page 3 6 for more information about this on chip memory region To facilitate page switching through software the C548 C549 C5402 C5410 and C5420 have six special instructions that affect the XPC _j FB Far branch with or without delay i FBACC Far branch to the location specified by the value in accumulator A or accumulator B with or without delay FCALA Far call to the location specified by the value in accumulator A or accumulator B with or without delay G FCALL Far call with or without delay J FRET Far return with or without delay _j FRETE Far return with interrupts enabled with or without delay The following C54x DSP instructions are extended in the C548 C549 C5402 C5410 and C5420 to use 23 bits 20 bits in the C5402 and 18 in the C5420 _j READA Read program memory addressed by accumulator A and store in data memory _ WRITA Write data to program memory addressed by accumulator A All other instructions do not modify the XPC and access only memory within the current page SPRU131G Memory 3 21 Data Memory 3 3 Data Memory The data memory on the C54x devices contains up to 64K 16 bit words The C54x devices have on chip ROM that can be mapped by software into the data ROM DROM in addition to any dual access RAM DARAM and single access RAM SARAM Table 3 2 shows the on chip
538. umulator Writing to BRC without using an accumulator Writing to BRC using an accumulator Instruction s STM MVDK MVMM MVMD STLM STH STL Store typet POPM STM MVDK MVMM MVMD STLM STH STL Store typet STM MVDK LD Smem T LD Smen T ST STLM STH STL STM MVDK STLM STH Sme Store typet Latency ARx update None BK update The next word must not use circular addressing The next 2 words ARx or 3 words BK must not use the same register The next 1 word ARx or 2 words BK must not use the same register None if CPL 0 The next 1 word must not use SP if CPL 1 The next 2 if CPL 0 or 3 if CPL 1 words must not use SP None The next word must not use T None The next instruction must not be a RPTB D Additional Restrictions None The next instruction must not write to any ARx BK or SP using STM MVDK or MVMD Do not precede a category 3 instruction with any cate gory 2 or 5 instruction that writes to any ARx BK or SH None The next instruction must not write to ARx BK or SP using STM MVDK or MVMD None None None None Category Any other store type instruction See Table 7 5 on page 7 39 for a list of store type instructions Interrupts cause an update of SP This update of SP can interfere with a previous write to SP Therefore special considerations must be made when using interrupts while e
539. unit that shifts bits in a word to the left or to the right sign control logic Circuitry used to extend data bits signed unsigned to match the input data format of the multiplier ALU and shifter sign extension An operation that fills the high order bits of a number with the sign bit sign extension mode SXM A bit in status register 1 ST1 that enables sign extension in CPU operations SMUL See saturation on multiplication Soft bit A bit in the serial port control register SPC buffered serial port control register BSPC timer control register TCR and TDM serial port control register TSPC used in conjunction with the Free bit to determine the state of the serial port or timer clock when a breakpoint is encoun tered in the high level language debugger See also Free bit software interrupt SINT An interrupt caused by the execution of an INTR or TRAP instruction software wait state register SWWSR A 16 bit register that selects the number of wait states for the program data and I O spaces of off chip memory SP See stack pointer SPC SPCO SPC1 serial port control register A 16 bit register that contains status and control bits for the synchronous serial port SPCO corresponds to synchronous serial port 0 SPC1 corresponds to synchro nous serial port 1 D 16 Glossary SPRU131G SPRU131G Glossary SST See saturation on store STO A 16 bit register that contains C54x CPU status and control
540. upt some memory locations The following example illustrates some of these functional aspects of the auto buffering process Consider a transmit buffer of size 5 BKX 5 and a receive buffer of size 8 BKR 8 as shown in Figure 9 27 The transmit buffer may start at any relative address that is a multiple of 8 address 0x0000 0x0008 0x0010 0x0018 Ox07F8 and the receive buffer may start at any relative address that is a multiple of 16 0x0000 0x0010 0x0020 OxO7FO In this SPRU131G Serial Ports 9 47 Buffered Serial Port BSP Interface example the transmit buffer starts at relative address 0x0008 and the receive buffer starts at relative address 0x0010 AXR may therefore contain any value in the range 0x0008 0x000C and ARR may contain any value in the range 0x0010 0x0017 If AXR in this example had been loaded with the value 0x000D not acceptable in a modulo 5 buffer memory accesses would be performed and AXR incremented until it reaches address 0x0010 which is an acceptable starting address for a modulo 5 buffer Note however that if this had occurred AXR would then specify a transmit buffer starting at the same base address as the receive buffer which may cause improper buffer opera tion Figure 9 27 Transmit Buffer and Receive Buffer Mapping Example 9 48 Serial Ports 0000h 0008h Transmit OO0Ah lt ___ AXR BKX 5 000Ch 0010h Receive ARR 0014h 00
541. uring the read phase the data address of the write operand is loaded onto EAB In the following cycle the operand is written to memory using EB Each memory access is performed in two phases by the C54x DSP pipeline In the first phase an address bus is loaded with the memory address In the second phase a corresponding data bus reads from or writes to that memory address Figure 7 2 shows how various memory accesses are performed by the C54x DSP pipeline It is assumed that all memory accesses in the figure are performed by single cycle single word instructions to on chip dual access memory The on chip dual access memory can actually support two accesses in a single pipeline cycle This is discussed in section 7 3 Dual Access Memory and the Pipeline on page 7 27 Pipeline 7 3 Pipeline Operation Figure 7 2 Pipelined Memory Accesses a Instruction word fetch one cycle Prefetch Fetch Decode Access Read Execute Write b Instruction performing single operand read for example LD AR1 A one cycle Prefetch Fetch Decode Access Read Execute Write c Instruction performing dual operand read for example MAC AR2 AR3 A or DLD AR2 A one cycle Prefetch Fetch Decode Access Read Execute Write Load DAB Read from DB and CAB and CB d Instruction performing single operand write for example STH A AR1 one cycle Prefetch Fetch Decode Access Read Execute Write e Instruction performing dual operand write for
542. used to automatically store the program counter during interrupts and subroutines It can also be used at your discretion to store additional items of context or to pass data values The stack is filled from the highest to the lowest memory address The processor uses a 16 bit memory mapped register the stack pointer SP to address the stack SP always points to the last element stored onto the stack Four instructions access the stack using the stack addressing mode g PSHD pushes a data memory value onto the stack 1 PSHM pushes a memory mapped register onto the stack i POPD pops a data memory value from the stack i POPM pops a memory mapped register from the stack A push predecrements and a pop postincrements the address in the SP Figure 5 16 shows an example of the stack and SP before and after a push of X2 into the stack PSHD X2 Figure 5 16 Stack and Stack Pointer Before and After a Push Operation Stack and SP before operation Stack and SP after operation SP 0011 SPRU131G 0001 a SP 0010 0001 0010 fF 0010 X2 0011 0011 X1 0100 fs 0100 0101 fF 0101 Other operations also affect the stack and the stack pointer The stack is used during interrupts and subroutines to save and restore the PC contents When a subroutine is called or an interrupt occurs the return address is automatically saved in the stack using a push operation Instructions used for subroutine calls and interrupts are CALA D CALL D CC D
543. used to refer to each vector location When an INTR interrupt is acknowledged the interrupt mode bit INTM in ST1 is set to 1 to disable maskable interrupts TRAP This instruction performs the same function as the INTR instruction without setting the INTM bit Table 6 19 through Table 6 24 pages 6 38 through 6 43 show the operand K used to refer to each vector location RESET This instruction performs a nonmaskable software reset that can be used any time to put the C54x DSP into a known state The RESET instruction affects STO and ST1 but does not affect PMST For a summary of the registers and bits affected see the description of the RESET instruction in TMS320C54x DSP Reference Set Volume 2 Mnemonic Instruction Set or Volume 3 Algebraic Instruction Set Program Memory Addressing 6 31 Interrupts When the RESET instruction is acknowledged INTM is set to 1 to disable maskable interrupts The initialization of IPTR and the periph eral registers is different from the initialization done by a hardware reset see section 6 9 Reset Operation on page 6 25 6 10 4 Phase 2 Acknowledge Interrupt Interrupt After an interrupt has been requested by hardware or software the CPU must decide whether to acknowledge the request Software interrupts and non maskable hardware interrupts are acknowledged immediately Maskable hardware interrupts are acknowledged only after certain conditions are met 1 Priority is highest When mor
544. usses standard serial ports buffered serial ports and time division multiplexed TDM serial ports Setting Up TMS320 DSP Interrupts in C Application Report literature number SPRAO36 describes methods of setting up interrupts for the TMS320 DSP family of processors in C programming language Sample code segments are provided along with complete examples of how to set up interrupt vectors TMS320VC5402 and TMS320UC5402 Bootloader literature number SPRA618 describes the features and operation of the TMS320VC5402 and TMS320UC5402 bootloader Also discussed is the contents of the on chip ROM TMS320C548 C549 Bootloader Technical Reference literature number SPRU288 describes the process the bootloader uses to transfer user code from an external source to the program memory at power up Pres ently available only on the internet TMS320 Third Party Support Reference Guide literature number SPRU052 alphabetically lists over 100 third parties that provide various products that serve the TMS320 DSP family A myriad of products and applications are offered software and hardware development tools speech recognition image processing noise cancellation modems etc Awide variety of related documentation is available on digital signal processing These references fall into one of the following application categories General Purpose DSP Graphics Imagery Speech Voice Control Multimedia Military Telecommunications Automotiv
545. ve where SAM timings apply for host accesses is shown in Table 8 25 When HRDY is not active HRDY stays high HOM timings apply Refer to the TMS320C54x DSP data sheet for detailed HPI timing specifications Table 8 25 Wait State Generation Conditions Access Sequences Wait State Generated Register Reads Writes HPIC No 1 to DSPINT HINT Yes All other cycles No HPIA No HOM No SAM Yes HPID HOM No HOM No SAM Yes SAM Yes A complete host access cycle always involves two bytes the first with HBIL low and the second with HBIL high This 2 byte sequence must be followed regardless of the type of host access HPIA HPIC or data access and the host must not break the first byte second byte HBIL low high sequence of an ongoing HPI access If this sequence is broken data may be lost and an un predictable operation may result Before accessing data the host must first initialize HPIC in particular the BOB bit and then HPIA in this order because BOB affects the HPIA access After initializing BOB the host can then write to HPIA with the correct byte align ment On an HPI memory read operation after completion of the HPIA write the HPI memory is read and the contents at the given address are transferred to the two 8 bit data latches the first byte data latch and the second byte data latch Table 8 26 illustrates the sequence involved in initializing BOB and HPIA for an HPI memory read In this
546. verview 000 eee tenes 1 3 TMS320C54x DSP Key Features 00 0 cece eee 2 Architectural Overview 0 0c cece eee eee eee Summarizes the TMS320C54x DSP architecture Provides general information about the CPU bus structures internal memory organization on chip peripherals and scanning logic 2 1 Bus Structure 2c2 22 284 25 4 oS eee Bek Davin ghb Makan Sake bed eee Reed Ged eae ee 2 2 Internal Memory Organization 000 e neeaaea 2 21 On Chip ROM ee c8ucce ataa ae beRees Lave EAE E ees 2 2 2 On Chip Dual Access RAM DARAM 00 00 eect e eens 2 2 3 On Chip Single Access RAM SARAM 0 000 eee eens 2 2 4 On Chip Two Way Shared RAM 000 0c cece teens 2 2 5 On Chip Memory Security 0 00 teens 2 2 6 Memory Mapped Registers 0c cece eee eee eee 2 3 Central Processing Unit CPU 0 eee een eee 2 3 1 Arithmetic Logic Unit ALU 0 c cee ee 23 2 jACCUIMUIALONS 5 os ccd oslo cad aac a AAE a a A AEE Pe aad actus Sokeho eden 23 3 Barrel SMET ssc cccc scree rra sawed sacha e aad sa dead sane eka s 2 3 4 Multiplier Adder Unit 0000s 2 3 5 Compare Select and Store Unit CSSU 00 e eee eee 24 Data Addressing sires teeudades a aie haiie aia iaa ei ewe bee eh de 2 5 Program Memory Addressing 00 cece eee eee teen teens 2 6 Pipeline Operation crases s ennau ccc teens 27 On C
547. vice to receive from one or more than one transmitter This can also allow the transmitting device to control which devices receive without the receive address on any of the devices having to be changed The TDM receive address register TRAD contains various information regarding the status of the TADD line which can be polled to verify the previous values of this signal and to verify the relationship between instruction cycles and TDM port timing Bits 138 11 X2 X0 contain the current slot number value regardless of whether a valid data receive was executed in that slot or not This value is latched at the beginning of the slot and retained only until the end of the slot Serial Ports 9 61 Time Division Multiplexed TDM Serial Port Interface Bits 10 8 SO2 S0 hold the number of the last slot plus one modulo eight in which data was received that is if the last valid data read occurred in slot 5 in the previous frame these bits would contain the number six This value is latched during the TDM receive interrupt TRINT at the end of the slot in which the last valid data receive occurred and maintained until the end of the next slot in which a valid receive occurs Bits 7 0 A7 A0 hold the last address sampled on the TADD line regardless of whether a valid data receive was executed or not This value is latched half way through each slot so the value on the TADD may be shifted in and main tained until halfway thro
548. wed by a Software Trap STM k PMST This instruction relocates NOP interrupt vectors by writing to NOP the IPTR bit field TRAP Fetch a TRAP vector from the Ne Ne Ne Ne SN relocated vector table Table 7 27 lists the latencies between instructions that write to the DROM bit of PMST and those that subsequently read from or write to the DROM address range a_ _ __ Va_pe_ _ _ maaanaas gt _ au a_1 SS SGSGa_ a SS a ss Note You are is responsible for rearranging instructions or inserting NOPs if necessary to accommodate latencies ee SPRU131G Pipeline 7 77 Pipeline Latencies Table 7 27 Latencies for the DROM Bit a Latencies based on second instruction category And second instruction is First instruction is Category I the latency is STM lk drom 2 Si lk drom MVDK dmad drom MVMD MMR drom All other instructions that modify 3 DROM b Catagory for the second instruction Category All instructions that read from or write to the DROM address range Legend drom Destination operand pointing at PMST to modify DROM bit in either direct indirect or memory mapped addressing modes Notes 1 Additional latency cycles are required if an external memory access is occurring at the time when an instruction is trying to modify the DROM bit field 2 Any instruction not listed in this table that modifies DROM bit of PMST register has zero latency
549. wide range of arithmetic and logical functions most of which execute in a single clock cycle After an operation is performed in the ALU the result is usually transferred to a destina tion accumulator accumulator A or B Instructions that perform memory to memory operations ADDM ANDM ORM and XORM are exceptions Figure 4 4 ALU Functional Diagram T DB15 DBO D S Shifter output 40 40 40 SXM SXM OVM C16 A A OVA OVB ZA ZB 40 TC 40 A Legend Accumulator A 40 Accumulator B CB data bus DB data bus MAC unit Barrel shifter T register ALU MAC output CAWMZVNODS 4 2 1 ALU Input ALU input takes several forms from several sources The X input source to the ALU is either of two values J The shifter output a 32 bit or 16 bit data memory operand or a shifted accumulator value A data memory operand from data bus DB 4 10 Central Processing Unit SPRU131G Arithmetic Logic Unit ALU The Y input source to the ALU is any of three values Lj The value in one of the accumulators A or B J Adata memory operand from data bus CB _j The value in the T register When a 16 bit data memory operand is fed through data bus CB or DB the 40 bit ALU input is constructed in one of two ways _ If bits 15 through 0 contain the data memory operand bits 39 through 16 are zero filled SXM 0 or sign extended SXM 1 _ If bits 31 thro
550. with the last address on the bus AVIS 1 This mode allows the internal program address to appear at the pins of the C54x device so that the internal program address can be traced Also it allows the interrupt vector to be decoded in conjunction with IACK when the interrupt vectors reside in on chip memory Data ROM DROM enables on chip ROM to be mapped into data space The values for the DROM bit are DROM 0 The on chip ROM is not mapped into data space DROM 1 A portion of the on chip ROM is mapped into data space See Chapter 3 Memory for details CLOCKOUT off When the CLKOFF bit is 1 the output of CLKOUT is disabled and remains at a high level Saturation on multiplication When SMUL 1 saturation of a multiplication result occurs before performing the accumulation in a MAC or MAS instruction The SMUL bit applies only when OVM 1 and FRCT 1 SMUL bit allows the MAC and MAS operations to be consistent with MAC and MAS basic operation defined in ETSI GSM specifications GSM specs 6 06 6 10 6 53 The effect is that the result of 8000h x 8000h is saturated to 7FF FFFFh in fractional mode before performing subsequent addition subtrac tion required by a MAC or MAS instruction In this mode the MAC instruction is equivalent to MPY ADD when OVM 1 If the mode is not set and OVM 1 the result of the multiplication is not saturated before performing the addition subtraction only the results of the MAC and MAS inst
551. wo instruction words have already been fetched How these two instruction words are handled depends in part on whether the branch is nondelayed or delayed J Nondelayed The two instruction words are flushed from the pipeline so that they are not executed and then execution continues at the branched to address J Delayed The one 2 word instruction or two 1 word instructions following the branch instruction are executed This allows you to avoid flushing the pipeline which requires extra cycles cc OO Note The two words following a delayed instruction cannot be an instruction that causes a PC discontinuity a branch call return or software interrupt Table 6 4 shows the unconditional branch instructions in the C54x DSP and the number of cycles needed to execute these instructions both nondelayed and delayed Delayed instructions use two cycles fewer than the correspond ing nondelayed instructions because they do not flush the pipeline 6 6 Program Memory Addressing SPRU131G Branches Table 6 4 Unconditional Branch Instructions Number of Cycles Instruction Description Nondelayed Delayed B D Load PC with the address specified by 4 2 the instruction BACC D Load PC with the address specified by 6 4 the low 16 bits of the designated accumulator 6 3 2 Conditional Branches SPRU131G Conditional branches operate like unconditional branches but they execute only when one or more user specified conditions
552. x latencies for SP memory space 3 2 to 3 14 compiler mode memory mapped registers non compiler mode CPL 0 7 55 conflict example 7 43 latency instructions for accessing definition memory mapped register addressing explanation of least significant bit LSB definition D 11 diagram logic arithmetic operations multiconditional instructions Ta instructions E EM E long immediate addressing RPT instruction MVMD MVMM M POPM PSHM STLM MAC and MAS saturation 4 23 STM 5 26 maskable interrupt memory mapped registers 2 7 3 25 McBSPs 2 16 defined MCM 9 11 9 14 4 D 11 peihana definition D 6 micro stack definition medical applications microcomputer mode definition memory microprocessor mode definition data memory microprocessor microcomputer MP MC 4 6 data security oe definition D 12 extended program memory 3 20 military applications ri xii I O access he n to 19 1 to 19 mode selection clock modes introduction memory on EN ing most significant bit MSB definition D 12 memory space to MP MG program memory definition D 12 extended program memory latencies table 7 76 word order 5 29 MP MC setup followed by an unconditional delayed memory maps call A C541 multichannel buffered serial port McBSP C542 definition a multichannel buffered serial ports 2 16 C546 multicycle instructions transformed to single C548 cycle C5402 B9 multimedia applications vi xi C541
553. xecuting instructions that update SP 7 36 Pipeline SPRU131G Pipeline Latencies Table 7 3 Recommended Instructions for Accessing Memory Mapped Registers Continued Catt 10 11 12 13 14 15 16 iy 18 19 20 Function Writing to ARP Writing to DP Writing to CPL Writing to SXM Writing to ASM Writing to BRAF Writing BRC to memory Writing to OVLY MP MC or IPTR Writing to DROM bit Calculating an exponent Stack manipulation in compiler mode CPL 1 Instruction s LD k ARP LD k DP LD Smem DP RSBX SSBX RSBX SSBX LD k ASM LD Smem ASM RSBX SSBX SRCCD ANDM ORM XORM ANDM ORM XORM EXP FRAME POPM POPD PSHM PSHD Latency None None The next 3 words must not use direct addres sing mode The next word must not be affected by SXM sta tus None The next 5 words must not contain the last instruction word in the RPTB loop The next 2 words must not contain the last instruction word in the RPTB loop The next 6 cycles must not include an instruc tion fetch from the on chip memory s address range The next 3 words must not access the DROM s ad dress range The next instruction must not use T The next instruction must not use direct addressing mode CPL 1 Additional Restrictions None None None None None None None An external bus cycle may cause additional latency
554. xind pmad src MACD ADD LD STH STL SUB auxind pmad src auxind shift src dst With an auxind shift dst extended shiftT src shift auxind and a long offset arc shift auxind modifier auxind shift src dst All other instructions that use ARP or CMPT in indirect addressing mode with or without a long offset modifier Legend Note 7 62 MACD auxind pmad src ADD LD STH STL SUB auxind shift src dst auxind shift dst src shift auxind src shift auxind auxind shift src dst Category Il 2 Without a long offset modifier With an extended shiftt and without a long offset modifier status Destination operand pointing to STO or ST1 to update ARP or CMPT respectively in either direct or indirect addressing modes MMR Any memory mapped register auxind A read or write operand using indirect addressing mode statbit Destination operand writing to a bit in ARP or CMPT T Shift value between 16 and 15 Any instruction that does not fit in either of the two categories has zero latency Pipeline SPRU131G Pipeline Latencies Example 7 41 ARP Load With No Latency in Compatibility Mode CMPT 1 LD 1h ARP This ARP load does not require any latency LD BRO A Example 7 42 ARP Load With a 2 Cycle Latency in Compatibility Mode CMPT 1 STLM A STO The ARP field of STO is updated here NOP NOP ADD ARO 3 B The new ARP value i
555. y blocks see Chapter 3 Memory For device specific on chip memory configurations see the device datsheet Table 2 2 Program and Data Memory on the TMS320C54x Devices Memory Type ROM Program Program data DARAMt SARAMt C541 28K 20K 8K 5K 0 C542 C543 C545 C546 C548 C549 C5402 C5410 C5420 2K 2K 48K 48K 2K 16K 4K 16K 0 2K 2K 32K 32K 2K 16K 4K 16K 0 0 0 16K 16K 0 16K 4K 0 0 10K 10K 6K 6K 8K 8K 16K 8K 32K 0 0 0 0 24K 24K 0 56K 168K t You can configure the dual access RAM DARAM and single access RAM SARAM as data memory or program data memory 2 2 1 On Chip ROM SPRU131G The on chip ROM is part of the program memory space and in some cases part of the data memory space The amount of on chip ROM available on each device varies as shown in Table 2 2 On most devices the ROM contains a bootloader that is useful for booting to faster on chip or external RAM For bootloading details on C54x devices visit the TI web site and review the list of application reports Architectural Overview 2 5 Internal Memory Organization On devices with large amounts of ROM a portion of the ROM may be mapped into both data and program space The larger ROMs are also custom ROMs you provide the code or data to be programmed into the ROM in object file format and Texas Instruments generates the appropriate process mask to program the ROM For details on submitting ROM codes to Texas Instruments see Appendix C S
556. ype instruction that accesses any DAGEN register to load a new value see Table 7 5 on page 7 39 m Move type 1 instruction see Table 7 4 that has a DAGEN register conflict with the previous instruction J The second instruction is a constant initialization type instruction a move type 1 instruction or a move type 2 instruction see Table 7 4 that writes to BK SP or any ARx The instruction must not use a long offset modifier see Example 7 27 I The third instruction uses the same register as the second instruction in indirect addressing mode 7 5 4 Latencies for ARx and BK 7 44 Pipeline An unprotected pipeline conflict can occur when accessing an auxiliary regis ter or BK when both of the following two conditions are met J Ahn instruction writes to an auxiliary register or BK J Thenextinstruction uses the same auxiliary register as an address pointer or index in indirect addressing mode or uses BK in circular addressing mode This instruction could also be an MVMM or a CMPR that reads BK or the same ARx This conflict occurs because the first instruction updates ARx or BK in either the read or execute stage of the pipeline and the following instruction uses BK or the same ARx when it is in the access stage of the pipeline This results in an incorrect ARx or BK read by the second instruction because the previous instruction has not yet updated the register s contents Certain instructions see Table 7
557. zer Proceedings of ICASSP 89 USA pages 801 804 May 1989 Rabiner L R and R W Schafer Digital Processing of Speech Signals Englewood Cliffs NJ Prentice Hall Inc 1978 Reimer J B and K S Lin TMS320 Digital Signal Processors in Speech Applications Proceedings of SPEECH TECH 88 April 1988 Reimer J B M L McMahan and W W Anderson Speech Recognition for a Low Cost System Using a DSP Digest of Technical Papers for 1987 International Conference on Consumer Electronics June 1987 Control 1 2 Ahmed l 16 Bit DSP Microcontroller Fits Motion Control System Applica tion PCIM October 1988 Ahmed l Implementation of Self Tuning Regulators with TMS320 Family of Digital Signal Processors MOTORCON 88 pages 248 262 Septem ber 1988 Allen C and P Pillay 7MS320 Design for Vector and Current Control of AC Motor Drives Electronics Letters UK Volume 28 Number 23 pages 2188 2190 November 1992 Read This First xi Technical Articles xii 4 Panahi I and R Restle DSPs Redefine Motion Control Motion Control Magazine December 1993 5 Lovrich A G Troullinos and R Chirayil An All Digital Automatic Gain Control Proceedings of ICASSP 88 USA Volume D page 1734 April 1988 6 Ahmed l and S Meshkat Using DSPs in Control Control Engineering February 1988 7 Meshkat S and I Ahmed Using DSPs in AC Induction Mo

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