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PMC66-SIO4BXR - General Standards Corporation

1. 29 AVA TDMA REGISTERS 5 29 4 1 4 1 DMA CHANNEL MODE REGISTER PCI 0x80 0X94 enne enne nnne rennen 29 CHAPTER 5 HARDWARE CONFIGURATION e eese eese eese een oeste ense seta e ese sese ease sese snae seta 30 5 0 BOARD LAY OUT 5 E 30 5 1 BOXRD ID JUMPER veese rete ce ceo 31 5 2 RESISTORS 2 CERTUS 31 5 3 ri DP MI MM MIDI M ED T CD 31 5 4 INTERFACE CONNECTORS ree Fee FPE EFEEEREREFEEE PEE EE ER E EE Eee ERE ETE EE FREE Nep EEEE 32 CHAPTER 6 ORDERING 22 555555 55921 555538855245 00 3888846 848061468465900465 6 06056660 660 6606 34 6 0 ORDERING INFORMATION e n n nnn nnn nnn a eaa ikea E sese se naa 34 6 1 eee v EE Pe Ee 34 6 2 DEVICE DRIVERS
2. General Standards Corporation High Performance Bus Interface Solutions System I O Connections cont PMC P4 Note Protocol Mode is set on a per channel basis RS422 RS485 V 35 RS232 RS423 DTE DCE DCE DTE DCE Unused RS422 RS485 V 35 RS232 RS423 DTE TXC3 DCE RXC3 DCE DTE DCE Unused TXCl RXC1 Unused TXC3 RXC3 Unused TXDI RXDI Unused TXD3 RXD3 Unused TXD1 RXD1 Unused TXD3 RXD3 Unused RTSI1 CTSI RTSI CTS1 RTS3 CTS3 RTS3 CTS3 RTS1 CTS1 Unused RTS3 CTS3 Unused AUXCI RXCI TXCI AUXC3 RXC3 TXC3 AUXC1 RXCI AUXC3 TXC3 RXC3 DCDI RXDI TXDI DCD3 RXD3 TXD3 DCD1 TXDI RXDI DCD3 TXD3 RXD3 S co RP a nused RXC3 TXC3 nused N RXC1 TXC1 nused RXC3 TXC3 nused RXDI TXDI nused RXD3 TXD3 RXD1 TXD1 nused RXD3 TXD3 nused CTSI RTSI1 RTS1 CTS3 RTS3 U U Unused U 3 CTS
3. x4 Channels Universal RS485 RS422 we 21 Controller Transceiver Rx 4 68 Pin FIFO N 4 Receiver User Tx Transmitter FIFO I 3 Bridge fore et ee ee es ERROR SRI MERE 64 Pin Control FMG Logic a Osc Figure 1 1 Block Diagram of PMC66 SIO4BXR 1 1 Z16C30 Universal Serial Controller The PMC66 SIO4BXR is designed around the Z16C30 Universal Serial Controller USC The Z16C30 is a dual channel multi protocol serial controller which may be software configured to satisfy a wide variety of serial communications applications The USC supports most common asynchronous and synchronous serial protocols The USC provides many advanced features including e Completely independent transmitter and receiver operation e Odd Even Space Mark parity e Two 16 bit or one 32 bit CRC polynomial e Fight Data Encoding methods NRZ NRZB NRZI Mark NRZI Space Biphase Mark Biphase Space Biphase Level and Differential Biphase Level 12 Deep Transmit Receive FIFOs Data is transferred to from the serial interface through Transmit and Receive FIFOs Each of the four serial channels has an independent Transmit FIFO and a Receive FIFO for a total of eight separate on board FIFOs These FIFOs can vary from 4k bytes to 32k bytes based on ordering option FIFOs allow data transfer to co
4. eue et dee Opec eed 34 6 3 CUSTOM APPLICATIONS etr EM 34 APPENDIX A PROGRAMMABLE OSCILLATOR 2 24 22 4 00 2410 40040 000 0 4 35 APPENDIX B FIRMWARE REVISIONS FEATURES REGISTER 4 ee ee eere eese 0 38 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com iv Rev 4 General Standards Corporation High Performance Bus Interface Solutions CHAPTER 1 INTRODUCTION 10 General Description The PMC66 SI04BXR board is a four channel serial interface card which provides high speed full duplex multi protocol serial capability for PMC applications The SIO4BXR combines two multi protocol Dual Universal Serial Controllers USCG 8 external FIFOs and multiprotocol transceivers to provide four fully independent synchronous asynchronous serial channels These features along with a high performance PCI interface engine give the PMC66 SIO4BXR unsurpassed performance in a serial interface card Features e Four Independent Multi Protocol Serial Channels e Synchronous Serial Data Rates up to 10 Mbits sec e Asynchronous Serial Data Rates up to 1 Mbit sec e Independent Transmit and Receive FIFOs for each Serial Channel Options from 4k to 32k Deep e Serial Mode Protocol
5. 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com iii Rev 4 General Standards Corporation High Performance Bus Interface Solutions 3 3 BOARD VS CHANNEL REGISTERS a a a a A a A 22 3 4 PROGRAMMABLE OSCILLATOR PROGRAMMABLE 8 40000 0 22 3 5 e Foe ius 23 3 6 MULTIPROTOCOL TRANSCEIVER CONTROL 0ssesesessssssssssssscsescssnsssesscssssscsessssnseessssssessseenseessesnsesnsesnsseees 25 3 7 E 25 3 8 LOOPBACK MODES 25 3 9 GENERAL PURPOSE TO EE det Dee Ee TE aede eene ce PEE 26 3 10 INTERRUPTS iere etie bere MEE Od 26 3 11 GIN DJ P KU 26 CHAPTER 4 349054 SUE SER UE 28 4 0 PCI INTERFACE REGISTERS 4 ene ore te E Bee ERO Ie 28 4 1 PCIREGISTERS eee ted NEIN enu e iie vu eia 28 4 1 1 PCI CONFIGURATION 5 5 28 4 1 2 LOCAL CONFIGURATION 5 5 29 4 1 3 RUNTIME REGISTERS 525
6. PLX PCI 9056 Data Book PLX Technology Inc 390 Potrero Avenue Sunnyvale CA 4085 408 774 3735 http www plxtech com EIA 422 A Electrical Characteristics of Balanced Voltage Digital Interface Circuits EIA order number EIA RS 422A EIA 485 Standard for Electrical Characteristics of Generators and Receivers for Use in Balanced Digital Multipoint Systems EIA order number EIA RS 485 EIA Standards and Publications can be purchased from GLOBAL ENGINEERING DOCUMENTS 15 Inverness Way East Englewood CO 80112 Phone 800 854 7179 http global ihs com PCI Local Bus Specification Revision 2 2 December 18 1998 Copies of PCI specifications available from PCI Special Interest Group NE 2575 Kathryn Street 17 Hillsboro OR 97124 http www pcisig com General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email sales generalstandards com ii Rev 4 General Standards Corporation High Performance Bus Interface Solutions TABLE OF CONTENTS CHAPTER 1 INTRODUCTION siiisissccscsscescsccesissoccscesssbscssecasssnnssoosestacesconssnoecsetesssscoesessvandesoossssssoseesseseessenssossesseease 1 1 0 GENERAL DESCRIPTION 5555 dieu due 1 1 1 Z16C30 UNIVERSAL SERIAL CONTROLLER 2 2020000000000000000000000000000000000 2 1 2 DEEP TRANSMIT RECEI
7. Protocol Xevr Multi Protocol Xevr Multi Protocol Bridge Multi Protocol Figure 5 1 Board Layout Multi Protocol Multi Protocol Multi Protocol Multi Protocol Figure 5 2 Board Layout Bottom General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 30 Rev D General Standards Corporation High Performance Bus Interface Solutions 5 1 Board ID Jumper J5 Jumper J5 allows the user to set the Board ID in the GSC Board Status Register See Section 2 1 3 This is useful to uniquely identify a board if more than one SIO4BXR card is in a system When the Board ID jumper is installed it will read 1 in the Board Status Register The Board Status Register bit will report 0 when the jumper is removed Refer to Figure 5 1 f
8. 1 0 0 USC_TxC 1 0 1 USC_RxC 1 1 0 Cable RxC Input 1 1 1 Cable RxAuxC Input General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 14 Rev D General Standards Corporation High Performance Bus Interface Solutions D5 3 USC RxC Source Defines the Clock Source for the USC RxC pin The clock source must agree with the USC Clock setup USC I O Control Reg D5 3 to ensure the signal is not being driven by both the USC and the T 0 0 0 Prog Clock 000 Input 0 0 1 Inverted Prog Clock 000 Input 0 1 0 0 000 Input 0 1 1 T 000 Input 1 0 0 Cable RxC Input 000 Input 1 0 1 Cable RxAuxC Input 000 Input 1 1 0 RESERVED e 1 1 1 Driven from USC IOCR 2 00 000 Output D2 0 USC TxC Source Defines the Clock Source for the USC TxC pin Since this signal is bidirectional it may be used as either an input or output to the USC the clock source must agree with the USC Clock setup USC IO Control Reg D2 0 to ensure the signal is not being driven by both the USC and the wes T 0 0 0 Prog Clock 000 Input 0 0 1 Inverted Prog Clock 000 Input 0 1 0 0 000 Input 0 1 1 T 000 Input 1 0 0 Cable RxC Input 000 Input 1 0 1 Cable R
9. D10 Tx FIFO Almost Full Flag Lo 0 Tx FIFO Almost Full D9 Tx FIFO Almost Empty Flag Lo 0 Tx FIFO Almost Empty D8 Tx FIFO Empty Flag Lo 0 Tx FIFO Empty General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 8 Rev D General Standards Corporation High Performance Bus Interface Solutions D7 0 Channel Control Bits D7 Reset USC Pulsed 1 Reset USC chip Notes This value will automatically clear to 0 e Following a USC Reset the next access to the USC must be a write of 0x00 to Local Offset 0x100 1 2 or Local Offset 0x300 Ch3 4 e Since two channels share each USC Chl amp Ch2 Ch3 amp Ch4 resetting a USC will affect both channel D6 Reserved Channel Reset 05 04 FIFO Rx Tx Allocation 48KLC and 64K options only 00 48KLC 8kRx 4kTx 64k 16kRx 8kTx 01 48KLC 4kRx 8kTx 64k 8kRx 16kTx D3 Receive Status Word Enable 1 Receive status word RSR is saved in data stream with every received data word D2 Timestamp Enable 1 24 bit timestamp word is saved in data stream with every received data word D1 Reset Channel Rx FIFO Pulsed Note This value will automatically clear to 0 DO Reset Channel Tx FIFO Pulsed Note This value will automatically clear to 0 2 1 9 Channel Sync Detect Byte Local Offset 0x0050 0x0054 0x0058 0x005C The Sync Detect Byte al
10. PMC66 SIO4BXR Rev E D15 8 Firmware Type ID 01 SIO4B Standard D7 0 Firmware Revision Firmware Version General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 5 Rev D General Standards Corporation High Performance Bus Interface Solutions 2 1 2 Board Control Local Offset 0x0004 The Board Control Register defines the general control functions for the board D31 D30 D29 D28 27 D26 24 D23 D22 D21 9 D8 D7 D6 4 D3 D2 0 Board Reset 1 Reset all Local Registers and FIFOs to their default values Notes This bit will automatically clear to 0 following the board reset Board Reset will NOT reset programmable oscillator Following a Board Reset ResetInProgress bit D31 of the Board Status Register will remain set until the Board reset is complete RESERVED Debug Test FIFO Test 0 Normal Mode FIFO Write to Tx FIFO FIFO Read from Rx FIFO 1 Test Mode FIFO Write to Rx FIFO FIFO Read from Tx FIFO FIFO Allocation 64k option only 01 Ch1 Ch2 32k Ch3 Ch4 4k 8k 10 Chl 64k Ch2 Ch3 Ch4 4k 8k LED D4 D2 1 Turn on green LED D2 D3 D4 Timestamp Clear 0 timestamp counter is enabled 1 reset timestamp count to zero Timestamp Source 0 timestamp counter runs off internal 105 clock 1 timestamp counter runs off external TTL clock if board is configured for extern
11. DMA and Non Demand Mode DMA Demand Mode DMA refers to data being transferred on demand For receive this means data will be transferred as soon as it is received into the FIFO Likewise for transmit data will be transferred to the FIFOs as long as the FIFO is not full The disadvantage to Demand Mode DMA is that the DMA transfers are dependent on the user data interface If the user data transfer is incomplete the Demand mode DMA transfer will also stop If a timeout occurs there is no way to determine the exact amount of data transferred before it was aborted General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 26 Rev D General Standards Corporation High Performance Bus Interface Solutions Non Demand Mode DMA does not check the FIFO empty full flags before or during the data transfer it simply assumes there is enough available FIFO space to complete the transfer If the transfer size is larger than the available data the transfer will complete with invalid results This is the preferred mode for DMA operation The FIFO Counters may be used to determine how much space is available for DMA so that the FIFO will never over under run Demand Mode DMA requires less software control but runs the risk of losing data due to an incomplete transfer The GSC library uses this method Non Demand DMA and checking the FIFO counters a
12. RTS3 A CTS1 TXC2 RTS1 RXC2 nused nused CTS3 TXC4 RTS3 RXC4 nused nused TXC2 RXC2 nused TXC4 RXC4 TXD2 RXD2 Unused TXD4 RXD4 nused TXD2 RXD2 Unused TXD4 RXD4 U U Unused U U nused RTS2 CTS2 RTS2 CTS2 RTS4 CTS4 RTS4 CTS4 RTS2 CTS2 U nused RTS4 CTS4 U nused AUXC2 RXC2 TXC2 AUXC4 AUXC2 TXC2 RXC2 AUXC4 TXC4 RXC4 DCD2 RXD2 TXD2 DCD4 RXD4 TXD4 DCD2 TXD2 RXD2 DCD4 TXD4 RXD4 RXC2 TXC2 Unused RXC4 TXC4 Unused RXC2 TXC2 Unused RXC4 TXC4 Unused RXD2 TXD2 Unused RXD4 TXD4 Unused RXD2 TXD2 Unused RXD4 TXD4 Unused CTS2 RTS2 CTS2 RTS2 CTS4 RTS4 CTS4 RTS4 CTS2 RTS2 Unused CTS4 RTS4 Table 2 PMC P4 Rear IO Connections Unused General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 33 Rev D General Standards Corporation High Performance Bus Interface Solutions CHAPTER 6 ORDERING OPTIONS 6 0 Ordering Information PMC66 SIO4BXR lt FIFO Size gt lt Temperature
13. RxC RxD RxAuxC and DCD have built in termination at the transceivers These internal terminations may be disabled to allow external terminations or no terminations to be used Setting this bit will disable the internal transceiver termination resistors 029 External Loopback Mode When DCE DTE Mode is enabled Bit D31 1 this bit will automatically loopback the TxC RxC TxD RxD and RTS CTS signals at the cable transceivers enabled This allows the transceivers to be tested in a standalone mode Notes e The DCE DTE mode will select the set of signals DCE or DTE to be looped back e Since the transceivers will be enabled this mode all external cables should be disconnected to prevent interference from external sources D28 DCE DTE Mode When DCE DTE Mode is enabled Bit D31 1 this bit set the mode to DCE 1 or DTE 0 DCE DTE mode changes the direction of the signals at the IO Connector D27 24 Transceiver Protocol Mode 0 0 0 0 RS 422 RS 485 0 0 0 1 RS 423 0 0 1 0 RS 232 0 0 1 1 RESERVED 0 1 0 0 RS530 Mode RS 422 RS 423 0 1 0 1 RS530A Mode RS 422 RS 423 0 1 1 0 V 35 Mode 35 5 232 0 1 1 1 RESERVED 1 X X X RESERVED General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 12 Rev D General Standards Corporation High Performan
14. Since the SIO4BXR has much deeper external FIFOs or internal FPGA FIFOs the internal USC FIFOs are setup to immediately transfer data to from the external FIFOs Immediate transfer of received data to the external FIFOs eliminates the possibility of data becoming stuck in the USC internal receive FIFOs while bypassing the USC internal transmit FIFOs ensures better control of the transmit data In order to automatically transfer data to and from the external FIFOs the USC should use DMA to request a data transfer whenever one byte is available in the USC internal FIFOs This DMA should not be confused with the DMA of data from the SIO4BXR external FIFOs to the PCI interface To accomplish the USC to External FIFO DMA transfer the TxReq RxReq pins should be set as DMA Requests in the IOCR and the TxAck RxAck pins should be set as DMA Acknowledge inputs in the In addition the Tx Request Level should be set to Ox1F 31 using TCSR TICR and the Rx Request Level should be set to 0 using RCSR RICR See Z16C30 manual for further details on programming the DMA request levels General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 19 Rev D General Standards Corporation High Performance Bus Interface Solutions 2 2 4 USC Register Memory Map To access the USC in 8 bit mode the driver is required to access the uppe
15. fields independent of DCE DTE mode TxC TxC Out RxC In RxC RxC In TxC Out TxD TxD Out RxD In RxD RxD In TxD Out RTS RTS Out CTS In CTS CTS In RTS Out DCD Direction controlled by Pin Source Reg D16 15 AuxC Direction controlled by Pin Source Reg D18 17 3 8 Loopback Modes For normal operation the Cable Transceiver Enable bit of the Pin Source Register will turn on the cable transceivers and the DTE DCE Mode bit will set the transceiver direction These bits must be set before any data is transmitted over the user interface Additionally there are several ways to loopback data to aid in debug operations Data may be physically looped back externally by connecting one channel to another For DB25 cable applications this simple loopback method will require a gender changer to connect one channel to another One channel will be set to DTE mode the other to DCE mode Data sent from one channel will be received on the other General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 25 Rev D General Standards Corporation High Performance Bus Interface Solutions An External Loopback mode External Loopback bit set in the Pin Source Register is also provided to loop back data on the same channel without requiring any external cabling In this mode the DTE DCE mode will control the location for the t
16. gt Valid Selections FIFO Size 48KLC software selectable 4K byte Tx 8K byte Rx FIFO 8K byte Tx 4K byte Rx FIFO mem selectable 8K byte Tx 16K byte Rx FIFO or 16K byte Tx 8K byte Rx FIFO 256K 32K byte Tx 32K byte Rx FIFO C to 70 C Commercial Standard 40 C to 85 C Industrial Please consult our sales department with your application requirements to determine the correct ordering options quotes generalstandards com 6 1 Interface Cable General Standards Corporation can provide an interface cable for the SIO4BXR board This standard cable is a twisted pair cable for increased noise immunity Several standard cable lengths are offered or the cable length can be custom ordered to the user s needs Versions of the cable are available with connectors on both ends or the cable may be ordered with a single connector to allow the user to adapt the other end for a specific application A standard cable is available which will breakout the serial channels into eight DB25 connectors Shielded cable options are also available Please consult our sales department for more information on cabling options and pricing 6 2 Device Drivers General Standards has developed many device drivers for The SIO4BXR boards including VxWorks Windows Linux and LabView As new drivers are always being added please consult our website www generalstandards com or consult our sales department for a complete list of available dri
17. is driven from the Pin Source register the user should program the pin as an input to the USC General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 23 Rev D General Standards Corporation High Performance Bus Interface Solutions FPGA CLOCK CONTROL ProgClk TxAuxC Source Pin Source Reg D18 D17 RxAuxC IO RxC Connector RxC TxC On Board Source Programmable ProgClk Oscillator Pin Source Reg USC TxC m D5 D6 Source Pin Source Reg D2 DO USC TxC USC 4 USC RxC Source USC USC RxC USC RxC Pin Source Reg D5 D3 Figure 3 1 Clock Configuration The programmable clocks on the SIO4BXR provide flexibility to handle almost any clock configuration scenario However this flexibility can also complicate the clock setup especially for simple setups The following guidelines are typical asynchronous and synchronous setups which should work for most setups In asynchronous mode the clock does not need to be transmitted with the data Therefore the USC Clock pins will be used for the input baud rate clock Since the RxC and TxC pins have identical functions the RxC and TxC pins may be used interchangeably The async baud rate clock will be 16x 32x or 64x the actual baud rate due
18. on the SIO4BXR performance The following section attempts to filter the information from the PCI9056 manual to provide the necessary information for a SIO4BXR specific driver The SIO4BXR uses an on board serial EEPROM to initialize many of the PCI9056 registers after a PCI Reset This allows board specific information to be preconfigured correctly 4 1 1 PCI Configuration Registers The PCI Configuration Registers allow the PCI controller to identify and control the cards in a system PCI device identification is provided by the Vendor ID Device ID Addr 0x0000 and Sub Vendor ID Sub Device ID Registers 0 002 The following definitions are unique to the General Standards SIO4BXR boards drivers should verify the ID Sub ID information before attaching to this card These values are fixed via the Serial EEPROM load following a PCI Reset and cannot be changed by software Vendor ID 0 10 5 PLX Technology Device ID 0x9056 PCI9056 Sub Vendor ID 0 10 5 PLX Technology Sub Device ID 0x3198 GSC SIO4BXR The configuration registers also setup the PCI IO and Memory mapping for the SIO4BXR The PCI9056 is setup to use PCIBARO and PCIBARI to map the internal PLX registers into PCI Memory and IO space respectively PCIBAR2 will map the Local Space Registers into PCI memory space and PCIBAR3 is unused Typically the OS will configure the PCI configuration space For further information of the PCI configuration registers please consult the
19. the firmware versions Bits will be assigned as new features are added See Appendix B for more details D31 23 RESERVED D22 1 Rx Stop on Full in Ch Ctrl D21 1 2 SRAM Debug D20 1 No Rx Status byte std only D19 D18 10 Internal Timestamp std only D17 D16 01 FPGA Reprogram field D15 D14 01 Configurable FIFO space D13 1 FIFO Test Bit D12 1 FW Reg D11 8 Features Rev Level BX level D7 1 Demand Mode DMA Single Cycle Disable feature implemented D6 1 Board Reset D5 1 FIFO Counters Size D4 1 D3 0 Programmable Clock Configuration 0x4 Two CY22393 6 Oscillators General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 17 Rev D General Standards Corporation High Performance Bus Interface Solutions 2 2 Universal Serial Controller Registers The internal registers of the Zilog Z16C30 Universal Serial Controller USC are memory mapped into Local Address space It is beyond the scope of this manual to provide comprehensive USC programming information For detailed programming information please refer to the Zilog High Speed Communication Controller Product Specifications Databook for the Z16C30 and the Zilog Z16C30USC User s Manual These manuals may be obtained directly from Zilog www zilog com or copies of these manuals may be downloaded from the General Standards website www generalst
20. to the async oversampling This oversample rate is set in the USC Channel Mode Register when async mode is selected The simplest method will be to program the channel programmable clock to be 16 32 64 times the desired baudrate and use this clock as the source for the TxC RxC pin Section 2 1 11 describes how to program the Pin Source Register to set TxC RxC Programmable Clock The USC should be programmed such that TxC RxC is an input in the USC I O Control Register and the USC baudrate generator will be bypassed completely If both Rx and Tx are operating at the same baud rate the same USC clock pin can be used for both the transmit and receive clocks For synchronous modes the clock is transmitted and received on the cable along with the data This can present a problem since the USC only has two clock pins Since one clock is necessary for receive clock and the other is necessary for the transmit clock there is no clock pin available for an input to the USC baud rate generators The on board programmable clocks provide a solution for this situation By using the programmable oscillator and the programmable clock post divider the on board programmable clock can usually be set directly to the desired transmit baud rate The USC TxC pin and the Cable TxC are both set equal to the Programmable Clock in the Pin Source Register The USC RxC pin is used for the receive clock from the cable interface so it will be set to the cable RxC in the Pin So
21. 1 ICD2053B 1 Osc 0x2 ICD2053B 4 Osc 0x3 CY22393 4 Osc 0 4 2 x CY22393 6 Osc General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 39 Rev D
22. 22 RS485 V 35 35 AUXC1 AUXC3 Unused AUXCI TXCI AUXC3 AUXC3 DCD1 RXDI DCD3 Unused DCDI TXDI DCD3 DCD3 CTS1 RTS1 nused CTS3 RTS3 Unused CTSI RTSI RTSI CTS3 RTS3 CTS3 RTS3 RXD1 TXD1 S nused RXD3 TXD3 Unused RXDI TXDI nused RXD3 TXD3 RXD3 TXD3 TXC1 S Unused RXC3 TXC3 Unused 1 1 nused RXC3 TXC3 RXC3 TXC3 RTS1 CTS1 5 nused RTS3 CTS3 Unused RTSI CTSI CTSI RTS3 CTS3 RTS3 CTS3 TXDI1 RXD1 5 nused TXD3 RXD3 Unused TXDI RXDI nused TXD3 RXD3 TXD3 RXD3 TXC1 1 nused TXC3 RXC3 Unused TXCl 1 nused TXC3 RXC3 TXC3 RXC3 SGNDI SGND3 SGND3 SGND2 SGND4 CTS2 RTS2 CTS4 RTS4 CTS2 RTS2 CTS4 RTS4 RXD2 TXD2 5 RXD4 TXD4 RXD2 TXD2 S RXD4 TXD4 RXC2 TXC2 5 5 RXC4 TXC4 RXC2 TXC2 RXC4 TXC4 RTS2 CTS2 5 RTS4 CTS4 RTS2 CTS2 RTS4 CTS4 TXD2 RXD2 5 TXD4 RXD4 TXD2 RXD2 Unused TXD4 RXD4 TXC2 RXC2 5 Unused TXC4 RXC4 TXC2 RXC2 Unused TXC4 RXC4 DCD2 TXD2 RXD2 DCD4 DCD2 RXD2 TXD2 DCD4 AUXC2 TXC2 RXC2 AUXC4 AUXC2 RXC2 TXC2 AUXC4 Table 1 Front Panel P5 IO Connections General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 32 Rev D S o un BY Ge N
23. 3 is controlled by Board Control Register D25 LED D4A is controlled by Board Control Register 026 The remaining 8 LEDs are controlled 2 each from D23 D20 of the Channel Control Register Additionally if all the LED controls are set to O in all four of the Channel Control Registers power up default the LEDs will display the lower 6 bits of the firmware revision in LED D7 to LED 12 LED D5 should power up off and LED D7 should power up on to indicate all channels are set to SYNC Channel Control Register D23 D20 allow software control of the LEDs Each Channel Control Register controls 2 LEDs in order from Ch4 to Ch1 If 023 022 10 the upper LED will turn off Likewise if D23 D22 11 the upper LED will turn on D21 D20 control the lower LED in the pair General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 31 Rev D General Standards Corporation High Performance Bus Interface Solutions 5 4 Interface Connectors User I O Connector 68 pin SCSI connector female P5 Part Number AMP TYCO 787170 7 Mating Connector AMP TYCO 749111 6 or equivalent Pin 34 Pin 1 Y QN 68 35 Note Protocol Mode is set per channel basis RS422 RS485 RS4
24. CHANNEL FIFO LOCAL OFFSET 0x0018 0x0028 0x0038 0 0048 8 2 1 8 CHANNEL CONTROL STATUS LOCAL OFFSET 0x001C 0x002C 8 2 1 9 CHANNEL SYNC DETECT BYTE LOCAL OFFSET 0x0050 0x0054 0x0058 0 005 9 2 1 10 INTERRUPT REGISTERS cccesescccececsessssececececeesenseceeececeenenseaecececeesesseaeseeececeesesaeseesceesesseaeseeececeeseaseeeeeeeeenes 10 2 1 10 1 INTERRUPT CONTROL LOCAL OFFSET 0 0060 ccccsessscccececsessnsececececsessaececeeeeseseaeseseeeceesesseaeeeeees 11 2 1 10 2 INTERRUPT STATUS CLEAR LOCAL OFFSET OXOO64 cccccecsessssssecececsesenseseeeceesessaesesececeesenseaeeeeees 11 2 1 10 3 INTERRUPT EDGE LEVEL LOCAL OFFSET 0 0068 202 2020200000 0 0 000000000000000 11 2 1 10 4 INTERRUPT HI LO LOCAL OFFSET 0 006 11 2 1 11 CHANNEL SOURCE LOCAL OFFSET 0X0080 0x0084 0x0088 8 12 2 1 12 CHANNEL PIN STATUS LOCAL OFFSET 0X0090 0 0094 0x0098 9 15 2 1 13 PROGRAMMABLE CLOCK REGISTERS LOCAL OFFSET 4 0 00 8 OXAC 16 2 1 14 FIFO COUNT REGISTER LOCAL OFFSET 0 00 0 0 00 04 0 0008 0X00DC 16 2 1 15 FIFO SIZE R
25. EGISTER LOCAL OFFSET OXOOEA 0 00 8 16 2 1 16 FW ID REGISTER LOCAL OFFSET OXOOF8 ccccsessecececeesesseceeecececeesesaeeeeececsesaeseeeeeceeseaaseeeeeeeeensa 16 2 1 17 FEATURES REGISTER LOCAL OFFSET 0 00 17 22 UNIVERSAL SERIAL CONTROLLER REGISTERS cscsessssecececeesseaececececsesseaesecececeeseaeseeececsessaaseeseeseeesenseaeeeeess 18 PALME UNIO UELUT 18 22 2 S BIT USCCREGISTER ACGESS decre siepe erede no ro rye rece Ve Een 18 2 2 3 USC DATATRANSEER oerte reves tete aet e pee neo 19 2 2 4 USC REGISTER MEMORY 20 CHAPTER 3 PROGRAMMING sisiscscssccsesssssscscssssssesesessessssasessssssscoscsossssascsecs aS aU 21 3 0 ER 21 3 1 RESETS oo 21 3 2 BIEOS I ST 21 FIFO FLAGS CPI a 21 SEES digerit 22 328 FIFRO SIE 4 en t testet tenu 22 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone
26. LL1 P Lo 0 Setup2 0x00 0x48 PLL1 Enable PLL1 P Hi Setup2 0x00 0x49 PLL1 Setup3 0x00 Ox4A PLL1 P Lo 0 Setup3 0x00 Ox4B PLL1 Enable PLL1 P Hi Setup3 0x00 0 4 Setup4 0x00 Ox4D PLL1 P Lo 0 Setup4 0x00 Ox4E PLL1 Enable PLL1 P Hi Setup4 0x00 Ox4F 11 Setup5 0 00 0 50 PLL1 P Lo 0 Setup5 0x00 0x51 PLL1 Enable PLL1 P Hi Setup5 0x00 0x52 11 Setup6 0 00 0 53 PLL1 P Lo 0 Setup6 0x00 0x54 PLL1 Enable PLL1 P Hi Setup6 0x00 0x55 PLL1 Setup 0x00 0x56 PLLI P Lo 0 Setup7 0x00 0x57 PLL1 Enable PLL1 P Hi Setup 0x00 0 58 0 Reserved Unused 0x00 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 37 Rev D General Standards Corporation High Performance Bus Interface Solutions APPENDIX B FIRMWARE REVISIONS FEATURES REGISTER Since 5104 boards can exist across multiple form factors and with various hardware features the firmware features registers attempt to help identify the exact version of a SIO4 board This appendix provides a more detailed breakdown of what the firmware and features registers and detail differences between the firmware revisions Firmware Register Local Offset 0x00 0 2250119 D31 16 HW Board Rev 0 225 PMC66 SIO4BXR Rev D31 1 Features Register Present D30 1 Complies with this standard D29 1 66MHz PCI bus inte
27. PGA CLOCK RAM to allow the user to simply setup the data in the FPGA RAM and then command the on board logic to program the clock chip This isolates the user from the hardware serial interface to the chip For detailed CY22393 programming details please refer to the Cypress Semiconductor CY22393 data sheet For the SIO4BXR a second programmable oscillator has been added to assure that each channel has a dedicated PLL The older SIO4BX uses 3 PLLs in a single CY22393 to generate all four clocks To implement this a second CLOCK RAM block was added CLOCK programs the first CY22393 using CLKA Ch1_Clk CLKB Ch2_Clk CLKC Ch3_Clk and CLOCK_RAM2 programs the second CY22393 using CLKD Ch4_Clk Since the original SIO4BX with a single CY22393 used CLKD for Ch4_Clk the same code can be made to support both schemes by simply programming CLKD of the first CY22393 Each CLOCK RAM block is accessed through 2 registers Address Offset at local offset and Data at local ffset at 4 CLOCK or CLOCK RAM2 The user simply sets the RAM Address register to the appropriate offset then reads or writes the the RAM data The Programmable Osc Control Status register allows the user to program the CY22393 or setup the clock post dividers The GSC Local Programmable Clock Registers are defined as follows 0x00A0 RAM Address Register Defines the internal CLOCK RAM address to read write 0x00A4 RAM Da
28. PLX Technology PCI9056 Manual General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 28 Rev D General Standards Corporation High Performance Bus Interface Solutions 4 1 2 Local Configuration Registers The Local Configuration registers give information on the Local side implementation These include the required memory size The SIO4BXR memory size is initialized to 4k Bytes All other Local Registers initialize to the default values described in the PCI9056 Manual 41 3 Runtime Registers The Runtime registers consist of mailbox registers doorbell registers and a general purpose control register The mailbox and doorbell registers are not used and serve no purpose on the SIO4BXR All other Runtime Registers initialize to the default values described in the PCI9056 Manual 4 1 4 DMA Registers The Local DMA registers are used to setup the DMA transfers to and from the on board FIFOs DMA is supported only to the four FIFO locations The SIO4BXR supports both Demand DREQ controlled and Non Demand mode DMA Both Channel 0 and Channel 1 DMA are supported 4 1 4 1 DMA Channel Mode Register PCI 0x80 0x94 The DMA Channel Mode register must be setup to match the hardware implementation Bit Description Value Notes D1 0 Local Bus Width 11 32 bit Although the serial FIFO
29. PMC66 SIO4BXR User s Manual Quad Channel Multi Protocol Serial Controller With Deep Transmit and Receive FIFOs and Multi Protocol Transceivers with PMC Rear IO Connector RS 485 RS 422 V 11 RS423 V 10 RS232 V 28 V 35 RS530 RS530A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL www generalstandards com E mail techsupport generalstandards com Rev 4 General Standards Corporation High Performance Bus Interface Solutions PREFACE Revision History Rev NR Apr 2007 Original rev from PMC SIO4BX manual Rev A Nov 2009 Add memory configuration features and timetag RevB Aug 2010 Update timetag features and ordering options Rev C Mar 2011 Update for PCB RevD LEDs ordering options pinouts Rev4 Mar 2013 Update ordering options pinouts Om Additional copies of this manual or other General Standards Corporation literature may be obtained from General Standards Corporation 8302A Whitesburg Drive Huntsville Alabama 35802 Telephone 256 880 8787 Fax 256 880 8788 URL www generalstandards com The information in this document is subject to change without notice General Standards Corporation makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Although extensive editing and reviews are p
30. SIO4BXR board These clock sources can be most simply viewed in three sections On Board Programmable Clocks IO Connector Clocks and USC Clocks The Programmable Clocks consist of a one on board programmable PLL with postdivider per channel This allows each channel to have a unique programmable clock ProgClk The IO Connector Clocks consist of a Receive Clock RxC a Transmit Clock TxC and a bidirectional Auxiliary Clock AuxC for each channel RxC is always an input and may be used as a clock source for either TxC or the USC Clocks The Auxiliary clock may be set as an input RxAuxC or output TxAuxC TxC is always an output It may be generated from ProgClk inverted ProgClk RxC RxAuxC either of the USC clocks 9 TxC or USC_RxC or forced hi or low for software control The TxC Source is controlled by bits D8 D6 of the Pin Source Register The USC Clocks USC RxC and USC TxC are bidirectional signals Even though the names of these clocks seem to imply a receive clock and a transmit clock both clocks are fully programmable and identical in function either clock may be used for transmit or receive The USC clocks may be sourced from either the USC or the FPGA via the Pin Source register The user must be careful to ensure that both the USC and Pin Source Register are setup to agree If a USC clock is set as an output in the USC it should be programmed as an input in the Pin Source register Likewise if a USC clock source
31. Timestamp Local Offset 0x000C The Timestamp is a new feature added with firmware rev 106 The timestamp will add a 24 bit timestamp value for each data value in the data stream D31 D24 D23 D0 RESERVED Current timestamp value 2 1 5 Channel TX Almost Flags Local Offset 0x0010 0x0020 0x0030 0x0040 The Tx Almost Flag Registers are used to set the Almost Full and Almost Empty Flags for the transmit FIFOs The Almost Full Empty Flags may be read as status bits in the Channel Control Status Register and are also edge triggered interrupt sources to the Interrupt Register D31 16 D15 0 TX Almost Full Flag Value Number of words from FIFO Full when the Almost Full Flag will be asserted i e FIFO contains FIFO Size Almost Full Value words or more TX Almost Empty Flag Value Number of words from FIFO Empty when the Almost Empty Flag will be asserted General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 7 Rev D General Standards Corporation High Performance Bus Interface Solutions 2 1 6 Channel RX Almost Flags Local Offset 0x0014 0x0024 0x0034 0x0044 The Rx Almost Flag Registers are used to set the Almost Full and Almost Empty Flags for the transmit FIFOs The Almost Full Empty Flags may be read as status bits in the Channel Control Status Register and are also edge triggered inter
32. VE FIFOS cccessssecececeeseenceeececsesssaesecececeesenaesesececeessaesececseceseaeseeeecesesesseaeseesesenes 2 1 3 MULTIPROTOCOL 8 2 41 00000000000000000000000000000000000 0 3 1 4 PMC PCLINTERBACB 55 3 1 5 GENERAL PURPOSE 3 1 6 CONNECTOR INTERFACE correire aeoe 3 17 INEW 25 4 3 CHAPTER 2 LOCAL SPACE 8 8 00000 4 2 0 RE 4 2 1 GSC FIRMWARE REGISTERS eek e eee Prae ro ck bee esi use nae ge eiae re E SERE PNE 4 2 1 1 FIRMWARE REVISION LOCAL OFFSET isses enne 5 2 1 2 BOARD CONTROL LOCAL OFFSET 0 0004 6 2 1 3 BOARD STATUS LOCAL OFFSET 0 0008 00200000 0 2222 2 000200000000 7 2 1 4 TIMESTAMP LOCAL OFFSET 0 000 2 0 00120 20 0 2000000000000000000 7 2 1 5 CHANNEL TX ALMOST FLAGS LOCAL OFFSET 0x0010 0x0020 0x0030 0 0040 7 2 1 6 CHANNEL RX ALMOST FLAGS LOCAL OFFSET 0x0014 0x0024 0x0034 0x0044 8 2 1 7
33. al timestamp option RESERVED Rx FIFO Stop on Full 1 If Rx FIFO becomes full stop receiving data disable receiver Demand Mode DMA Channel Single Cycle Disable Demand Mode DMA Channel 1 Request 000 Rx 100 Chl Tx 010 Ch2 Rx 110 Ch2 Tx 001 Ch3 Rx 101 Tx 011 Ch4 Rx 111 Ch4 Tx Demand Mode DMA Channel 0 Single Cycle Disable Demand Mode DMA Channel 0 Request 000 Rx 100 Chl Tx 010 Ch2 Rx 110 Ch2 Tx 001 Ch3 Rx 101 Tx 011 Ch4 Rx 111 2 Ch4 Tx General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 6 Rev D General Standards Corporation High Performance Bus Interface Solutions 2 1 3 Board Status Local Offset 0x0008 The Board Status Register gives general overall status for a board The Board Jumpers 01 00 are physical jumpers which can be used to distinguish between boards if multiple 5104 boards are present a system D31 D9 D8 D7 D6 05 04 D3 D0 D3 D2 D1 DO RESERVED 0 Standard 1 Sync 0 Standard 1 External Timetag Option 0 Standard PCB 1 L3RIO PCB FIFO Size 00 48KLC 01 64K 10 256K Board Jumper J5 Board ID4 0 15 7 15 8 jumper installed Board ID3 0 J5 5 J5 6 jumper installed Board ID2 0 15 3 15 4 jumper installed Board ID1 0 15 1 15 2 jumper installed 2 1 4
34. andards com Some specific setup information may be needed for a driver to interface to the USC Typically the driver will handle the hardware specific characteristics and the end user will only need to be concerned with the driver interface the following hardware setup information may be safely ignored If you aren t sure if you need this information you probably don t 2 2 1 USC Reset The four serial channels are implemented in two Z16C30 Universal Serial Controllers Channels and 2 share USC and Channels 3 and 4 share the other This implementation is important to realize since resetting a Z16C30 chip will have an effect on two serial channels Since the USC chips are typically reset upon initialization this means a Reset USC for Channel 1 will also Reset USC for Channel 2 In addition to making the second reset redundant and unnecessary a Reset USC on one channel may inadvertently adversely affect normal operation on the second channel Therefore care must be exercised when resetting a USC USC Reset bit in the Board Control Register especially in multithreaded environments Since the USC Reset physically resets the USC the first access to the USC following the reset must reinitialize the BCR in the USC To complete the Reset process the user should write data 0x00 to USC base address offset 0x100 or 0x300 to correctly initialize the BCR Following this initial byte write the USC may be accessed normal
35. cations may be customized The following sections describe the hardware setup in detail for common programming issues 3 1 Resets Each serial channel provides control for four unique reset sources a USC Reset a Channel Reset a Transmit FIFO Reset and a Receive FIFO Reset All resets are controlled from the GSC Channel Control Status Registers In addition a Board Reset has been implemented in the Board Control Register This board reset will reset all local registers to their default state as well as reset all FIFOs and USCs all channels will be reset It is important to realize that since each Zilog Z16C30 chip contains two serial channels a USC Reset to either channel will reset the entire chip both channels affected Due to the limitation of a USC Reset to affecting two channels it is recommended that a single USC Channel be Reset via the RTReset bit of the USC Channel Command Address Register CCAR as well as the Channel Reset The FIFO resets allow each individual FIFO Tx and Rx to be reset independently Setting the FIFO reset bit will clear the FIFO immediately 32 FIFOs Deep transmit and receive FIFOs are the key to providing four high speed serial channels without losing data Several features have been implemented to help in managing the on board FIFOs These include FIFO flags Empty Full Almost Empty and Almost Full presented as both real time status bits and interrupt sources and individual FIFO counters to determin
36. ce Bus Interface Solutions D23 Internal Loopback Mode When DCE DTE Mode is enabled Bit D31 1 this bit will automatically loopback the TxC RxC TxD RxD and RTS CTS signals internal to the board D22 RESERVED D21 19 Cable TxD Output Control Allows TxD output to be used as a general purpose output 0 0 X USC TxD 0 0 0 Output 0 0 1 1 Output 1 1 0 0 Differential Biphase Mark 1 0 1 Differential Biphase Space 1 1 0 Level 1 1 1 Differential Biphase Level D18 17 Cable TxAuxC Output Control Defines the Clock Source for the TxAuxC signal to the IO connector TxAuxC Source 0 0 Tristate 0 1 On board Programmable Clock 1 0 Output 0 1 1 Output 1 D16 15 Cable DCD Output Source 0 0 USC_DCD Output USC DCD field D12 D11 must equal 11 0 I RTS Output Rx FIFO Almost Full 1 0 0 Drive low 1 1 Drive Hi D14 13 Cable RTS Output Source 0 0 USC_CTS Output USC CTS field D10 D9 must equal 11 0 1 RTS Output Rx FIFO Almost Full 1 0 0 Drive low 1 1 T Drive Hi General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 13 Rev D General Standards Corporation High Performance Bus Interface Solutions D12 11 USC DCD Direction Setup Defines the DCD direc
37. e exactly the programmed frequency due to the 100ppm 0 01 accuracy of the on board reference General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 36 Rev D General Standards Corporation High Performance Bus Interface Solutions The Internal RAM is defined as follows RAM Address 0 08 0 57 correspond directly to the CY22393 registers 0x00 0x05 Reserved Unused 0x00 0x06 Reserved OxD2 0x07 Reserved 0x08 0x08 Divisor Setup0 0x01 0x09 Divisor Setup1 0x01 Ox0A Divisor Setup0 0 01 OxOB Divisor Setup1 0 01 0 0 Divisor 0 01 0 0 ClkD Divisor 0 01 OxOE Source Select 0x00 OxOF Bank Select 0x50 0x10 Drive Setting 0 55 Ox11 PLL2 Q 0x00 0x12 PLL2 P Lo 0x00 0x13 PLL2 Enable PLL2 P Hi 0x00 0x14 PLL3 Q 0x00 0x15 PLL3 P Lo 0x00 0x16 PLL3 Enable PLL3 P Hi 0x00 0x17 OSC Setting 0x00 0x18 Reserved 0x00 0x19 Reserved 0x00 OxlA Reserved OxE9 Ox1B Reserved 0x08 Ox1C Ox3F Reserved Unused 0x00 0x40 PLL1 Setup0 0x00 0 41 PLL1 P Lo 0 Setup0 0x00 0 41 PLL1 Enable PLL1 P Hi Setup0 0x00 0x43 PLL1 Setupl 0x00 0x44 PLL1 P Lo 0 Setupl 0x00 0x45 PLL1 Enable PLL1 P Hi Setup1 0x00 0x46 PLL1 Setup2 0x00 0x47 P
38. e the exact FIFO fill level DMA of data to from the FIFOs provides for fast and efficient data transfers A single memory address is used to access both transmit and receive FIFOs for each channel Data written to this memory location will be written to the transmit FIFO and data read from this location retrieves data from the receive FIFO Individual resets for the FIFOs are also provided in the Channel Control Status Register 3 2 1 FIFO Flags Four FIFO flags are present from each on board FIFO FIFO Empty FIFO Full FIFO Almost Empty and FIFO Almost Full These flags may be checked at any time from the Channel Control Status Register Note these flags are presented as active low signals 0 signifies condition is true The Empty and Full flags are asserted when the FIFO is empty or full respectively The Almost Empty and Almost Full flags are software programmable such that they may be asserted at any desired fill level This may be useful in determining when a data transfer is complete or to provide an indicator that the FIFO is in danger of overflowing and needs immediate service General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 21 Rev D General Standards Corporation High Performance Bus Interface Solutions The Almost Flag value represents the number of bytes from each respective end of the FIFO The Al
39. each register DO IRQO D1 IRQ etc All FIFO interrupts are edge triggered active high This means that an interrupt will be asserted assuming it is enabled when a FIFO Flag transitions from FALSE to TRUE rising edge triggered or TRUE to FALSE falling edge For example If Tx FIFO Empty Interrupt is set for Rising Edge Triggered the interrupt will occur when the FIFO transitions from NOT EMPTY to EMPTY Likewise if Tx FIFO Empty Interrupt is set as Falling Edge Triggered the interrupt will occur when the FIFO transitions from EMPTY to NOT EMPTY All Interrupt Sources share a single interrupt request back to the PCI9056 PLX chip Likewise all USC interrupt sources share a single interrupt request back to the interrupt controller and must be further qualified in the USC chip General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 10 Rev D General Standards Corporation High Performance Bus Interface Solutions 2 1 10 1 Interrupt Control Local Offset 0x0060 The Interrupt Control register individually enables each interrupt source A 1 enables each interrupt source a 0 disables An interrupt source must be enabled for an interrupt to be generated 2 1 10 2 Interrupt Status Clear Local Offset 0x0064 The Interrupt Status Register shows the status of each respective interrupt source If an interrupt s
40. erformed before release to ECO control General Standards Corporation assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information contained in this document General Standards Corporation does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent right of any rights of others General Standards Corporation assumes no responsibility resulting from omissions or errors in this manual or from the use of information contained herein General Standards Corporation reserves the right to make any changes without notice to this product to improve reliability performance function or design All rights reserved No parts of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corporation Copyright 2013 General Standards Corporation General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 800 653 9970 FAX 256 880 8788 Email salest generalstandards com i Rev 4 General Standards Corporation High Performance Bus Interface Solutions RELATED PUBLICATIONS ZILOG Z16C30 USC User s Manual ZILOG Z16C30 USC Product Specifications Databook ZILOG Inc 210 East Hacienda Ave Campbell CA 95008 6600 408 370 8000 http www zilog com
41. ernal SRAM bug adjust FIFO read timing enhance Clock Programming General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 38 Rev D General Standards Corporation High Performance Bus Interface Solutions 0 18 Speed up SRAM Sync 9056 releases 0 19 Add Rx Stop on Full to Ch Ctrl Feature Register Local Offset D31 23 RESERVED D22 1 Rx Stop on Full in Ch Ctrl D21 1 SRAM Debug D20 1 No Rx Status byte std only D19 D18 Timestamp 01 single external clock 10 single internal clock D17 D16 FPGA Reprogram field 01 Present 00 Not Present D15 D14 Configurable FIFO space 01 Rx Tx select Up to 32k deep FIFOs D13 1 FIFO Test Bit D12 1 FW Type Reg D11 D8 FW Feature Level Set at common code level 0x01 RS232 support Pin Source Change 0x02 Multi Protocol support 0x03 Common Internal External FIFO Support 0x04 FIFO Latched Underrun Overrun Level 0x05 Demand mode DMA Single Cycle for Tx 0x06 Single Cycle Dis updated Pin Src 0x07 Rx Underrun Only Reset Status 0x08 Clock to 50Hz with 10Hz resolution 0x09 No Legacy Support No Clock Control Register 0x0A Falling Int fix D7 1 DMA Single Cycle Disable D6 1 Board Reset FIFO present bits D5 1 FIFO Size Counters present D4 1 FW ID complies with this standard D3 D0 Clock Oscillator 0x0 Fixed 0
42. errupt Level Hi NONE IRQ8 Channel 3 Sync Detected Rising Edge NONE IRQ9 Channel 3 Tx FIFO Almost Empty Rising Edge Falling Edge 10 Channel 3 Rx FIFO Almost Full Rising Edge Falling Edge IRQI1 Channel 3 USC Interrupt Level Hi NONE IRQ12 Channel 4 Sync Detected Rising Edge NONE IRQ13 Channel 4 Tx FIFO Almost Empty Rising Edge Falling Edge 14 Channel 4 Rx FIFO Almost Full Rising Edge Falling Edge 15 Channel 4 USC Interrupt Level Hi NONE 16 Channel 1 Tx FIFO Empty Rising Edge Falling Edge 17 Channel 1 Tx FIFO Full Rising Edge Falling Edge 18 Channel 1 Rx FIFO Empty Rising Edge Falling Edge IRQI9 Channel 1 Rx FIFO Full Rising Edge Falling Edge IRQ20 Channel 2 Tx FIFO Empty Rising Edge Falling Edge IRQ21 Channel 2 Tx FIFO Full Rising Edge Falling Edge IRQ22 Channel 2 Rx FIFO Empty Rising Edge Falling Edge IRQ23 Channel 2 Rx FIFO Full Rising Edge Falling Edge IRQ24 Channel 3 Tx FIFO Empty Rising Edge Falling Edge IRQ25 Channel 3 Tx FIFO Full Rising Edge Falling Edge IRQ26 Channel 3 Rx FIFO Empty Rising Edge Falling Edge IRQ27 Channel 3 Rx FIFO Full Rising Edge Falling Edge IRQ28 Channel 4 Tx FIFO Empty Rising Edge Falling Edge IRQ29 Channel 4 Tx FIFO Full Rising Edge Falling Edge IRQ30 Channel 4 Rx FIFO Empty Rising Edge Falling Edge IRQ31 Channel 4 Rx FIFO Full Rising Edge Falling Edge For all interrupt registers the IRQ source IRQ31 IRQO will correspond to the respective data bit 031 0 of
43. et all the GSC registers and FIFOs to their default state Interrupt control is also shared among all registers although local bits are segregated by channel The device driver should take care of appropriately handling the inter mixed channel interrupts and pass them on to the application appropriately General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 22 Rev D General Standards Corporation High Performance Bus Interface Solutions 3 4 Programmable Oscillator Programmable Clocks Two On Board Programmable Oscillators provide each channel with a unique programmable clock source using Cypress Semiconductor CY22393 Programmable Clock generators In order to program the oscillator it is necessary to calculate and program values for different clock frequencies General Standards has developed routines to calculate the necessary values for a given setup and program the clock generator As these routines are written in C ona windows based PC they may need to be ported for user specific applications Contact GSC for help in porting these routines The default clock configuration at power up for the programmable clock on all channels is 20MHz See Appendix A for more detailed information concerning programming the on board clock frequencies 3 5 Clock Setup Figure 3 1 shows the relationship of the various clock sources on the
44. f data which can be safely transferred without over running or under running the FIFOs D31 D16 Number of words in Rx FIFO D15 D0 Number of words in Tx FIFO 2 1 15 FIFO Size Register Local Offset 0 00 0 0x00E4 0 00 8 0 00 The FIFO Size Registers display the sizes of the installed data FIFOs This value is calculated at power up This value along with the FIFO Count Registers may be used to determine the amount of data which can be safely transferred without over running or under running the FIFOs D31 D16 Size of installed Rx FIFO D15 D0 Size of installed Tx FIFO 2 1 16 FW Type ID Register Local Offset 0 00 8 This register allows boards to change functionality on each channel Currently a channel can only be defined as Standard or Sync For SIO4BX Sync information please refer to the PCle SIO4BX2 SYNC manual D31 D24 Channel 4 FW Type gt 01 Standard 04 Sync D23 D16 Channel 3 FW Type gt 01 Standard 04 Sync D15 D8 Channel 2 FW Type gt 01 Standard 04 Sync D7 D0 Channel 1 FW Type gt 01 Standard 04 Sync General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 16 Rev D General Standards Corporation High Performance Bus Interface Solutions 2 1 17 Features Register Local Offset 0x00FC The Features Register allows software to account for added features in
45. figuration This allows for either full duplex or half duplex configurations 1 4 PMC PCI Interface The control interface to the SIO4BXR is through the PMC PCI interface An industry standard PCI9056 bridge chip from PLX Technology is used to implement PCI Specification 2 2 The PCI9056 provides the 32bit 66MHz 264MBit sec interface between the PCI bus and the Local 32 bit bus It also provides for high speed DMA transfers to efficiently move data to and from the board 1 5 General Purpose IO Since some signals may not be used in all applications the SIO4BXR provides the flexibility to remap unused signals to be used as general purpose IO For example this would allow support for an application requiring DTR DSR signals to be implemented on an unused DCD or TxAuxC signals This also allows signals from unused channels to be available as general purpose IO 1 6 Connector Interface The SIO4BXR provides a user IO interface through a front side card edge connector All four serial channels interface through this high density 68 pin SCSI 3 type connector and are grouped to simplify separating the cable into four distinct serial connectors Standard cables are available from General Standards in various lengths to adapt the single 68 pin SCSI 3 connector into four DB25 connectors one per channel A standard cable is also available with a single 68 pin SCSI 3 connector on one end and open on the other This allows the user to add a custom con
46. he receive FIFO This information should help streamline data transfers by eliminating the need to continuously check empty and full flags yet still allow larger data blocks to be transferred 3 2 3 FIFO Size In some applications 4Kbyte FIFOs may be all that is required to implement a serial interface This typically includes baud rates slower than 500kbps or applications where the transfer size is limited to less than 4k bytes at a time and an effective throughput rate less than 500kpbs For these applications a PMC66 SIO4BXR 48KLC board should be adequate For faster applications deeper external FIFOs are required to ensure no data will be lost Please contact General Standards if you have any questions about determining which FIFO size may be necessary for a specific application 3 3 Board vs Channel Registers Since four serial channels are implemented on a single board some registers apply to the entire board while others are unique to each channel It is intended that each channel can act independently but the user must keep in mind that certain accesses will affect the entire board Typically the driver will adequately handle keeping board and channel interfaces separate However the user must also be mindful that direct access to certain registers will affect the entire board not just a specific channel The Board Control and Board Status registers provide board level controls Fundamentally a board reset will do just that res
47. ich denotes all interrupt sources as edge triggered The Interrupt Hi Lo Register defines each interrupt source as rising edge or falling edge For example a rising edge of the TX Empty source will generate an interrupt when the TX FIFO becomes empty Defining the source as falling edge will trigger an interrupt when the TX FIFO becomes NOT Empty General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email sales generalstandards com 11 Rev D General Standards Corporation High Performance Bus Interface Solutions 2 1 11 Channel Pin Source Local Offset 0x0080 0x0084 0x0088 0x008C The Channel Pin Source Register configures the Output source for the Clocks Data RTS and DCD outputs 31 30 29 28 27 26 25 24 Transceiver Termination Loopback DCE DTE Transceiver Protocol Mode Enable Disable Enable Mode 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 716 51413 2 1 0 TxD Unused DCD RTS USC DCD USC CTS TxC USC RXC USC TxC LB Source Source Source Source Direction Direction Source Source Source Pin Source Register D31 Cable Transceiver Enable Setting this bit turns on the cable transceivers If this bit is cleared the transceivers are tristated D30 Termination Disable For RS422 RS485 RS530 and V 35 the
48. ister Block Description 0x0000 0 0000 GSC Firmware Registers 0x0100 0x013F 0x0100 Channel 1 USC Registers 0x0140 0 01 Reserved 0x0200 0x023F 0x0200 Channel 2 USC Registers 0x0240 0 02 Reserved 0x0300 0x033F 0x0300 Channel 3 USC Registers 0x0340 Reserved 0x0400 0x043F 0x0400 Channel 4 USC Registers The GSC Firmware Registers are detailed in Section 2 1 The USC Registers are briefly touched on in Section 2 2 of this manual but are described in much greater detail in the Zilog Z16C30 Users Manuals 2 1 GSC Firmware Registers The GSC Firmware Registers provide the primary control status for the SIOABXR board The following table shows the GSC Firmware Registers General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 4 Rev D General Standards Corporation High Performance Bus Interface Solutions Ox0070 0x00C RESERVED Ox00B0 0x00cC_ RESERVD Ox00F0 0x00F4 RESERVD 21 1 Firmware Revision Local Offset 0x0000 The Firmware ID register provides version information about the firmware on the board This is useful for technical support to identify the firmware version See Appendix B for more detailed information D31 16 HW Board Rev E225
49. lows an interrupt to be generated when the received data matches the Sync Detect Byte D31 8 RESERVED D7 0 Channel Sync Detect Byte If the data being loaded into the Receive FIFO matches this data byte an interrupt request Channel Sync Detect IRQ will be generated The interrupt source must be enabled in the Interrupt Control Register in order for an interrupt to be generated General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email sales generalstandards com 9 Rev D General Standards Corporation High Performance Bus Interface Solutions 2 1 10 Interrupt Registers There are 32 on board interrupt sources in addition to USC interrupts and PLX interrupts which may be individually enabled Four interrupt registers control the on board interrupts Interrupt Control Interrupt Status Interrupt Edge Level and Interrupt Hi Lo The 32 Interrupt sources are 0 Channel 1 Sync Detected Rising Edge NONE IRQI Channel 1 Tx FIFO Almost Empty Rising Edge Falling Edge IRQ2 Channel 1 Rx FIFO Almost Full Rising Edge Falling Edge IRQ3 Channel 1 USC Interrupt Level Hi NONE IRQ4 Channel 2 Sync Detected Rising Edge NONE IRQ5 Channel 2 Tx FIFO Almost Empty Rising Edge Falling Edge IRQ6 Channel 2 Rx FIFO Almost Full Rising Edge Falling Edge IRQ7 Channel 2 USC Int
50. ly Due to the ability for a USC Reset to affect two channels it is recommended that a single USC Channel be Reset via the RTReset bit of the USC Channel Command Address Register CACR 2 2 2 8 Bit USC Register Access As the USC has a configurable bus interface the USC must be set to match the 8 bit non multiplex interface implementation of the SIO4BXR This setup information must be programmed into the USC Bus Configuration Register BCR upon initial power up and following every hardware reset of the USC The BCR is accessible only following a USC hardware reset the first write to the USC following a USC Reset programs the BCR Even though the Zilog manual states the BCR has no specific address the driver must use the channel USC base address 0 100 for Ch 1 amp Ch 2 0x300 for Ch 3 amp Ch 4 as the BCR address Failure to do so may result in improper setup Since the user interface to the USC is an 8 bit interface the software only needs to set the lower byte to 0x00 hardware implementation will program the upper byte of the BCR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 18 Rev D General Standards Corporation High Performance Bus Interface Solutions 2 2 3 USC Data Transfer Although the Z16C30 USC contains 32 byte internal FIFOs for data transfer these are typically not used on the SIO4BXR
51. most Empty value represents the number of bytes from empty and the Almost Full value represents the number of bytes from full NOT the number of bytes from empty For example the default value of 0007 0007 in the FIFO Almost Register means that the Almost Empty Flag will indicate when the FIFO holds 7 bytes or fewer It will transition as the 8 byte is read or written In this example the Almost Full Flag will indicate that the FIFO contains FIFO Size 7 bytes or more For the standard 32Kbyte FIFO an Almost Full value of 7 will cause the Almost Full flag to be asserted when the FIFO contains 32761 32k 7 or more bytes of data The values placed in the FIFO Almost Registers take effect immediately but should be set while the FIFO is empty or the FIFO should be reset following the change Note that this is a little different than the method for FIFO Flag programming which has previously been implemented on 5104 boards No FIFO programming delay is necessary 3 2 2 FIFO Counters The FIFO Size and FIFO count registers can be used to determine the exact amount of data in a FIFO as well as the amount of free space remaining in a FIFO The size of each FIFO is auto detected following a board reset Real time FIFO counters report the exact number of data words currently in each FIFO By utilizing this information the user can determine the exact amount of data which can safely be transferred to the transmit FIFOs or transferred from t
52. nector or connect to a terminal block General Standards will also work with customers to fabricate custom cables Consult factory for details on custom cables 1 7 New Features The PMC66 SIO4BXR has been enhanced with several new features These include improved receive data status recording timestamping of data flexible FIFO memory allocation sync standard channel select and channel reset General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 3 Rev D General Standards Corporation High Performance Bus Interface Solutions CHAPTER 2 LOCAL SPACE REGISTERS 2 0 Register Map The SIO4BXR is accessed through three sets of registers PCI Registers USC Registers and GSC Firmware Registers The GSC Firmware Registers and USC Registers are referred to as Local Space Registers and are described below The PCI registers are discussed in Chapter 3 The Local Space Registers are divided into two distinct functional register blocks the GSC Firmware Registers and the USC Registers The GSC Firmware Registers perform the custom board control functions while the USC Registers map the Zilog Z16C30 registers into local address space The register block for each USC channel is accessed at a unique address range The table below shows the address mapping for the local space registers Local Address Range Base Address Offset Reg
53. ntinue to from the IO interface independent of PCI interface transfers and software overhead The required FIFO size may depend on several factors including data transfer size required throughput rate and the software overhead which will also vary based on OS Generally faster baud rates greater than 500kbps will require deeper FIFOs Deeper FIFOs help ensure no data is lost for critical systems The SIO4BXR provides access to complete FIFO status to optimize data transfers In addition to Empty and Full indicators each FIFO has a programmable Almost Empty Flag and a programmable Almost Full Flag These FIFO flags may be used as interrupt sources to monitor FIFO fill levels In addition real time FIFO counters showing the exact number of words in the FIFO are also provided for each FIFO By utilizing these FIFO counters data transfers can be optimized to efficiently send and receive data General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 2 Rev D General Standards Corporation High Performance Bus Interface Solutions 13 Miultiprotocol Transceivers The SIO4BXR data is transferred over the user interface using high speed multiprotocol transceivers These multiprotocol transceivers are software selectable as RS422 RS485 RS423 or RS232 on a per channel basis Each channel direction may also be configured as DTE or DCE con
54. or Jumper J5 location J5 Jumper 1 2 Board ID 1 Board ID 1 in Board Status Register DO 3 4 Board ID 2 Board ID 2 in Board Status Register D1 5 6 Board ID 3 Board ID 3 in Board Status Register D2 7 8 Board ID 4 Board ID 4 in Board Status Register D3 5 2 Termination Resistors The PMC66 SIO4BXR transceivers have built in termination resistors of for RS 422 and V 35 modes The built in RS 422 termination is a 120 Ohm parallel termination only on the high speed receiver signals RxD RxAuxC and DCD The built in V 35 termination is a Y network of 51 124 Ohms If desired the internal termination resistors may be disabled by setting bit D30 in the Pin Source Register The board is designed with socketed external parallel termination if a different value than the internal termination is required The external termination resistors 8 pin SIPs There 8 termination SIPs RP6 RP7 2 RP13 RP17 RP18 RP23 and RP24 The external parallel resistors are for RS422 RS485 termination only no provision is made for external V 35 termination resistors Refer to Figure 5 1 for resistor pack locations Please contact quotes generalstandards com if a different termination value is required 5 3 LEDs Eleven green LEDs D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 are accessible via software Refer to Figure 5 2 for these LED locations LED 2 is controlled by Board Control Register D24 LED D
55. ource is enabled in the Interrupt Control Register a 1 in the Interrupt Status Register indicates the respective interrupt has occurred The interrupt source will remain latched until the interrupt is cleared either by writing to the Interrupt Status Clear Register with a 1 in the respective interrupt bit position or the interrupt is disabled in the Interrupt Control register If an interrupt source is not asserted or the interrupt is not enabled writing a 1 to that bit in the Interrupt Status Clear Register will have no effect on the interrupt If the interrupt source is a level triggered interrupt USC interrupt the interrupt status may still be 1 even if the interrupt is disabled This indicates the interrupt condition is true regardless of whether the interrupt is enabled Likewise if a level interrupt is enabled and the interrupt source is true the interrupt status will be reasserted immediately after clearing the interrupt and an additional interrupt will be requested 2 1 10 3 Interrupt Edge Level Local Offset 0x0068 The Interrupt Edge Register is an information only read only register This register can be used by a generic driver to determine if the interrupt source is edge or level triggered Only the USC interrupts are level triggered All other interrupt sources on the SIO4BXR are edge triggered 2 1 10 4 Interrupt Hi Lo Local Offset 0x006C The Interrupt Edge Register is an information only register wh
56. r and lower bytes of each register independently The odd address byte will access the upper byte of each register D15 D8 and the even address byte will access the lower byte D7 D0 Each USC register must be accessed independently as a byte access the software cannot perform word or long word accesses to the USC registers The USC register map is provided below The Channel Offset Address depicted is from the Channel Base Address Ch 1 Base Address 0x100 Ch 2 Base Address 0x200 Ch 3 Base Address 0x300 Ch 4 Base Address 0x400 For further programming details please refer to the Zilog Z16C30 data books Channel Offset Access Register Name Address 020 RDR Receive DataRegister TDR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 20 Rev D General Standards Corporation High Performance Bus Interface Solutions CHAPTER 3 PROGRAMMING 3 0 Introduction This section addresses common programming questions when developing an application for the SIO4 General Standards has developed software libraries to simplify application development These libraries handle many of the low level issues described below including Resets FIFO programming and DMA These libraries may default the board to a standard configuration one used by most applications but still provide low level access so appli
57. r has occurred D2 Clock Measurement complete 0 Clock Measurement in progress D7 D3 Reserved Unused D31 D8 If Command Word D6 0 Measured Channel Clock Value If Command Word D6 1 Control Word D23 D0 Channel Clock Post Dividers The Control Word defines 4 fields for Channel Clock Post dividers These post dividers will further divide down the input clock from the programmable oscillator to provide for slow baud rates Each 4 bit field will allow a post divider of 2 n For example if the post divider value 0 the input clock is not post divided A value of 2 will provide a post divide of 4 2 2 This will allow for a post divide value of up to 32768 2 15 for each input clock Bit D7 of the Control word qualifies writes to the post divide registers This allows other bits in the command register to be set while the post divide values are maintained Channel Clock Measurement The Control Word defines 4 bits which will select one of the 4 channel clocks input clock post divide for a measurement This will allow the user feedback as to whether the programmable oscillator was programmed correctly To measure a clock select the clock to measure in the Control word and also clear Bit D6 to allow for readback of the result Read back the Status Word until D2 is set Status Word D31 D8 should contain a value representing 1 10 the measured clock frequency Value 10 Measured Frequency in MHz Keep in mind that this value will not b
58. ransmit signals TxC TXD RTS and the receive signals will use these same signals as the receive inputs Since signals are transmitted and received through the transceivers this mode allows the setup to be verified including signal polarity without any external connections Since external signals could interfere with loopback operation all cables should be disconnected when running in external loopback mode An Internal Loopback Mode is also provided which loops back on the same channel internal to the board This provides a loopback method which does not depend on DTE DCE mode or signal polarity This can remove cable transceiver and signal setup issues to aid in debugging If the Cable Transceivers are enabled the transmit data will still appear on the appropriate transmit pins based on DTE DCE Mode setting The Pin Status register will not reflect internally looped back signals only signals to from the transceivers 3 9 General Purpose IO Unused signals at the cable may be used for general purpose IO The Pin Source and Pin Status Registers provide for simple IO control of all the cable interface signals For outputs the output value is set using the appropriate field in the Pin Source Register All inputs can be read via the Pin Status register 3 10 Interrupts The SIO4BXR has a number of interrupt sources which are passed to the host CPU via the PCI Interrupt A Since there is only one physical interrupt source the interrupts pass th
59. rface 0 33MHz PCI bus interface D28 1 64 bit PCI bus interface 0 32 bit bus interface D27 D24 Form Factor 0 Reserved 1 PCI 2 3 4 PC104P D23 D20 HW Board sub field of form factor 0 PMC SIO4AR 1 PMC SIO4BX 2 PMC66 SIO4BXR D19 D16 HW Board Rev lowest rev for firmware version 0 5 015 8 Firmware ID 0 01 Std Firmware default 0x04 Sync Firmware default D7 0 Firmware Revision XX Firmware Version 0x00 Initial release Internal Only 0x01 Add RS423 support Internal Only 0x02 Add 4 PLL Internal Only 0x03 Falling Int fix add LED control link in 4 PLL Internal Only 0x04 HW Rev C Release 0x05 HW Rev D Release 0x06 Add timestamp 9 FIFO bit Timestamp release 0x07 Allow 32 bit FIFO access Timestamp release 0x08 Add biphase encoding Add compile option for Rev C D Timestamp release 0x09 Fix external RxFIFO always 256k Timestamp release 0x10 Add status to RxFIFO always 256k Timestamp release 0x11 Fix Ext FIFO writes Timestamp Release 0x12 Sync timetag with std release Begin adding sync code Remove Ext Timestamp Clock 0x13 Add sync Add L3RIO support Force Xcvr mode reset when channel reset 0x14 Update Ext FIFO counters to support lt 32K FIFOs Add more sync code 0 15 Add Channel reset SRAM pipeline Env Delay Sync PinSrcB Reg Sync fix Ch4 Config FIFO 0x16 Fix Rx Sync 0x17 Ext
60. rough a number of levels to get multiplexed onto this single interrupt The interrupt originates in the PCI9056 PCI Bridge which combines the internal PLX interrupt sources DMA with the local space interrupt The driver will typically take care of setting up and handling the 19056 interrupts The single Local Interrupt is made up of the interrupt sources described in Section 2 1 10 In addition the Zilog USC contains a number of interrupt sources which are combined into a single Local Interrupt The user should be aware that interrupts must be enabled at each level for an interrupt to occur For example if a USC interrupt is used it must be setup and enabled in the USC enabled in the GSC Firmware Interrupt Control Register and enabled in the PCI9056 In addition the interrupt must be acknowledged and or cleared at each level following the interrupt 311 PCI DMA The PCI DMA functionality allows data to be transferred between host memory and the SIO4BXR onboard FIFOs with the least amount of CPU overhead The PCI9056 bridge chip handles all PCI DMA functions and the device driver should handle the details of the DMA transfer Note DMA refers to the transfer of Data from the on board FIFOs over the PCI bus This should not be confused with the DMA mode of the USC transfer of data between the USC and the on board FIFOs This On Board DMA is setup by the driver and should always be enabled There are two PCI DMA modes Demand Mode
61. rupt sources to the Interrupt Register D31 16 RX Almost Full Flag Value Number of words from FIFO Full when the Almost Full Flag will be asserted i e FIFO contains FIFO Size Almost Full Value words or more D15 0 RX Almost Empty Flag Value Number of words from FIFO Empty when the Almost Empty Flag will be asserted 2 1 7 Channel FIFO Local Offset 0x0018 0 0028 0x0038 0x0048 The Channel FIFO Register passes serial data to from the serial controller The same register is used to access both the Transmit FIFO writes and Receive FIFO reads D31 8 RESERVED D7 0 Channel FIFO Data 2 1 8 Channel Control Status Local Offset 0x001C 0x002C 0x003C 0x004C The Channel Control Status Register provides the reset functions and data transceiver enable controls and the FIFO Flag status for each channel D31 24 RESERVED D23 20 LED Control Each Channel controls 2 LEDs on the back of the PCB See Section 5 3 for more detailed information about the LEDs D19 Rx Stop on Full D18 8 Channel Status Bits 018 Rx FIFO Underflow D17 Tx FIFO Overflow Latched D16 Rx FIFO Overflow Latched 1 Rx Data was lost due to Rx Overflow Note This bit is latched Write D16 1 to clear D15 Rx FIFO Full Flag Lo 0 Rx FIFO Full 014 Rx FIFO Almost Full Flag Lo 0 Rx FIFO Almost Full D13 Rx FIFO Almost Empty Flag Lo 0 Rx FIFO Almost Empty D12 Rx FIFO Empty Flag Lo 0 Rx FIFO Empty Tx FIFO Full Flag Lo 0 Tx FIFO Full
62. s include Asynchronous MonoSync Bisync SDLC HDLC e Multiprotocol Transceivers support RS422 V 11 RS485 RS423 10 RS232 V 28 V 35 and RS530 e Parity and CRC detection capability e Four Programmable Oscillators provide increased flexibility for exact Baud Rate Clock generation SCSI 3 type 68 pin front edge I O Connector with optional cable adapter to four DB25 connectors e PMC 64 pin Rear IO Connection P4 e Fight signals per channel configurable as either DTE DCE configuration 3 Serial Clocks 2 Serial Data signals Clear To Send CTS Ready To Send RTS and Data Carrier Detect DCD Unused signals may be reconfigured as general purpose IO Fast RS422 RS485 Differential Cable Transceivers Provide Data Rate up to 10Mbps RS423 and RS232 Cable Transceivers Provide Data Rate up to 230kbps Industry Standard Zilog Z16C30 Multi Protocol Universal Serial Controllers USC Dual PCI DMA Engine to speed transfers and minimize host I O overhead A variety of device drivers are available including VxWorks WinNT Win2k WinXP Linux and Labview General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 1 Rev D General Standards Corporation High Performance Bus Interface Solutions
63. s only contain 8 bits of 00 8 bit data the register access is still a 32bit access It is possible to pack the data by setting the Local Bus Width to 8 but this is only guaranteed to work with Non Demand Mode DMA D5 2 Internal Wait States 0000 Unused D6 Ready Input Enable 1 Enabled D7 Bterm Input Enabled 0 Unused D8 Local Burst Enable 1 Supported Bursting allows fast back to back accesses to the FIFOs to speed throughput D9 Chaining Enable Scatter X DMA source addr destination addr and byte Gather DMA count are loaded from memory in PCI Space D10 Done Interrupt Enable X DMA Done Interrupt D11 Local Addressing Mode 1 No Increment DMA to from FIFOs only D12 Demand Mode Enable X Demand Mode DMA is supported for FIFO accesses on the SIO4BXR See Section 3 3 D13 Write amp Invalidate Mode X D14 DMA EOT Enable 0 Unused D15 DMA Stop Data Transfer 0 BLAST Enable terminates DMA D16 DMA Clear Count Mode 0 Unused D17 DMA Channel Interrupt X Select D31 18 Reserved 0 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 29 Rev D General Standards Corporation High Performance Bus Interface Solutions CHAPTER 5 HARDWARE CONFIGURATION 5 0 Board Layout The following figure is a drawing of the physical components of the PMC66 SIO4BXR Multi
64. s the standard transfer method General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email sales generalstandards com 27 Rev D General Standards Corporation High Performance Bus Interface Solutions CHAPTER 4 PCI INTERFACE 40 PCI Interface Registers The PMC PCI interface is handled by PCI9056 I O Accelerator from PLX Technology The PCI interface is compliant with the 5V 66MHz 32 bit PCI Specification 2 2 The PCI9056 provides dual DMA controllers for fast data transfers to and from the on board FIFOs Fast DMA burst accesses provide for a maximum burst throughput of 264MB s to the PCI interface To reduce CPU overhead during DMA transfers the controller also implements Chained Scatter Gather DMA as well as Demand Mode DMA Since many features of the PCI9056 are not utilized in this design it is beyond the scope of this document to duplicate the PCI9056 User s Manual Only those features which will clarify areas specific to the PMC66 SIO4BXR are detailed here Please refer to the PCI9056 User s Manual See Related Publications for more detailed information Note that the BIOS configuration and software driver will handle most of the PCI9056 interface Unless the user is writing a device driver the details of this PCI Interface Chapter may be skipped 4 1 PCI Registers The PLX 9056 contains many registers many of which have no effect
65. tal Register Provides access to the CLOCK pointed to by the RAM Addr Register 0x00A C RAM Data2 Register Provides access to the CLOCK 2 pointed to by the RAM Addr Register 0x00A8 Programmable Osc Control Status Register Provides control to write the contents of the CLOCK RAM to the CY22393 and setup additional post dividers for the input clocks Control Word Write Only DO Program Oscillator 1 Program contents of CLOCK RAM to CY22393 Automatically resets to 0 D1 Measure Channel 1 Clock D2 Measure Channel 2 Clock General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 35 Rev D General Standards Corporation High Performance Bus Interface Solutions D3 Measure Channel 3 Clock D4 Measure Channel 4 Clock D5 Reserved Unused D6 Status Word Readback Control 0 gt Status Word D31 D8 Measured Channel Value 1 gt Status Word D31 D8 Control Word D23 D0 D7 Post divider set 0 Ignore D23 D8 during Command Word Write 1 Set Channel Post Dividers from D23 D8 during Command Word Write D11 D8 Channel 1 Post Divider D15 D12 Channel 2 Post Divider D19 D16 Channel 3 Post Divider D23 D20 Channel 4 Post Divider D31 D24 Reserved Unused Status Word Read Only DO Program Oscillator Done 0 Oscillator Programming in progress D1 Program Oscillator Error 1 Oscillator Programming Erro
66. tion for the USC DCD pin Notes If DCD is used as GPIO set this field to 00 and set Pin Source Register D16 D15 for output Pin Status Register D3 for input e If set the DCD direction must agree with the USC DCD setup USC IOCR D13 12 to ensure proper operation e If field set to 117 Output DCD Source field D16 15 must be set to 00 DCD Buffer Direction USC IOCR D13 D12 Setup 0 0 Buffer Disabled XX Don t Care 0 I Input from IO Connector DCD 0 Input 1 0 Reserved XX Don t Care 1 1 Output to IO Connector 1X Output D10 9 USC CTS Direction Setup Defines the CTS direction for the USC CTS pin Notes e If CTS is used as GPIO set this field to 00 and set Pin Source Register D14 D13 for output Pin Status Register D2 for input e If set the CTS direction must agree with the USC CTS setup USC D15 14 to ensure proper operation Iffield set to 117 Output RTS Source field D14 13 must be set to 00 D10 D9 CTS Buffer Direction USC IOCR D15 D14 Setup 0 0 Tristate XX Don t Care 0 1 Input from IO Connector CTS OX Input 1 0 Reserved XX Don t Care 1 1 Output to IO Connector 1X Output D8 6 Cable TxC Source Defines the Clock Source for the TxC signal to the IO connector 0 0 0 1 0 0 1 Inverted Prog Clock 0 1 0 0 Drive Line Lo 0 1 1 17 Drive Line Hi
67. urce Register Since the FPGA will source both USC clocks they must be programmed as inputs in the USC I O Control Register General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 24 Rev D General Standards Corporation High Performance Bus Interface Solutions The preceding suggestions should work for most applications The default Pin Source Register value should set the clocks to work with both scenarios USC TxC pin Programmable Clock USC RxC Pin Cable RxC Cable TxC Programmable Clock For async use USC is input clock 3 6 Multiprotocol Transceiver Control The SIO4BXR has multiprotocol transceivers which allow RS422 RS485 RS423 RS232 RS530 V 35 and RS422 RS423 Mixed mode The Mode is set by the Protocol Mode field in the Pin Source Register Mow RS 422 RS 485 RS 423 RS 232 RS 530 RS 530A V 35 RS 423 remaps the TxC RxC and TxD RxD signals on the user connector See Connector pinout 37 DCE DTE Mode As all signals are bidirectional the DCE or DTE mode will set the direction for each signal For the transceivers to be configured as either DTE or DCE set the DCE DTE Enable bit in the Pin Source register D31 The following table gives the input output configuration for each signal The DCD and AuxC direction is set in the Pin Source register
68. vers and pricing 6 3 Custom Applications Although the SIO4BXR board provides extensive flexibility to accommodate most user applications a user application may require modifications to conform to a specialized user interface General Standards Corporation has worked with many customers to provide customized versions based on the SIO4BXR boards Please consult our sales department with your specifications to inquire about a custom application General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 34 Rev D General Standards Corporation High Performance Bus Interface Solutions APPENDIX A PROGRAMMABLE OSCILLATOR PROGRAMMING The 4 on baord clock frequencies are supplies via two Cypress Semiconductor CY22393 Programmable Clock Generatosr In order to change the clock frequencies this chip must be reprogrammed This document supplies the information necessary to reprogram the on board clock frequencies GSC has developed routines to calculate and program the on board oscillator for a given set of frequencies so it should not be necessary for the user need the following information it is provided for documentation purposes Please contact GSC for help in setting up the on board oscillator The CY22393 contains several internal address which contain the programming information GSC has mirrored this data internal to the F
69. xAuxC Input 000 Input 1 1 0 RESERVED e 1 1 1 Driven from USC IOCR D5 D3 000 Output 2 1 12 Channel Pin Status Local Offset 0x0090 0x0094 0x0098 0x009C Unused inputs may be utilized as general purpose input signals The Channel Pin Status Register allows the input state of all the IO pins to be monitored Output signals as well as inputs are included to aid in debug operation D31 D10 RESERVED D9 TxAuxC Output D8 RxAuxC Input D7 DCD Output D6 RTS Output D5 TxD Output D4 TxC Output D3 DCD Input D2 CTS Input D1 RxD Input DO RxC Input General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 15 Rev D General Standards Corporation High Performance Bus Interface Solutions 2 1 13 Programmable Clock Registers Local Offset 0x00A0 0x00A4 0x00A8 The Programmable Clock Registers allow the user to program the on board programmable oscillator and configure the channel clock post dividers As GSC should provide software routines to program the clock the user should have no need to access these registers See section 3 6 for more information 2 1 14 FIFO Count Register Local Offset 0x00D0 0x00D4 0x00D8 0x00DC The FIFO Count Registers display the current number of words in each FIFO This value along with the FIFO Size Registers may be used to determine the amount o

PMC66-SIO4BXR - General Standards Corporation

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