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PMC-LX/SX User`s Manual

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1. 7 2 3 4 5 6 7 8 Byte 1 D8 to D15 Byte 2 D16 to D23 Byte 3 D24 to D31 Byte 0 DO to D7 Byte 1 D8 to D15 Byte 2 D16 to D23 Byte 3 D24 to D31 Not Used Read or writing this register is possible via 32 16 or 8 bit transfers STATIC RAM MEMORY Static RAM Memory Read Write PCIBAR2 100000H to 1FFFFFH The Static RAM memory space is used to provide read or write access to on board SRAM memory The Static RAM device has a 256K x 36 bit memory configuration Reading or writing to this memory space using DMA access is also only possible in 32 bit transfers DUAL PORT MEMORY A 256K x 36 bit Dual Port synchronous SRAM DP SRAM is provided on the LX SX board One port of the SRAM connects directly to the local bus to allow for PCI access The remaining port connects directly with the FPGA This design allows for the user to maximize data throughput between the Field I O s and the controlling processor Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module 3 3 There are two automatic DMA initiators available that will trigger upon a user set threshold Furthermore upon a DMA transfer the internal counter can be reset to a user specified value See DMA Registers for more information on these operations These features can be in
2. ae 390 A o Z 5 O c282 2 yeu e e ES C315 da SiS a C279 El 5 lt x C293 4 Ee Q t lt 3 i O c292 3 O 5 C267 R153 JJ gt R130 R152 x 3 ul 5 z y i En O 2s oO ate SL OTD LIX 32 EL 5 0 a TJE gs C1841C189C18IC 1815 S Z dorea SB s Jo os O x sg 5 o LU own 00 N om gt N oD O e 2 og O N C243C266 ES C18010179C1821C 181 C242 oo ee J 52 a on SE E R201 5 O C248 C264 10 o acer O 2 O O NY NY rs oo 2 mu pr It ollo lO ac a gt gt llo v ean le R138 e2 8 O en O nooo R5 ag gt Cc O O to O O e 1d Do oD O oc O FRONT PANEL Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com
3. A23 A11 A25 A24 A26 A28 A27 Not Used Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual A31 A29 Load Mode Register The burst length burst type CAS latency and operating mode are defined in the mode register These mode control settings are programmed via the mem_interface_top_parameters vhd parameter file Auto Refresh The DDR is required to be refreshed once every 7 8us The Xilinx DDR controller will automatically issue the refresh command The refresh frequency is based on a 150Mhz DDR clock frequency If the DDR clock frequency is changed the max_ref_cnt parameter in the mem_interface_top_parameters vhd file needs to be changed accordingly For example at 150MHz max_ref_cnt is 1001000 Precharge The precharge command is used to deactivate the open row in a particular bank or an open row in all banks Address signal A10 is held High during Precharge All Banks A10 held Low during single bank precharge and is selected by BA1 and BAO A25 and A24 Active This command activates a row in a bank allowing any Read or Write to be issued to a bank in the memory array The value on BA1 and BAO A25 and A24 selects the bank and the address on A23 to A11 selects the row The row remains active for accesses until a precharge command is issued to that bank A precharge command must be issued before open
4. The Xilinx FPGA should also be cleared of its current configuration prior to loading of a new configuration file The FPGA is cleared of its current configuration by writing logic 1 to bit 2 at address plus 04H Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module 1 Flash Status 1 Read Only PCIBAR2 0CH FLASH CONTROL REGISTERS This read only register is used to read the DQ5 status of the flash chip The Flash Status 1 register is at base address plus OCH Bit s FUNCTION Table 3 5 Flash Status 1 Oto4 2 4 Not Used bits are read as logic 1 or 0 Register O Chip enabled for reading array data goes high DQ5 can go high during a Flash Start Write Flash Erase Chip or Flash Erase Sector operation 6and7 Not Used bits are read as logic 1 or 0 The system must issue the Flash Reset command to 1 re enable the device for reading array data if DQ5 Flash Status 2 Read Only PCIBAR2 10H This read only register is used to read the ready or busy status of the flash chip The Flash Status 2 register is at base address plus 10H The system must first verify that that Flash Chip is not busy before executing a new Flash command The Flash Chip is busy if bit 7 of this register is set to logic 1 The Flash will always be Busy while bit 0 of the Configuration Control register is set to log
5. PMC LX SX User s Manual DDR SDRAM Write Registers Read Write PCIBAR2 8074H to 8080H The four DDR SDRAM Write registers hold four data values that are to be written to the DDR SDRAM The DDR SDRAM is set for a burst of four for the purposes of this design example A DDR SDRAM write is implemented by executing the following steps 1 Issue a Precharge Command a Write the following value to the SDRAM Address Register at 8060H A31 A29 A28 A27 A26 A25 A24 A23 A11 A10 A9 A0 010 xX 1 Bank Row 1 Xx b Send the precharge command out by setting bit 2 of the SDRAM Control Register at 805CH to a logic 1 2 Issue an Active Command a Write the following value to the SDRAM Address Register at 8060H A31 A29 A28 A27 A26 A25 A24 A23 A11 A10 A9 A0 011 X 1 Bank Row 0 Xx b Send the active command out by setting bit 2 of the SDRAM Control Register at 805CH to a logic 1 3 Write the four 32 bit data values that are to be written to the DDR SDRAM to the registers at base address 8074H to 8080H DDR SDRAM Write Registers DDR SDRAM Write Register DO DDR SDRAM Write Register D1 DDR SDRAM Write Register D2 DDR SDRAM Write Register D3 4 Setthe DDR SDRAM Mask bits as desired at base address 8084H A value of OH would enable all bytes to be written 5 Issue the Write Command a Setthe DDR SDRAM Address register with
6. 1 DMA Local Burst Enable EA DMA Local Address is Incremented E ty DMA Demand Mode Enable 15 o DMA Slow Terminate mode 84H Chan 0 User 98H Chan 1 defined PCI DMA starting Address 88H Chan 0 f User 9CH Chan 1 defined Local DMA starting Address 8CH Chan 0 User AOH Chan 1 defined DMA Transfer Size 90H Chan 0 pa DMA Transfer PCI gt LX SX Board A4H Chan 1 1 DMA Transfer LX SX Board gt PCI A8H Chan 0 SS DMA Channel Enable A9H Chan 1 1 1 DMA Channel Start Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module 2 3 See the PCI9656 user s manual and Acromag s software source code which provides an example for further details The DMA Control and DMA Transfer Size registers are only used to initiate DMA Demand Mode transfers These registers are used to illustrate DMA Demand Mode data transfers Writing to these registers is possible via 32 bit 16 bit or 8 bit data transfers DMA Transfer Size Registers Read Write PCIBAR2 8038H and 803CH DMA REGISTERS The DMA Transfer Size Register is used to set the size of the DMA Demand mode data transfer that moves data to or from the onboard Static RAM memory The onboard static RAM has 256K memory locations As such the maximum value that can be written to this register is 3FFFFH which corresponds to 2
7. 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION FS Wy CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS WARNING This board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS IMPORTANT Adequate air circulation or conduction cooling must be provided to prevent a temperature rise above the maximum operating temperature BOARD CONFIGURATION Default Hardware Configuration Front Panel Field I O Connector Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 8 PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module Rear P4 Field I O Connector The rear I O P4 PMC connector connects directly to bank 5 of the FPGA The bank 5 VCCO pins are powered by 2 5 volts and thus will support the 2 5 volt OStandards The IOSTANDARD attribute can be set in the user constraints file UCF For example rear I O can be defined for LVCMOS25 low voltage CMOS The example design defines the rear I O to LVDS_25 in the user constraints file The 2 5 volt OStandards available are listed in table 6 38 of the Virtex 4 User Guide The example design defines the rear I O connector with 28 LVDS I O pairs with an additional 4 LVDS input only pairs The LVDS input only pairs are RP_IOO RN_101 RP_1010 RN_1011 RP_IO30 RN_1031 and
8. Note that the transfer size specifies the number of Lwords transferred A value of 3FFFFH would specify the move of 256K long words The DMA Transfer Size Register at base address 8038H is used to set the DMA channel 0 data transfer size The register at base address 803CH is used to set the DMA channel 1 data transfer size Writing to these registers is possible via 32 bit 16 bit or 8 bit data transfers Dual Port SRAM Control Register Read Write PCIBAR2 8040H DP SRAM REGISTERS This read write register is used to control the Dual Port SRAM including enabling writing automatic DMA transfer and automatic address reset on DMA thresholds The default power up state of this register is logic low A reset will set all bits in this register to O Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com Virtex 4 Based FPGA PMC Module 24 PMC LX SX User s Manual FUNCTION Table 3 10 Dual Port SRAM Control Register 1 2 Bits are not used and will return logic 0 when read All DMA transfer settings in the DMA Registers and on the PLX9656 should be set prior to enabling automatic DMA transfers WARNING Before enabling Address Reset on DMA Thresholds bits 3 amp 4 verify that the DMA Ch 0 Threshold Register is not equal to the Address Reset Re
9. 1 SFFFFH Threshold Reg as logic 0 Threshold Address Dual Port SRAM Address Reset Registers 0 1 Read Write PCIBAR2 8050H 8054H The Dual Port SRAM Address Reset Registers are used to reset the internal address counter to a user defined value immediately upon reaching the DMA Threshold value For example after a SRAM write cycle where the internal address counter is equal to the value defined in the DMA Channel 0 Threshold Register the internal address counter will then be loaded with the value defined in the Address Reset Register 0 Similarly after a SRAM write cycle where the internal address counter is equal to the value defined in the DMA Channel 1 Threshold Register the internal address counter will then be loaded with the value defined in the Address Reset Register 1 This allows for the internal address counter to be changed without any interruption in the transfer of data from the front connector input to the DP SRAM This feature must be enabled via bits 3 and 4 for Channel 0 amp 1 thresholds respectively of the DP SRAM Control Register Note that the DMA transfers do not have to be enabled for this feature to function Reading bits 0 to 17 of either register will return the corresponding internal address reset value Writing to bits 0 through 17 of this register will set the corresponding internal address reset register to the provided value Bits 18 to 31 are not used and will return logic 0 when read A
10. 66MHz Frequency Stability 0 0025 or 25ppm 32M x 36 bit Density Micron MT46V32M16BN 5B SDRAM Crystal Oscillator 200MHz Frequency Stability 0 01 or 100ppm DDR SDRAM Clock 150MHz Data Transfer Rate 300M longwords 32 bits s 256K x 36 bit Integrated Devices Technology IDT70T3519S133BC 133 Megahertz Speed LCLK Maximum Clock Frequency 66MHz PMC Compatibility Conforms to PCI Bus Specification Revision 2 2 and PMC Specification P1386 1 PCI Master Target Implemented by PLX Technology PCI9656 Chip 2M Memory Space Required One Base Address Register for this 2M space PCI commands Supported Configuration Read Write memory Read Write 64 32 16 and 8 bit data transfer types supported Signaling 5V or 3 3V Compliant INTA Interrupt A is used to request an interrupt Source of interrupt can be from the Digital I O or PCI9656 Functions Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module 4 1 gt faa o Ww Ze Om Wk co ic Sos oo na an awn o as o az aol Regd To lt L Si gt ES O go Lies y 5 ES a X w 2 Pz g a a So ul Das lo Su xo ot o o O Sanras we o 7 oe a a lt gt ol a o 3 lt P So x o y 2138 o z258 S883 2S ae SF zl g O mo 50 o
11. Configuration Status register before programming is initiated 4 Verify Flash Chip is not busy by reading bit 7 as logic O of the Flash Status 2 register at base address plus 10H before starting a new Flash operation 5 Erase the current flash contents by using the Flash Erase Sector method Flash erase sectors are implemented by setting bit 0 of the Flash Erase Sector register to logic high There are 128 flash sectors which are addressed via the most significant seven flash address lines The most significant seven flash address lines are set via the Flash Address 22 16 register at base address plus 34H Issuing a Flash Erase Sector command will erase the contents of the flash chip only in the sector specified 6 Verify Flash Chip is not busy by reading bit 7 as logic O of the Flash Status 2 register at base address plus 10H before going to the next step 7 Download the Configuration file to the flash configuration chip via the PCI bus i Write the byte to be sent to the Flash Data register at base address plus 28H ii Write the address of the Flash Chip to receive the new data byte to the Flash Address registers at base address plus 2CH 30H and 34H Issuing a Flash Start Write will automatically increment this address after the prior Flash Write has been completed Thus the address will not need to be set prior to issuing the next Flash Start Write The first byte of the configuration file should be written to address 0 of the Fl
12. Precharge Command a Write the following value to the SDRAM Address Register at 8060H A31 A29 A28 A27 A26 A25 A24 A23 A11 A10 A9 A0 010 Xx 1 Bank Row 1 Xx b Send the precharge command out by setting bit 2 of the SDRAM Control Register at 805CH to a logic 1 2 Issue an Active Command a Write the following value to the SDRAM Address Register at 8060H A31 A29 A28 A27 A26 A25 A24 A23 A11 A10 A9 A0 011 X 1 Bank Row 0 X b Send the active command out by setting bit 2 of the SDRAM Control Register at 805CH to a logic 1 3 Issue the Read Command a Setthe DDR SDRAM Address register with the start address location and read command Write the following value to the SDRAM Address Register at 8060H A31 A29 A28 A27 A26 A25 A24 A23 A11 A10 A9 A0 101 Xx 1 Bank Row 0 Column b Set the start read bit of the DDR SDRAM Control register at base address 805C Set bit 1 of the SDRAM Control Register at 805CH The data is read from the SDRAM and moved to the SDRAM Read Registers at 8064H to 8070H Reading these registers is possible via 32 16 or 8 bit transfers DDR SDRAM Read Registers DDR SDRAM Read Register DO DDR SDRAM Read Register D1 DDR SDRAM Read Register D2 DDR SDRAM Read Register D3 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com
13. RP_1046 RN_1047 The LVDS pairs are arranged in the same row in table 2 1 For example RP 100 and RN 101 form a signal pair The RP identifies the plus input while the RN identifies the negative input Table 2 1 Board Rear Field Ch Pin Description Pin Description I O Pin Connections RP_IOO LVDS Input Only N_IO1 LVDS Input Only RP_lO2 RN_I03 The example design RP 104 RN 105 implements 2 5volt LVDS O RP 106 RN 107 VREF to the rear connector Signal pairs are routed to pins 1 2 EJ RP_108 9 RN_IO9 Pn a 5 Ea 3 4 elo APOYO LVDS Input Only 11 ANOT LVDS Input Oniy E meon a ANOS RP ora Js ONTOS oi 7 A oes Jo mon A a Ros o mos 7 3 3 E 3 ze 3 gt 3 4 BA 4 4 4 4 a RN_IO33 RP_1034 RP_lO36 RP_lO16 RN_1017 RN_1035 RN_1037 RP_1038 RN_1039 VREF 31 33 35 37 C Ron a ANO O C C PoR a mNoOoB Y RP_1044 45 RN_1045 RP_1046 LVDS Input Only 47 RN1O47 LVDS Input Only C Ros Ci CRN APTOS O a ANIOS Co ReO s O RNO O C RPO O s CRNIOSS VREF O O C RPO 57 RNO C ReO s RNO O Reo O a RNO O Reo gt es RN Pn 67 EN 46 760 1 3 5 7 11 13 15 17 19 1 3 5 7 1 3 5 7 9 1 3 5 7 9 51 53 55 57 59 61 63 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag c
14. SX boards are available in the standard temperature range KEY FEATURES The re configurable PMC LX modules use the Xilinx Virtex 4 LX FPGA The re configurable PMC SX modules use the Xilinx Virtex 4 SX FPGA Re configuration of the FPGA is possible via a direct download into the Xilinx FPGA over the PCI bus In addition on board flash memory can be loaded with FPGA configuration data for automatic Xilinx configuration on power up Flash programming is also implemented over the PCI bus The example design includes an interface to the user rear I O and front I O connectors and an example memory interface controller to 32M x 32 bit DDR SDRAM Also the example design includes an interface to the 256K x 36 bit SRAM with DMA hardware support OPERATING MODEL TEMPERATURE RANGE 0 C to 70 C or 0 C to 70 C 0 C to 70 C or PMC LX60 XC4VLX60 Conduction Cooled 0 C to 70 C 0 C to 70 C or PMC SX35 XC4VSX35 Conduction Cooled 0 C to 70 C e Reconfigurable Xilinx FPGA In system configuration of the FPGA is implemented through a flash configuration device or via the PCI bus This provides a means for implementation of custom user defined designs e 32M x 32 DDR SDRAM A 32M x 32 bit double data rate DDR dynamic random access memory DRAM is directly accessed through the Xilinx device Read and write accesses to the DDR SDRAM are burst oriented e 256K x 36 Dual Port SRAM A 256K x 36 bit dual port static ra
15. Standalone Operation 3 0 PROGRAMMING INFORMATION Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 0 PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module The document Using the PMC LX SX Engineer Design Kit provided in the engineering design kit will guide you through the steps required to modify the example design for your custom application See the Direct PCI bus to Xilinx Configuration section for a description of the steps required to perform reconfiguration directly from the PCI bus The registers provided in the FPGA Programming Memory Map are used to implement a direct reconfiguration 3 After you have thoroughly tested your customized FPGA design you can erase the flash and write your code to flash Once the flash is erased you will not be able to go back to the example design by simply powering down and restarting the board See the Flash Configuration section for a description of the steps required to write new design code to the flash device The registers provided in the FPGA Programming Memory Map are used to implement a flash erase and reprogram operations This board is a PCI Specification version 2 2 compliant PCI bus PCI Configuration Address master target board Space The PCI bus is defined to address three distinct address spaces I O memory and configuration space This board can be accessed via the PCI bus I O memory and configuration spaces
16. The card s configuration registers are initialized by system software at power up to configure the card The board is a Plug and Play PCI card As a Plug and Play card the board s base address and system interrupt request line are not selected via jumpers but are assigned by system software upon power up via the configuration registers A PCI bus configuration access is used to read write the PCI card s configuration registers When the computer is first powered up the computer s system configuration software scans the PCI bus to determine what PCI devices are present The software also determines the configuration requirements of the PCI card The system software accesses the configuration registers to determine how many blocks of memory space the module requires It then programs the board s configuration registers with the unique memory base address The configuration registers are also used to indicate that the board requires an interrupt request line The system software then programs the configuration registers with the interrupt request line assigned to the board Since this board is relocatable and not fixed in address space its device driver must use the mapping information stored in the board s Configuration Space registers to determine where the board is mapped in memory space and which interrupt line will be used Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX
17. Virtex 4 Based FPGA PMC Module DDR SDRAM Address Register Read Write PCIBAR2 8060H This read write register is used to set the DDR SDRAM column address row address bank chip select and command This Address register must be written prior to issuing of a DDR SDRAM read or write burst transfer via bits O or 1 of the DDR SDRAM Control register Table 3 14 DDR SDRAM DDR SDRAM Column address is written to these bits A 1 All bits labeled Not Used column address is required when a read or write command is will return logic 0 when present on bits 29 to 31 There are 1024 unique columns read A10 is used for precharge control with a read or write command If A10 is logic high auto precharge is selected and the row being accessed will be precharged at the end of the write If A10 is logic low the row will remain open for subsequent accesses Logic 0 Disables auto precharge Logic 1 Enables auto precharge A10 will also determine whether one or all banks are precharged when a precharge command is issued Single precharge BA1 and BAO A25 A24 determine which bank is precharged Logic 0 Logic 1 All Banks are precharged DDR SDRAM Row address is written to these bits There are 8192 unique rows DDR SDRAM Bank address BA1 BAO is written to these bits The DDR SDRAM has four unique banks DDR SDRAM Chip Select CS This bit should always be set to logic High
18. board be visually inspected for evidence of mishandling prior to applying power Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the system boards plus the installed Acromag board within the voltage tolerances specified In an air cooled assembly adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering In a conduction cooled assembly adequate thermal conduction must be provided to prevent a temperature rise above the maximum operating temperature Remove power from the system before installing board cables termination panels and field wiring The board may be configured differently depending on the application When the board is shipped from the factory it is configured as follows e The default configuration of the programmable software control register bits at power up are described in section 3 e The control registers must be programmed to the desired configuration before starting data input or output operation The front panel connector provides the field I O interface connections via optional mezzanine I O modules purchased separately Virtex 4 Based FPGA PMC Module
19. by writing to the Configuration Data register The entire configuration file must be written to the Xilinx FPGA one byte at a time to the Configuration Data register at base address plus 08H 5 Verify configuration complete by reading DONE bit 0 of Configuration Status Register as logic high DONE is expected to be logic high immediately after the last byte of the configuration file is written to the Xilinx FPGA 6 At each power up the configuration file will need to be reloaded into the FPGA Configuration Status Register Read Only PCIBAR2 Configuration Status 0000H Register This read only register reflects the status of configuration complete and Xilinx configuration clear bits This Configuration Status register is read at base address plus OH Bit s FUNCTION Table 3 3 Configuration s DONE Status Register 0 Xilinx FPGA is not configured 1 Xilinx FPGA configuration is complete INIT INIT is held low until the Xilinx is clear of its current configuration INIT transitions high when the clearing of the current Xilinx configuration is complete Not Used bits are read as logic 0 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 6 PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module CONFIGURATION CONTROL Configuration Control Read Write PCIBAR2 04H REGISTERS This read write register is used to stop Xilinx configuration clear Xili
20. example design defines the rear I O with 2 5 volt LVDS e Maximum Recommeded Clock Rate 150MHz 6 7ns clock period e Veco Supply Voltage ceeeeee aes 2 5 volt e Vox Output High Voltage 1 602 volt e Vo Output Low Voltage o coo oc o 0 898 volt e Vopier Differential Output Voltage 350m volt typical e Vocm Output Common Mode Voltage 1 25 volt typical e Vipier Differential Input Voltage 100m volt minimum e Vicm Input Common Mode Voltage 0 3 volt min 2 2 volt max Virtex 4 Based FPGA PMC Module 3 9 SPECIFICATIONS Reliability Prediction FPGA PMC LX40 FPGA PMC LX60 FPGA PMC SX35 REAR l O Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com A PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module FRONT I O Write Disable Jumper Double Data Rate SDRAM Dual Port SRAM PLX 9656 Local Bus PCI Local Bus Interface See the mezzanine module users manual for front I O specifications This PMC module uses the 150 pin Samtec connector part number XX which mates with the mezzanine module connector part number QTS 075 02 L D A K Write Disable Jumper Removal of surface mount resistor R171 disables write to the PCI bus configuration EEPROM and removal of surface mount resister R172 disables write to the Xilinx FPGA configuration flash device Board Crystal Oscillator
21. operation Note that the example program requires the use of continuous burst and slow terminate mode DMA transfer options For other DMA modes of operation see the PLX Technology PCI9656 user manual The DMA demand mode requires Xilinx FPGA hardware to drive two PCI9656 signals active to request the DMA transfer of data The signal DREQOf is driven active to request a DMA channel 0 transfer The signal DREQ1 is driven active to request a DMA channel 1 transfer To identify the pins corresponding to these signals see the user constraints UCF file provided in the engineering design kit This LX SX board does not utilize the PCI9656 PCI power management functions The power management request signal PME is not used and is tied high with an external pullup resistor The internal PCI Arbiter is not used External pull up resistors are tied to the REQ 6 1 input and GNT 6 1 output signals of the PCI9656 chip Many features of the PCI9656 are not used in the example design but NOT USED PCI9656 are available if enabled It is beyond the scope of this document to FUNCTIONS duplicate the PCI9656 User s Manual Please refer to the PCI9656 User s Manual See Related Publications for more detailed information Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 6 PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module THEORY OF OPERATION CONTINUED SYNCHRONOUS Dual Port SRAM THEORY
22. system reset will cause these registers to reset to OOOOOH Dual Port SRAM Read Register Read Only PCIBAR2 8058H The Dual Port SRAM Read Register is provided for production testing of the LX SX product This port can be used to verify the integrity of the SRAM port linked to the FPGA Reading this register is only possible in 32 bit transfers The address in SRAM read is initialized by the Dual Port SRAM Internal Address register at base address 8044H With each additional read the address is automatically incremented Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module 2 DDR SDRAM Control Register Read Write PCIBAR2 805CH DDR SDRAM REGISTERS This read write register is used to control burst read or write to DDR SDRAM In addition a DDR SDRAM error status bit is available in this register The DDR SDRAM is set for a burst length of four and will require the DDR SDRAM Write register to be preloaded with four 32 bit data values prior to issuing of the write operation The DDR SDRAM Read register will contain four 32 bit data values upon issue of a read operation For either a read or write the DDR SDRAM Address register must be written with the desired command and address location for the access Table 3 13 DDR SDRAM FUNCTION Control Register Start DDR SDRAM write operation The DDR SDRAM 1 All bits labeled N
23. the start address location and write command Write the following value to the SDRAM Address Register at 8060H A31 A29 A28 A27 A26 A25 A24 A23 A11 A10 A9 A0 100 X 1 Bank Row 0 Column Virtex 4 Based FPGA PMC Module 3 1 Table 3 16 DDR SDRAM Write Registers Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 2 PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module b Set the start write bit of the DDR SDRAM Control register at base address 805C Set bit 0 of the SDRAM Control Register at 805CH DDR SDRAM Mask Register Read Write PCIBAR2 8084H The DDR SDRAM mask register holds the write mask data bits that accompany the write data as it is written to the DDR SDRAM If a given data mask DM bit is set low the corresponding data will be written to memory if the DM bit is set high the corresponding data will be ignored and a write will not be executed to that byte location The DDR SDRAM is set for a burst of four for the purposes of this design example Table 3 17 DDR SDRAM DDR SDRAM Mask Mask Register Register Bit valle Register io 2 All bits labeled Not Used pyle 01001020 es Byte 1 D8 to D15 will return logic 0 when DO read d Byte 2 D16 to D23 Byte 3 D24 to D31 Byte 0 DO to D7 Byte 1 D8 to D15 Byte 2 D16 to D23 Byte 3 D24 to D31 Byte 0 DO to D7
24. 0MHz AM amp 900MHz keyed and European Norm EN50082 1 with no register upsets Conducted R F Immunity CRFI Complies with EN61000 4 6 3V rms 150KHz to 80MHz and European Norm EN50082 1 with no register upsets Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Surge Immunity Not required for signal I O per European Norm EN50082 1 Radiated Emissions Designed to comply with European Norm EN50081 1 for class B equipment Shielded cable with I O connections in shielded enclosure are required to meet compliance Mean Time Between Failure MIL HDBK 217F Notice 2 25 C PMC LX40 773 246 Hours PMC LX110 870 489 Hours PMC SX35 869 686 Hours Xilinx XC4VLX40 10FF668C e 36 864 CLB Flip Flops e 294 912 Distributed RAM Bits e 96 18Kbit Block RAMs e 64 DSP Slices e 8 Digital Clock Managers Xilinx XC4VLX60 10FF668C e 53 248 CLB Flip Flops e 425 984 Distributed RAM Bits e 160 18Kbit Block RAMs e 64 DSP Slices e 8 Digital Clock Managers Xilinx XC4VSX35 10F F668C e 30 720 CLB Flip Flops e 245 760 Distributed RAM Bits e 192 18Kbit Block RAMs e 192 DSP Slices e 8 Digital Clock Managers The rear I O P4 PMC connector connects directly to bank 5 of the FPGA The bank 5 Vcco pins are powered by 2 5 volts and thus will support the 2 5 volt IOStandards Table 6 38 of the Virtex 4 User Guide lists all the supported lOStandards available The
25. Acromag kd THE LEADER IN INDUSTRIAL 1 0 Series PMC LX SX Virtex 4 Based FPGA PMC Module USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A Copyright 2010 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 795 C10H013 2 PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module TABLE OF IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power wiring CONTENTS component sensor or software failure in the design of any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility 1 0 General Information The information of this manual KEY FEATURES coria didas dig 4 may change without notice PCI INTERFACE FEATUREG 22 000 cee eee eeees 5 Acromag makes no warranty Board DLL Control Software sseee 6 of any kind with regard to this Board VXWORKS Software cessseeeeeee 6 material including but not Board QNX Software 0ccsceceeeeeeeeeeeeseeeeenens 6 limited to the implied warranties of merchantability 2 0 PREPARATION FOR USE and fitness for a particular PUD OSE ROO UNPACKING AND INSPECTION s ssssssseseessssee 7 g
26. DMA Control Register is used to request a DMA Demand mode transfer The transfer must include the Static RAM Memory as either the source or the destination Bit 0 is used to request a DMA channel 0 transfer while bit 1 is used to request a channel 1 DMA transfer The bit must be set to logic high to request a transfer Once set the bit will remain set until the DMA transfer has completed If both bits are set simultaneously the channel 0 DMA transfer will be implemented first followed by the channel 1 DMA transfer PLX PCI9656 DMA Setup Registers The size of the DMA transfer must be set in the DMA Transfer Size register corresponding to the channel handling the transfer See the description of the DMA Transfer Size registers in the following paragraphs In addition the DMA transfer size direction source and destination must be set in the PCI9656 DMA control registers The PCI9656 DMA registers are at PCIBARO base address offset 80H to B8H Specifically the registers and bits must be assigned as shown in the table below when performing a DMA channel for proper operation Bose Andre Bit s e Jic Description 6 Lo DMA Channel 1 Little Endian Mode 7 DMA Channel 1 Big Endian Mode Ea DMA Channel 0 Little Endian Mode OCH 1 DMA Channel 0 Big Endian Mode KARR DMA Local Bus Data Width 32 bits Para DMA READY Input Enable EARRA DMA Burs 4 Mode Enable 80H Chan 0 DMA DMA Local Burst Enable Burst Enable Soh Chan 0 e
27. Digital Clock Manager for more information The USERo signal is controlled via a PCI9656 device register over the PCI bus The PCI9656 User I O Control register at PCIBARO base address offset 6CH must have bit 19 set to a logic high to select USERo to be an output from the PCI9656 In addition User I O Control register at PCIBARO base address offset 6CH must control bit 16 Bit 16 set to logic high causes the Board clock to be 66MHz Bit 16 set to logic low will select the PLL_CLK as the Board clock frequency PCI PCIBARO PCI9656 Runtime Register Address 6CH User I O Control iets RE Board clock becomes PLL_CLK Board clock 66MHz Default Do not set as logic low USERo Enabled as output Note that the Xilinx FPGA can not be reconfigured with the PLL_CLK signal selected The first step in FPGA reconfiguration is to clear the FPGA device and this will disable the PLL_CLK signal Without a board clock the LX SX board will lock up and require a system power down to reactivate The USERo clock control signal must be set to logic high prior to FPGA reconfiguration Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module 3 5 This section contains information regarding the design of the board A description of the basic functionality of the circuitry used on the board is also 4 0 THEORY OF provided Refer to the Block Diagram shown in Dra
28. H PLX DMA Channel 0 Command Status register 2 The LX SX DMA registers must also be set to transfer 131 072 Lwords e Write 20000H to LX SX DMA Transfer Size Register at PCIBAR2 plus 8038H Note the transfer size specifies the number of Lwords transferred e Initialize the SRAM Internal Address register to OH External field data is written to SRAM at this starting address Write OH to PCIBARZ2 plus 8044H e Setting the SRAM DMA channel 0 Threshold register to 1 FFFFH will starta DMA demand mode transfer when the internal address counter reaches 1FFFFH 131071 decimal Write 1FFFFH to PCIBAR2 plus 8048H 3 Lastly the LX SX external rear I O data is enabled for write to SRAM and DMA Channel 0 demand mode start when the internal address equals the Channel 0 Threshold register e Write SRAM Control Register with 3H to PCIBAR2 plus 8040H Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 4 PMC LX SX User s Manual PCI9656 REGISTERS PCI9656 USERo CLOCK CONTROL Note the PCI9656 USERo signal is a general purpose output controlled from the PCI9656 Configuration registers The o at the end of this signal name indicates that this is an output signal Table 3 18 USERo Control Virtex 4 Based FPGA PMC Module PCI9656 Registers Read Write PCIBARO The PCI9656 is configured for PLX PCI9656 chip C Mode Local bus operation Only the PCI9656 User s Manual reference
29. N PCI INTERFACE LOGlCoooncoconconcncononconnnranoncnnnnnaas 35 NOT USED PCI9656 FUNCTIONG 0 sseeeeeeeeee 35 SYNCHRONOUS DUAL PORT SRAM 0 000 36 SERIAL EEPROM gai ccccneccosntechcutvceveneeschees testes 36 CLOCK CONTROL coocoonccconcononnoncnnononcnnnnnanencnnnnnss 37 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE 000 37 PRELIMINARY SERVICE PROCEDURE 37 WHERE TO GET HELP iaria anhon airosa 37 6 0 SPECIFICATIONS PHYSICAL ccoo iia 38 ENVIRONMENT AL cooconcoococconcoconcnconcononnarenennnnnes 38 FPGA SPECIFICATIONS oococcoccoconconnarononcnnnononans 39 DUAL PORT SRAM coococcccnncnonnnnnaronnnnononronnonnnnn nos 39 PCI LOCAL BUS INTERFACE 2 ccceseeeeeeeeees 40 DRAWINGS Trademarks are the property 4502 054 BLOCK DIAGRAM s ccceeseeeeeeeeeees 41 4502 053 J7 EXTERNAL POWER LOCATION 42 e dd lt The following manuals and part specifications provide the necessary information for in depth understanding of the AX board RELATED m PUBLICATIONS Virtex 4 Data Book http www xilinx com PCI 9656 Data Book http www plxtech com IDT70T3519S133 Spec http www idt com MT46V32M16 Spec http www micron com CY2305 Specification http www cypress com Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 4 PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module 1 0 GENERAL INFORMATION Table 1 1 The PMC LX
30. OF OPERATION CONTINUED SERIAL EEPROM The PCI9656 is hardwired for C bus mode This is a generic 32 bit non multiplexed address and data bus interface The example design implements the PCI9656 as the local bus master The local bus is the bus interface between the PCI9656 and the Xilinx FPGA As the local bus master the PCI9656 responds to BREQi assertion to relinquish local bus ownership The example design has BREQi tied low The Xilinx FPGA does not request the local bus However the FPGA may drive BREQi high if the FPGA must take control of the local bus The example design implements single cycle mode In single cycle mode the PCI9656 issues one ADS per data cycle The starting address for a single cycle data transfer can be any address Burst read and write cycles can be implemented but must be enabled in the PCI9656 and supported in the logic of the FPGA The PCI9656 Local Address Space 0 Expansion ROM Bus Region Descriptor register at PCIBARO base address offset 18H must have bit 24 set to a logic high to enable bursting A 256K x 36 bit synchronous Dual Port SRAM is provided on the board One port of the SRAM uses the address and data lines from the PCI9656 The remaining port connects directly to the FPGA This configuration allows for a continuous data flow from the field inputs through the FPGA to the SRAM and then to the PCI bus via the PCI9656 IC Both ports of the SRAM operate in Pipeline mode This allows for fas
31. PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module 6 0 SPECIFICATIONS PHYSICAL Unit Weight Connectors Table 6 1 Power Requirements for Example Design Power will vary dependent on the application 5V Maximum rise time of 100m seconds ENVIRONMENTAL Single PMC Board Height 13 5 mm 0 531 in Stacking Height 10 0 mm 0 394 in Depth 149 0 mm 5 866 in Width 74 0 mm 2 913 in Board Thickness 1 59 mm 0 062 in PMC LX SX 3 260z 0 0924Kg typical e PMC PCI Local Bus Interface Four 64 pin female receptacle header AMP 120527 1 or equivalent Three of these connectors interface to the PCI bus the fourth connector provide 64 rear I O connections e Front Field I O Connector on PMC module Samtec QSS 075 01 L D A Mating Mezzanine Connector Samtec QTS 075 01 L D A with 5mm stack height or Samtec QTS 075 02 L D A with 8mm stack height Power PMC Modules Requirements a or a 1200mA On Board 1 2V Power to Current Rating Virtex 4 FPGA 3 3V 45 120 08 Operating Temperature 0 to 70 C Conduction Cooled PCI mezzanine card Complies with ANSI VITA 20 2001 R2005 The PMC LX SX without a faceplate is fully compatible with a conduction cooled host card Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 125 C Non Isolated Logic and field commons have a direct electrical connection Radiated Field Immunity RFI Complies with EN61000 4 3 3V m 80 to 100
32. RO base address offset 68H must have bits 18 and 19 set to a logic high in order for DMA interrupts to occur on DMA channels 0 and 1 respectively DMA transfers are configured and controlled via PCI9656 DMA registers The PCI9656 DMA registers are at PCIBARO base address offset 80H to B8H These registers control the transfer direction size source address and destination address for DMA channels 0 and 1 Rear I O Connector Read Register Read Only PCIBAR2 802CH REAR Read REGISTER The Rear I O Connector Read Register is used to read the LVDS input status of 16 channels This example design has 16 channels identified in Table 3 8 programmed as LVDS input only channels Table 2 1 shows each channel and it s corresponding P4 connector pin assignment This Rear I O Connector Read register is a read only register and writing to this register has no effect on the LVDS input channels Reading from this register is possible via 32 bit 16 bit or 8 bit data transfers Rear I O Connector Write Register Read Write PCIBAR2 8030H REAR Write REGISTER The Rear I O Connector Write Register is used to set 16 LVDS output channels This example design has 16 channels identified in Table 3 8 fixed as LVDS output only channels Table 2 1 shows the P4 connector pins and their corresponding channel identifiers This Rear I O Connector Write register is written to set the LVDS output channels and can also be read to verify the output cha
33. SX User s Manual Virtex 4 Based FPGA PMC Module 1 1 The PCI specification requires software driven initialization and CONFIGURATION configuration via the Configuration Address space This board provides 512 REGISTERS bytes of configuration registers for this purpose It contains the configuration registers shown in Table 3 1 to facilitate Plug and Play compatibility The Configuration Registers are accessed via the Configuration Address and Data Ports The most important Configuration Registers are the Base Address Registers and the Interrupt Line Register which must be read to determine the base address assigned to the board and the interrupt request line that goes active on a board interrupt request 0x4C40 LX40 0x4C60 LX60 Device ID 0x5335 SX35 Vendor ID 16D5 Class Code 118000 Rev ID 00 aes foams 3 sist Header Latency Cache Table 3 1 Configuration Registers 32 bit Memory Base Address for Memory Accesses to Local Runtime DMA and Messaging Queue Registers PCIBARO PCI Base Address for I O Accesses to Local Runtime DMA and Messaging Queue Registers PCIBAR1 32 bit Memory Base Address for Memory Accesses to Local Address Space 0 2M Space FPGA Space PCIBAR2 Not Used 0x4C40 LX40 Subsystem 0x4C60 LX60 ID 0x5335 SX35 Subsystem Vendor ID 16D5 Not Used This board is allocated memory space address PCIBARO to access the PCI9656 runtime DMA and messaging queue registers The PCI9656 d
34. The example design implements DMA block and demand modes of operation e 32 16 8 bit I O Register Read Write is performed through data transfer cycles in the PCI memory space All registers can be accessed via 32 16 or 8 bit data transfers e Compatibility Complies with PCI Local Bus Specification Revision 2 2 Provides one multifunction interrupt Board is 5V or 3 3V signaling compliant The voltage provided on the PCI connector VIO pins determines the operating voltage of the PCI bus e Supply Voltage Requirement The board requires that 3 3 volts external power be provided on the 3 3 volt signal lines of the PCI bus connector Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 6 PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module ENGINEERING DESIGN KIT BOARD DLL CONTROL SOFTWARE BOARD VxWORKS SOFTWARE BOARD QNX SOFTWARE BOARD Linux SOFTWARE Acromag provides an engineering design kit for the LX SX boards sold separately a must buy for first time LX SX module purchasers The design kit model PMC LX SX EDK provides the user with the basic information required to develop a custom FPGA program for download to the Xilinx FPGA The design kit includes a CD containing schematics parts list part location drawing example VHDL source and other utility files The LX SX modules are intended for users fluent in the use of Xilinx FPGA design tools Acroma
35. a Mezzanine Identification Code 001 for all digital l O mezzanine boards A digital temperature sensor monitors the temperature of the Xilinx Virtex 4 FPGA The digital temperature sensor has an accuracy of 2 4 C The data is available as a 13 bit two s complement value The 13 bit data value provides a resolution of 0 0625 C Multiply the signed 3 bit data value by 0 0625 C to obtain the FPGA die temperature Temperature D28 D16 150 C 0 1001 0110 0000 125 C 0 0111 1101 0000 25 C 0 0001 1001 0000 0 0625 C 0 0000 0000 0001 0 C 0 0000 0000 0000 0 0625 C 1 1111 1111 1111 25 C 1 1110 0111 0000 55 C 1 1100 1001 0000 30 29 Not Used The most significant bit of this register when set to a logic 1 will issue a software reset No Operation Software Reset issued to Xilinx Virtex 4 FPGA Interrupts must be enabled via the PCI9656 control registers and the Mezzanine Interrupt Enable register in order to generate interrupts The PCI9656 Interrupt Control Status register at PCIBARO base address offset 68H must have bits 8 and 11 set to logic high in order for interrupts to occur Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX Users Manual Virtex 4 Based FPGA PMC Module 2 1 DMA interrupts must be enabled and controlled through the PCI9656 registers The PCI9656 Interrupt Control Status register at PCIBA
36. ad address Writing to bits 0 through 17 of this register will set the Internal SRAM Address to the provided value Writing logic 1 to bit 31 of this register or a system reset will cause the Internal SRAM Address to reset to OOOOOH the start of the SRAM memory Reading or writing to this register is possible via 32 bit data transfers only Dual Port SRAM Internal Address Register SRAM Internal Not Used Read SRAM Internal Address Reset as logic 0 Address Dual Port SRAM DMA Channel 0 1 Threshold Registers Read Write PCIBAR2 8048H 804CH The Dual Port SRAM DMA Channel 0 1 Threshold Registers are used to initiate an automatic DMA transfer When the internal address counter is equal the value in the DMA Channel 0 Threshold Register a Channel 0 DMA request will be initiated Similarly when the internal address counter is equal the value in the DMA Channel 1 Threshold Register and there is valid data at that address a Channel 1 DMA request will be initiated This feature must be enabled via bits 1 and 2 for Channels 0 amp 1 respectively of the DP SRAM Control Register Note that DMA settings must be set prior to the initiated transfer on both the PCI9656 and in the DMA Registers A DMA transfer in progress is indicated via bits 0 and 1 for DMA Channels 0 and 1 respectively in the DMA Control Register See the DMA Registers section of this manual for further details Reading bits 0 to 17 of either regi
37. ash Chip The Flash Start Write operation will take 9u seconds to complete iii Issue a Flash Start Write command to the Flash Chip by writing logic 1 to bit O of base address plus 1CH Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module 1 D iv Verify the Flash Chip is not busy by reading bit 7 as logic 0 of the Flash Status 2 register at base address plus 10H before going back to step i to write the next byte 8 Enable auto configuration by setting bit 0 Stop Configuration of the Configuration Control register to logic low 9 Verify configuration complete by reading DONE bit 0 of Configuration Status Register as logic high 10 Thereafter at power up the configuration file will automatically be loaded into the FPGA Configuration of the Xilinx FPGA can be implemented directly from the Direct PCI bus to Xilinx PCI bus The following is the general procedure for re configuration of the Configuration Xilinx FPGA via the PCI bus 1 Disable auto configuration by setting bit 0 Stop Configuration of the Configuration Control register to logic high 2 Clear the Xilinx FPGA of its previous configuration by setting the Configuration Control register bit 2 to logic high 3 Read INIT as logic high Bit 1 of Configuration Status register before programming is initiated 4 Download the Configuration file directly to the Xilinx FPGA
38. dividually controlled through the SRAM Control Registers Dual Port SRAM DMA Transfer Example In this example external data is written to LX SX board SRAM Upon receiving the 131 072 Lwords the DMA demand mode transfer is started The DMA transfer will move the 131 072 Lword samples to a designated location in system memory 1 The PCI 9656 DMA Channel 0 registers must first be set to transfer 131 070 Lwords e Write 1043H to PLX DMA Channel 0 Mode register at PCIBARO plus 80H e Write the destination start address This is the location in system memory that the LX SX SRAM data will be moved The address is written to the PLX DMA Channel 0 PCI Address register at PCIBARO plus 84H e Write the source start address This is the start address of the LX SX SRAM Write PCIBAR2 100000H to location PCIBARO plus 88H PLX DMA Channel 0 Local Address register e Write the number of bytes moved by the DMA transfer to the PLX DMA Channel 0 Transfer Size register Write 80000H 524 288 bytes decimal to PCIBARO plus 8CH e Setup the DMA transfer direction as LX SX board to PCI Write 8H to PCIBARO plus 90H PLX DMA Channel 0 Descriptor Pointer register e Enable the PLX chip for the DMA transfer Write 1H to PCIBARO plus A8H PLX DMA Channel 0 Command Status register e Set the PLX chip up to start the DMA transfer Note that the transfer will not be started until the LX SX hardware drives the DREQO signal active Write 3H to PCIBARO plus A8
39. e PCI9656 to provide power up configuration information required by the PCI9656 device The stored data in the EEPROM contains PCI device and vendor ID information In addition the PCI interrupt line PCI base address size and user options such as burst enabled are specified in this memory device The contents of the serial EEPROM can be changed using the PCI9656 VPD function Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Acromag software also provides the functions needed to implement read and write operations to the serial EEPROM The board clock is routed to the PCI9656 Local bus pin SRAM CPLD and FPGA using a low skew clock driver Cypress CY2305 The input to the CY2305 can be one of two sources The on board 66MHz crystal oscillator is input to the CY2305 upon power up as the default condition After the FPGA is configured an FPGA generated clock signal PLL_CLK can be selected as the board clock The PLL_CLK signal is selected as the board clock by setting the USERo PCI9656 output signal to logic low See the PCI9656 USERo CLOCK CONTROL section of chapter 3 for additional details Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag
40. ecodes 512 bytes for these memory space registers These registers can also be accessed by an I O cycle with the PCI bus address matching the I O Base Address PCIBAR1 In addition this board is allocated a 2M byte block of memory PCIBAR2 that is addressable in the PCI bus memory space to control the board s many functions included in the Virtex 4 FPGA Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 2 PMC LX SX User s Manual FPGA PROGRAMMING Virtex 4 Based FPGA PMC Module The memory space address map used to program the FPGA and flash device is shown in Table 3 2 Note that the base address for the board MEMORY MAP PCIBAR2 in memory space must be added to the addresses shown to properly access these registers Register accesses as 32 16 and 8 bit in memory space are permitted Table 3 2 D31 Dos D07 Doo Base FPGA Programming Addr r aoc Memory Map 0003 Not Used Configuration Status 0000 1 The board will return O for all addresses that are Not Used 0007 000B 000F 0013 0017 001B 001F 0023 0027 002B 002F 0033 0037 003B Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Register Configuration Control Register Configuration Data Flash Status 1 Register Flash Status 2 Register Flash Read Flas
41. enes Te ene ny iat CARD CAGE CONSIDERATIONS sssesssssesessssee 7 any eb Or el May abpeanip BOARD CONFIGURATION cssssesssesteseteceesnesee 7 this manual and makes no Default Hardware Configuration 0 7 commitment to update oe Front Panel lO oooonococonocancarcnacnanonccnananonens 7 keep current the information Non Isolation Considerations momonomom 9 contained in this manual No nica or reproduced mary 3 0 PROGRAMMING INFORMATION form without the prior written consent of Acromag Inc GETTING STARTED a eee 9 PCI CONFIGURATION ADDRESS SPACE 10 Configuration registerS oococoococccroconcnnnn nos 11 MEMORY MAP 22 ccsscceseceseeeeeeeeeeeeeeeeeeeeeeeeeeeees 12 Flash Configuration ccccscccsseeesseesseeeees 14 PCI bus to Xilinx Configuration 008 15 Configuration Status Registet cssee 15 Configuration Control Registet s 008 16 Configuration Data ooooococooninnonnoncnranonnnancnennnos 16 Flash Status1 Registet ccscessseesseeeees 17 Flash Status2 Register 1 cccssessseeeseeeees 17 Flash Read eiicic i occ cenedessccccreedencteneedsccsceeteeecectone 17 Flash Reset so coc0oorcarmaconimiciacccsrierrnnta ci 17 Flash Start WiitO oooooonocccnnnonnonononconnnnnnnnnnens 18 Flash Erase Sector ooccononconnconnanonnononanananennns 18 Flash Erase ChiP oocococccconcocccononnancnnonnnananennns 18 Flash Data ReQiSter ccc
42. escececeeeseeeeeeeeeeeneees 19 Flash Address Registet s scccssseeeeeeseeee 19 Reset Register ceceeeceececsssseeeeeesseeseenenes 20 Rear Connector Read Register 2 0 00 21 Rear Connector Write Register 21 DMA Control Register o coocococcononnannanononoos 22 PLX PCI9656 DMA Setup Registers 22 DMA Transfer Size RegiSterS oooommccconionismmomm 23 DUAL PORT MEMORY cocccocciccncnccnnenanccnnnenennnnnnnns 24 Dual Port SRAM Control Register 24 Dual Port SRAM Internal Address Register 25 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module 3 Dual Port SRAM DMA Threshold Registers 25 Dual Port SRAM Address Reset Registers 26 Dual Port SRAM Read Registers o 26 DDR SDRAM MEMORY cseecsseeeeeeeeeeeeeeees 27 DDR SDRAM Control Register o oocoo o 27 DDR SDRAM Address Register 28 DDR SDRAM Read Registers ocoococcoocomoo 30 DDR SDRAM Write RegisterS ccoccococoo 31 DDR SDRAM Mask Register omcocccocooconoo 32 STATIC RAM MEMORY oconaocccccccccconnnnenancnennnannnnnnnos 32 Dual Port Memory ocomcncncnconconononcnnnnennennnnonas 32 Dual Port SRAM DMA Transfer Example 33 PCI9656 REGISTERS cccoooncccococcconnnnonnanncnnnnonnnannans 34 4 0 THEORY OF OPERATIO
43. ex 4 Based FPGA PMC Module This memory map reflects byte accesses using the Little Endian byte ordering format Little Endian uses even byte addresses to store the low order byte The Intel x86 family of microprocessors uses Little Endian byte ordering In Big Endian the lower order byte is stored at odd byte addresses If using a Power PC platform and performing DMA transfers of DP SRAM data you will need to switch the PLX PCI9656 to the Big Endian convention The PLX chip provides a Big Little Endian descriptor to control Big Little Endian data formats See the PLX PCI9656 DMA Setup Registers section of this manual or the PCI9656 user manual Flash Configuration The LX SX board uses a flash configuration device to store programming information for the Xilinx FPGA The flash configuration device and FPGA are hardwired together so that during power up the contents of the configuration device are downloaded to the FPGA The flash configuration data can be reprogrammed using the PCI bus interface The following is the general procedure for reprogramming the flash memory and reconfiguration of the Xilinx FPGA 1 Disable auto configuration by setting bit 0 Stop Configuration of the Configuration Control register to logic high 2 Clear the Xilinx FPGA of its previous configuration by setting the Configuration Control register bit 2 to logic high Software must also keep bit 0 set to a logic high 3 Read INIT as logic high Bit 1 of
44. g provides a software product sold separately to facilitate the development of Windows 2000 XP Vista 7 applications accessing Acromag PMC and XMC I O board products PCI and PCle I O Cards and CompactPCI I O Cards This software Model PCISW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLs that are compatible with a number of programming environments including Visual C Visual Basic Borland C Builder and others The DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers Acromag provides a software product sold separately consisting of board VxWorks software This software Model PMCSW API VXW is composed of VxWorks real time operating system libraries for all Acromag PMC and XMC l O board products PCI and PCle I O Cards and CompactPCI I O Cards The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PCI and PCle boards Acromag provides a software product sold separately consisting of board QNX software This software Model PMCSW API QNX is composed of QNX real time operating system libraries for all Acromag PMC and XMC I O board products PCI and PCle I O cards and CompactPCI I O cards The software supports X86 PCI bus only and is implemented as library of C functions which
45. gister 0 and the DMA Ch 1 Threshold Register is not equal to the Address Reset Register 1 If these registers are equal and automatic reset is enabled an infinite loop will be created within the internal logic of the FPGA Rear I O channels 0 to 15 can be sampled and written to SRAM if enabled via this bit The SRAM Internal Address register must also be set with the start address at which the data begins filling the SRAM Writing to the SRAM from the Rear I O port will automatically be disabled upon reaching the DMA Channel 1 Threshold value Reset on DMA Thresholds bit 3 and bit 4 of this register should not be enabled Disable Rear I O write to SRAM Enable Rear I O write to SRAM If enabled via this bit a DMA channel 0 request will be issued when the internal address counter is equal to the DMA Channel 0 Threshold Register This will have the same effect as writing a 1 to bit O of the DMA Control Register See Synchronous DP SRAM in Section 4 0 for further details on ing this feature Disable Auto DMA Request Channel 0 Enable Auto DMA Request Channel 0 If enabled via this bit a DMA Channel 1 request will be issued when the internal address counter is equal to the DMA Channel 1 Threshold Register This will have the same effect as writing a 1 to bit 1 of the DMA Control Register Disable Auto DMA Request Channel 1 Enable Auto DMA Request Channel 1 If enabled via this bit the Internal Address Counter w
46. h Reset Flash Start Write Flash Erase Sector Flash Erase Chip Flash Data Register Flash Address 7 gt 0 Flash Address 15 gt 8 Flash Address 22 gt 16 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 002C 0030 0034 Not Used 0038 l Not Used y 7FFF Not Used 7FFC Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module 1 3 Addr MEMORY MAP Software Reset and Status Register Table 3 2 Example Design Memory Map Mezzanine Module 1 The board will return O for Memory Space all addresses that are Not Used Rear I O Connector Read Register Rear I O Connector Write Register DMA Control Register DMA Transfer Size Channel 0 DMA Transfer Size Channel 1 DP SRAM Control Register DP SRAM Address Register DMA Channel 0 Threshold Register DP SRAM DMA Channel 1 Threshold Register DP SRAM Address Reset Register 0 DP SRAM Address Reset Register 1 DP SRAM DP SRAM Read Register DDR SDRAM Control Register DDR SDRAM Address Register DDR SDRAM Read Registers DO D1 D2 D3 DDR SDRAM Write Registers DO D1 D2 D3 DDR SDRAM Mask Register 8084 90000 Not Used FFFFC 100000 100003 y Static RAM M y 1FFFFF iad i 1FFFFC Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 4 PMC LX SX User s Manual Virt
47. has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed ina burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier CPU board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a good technique to isolate a faulty board If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Acromag s application engineers can also be contacted directly for technical assistance via telephone or email Contect information is listed at the bottom of this page When needed complete repair services are also available Virtex 4 Based FPGA PMC Module 3 CLOCK CONTROL 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE PRELIMINARY SERVICE PROCEDURE CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WA Erb Seed P Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 8
48. ic 0 Bit s FUNCTION Table 3 6 Flash Status 2 Not Used bits are read as logic 0 Register Busy Ready Set bit 0 of the Configuration Control register to logic 1 before monitoring this busy bit 0 Flash Chip is Ready Flash Chip is Busy Flash Read Read Only PCIBAR2 14H A Flash Read command is executed by reading this register at base address plus 14H Prior to issue of a Flash Read the Flash Address registers must be set with the desired address to be read See the Flash Address registers at base address plus 2CH 30H and 34H The system must issue the Flash Reset command to re enable the device for reading array data if DQ5 goes high DQ5 can go high during a Flash Start Write Flash Erase Chip or Flash Erase Sector operation DQ5 can be monitored via the Flash Status 1 register at base address plus OCH Flash Reset Write Only PCIBAR2 18H This write only register is used to initiate a reset of the flash chip A Flash Reset command is executed by writing logic 1 to bit 0 of this register at base address plus 18H Writing the flash reset command resets the chip to reading data mode Flash reset can be useful when busy is held active Busy can be held active when write of a logic high is executed to a bit that is currently a logic low The only way to set bits to logic high is by way of a Flash chip erase Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com ht
49. ill be loaded with the value in Address Reset Register O when the counter is equal to the DMA Channel 0 Threshold Register See the Address Reset Register description for further details The DMA does not have to be enabled to use this feature Disable Add Reset on DMA Ch 0 Threshold Enable Add Reset on DMA Ch 0 Threshold If enabled via this bit the Internal Address Counter will be loaded with the value in Address Reset Register 1 when the counter is equal to the DMA Channel 1 Threshold Register See the Address Reset Register description for further details The DMA does not have to be enabled to use this feature Logic 0 Disable Add Reset on DMA Ch 1 Threshold Logic 1 Enable Add Reset on DMA Ch 1 Threshold DMA Burst Control Logic 0 DMA Performed Without Burst Logic 1 DMA Burst Transfer Enabled 6 15 Not Used Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Dual Port SRAM Internal Address Register Read Write PCIBAR2 8044H The Dual Port SRAM Internal Address Register is used to view and set the internal SRAM address The FPGA will only write using 32 bit data transfers allowing for 3FFFFH 2 unique memory accesses Reading bits 0 to 17 of this register will return the internal SRAM address Due to delays during data processing and the PCI transfer the actual internal address may be slightly greater than the re
50. ing a different row in the same bank When the controller detects an incoming address that refers to a row in a bank other than the currently opened row the controller issues a precharge to deactivate the open row and then issues another Active command to the new row Write The write burst access is initiated to the active row The value on BA1 and BAO selects the bank address while the value on A9 to AO selects the starting column location in the active row See bit A10 above for precharge description Read The read burst access is initiated to the active row The value on BA1 and BAO selects the bank address while the value on A9 to AO selects the starting column location in the active row See bit A10 above for precharge description No Operation NOP Virtex 4 Based FPGA PMC Module 29 BIT FUNCTION DDR SDRAM Command Table 3 14 Continued DDR SDRAM Address Command Register Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 0 PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module Table 3 15 DDR SDRAM Read Registers DDR SDRAM Read Registers Read Only PCIBAR2 8064H to 8070H The four DDR SDRAM Read registers are read only and hold the last four data values read from the DDR SDRAM The DDR SDRAM is set for a burst of four for the purposes of this design example A DDR SDRAM read is implemented by executing the following steps 1 Issue a
51. link with existing user code to make possible simple control of all Acromag PCI and PCle boards Acromag provides a software product consisting of board Linux software This software Model PMCSW API LNX is composed of Linux libraries for all Acromag PMC and XMC I O board products PCI and PCle I O cards and CompactPCI I O cards The software supports X86 PCI bus only and is implemented as library of C functions which link with existing user code to make possible simple control of all Acromag PCI and PCle boards Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the
52. ly in the sector specified A flash bit cannot be programmed from logic O back to logic 1 Only an erase chip operation can convert logic O back to logic 1 Prior to reprogramming of the flash chip a Flash Erase Chip or Flash Erase Sector command must be performed The system can determine the status of the erase operation by reading the Flash Ready Busy status Bit 7 of the Flash Status 2 register at base address plus 10H will read as logic 0 when chip erase is completed Any other flash commands written to the flash chip during execution of the flash erase sector operation are ignored Note that a hardware reset during the erase sector operation will immediately terminate the operation Flash Erase Chip Write Only PCIBAR2 24H This write only register is used to erase the entire contents of the flash chip A flash bit cannot be programmed from logic 0 back to logic 1 Only an erase chip operation can convert logic 0 back to logic 1 Prior to reprogramming of the flash chip a Flash Erase Chip command must be performed A Flash Erase Chip command is executed by writing logic 1 to bit 0 of this register at base address plus 24H Verify that the Flash Chip is not busy from a previous operation before beginning a new operation This is accomplished by reading bit 7 as logic 0 of the Flash Status 2 register Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Vi
53. ndom access memory SRAM is included One port of the SRAM provides a direct link from the PCI bus to the SRAM memory The second port of the SRAM provides a direct link to the Xilinx FPGA e Interface to Front Multifunction Modules Various mezzanine modules ordered separately allow the user to select the Front I O required for their application e Interface to Rear P4 Connector Bank 5 of the FPGA is directly connected to 64 pins of the rear P4 connector All 2 5volt IO standards supported by the Virtex 4 device are available The example design provides low voltage differential signaling as 16 LVDS input and 16 LVDS output signals e Write Disable Jumper User configurable flash and EEPROM board memory can be hardware write disabled by removal of an on board zero ohm surface mount resistor e Example Design Provided The example VHDL design includes implementation of the PCI9656 Local bus interface control of digital I O Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module D SRAM read write interface logic and DDR SDRAM memory interface controller e PCI Bus Master The PCI9656 PCI interface chip becomes the bus master to perform DMA transfers PCI INTERFACE FEATURES e DMA Operation The PCI9656 supports two independent DMA channels capable of transferring data from the PCI to Local bus and Local to PCI bus
54. nnel settings Reading from this register is possible via 32 bit 16 bit or 8 bit data transfers Rear Connector Write Rear Connector Read Table 3 8 Rear I O Registers near aneao Register Register 3 Output Channels Input Channels Column 1 identifies the write 0 data bit that drives the output channel listed in column 2 Column 1 also identifies the read data bit that returns the input channel listed in column 3 For example data bit 0 drives output channel 1 when written and returns channel 1 register setting when read 1 All bits labeled Not Used will return logic O when read 7 2 3 4 5 6 7 8 26 28 30 31 Not Used Not Used Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 2 PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module DMA REGISTERS DMA REGISTERS Table 3 9 PCI9656 DMA Register Setup Values Big Endian Mode will be required for Power PC system Note that any registers bits not mentioned may remain at the default value This is not an all inclusive list Other DMA features are available that are not listed See the PCI9656 manual for more details DMA transfers must start aligned to a Lword boundary Every time you need to perform a new demand mode DMA transfer you must reset the DMA Channel Start bit DMA Control Register Read Write PCIBAR2 8034H The
55. nx configuration memory and set Local Bus Hold control This Configuration Control register is accessed at base address plus 04H Table 3 4 Configuration Bit s FUNCTION Control Register Stop Xilinx Configuration 0 Enable Xilinx FPGA configuration Stop Xilinx FPGA configuration Not Used bit is read as logic 0 2 Clear Current Xilinx Configuration Logic low has no effect Logic high resets the Xilinx configuration logic Re configuration can begin after INIT transitions high Not Used bits are read as logic 0 Local Bus Hold Control CPLD controls generation of Local Hold Acknowledge The CPLD logic will always grant control of the local bus to the PCI9656 device Xilinx FPGA controls generation of the Local Hold Acknowledge signal Configuration Data Write Only PCIBAR2 08H This write only register is used to write Xilinx configuration data directly to the Xilinx FPGA from the PCI bus The Configuration Data register is accessed at base address plus 08H The entire configuration file must be written to the Xilinx FPGA one byte at a time Configuration complete is verified by reading DONE bit 0 of Configuration Status Register as logic high A write to the Configuration Data register while auto configuration from Flash is active will cause the Xilinx configuration to fail Auto configuration is stopped by writing logic 1 to bit O of the Configuration Control register at base address plus 04H
56. om PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module 9 This connector is a 64 pin female receptacle header AMP 120527 1 or equivalent which mates to the male connector on the carrier CPU board AMP 120521 1 or equivalent The board is non isolated since there is electrical continuity between the logic and field I O grounds As such the field I O connections are not isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections Powering the PMC LX SX as an independent board is possible using the J7 board through holes As an independent standalone board the PMC LX SX board would not be plugged into a PMC slot It must in this case receive power though the J7 contact holes and provide passive resistive pullups on all PCI bus signals required to be pulled up by the system card Note the board could be damaged if the required pull up resistors are not used To independently power the board the required 5 volt and 3 3 volt power supplies must be provided via the J7 contact holes The holes have 29 mil openings with 60 mil pads The location of the J7 contact holes on the board are shown in diagram 4502 053 at the end of this manual This Section provides the specific information necessary to program and operate the board GETTING STARTED 1 The PMC LX SX board is shipped with Xilinx FPGA code stored in flash memory Upon
57. ot Used Write and Mask registers must first be written with the will return logic 0 when desired data that are burst out to the DDR SDRAM In g addition the DDR SDRAM Address register must be read written with the write address and command prior to setting this bit Logic 0 No operation performed Logic 1 Write Transfer Performed Start DDR SDRAM read operation The Address Register must be written with the start address location and the read command prior to setting this bit The DDR SDRAM Read registers are filled with four data words that are burst out from the DDR SDRAM Logic 0 No operation performed Logic 1 Read Transfer Performed Start DDR SDRAM command operation A precharge or active command loaded into the Address Register can be initiated by setting this bit Command Performed Logic 0 No operation performed Logic 1 Not Used WDF_Almost_Full DDR Write data FIFO is almost full when this bit is Logic 1 AF_Almost_Full DDR Address FIFO is almost full when this bit is Logic 1 DDR burst length Logic 001 Burst Length 2 Logic 010 Burst Length 4 Logic 011 Burst Length 8 DDR SDRAM Error Status Logic 0 No Error Logic 1 Error Condition 30 29 28 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 8 PMC LX SX User s Manual
58. power up the PMC LX SX will automatically configure the FPGA with the example design code stored in flash As a first step become familiar with the PMC LX SX as suppplied by Acromag The board will perform all the functions of the example design The Example Design Memory Map section gives a description of the I O operations performed by the example design It will allow testing of digital I O interrupts read write of dual port SRAM read write of double data rate SDRAM and testing of both DMA channels It is strongly recommended that you become familiar with the board features by using the example design as provided by Acromag Do not attempt to reconfigure the flash memory until after you have tested and become familiar with the PMC LX SX as provided in the example design 2 After you are familiar with the PMC LX SX and have tested it using the example design you can move on to step 2 Here you will modify the example design VHDL code slightly It is recommended that you test this modified example design using the reconfiguration direct method It is not recommended that the flash be overwritten until you have tested your code The reconfigure direct method will allow programming of the FPGA directly from the PCI bus If for some reason the PMC LX SX does not perform as expected you can power the PMC LX SX down Upon power up the example design provided by Acromag will again be loaded into the FPGA Non Isolation Considerations
59. riting this register is possible via 32 bit 16 bit or 8 bit data transfer Flash Address 22 gt 16 Read Write PCIBAR2 34H This read write register sets bits 22 to 16 of the address to which the flash chip is written upon issue of a Flash Start Write command The most significant bit of this register is not used Although only the least significant 7 bits of this register are used reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfer Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 20 PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module RESET REGISTER Table 3 7 Software Reset and Status Register 1 All bits labeled Not Used will return logic 0 when read DMA INTERRUPT REGISTERS Software Reset and Status Register Read Write PCIBAR2 8000H This read write register is used to Software reset the board monitor the status of board interrupts and monitor the temperature of the Xilinx virtex 4 FPGA Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Mezzanine interrupt status is identified via data bits O to 7 Read of a 1 indicates that an interrupt is pending for the corresponding data bit A pending interrupt will remain active until disabled via the mezzanine interrupt control registers Logic 0 Interrupt Not Pending Logic 1 Interrupt Pending
60. rtex 4 Based FPGA PMC Module 1 9 The system can determine the status of the erase operation by reading the Flash Ready Busy status Bit 7 of the Flash Status 2 register at base address plus 10H will read as logic 0 when chip erase is completed FLASH REGISTERS Any other flash commands written to the flash chip during execution of the flash erase chip operation will be ignored Note that a hardware reset during the chip erase operation will immediately terminate the operation Flash Data Register Read Write PCIBAR2 28H This read write register holds the data byte which is sent to the flash chip upon issue of a Flash Start Write command Although only the least significant 8 bits of this register are used reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfer Flash Address 7 gt 0 Read Write PCIBAR2 2CH This read write register holds the least significant byte of the address to which the flash chip is written upon issue of a Flash Start Write command Although only the least significant 8 bits of this register are used reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfer Flash Address 15 gt 8 Read Write PCIBAR2 30H This read write register sets bits 15 to 8 of the address to which the flash chip is written upon issue of a Flash Start Write command Although only the least significant 8 bits of this register are used reading or w
61. s EA o5 LU S Sea e a Ll Duo ES ro OR s 127 o x a NI S oo z grz Quo sic Eno o ma a A e oaz ose SES re or S gt E a lt w o uE Lo a 2 oe A oO uy lt M uy a a al OF ua o coil 5 o 2 w w 2 gt w Ez a gt zo 22 o oja z n a z 2 o os z o a gt z sexe Cox N E x ON S T lt X az G n Ai o a E e SE S 5 2 o 2 gt o o o Sas oc pa wd rey ad a o br o 2 o sgo a gt lt a oof o ES o lt ao o no via a ao o wo a ak a 2 o rl a o Lan Q 2 o o o 5 2 AA A A d o S o lt E o uu n R n oc gt zw wz lt a va zx oo 0 a o 3 3V CRYSTAL REAR 1 0 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 4 2 PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module J4 o J2 casallc254 coselcasalicas7 J3 J1 le
62. s to C Mode configuration apply to the LX SX boards The LX SX boards use the C Mode generic 32 bit non multiplexed address and data bus interface for communication between the PCI9656 and the Xilinx FPGA The default power up condition of the LX SX board enables the on board 66MHz crystal as the active clock The active clock is used to clock the PCI9656 Local bus SRAM interface CPLD operation and FPGA operation After configuration the on board 66MHz can be deselected and a Xilinx FPGA generated clock PLL_CLK signal can be selected as the new active board clock Clock signal selection is controlled via the PCI9656 USERo signal The USERo control signal output from the PCI9656 is used to select between the 66MHz clock and the user defined clock PLL_CLK The user defined clock must be defined in the FPGA and output from the FPGA on signal PLL_CLK The Digital Clock Manager of the FPGA offers a wide range of clock management features including clock multiplication and division for generation of a user defined clock PLL_CLK A 66MHz crystal generated clock signal FPGA_CLK_PLL is input to the FPGA for use in generation of the user defined clock signal PLL_CLK The PLL_CLK can be a minimum of 10MHz and a maximum of 100MHz Since the PLL_CLK signal is generated and driven by the FPGA it will only be available after the FPGA is configured See the example VHDL file included in the engineering design kit and the Xilinx documentation on the
63. ster will return the corresponding DMA Threshold Writing to bits 0 through 17 of this register will set the corresponding DMA Threshold to the provided value Reading or writing to this register is possible via 32 bit data transfers only Virtex 4 Based FPGA PMC Module 2 5 DP SRAM REGISTERS Warning To guarantee functionality disable DP SRAM write cycles via bit 0 of the DP SRAM Conirol Registers before writing to the DP SRAM Internal Address Register Table 3 11 Dual Port SRAM Internal Address Register Note A SRAM DMA Request will occur only after a data write cycle to the address defined by the DMA Threshold Registers Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 26 PMC LX SX User s Manual Table 3 12 Dual Port DMA Threshold Registers DP SRAM REGISTERS WARNING The DMA Ch 0 Threshold Register must not equal the Address Reset Register 0 and the DMA Ch 1 Threshold Register must not equal the Address Reset Register 1 If these registers are equal and the address reset is enabled via the DP SRAM Control Register an infinite loop will be created within the internal logic of the FPGA Virtex 4 Based FPGA PMC Module Dual Port SRAM DMA Channel 0 1 Threshold Registers D31 D18 D17 DO Reset Value DMA Channel 0 Not Used Read Channel 0 FFFFH Threshold Reg as logic 0 Threshold Address DMA Channel 1 Not Used Read Channel
64. ter operational speed but does cause a one cycle delay during read operations The pins corresponding to the control signals address and data buses are in the user constraint UCF file provided in the engineering design kit The SRAM port connected directly to the FPGA supports continuous writes or single cycle reads The SRAM port connected to the local bus and the PCI9656 IC supports reading and writing using a single cycle or DMA transfers For single cycle accesses address and control signals are applied to the SRAM during one clock cycle and either a write will occur on the next cycle or a read in two clock cycles DMA accesses operate using the continuous burst method for maximum data throughput The control signal starting address and data if writing are applied to the SRAM during one clock cycle Then during a write DMA transfer new data is applied by the PCI9656 to the bus every subsequent clock cycle until the transfer is complete If a DMA read transfer is occurring then there would be a two cycle delay before the data was available on the bus After the initial delay every subsequent clock cycle will contain the data from the next address During DMA transfers the address is held constant on the local bus and incremented internally in the Dual Port SRAM Please refer to the IDT70T3519S133BC Data Sheet and PCI9656 Data Sheet See Related Publications for more detailed information A 128 x 16 bit Serial EEPROM is wired to th
65. tp www acromag com 1 8 PMC LX SX User s Manual Virtex 4 Based FPGA PMC Module FLASH CONTROL REGISTERS Flash Start Write Write Only PCIBAR2 1CH This write only register is used to initiate the write of a byte to the flash chip A Flash Start Write command is executed by writing logic 1 to bit 0 of this register at base address plus 1CH Prior to issue of a Flash Start Write the Flash Data and Address registers must be set with the desired data and address to be written See the Flash Data and Address registers at base address plus 28H 2CH 30H and 34H Issue of a Flash Start Write will automatically increment this address after the issued Flash Write has completed Thus the address will not need to be set prior to issue of the next Flash Start Write if consecutive addresses are to be written Flash Erase Sector Write Only PCIBAR2 20H A Flash Erase Sector command is executed by writing logic 1 to bit 0 of this register at base address plus 20H Verify that the Flash Chip is not busy from a previous operation before beginning a new operation This is accomplished by reading bit 7 as logic 0 of the Flash Status 2 register There are 128 flash sectors which are addressed via the most significant seven flash address lines The most significant seven flash address lines are set via the Flash Address 22 16 register at base address plus 34H Issue of a Flash Erase Sector command will erase the contents of the flash chip on
66. wing 4502 054 as you OPERATION review this material A PLX Technology PCI9656 IC installed on the board provides a 66MHz PCI INTERFACE LOGIC 64 bit interface to the carrier CPU board per PCI Local Bus Specification 2 2 The interface to the carrier CPU board allows complete control of all board functions The PCI9656 is compliant with both 5V and 3 3V signaling The PCI bus VIO signals are tied directly to the PCI9656 chip which monitors the voltage present on VIO to automatically implement the matching signaling voltage Note that the LX SX board requires that system 3 3 volts be present on the PCI bus 3 3V pins There are some older systems that do not provide 3 3 Volts on the PCI bus 3 3 volt pins The LX SX boards will not work in these systems This is a master target board with the PCI bus interface logic contained within the PCI9656 This logic includes support for PCI commands including configuration read write and memory read write In addition the PCI interface performs parity error detection uses a single 2Meg base address register PCIBAR2 and implements target abort retry and disconnect The logic also implements interrupt requests via interrupt line INTA The PCI9656 becomes the PCI bus master to perform DMA transfers on channels 0 and 1 The DMA control registers of the PCI9656 chip can be configured for DMA block mode and demand mode The example device driver can be used to exercise DMA block and demand modes of

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