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UM10334 P89LPC9301/931A1 User manual

1. Table 55 Master Transmitter mode continued Status code Status of the I2C Application software response Next action taken by I2C I2STAT hardware to from I2DAT to I2CON hardware STA STO 8 30h Data byte in Load data byte 0 0 0 Data byte will be transmitted I2DAT or ACK bit will be received transmitted has been no I2DAT action 1 0 0 Repeated START will be received or transmitted no I2DAT action 0 1 0 STOP condition will be or transmitted STO flag will be reset nol2DAT action 1 1 0 STOP condition followed by a START condition will be transmitted STO flag will be reset 38H Arbitration lostin No I2DAT action 0 0 0 I C bus will be released not SLA R W ordata or addressed slave will be bytes entered No l2DAT action 1 0 0 A START condition will be transmitted when the bus becomes free Table 56 Master Receiver mode Status code Status of the IPC Application software response Next action taken by I C hardware I2STAT hardware to from I2DAT I2CON STA STO 1 STA 08H A START Load SLA R X 0 0 x SLA R will be transmitted ACK bit condition has will be received been transmitted 10H A repeat START Load SLA R or X 0 0 X As above condition has Load SLA W SLA W will be transmitted 2C bus been transmitted will be switched to Master Transmitter Mode 38H Arbitration lostin no I2DAT action 0 0 0 x I2C bus will be released it will enter NOT ACK bit Or a slave mode no I2DAT act
2. 29 Power monitoring functions 30 Brownout 30 Power on detection 31 Power reduction modes 31 FROSOU DT 34 Reset 35 Timers 0 and1 36 0 37 Mode 1 37 Mode 2 ee Gee adie VR 38 Mod ER ae RE 38 All information provided in this document is subject to legal disclaimers 7 5 7 6 8 1 8 2 8 3 8 3 1 8 4 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 10 9 11 9 12 9 13 9 14 9 15 9 16 9 17 9 18 9 19 9 20 10 10 1 10 2 10 3 10 4 10 5 10 6 10 6 1 10 6 2 10 6 3 10 6 4 11 11 1 11 2 Mode 6 38 Timer overflow toggle output 40 Real time clock system timer 40 Real time clock source 41 Changing RTCS1 RTCSO 42 Real time clock interrupt wake up 42 Real time clock read back 42 Reset sources affecting the Real time clock 42 io 44 Mode Qi ERR ed i ERU 44 Mode Tai eis LP 44 M de2 i oiresse eaten ee Sa 44 3 2 2 nen itd REPE 45 SER Space s iss rli bo E RR REI 45 Baud Rate generator and selection 45 Updating the BRGR1 and BRGRO SFRs 45 Framing 46 Break detect
3. 46 More about UART 0 48 More about UART Mode 1 49 More about UART Modes 2and3 50 Framing error and RI in Modes 2 and 3 with SM2 zu ccm uter eu LUN E E 50 Break detect 51 Double buffering 51 Double buffering in different modes 51 Transmit interrupts with double buffering enabled Modes 1 2 3 51 The 9th bit bit 8 in double buffering Modes 1 2 andi9 s netu ek RE xr euh 52 Multiprocessor communications 53 Automatic address recognition 54 2 55 12 data register 56 2 slave address register 56 2 control register 57 2 Status register 58 12C SCL duty cycle registers 25 and l2 SOLI cies tegen eens ee 58 2 operation modes 59 Master Transmitter mode 59 Master Receiver mode 60 Slave Receiver mode 61 Slave Transmitter mode 62 Serial Peripheral Interface SPI 69 Configuring the 73 Additional considerations foraslave 74 continued gt gt NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 118 of 119 NXP Semiconductors UM10
4. 56 Table 11 Summary of interrupts 24 Table 46 I C slave address register I2ADR address DBh Table 12 Number of I O pins available 25 bit allocation 56 Table 13 Port output configuration settings 26 Table 47 12 slave address register IZADR address DBh Table 14 Port output configuration 29 bit 56 Table 15 BOD Trip points configuration 31 Table 48 12C Control register 2 address D8h bit Table 16 BOD Reset and BOD Interrupt configuration 31 57 Table 17 Power reduction modes 32 Table 49 12C Control register IICON address D8h bit Table 18 Power Control register PCON address 87h bit lt 57 allocation ma 33 Table 50 I C Status register IPSTAT address D9h bit Table 19 Power Control register PCON address 87h bit allocation 58 description 33 Table 51 I C Status register 25 address D9h bit Table 20 Power Control register A PCONA address B5h 58 bit allocation 33 Table 52 12C clock rates selection 59 Table 21 Power Control register A PCONA
5. 62 Fig 30 I C serial interface block diagram 63 Fig 31 SPI block diagram 70 Fig 32 SPI single master single slave configuration 72 Fig 33 SPI dual device configuration where either can be a master 5 72 Fig 34 SPI single master multiple slaves configuration 73 Fig 35 SPI slave transfer format with CPHA 2 0 76 Fig 36 SPI slave transfer format with 1 77 Fig 37 SPI master transfer format with CPHA 20 78 Fig 38 SPI master transfer format with CPHA 2 1 79 Fig 39 Comparator input and output connections 80 Fig 40 Comparator configurations Suppose PGA1 is disabled or gain 2 1 82 Fig 41 Watchdog 85 Fig 42 Watchdog Timer in Watchdog Mode WDTE 1 89 Fig 43 Watchdog Timer in Timer Mode WDTE 0 90 Fig 44 Forcing ISP mode 98 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 117 of 119 NXP Semiconductors UM10334 21 Contents P89LPC9301 931A1 User manual 2 10 2 11 3 1 3 2 4 1 4 2 4 3 4 4 4 5 4 6 4 7 5 1 5 2 5 3 6 1 7 1 7 2 7 3 7 4 UM10334 Introduction 3 Pin 3 Pin
6. write to SBUF shift transmit tart TXB Lo X Di X 02 X X 04 X X 05 07 Y TI 4 INTLO 0 INTLO 1 clock sum RXD Bt X Di gt X_ba X 04 X Ds X X B7 sop RI receive 002aaa926 Fig 21 Serial Port Mode 1 only single transmit buffering case is shown 9 12 More about UART Modes 2 and 3 Reception is the same as in Mode 1 The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated a RI 0 and b Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SBUF write to SBUF shift l l l l transmit tart TxD Xo XC 02 X 05 X04 05 X 06 X07 X 188 Y sop Bh __ INTLO 0 INTL RX TL m mp nm m m mnm m m m m Ig RXD ut Do X Di X 02 X D3 X D4 X Ds X 06 X DT X RES a pum SMODO 0 SMODO 1 002 927 Fig 22 Serial Port Mode 2 or 3 only single transmit buffering case is shown 9 13 Framing error and RI in Modes 2 and 3 with SM2 1 If SM2 1 in modes 2 and 3 RI and FE behaves as in the following table UM1
7. Table 81 Flash Memory Control register FMCON address E4h bit description Bit Symbol Access Description 0 OI R Operation interrupted Set when cycle aborted due to an interrupt or reset FMCMD 0 W Command byte bit 0 1 SV R Security violation Set when an attempt is made to program erase or CRC a secured sector or page FMCMD 1 W Command byte bit 1 2 HVE R High voltage error Set when an error occurs in the high voltage generator FMCMD 2 W Command byte bit 2 3 HVA R High voltage abort Set if either an interrupt or BOD FLASH is detected during a program or erase cycle FMCMD 3 W Command byte bit 3 47 R reserved 4 FMCMD 4 Command byte bit 4 5 FMCMD 5 W Command byte bit 5 6 FMCMD 6 W Command byte bit 6 7 FMCMD 7 W Command byte bit 7 An assembly language routine to load the page register and perform an erase program operation is shown below XE ORE OE ERASER EEE AALS EERE EEE ERE ERE SERS A ER oe pgm user code SALE Inputs R3 number of bytes to program byte R4 page address MSB byte R5 page address LSB byte R7 pointer to data buffer in RAM byte Outputs status byte C clear on no error set on error i hE REESE REE ERLE SEAL ESE ERE LER EERE LAER ERE SE EIR ERK LOAD EQU 00H EP EQU 68H PGM_USER OV FMCON LOAD load command clears page register OV FMADRH R4 get high address Ov FMADRL R5 get low address MOV A R7 i OV RO A get point
8. 0 X STOP condition will be transmitted NACK has been STO flag will be reset returned read data byte 1 1 0 STOP condition followed by START condition will be transmitted STO flag will be reset Table 57 Slave Receiver mode Status code Status of the IPC Application software response Next action taken by 2 I2STAT hardware to from I2DAT to ICON hardware STA STO 51 AA 60H Own SLA W has nol2DAT action x 0 0 0 Data byte will be received and NOT been received or ACK will be returned ACK has been I2DAT action 0 0 1 Data byte will be received received will be returned 68H Arbitration lostin No I2DAT action x 0 0 0 Data byte will be received and NOT SLA R Was or ACK will be returned master Own no I2DAT action 0 0 1 Data byte will be received and ACK SLA W has been will be returned received ACK returned 70H General call Nol2DAT action x 0 0 0 Data byte will be received and NOT address 00H has or ACK will be returned been received I2DAT action 0 0 1 Data byte will be received ACK has been will be returned returned 78H Arbitration lostin l2DAT action x 0 0 0 Data byte will be received and NOT SLA R W as or ACK will be returned master General nojoDAT action 0 0 1 Data byte will be received and ACK call address has will be returned been received ACK bit has been returned 80H Previously Read data byte or x 0 0 0 Data byte will be received and NOT addressed with ACK will be retu
9. SPI STATUS REGISTER MISO P2 3 MOSI P2 2 SPICLK P2 5 55 2 4 SPI interrupt request internal data bus Fig 31 SPI block diagram 002aaa900 UM10334 The SPI interface has four pins SPICLK MOSI MISO and SS SPICLK MOSI and MISO are typically tied together between two or more SPI devices Data flows from master to slave on the MOSI Master Out Slave In pin and flows from slave to master on the MISO Master In Slave Out pin The SPICLK signal is output in the master mode and is input in the slave mode If the SPI system is disabled i e SPEN SPCTL 6 0 reset value these pins are configured for port functions SS is the optional slave select pin In a typical configuration an SPI master asserts one of its port pins to select one SPI device as the current slave An SPI slave device uses its SS pin to determine whether it is selected The SS is ignored if any of the following conditions are true fthe SPI system is disabled i e SPEN SPCTL 6 0 reset value Ifthe SPI is configured as a master i e SPCTL 4 1 and P2 4 is configured as an output via the P2M1 4 and P2M2 4 SFR bits Ifthe SS pin is ignored i e SSIG SPCTL 7 bit 1 this pin is configured for port functions Note that even if the SPI is configured as a master MSTR 1 it can still be converted to a slave by driving the SS pin low if P2 4 is confi
10. Bit Symbol Description 0 reserved 1 SPD Serial Port UART power down When logic 1 the internal clock to the UART is disabled Note that in either Power down mode or Total Power down mode the UART clock will be disabled regardless of this bit 2 SPPD SPI power down When logic 1 the internal clock to the SPI is disabled Note that in either Power down mode or Total Power down mode the SPI clock will be disabled regardless of this bit 3 I2PD 2 power down When logic 1 the internal clock to the I2C bus is disabled Note that in either Power down mode or Total Power down mode the 12C clock will be disabled regardless of this bit 4 reserved UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 33 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 21 Power Control register A PCONA address B5h bit description continued Bit Symbol Description 5 VCPD Analog Voltage Comparators power down When logic 1 the voltage comparators are powered down User must disable the voltage comparators prior to setting this bit 6 reserved RTCPD Real time Clock power down When logic 1 the internal clock to the Real time Clock is disabled 6 Reset The P1 5 RST pin can function as either an active low reset input or as a digital input P1 5 The RPE Reset Pin Enable bit in UCFG1 w
11. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two special Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to be used and which bits are don t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme Table 43 Slave 0 1 examples Example 1 Example 2 Slave 0 SADDR 11000000 Slave 1 SADDR 1100 0000 SADEN 1111 1101 SADEN 11111110 Given 1100 00X0 Given 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1 A unique address for slave 1 would be 1100 0001 since a 1 in bit O will exclude slave 0 Both slaves can be selected at the same time by an address which has bit 0 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000
12. 0 SPICLK CPOL 0 LLL LE LL LE LEP LE LE I SPICLK CPOL 1 ELE TL I DORD 0 MSB v LSB 1 DORD 1 NLSB MSB 002aaa934 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 76 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Clock cycle 1 SPICLK CPOL 0 PLY LE LE Ly SPICLK CPOL 1 LE LI LE LE Ly LI MOSI input MISO output SS if SSIG bit 0 002aaa935 1 Not defined Fig 36 SPI slave transfer format with CPHA 1 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 77 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Clock cycle 1 sriciK croL 0 PE y LE LE LE LEP LE LE I LE TL I MOSI input DORD 0 MSB LSB DORD 1 LSB MSB MISO output SS if SSIG bit 0 4 t 002aaa936 1 Not defined Fig 37 SPI master transfer format with CPHA 0 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 78
13. 00xxxx08cc Where xxxx required field but value is a don t care cc checksum Example 00000008F8 In application programming IAP Several In Application Programming IAP calls are available for use by an application program to permit selective erasing and programming of Flash sectors pages security bits configuration bytes and device id All calls are made through a common interface PGM MTP The programming functions are selected by setting up the microcontroller s registers before making a call to PGM MTP at FFO3H The IAP calls are shown in Table 85 IAP authorization key IAP functions which write or erase code memory require an authorization key be set by the calling routine prior to performing the IAP function call This authorization key is set by writing 96H to RAM location FFH The following example was written using the Keil C compiler The methods used to access a specific physical address in memory may vary with other compilers include ABSACC H enable absolute memory access define key DBYTE OxFF force key to be at address OxFF short pgm mtp void OxFF00 set pointer to IAP entry point key 0x96 set the authorization key pgm mtp execute the IAP function call After the function call is processed by the IAP routine the authorization key will be cleared Thus it is necessary for the authorization key to be set prior to EACH call to PGM MTP that requires a key If
14. 01 UCFG2 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 0B Security Byte 3 OC Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 102 Manufacturer Id 112 Device Id 12 Derivative Id Example 0100000312EA 04 Erase Sector Page 03xxxx04ssaaaacc Where xxxx required field but value is a don t care aaaa sector page address ss 01 erase sector ss 00 erase page cc checksum Example 03000004010000F8 05 Read Sector CRC 01xxxx05aacc Where xxxx required field but value is a don t care aa sector address high byte checksum Example 0100000504F6 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 101 of 119 NXP Semiconductors U M1 0334 UM10334 16 12 16 13 16 14 P89LPC9301 931A1 User manual Table 83 In system Programming ISP hex record formats continued Record type Command data function 06 Read Global CRC 00xxxx06cc Where xxxx required field but value is a don t care cc checksum Example 00000006FA 07 Direct Load of Baud Rate 02xxxx07HHLLcc Where xxxx required field but value is a don t care HH high byte of timer LL low byte of timer cc checksum Example 02000007FFFFF9 08 Reset MCU
15. 7 CLKOK Clock switch completed flag When 1 clock switch is completed When 0 clock switch is processing and writing to register CLKCON is not allowed UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 21 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 9 Oscillator type selection for clock switch FOSC 2 0 Oscillator configuration 111 External clock input on XTAL1 100 Watchdog Oscillator 400 kHz 5 95 011 Internal RC oscillator 7 373 MHz 1 96 010 Low frequency crystal 20 kHz to 100 kHz 001 Medium frequency crystal or resonator 100 kHz to 4 MHz 000 High frequency crystal or resonator 4 MHz to 18 MHz 2 9 Oscillator Clock OSCCLK wake up delay 2 10 2 11 3 Interrupts UM10334 The P89LPC9301 931A1 has an internal wake up timer that delays the clock until it stabilizes depending on the clock source used If the clock source is any of the three crystal selections low medium and high frequencies the delay is 1024 OSCCLK cycles plus 60 us to 100 us If the clock source is the internal RC oscillator the delay is 200 us to 300 us If the clock source is watchdog oscillator or external clock the delay is 32 OSCCLK cycles CPU Clock CCLK modification DIVM register The OSCCLK frequency can be divided down by an integer up to 510 times by configuri
16. Power on detection The Power On Detect has a function similar to the Brownout Detect but is designed to work as power initially comes up before the power supply voltage reaches a level where the Brownout Detect can function The POF flag RSTSRC 4 is set to indicate an initial power on condition The POF flag will remain set until cleared by software by writing a logic 0 to the bit BOF RSTSRO 5 will be set when POF is set Power reduction modes The P89LPC9301 931A1 supports three different power reduction modes as determined by SFR bits PCON 1 0 see Table 17 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 31 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 17 Power reduction modes PMOD1 PMODO Description PCON 1 0 0 0 Normal mode default no power reduction 0 1 Idle mode The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated Any enabled interrupt source or reset may terminate Idle mode 1 0 Power down mode The Power down mode stops the oscillator in order to minimize power consumption The P89LPC9301 931A1 exits Power down mode via any reset or certain interrupts external pins INTO INT1 brownout Interrupt keyboard Real time Clock System Timer watchdog and comparator trips Waking u
17. Reception is initiated by detecting a 1 to 0 transition on RxD RxD is sampled at a rate 16 times the programmed baud rate When a transition is detected the divide by 16 counter is immediately reset Each bit time is thus divided into 16 counter states At the 7th 8th and 9th counter states the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the receiver goes back to looking for another 1 to 0 transition This provides rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and either SM2 0 or the received stop bit 1 If either of these two conditions is not met the received frame is lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 49 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual TX clock
18. cesado E 92 Flash programming and erase 92 Using Flash as data storage IAP Lite 93 In circuit programming ICP 96 ISP and IAP capabilities of the 891 9 01 931 1 97 Boot 97 Power on reset code execution 97 Hardware activation of Boot Loader 98 In system programming ISP 98 Using the In system programming ISP 98 In application programming IAP 102 IAP authorization key 102 Flash write enable 102 Configuration byte protection 103 IAP error 5 103 User configuration bytes 107 User security 108 Boot Vector register 109 Boot status register 109 Instruction 111 Legal 114 Definitloris 2 s ser ete 114 P89LPC9301 931A1 User manual 18 2 Disclaimers 114 18 3 Trademarks 114 19 Tables uu lm RR tes wend 115 20 FIQ ureS 117 21 Gontenls 118 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information B V 2010 For more
19. 11 Internal RC oscillator UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 42 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 30 Real time Clock System Timer clock sources continued FOSC2 0 RCCLK RTCS1 0 RTC clock source CPU clock source 010 0 00 Low frequency crystal Low frequency crystal 01 DIVM 10 11 Low frequency crystal DIV 1 00 Low frequency crystal Internal RC oscillator 01 10 11 Internal RC oscillator 011 0 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal DIVM 10 Low frequency crystal 11 Internal RC oscillator DIVM 1 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal 10 Low frequency crystal 11 Internal RC oscillator 100 0 00 High frequency crystal Watchdog oscillator 01 Medium frequency crystal DIVM 10 Low frequency crystal 11 Watchdog oscillator DIVM 1 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal 10 Low frequency crystal 11 Internal RC oscillator 101 x XX undefined undefined 110 X undefined undefined 111 0 00 External clock input External clock input 01 DIVM 10 11 External clock input DIVM 1 00 External clock input Internal RC oscillator 01 10 11 Internal RC oscillator Table 31 Real time Clock Control register RTCCON address D1h bit allocation Bit 7 6 5 4
20. 2010 All rights reserved User manual Rev 2 5 November 2010 83 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 71 Keypad Interrupt Mask register KBMASK address 86h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol KBMASK 7 KBMASK 6 KBMASK 5 KBMASK 4 KBMASK 3 KBMASK 2 1 KBMASK 0 Reset 0 0 0 0 0 0 0 0 Table 72 Keypad Interrupt Mask register KBMASK address 86h bit description Bit Symbol Description 0 When set enables 0 as a cause of a Keypad Interrupt 1 KBMASK 1 When set enables PO 1 as a cause of a Keypad Interrupt 2 KBMASK 2 When set enables PO 2 as a cause of a Keypad Interrupt 3 KBMASK 3 When set enables P0 3 as a cause of a Keypad Interrupt 4 4 When set enables PO 4 as a cause of a Keypad Interrupt 5 KBMASK 5 When set enables PO 5 as a cause of a Keypad Interrupt 6 KBMASK 6 When set enables 6 as a cause of a Keypad Interrupt 7 KBMASK 7 When set enables 7 as a cause of a Keypad Interrupt 1 The Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective 14 Watchdog timer WDT The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count The watchdog timer can only be reset by a power on reset 14 1 Wa
21. 7 373 MHz 1 96 010 Low frequency crystal 20 kHz to 100 kHz 001 Medium frequency crystal or resonator 100 kHz to 4 MHz 000 High frequency crystal or resonator 4 MHz to 18 MHz Table 89 Flash User Configuration Byte 2 UCFG2 bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKDBL Unprogrammed 0 X X X X X x x value Table 90 Flash User Configuration Byte 2 UCFG2 bit description Bit Symbol Description 0 6 Not used 7 CLKDBL Clock doubler When set doubles the output frequency of the internal RC oscillator 16 18 User security bytes This device has three security bits associated with each of its eight sectors as shown in Table 91 Table 91 Sector Security Bytes SECx bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x EDISx SPEDISx MOVCDISx Unprogrammed 0 0 0 0 0 0 0 0 value UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 108 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 92 Sector Security Bytes SECx bit description Bit Symbol Description 0 MOVCDISx MOVC Disable Disables the MOVC command for sector x Any MOVC that attempts to read a byte in a MOVC protected sector will return invalid data This bit can only be erased when sector x is erased 1 SPEDISx Sector Program Erase Disable x Disables program or erase of all or par
22. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0 Table 44 Slave 0 1 2 examples Example 1 Slave 0 SADDR SADEN Given UM10334 Example 2 Example 3 1100 0000 Slave 1 SADDR 11100000 Slave 2 SADDR 1100 0000 1111 1001 SADEN 1111 1010 SADEN 1111 1100 1100 0XX0 Given 1110 0X0X Given 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit 0 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 and 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are treated as don t cares In most cases interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 54 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual reset SADDR and SADEN are loaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t cares This effective
23. In this case the data currently being transmitted will continue to be transmitted but the new data i e the one causing the collision will be lost While write collision is detected for both a master or a slave it is uncommon for a master because the master has full control of the transfer in progress The slave however has no control over when the master will initiate a transfer and therefore collision can occur For receiving data received data is transferred into a parallel read data buffer so that the shift register is free to accept a second character However the received character must be read from the Data Register before the next character has been completely shifted in Otherwise the previous data is lost WCOL can be cleared in software by writing a logic 1 to the bit Data mode Clock Phase Bit CPHA allows the user to set the edges for sampling and changing data The Clock Polarity bit CPOL allows the user to set the clock polarity Figure 35 to Figure 38 show the different settings of Clock Phase bit CPHA All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 75 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual Clock cycle 1 MOSI input MISO output SS if SSIG bit 0 1 Not defined Fig 35 SPI slave transfer format with
24. MSTR Master Slave mode Select see Table 64 DORD SPI Data ORDer 1 The LSB of the data word is transmitted first 0 The MSB of the data word is transmitted first 6 SPEN SPI Enable 1 The SPI is enabled 0 The SPI is disabled and all SPI pins will be port pins 7 SSIG 85 10 1 MSTR bit 4 decides whether the device is a master or slave 0 The SS pin decides whether the device is master or slave The SS pin can be used as a port pin see Table 64 Table 61 SPI Status register SPSTAT address E1h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SPIF WCOL 2 s Reset 0 0 x x x x x x Table 62 SPI Status register SPSTAT address Eth bit description Bit Symbol Description 0 5 reserved 6 WCOL _ SPI Write Collision Flag The WCOL bit is set if the SPI data register SPDAT is written during a data transfer see Section 11 5 Write collision The WCOL flag is cleared in software by writing a logic 1 to this bit 7 5 SPI Transfer Completion Flag When a serial transfer finishes the SPIF bit is set and an interrupt is generated if both the ESPI IEN1 3 bit and the EA bit are set If SS is an input and is driven low when SPI is in master mode and SSIG 0 this bit will also be set see Section 11 4 Mode change on SS The SPIF flag is cleared in software by writing a logic 1 to this bit All information provided in this document is subject to legal
25. SPI Data register SPDAT address E3h bit 88h bit allocation 38 allocation seed eae bU IY whe oe 72 Table 29 Timer Counter Control register TCON address Table 64 SPI master and slave selection 7 88h bit description 38 Table 65 Comparator Control register CMP1 address Table 30 Real time Clock System Timer clock sources 42 ACh CMP2 address ADh bit allocation 80 Table 31 Real time Clock Control register RTCCON Table 66 Comparator Control register CMP1 address address 1 bit allocation 43 ACh CMP2 address ADh bit description 80 Table 32 Real time Clock Control register RTCCON Table 67 Keypad Pattern register KBPATN address 93h address D1h bit description 44 bit allocation 83 Table 33 UART SFR addresses 45 Table 68 Keypad Pattern register KBPATN address 93h Table 34 UART baud rate generation 46 bit description 83 Table 35 Baud Rate Generator Control register BRGCON Table 69 Keypad Control register KBCON address 94h address BDh bit allocation 46 bit allocation 83 Table 36 Baud Rate Generator Control register BRGCON Table 70 Keypad Control register KBCON address 94h address BDh bit description 46 bit description 83 UM10334
26. With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow The slaves that weren t being addressed leave their SM2 bits set and go on about their business ignoring the subsequent data bytes Note that SM2 has no effect in Mode 0 and must be logic 0 in Mode 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 53 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual 9 20 Automatic address recognition Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled by setting the SM2 bit in SCON In the 9 bit UART modes mode 2 and mode 3 the Receive Interrupt flag RI will be automatically set when the received byte contains either the Given address or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data
27. address B5h Table 53 12C Control register IBCON address D8h 59 bit description 33 Table 54 I C Control register I2CON address D8h 61 Table 22 Reset Sources register RSTSRC address DFh Table 55 Master Transmitter mode 64 bit allocation 35 Table 56 Master Receiver mode 65 Table 23 Reset Sources register RSTSRC address DFh Table 57 Slave Receiver mode 66 bit description 35 Table 58 Slave Transmitter mode 68 Table 24 Timer Counter Mode register TMOD address Table 59 SPI Control register SPCTL address E2h bit 89h bit allocation 36 allOCAtlON wos sse e Ren dn 70 Table 25 Timer Counter Mode register TMOD address Table 60 SPI Control register SPCTL address E2h bit 89h bit description 36 lt 71 Table 26 Timer Counter Auxiliary Mode register TAMOD Table 61 SPI Status register SPSTAT address E1h bit address 8Fh bit allocation 37 allocation Rechner 71 Table 27 Timer Counter Auxiliary Mode register TAMOD Table 62 SPI Status register SPSTAT address E1h bit address 8Fh bit description 37 lt 71 Table 28 Timer Counter Control register TCON address Table 63
28. and BOOTSTAT If programmed to a logic 1 the writes to these registers are disabled If programmed to a logic 0 writes to these registers are enabled This bit is set by programming the BOOTSTAT register This bit is cleared by writing the Clear Configuration Protection CCP command to FMCON followed by writing 96H to FMDATA Disable Clear Configuration Protection command If Programmed to 1 the Clear Configuration Protection CCP command is disabled during ISP or IAP modes This command can still be used in ICP or parallel programmer modes If programmed to 0 the CCP command can be used in all programming modes This bit is set by programming the BOOTSTAT register This bit is cleared by writing the Clear Configuration Protection CCP command in either ICP or parallel programmer modes UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 110 of 119 NXP Semiconductors UM10334 17 Instruction set P89LPC9301 931A1 User manual Table 98 Instruction set summary Mnemonic Description Bytes Cycles Hex code ARITHMETIC ADD A Rn Add register to A 1 1 28 to 2F ADD AJir Add direct byte to A 2 1 25 ADD A Ri Add indirect memory to A 1 1 26 to 27 ADD A data Add immediate to A 2 1 24 ADDC A Rn Add register to A with carry 1 1 38 to 3F ADDC A dir Add direct byte to A with carry 2 1 35 ADDC
29. except in power down or total power down mode PCON 1 1 It can not be disabled in software BOD FLASH has only 1 trip voltage level of 2 4 V When voltage supply is lower than 2 4 V the BOD FLASH is tripped and flash program erase is blocked If brownout detection is enabled the brownout condition occurs when Vpp falls below the brownout trip voltage and is negated when Vpp rises above the brownout trip voltage For correct activation of Brownout Detect certain Vpp rise and fall times must be observed Please see the data sheet for specifications All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 30 of 119 NXP Semiconductors U M1 0334 5 2 5 3 UM10334 P89LPC9301 931A1 User manual Table 15 BOD Trip points configuration BOE1 BOEO BOICFG1 BOICFGO BOD Reset BOD UCFG1 5 UCFG1 3 BOICFG 1 BOICFG 0 Interrupt 0 0 0 0 Reserved 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 2 2V 2 4V 0 1 1 0 2 2V 2 6V 0 1 1 1 2 2V 3 2V 1 0 0 0 Reserved 1 0 0 1 1 0 1 0 2 4V 2 6V 1 0 1 1 2 4V 3 2V 1 1 0 0 Reserved 1 1 0 1 1 1 1 0 1 1 1 1 3 0V 3 2V Table 16 BOD Reset and BOD Interrupt configuration PMOD1 PMODO PCON 1 0 EBO EA BOD BOD PCON 4 5 IENO 7 Reset Interrupt 11 total power down X X X N N 11 any mode other than total 0 X X Y N power down 1 0 X Y N X 0 Y N 1 1 Y Y
30. the UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 84 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual nominal 400 kHz watchdog oscillator or low speed crystal oscillator selected by the WDCLK bit in the WDCON register and XTALWD bit in the CLKCON register Note that switching of the clock sources will not take effect immediately see Section 14 3 The watchdog asserts the watchdog reset when the watchdog count underflows and the watchdog reset is enabled When the watchdog reset is enabled writing to WDL or WDCON must be followed by a feed sequence for the new values to take effect If a watchdog reset occurs its behavior is similar to power on reset Both POF and BOF are cleared Table 73 Watchdog timer configuration WDTE WDSE FUNCTION 0 x The watchdog reset is disabled The timer can be used as an internal timer and can be used to generate an interrupt WDSE has no effect 1 0 The watchdog reset is enabled The user can set WDCLK to choose the clock source 1 1 The watchdog reset is enabled along with additional safety features 1 WDCLK is forced to 1 using watchdog oscillator 2 WDCON and WDL register can only be written once 3 WDRUN is forced to 1 Watchdog oscillator crystal oscillator Watchdog clock after a Watchdog feed seq
31. 0 0 0 0 Switched to not addressed SLA or repeated mode no recognition of own SLA or START condition General call address hasbeenreceived no I2DAT action 0 0 0 1 Switched to not addressed SLA while still mode Own slave address will be addressed as recognized General call address SLA REC or will be recognized if IZADR 0 1 SLA TRX nol2DAT action 1 0 0 0 Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free nol2DAT action 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IBADR 0O 1 A START condition will be transmitted when the bus becomes free Table 58 Slave Transmitter mode Status code Status of the IPC Application software response Next action taken by I2C I2STAT hardware to from IIDAT I2CON hardware STA STO 51 AA A8h Own SLA R has Load data byte or x 0 0 0 Last data byte will be transmitted been received and ACK bit will be received ACK has been load data byte x 0 0 1 Data byte will be transmitted ACK returned will be received BOh Arbitration lostin Load data byte or x 0 0 0 Last data byte will be transmitted SLA R W as and ACK bit will be received master Own load data byte x 0 0 1 Data byte will be transmitted ACK SLA R has been bit will be received received ACK has been returned B8H Data byte in Load data byte or x 0 0 0 Last data byte will be trans
32. 5 are used as port pins Selected as slave Not selected MISO is high impedance to avoid bus contention P2 4 SS is configured as an input or quasi bidirectional pin SSIG is 0 Selected externally as slave if SS is selected and is driven low The MSTR bit will be cleared to logic 0 when SS becomes low NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 73 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 64 SPI master and slave selection continued SPEN SSIG SSPin MSTR Master MISO MOSI SPICLK Remarks 1 1 1 1 P2 4l1 2 41 or Slave Mode 1 Master X input Hi Hi Z MOSI and SPICLK are at high impedance to idle avoid bus contention when the MAster is idle The application must pull up or pull down SPICLK depending on CPOL SPCTL 3 to avoid a floating SPICLK N Master output output MOSI and SPICLK are push pull when the active Master is active 0 Slave output input input 1 Master input output output 1 Selected as a port function 2 The MSTR bit changes to logic 0 automatically when SS becomes low in input mode and SSIG is logic 0 UM10334 11 2 Additional considerations for a slave When CPHA equals zero SSIG must be logic 0 and the SS pin must be negated and reasserted between each successive serial byte If the SPDAT register is written while SS is active low a write collision error results The operation is undefine
33. A Ri Add indirect memory to A with carry 1 1 36 to 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1 98 to 9F SUBB A dir Subtract direct byte from A with borrow 2 1 95 SUBB A Ri Subtract indirect memory from A with 1 1 96 to 97 borrow SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 to OF INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 to 07 DECA Decrement A 1 1 14 DEC Rn Decrement register 1 1 18 to 1F DEC dir Decrement direct byte 2 1 15 DEC Ri Decrement indirect memory 1 1 16 to 17 INC DPTR Increment data pointer 1 2 A3 MUL AB Multiply A by B 1 4 A4 DIV AB Divide A by B 1 4 84 DAA Decimal Adjust A 1 1 D4 LOGICAL ANL A Rn AND register to A 1 1 58 to 5F ANL A dir AND direct byte to A 2 1 55 ANL A Ri AND indirect memory to A 1 1 56 to 57 ANL A data AND immediate to A 2 1 54 ANL dir A AND A to direct byte 2 1 52 ANL dir data AND immediate to direct byte 3 2 53 ORL A Rn OR register to A 1 1 48 to 4F ORL A dir OR direct byte to A 2 1 45 ORL A Ri OR indirect memory to A 1 1 46 to 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 201
34. All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 3 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual Table 1 Pin description continued Symbol Pin Type Description TSSOP28 P0 2 CIN2A 25 y o P0 2 Port 0 bit 2 2 CIN2A Comparator 2 positive input A KBI2 Keyboard input 2 P0 3 CIN1B 24 y o P0 3 Port 0 bit 3 High current source KBIS CIN1B 1 positive input B KBI3 Keyboard input 3 4 23 P0 4 Port 0 bit 4 High current source KBI4 CIN1A Comparator 1 positive input A KBI4 Keyboard input 4 P0 5 CMPREF 22 y o P0 5 Port 0 bit 5 High current source KBIS CMPREF Comparator reference negative input KBI5 Keyboard input 5 PO 6 CMP1 KBI6 20 y o P0 6 Port 0 bit 6 High current source CMP1 Comparator 1 output KBl6 Keyboard input 6 PO 7 T1 KBI7 19 y o P0 7 Port 0 bit 7 High current source y o T1 Timer counter 1 external count input or overflow output KBI7 Keyboard input 7 P1 0 to P1 7 Port 1 Port 1 is an 8 bit I O port with a user configurable output type except for 1 three pins as noted below During reset Port 1 latches are configured the input only mode with the internal pull up disabled The operation of the configurable Port 1 pins as
35. Configuration Byte 1 UCFG1 bit description 107 Table 88 Oscillator type selection 108 Table 89 Flash User Configuration Byte 2 UCFG2 bit AllOCALON uiii n ERE REGES 108 Table 90 Flash User Configuration Byte 2 UCFG2 bit description 108 Table 91 Sector Security Bytes SECx bit allocation 108 Table 92 Sector Security Bytes SECx bit description 109 Table 93 Effects of Security Bits 109 Table 94 Boot Vector BOOTVEC bit allocation 109 Table 95 Boot Vector BOOTVEC bit description 109 Table 96 Boot Status BOOTSTAT bit allocation 109 Table 97 Boot Status BOOTSTAT bit description 110 Table 98 Instruction set summary 111 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 116 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual 20 Figures Fig 1 TSSOP28 pin configuration 3 Fig 2 P89LPC9301 931A1 logic symbol 7 Fig 3 Block diagram 8 Fig 4 P89LPC9301 931A1 memory map 17 Fig5 Using the crystal oscillator 20 Fig6 Block diagram of oscillator control 21 Fig 7 Interrupt sources interrupt enables and power down wake up 25 Fig8 Quasi bidir
36. Fewer or more than three pulses will result in the device not entering ISP mode Timing specifications may be found in the data sheet for this device This has the same effect as having a non zero status bit This allows an application to be built that will normally execute the user code but can be manually forced into ISP operation If the factory default setting for the Boot Vector is changed it will no longer point to the factory pre programmed ISP boot loader code If this happens the only way it is possible to change the contents of the Boot Vector is through the parallel or ICP programming method provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the Boot Vector and Boot Status Bit After programming the Flash the status byte should be programmed to zero in order to allow execution of the user s application code beginning at address OOOOH RST tRL 002aaa912 Fig 44 Forcing ISP mode In system programming ISP In System Programming is performed without removing the microcontroller from the system The In System Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC9301 931A1 through the serial port This firmware is provided by NXP and embedded within each P89LPC9301 931A1 device The NXP In System Programming facility has made in circuit programm
37. Many system level functions have been incorporated into the P89LPC9301 931A1 in order to reduce component count board space and system cost 1 1 Pin configuration P2 0 P2 7 P2 1 C P2 6 P0 0 CMP2 KBIO PO 1 CIN2B KBI1 P1 7 2 2 2 1 6 PO 3 CIN1B KBI3 P1 5 RST PO 4 CIN1A KBI4 Vss P89LPC9301FDH P0 5 CMPREF KBI5 P3 1 XTAL1 P89LPC931A1FDH Vpp P3 0 XTAL2 CLKOUT P0 6 CMP1 KBI6 P1 4 INT1 PO 7 T1 KBI7 P1 3 INTO SDA P1 0 TXD P1 2 TO SCL P1 1 RXD P2 2 MOSI P2 5 SPICLK P2 3 MISO P2 4 SS 002aae451 Fig 1 TSSOP28 pin configuration 1 2 Pin description Table 1 Pin description Symbol Pin Type Description TSSOP28 0 0 to 0 7 Port 0 Port 0 is 8 bit I O port with a user configurable output type During reset Port 0 latches are configured in the input only mode with the internal pull up disabled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 4 1 Port configurations for details The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt trigger inputs Port 0 also provides various special functions as described below P0 0 CMP2 3 P0 0 Port 0 bit 0 KBIO CMP2 Comparator 2 output KBIO Keyboard input 0 P0 1 CIN2B 26 P0 1 Port 0 bit 1 CIN2B Comparator 2 positive input KBI1 Keyboard input 1 UM10334
38. Mode 2 011 Timer 0 is a dual 8 bit Timer Counter in this mode TLO is an 8 bit Timer Counter controlled by the standard Timer 0 control bits THO is an 8 bit timer only controlled by the Timer 1 control bits see text Timer 1 in this mode is stopped Mode 3 100 Reserved User must not configure to this mode 101 Reserved User must not configure to this mode 110 PWM mode see Section 7 5 111 Reserved User must not configure to this mode 5 7 reserved 71 ModeO Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a divide by 32 prescaler Figure 18 shows Mode 0 operation In this mode the Timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the Timer interrupt flag TFn The count input is enabled to the Timer when TRn 1 and either TnGATE 0 or INTn 1 Setting TNGATE 1 allows the Timer to be controlled by external input INTn to facilitate pulse width measurements TRn is a control bit in the Special Function Register TCON Table 29 The TnGATE bit is in the TMOD register The 13 bit register consists of all 8 bits of THn and the lower 5 bits of TLn The upper 3 bits of TLn are indeterminate and should be ignored Setting the run flag TRn does not clear the registers Mode 0 operation is the same for Timer 0 and Timer 1 See Figure 13 There are two different GATE bits one for Timer 1 TMOD 7 a
39. P STOP condition RS repeated START condition 002aaa932 Fig 28 Format of Slave Receiver mode 10 6 4 Slave Transmitter mode The first byte is received and handled as in the Slave Receiver Mode However in this mode the direction bit will indicate that the transfer direction is reversed Serial data is transmitted via P1 3 SDA while the serial clock is input through P1 2 SCL START and STOP conditions are recognized as the beginning and end of a serial transfer In a given application the 2 may operate as a master and as a slave In the slave mode the 12C hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode the I2C bus switches to the slave mode immediately and can detect its own slave address in the same serial transfer Fees To T4 T2 T T7 logic write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW from Master to Slave not acknowledge SDA HIGH from Slave to Master S START condition P STOP condition 002aaa933 Fig 29 Format of Slave Transmitter mode All information provided in this document is subject to legal d
40. P2M2 P3M1 P3M2 PCON PCONA PSW PTOAD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF Description SFR addr Port 1 output 92H mode 2 Port 2 output A4H mode 1 Port 2 output ASH mode 2 Port 3 output BiH mode 1 Port 3 output B2H mode 2 Power control 87H register Power control B5H register A Bit address Program status DOH word Port 0 digital F6H input disable Reset source DFH register RTC control D1H RTC register D2H high RTC register D3H low Serial port A9H address register Serial port B9H address enable Serial Portdata 99H buffer register Bit functions and addresses Reset value MSB LSB Hex Binary P1M2 7 1 2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 1 2 0 000 00x0 xx00 P2M1 7 P2M1 6 P2M1 5 P2M1 4 P2M1 3 P2M1 2 P2M1 1 2 1 0 FFE 1111 1111 P2M2 7 P2M2 6 P2M2 5 P2M2 4 P2M2 3 P2M2 2 P2M2 1 2 2 0 00101 0000 0000 P3M1 1 1 0 0301 XXXX xx11 P3M2 1 P3M2 0 0001 xx00 SMOD1 SMODO BOI GF1 GFO PMOD1 PMODO 00 0000 0000 RTCPD VCPD I2PD SPPD SPD 0011 0000 0000 07 D6 D5 D4 D3 D2 D1 DO CY AC FO RS1 RSO OV F1 P 00 0000 0000 PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00 000x BOIF BOF POF R BK R WD R SF REX dB RTCF RTCS1 RTCSO ERTC RTCEN 60016 011x xx00 00 61 0000 0000 00 61 0000 0000 00 0000 0000 00 0000 0000 XXXX Jenueui Jesf LWLE6 LOE6Dd 1
41. Register SCON and the stop bit is not saved The baud rate is programmable to either 1 16 or 1 2 of the CCLK frequency as determined by the SMOD bit in PCON All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 44 of 119 NXP Semiconductors U M1 0334 UM10334 9 4 9 5 9 6 9 7 P89LPC9301 931A1 User manual Mode 3 11 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 9 6 Baud Rate generator and selection In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 SFR space The UART SFRs are at the following locations Table 33 UART SFR addresses Register Description SFR location PCON Power Control 87H SCON Serial Port UART Control 98H SBUF Serial Port UART Data Buffer 99H SADDR Serial Port UART Address A9H SADEN Serial Port UART Address Enable B9H SSTAT Serial Port UART Status BAH BRGR1 Baud Rate G
42. Source used to produce the wake up The Real time clock running from the internal RC oscillator can be used The power consumption of this oscillator is approximately 300 uA Instead if the WDT is used to generate interrupts the current is reduced to approximately 50 uA Whenever the WDT underflows the device will wake up 15 Additional features The AUXR1 register contains several special purpose control bits that relate to several chip features AUXR1 is described in Table 79 Table 78 AUXR1 register address A2h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKLP EBRR ENT1 ENTO SRST 0 DPS Reset 0 0 0 0 0 0 0 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 90 of 119 NXP Semiconductors U M1 0334 UM10334 15 1 15 2 P89LPC9301 931A1 User manual Table 79 AUXR1 register address A2h bit description Bit Symbol Description 0 DPS Data Pointer Select Chooses one of two Data Pointers 1 Not used Allowable to set to a logic 1 2 0 This bit contains a hard wired 0 Allows toggling of the DPS bit by incrementing AUXR1 without interfering with other bits in the register 3 SRST Software Reset When set by software resets the P89LPC9301 931A1 as if a hardware reset occurred 4 ENTO When set the P1 2 pin is toggled whenever Timer 0 overflows The output frequency is therefore one half of t
43. W has been Load data byte or 0 0 0 X Data byte will be transmitted transmitted ACK ACK bit will be received has been received no I2DAT action 1 o x Repeated START will be or transmitted no I2DAT action 0 1 0 x STOP condition will be or transmitted STO flag will be reset nol2DAT action 1 1 0 STOP condition followed by a START condition will be transmitted STO flag will be reset 20h SLA W has been Load data byte 0 0 0 X Data byte will be transmitted transmitted ACK bit will be received NOT ACK has mnojoDATaction 1 0 0 x Repeated START will be been received or transmitted no I2DAT action 0 1 0 x STOP condition will be or transmitted STO flag will be reset nol2DAT action 1 1 0 STOP condition followed by a START condition will be transmitted STO flag will be reset 28h Data byte in Load data byte 0 0 0 X Data byte will be transmitted I2DAT bit will be received transmitted has been received I2DAT action 1 0 0 X Repeated START will be or transmitted no I2DAT action 0 1 0 x STOP condition will be or transmitted STO flag will be reset nol2DAT action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 64 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual
44. for glitch filter specifications input port data lt pin glitch rejection 002aaa916 Fig 10 Input only 4 5 Push pull output configuration The push pull output configuration has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output The push pull port configuration is shown in Figure 11 A push pull port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC9301 931A1 data sheet Dynamic characteristics for glitch filter specifications Vpp strong port N T t pin input data aan glitch rejection 002aaa917 port latch data Fig 11 Push pull output 4 6 Port 0 and Analog Comparator functions The P89LPC9301 931A1 incorporates two Analog Comparators In order to give the best analog performance and minimize power consumption pins that are being used for analog functions must have both the digital outputs and digital inputs disabled Digital outputs are disabled by putting the port pins into the input only mode as described in the Port Configurations section see Figure 10 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 N
45. in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 38 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 29 Timer Counter Control register TCON address 88h bit description continued Bit Symbol 3 IE1 TRO TFO TR1 TF1 Description Interrupt 1 Edge flag Set by hardware when external interrupt 1 edge is detected Cleared by hardware when the interrupt is processed or by software Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off Timer 0 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the processor vectors to the interrupt routine or by software except in mode 6 where it is cleared in hardware Timer 1 Run control bit Set cleared by software to turn Timer Counter 1 on off Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the interrupt is processed or by software except in mode 6 see above when it is cleared in hardware C T 0 overflow PCLK Topi Hn TFn interrupt n pin 1 C T 21 conir l 5 bits 8 bits TRn 0 Tn pin Gate INTn pin ENTn 002aaa919 Fig 13 Timer counter 0 or 1 in Mode 0 13 bit counter C T 0 overflow PCLK THn TFn gt interrupt n pin 1 i contro
46. include an independent Baud Rate Generator The baud rate can be selected from the oscillator divided by a constant Timer 1 overflow or the independent Baud Rate Generator In addition to the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection break detect automatic address recognition selectable double buffering and several interrupt options The UART can be operated in 4 modes as described in the following sections Mode 0 Serial data enters and exits through RXD TXD outputs the shift clock 8 bits are transmitted or received LSB first The baud rate is fixed at 46 of the CPU clock frequency Mode 1 10 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first and a stop bit logic 1 When data is received the stop bit is stored in RB8 in Special Function Register SCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 9 6 Baud Rate generator and selection Mode 2 11 bits are transmitted through TXD or received through RXD start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 When data is transmitted the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 When data is received the 9th data bit goes into RB8 in Special Function
47. information please visit http Avww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 5 November 2010 Document identifier UM10334 All rights reserved
48. modifying bit 6 and writing this result back into the TRIM register Alternatively the ANL direct or ORL direct instructions can be used to clear or set bit 6 of the TRIM register On chip RC oscillator option The P89LPC9301 931A1 has a 6 bit TRIM register that can be used to tune the frequency of the RC oscillator During reset the TRIM value is initialized to a factory pre programmed value to adjust the oscillator frequency to 7 373 MHz 1 96 at room temperature Note the initial value is better than 1 96 please refer to the P89LPC9301 931A1 data sheet for behavior over temperature End user applications can write to the TRIM register to adjust the on chip RC oscillator to other frequencies Increasing the TRIM value will decrease the oscillator frequency When the clock doubler option is enabled UCFG2 7 1 the output frequency is doubled If CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to logic 1 to reduce power consumption On reset CLKLP is logic 0 allowing highest performance access This bit can then be set in software if CCLK is running at 8 MHz or slower When clock doubler option is enabled BOE 1 bit UCFG1 5 and BOEO bit UCFG1 3 are required to hold the device in reset at power up until Vpp has reached its specified level Table5 On chip RC oscillator trim register TRIM address 96h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O Reset
49. of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Clock cycle 1 i SPICLK CPOL 0 SPICLK CPOL 1 MOSI input DORD O S DORD 1 B MSB MISO output SS if SSIG bit 0 1 an 002 937 1 Not defined Fig 38 SPI master transfer format with CPHA 1 11 7 SPI clock prescaler select The SPI clock prescaler selection uses the SPR1 SPRO bits in the SPCTL register see Table 60 12 Analog comparators Two analog comparators are provided on the P89LPC9301 931A1 Input and output options allow use of the comparators in a number of different configurations Comparator operation is such that the output is a logic 1 which may be read in a register and or routed to a pin when the positive input one of two selectable pins is greater than the negative input selectable from a pin or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the output value changes 12 4 Comparator configuration Each comparator has a control register CMP1 for comparator 1 and CMP2 for comparator 2 The control registers are identical and are shown in Table 66 The overall connections to both comparators are shown in Figure 39 There are eight possible configurations for each comp
50. output whenever a timer overflow occurs The same device pins that are used for the TO and T1 count inputs and PWM outputs are also used for the timer toggle outputs This function is enabled by control bits ENTO and in the AUXR1 register and apply to Timer 0 and Timer 1 respectively The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on In order for this mode to function the C T bit must be cleared selecting PCLK as the clock source for the timer 8 Real time clock system timer The P89LPC9301 931A1 has a simple Real time Clock System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down The Real time Clock can be an interrupt or a wake up source see Figure 18 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 40 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual The Real time Clock is a 23 bit down counter The clock source for this counter can be either the CPU clock CCLK or the XTAL 1 2 oscillator There are five SFRs used for the RTC RTCCON Real time Clock control RTCH Real time Clock counter reload high bits 22 to 15 RTCL Real time Clock counter reload low bits 14 to 7 RTCDATH Real time clock data register high RTCDATL Real time Clock data register low T
51. relative to DPTR value MOV DPTR data16 Load the Data Pointer with a 16 bit constant MOVC A A DPTR Move code byte relative to DPTR to the accumulator MOVX A DPTR Move accumulator to data memory relative to DPTR MOVX DPTR A Move from data memory relative to DPTR to the accumulator Also any instruction that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC9301 931A1 since the part does not have an external data bus However they may be used to access Flash configuration information see Flash Configuration section or auxiliary data XDATA memory All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 91 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Bit 2 of AUXR1 is permanently wired as a logic 0 This is so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register 16 Flash memory UM10334 16 1 General description The P89LPC9301 931A1 Flash memory provides in circuit electrical erasure and programming The Flash can be read and written as bytes The Sector and Page Erase functions can erase any Flash secto
52. should be held for at least one full machine cycle The Timer or Counter function is selected by control bits TnC T x 0 and 1 for Timers 0 and 1 respectively in the Special Function Register TMOD Timer 0 and Timer 1 have five operating modes modes 0 1 2 3 and 6 which are selected by bit pairs TnM1 TnMO in TMOD and TnM2 in TAMOD Modes 0 1 2 and 6 are the same for both Timers Counters Mode 3 is different The operating modes are described later in this section Table 24 Timer Counter Mode register TMOD address 89h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol T1GATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO Reset 0 0 0 0 0 0 0 0 Table 25 Timer Counter Mode register TMOD address 89h bit description Bit Symbol Description 0 TOMO Mode Select for Timer 0 These bits are used with the TOM2 bit in the TAMOD register to determine the 1 TOM1 Timer 0 mode see Table 27 2 Timeror Counter selector for Timer 0 Cleared for Timer operation input from CCLK Set for Counter operation input from TO input pin Gating control for Timer 0 When set Timer Counter is enabled only while the INTO pin is high and the TRO control pin is set When cleared Timer 0 is enabled when the TRO control bit is set 4 Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD register to determine the 5 Timer 1 mode see Table 27 6 T1C T Timeror Counter Selector fo
53. the data currently in the shifter which is also the last data 7 If there is more data the CPU writes to TB8 again 8 The CPU writes to SBUF again Then f INTLO is logic 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter 9 Go to 4 10 Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following Multiprocessor communications UART modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received or transmitted When data is received the 9th bit is stored in RB8 The UART can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON One way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte
54. the next character is written between the start bit and the stop bit of the previous character Double buffering can be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out Double buffering in different modes Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD 0 Transmit interrupts with double buffering enabled Modes 1 2 and 3 Unlike the conventional UART when double buffering is enabled the Tx interrupt is generated when the double buffer is ready to receive new data The following occurs during a transmission assuming eight data bits 1 The double buffer is empty initially 2 The CPU writes to SBUF 3 The SBUF data is loaded to the shift register and a Tx interrupt is generated immediately 4 If there is more data to 6 else continue 5 If there is no more data then f DBISEL is logic 0 no more interrupts will occur All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 51 of 119 NXP Semiconductors UM10334 If P89LPC9301 931A1 User manual If DBISEL is logic 1 and INTLO is logic 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shift
55. the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected UM10334 All information provided in this document is subject to legal disclaimers to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole re
56. this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 22 of 119 NXP Semiconductors U M1 0334 UM10334 3 1 P89LPC9301 931A1 User manual Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IENO or IEN1 The IENO register also contains a global enable bit EA which enables all interrupts Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IPO IPOH IP1 and IP1H An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are received simultaneously the request of higher priority level is serviced If requests of the same priority level are pending at the start of an instruction cycle an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used for pending requests of the same priority level Table 11 summarizes the interrupt sources flag bits vector addresses enable bits priority bits arbitration ranking and whether each interrupt may wake up the CPU from a Power down mod
57. to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 7 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual 1 4 Block diagram Fig 3 P89LPC9301 931A1 HIGH PERFORMANCE ACCELERATED 2 CLOCK 80C51 CPU 4 kB 8 lt TXD CODE FLASH K UART RXD internal 256 BYTE y K y REAL TIME CLOCK DAARAM _ SYSTEM TIMER PORT 3 SCL Pane CONFIGURABLE 1 0s AK I C BUS SDA P2 7 0 ls ai WATCHDOG TIMER AND OSCILLATOR os Co 1 TIMER 0 TO PIAR CONFIGURABLE 1 Os AK TIMER 1 Ti CMP PORTO C conriGURABLE COMPARATORS CIN1B KEYPAD SPICLK INTERRUPT MOSI C y SPI MiSo SS PROGRAMMABLE OSCILLATOR DIVIDER cro XTAL1 CRYSTAL CONF CURABLE ON CHIP RC POWER MONITOR osi ardH OSCILLATOR WITH POWER ON RESET RESONATOR CLOCK DOUBLER BROWNOUT RESET XTAL2 002aae447 Block diagram UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 8 of 119 UM10334 P89LPC9301 931A1 User manual NXP Semiconductors 1 5 Special function registers Remark SFR accesses are restricted in the following ways User must not attempt to access any SFR locations not defined Acce
58. to the CPU clock 3 Comparator negative input select When logic 0 the comparator reference pin CMPREF is selected as the negative comparator input When logic 1 the internal comparator reference Vngr is selected as the negative comparator input 4 Comparator positive input select When logic 0 CINnA is selected as the positive comparator input When logic 1 CINnB is selected as the positive comparator input 5 Comparator enable When set the corresponding comparator function is enabled Comparator output is stable 10 microseconds after CEn is set 67 reserved 4 CIN1A P0 3 CIN1B CMP1 P0 6 P0 5 CMPREF Vref bg 73 2 gt t interrupt change detect CP2 EC P0 2 CIN2A comparator 2 P0 1 CIN2B D CMP2 P0 0 2 go i OE2 CN2 002aae456 Fig 39 Comparator input and output connections UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 80 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual 12 2 Internal reference voltage An internal reference voltage Vret og may supply a default reference when a single comparator input pin is used Please refer to the P89LPC9301 931A1 data sheet for specifications 12 3 Comparator input pins Comparator input and reference pins maybe be used as either digita
59. underflows In watchdog mode a feed sequence will clear this bit It can also be cleared by writing a logic 0 to this bit in software 2 WDRUN Watchdog Run Control The watchdog timer is started when WDRUN 1 and stopped when WDRUN 0 This bit is forced to 1 watchdog running and cannot be cleared to zero if both WDTE and WDSE are set to 1 3 4 reserved PREO 6 PRE1 Clock Prescaler Tap Select Refer to Table 76 for details 7 PRE2 Table 76 Watchdog timeout vales PRE2 to PREO WDL in decimal Timeout Period Watchdog Clock Source in watchdog clock 400 KHz Watchdog 12 MHz CCLK 6 MHz cycles Oscillator Clock CCLK Watchdog 1 000 0 33 82 5 us 5 50 us 255 8 193 20 5 ms 1 37 ms 001 0 65 162 5 us 10 8 us 255 16 385 41 0 ms 2 73 ms 010 0 129 322 5 us 21 5 us 255 32 769 81 9 ms 5 46 ms 011 0 257 642 5 us 42 8 us 255 65 537 163 8 ms 10 9 ms 100 0 513 1 28 ms 85 5 us 255 131 073 327 7 ms 21 8 ms 101 0 1 025 2 56 ms 170 8 us 255 262 145 655 4 ms 43 7 ms 110 0 2 049 5 12 ms 341 5 us 255 524 289 1 315 87 4 ms 111 0 4097 10 2 ms 682 8 us 255 1 048 577 2 625 174 8 ms UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 87 of 119 NXP Semiconductors U M1 0334 UM10334 P89LPC9301 931A1 User manual 14 3 Watchdog clock source The watchdog timer system has an on chip 400 KHz osc
60. will be returned General call Data data byte x 0 0 1 Data byte will be received and ACK has been will be returned received ACK has been returned 98H Previously Read data byte 0 0 0 0 Switched to not addressed SLA addressed with mode no recognition of own SLA or General call Data General call address has peet read data byte 0 0 0 1 Switched to not addressed SLA received NACK mode Own slave address will be has been returned recognized General call address will be recognized if IZADR 0 1 read data byte 1 0 0 0 Switched to not addressed SLA UM10334 read data byte 1 0 0 All information provided in this document is subject to legal disclaimers mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IBADR 0O 1 A START condition will be transmitted when the bus becomes free NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 67 of 119 NXP Semiconductors UM10334 Table 57 Slave Receiver mode continued P89LPC9301 931A1 User manual Status code Status of the 2 Application software response Next action taken by I2C I2STAT hardware to from I2DAT to I2ZCON hardware STA STO A STOP condition No I2DAT action
61. 0 All rights reserved User manual Rev 2 5 November 2010 25 of 119 NXP Semiconductors U M1 0334 UM10334 4 2 P89LPC9301 931A1 User manual P1 5 RST can only be an input and cannot be configured P1 2 SCL TO and P1 3 SDA INTO may only be configured to be either input only or open drain Table 13 Port output configuration settings PxM1 y PxM2 y Port output mode 0 0 Quasi bidirectional 0 1 Push pull 1 0 Input only high impedance 1 1 Open drain Quasi bidirectional output configuration Quasi bidirectional outputs can be used both as an input and output without the need to reconfigure the port This is possible because when the port outputs a logic high it is weakly driven allowing an external device to pull the pin low When the pin is driven low it is driven strongly and able to sink a large current There are three pull up transistors in the quasi bidirectional output that serve different purposes One of these pull ups called the very weak pull up is turned on whenever the port latch for the pin contains a logic 1 This very weak pull up sources a very small current that will pull the pin high if it is left floating A second pull up called the weak pull up is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level This pull up provides the primary source current for a quasi bidirectional pin that is outputting a 1 If this pin i
62. 0 0 Bits 5 0 loaded with factory stored value during reset UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 19 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 6 On chip RC oscillator trim register TRIM address 96h bit description Bit Symbol Description 0 TRIM O Trim value Determines the frequency of the internal RC oscillator During reset 1 TRIM 1 these bits are loaded with a stored factory calibration value When writing to either i bit 6 or bit 7 of this register care should be taken to preserve the current TRIM value 2 TRIM 2 by reading this register modifying bits 6 or 7 as required and writing the result to 3 TRIM 3 this register 4 TRIM 4 5 TRIM 5 6 ENCLK when 1 CLK is output on the XTAL2 pin provided the crystal oscillator is not being used 7 RCCLK when 1 selects the RC Oscillator output as the CPU clock CCLK This allows for fast switching between any clock source and the internal RC oscillator without needing to go through a reset cycle 2 6 Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz calibrated to 5 96 at room temperature This oscillator can be used to save power when a high clock frequency is not needed 2 7 External clock input option In this configuration the p
63. 0 111 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual Table 98 Instruction set summary continued Mnemonic Description Bytes Cycles Hex code A Rn Exclusive OR register to A 1 1 68 to 6F A dir Exclusive OR direct byte to A 2 1 65 XRL A Ri Exclusive OR indirect memory to A 1 1 66 to 67 XRL A data Exclusive OR immediate to A 2 1 64 dir A Exclusive OR A to direct byte 2 1 62 XRL dir data Exclusive OR immediate to direct byte 3 2 63 CLR A Clear A 1 1 E4 CPLA Complement A 1 1 F4 SWAP A Swap Nibbles of A 1 1 C4 RLA Rotate A left 1 1 23 RLC A Rotate A left through carry 1 1 33 Rotate A right RRA 1 1 03 RRC A Rotate A right through carry 1 1 13 DATA TRANSFER MOV A Rn Move register to A 1 1 E8 to EF MOV A dir Move direct byte to A 2 1 E5 Move indirect memory to A MOV A Ri 1 1 E6 to E7 MOV A data Move immediate to A 2 1 74 MOV Rn A Move A to register 1 1 F8 to FF MOV Rn ir Move direct byte to register 2 2 A8 to AF MOV Rn data Move immediate to register 2 1 78 to 7F MOV dir A Move A to direct byte 2 1 F5 MOV dir Rn Move register to direct byte 2 2 88 to 8F MOV dir dir Move direct byte to direct byte 3 2 85 MOV dir Ri Move indirect memory to direct byte 2 2 86 to 87 MOV dir data Move immediate to direct byte 3 2 75 MOV Ri A Move A to indirect memory 1 1 F6 to F7 MOV Ri dir Move direct byte to indirect memory 2 2 A6 to A7 MOV Ri data Move immediate to indirect m
64. 0334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 50 of 119 NXP Semiconductors U M1 0334 UM10334 9 14 9 15 9 16 9 17 P89LPC9301 931A1 User manual Table 42 FE and RI when SM 1 in Modes 2 and Mode 6 RB8 RI FE SMODO 2 0 0 No RI when RB8 0 Occurs during STOP bit 1 Similar to Figure 22 with SMODO 0 RI Occurs during STOP occurs during RB8 one bit before FE bit 3 1 0 No RI when RB8 0 Will NOT occur 1 Similar to Figure 22 with SMODO 1 RI Occurs during STOP occurs during STOP bit bit Break detect A break is detected when 11 consecutive bits are sensed low and is reported in the status register SSTAT For Mode 1 this consists of the start bit 8 data bits and two stop bit times For Modes 2 and 3 this consists of the start bit 9 data bits and one stop bit The break detect bit is cleared in software or by a reset The break detect can be used to reset the device and force the device into ISP mode This occurs if the UART is enabled and the the EBRR bit AUXR1 6 is set and a break occurs Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted Double buffering allows transmission of a string of characters with only one stop bit between any two characters provided
65. 19 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual 13 Keypad interrupt KBI The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern This function can be used for bus address recognition or keypad recognition The user can configure the port via SFRs for different tasks There are three SFRs used for this function The Keypad Interrupt Mask Register KBMASK is used to define which input pins connected to Port 0 are enabled to trigger the interrupt The Keypad Pattern Register KBPATN is used to define a pattern that is compared to the value of Port 0 The Keypad Interrupt Flag KBIF in the Keypad Interrupt Control Register KBCON is set when the condition is matched while the Keypad Interrupt function is active An interrupt will be generated if it has been enabled by setting the EKBI bit in IEN1 register and EA 1 The PATN SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an original KBI function like in the 87LPC76x series the user needs to set KBPATN OFFH and PATN SEL 0 not equal then any key connected to PortO which is enabled by KBMASK register is will cause the hardware to set KBIF 1 and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down
66. 1_ Receive transmit baud rate for UART SMO SM1 SMOD1 SBRGS 1 0 0 X 1 X CCLKy 6 1 1 0 0 CCL 256 TH1 64 1 0 COLS 256 TH1 32 X 1 CCLK amp RGR1 BRGRO 16 Table 35 Baud Rate Generator Control register BRGCON address BDh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SBRGS BRGEN Reset x 0 0 Table 36 Baud Rate Generator Control register BRGCON address BDh bit description Bit Symbol Description 0 BRGEN Baud Rate Generator Enable Enables the baud rate generator BRGR1 and BRGRO can only be written when BRGEN 0 1 SBRGS Select Baud Rate Generator as the source for baud rates to UART in modes 1 and 3 see Table 34 for details 2 7 reserved timer 1 overflow PCLK based oM E BRES ZD o baud rate modes 1 and 3 SMOD1 0 baud rate generator SBRGS 1 CCLK based 002 897 Fig 19 Baud rate generation for UART Modes 1 3 Framing error A Framing error occurs when the stop bit is sensed as a logic 0 A Framing error is reported in the status register SSTAT In addition if SMODO PCON 6 is 1 framing errors can be made available in SCON 7 If SMODO is 0 SCON 7 is SMO It is recommended that SMO and SM1 SCON 7 6 are programmed when SMODO is logic O Break detect A break detect is reported in the status register SSTAT A break is detected when any 11 consecutive bits are sensed low Since a break conditio
67. 3 2 1 0 Symbol RTCS1 RTCSO0 ERTC RTCEN Reset 0 1 1 0 0 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 43 of 119 NXP Semiconductors U M1 0334 9 UART P89LPC9301 931A1 User manual Table 32 Real time Clock Control register RTCCON address D1h bit description Bit Symbol Description 0 RTCEN Real time Clock enable The Real time Clock will be enabled if this bit is logic 1 Note that this bit will not power down the Real time Clock The RTCPD bit PCONA 7 if set will power down and disable this block regardless of RTCEN 1 ERTC Real time Clock interrupt enable The Real time Clock shares the same interrupt as the watchdog timer Note that if the user configuration bit WOTE UCFG1 7 is logic 0 the watchdog timer can be enabled to generate an interrupt Users can read the RTCF RTCCON 7 bit to determine whether the Real time Clock caused the interrupt reserved RTCSO Real time Clock source select see Table 30 RTCS1 RTCF Real time Clock Flag This bit is set to logic 1 when the 23 bit Real time Clock reaches a count of logic 0 It can be cleared in software UM10334 9 1 9 2 9 3 The P89LPC9301 931A1 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source The P89LPC9301 931A1 does
68. 334 11 3 11 4 11 5 11 6 11 7 12 12 1 12 2 12 3 12 4 12 5 12 6 13 14 14 1 14 2 14 3 14 4 14 5 14 6 15 15 1 15 2 16 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 10 16 11 16 12 16 13 16 14 16 15 16 16 16 17 16 18 16 19 16 20 17 18 18 1 Additional considerations for a master 74 Mode change on 5 74 Write 75 Data mode 75 SPI clock prescaler select 79 Analog comparators 79 Comparator configuration 79 Internal reference voltage 81 Comparator input pins 81 Comparator 81 Comparators and power reduction modes 81 Comparators configuration example 82 Keypad interrupt 83 Watchdog timer WDT 84 Watchdog function 84 Feed sequence 85 Watchdog clock source 88 Watchdog Timer in Timer mode 89 Power down 90 Periodic wake up from power down without an external oscillator 90 Additional features 90 Software reset 91 Dual Data Pointers 91 Flash memory 92 General description 92 Features
69. 56 bytes of internal data memory space 00h FFh accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruction The P89LPC9301 931A1 has 8 kB of on chip Code memory Table 4 Data RAM arrangement Type Data RAM Size bytes DATA Directly and indirectly addressable memory 128 IDATA Indirectly addressable memory 256 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 17 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual 2 Clocks 2 1 Enhanced CPU The P89LPC9301 931A1 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices A machine cycle consists of two CPU clock cycles and most instructions execute in one or two machine cycles 2 2 Clock definitions The P89LPC9301 931A1 device has several internal clocks as defined below OSCCLK Input to the DIVM clock divider OSCCLK is selected from one of four clock Sources and can also be optionally divided to a slower frequency see Figure 6 and S
70. 61 Kbps 230 Kbps 1500 Kbps 750 Kbps Timer 1 in Timer 1 in Timer 1 in Timer 1 in Timer 1 in mode 2 mode 2 mode 2 mode 2 mode 2 I C operation modes Master Transmitter mode In this mode data is transmitted from master to slave Before the Master Transmitter mode can be entered I2CON must be initialized as follows Table 53 1 C Control register I2CON address D8h Bit 7 6 5 4 3 2 1 0 I2EN STA STO SI AA CRSEL value 1 0 0 0 x bit rate CRSEL defines the bit rate IBEN must be set to 1 to enable the I C function If the AA bit is 0 it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus and it can not enter slave mode STA STO and SI bits must be cleared to 0 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 59 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this case the data direction bit R W will be logic 0 indicating a write Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and the end of a serial transfer The I C bus will enter Master Transmitter Mode by setting the STA
71. 68d v 0LINn SJ0jonpuoolul8S dXN jenuew sn 010 2 eH 1oe qns s jueuinoop siy 6LL JO v 0LAn pamasa syfu 0102 A a dXN Table 2 Special function registers continued indicates SFRs that are bit addressable Name SCON SSTAT SP SPCTL SPSTAT SPDAT TAMOD TCON THO TH1 TLO TL1 TMOD TRIM WDCON Description SFR addr Bit address Serial port 98H control Serial port BAH extended status register Stack pointer 81H SPI control E2H register SPI status E1H register SPI data E3H register Timer 0 and 1 8FH auxiliary mode Bit address Timer 0 and 1 88H control Timer 0 high 8CH Timer 1 high 8DH Timer 0 low 8AH Timer 1 low 8BH Timer 0 and 1 89H mode Internal 96H oscillator trim register Watchdog A7H control register Bit functions and addresses Reset value MSB 9F SMO FE DBMOD SSIG SPIF 8F TF1 T1GATE RCCLK PRE2 9E SM1 INTLO SPEN WCOL 8E TRI T1C T ENCLK PRE1 9D SM2 CIDIS DORD 8D TFO T1M1 TRIM 5 PREO 9C REN DBISEL MSTR T1M2 8c TRO T1MO TRIM 4 9B TB8 FE CPOL 8B IE1 TOGATE TRIM 3 9A RB8 BR CPHA 8A IT1 TOC T TRIM 2 WDRUN 99 TI OE SPR1 89 IEO TOM1 TRIM 1 W
72. 7 DBMOD Double buffering mode When set 1 enables double buffering Must be logic 0 for UART mode In order to be compatible with existing 80C51 devices this bit is reset to logic 0 to disable double buffering 9 10 More about UART Mode 0 In Mode 0 a write to SBUF will initiate a transmission At the end of the transmission TI SCON 1 is set which must be cleared in software Double buffering must be disabled in this mode Reception is initiated by clearing RI SCON 0 Synchronous serial transfer occurs and will be set again at the end of the transfer When RI is cleared the reception of the next character will begin Refer to Figure 20 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 48 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual s ni sie s stels gs stels sies DE sie s E 1 1 a si6 si is sie s si6 st at ste s stels stel ed 516 write to SBUF shift transmit RXD data out TxD shittclock LILI LILILILILILI TI WRITE to SCON fl clear RI RI l RXD 2 D4 D5 D7 data in TXD shift clock l l l l l 2 receive 002aaa925 Fig 20 Serial Port Mode 0 double buffering must be disabled 9 11 More about UART Mode 1
73. 931A1 User manual 19 Tables Table 1 Pin description 3 Table 37 Serial Port Control register SCON address 98h Table 2 Special function registers 10 bit allocation 47 Table 3 Extended special function registers 16 Table 38 Serial Port Control register SCON address 98h Table 4 Data RAM arrangement 17 bit description 47 Table 5 On chip RC oscillator trim register TRIM Table 39 Serial Port modes 47 address 96h bit allocation 19 Table 40 Serial Port Status register SSTAT address BAh Table 6 On chip RC oscillator trim register TRIM bit allocation 47 address 96h bit description 20 Table 41 Serial Port Status register SSTAT address BAh Table 7 Clock control register CLKCON address bit description 48 FFDEh bit allocation 21 Table 42 FE and RI when SM2 1 in Modes 2 and 3 51 Table 8 Clock control register CLKCON address Table 43 Slave 0 1 examples 54 FFDEh bit description 21 Table 44 Slave 0 1 2 examples 54 Table 9 Oscillator type selection for clock switch 22 Table 45 I C data register IBDAT address DAh bit Table 10 Interrupt priority level 23 allocation
74. ADEYE EWDRT em CMF2 CMF1 EC EA IEO 7 ETO ET1 TI and RI RI j interrupt ES ESR to CPU nT EST EI2C AL ESPI Fig7 Interrupt sources interrupt enables and power down wake up sources 002aae453 4 ports The P89LPC9301 931A1 has four I O ports Port 0 Port 1 Port 2 and Port 3 Ports 0 1 and 2 are 8 bit ports and Port 3 is a 2 bit port The exact number of I O pins available depends upon the clock and reset options chosen see Table 12 Table 12 Number of I O pins available Clock source Reset option Number of I O pins On chip oscillator or watchdog No external reset except during power up 26 oscillator External RST pin supported 25 External clock input No external reset except during power up 25 External RST pin supported 24 Low medium high speed oscillator No external reset except during power up 24 external crystal or resonator External RST pin supported 23 4 1 Port configurations All but three I O port pins on the P89LPC9301 931A1 may be configured by software to one of four types on a pin by pin basis as shown in Table 13 These are quasi bidirectional standard 80C51 port outputs push pull open drain and input only Two configuration registers for each port select the output type for each port pin UM10334 All information provided in this document is subject to legal disclaimers NXP B V 201
75. All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 115 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual Table 71 Keypad Interrupt Mask register KBMASK address 86h bit allocation 84 Table 72 Keypad Interrupt Mask register KBMASK address 86h bit description 84 Table 73 Watchdog timer configuration 85 Table 74 Watchdog Timer Control register WDCON address A7h bit allocation 87 Table 75 Watchdog Timer Control register WDCON address A7h bit description 87 Table 76 Watchdog timeout vales 87 Table 77 Watchdog input clock selection 88 Table 78 AUXR1 register address A2h bit allocation 90 Table 79 AUXR 1 register address A2h bit description 91 Table 80 Flash Memory Control register FMCON address E4h bit allocation 94 Table 81 Flash Memory Control register FMCON address E4h bit description 95 Table 82 Boot loader address and default Boot vector 97 Table 83 In system Programming ISP hex record 100 Table 84 IAP error status 104 Table 85 IAP function calls 105 Table 86 Flash User Configuration Byte 1 UCFG1 bit allocation iu sx RR ee en 107 Table 87 Flash User
76. CNn OEn 0 1 1 CINnB CINnB COn CMPREF CMPREF CMPn 002aaa623 002aaa624 e CPn CNn OEn 100 f CPn CNn OEn 101 CINnB CINnB COn Vner 1 23 V con Vner 1 23 V CMPD 002aaa625 002aaa626 g CPn CNn 110 h CPn CNn OEn 2 1 1 1 Fig 40 Comparator configurations Suppose PGA1 is disabled or gain 1 12 6 Comparators configuration example The code shown below is an example of initializing one comparator Comparator 1 is configured to use the CIN1A and CMPREF inputs outputs the comparator result to the pin and generates an interrupt when the comparator output changes CMPINIT MOV PTOAD 030h Disable digital INPUTS on CINIA CMPREF ANL POM2 0CFh Disable digital OUTPUTS on pins that are used ORL POM1 030h for analog functions CIN1A CMPREF MOV CMP1 024h Turn on comparator 1 and set up for Positive input on CIN1A Negative input from CMPREF pin Output to CMP1 pin enabled CALL delayl0us The comparator needs at least 10 microseconds before use ANL CMP1 0FEh Clear comparator 1 interrupt flag SETB EC Enable the comparator interrupt SETB EA Enable the interrupt system if needed RET Return to caller The interrupt routine used for the comparator must clear the interrupt flag CMF1 in this case before returning UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 82 of 1
77. CPU vam P CLOCK DELAY strong y weak weak port latch data input data glitch rejection 002aaa914 Fig 8 Quasi bidirectional output 4 3 Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down transistor of the port pin when the port latch contains a logic To be used as a logic output a port configured in this manner must have an external pull up typically a resistor tied to Vpp The pull down for this mode is the same as for the quasi bidirectional mode The open drain port configuration is shown in Figure 9 An open drain port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC9301 931A1 data sheet Dynamic characteristics for glitch filter specifications port pin port latch data input data e glitch rejection 002aaa915 Fig 9 Open drain output 4 4 Input only configuration The input port configuration is shown in Figure 10 It is a Schmitt triggered input that also has a glitch suppression circuit UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 27 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Please refer to the P89LPC9301 931A1 data sheet Dynamic characteristics
78. DTOF LSB 98 RI STINT SPRO TOM2 88 ITO TOMO TRIM O WDCLK Hex Binary 00 0000 0000 00 0000 0000 07 0000 0111 04 0000 0100 00 OOxx xxxx 00 0000 0000 00 XXx0 xxxO 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 Jenueui Jesf LV IL 6 L0 60d 168d v 0LINn SJ0jonpuoolul8S dXN OLOZ J9qui9AON S Z jenuew sn 1oe qns s jueuinoop siy 6LL Jo GL YEEOLNN pamasa 51 0102 A d dXN Table 2 Special function registers continued indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary WDL Watchdog load C1H FF 1111 1111 WFEED1 Watchdog C2H feed 1 WFEED2 Watchdog C3H feed 2 1 All ports are in input only high impedance state after power up 2 BRGR and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable 3 RSTSRC register reflects the cause of the P89LPC9301 931A1 reset except BOIF bit Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is x011 0000 4 After reset the value is 1110 01x1 i e PRE2 to PREO are all logic 1 WDRUN 1 and WDCLK 1 WDTOF bit is logic 1 after watchdog reset and is logic 0 after p
79. ISP loader allowing for the device to be programmed in circuit through the serial port This ISP boot loader will in turn call low level routines through the same common entry point that can be used by the end user application Boot ROM When the microcontroller contains a a 256 byte Boot ROM that is separate from the user s Flash program memory This Boot ROM contains routines which handle all of the low level details needed to erase and program the user Flash memory A user program simply calls a common entry point in the Boot ROM with appropriate parameters to accomplish the desired operation Boot ROM operations include operations such as erase sector erase page program page CRC program security bit etc The Boot ROM occupies the program memory space at the top of the address space from FF00 to FFFFh thereby not conflicting with the user program memory space This function is in addition to the IAP Lite feature Power on reset code execution The P89LPC9301 931A1 contains two special Flash elements the BOOT VECTOR and the Boot Status Bit Following reset the P89LPC9301 931A1 examines the contents of the Boot Status Bit If the Boot Status Bit is set to zero power up execution starts at location 0000H which is the normal start address of the user s application code When the Boot Status Bit is set to one the contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to 00H The factory
80. NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 41 of 119 NXP Semiconductors U M1 0334 8 2 8 3 8 3 1 8 4 P89LPC9301 931A1 User manual Changing RTCS1 RTCSO RTCS1 RTCSO cannot be changed if the RTC is currently enabled RTCCON O 1 Setting RTCEN and updating RTCS1 RTCSO may be done in a single write to RTCCON However if RTCEN 1 this bit must first be cleared before updating RTCS1 RTCSO Real time clock interrupt wake up If ERTC RTCCON 1 EWDRT IEN1 0 6 and EA IENO 7 are set to logic 1 RTCF can be used as an interrupt source This interrupt vector is shared with the watchdog timer It can also be a source to wake up the device Real time clock read back Users can read RTCDATH and RTCDATL registers and get the 16 bit counter portion of the RTC Reset sources affecting the Real time clock Only power on reset and watchdog reset will reset the Real time Clock and its associated SFRs to their default state Table 30 Real time Clock System Timer clock sources FOSC2 0 RCCLK RTCS1 0 RTC clock source CPU clock source 000 0 00 High frequency crystal High frequency crystal DIVM 01 10 11 High frequency crystal DIVM 1 00 High frequency crystal Internal RC oscillator 01 10 11 Internal RC oscillator 001 0 00 Medium frequency crystal Medium frequency crystal DIVM 01 10 11 Medium frequency crystal DIVM 1 00 Medium frequency crystal Internal RC oscillator 01 10
81. OF are set but the other flag bits are cleared For any other reset previously set flag bits that have not been cleared will remain set UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 34 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual RPE UCFG1 6 WDTE UCFG1 7 watchdog timer reset 0 Software reset SRST AUXR1 3 gt chip reset power on detect UART break detect EBAR AUxR1 6 brownout detect reset 002aae129 Fig 12 Block diagram of reset Table 22 Reset Sources register RSTSRC address DFh bit allocation Bit Symbol Reset 7 6 5 4 3 2 1 0 BOIF BOF POF R BK R WD R SF R EX X 0 1 1 0 0 0 0 1 The value shown is for a power on reset Other reset sources will set their corresponding bits Table 23 Reset Sources register RSTSRC address DFh bit description Bit Symbol 0 REX R SF 2 RWD 3 RBK 4 POF 5 BOF 6 Description external reset Flag When this bit is logic 1 it indicates external pin reset Cleared by software by writing a logic to the bit or a Power on reset If RST is still asserted after the Power on reset is over R_EX will be set software reset Flag Cleared by software by writing a logic 0 to the b
82. P erase program or CRC the CPU enters a program idle state The CPU will remain in this program idle state until the erase program or CRC cycle is completed These cycles are self timed When the cycle is completed code execution resumes If an interrupt occurs during an erase programming or CRC cycle the erase programming or CRC cycle will be aborted so that the Flash memory can be used as the source of instructions to service the interrupt An IAP error condition will be flagged by setting the carry flag and status information returned The status information returned is shown in Table 84 If the application permits interrupts during erasing programming or CRC cycles the user code should check the carry flag after each erase programming or CRC operation to see if an error occurred If the operation was aborted the user s code will need to repeat the operation All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 103 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 84 1AP error status Bit Flag Description 0 Operation Interrupted Indicates that an operation was aborted due to an interrupt occurring during program or erase cycle 1 SV Security Violation Set if program or erase operation fails due to security settings Cycle is aborted Memory contents are unchanged CRC output is
83. XP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Writing the erase program command 68H to FMCON will start the erase program process and place the CPU in a program idle state The CPU will remain in this idle state until the erase program cycle is either completed or terminated by an interrupt When the program idle state is exited FMCON will contain status information for the cycle If an interrupt occurs during an erase programming cycle the erase programming cycle will be aborted and the OI flag Operation Interrupted in FMCON will be set If the application permits interrupts during erasing programming the user code should check the OI flag FMCON 0 after each erase programming operation to see if the operation was aborted If the operation was aborted the user s code will need to repeat the process starting with loading the page register The erase program cycle takes 4 ms 2 ms for erase 2 ms for programming to complete regardless of the number of bytes that were loaded into the page register Erasing programming of a single byte or multiple bytes in code memory is accomplished using the following steps Write the LOAD command 00H to FWCON The LOAD command will clear all locations in the page register and their corresponding update flags Write the address within the page register to FMADRL Since the loading the page register uses FMADRL 5 0 and since the erase program command uses FMADRH and FMADRL T7 6
84. a UCFG1 When functioning as a reset input a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 Also used during a power on sequence to force ISP mode P1 6 5 y o P1 6 Port 1 bit 6 High current source P1 7 y o P1 7 Port 1 bit 7 High current source P2 0 to P2 7 y o Port 2 Port 2 is an 8 bit I O port with a user configurable output type During reset Port 2 latches are configured in the input only mode with the internal pull up disabled The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 4 1 Port configurations for details All pins have Schmitt trigger inputs Port 2 also provides various special functions as described below P2 0 y o P2 0 Port 2 bit 0 P2 1 2 y o P2 1 Port 2 bit 1 P2 2 MOSI 13 y o P2 2 Port 2 bit 2 MOSI SPI master out slave in When configured as master this pin is output when configured as slave this pin is input P2 3 MISO 14 2 3 Port 2 bit 3 y o MISO When configured as master this pin is input when configured as slave this pin is output P2 4 SS 15 y o P2 4 Port 2 bit 4 SS SPI Slave select P2 5 SPICLK 16 y o P2 5 Port 2 bit 5 y o SPICLK SPI clock When configured as master this pin is output when configured as slave this pi
85. a bit that was received in Modes 2 and 3 In Mode 1 SM2 must be 0 RB8 is the stop bit that was received In Mode 0 RB8 is undefined TB8 The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired 4 REN Enables serial reception Set by software to enable reception Clear by software to disable reception 5 5 2 Enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit RB8 is 0 In Mode 0 SM2 should be 0 In Mode 1 SM2 must be 0 6 SMi With SMO defines the serial port mode see Table 39 7 SMO FE The use of this bit is determined by SMODO in the PCON register If SMODO 0 this bit is read and written as SMO which with SM1 defines the serial port mode If SMOD O 1 this bit is read and written as FE Framing Error FE is set by the receiver when an invalid stop bit is detected Once set this bit cannot be cleared by valid frames but is cleared by software Note UART mode bits SMO and SM1 should be programmed when SMODO is logic 0 default mode on any reset Table 39 Serial Port modes SMO SM1 00 01 10 11 UART mode UART baud rate Mode 0 shift register CCLK 6 default mode on any reset Mode 1 8 bit UART Variable see Table 34 Mode 2 9 bit UART COLE CCLKA 6 Mode 3 9 bit UART Variable see Table 34 Table 40 Serial Port Status register SSTAT addres
86. an IAP routine that requires an authorization key is called without a valid authorization key present the MCU will perform a reset Flash write enable This device has hardware write enable protection This protection applies to both ISP and IAP modes and applies to both the user code memory space and the user configuration bytes UCFG1 UCFG2 BOOTVEC and BOOTSTAT This protection does not apply to ICP or parallel programmer modes If the Activate Write Enable AWE bit in BOOTSTAT 7 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 102 of 119 NXP Semiconductors U M1 0334 UM10334 16 15 16 16 P89LPC9301 931A1 User manual is alogic 0 an internal Write Enable WE flag is forced set and writes to the flash memory and configuration bytes are enabled If the Active Write Enable AWE bit is a logic 1 then the state of the internal WE flag can be controlled by the user The WE flag is SET by writing the Set Write Enable 08H command to FMCON followed by a key value 96H to FMDATA FMCON 0x08 FMDATA 0x96 The WE flag is CLEARED by writing the Clear Write Enable OBH command to FACON followed by a key value 96H to FMDATA or by a reset FMCON 0x0B FMDATA 0x96 The ISP function in this device sets the WE flag prior to calling the IAP routines The IAP function in this device executes a Clear Write E
87. and I2SCLH to select the data rate 25 defines the number of PCLK cycles for SCL high I2SCLL defines the number of PCLK cycles for SCL low The frequency is determined by the following formula Bit Frequency 2 IBSCLH I2SCLL Where fpc x is the frequency of PCLK All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 58 of 119 NXP Semiconductors U M1 0334 UM10334 10 6 10 6 1 P89LPC9301 931A1 User manual The values for I2SCLL and I2SCLH do not have to be the same the user can give different duty cycles for SCL by setting these two registers However the value of the register must ensure that the data rate is in the I C data rate range of 0 to 400 kHz Thus the values of I2SCLL and I2SCLH have some restrictions and values for both registers greater than three PCLKs are recommended Table 52 12C clock rates selection Bit data rate Kbit sec at fosc I2SCLL CRSEL 7 373 MHz 3 6865 MHz 1 8433 MHz 12 MHz 6 MHz I2SCLH 6 0 307 154 7 0 263 132 8 0 230 115 375 9 0 205 102 333 10 0 369 184 92 300 15 0 246 123 61 400 200 25 0 147 74 37 240 120 30 0 123 61 31 200 100 50 0 74 37 18 120 60 60 0 61 31 15 100 50 100 0 37 18 9 60 30 150 0 25 12 6 40 20 200 0 18 9 5 30 15 1 3 6 Kbps to 1 8 Kbpsto 0 9 Kbpsto 5 86 Kbpsto 2 93 Kbps to 922 Kbps 4
88. and reset value of CLKDBL bit comes from UCFG2 7 Jenuew Jesf LV L 6 L0 60d 168d YESO LNN SJ0jonpuoolul9S dXN NXP Semiconductors U M1 0334 1 6 P89LPC9301 931A1 User manual Memory organization FFOOh FFEFh 1FFFh 1 00h 1C00h 1BFFh 1800h 17FFh 1400h 13FFh 1000h OFFFA OCOOh OBFFh 0800h 07FFh 0400h O3FFh 0000h SECTOR 6 SECTOR 5 SECTOR 4 SECTOR 3 SECTOR2 SECTOR 1 SECTOR 0 read protected IAP calls only FFEFh FFh IDATA routines IDATA incl DATA entry points for SPECIAL FUNCTION 128 BYTES ON CHIP FF1Fh sI code Se REGISTERS DATA MEMORY STACK C code FFO0h DIRECTLY ADDRESSABLE AND INDIR ADDR 80h DATA 7Fh 128 BYTES ON CHIP 1FFFh DATA MEMORY STACK DIRECT AND INDIR ADDR 4 REG BANKS R 7 0 ISP serial loader entry points for UART auto baud I2C SPI etc 1 00h 1E00h data memory DATA IDATA FFFFh EXTENDED SFRs FFBOh RESERVED 0000h XDATA 002aae484 1 ISP code is located at the end of sector on the P89LPC9301 and at the end of sector 7 on the P89LPC931A1 Fig 4 P89LPC9301 931A1 memory map The various P89LPC9301 931A1 memory spaces are as follows DATA 128 bytes of internal data memory space 00h 7Fh accessed via direct or indirect addressing using instruction other than MOVX and MOVC All or part of the Stack may be in this area IDATA Indirect Data 2
89. arator as determined by the control bits in the corresponding CMPn register CPn CNn and OEn These configurations are shown in Figure 40 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 79 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual When each comparator is first enabled the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds The corresponding comparator interrupt should not be enabled during that time and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service Table 65 Comparator Control register CMP1 address ACh CMP2 address ADh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CEn CPn CNn OEn COn CMFn Reset X X 0 0 0 0 0 0 Table 66 Comparator Control register CMP1 address ACh CMP2 address ADh bit description Bit Symbol Description 0 CMFn Comparator interrupt flag This bit is set by hardware whenever the comparator output COn changes state This bit will cause a hardware interrupt if enabled Cleared by software COn Comparator output synchronized to the CPU clock to allow reading by software 2 OEn Output enable When logic 1 the comparator output is connected to the CMPn pin if the comparator is enabled CEn 1 This output is asynchronous
90. are received from a master transmitter To initialize the Slave Receiver Mode the user should write the slave address to the Slave Address Register IBADR and the I C Control Register ICON should be configured as follows Table 54 1 C Control register I2CON address D8h Bit 7 6 5 4 3 2 1 0 I2EN STA STO SI AA CRSEL value 1 0 0 0 1 CRSEL is not used for slave mode I2EN must be set 1 to enable I C function AA bit must be set 1 to acknowledge its own slave address or the general call address STA STO and SI are cleared to 0 After I2ADR and I2CON are initialized the interface waits until it is addressed by its own address or general address followed by the data direction bit which is O W If the direction bit is 1 R it will enter Slave Transmitter Mode After the address and the direction bit have been received the SI bit is set and a valid status code can be read from the Status Register I2S TAT Refer to Table 58 for the status codes and actions UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 61 of 119 NXP Semiconductors U M1 0334 UM10334 P89LPC9301 931A1 User manual logic write data transferred logic 1 read n Bytes acknowledge acknowledge SDA LOW from Master to Slave A not acknowledge SDA HIGH from Slave to Master S STAHT condition
91. bit The 12C logic will send the START condition as soon as the bus is free After the START condition is transmitted the SI bit is set and the status code in I2STAT should be 08h This status code must be used to vector to an interrupt service routine where the user should load the slave address to I2DAT Data Register and data direction bit SLA W The SI bit must be cleared before the data transfer can continue When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the SI bit is set again and the possible status codes are 18h 20h or 38h for the master mode or 68h 78h or OBOh if the slave mode was enabled setting AA Logic 1 The appropriate action to be taken for each of these status codes is shown in Table 55 ZEN cd logic 0 write L data transferred _ logic 1 read n Bytes acknowledge A acknowledge SDA LOW from Master to Slave not acknowledge SDA HIGH from Slave to Master S START condition P STOP condition 002aaa929 Fig 25 Format in the Master Transmitter mode 10 6 2 Master Receiver mode In the Master Receiver Mode data is received from a slave transmitter The transfer started in the same manner as in the Master Transmitter Mode When the START condition has been transmitted the interrupt service routine must load the slave address and the data direction bit to IC Data Register I2DAT The SI bit must be cleared before the
92. can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt 7 5 Mode6 In this mode the corresponding timer can be changed to a PWM with a full period of 256 timer clocks see Figure 17 Its structure is similar to mode 2 except that e TFn n 0 and 1 for Timers 0 and 1 respectively is set and cleared in hardware The low period of the TFn is in THn and should be between 1 and 254 and The high period of the TFn is always 256 THn Loading THn with 00h will force the Tx pin high loading THn with FFh will force the Tx pin low Note that interrupt can still be enabled on the low to high transition of TFn and that TFn can still be cleared in software like in any other modes Table 28 Timer Counter Control register TCON address 88h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TF1 TR1 TFO TRO IE1 IT1 IEO ITO Reset 0 0 0 0 0 0 0 0 Table 29 Timer Counter Control register TCON address 88h bit description Bit Symbol Description 0 ITO Interrupt O Type control bit Set cleared by software to specify falling edge low level triggered external interrupts 1 IEO Interrupt O Edge flag Set by hardware when external interrupt 0 edge is detected Cleared by hardware when the interrupt is processed or by software 2 IT1 Interrupt 1 Type control bit Set cleared by software to specify falling edge low level triggered external interrupts UM10334 All information provided
93. curs the contents of WDL is reloaded into the down counter and the watchdog timer immediately begins to count down again A feed is necessary to cause WDL to be loaded into the down counter before an underflow occurs Incorrect feeds are ignored in this mode UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 89 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual PCLK Watchdog oscillator MOV WFEED1 0A5H MOV WFEED2 05AH oscillator i PRESCALER m interrupt A A XTALWD Fig 43 Watchdog Timer in Timer Mode WDTE 0 002aae094 14 5 Power down operation 14 6 The WDT oscillator and low speed crystal oscillator will continue to run in power down consuming approximately 50 LA as long as the WDT oscillator is selected as the clock source for the WDT Selecting PCLK as the WDT source will result in the WDT oscillator going into power down with the rest of the device see Section 14 3 Power down mode will also prevent PCLK from running and therefore the watchdog is effectively disabled Periodic wake up from power down without an external oscillator Without using an external oscillator source the power consumption required in order to have a periodic wake up is determined by the power consumption of the internal oscillator
94. d if CPHA is logic 0 and SSIG is logic 1 When CPHA equals one SSIG may be set to logic 1 If SSIG 0 the SS pin may remain active low between successive transfers can be tied low at all times This format is sometimes preferred in systems having a single fixed master and a single slave driving the MISO data line Additional considerations for a master In SPI transfers are always initiated by the master If the SPI is enabled SPEN 1 and selected as master writing to the SPI data register by the master starts the SPI clock generator and data transfer The data will start to appear on MOSI about one half SPI bit time to one SPI bit time after data is written to SPDAT Note that the master can select a slave by driving the SS pin of the corresponding device low Data written to the SPDAT register of the master is shifted out of the MOSI pin of the master to the MOSI pin of the slave at the same time the data in SPDAT register in slave side is shifted out on MISO pin to the MISO pin of the master After shifting one byte the SPI clock generator stops setting the transfer completion flag SPIF and an interrupt will be created if the SPI interrupt is enabled ESPI or IEN1 3 1 The two shift registers in the master CPU and slave CPU can be considered as one distributed 16 bit circular shift register When data is shifted from the master to the slave data is also shifted in the opposite direction simultaneously This means that during
95. d rate BDH SBRGS BRGEN 0021 xxxx xx00 generator 0 control CMP1 Comparator 1 ACH CE1 CP1 CN1 OE1 CO1 CMF1 ool xx00 0000 control register CMP2 Comparator 2 ADH 2 2 CN2 OE2 2 CMF2 0021 xx00 0000 control register DIVM CPU clock 95H 00 0000 0000 divide by M control DPTR Data pointer 2 bytes DPH Data pointer 83H 00 0000 0000 high DPL Data pointer 82H 00 0000 0000 low FMADRH Program flash E7H 00 0000 0000 address high FMADRL Program flash E6H 00 0000 0000 address low SIOJONPUODIWIS dXN Jenuew Jesf LW LE6 LOE6Dd 168d v 0LINn OLOZ J9qui9AON S Z jenuew sn 1oe qns s jueuinoop siy uoreuuojul 6LL 40 LL YEEOLNN pamasa 51 0102 A d dXN Table 2 Special function registers continued indicates SFRs that are bit addressable Name FMCON FMDATA I2ADR I2CON I2DAT I2SCLH I2SCLL I2STAT IENO IEN1 Description SFR addr Program flash EAH control Read Program flash EAH control Write Program flash EBH data I C bus slave DBH address register Bit address I2C bus control D8H register 2 data DAH register Serial clock DDH generator SCL duty cycle register high Serial clock DCH generator SCL duty cycle register low I2C bus status D9H register Bit address Interrupt A8H enable 0 Bit address Interrup
96. d when Power down mode or Idle mode is activated but both comparators are disabled automatically in Total Power down mode If a comparator interrupt is enabled except in Total Power down mode a change of the comparator output state will generate an interrupt and wake up the processor If the comparator output to a pin is enabled the pin should be configured in the push pull mode in order to obtain fast switching times while in Power down mode The reason is that with the oscillator stopped the temporary strong pull up that normally occurs during switching on a quasi bidirectional port pin does not take place Comparators consume power in Power down mode and Idle mode as well as in the normal operating mode This should be taken into consideration when system power consumption is an issue To minimize power consumption the user can power down the comparators by disabling the comparators and setting PCONA 5 to logic 1 or simply putting the device in Total Power down mode UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 81 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual CINnA CINnA COn CMPREF gt m CMPREF gt CME 002aaa618 002aaa620 a CPn CNn OEn 000 b CPn CNn OEn 001 CINnA CINnA COn Vner 1 23 V COn Vper 1 23 V m 002 621 002aaa622 c CPn CNn 010 d CPn
97. data received The CPU can read and write to this 8 bit register while it is not in the process of shifting a byte Thus this register should only be accessed when the SI bit is set Data in I2DAT remains stable as long as the SI bit is set Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT Table 45 1 C data register IBDAT address DAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2DAT 7 1 2 0 6 120 5 120 4 lI2DAT3 lI2DAT2 1 20 1 I2DAT O Reset 0 0 0 0 0 0 0 0 I C slave address register I2ADR register is readable and writable and is only used when the 12 interface is set to slave mode In master mode this register has no effect The LSB of I2ADR is general call bit When this bit is set the general call address 00h is recognized Table 46 1 C slave address register IZADR address DBh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2ADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR 0 GC Reset 0 0 0 0 0 0 0 0 Table 47 1 C slave address register IZADR address DBh bit description Bit Symbol Description 0 GC General call bit When set the general call address 00H is recognized otherwise it is ignored 1 7 I2ADR1 7 7 bit own slave address When in master mode the contents of this register has no effect All information provided in this d
98. data transfer can continue When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status codes are 40H 48H or 38H For slave mode the possible status codes are 68H 78H or BOH Refer to Table 57 for details UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 60 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Eee 8T logic write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW from Master to Slave A not acknowledge SDA HIGH from Slave to Master S START condition 002aaa930 Fig 26 Format of Master Receiver mode After a repeated START condition I2C bus may switch to the Master Transmitter Mode Ts TT om logic 0 write L data transferred _ logic 1 read n Bytes acknowledge A acknowledge SDA LOW from Master to Slave not acknowledge SDA HIGH L from Slave to Master S START condition P STOP condition SLA slave address RS repeat START condition 002aaa931 Fig 27 A Master Receiver switches to Master Transmitter after sending Repeated Start 10 6 3 Slave Receiver mode In the Slave Receiver Mode data bytes
99. default settings for this device is shown in Table 82 below The factory pre programmed boot loader can be erased by the user Users who wish to use this loader should take cautions to avoid erasing the last 1 kB sector on the device Instead the page erase function can be used to erase the eight 64 byte pages located in this sector A custom boot loader can be written with the Boot Vector set to the custom boot loader if desired Table 82 Boot loader address and default Boot vector Product P89LPC9301 P89LPC931A1 Flash size End Signature bytes Sector Page Pre programmed Default Boot address Mfg id Id 1 Id 2 size size serial loader vector 4kBx8 OFFFh 15h 35h 1kBx8 64x8 OEOO0h to OFFFh OFh 8kB x8 1FFFh 15h 36h 1kBx8 64x8 1E00h to 1FFFh 1Fh UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 97 of 119 NXP Semiconductors U M1 0334 UM10334 16 9 16 10 16 11 P89LPC9301 931A1 User manual Hardware activation of Boot Loader The boot loader can also be executed by forcing the device into ISP mode during a power on sequence see Figure 44 This is accomplished by powering up the device with the reset pin initially held low and holding the pin low for a fixed time after Vpp rises to its normal operating value This is followed by three and only three properly timed low going pulses
100. des 1 2 and 3 If double buffering is disabled DBMOD i e SSTAT 7 0 TB8 can be written before or after SBUF is written provided TB8 is updated before that TB8 is shifted out TB8 must not be changed again until after TB8 shifting has been completed as indicated by the Tx interrupt UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 52 of 119 NXP Semiconductors U M1 0334 UM10334 9 19 P89LPC9301 931A1 User manual If double buffering is enabled TB8 MUST be updated before SBUF is written as TB8 will be double buffered together with SBUF data The operation described in the Section 9 17 Transmit interrupts with double buffering enabled Modes 1 2 and 3 becomes as follows The double buffer is empty initially The CPU writes to TB8 The CPU writes to SBUF The SBUF TB8 data is loaded to the shift register and a Tx interrupt is generated immediately gt A N 5 If there is more data go to 7 else continue on 6 6 If there is no more data then If DBISEL is logic 0 no more interrupt will occur If DBISEL is logic 1 and INTLO is logic 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data f DBISEL is logic 1 and INTLO is logic 1 a Tx interrupt will occur at the end of the STOP bit of
101. description 3 Logic 7 Block 8 Special function registers 9 Memory organization 17 Clocks lk x RR RR ae 18 Enhanced 18 Clock definitions 18 Oscillator Clock OSCCLK 18 Crystal oscillator 18 Low speed oscillator option 18 Medium speed oscillator option 18 High speed oscillator option 18 Clock 19 On chip RC oscillator option 19 Watchdog oscillator option 20 External clock input option 20 Clock source switching on the fly 21 Oscillator Clock OSCCLK wake up delay 22 CPU Clock CCLK modification DIVM Ieglster iuuenes Yaa PS dha ES 22 Low power select 22 Interrupts 22 Interrupt priority structure 23 External Interrupt pin glitch suppression 24 VO POMS seduce cea Ehe REFER Rai 25 Port configurations 25 Quasi bidirectional output configuration 26 Open drain output configuration 27 Input only configuration 27 Push pull output configuration 28 Port 0 and Analog Comparator functions 28 Additional port features
102. disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 71 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 63 SPI Data register SPDAT address E3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol LSB Reset 0 0 0 0 0 0 0 0 master slave MISO MISO 8 BIT SHIFT F T 8 BIT SHIFT REGISTER MOS MOSI REGISTER SPICLOCK 7 2 GENERATOR PORT SS 1 1 1 1 1 1 1 1 1 1 1 1 1 SPICLK SPICLK 1 1 T 1 1 1 1 1 002 901 1 1 1 Fig 32 SPI single master single slave configuration In Figure 32 SSIG SPCTL 7 for the slave is logic 0 and SS is used to select the slave The SPI master can use any port pin including P2 4 SS to drive the SS pin master slave 8 BIT SHIFT E REGISTER 8 BIT SHIFT REGISTER SPI CLOCK T GENERATOR 2 5 SPICLOCK SS GENERATOR 1 1 1 1 1 1 1 1 1 1 1 1 SPICLK 1 1 T 1 1 1 1 1 002aaa902 1 1 1 Fig 33 SPI dual device configuration where either can be a master or a slave Figure 33 shows a case where two devices are connected to each other and either device can be a master or a slave When no SPI operation is occurring both can be configured as masters MSTR 1 with SSIG cleared to 0 and P2 4 SS configured in quasi bidirectional mode When a device initiates a transfer it can configure P2 4 as a
103. e Interrupt priority structure Table 10 Interrupt priority level Priority bits IPXH IPx Interrupt priority level 0 0 Level 0 lowest priority 0 1 Level 1 1 0 Level 2 1 1 Level 3 There are four SFRs associated with the four interrupt levels IPO IPOH IP1 IP1H Every interrupt has two bits in IPx and IPxH x 0 1 and can therefore be assigned to one of four levels as shown in Table 11 The P89LPC9301 931A1 has two external interrupt inputs in addition to the Keypad Interrupt function The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers These external interrupts can be programmed to be level triggered or edge triggered by clearing or setting bit IT1 or ITO in Register TCON If ITn 0 external interrupt n is triggered by a low level detected at the INTn pin If Tn 1 external interrupt n is edge triggered In this mode if consecutive samples of the INTn pin show a high level in one cycle and a low level in the next cycle interrupt request flag IEn in TCON is set causing an interrupt request Since the external interrupt pins are sampled once each machine cycle an input high or low level should be held for at least one machine cycle to ensure proper sampling If the external interrupt is edge triggered the external source has to hold the request pin high for at least one machine cycle and then hold it low for at least one machine cycle This is to ensure that the
104. ecome disabled when the old clock source is disabled For example suppose PCLK WCLK 0 is the current clock source After WCLK is set to logic 1 the program should wait at least two PCLK cycles 4 CCLKs after the feed completes before going into Power down mode Otherwise the watchdog could become disabled when CCLK turns off The watchdog oscillator will never become selected as the clock source unless CCLK is turned on again first All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 88 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual MOV WFEED 1 0 5 MOV WFEED2 05AH Watchdog Lo 8 BIT DOWN oscillator z raset A A A oscillator D E 1 D SHADOW REGISTER XTALWD A A ADL pace reer Toe T T worun woror woo 002aae093 WDCON A7H Fig 42 Watchdog Timer in Watchdog Mode WDTE 1 14 4 Watchdog Timer in Timer mode Figure 43 shows the Watchdog Timer in Timer Mode In this mode any changes to WDCON are written to the shadow register after one watchdog clock cycle A watchdog underflow will set the WDTOF bit If IENO 6 is set the watchdog underflow is enabled to cause an interrupt WDTOF is cleared by writing a logic O to this bit in software When an underflow oc
105. ection 2 10 CPU Clock CCLK modification DIVM register Note fosc is defined as the OSCCLK frequency CCLK CPU clock output of the DIVM clock divider There are two CCLK cycles per machine cycle and most instructions are executed in one to two machine cycles two or four CCLK cycles RCCLK The internal 7 373 MHz RC oscillator output The clock doubler option when enabled provides an output frequency of 14 746 MHz Clock for the various peripheral devices and is CCLK 2 2 4 Oscillator Clock OSCCLK The P89LPC9301 931A1 provides several user selectable oscillator options in generating the CPU clock This allows optimization for a range of needs from high precision to lowest possible cost These options are configured when the flash is programmed and include an on chip watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source 2 3 Crystal oscillator option The crystal oscillator can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 18 MHz It can be the clock source of OSCCLK and RTC Low speed oscillator option can be the clock source of WDT 2 3 1 Low speed oscillator option This option supports an external crystal in the range of 20 kHz to 100 kHz Ceramic resonators are also supported in this configuration 2 3 2 Medium speed oscillator option This option supports an external crystal in the range of 100 kHz to 4 MHz Ceramic r
106. ectional output 27 Fig9 27 Fig 10 Inputonly llle 28 Fig 11 Push pull output 28 Fig 12 Block diagram of 35 Fig 13 Timer counter 0 or 1 in Mode 0 13 bit counter 39 Fig 14 Timer counter 0 or 1 in mode 1 16 bit counter 39 Fig 15 Timer counter 0 or 1 in Mode 2 8 bit auto reload 39 Fig 16 Timer counter 0 Mode two 8 bit counters 40 Fig 17 Timer counter 0 or 1 in mode 6 PWM auto reload ne ER eR RR 40 Fig 18 Real time clock system timer block diagram 41 Fig 19 Baud rate generation for UART Modes 1 3 46 Fig 20 Serial Port Mode 0 double buffering must be disabled iid e E teret ud 49 Fig 21 Serial Port Mode 1 only single transmit buffering case is 5 50 Fig 22 Serial Port Mode 2 or 3 only single transmit buffering case is shown 50 Fig 23 Transmission with and without double buffering 52 Fig 24 12 56 Fig 25 Format in the Master Transmitter mode 60 Fig 26 Format of Master Receiver mode 61 Fig 27 A Master Receiver switches to Master Transmitter after sending Repeated Start 61 Fig 28 Format of Slave Receiver mode 62 Fig 29 Format of Slave Transmitter mode
107. ecurity Byte 2 OB Security Byte 3 0C Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 10 Clear Configuration Protection Return parameter s R7 status Carry set on error clear on no error All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 105 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 85 IAP function calls continued IAP function IAP call parameters Misc Read Input parameters ACC 03h R7 register address 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 to 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 0C Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 Return parameter s R7 register data if no error else error status Carry set on error clear on no error Erase Sector Page Input parameters requires key ACC 04h R4 address MSB R5 address LSB R7 OOH erase page or 01H erase sector Return parameter s R7 data Carry set on error clear on no error UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 106 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 85 IAP func
108. emory 2 1 76 to 77 MOV data Move immediate to data pointer 3 2 90 MOVC A A DPTR Move code byte relative DPTR to A 1 2 93 MOVC Move code byte relative PC to A 1 2 94 MOVX A Ri Move external data A8 to A 1 2 E2 to MOVX A DPTR Move external data A16 to A 1 2 EO MOVX Ri A Move A to external data A8 1 2 F2 to F3 MOVX QDPTR A Move A to external data A16 1 2 FO PUSH dir Push direct byte onto stack 2 2 CO POP dir Pop direct byte from stack 2 2 DO XCH A Rn Exchange A and register 1 1 C8 to CF XCH A dir Exchange A and direct byte 2 1 C5 XCH A Ri Exchange A and indirect memory 1 1 C6 to C7 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 112 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual Table 98 Instruction set summary continued Mnemonic Description Bytes Cycles Hex code XCHD A Ri Exchange A and indirect memory nibble 1 1 D6 to D7 BOOLEAN Mnemonic Description Bytes Cycles Hex code CLR C Clear carry 1 1 C3 CLR bit Clear direct bit 2 1 C2 SETBC Set carry 1 1 D3 SETB bit Set direct bit 2 1 D2 CPLC Complement carry 1 1 B3 CPL bit Complement direct bit 2 1 B2 ANL C bit AND direct bit to carry 2 2 82 ANL C bit AND direct bit inverse to carry 2 2 BO ORL C bit OR direct bit to carry 2 2 72 ORL C bit OR direct bit inverse to carr
109. en the value written to FMDATA will be stored in the page register at the location specified by the lower 6 bits of FMADRL In addition the update flag for that location will be set FMADRL will auto increment to the next location Auto increment after writing to the last byte in the page register will wrap around to the first byte in the page register but will not affect FMADRL 7 6 Bytes loaded into the page register do not have to be continuous Any byte location can be loaded into the page register by changing the contents of FMADRL prior to writing to FMDATA However each location in the page register can only be written once following each LOAD command Attempts to write to a page register location more than once should be avoided FMADRH and FMADRL 7 6 are used to select a page of code memory for the erase program function When the erase program command is written to FMCON the locations within the code memory page that correspond to updated locations in the page register will have their contents erased and programmed with the contents of their corresponding locations in the page register Only the bytes that were loaded into the page register will be erased and programmed in the user code array Other bytes within the user code memory will not be affected UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 93 of 119 N
110. enerator Rate High Byte BRGRO Baud Rate Generator Rate Low Byte BRGCON Baud Rate Generator Control BDH Baud Rate generator and selection The P89LPC9301 931A1 enhanced UART has an independent Baud Rate Generator The baud rate is determined by a value programmed into the BRGR1 and BRGRO SFRs The UART can use either Timer 1 or the baud rate generator output as determined by BRGCON 2 1 see Figure 19 Note that Timer T1 is further divided by 2 if the SMOD bit PCON 7 is set The independent Baud Rate Generator uses CCLK Updating the BRGR1 and BRGRO SFRs The baud rate SFRs BRGR1 and BRGRO must only be loaded when the Baud Rate Generator is disabled the BRGEN bit in the BRGCON register is logic 0 This avoids the loading of an interim value to the baud rate generator CAUTION If either BRGRO or BRGR1 is written when BRGEN 1 the result is unpredictable Table 34 UART baud rate generation SCON 7 SCON 6 PCON 7 BRGCON 1_ Receive transmit baud rate for UART SMO SM1 SMOD1 SBRGS 0 0 X X CCLKy 6 0 1 0 0 CELK os6 TH1 64 1 0 CELK ose TH1 32 X 1 CCLKY BRGR1 BRGRO 16 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 45 of 119 NXP Semiconductors U M1 0334 UM10334 9 8 9 9 P89LPC9301 931A1 User manual Table 34 UART baud rate generation continued SCON 7 SCON 6 PCON 7 BRGCON
111. ent is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 18 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves
112. er which is also the last data If DBISEL is logic 1 and INTLO is logic 1 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following there is more data the CPU writes to SBUF again Then If INTLO is logic 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter Go to 3 write to SBUF TX interrupt TXD write to SBUF TX interrupt TXD write to SBUF TX interrupt Fig 23 Transmission with and without double buffering single buffering DBMOD SSTAT 7 0 early interrupt INTLO SSTAT 6 0 is shown i double buffering DBMOD SSTAT 7 1 early interrupt INTLO SSTAT 6 0 is shown no ending TX interrupt DBISEL SSTAT 4 0 double buffering DBMOD SSTAT 7 1 early interrupt INTLO SSTAT 6 0 is shown with ending TX interrupt DBISEL SSTAT 4 1 002aaa928 9 18 The 9th bit bit 8 in double buffering Mo
113. er into RO LOAD_PAGE OV FMDAT GRO write data to page register INC RO point to next byte DJNZ R3 LOAD PAGE do until count is zero OV FMCON EP else erase amp program the page UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 95 of 119 NXP Semiconductors U M1 0334 UM10334 P89LPC9301 931A1 User manual MOV R7 FMCON copy status for return MOV A R7 read status ANL A 0FH save only four lower bits JNZ BAD CLR clear error flag if good RET and return BAD SETB C set error flag RET and return A C language routine to load the page register and perform an erase program operation is shown below include REG9301 H unsigned char idata dbytes 64 data buffer unsigned char Fm stat status result bit PGM USER unsigned char unsigned char bit prog fail void main prog fail PGM USER Ox1F 0xC0 bit USER unsigned char page hi unsigned char page 10 define LOAD0x00 clear page register enable loading define EP x68 erase amp program page unsigned char i loop count FMCON LOAD load command clears page reg FMADRH page hi FMADRL page lo write my page address to addr regs for 1 0 1 lt 64 1 1 1 FMDATA dbytes i FMCON EP erase amp prog page command Fm_stat FMCON read the result status if Fm stat amp Ox0F 0 prog fail 1 el
114. esonators are also supported in this configuration 2 3 3 High speed oscillator option This option supports an external crystal in the range of 4 MHz to 18 MHz Ceramic resonators are also supported in this configuration UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 18 of 119 NXP Semiconductors U M1 0334 2 4 2 5 P89LPC9301 931A1 User manual Clock output The P89LPC9301 931A1 supports a user selectable clock output function on the XTAL2 CLKOUT pin when the crystal oscillator is not being used This condition occurs if a different clock source has been selected on chip RC oscillator watchdog oscillator external clock input on X1 and if the Real time Clock and Watchdog Timer are not using the crystal oscillator as their clock source This allows external devices to synchronize to the P89LPC9301 931A1 This output is enabled by the ENCLK bit in the TRIM register The frequency of this clock output is that of the CCLK If the clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power Note on reset the TRIM SFR is initialized with a factory preprogrammed value Therefore when setting or clearing the ENCLK bit the user should retain the contents of other bits of the TRIM register This can be done by reading the contents of the TRIM register into the ACC for example
115. gnition of own SLA or transmitted General call address AA 0 ACK I2DAT action 0 0 0 1 Switched to addressed SLA has been received or mode Own slave address will be recognized General call address will be recognized if IZADR 0 1 nol2DAT action 1 0 0 0 Switched to not addressed SLA or mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free nol2DAT action 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IDADR O 1 A START condition will be transmitted when the bus becomes free 11 Serial Peripheral Interface SPI UM10334 The P89LPC9301 931A1 provides another high speed serial communication interface the SPI interface SPI is a full duplex high speed synchronous communication bus with two operation modes Master mode and Slave mode Up to 3 Mbit s can be supported in either Master or Slave mode It has a Transfer Completion Flag and Write Collision Flag Protection All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 69 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual CPU clock SPR 8 BIT SHIFT REGISTER DIVIDER READ DATA BUFFER BY 4 16 64 128 MESE NS o
116. gured as input and SSIG 0 Should this happen the SPIF bit SPSTAT 7 will be set see Section 11 4 Mode change on SS Typical connections are shown in Figure 32 to Figure 34 Table 59 SPI Control register SPCTL address E2h bit allocation Bit 7 6 5 4 3 2 Symbol 560 SPEN DORD MSTR CPOL CPHA Reset 0 0 0 0 0 1 1 0 SPR1 SPRO 0 0 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 70 of 119 NXP Semiconductors U M1 0334 UM10334 P89LPC9301 931A1 User manual Table 60 SPI Control register SPCTL address E2h bit description Bit Symbol Description 0 SPRO SPI Clock Rate Select 1 SPR1 SPR1 SPRO 00 01 CCLKY 6 10 CCK 11 CCLKy 28 2 SPI Clock PHAse select see Figure 35 to Figure 38 1 Data is driven on the leading edge of SPICLK and is sampled on the trailing edge 0 Data is driven when SS is low SSIG 0 and changes on the trailing edge of SPICLK and is sampled on the leading edge Note If SSIG 1 the operation is not defined 3 SPI Clock POLarity see Figure 35 to Figure 38 1 SPICLK is high when idle The leading edge of SPICLK is the falling edge and the trailing edge is the rising edge 0 SPICLK is low when idle The leading edge of SPICLK is the rising edge and the trailing edge is the falling edge
117. h in any sources of watchdog oscillator 7 14MHz IRC oscillator crystal oscillator and external clock input during code is running CLKOK bit in register CLKCON is read only and used to indicate the clock switch status When CLKOK is 0 clock switch is processing not completed When CLKOK is 1 clock switch is completed When start new clock source switch CLKOK is cleared automatically Notice that when CLKOK is 0 Writing to CLKCON register is not allowed During reset CLKCON register value comes from UCFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to UCFG1 0 and reset value of CLKDBL bit comes from UCFG2 7 Table 7 Clock control register CLKCON address FFDEh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKOK XTALWD CLKDBL FOSC2 FOSC1 FOSCO Reset 1 0 0 0 x X X X Table8 Clock control register address FFDEh bit description Bit Symbol Description 2 0 FOSC2 FOSC1 oscillator type selection for clock switch See Section 2 for additional FOSCO information Combinations other than those shown in Table 9 are reserved for future use and should not be used 3 CLKDBL Clock doubler option for clock switch When set doubles the output frequency of the internal RC oscillator 4 XTALWD Low speed external crystal oscillator as the clock source of watchdog timer When 0 disable the external crystal oscillator as the clock source of watchdog timer 6 5 reserved
118. he 8 bit down counter before a time out occurs The number of watchdog clocks before timing out is calculated by the following equations telks 20 FD YXWDL 41 41 1 where PRE is the value of prescaler PRE2 to PREO which can be the range 0 to 7 and WDL is the value of watchdog load register which can be the range of 0 to 255 The minimum number of tclks is tclks 20 9 04 1 12 33 2 The maximum number of tclks is All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 86 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual tclks 2 255 1 1 1048577 3 Table 76 shows sample P89LPC9301 931A1 timeout values Table 74 Watchdog Timer Control register WDCON address A7h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PRE2 PRE1 PREO WDRUN WDTOF WDCLK Reset 1 1 1 X 1 1 0 1 Table 75 Watchdog Timer Control register WDCON address A7h bit description Bit Symbol Description WDCLK Watchdog input clock select When set the watchdog oscillator is selected When cleared PCLK is selected If the CPU is powered down the watchdog is disabled if WDCLK 0 see Section 14 5 Note If both WDTE and WDSE are set to 1 this bit is forced to 1 Refer to Section 14 3 for details 1 WDTOF Watchdog Timer Time Out Flag This bit is set when the 8 bit down counter
119. he I C interface is in the Master Receiver Mode 2 A data byte has been received while the 12C interface is in the addressed Slave Receiver Mode UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 57 of 119 NXP Semiconductors U M1 0334 UM10334 10 4 10 5 P89LPC9301 931A1 User manual Table 49 12 Control register 2 address D8h bit description continued Bit Symbol Description 3 SI 2 Interrupt Flag This bit is set when one of the 25 possible I2C states is entered When EA bit and EI2C IEN1 0 bit are both set an interrupt is requested when SI is set Must be cleared by software by writing O to this bit 4 STO STOP Flag STO 1 In master mode a STOP condition is transmitted to the I2C bus When the bus detects the STOP condition it will clear STO bit automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed Slave Receiver Mode The STO flag is cleared by hardware automatically 5 STA Start Flag STA 1 I2C bus enters master mode checks the bus and generates START condition if the bus is free If the bus is not free it waits fora STOP condition which will free the bus and generates a START condition af
120. he Real time clock system timer can be enabled by setting the RTCEN RTCCON O bit The Real time Clock is a 23 bit down counter initialized to all 0 s when RTCEN 0 that is comprised of a 7 bit prescaler and a 16 bit loadable down counter When RTCEN is written with logic 1 the counter is first loaded with RTCH RTCL 1111111 and will count down When it reaches all 0 s the counter will be reloaded again with RTCH RTCL 1111111 and a flag RTCF RTCCON 7 will be set The 16 bit counter portion of the RTC is readable by reading the RTCDATH and RTCDATL registers Reload on underflow ji 23 bit down counter RTCDATH RTCDATL Wake up from power down A RTCF Interrupt if enabled RTC underflow flag shared with WDT ERTC Fig 18 Real time clock system timer block diagram Power on reset RTC Reset RTC enable RTC clk select oscillators XTAL2 XTAL1 LOW FREQ MED FREQ HIGH FREQ CCLK internal 002aae091 8 1 Real time clock source RTCS1 RTCSO RTCCON 6 5 are used to select the clock source for the RTC if either the Internal RC oscillator or the internal WD oscillator is used as the CPU clock If the internal crystal oscillator or the external clock input on XTAL1 is used as the CPU clock then the RTC will use CCLK as its clock source UM10334 All information provided in this document is subject to legal disclaimers
121. he Timer 0 overflow rate Refer to Section 7 Timers 0 and 1 for details 5 When set the PO 7 pin is toggled whenever Timer 1 overflows The output frequency is therefore one half of the Timer 1 overflow rate Refer to Section 7 Timers 0 and 1 for details 6 EBRR UART Break Detect Reset Enable If logic 1 UART Break Detect will cause a chip reset and force the device into ISP mode 7 CLKLP Clock Low Power Select When set reduces power consumption in the clock circuits Can be used when the clock frequency is 8 MHz or less After reset this bit is cleared to support up to 12 MHz operation Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely as if an external reset or watchdog reset had occurred If a value is written to AUXR1 that contains a 1 at bit position 3 all SFRs will be initialized and execution will resume at program address 0000 Care should be taken when writing to AUXR1 to avoid accidental software resets Dual Data Pointers The dual Data Pointers DPTR adds to the ways in which the processor can specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers The DPTR that is not currently selected is not accessible to software unless the DPS bit is toggled Specific instructions affected by the Data Pointer selection are INC DPTR Increments the Data Pointer by 1 JMP A DPTR Jump indirect
122. hen setto 1 enables the external reset input function on P1 5 When cleared P1 5 may be used as an input pin Remark During a power on sequence The RPE selection is overridden and this pin will always functions as a reset input An external circuit connected to this pin should not hold this pin low during a Power on sequence as this will keep the device in reset After power on this input will function either as an external reset input or as a digital input as defined by the RPE bit Only a power on reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit Note During a power cycle Vpp must fall below Vpor see P89LPC9301 931A1 data sheet Static characteristics before power is reapplied in order to ensure a power on reset Reset can be triggered from the following sources External reset pin during power on or if user configured via UCFG1 Power on detect Brownout detect Watchdog timer e Software reset UART break character detect reset For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a 0 to the corresponding bit More than one flag bit may be set During a power on reset both POF and BOF are set but the other flag bits are cleared A watchdog reset is similar to a power on reset both POF and B
123. i UM10334 P89LPC9301 931A1 User manual Rev 2 5 November 2010 User manual Document information Info Content Keywords P89LPC9301 931A1 Abstract Technical information for the P89LPC9301 931A1 device NXP Semiconductors UM10334 Revision history P89LPC9301 931A1 User manual Rev Date Description v 2 20101105 a Section 2 3 added low speed oscillator information Section 14 1 added low speed oscillator information Section 14 3 added low speed oscillator information Section 14 5 added low speed oscillator information Table 8 added low speed oscillator information v 1 20090409 Initial version Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 2 of 119 NXP Semiconductors UM10334 1 Introduction P89LPC9301 931A1 User manual The P89LPC9301 931A1 are single chip microcontrollers designed for applications demanding high integration low cost solutions over a wide range of performance requirements The P89LPC9301 931A1 are based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices
124. illator The watchdog timer can be clocked from the watchdog oscillator PCLK or low speed crystal oscillator refer to Figure 41 by configuring the WDCLK bit in the Watchdog Control Register WDCON and XTALWD bit in CLKCON register When the watchdog feature is enabled the timer must be fed regularly by software in order to prevent it from resetting the CPU Table 77 Watchdog input clock selection WDCLK WDCON 0 XTALWD CLKCON 4 Watchdog input clock selection 0 0 PCLK 1 0 Watchdog oscillator X 1 Low speed crystal oscillator WDCLK bit is used to switch between watchdog oscillator and PCLK and XTALWD bit is used to switch between watchdog oscillator PCLK and low speed crystal oscillator After changing clock source switching of the clock source will not immediately take effect As shown in Figure 43 the selection is loaded after a watchdog feed sequence In addition due to clock synchronization logic it can take two old clock cycles before the old clock source is deselected and then an additional two new clock cycles before the new clock Source is selected Since the prescaler starts counting immediately after a feed switching clocks can cause some inaccuracy in the prescaler count The inaccuracy could be as much as 2 old clock source counts plus 2 new clock cycles Note When switching clocks it is important that the old clock source is left enabled for two clock cycles after the feed completes Otherwise the watchdog may b
125. ing in an embedded application possible with a minimum of additional expense in components and circuit board area The ISP function uses five pins Vpp Vss TXDO RXDO and RST Only a small connector needs to be available to interface your application to an external circuit in order to use this feature Using the In system programming ISP The ISP feature allows for a wide range of baud rates to be used in your application independent of the oscillator frequency It is also adaptable to a wide range of oscillator frequencies This is accomplished by measuring the bit time of a single bit in a received character This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency The ISP feature requires that an initial character an uppercase U be sent to the P89LPC9301 931A1 to establish the baud rate The ISP firmware provides auto echo of received characters Once baud rate initialization has All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 98 of 119 NXP Semiconductors U M1 0334 UM10334 P89LPC9301 931A1 User manual been performed the ISP firmware will only accept Intel Hex type records Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below NNAAAARRDD DDCC crlf In the Intel Hex record the NN represents the n
126. inputs and outputs depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to Section 4 1 Port configurations for details P1 2 to P1 3 are open drain when used as outputs P1 5 is input only All pins have Schmitt trigger inputs Port 1 also provides various special functions as described below P1 0 TXD 18 P1 0 Port 1 bit 0 TXD Transmitter output for serial port P1 1 RXD 17 P1 1 Port 1 bit 1 RXD Receiver input for serial port P1 2 TO SCL 12 y o P1 2 Port 1 bit 2 open drain when used as output TO Timer counter 0 external count input or overflow output open drain when used as output y o SCL I C bus serial clock input output P1 3 INTO SDA 11 P1 3 Port 1 bit 3 open drain when used as output INTO External interrupt O input SDA I C bus serial data input output P1 4 INT1 10 y o P1 4 Port 1 bit 4 High current source UM10334 INT1 External interrupt 1 input All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 4 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual Table 1 Pin description continued Symbol Pin Type Description TSSOP28 P1 5 RST 6 P1 5 Port 1 bit 5 input only RST External Reset input during power on or if selected vi
127. invalid 2 HVE High Voltage Error Set if error detected in high voltage generation circuits Cycle is aborted Memory contents may be corrupted 3 VE Verify error Set during IAP programming of user code if the contents of the programmed address does not agree with the intended programmed value IAP uses the MOVC instruction to perform this verify Attempts to program user code that is MOVC protected can be programmed but will generate this error after the programming cycle has been completed 4107 unused reads as a logic 0 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 104 of 119 NXP Semiconductors UM10334 Table 85 IAP P89LPC9301 931A1 User manual function calls IAP function Program User Code Page requires key Read Version Id IAP call parameters Input parameters 00h R3 number of bytes to program R4 page address MSB R5 page address LSB R7 pointer to data buffer in RAM F1 Oh use IDATA Return parameter s R7 status Carry set on error clear on no error Input parameters ACC 01h Return parameter s R7 IAP version id Misc Write requires key Input parameters UM10334 ACC 02h R5 data to write R7 register address 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 to 07 reserved 08 Security Byte 0 09 Security Byte 1 OA S
128. ion 1 0 0 START condition will be transmitted when the bus becomes free 40h SLA R has been nol2DAT action 0 0 0 0 Data byte will be received NOT ACK transmitted ACK or bit will be returned has been received no jopAT action 0 0 1 Databyte will be received ACK bit Or will be returned 48h SLA R has been I2DAT action 1 0 0 X Repeated START will be transmitted transmitted NOT or ACK has been nol2DAT action 0 1 0 x STOP condition will be transmitted received STO flag will be reset 2 action 1 1 0 X STOP condition followed by a START UM10334 or All information provided in this document is subject to legal disclaimers condition will be transmitted STO flag will be reset NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 65 of 119 UM10334 P89LPC9301 931A1 User manual NXP Semiconductors Table 56 Master Receiver mode continued Status code Status of the I2C Application software response Next action taken by I2C hardware I2STAT hardware to from I2DAT I2CON STA STO 5 STA 50h Data byte has Read data byte 0 0 0 0 Data byte will be received NOT ACK been received bit will be returned ACK has been read data byte 0 0 0 1 Data byte will be received ACK bit returned will be returned 58h Data byte has Read data byte or 1 0 X Repeated START will be transmitted been received read data byte
129. isclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 62 of 119 NXP Semiconductors U M1 0334 UM10334 P89LPC9301 931A1 User manual 8 NY 1 ADDRESS REGISTER I2ADR COMPARATOR INPUT FILTER P1 3 SDA OUTPUT SHIFT REGISTER STAGE BIT COUNTER ARBITRATION amp CCLK 2 INPUT SYNC LOGIC TIMING m FILTER AND a CONTROL 2 P1 2 SCL LOGIC x SERIAL CLOCK E pda GENERATOR interrupt STAGE timer 1 overflow I2CON CONTROL REGISTERS amp I2SCLH SCL DUTY CYCLE REGISTERS I2SCLL aisn STATUS SAUS OUS DECODER I2STAT STATUS REGISTER 002aaa899 N Fig 30 1 C serial interface block diagram All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 63 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual Table 55 Master Transmitter mode Status code Status of the I2C Application software response Next action taken by I2C I2STAT hardware to from I2DAT to I2CON hardware STA STO SI AA 08H A START Load SLA W x 0 0 x SLA W will be transmitted condition has ACK bit will be received been transmitted 10H A repeat START LoadSLA Wor x 0 0 X As above SLA W will be condition has Load SLA R transmitted I C bus switches been transmitted to Master Receiver Mode 18h SLA
130. it or a Power on reset Watchdog Timer reset flag Cleared by software by writing a logic 0 to the bit or a Power on reset NOTE UCFG1 7 must be 1 break detect reset If a break detect occurs and EBRR AUXR1 6 is set to logic 1 a system reset will occur This bit is set to indicate that the system reset is caused by a break detect Cleared by software by writing a logic 0 to the bit or on a Power on reset Power on Detect Flag When Power on Detect is activated the POF flag is set to indicate an initial power up condition The POF flag will remain set until cleared by software by writing a logic 0 to the bit Note On a Power on reset both BOF and this bit will be set while the other flag bits are cleared BOD Reset Flag When BOD Reset is activated this bit is set It will remain set until cleared by software by writing a logic 0 to the bit Note On a Power on reset both POF and this bit will be set while the other flag bits are cleared BOD Interrupt Flag When BOD Interrupt is activated this bit is set It will remain set until cleared by software by writing a logic O to the bit reserved UM10334 6 1 Reset vector Following reset the P89LPC9301 931A1 will fetch instructions from either address 0000h or the Boot address The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address 00h The Boot address will be used All information provided in this document is s
131. its when selected via the flash configuration It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source and if XTAL1 XTAL2 are not used to generate the clock for the RTC system timer Vss 7 0 Vpp 21 Power supply This is the power supply voltage for normal operation as well as Idle and Power down modes 1 Input output for P1 0 to P1 4 P1 6 P1 7 Input for P1 5 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 6 of 119 NXP Semiconductors UM10334 1 3 Logic symbols P89LPC9301 931A1 User manual Fig 2 KBIO 2 KBl1 CIN2B KBI2 gt CIN2A KBI3 KBI4 gt CINIA 5 gt CMPREF KBI6 gt 1 KBI7 CLKOUT 4 XTAL2 XTAL1 P89LPC9301 931A1 logic symbol Vss Vpp 4 gt 4 gt lt gt gt 4 gt PORT 04 PEN pare lt gt 4 gt gt P89LPC9301 lt gt 931A1 PO PORT 4 Ce 4 0 4 gt gt gt 002 448 TXD 4 RXD 4 T0 4 SCL INTO 4 SDA PORTT NT RST gt MOSI 4 MISO SS 4 SPICLK PORT 2 UM10334 All information provided in this document is subject
132. l 8 bits 8 bits toggle TRn or 0 Tn pin Gate INTn pin ENTn 002aaa920 Fig 14 Timer counter 0 or 1 in mode 1 16 bit counter C T 0 PCLK overflow Toi on TFn interrupt n pin C T 1 control toggle TRn Tn pin Gate THn INTn pin 8 bits ENTn 002aaa921 Fig 15 Timer counter 0 or 1 in Mode 2 8 bit auto reload UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 39 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual C T 0 PCLK overflow TO pi interrupt C T 1 contro 8 05 toggle TRO oT TO pin Gate P1 2 open drain INTO pin ENTO AUXR1 4 overflow Osc 2 on TPO TF1 interrupt contro 8 bits toggle TRI O T1 pin 7 ENT1 AUXR1 5 002aaa922 Fig 16 Timer counter 0 Mode 3 two 8 bit counters overflow POLS o 07 interrupt control and 256 THn on rising transition toggle TRn Gate THn INTn pin 8 bits ENTn 002aaa923 Fig 17 Timer counter 0 or 1 in mode 6 PWM auto reload 7 6 Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port
133. l I O or as inputs to the comparator When used as digital I O these pins are 5 V tolerant However when selected as comparator input signals in CMPn lower voltage limits apply Please refer to the P89LPC9301 931A1 data sheet for specifications 12 4 Comparator interrupt Each comparator has an interrupt flag CMFn contained in its configuration register This flag is set whenever the comparator output changes state The flag may be polled by software or may be used to generate an interrupt The two comparators use one common interrupt vector The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the interrupt system is enabled via the EA bit in the IENO register If both comparators enable interrupts after entering the interrupt service routine the user will need to read the flags to determine which comparator caused the interrupt When a comparator is disabled the comparator s output COx goes high If the comparator output was low and then is disabled the resulting transition of the comparator output from a low to high state will set the comparator flag CMFx This will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user should clear the comparator flag CMFx after disabling the comparator 12 5 Comparators and power reduction modes Either or both comparators may remain enable
134. lows CLR EA disable interrupt MOV WFEED1 0A5h watchdog feed part 1 MOV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt This sequence assumes that the P89LPC9301 931A1 interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence If an interrupt was allowed to be serviced and the service routine contained any SFR writes it would trigger a watchdog reset If it is known that no interrupt could occur during the feed sequence the instructions to disable and re enable interrupts may be removed In watchdog mode WDTE 1 writing the WDCON register must be IMMEDIATELY followed by a feed sequence to load the WDL to the 8 bit down counter and the WDCON to the shadow register If writing to the WDCON register is not immediately followed by the feed sequence a watchdog reset will occur For example setting WDRUN 1 OV ACC WDCON get WDCON SETB ACC 2 set WD RUN 1 OV WDL 0FFh New count to be loaded to 8 bit down counter CLR EA disable interrupt OV WDCON ACC write back to WDCON after the watchdog is enabled a feed ust occur immediately OV WFEED1 0A5h do watchdog feed part 1 OV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt In timer mode WDTE 0 WDCON is loaded to the control register every CCLK cycle no feed sequence is required to load the control register but a feed sequence is required to load from the WDL SFR to t
135. ly disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature 10 12C interface The I C bus uses two wires serial clock SCL and serial data SDA to transfer information between devices connected to the bus and has the following features Bidirectional data transfer between masters and slaves Multimaster bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The I C bus may be used for test and diagnostic purposes A typical IC bus configuration is shown in Figure 24 Depending on the state of the direction bit R W two types of data transfers are possible on the I C bus Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all recei
136. mitted I2DAT has been and ACK bit will be received transmitted ACK load data byte x 0 0 1 Data byte will be transmitted ACK has been received will be received UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 68 of 119 UM10334 P89LPC9301 931A1 User manual NXP Semiconductors Table 58 Slave Transmitter mode continued Status code Status of the IC Application software response Next action taken by I2C I2STAT hardware to from I2DAT ICON hardware STA STO COH Data byte in No I2DAT action 0 0 0 0 Switched to not addressed SLA I2DAT has been or mode no recognition of own SLA or transmitted General call address NACK has been 2DAT action 0 0 0 1 Switched to not addressed SLA received or mode Own slave address will be recognized General call address will be recognized if IZADR 0 1 nol2DAT action 1 0 0 0 Switched to not addressed SLA or mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free nol2DAT action 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IPADR O 1 A START condition will be transmitted when the bus becomes free C8H Last data byte No I2DAT action 0 0 0 0 Switched to not addressed SLA I2DAT has been or mode no reco
137. modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to use In order to set the flag and cause an interrupt the pattern on Port 0 must be held longer than 6 CCLKs Table 67 Keypad Pattern register KBPATN address 93h bit allocation Bit 7 Symbol KBPATN 7 Reset 1 6 5 4 3 2 1 0 KBPATN 6 5 4 KBPATN 3 KBPATN 2 KBPATN 1 KBPATN O 1 1 1 1 1 1 1 Table 68 Keypad Pattern register KBPATN address 93h bit description Bit Symbol 0 7 KBPATN 7 0 R W Access Description Pattern bit O bit 7 Table 69 Keypad Control register KBCON address 94h bit allocation Bit 7 Symbol Reset 6 5 4 3 2 1 0 PATN SEL KBIF x x x x x 0 0 Table 70 Keypad Control register KBCON address 94h bit description Bit Symbol Access Description 0 KBIF R W Keypad Interrupt Flag Set when Port 0 matches user defined conditions specified in KBPATN KBMASK and PATN_SEL Needs to be cleared by software by writing logic 0 1 PATN SEL R W Pattern Matching Polarity selection When set Port 0 has to be equal to the user defined Pattern in KBPATN to generate the interrupt When clear Port 0 has to be not equal to the value of KBPATN register to generate the interrupt 2 7 reserved UM10334 All information provided in this document is subject to legal disclaimers NXP B V
138. n output and drive it low forcing a mode change in the other device see Section 11 4 Mode change on SS to slave UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 72 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual master slave 8 BIT SHIFT REGISTER SPI CLOCK GENERATOR 1 MISO rt 8 BIT SHIFT MOSI REGISTER 1 SPICLK port 1 1 1 slave 1 MISO 8 BIT SHIFT MOSI REGISTER SPICLK gt port ss gt 002aaa903 Fig 34 SPI single master multiple slaves configuration In Figure 34 SSIG SPCTL 7 bits for the slaves are logic 0 and the slaves are selected by the corresponding SS signals The SPI master can use any port pin including P2 4 SS to drive the SS pins Configuring the SPI Table 64 shows configuration for the master slave modes as well as usages and directions for the modes Table 64 SPI master and slave selection SPEN SSIG SSPin MSTR Master or Slave Mode 0 x P2 40 x SPI Disabled 1 0 0 0 Slave 1 0 1 0 Slave 1 0 0 1 gt Slave 0 2 UM10334 SPICLK Remarks MISO MOSI 2 301 pP2 201 P2 50 output input input Hi Z input input output input input All information provided in this document is subject to legal disclaimers SPI disabled P2 2 P2 3 P2 4 P2
139. n also satisfies the requirements for a framing error a break condition will also result in reporting a framing error Once a break condition has been detected the UART will go into an idle state and remain in this idle state until a stop bit has been received The break detect can be used to reset the device and force the device into ISP mode by setting the EBRR bit AUXR1 6 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 46 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual Table 37 Serial Port Control register SCON address 98h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMO FE 5 1 SM2 REN TB8 RB8 TI RI Reset X X X X X X 0 0 Table 38 Serial Port Control register SCON address 98h bit description Bit Symbol Description 0 RI Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or approximately halfway through the stop bit time in Mode 1 For Mode 2 or Mode 3 if SMODO it is set near the middle of the 9th data bit bit 8 If SMODO 1 itis set near the middle of the stop bit see SM2 SCON 5 for exceptions Must be cleared by software 1 TI Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the stop bit see description of INTLO bit in SSTAT register in the other modes Must be cleared by software 2 RB8 The 9th dat
140. n is input P2 6 27 y o P2 6 Port 2 bit 6 P2 7 28 y o P2 7 Port 2 bit 7 P3 0 to P3 1 Port 3 Port 3 is a 2 bit I O port with a user configurable output type During reset Port 3 latches are configured in the input only mode with the internal pull up disabled The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 4 1 Port configurations for details All pins have Schmitt trigger inputs Port 3 also provides various special functions as described below P3 0 XTAL2 9 P3 0 Port 3 bit 0 CLKOUT 2 Output from the oscillator amplifier when a crystal oscillator option is selected via the flash configuration CLKOUT CPU clock divided by 2 when enabled via SFR bit ENCLK TRIM 6 It can be used if the CPU clock is the internal RC oscillator watchdog oscillator or external clock input except when XTAL1 XTAL2 are used to generate clock source for the RTC system timer UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 5 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual Table 1 Pin description continued Symbol Pin Type Description TSSOP28 P3 1 XTAL1 8 P3 1 Port 3 bit 1 XTAL1 Input to the oscillator circuit and internal clock generator circu
141. nable command following any write operation If the Write Enable function is active user code which calls IAP routines will need to set the Write Enable flag prior to each IAP write function call Configuration byte protection In addition to the hardware write enable protection described above the configuration bytes may be separately write protected These configuration bytes include UCFG1 UCFG2 BOOTVEC and BOOTSTAT This protection applies to both ISP and IAP modes and does not apply to ICP or parallel programmer modes If the Configuration Write Protect bit CWP in BOOTSTAT 6 is a logic 1 writes to the configuration bytes are disabled If the Configuration Write Protect bit CWP is a logic 0 writes to the configuration bytes are enabled The CWP bit is set by programming the BOOTSTAT register This bit is cleared by using the Clear Configuration Protection CCP command in IAP or ISP The Clear Configuration Protection command can be disabled in ISP or IAP mode by programming the Disable Clear Configuration Protection bit DCCP in BOOTSTAT 7 to a logic 1 When DCCP is set the CCP command may still be used in ICP or parallel programming modes This bit is cleared by writing the Clear Configuration Protection CCP command in either ICP or parallel programming modes IAP error status It is not possible to use the Flash memory as the source of program instructions while programming or erasing this same Flash memory During an IA
142. nate usage Notes P0 0 POM1 0 POM2 0 KBIO CMP2 PO 1 POM1 1 2 1 KBI1 CIN2B Refer to Section 4 6 Port 0 and P0 2 POM1 2 2 2 2 CIN2A usage as analog inputs POM1 3 POM2 3 KBI3 CIN1B P0 4 POM1 4 POM2 4 KBI4 CIN1A P0 5 POM1 5 2 5 KBI5 CMPREF 6 1 6 2 6 KBI6 1 7 1 7 POM2 7 KBI7 T1 P1 0 P1M1 0 P1M2 0 TXD P1 1 P1M1 1 1 2 1 RXD P1 2 P1M1 2 P1M2 2 TO SCL Input only or open drain P1 3 P1M1 3 P1M2 3 INTO SDA input only or open drain P1 4 P1M1 4 P1M2 4 INT1 P1 5 P1M1 5 P1M2 5 RST P1 6 P1M1 6 P1M2 6 P1 7 P1M1 7 P1M2 7 P2 0 P2M1 0 P2M2 0 P2 1 P2M1 1 2 2 1 2 2 P2M1 2 P2M2 2 MOSI P2 3 P2M1 3 P2M2 3 MISO P2 4 P2M1 4 P2M2 4 SS All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 29 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 14 Port output configuration continued Port Configuration SFR bits PxM1 y PxM2 y Alternate usage Notes P2 5 P2M1 5 P2M2 5 SPICLK P2 6 P2M1 6 P2M2 6 P2 7 P2M1 7 P2M2 7 P3 0 P3M1 0 P3M2 0 CLKOUT XTAL2 P3 1 P3M1 1 P3M2 1 XTAL1 5 Power monitoring functions UM10334 5 1 The P89LPC9301 931A1 incorporates power monitoring functions designed to prevent incorrect operation during initial power on and power loss or reduction during operation This i
143. nd one for Timer 0 TMOD 3 7 2 Mode 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register THn and TLn are used See Figure 14 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 37 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual 7 3 Mode2 Mode 2 configures the Timer register as an 8 bit Counter TLn with automatic reload as shown in Figure 15 Overflow from TLn not only sets TFn but also reloads TLn with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 7 4 Mode 3 When Timer 1 is in Mode it is stopped The effect is the same as setting TR1 0 Timer 0 in Mode 3 establishes TLO and THO as two separate 8 bit counters The logic for Mode 3 on Timer 0 is shown in Figure 16 TLO uses the Timer 0 control bits TOC T TOGATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications that require an extra 8 bit timer With Timer 0 in Mode 3 an P89LPC9301 931A1 device can look like it has three Timer Counters Note When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it into and out of its own Mode 3 It
144. ng a dividing register DIVM to provide CCLK This produces the CCLK frequency using the following formula CCLK frequency fosc 2N Where fosc is the frequency of OSCCLK N is the value of DIVM Since N ranges from 0 to 255 the CCLK frequency can be in the range of fose to 5 510 for N 0 CCLK fosc This feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events other than those that can cause interrupts i e events that allow exiting the Idle mode by executing its normal program at a lower rate This can often result in lower power consumption than in Idle mode This can allow bypassing the oscillator start up time in cases where Power down mode would otherwise be used The value of DIVM may be changed by the program at any time without interrupting code execution Low power select The P89LPC9301 931A1 is designed to run at 18 MHz CCLK maximum However if CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to a logic 1 to lower the power consumption further On any reset CLKLP is logic 0 allowing highest performance This bit can then be set in software if CCLK is running at 8 MHz or slower The P89LPC9301 931A1 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the P89LPC9301 931A1 s 13 interrupt sources All information provided in
145. ocument is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 56 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual 10 3 control register The CPU can read and write this register There are two bits are affected by hardware the SI bit and the STO bit The SI bit is set by hardware and the STO bit is cleared by hardware CRSEL determines the SCL source when the I C bus is in master mode In slave mode this bit is ignored and the bus will automatically synchronize with any clock frequency up to 400 kHz from the master 12C device When CRSEL 1 the 12C interface uses the Timer 1 overflow rate divided by 2 for the 12C clock rate Timer 1 should be programmed by the user in 8 bit auto reload mode Mode 2 Data rate of I C bus Timer overflow rate 2 PCLK 2 256 reload value If fos 12 MHz reload value is 0 to 255 so I C data rate range is 11 72 Kbit sec to 3000 Kbit sec When CRSEL 0 the I C interface uses the internal clock generator based on the value of I2SCLL and I2CSCLH register The duty cycle does not need to be 50 The STA bit is START flag Setting this bit causes the 12C interface to enter master mode and attempt transmitting a START condition or transmitting a repeated START condition when it is already in master mode The STO bit is STOP flag Setting this bit causes the 12C interface to transmit a STOP condition in mas
146. ode 1 Port 0 output 85H mode 2 Port 1 output 91H mode 1 Bit functions and addresses Reset value MSB LSB Hex Binary BF BE BD BC BB BA B9 B8 PWDRT PBO PS PSR PT1 PX1 PTO PXO 001 x000 0000 PWDRTH PBOH PSH PT1H PX1H PTOH PXOH 0011 x000 0000 PSRH FF FE FD FC FB FA F9 F8 PST PSPI PC PKBI PI2C 0011 00x0 0000 PSTH PSPIH PCH PKBIH PI2CH 001 00x0 0000 T 7 E PATN KBIF 0011 00 _SEL 00 0000 0000 FF 1111 1111 87 86 85 84 83 82 81 80 T1 KB7 CMP1 CMPREF CIN1A CIN1B CIN2A CIN2B CMP2 KB6 KB5 KB4 KB3 KB2 KB1 KBO 97 96 95 94 93 92 91 90 RST INT1 INTO SDA TO SCL RXD TXD 5 4 2 1 SPICLK SS MISO MOSI p B7 B6 B5 B4 B3 B2 B1 BO XTAL1 XTAL2 POM1 7 POM1 6 1 5 1 4 POM1 3 1 2 POM1 1 1 0 1111 1111 POM2 7 2 6 2 5 2 4 2 3 POM2 2 POM2 1 2 0 0001 0000 0000 1 1 7 1 1 6 P1M1 4 1 1 3 1 1 2 1 1 1 1 1 0 D3U 11x1 xx11 Jenueui Jesf LWLE6 LOE6Dd 168d v 0LINn SJ0jonpuoolul8S dXN OLOZ J9qui9AON S Z jenuew sn 1oe qns s jueuinoop siy uoreuuojul 6LL 40 L YEEOLNN paniesal 51 0102 A d dXN Table 2 Special function registers continued indicates SFRs that are bit addressable Name P1M2 P2M1
147. on see Section 5 1 Brownout detection UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 107 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 87 Flash User Configuration Byte 1 UCFG1 bit description continued Bit Symbol Description WDSE Watchdog Safety Enable bit Refer to Table 73 Watchdog timer configuration for details BOE1 Brownout Detect Configuration see Section 5 1 Brownout detection 6 RPE Reset pin enable When set 1 enables the reset function of pin P1 5 When cleared P1 5 may be used as an input pin NOTE During a power up sequence the RPE selection is overridden and this pin will always functions as a reset input After power up the pin will function as defined by the RPE bit Only a power up reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit 7 WDTE Watchdog timer reset enable When set 1 enables the watchdog timer reset When cleared 0 disables the watchdog timer reset The timer may still be used to generate an interrupt Refer to Table 73 Watchdog timer configuration for details Table 88 Oscillator type selection FOSC 2 0 Oscillator configuration 111 External clock input on XTAL1 100 Watchdog Oscillator 400 kHz 5 011 Internal RC oscillator
148. one shift cycle data in the master and the slave are interchanged Mode change on SS If SPEN 1 SSIG 0 and MSTR 1 the SPI is enabled in master mode The SS pin can be configured as an input P2M2 4 P2M1 4 00 or quasi bidirectional P2M2 4 P2M1 4 01 In this case another master can drive this pin low to select this device as an SPI All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 74 of 119 NXP Semiconductors U M1 0334 UM10334 P89LPC9301 931A1 User manual slave and start sending data to it To avoid bus contention the SPI becomes a slave As a result of the SPI becoming a slave the MOSI and SPICLK pins are forced to be an input and MISO becomes an output The SPIF flag in SPSTAT is set and if the SPI interrupt is enabled an SPI interrupt will occur User software should always check the MSTR bit If this bit is cleared by a slave select and the user wants to continue to use the SPI as a master the user must set the MSTR bit again otherwise it will stay in slave mode Write collision The SPI is single buffered in the transmit direction and double buffered in the receive direction New data for transmission can not be written to the shift register until the previous transaction is complete The WCOL SPSTAT 6 bit is set to indicate data collision when the data register is written during transmission
149. oot vector If the Boot Vector is selected as the reset address the P89LPC9301 931A1 will start execution at an address comprised of 00h in the lower eight bits and this BOOTVEC as the upper eight bits after a reset 5 7 reserved 16 20 Boot status register Table 96 Boot Status BOOTSTAT bit allocation Bit 7 6 5 4 3 2 1 0 Symbol DCCP CWP AWP BSB Factory default 0 0 0 0 0 0 0 1 value UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 109 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 97 Boot Status BOOTSTAT bit description Bit Symbol 0 BSB 1 4 5 6 CWP 7 Description Boot Status Bit If programmed to logic 1 the P89LPC9301 931A1 will always start execution at an address comprised of 00H in the lower eight bits and BOOTVEC as the upper bits after a reset See Section 6 1 Reset vector reserved Activate Write Protection bit When this bit is cleared the internal Write Enable flag is forced to the set state thus writes to the flash memory are always enabled When this bit is set the Write Enable internal flag can be set or cleared using the Set Write Enable SWE or Clear Write Enable CWE commands Configuration Write Protect bit Protects inadvertent writes to the user programmable configuration bytes UCFG1 BOOTVEC
150. operation in 2 ms 4 ms for erase program Programmable security for the code in the Flash for each sector 100 000 typical erase program cycles for each byte 10 year minimum data retention 16 3 Flash programming and erase The P89LPC9301 931A1 program memory consists 1 kB sectors Each sector can be further divided into 64 byte pages In addition to sector erase and page erase a 64 byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time substantially reducing overall programming time Five methods of programming this device are available Parallel programming with industry standard commercial programmers All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 92 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual In Circuit serial Programming ICP with industry standard commercial programmers IAP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application Internal fixed boot ROM containing low level In Application Programming IAP routines that can be called from the end application in addition to IAP Lite A factory provided default serial loader located in upper end of user program memory providing In System Programming ISP via the serial port Note Fla
151. ot have the glitch suppression circuits Therefore INT1 has glitch suppression while INTO does not Table 11 Summary of interrupts Description Interrupt flag Vector Interrupt enable Interrupt Arbitration Power bit s address bit s priority ranking down wake up External interrupt 0 IEO 0003h IENO O IPOH O IPO O 1 highest Yes Timer 0 interrupt TFO 000Bh ETO IENO 1 1 IPO 1 4 No External interrupt 1 IE1 0013h EX1 IENO 2 IPOH 2 IPO 2 7 Yes Timer 1 interrupt TF1 001Bh ET1 IENO 3 IPOH 3 IPO 3 10 No Serial port Tx and Rx Tl and RI 0023h ES ESR IENO 4 IPOH 4 IPO 4 13 No Serial port Rx RI Brownout detect BOIF 002Bh EBO IENO 5 IPOH 5 IP0 5 2 Yes Watchdog timer Real time WDOVF RTCF 0053h EWDRT IENO 6 IPOH 6 IPO 6 3 Yes clock 12 interrupt SI 0033h EI2C IEN1 0 IP1H 0 IP1 0 5 No KBI interrupt KBIF 003Bh EKBI IEN1 1 IP1H 1 IP1 1 8 Yes Comparators 1 and 2 CMF1 CMF2 0043h EC IEN1 2 IP1H 2 1P1 2 11 Yes interrupts SPI interrupt SPIF 004Bh ESPI IEN1 3 IP1H 3 IP1 3 14 No Serial port Tx TI 006Bh EST IEN1 6 IP1H 6 IP1 6 12 No UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 24 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual IEO EXO EX1 k wake up RTCF J gt KBIF if in power down ERTC EKBI RTCCON 1
152. ovember 2010 28 of 119 NXP Semiconductors U M1 0334 UM10334 4 7 P89LPC9301 931A1 User manual Digital inputs on Port 0 may be disabled through the use of the PTOAD register Bits 1 through 5 in this register correspond to pins PO 1 through 5 of Port 0 respectively Setting the corresponding bit in PTOAD disables that pin s digital input Port bits that have their digital inputs disabled will be read as 0 by any instruction that accesses the port On any reset PTOAD bits 1 through 5 default to logic Os to enable the digital functions Additional port features After power up all pins are in Input Only mode Please note that this is different from the P89LPC76x series of devices After power up all l O pins except P1 5 may be configured by software Pin P1 5 is input only Pins P1 2 and P1 3 are configurable for either input only or open drain Every output on the P89LPC9301 931A1 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please refer to the P89LPC9301 931A1 data sheet for detailed specifications All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times Table 14 Port output configuration Port Configuration SFR bits PxM1 y PxM2 y Alter
153. ower on reset Other resets will not affect WDTOF 5 On power on reset and watchdog reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register 6 The only reset sources that affect these SFRs are power on reset and watchdog reset Jenuew Jesf LWLE6 LOE6Dd 168d YESO LNN SJo0jonpuoolul8S dXN jenuew sn 010 2 eH 1oe qns s jueuinoop siy uoreuuojul 6130 91 v 0LAn pamasa 51 0102 A a dXN Table 3 Extended special function registers Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary BODCFG BOD FFC8H BOICFG1 BOICFGO 21 configuration register CLKCON CLOCK Control FFDEH CLKOK XTALWD CLKDBL FOSC2 FOSC Fosco EI register RTCDATH Real time clock FFBFH 00 0000 0000 data register high RTCDATL Real time clock FFBEH 00 0000 0000 data register low 1 2 3 Extended SFRs are physically located on chip but logically located in external data memory address space XDATA The MOVX A DPTR and MOVX DPTR A instructions are used to access these extended SFRs The BOICFG1 0 will be copied from UCFG1 5 and UCFG1 3 when power on reset CLKCON register reset value comes from UCFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to UCFG1 0
154. p by reset is only enabled if the corresponding reset is enabled and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit IENO 7 is set External interrupts should be programmed to level triggered mode to be used to exit Power down mode In Power down mode the internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled In Power down mode the power supply voltage may be reduced to the RAM keep alive voltage VRAM This retains the RAM contents at the point where Power down mode was entered SFR contents are not guaranteed after Vpp has been lowered to VRAM therefore it is recommended to wake up the processor via Reset in this situation Vpp must be raised to within the operating range before the Power down mode is exited When the processor wakes up from Power down mode it will start the oscillator immediately and begin execution when the oscillator is stable Oscillator stability is determined by counting 1024 CPU clocks after start up when one of the crystal oscillator configurations is used or 200ms to 300ms after start up for the internal RC or 32 OSCCLK cycles after start up for external clock input Some chip functions continue to operate and draw power during Power down mode increasing the total power used during power down These include Brownout Detect e Watchdog Timer if WDCLK WDCON O is logic 1 Comparators Note Com
155. parators can be powered down separately with PCONA 5 set to logic 1 and comparators disabled Real time Clock System Timer and the crystal oscillator circuitry if this block is using it unless RTCPD i e PCONA 7 is logic 1 1 1 Total Power down mode This is the same as Power down mode except that the Brownout Detection circuitry and the voltage comparators are also disabled to conserve additional power Note that a brownout reset or interrupt will not occur Voltage comparator interrupts and Brownout interrupt cannot be used as a wake up source The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled The following are the wake up options supported e Watchdog Timer if WDCLK WDCON O is logic 1 Could generate Interrupt or Reset either one can wake up the device External interrupts INTO INT1 when programmed to level triggered mode Keyboard Interrupt Real time Clock System Timer and the crystal oscillator circuitry if this block is using it unless RTCPD i e PCONA 7 is logic 1 Note Using the internal RC oscillator to clock the RTC during power down may result in relatively high power consumption Lower power consumption can be achieved by using an external low frequency clock when the Real time Clock or watchdog timer is running during power down UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All right
156. r 1 kB or page 64 bytes The Chip Erase operation will erase the entire program memory Five Flash programming methods are available On chip erase and write timing generation contribute to a user friendly programming interface The P89LPC9301 931A1 Flash reliably stores memory contents even after 100 000 erase and program cycles The cell is designed to optimize the erase and programming mechanisms P89LPC9301 931A1 uses Vpp as the supply voltage to perform the Program Erase algorithms When voltage supply is lower than 2 4V the BOD FLASH is tripped and flash erase program is blocked 16 2 Features Parallel programming with industry standard commercial programmers e In Circuit serial Programming ICP with industry standard commercial programmers e AP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application Internal fixed boot ROM containing low level In Application Programming IAP routines that can be called from the end application in addition to IAP Lite Default serial loader providing In System Programming ISP via the serial port located in upper end of user program memory Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space providing flexibility to the user Programming and erase over the full operating voltage range Read Programming Erase using ISP IAP or IAP Lite Any flash program
157. r Timer 1 Cleared for Timer operation input from CCLK Set for Counter operation input from T1 input pin 7 1 Gating control for Timer 1 When set Timer Counter is enabled only while the INT1 pin is high and the TR1 control pin is set When cleared Timer 1 is enabled when the TR1 control bit is set UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 36 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 26 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol T1M2 TOM2 Reset x x 0 x x x 0 Table 27 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit description Bit Symbol Description 0 TOM2 Mode Select for Timer 0 These bits are used with the TOM2 bit in the TAMOD register to determine the Timer 0 mode see Table 27 1 3 reserved 4 1 2 Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD register to determine the Timer 1 mode see Table 27 The following timer modes are selected by timer mode bits TnM 2 0 000 8048 Timer TLn serves as 5 bit prescaler Mode 0 001 16 bit Timer Counter THn and TLn are cascaded there is no prescaler Mode 1 010 8 bit auto reload Timer Counter THn holds a value which is loaded into TLn when it overflows
158. rned own SLA address read data byte x 0 0 1 Data byte will be received ACK bit Data has been will be returned received ACK has been returned UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 66 of 119 NXP Semiconductors UM10334 Table 57 Slave Receiver mode continued P89LPC9301 931A1 User manual Status code Status of the 2 Application software response Next action taken by I2C I2STAT hardware to from I2DAT to I2ZCON hardware STA STO SI AA 88H Previously Read data byte 0 0 0 0 Switched to not addressed SLA addressed with mode no recognition of own SLA or own SLA address general address Data nae been read data byte 0 0 0 1 Switched to not addressed SLA received NACK mode Own SLA will be recognized has been returned general call address will be recognized if IZADR 0 1 read data byte 1 0 0 0 Switched to not addressed SLA or mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free read data byte 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IBADR 0O 1 A START condition will be transmitted when the bus becomes free 90H Previously Read data byte or x 0 0 0 Data byte will be received and NOT addressed with ACK
159. rocessor clock is derived from an external source driving the XTAL1 P3 1 pin The rate may be from 0 Hz up to 18 MHz The XTAL2 P3 0 pin may be used as a standard port pin or a clock output When using an oscillator frequency above 12 Mhz BOE1 bit UCFG1 5 and BOEO bit UCFG1 3 are required to hold the device in reset at power up until Vpp has reached its specified level quartz crystal or ceramic resonator XTAL1 L Fe a Hi XTAL2 002aad364 Note The oscillator must be configured in one of the following modes Low frequency crystal medium frequency crystal or high frequency crystal 1 A series resistor may be required to limit crystal drive levels This is especially important for low frequency crystals see text Fig 5 Using the crystal oscillator UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 20 of 119 NXP Semiconductors UM10334 P89LPC9301 931A1 User manual Fig 6 Block diagram of oscillator control XTAL1 XTAL2 HIGH FREQUENCY MEDIUM FREQUENCY LOW FREQUENCY p i OSCCLK CCLK CPU RC OSCILLATOR RCCLK B4 WITH CLOCK DOUBLER 7 3728 MHz 14 7456 MHz 1 96 WATCHDOG OSCILLATOR 400 kHz 5 PCLK 002aae452 TIMER 0 AND TIMER 1 2 8 Clock source switching on the fly P89LPC9301 931A1 can implement clock source switc
160. s pulled low by an external device the weak pull up turns off and only the very weak pull up remains on In order to pull the pin low under these conditions the external device has to sink enough current to overpower the weak pull up and pull the port pin below its input threshold voltage The third pull up is referred to as the strong pull up This pull up is used to speed up low to high transitions on a quasi bidirectional port pin when the port latch changes from a logic 0 to a logic 1 When this occurs the strong pull up turns on for two CPU clocks quickly pulling the port pin high The quasi bidirectional port configuration is shown in Figure 8 Although the P89LPC9301 931A1 is a 3 V device most of the pins are 5 V tolerant If 5 V is applied to a pin configured in quasi bidirectional mode there will be a current flowing from the pin to Vpp causing extra power consumption Therefore applying 5 V to pins configured in quasi bidirectional mode is discouraged A quasi bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC9301 931A1 data sheet Dynamic characteristics for glitch filter specifications All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 26 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual VDD 2
161. s BAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol DBMOD CIDIS DBISEL FE BR OE STINT Reset X X X X X X 0 0 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 47 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 41 Serial Port Status register SSTAT address BAh bit description Bit Symbol Description O STINT Status Interrupt Enable When set 1 FE BR or OE can cause an interrupt The interrupt used vector address 0023h is shared with RI CIDIS 1 or the combined TI RI CIDIS 0 When cleared 0 FE BR OE cannot cause an interrupt Note FE BR or OE is often accompanied by a RI which will generate an interrupt regardless of the state of STINT Note that BR can cause a break detect reset if EBRR AUXR1 6 is set to logic 1 1 OE Overrun Error flag is set if a new character is received in the receiver buffer while it is still full before the software has read the previous character from the buffer i e when bit 8 of a new byte is received while RI in SCON is still set Cleared by software 2 BR Break Detect flag A break is detected when any 11 consecutive bits are sensed low Cleared by software 3 Framing error flag is set when the receiver fails to see a valid STOP bit at the end of the frame Cleared by software 4 DBISEL Double buffering transmi
162. s accomplished with two hardware functions Power on Detect and Brownout Detect Brownout detection The brownout detect function determines if the power supply voltage drops below a certain level Enhanced BOD has 3 independent functions BOD reset BOD interrupt and BOD FLASH BOD reset will cause a processor reset and it is always on except in total power down mode It could not be disabled in software BOD interrupt will generate an interrupt and could be enabled or disabled in software BOD reset BOD interrupt each has 4 trip voltage levels BOE1 bit UCFG1 5 BOEO bit UCFG1 3 are used as trip point configuration bits of BOD reset BOICFG1 bit and BOICFGO bit in register BODCFG are used as trip point configuration bits of BOD interrupt BOD reset voltage should be lower than BOD interrupt trip point Table 15 gives BOD trip points configuration In total power down mode PMOD1 PMODO 11 the circuitry for the Brownout Detection is disabled for lowest power consumption When PMOD1 PMODO not equal to 11 BOD reset is always and BOD interrupt is enabled by setting PCON 4 bit Please refer Table 16 for BOD reset and BOD interrupt configuration BOF bit RSTSRC 5 BOD reset flag is default as 0 and is set when BOD reset is tripped BOIF bit RSTSRC 6 BOD interrupt flag is default as 0 and is set when BOD interrupt is tripped BOD FLASH is used for flash program erase protection BOD FLASH is always on
163. s reserved User manual Rev 2 5 November 2010 32 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 18 Power Control register PCON address 87h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMOD1 SMODO E BOI GF1 GFO PMOD1 PMODO Reset 0 0 0 0 0 0 0 Table 19 Power Control register PCON address 87h bit description Bit Symbol Description 0 PMODO Power Reduction Mode see Section 5 3 PMOD1 2 GFO General Purpose Flag 0 May be read or written by user software but has no effect on operation 3 GF1 General Purpose Flag 1 May be read or written by user software but has no effect on operation 4 BOI Brownout Detect Interrupt Enable When logic 1 Brownout Detection will generate a interrupt Reserved 6 SMODO Framing Error Location When logic O bit 7 of SCON is accessed as SMO for the UART When logic 1 bit 7 of SCON is accessed as the framing error status FE for the UART 7 SMOD1 Double Baud Rate bit for the serial port UART when Timer 1 is used as the baud rate source When logic 1 the Timer 1 overflow rate is supplied to the UART When logic 0 the Timer 1 overflow rate is divided by two before being supplied to the UART See Section 9 Table 20 Power Control register A PCONA address B5h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RTCPD 5 VCPD I2PD SPPD SPD Reset 0 0 0 0 0 0 0 0 Table 21 Power Control register A PCONA address B5h bit description
164. se prog fail 0 return prog fail 16 5 In circuit programming ICP In Circuit Programming is a method intended to allow commercial programmers to program and erase these devices without removing the microcontroller from the system The In Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC9301 931A1 through a two wire serial interface NXP has made in circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ICP function All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 96 of 119 NXP Semiconductors U M1 0334 16 6 16 7 16 8 P89LPC9301 931A1 User manual uses five pins Vss P0 5 P0 4 and RST Only a small connector needs to be available to interface your application to an external programmer in order to use this feature ISP and IAP capabilities of the P89LPC9301 931A1 An In Application Programming IAP interface is provided to allow the end user s application to erase and reprogram the user code memory In addition erasing and reprogramming of user programmable bytes including UCFG1 UCFG2 the Boot Status Bit and the Boot Vector is supported As shipped from the factory the upper 512 bytes of user code space contains a serial In System Programming
165. sh erase program will be blocked if BOD FLASH is detected Vdd 2 4 V 16 4 Using Flash as data storage IAP Lite The Flash code memory array of this device supports IAP Lite in addition to standard IAP functions Any byte in a non secured sector of the code memory array may be read using the MOVC instruction and thus is suitable for use as non volatile data storage IAP Lite provides an erase program function that makes it easy for one or more bytes within a page to be erased and programmed in a single operation without the need to erase or program any other bytes in the page IAP Lite is performed in the application under the control of the microcontroller s firmware using four SFRs and an internal 64 byte page register to facilitate erasing and programing within unsecured sectors These SFRs are FMCON Flash Control Register When read this is the status register When written this is a command register Note that the status bits are cleared to logic Os when the command is written FMADRL FMADRH Flash memory address low Flash memory address high Used to specify the byte address within the page register or specify the page within user code memory FMDATA Flash Data Register Accepts data to be loaded into the page register The page register consists of 64 bytes and an update flag for each byte When a LOAD command is issued to FMCON the page register contents and all of the update flags will be cleared When FMDATA is writt
166. sponsibility to determine whether the Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from national authorities 18 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP B V NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 114 of 119 NXP Semiconductors UM10334 P89LPC9301
167. sses to any defined SFR locations must be strictly for the functions for the SFRs SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specified must be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 must be written with 0 and will return a 0 when read 1 must be written with 1 and will return a 1 when read All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Rev 2 5 November 2010 9 of 119 UM10334 User manual v 0LAn jenuew sn 010 Z eH 1oe qns s jueuinoop siy uoreuuojul pamasa Syu 0102 A a dXN 6LL 40 OL Table 2 Special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 EO ACC Accumulator EOH 00 0000 0000 AUXR1 Auxiliary A2H CLKLP EBRR ENT1 ENTO SRST 0 DPS 00 0000 00x0 function register Bit address F7 F6 F5 FA F3 F2 F1 FO B B register FOH 00 0000 0000 BRGRO Baud rate BEH 00 0000 0000 generator 0 rate low BRGRiZ2 Baud rate BFH 00 0000 0000 generator 0 rate high BRGCON Bau
168. t E8H enable 1 Bit functions and addresses Reset value MSB LSB Hex Binary BUSY HVA HVE SV Ol 70 0111 0000 FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMOCMD 0 00 0000 0000 I2ADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR 0 GC 00 0000 0000 DF DE DD DC DB DA D9 D8 I2EN STA STO SI AA CRSEL 00 x000 00x0 00 0000 0000 00 0000 0000 STA 4 STA 3 STA 2 STA 1 STA O 0 0 0 F8 1111 1000 AF AE AD AC AB AA A9 A8 EA EWDRT EBO ES ESR ET1 EX1 ETO 00 0000 0000 EF EE ED EC EB EA E9 E8 EST ESPI EC EKBI EI2C 0011 00x0 0000 Jenueui Jesf LWLE6 LOE6Dd 168d v 0LINn SJ0jonpuoolul8S dXN OLOZ J9qui9AON S Z jenuew sn 1oe qns s jueuinoop siy 6LL Jo SL v 0LAn pamasa syu 0102 A a dXN Table 2 Special function registers continued indicates SFRs that are bit addressable Name IP1 IP1H KBCON KBMASK KBPATN Po P1 P2 P3 POM1 POM2 P1M1 Description SFR addr Bit address Interrupt B8H priority O Interrupt B7H priority O high Bit address Interrupt F8H priority 1 Interrupt F7H priority 1 high Keypad control 94H register Keypad 86H interrupt mask register Keypadpattern 93H register Bit address Port 0 80H Bit address Port 1 90H Bit address Port 2 AOH Bit address Port 3 BOH Port 0 output 84H m
169. t interrupt select Used only if double buffering is enabled This bit controls the number of interrupts that can occur when double buffering is enabled When set one transmit interrupt is generated after each character written to SBUF and there is also one more transmit interrupt generated at the beginning INTLO 0 or the end INTLO 1 of the STOP bit of the last character sent i e no more data in buffer This last interrupt can be used to indicate that all transmit operations are over When cleared 0 only one transmit interrupt is generated per character written to SBUF Must be logic 0 when double buffering is disabled Note that except for the first character written when buffer is empty the location of the transmit interrupt is determined by INTLO When the first character is written the transmit interrupt is generated immediately after SBUF is written 5 CIDIS Combined Interrupt Disable When set 1 Rx and Tx interrupts are separate When cleared 0 the UART uses a combined Tx Rx interrupt like a conventional 80C51 UART This bit is reset to logic O to select combined interrupts 6 INTLO Transmit interrupt position When cleared 0 the Tx interrupt is issued at the beginning of the stop bit When set 1 the Tx interrupt is issued at end of the stop bit Must be logic 0 for mode 0 Note that in the case of single buffering if the Tx interrupt occurs at the end of a STOP bit a gap may exist before the next start bit
170. t of sector x This bit and sector x are erased by either a sector erase command ISP IAP commercial programmer or a global erase command commercial programmer 2 EDISx Erase Disable ISP Disables the ability to perform an erase of sector x in ISP or IAP mode When programmed this bit and sector x can only be erased by a global erase command using a commercial programmer This bit and sector x CANNOT be erased in ISP or IAP modes 3 7 reserved Table 93 Effects of Security Bits EDISx SPEDISx MOVCDISx Effects on Programming 0 0 0 None 0 0 1 Security violation flag set for sector CRC calculation for the specific sector Security violation flag set for global CRC calculation if any MOVCDISx bit is set Cycle aborted Memory contents unchanged CRC invalid Program erase commands will not result in a security violation 0 1 Security violation flag set for program commands erase page command Cycle aborted Memory contents unchanged Sector erase and global erase are allowed 1 X X Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Global erase is allowed 16 19 Boot Vector register Table 94 Boot Vector BOOTVEC bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BOOTV4 BOOTV3 BOOTV2 BOOTV1 BOOTVO Factory default 0 0 0 1 1 1 1 1 value Table 95 Boot Vector BOOTVEC bit description Bit Symbol Description 0 4 BOOTV O 4 B
171. tchdog function The user has the ability using the WDCON and UCFG1 registers to control the run stop condition of the WDT the clock source for the WDT the prescaler value and whether the WDT is enabled to reset the device on underflow In addition there is a safety mechanism which forces the WDT to be enabled by values programmed into UCFG1 either through IAP or a commercial programmer The WDTE bit UCFG1 7 if set enables the WDT to reset the device on underflow Following reset the WDT will be running regardless of the state of the WDTE bit The WDRUN bit WDCON 2 can be set to start the WDT and cleared to stop the WDT Following reset this bit will be set and the WDT will be running All writes to WDCON need to be followed by a feed sequence see Section 14 2 Additional bits in WDCON allow the user to select the clock source for the WDT and the prescaler When the timer is not enabled to reset the device on underflow the WDT can be used in timer mode and be enabled to produce an interrupt IENO 6 if desired The Watchdog Safety Enable bit WDSE UCFG1 4 along with WDTE is designed to force certain operating conditions at power up Refer to Table 73 for details Figure 42 shows the watchdog timer in watchdog mode It consists of a programmable 13 bit prescaler and an 8 bit down counter The down counter is clocked decremented by a tap taken from the prescaler The clock source for the prescaler can be the PCLK
172. ter a delay of a half clock period of the internal clock generator When the 12C interface is already in master mode and some data is transmitted or received it transmits a repeated START condition STA may be set at any time it may also be set when the 12C interface is an addressed slave mode STA 0 no START condition or repeated START condition will be generated 6 I2EN I C Interface Enable When set enables the I C interface When clear the 12C function is disabled 7 reserved I C Status register This is a read only register It contains the status code of the I C interface The least three bits are always 0 There are 26 possible status codes When the code is F8H there is no relevant information available and SI bit is not set All other 25 status codes correspond to defined 12 states When any of these states entered the SI bit will be set Refer to Table 55 to Table 58 for details Table 50 1 C Status register I2STAT address D9h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol STA 4 STA 3 STA 2 STA 1 STA 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Table 51 12 Status register I2STAT address D9h bit description Bit Symbol Description 02 Reserved are always set to 0 3 7 STA 0 4 12 Status code I C SCL duty cycle registers I2SCLH and I2SCLL When the internal SCL generator is selected for the I C interface by setting CRSEL 0 in the I2CON register the user must set values for registers 25
173. ter mode or recovering from an error condition in slave mode If the STA and STO are both set then a STOP condition is transmitted to the I2C bus if it is in master mode and transmits a START condition afterwards If it is in slave mode an internal STOP condition will be generated but it is not transmitted to the bus Table 48 12 Control register I2CON address D8h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO SI AA CRSEL Reset x 0 0 0 0 0 x 0 Table 49 12 Control register 2 address D8h bit description Bit Symbol Description 0 CRSEL SCL clock selection When set 1 Timer 1 overflow generates SCL when cleared 0 the internal SCL generator is used base on values of I2SCLH and I2SCLL 1 reserved 2 AA The Assert Acknowledge Flag When set to 1 an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 The own slave address has been received 2 The general call address has been received while the general call bit GC in I2ADR is set 3 A data byte has been received while the I C interface is in the Master Receiver Mode 4 A data byte has been received while the I C interface is in the addressed Slave Receiver Mode When cleared to 0 an not acknowledge high level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 A data byte has been received while t
174. the user can write the byte location within the page register FMADRL 5 0 and the code memory page address FMADRH and FMADRL 7 6 at this time Write the data to be programmed to FMDATA This will increment FMADRL pointing to the next byte in the page register Write the address of the next byte to be programmed to FMADRL if desired Not needed for contiguous bytes since FMADRL is auto incremented All bytes to be programmed must be within the same page Write the data for the next byte to be programmed to FMDATA Repeat writing of FMADRL and or FMDATA until all desired bytes have been loaded into the page register e Write the page address in user code memory to FMADRH and FMADRL 7 6 if not previously included when writing the page register address to FWADRL 5 0 Write the erase program command 68H to FMCON starting the erase program cycle Read FMCON to check status If aborted repeat starting with the LOAD command Table 80 Flash Memory Control register FMCON address E4h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol gt s HVA HVE SV Symbol W 7 FMCMD 6 5 4 FMCMD 2 FMCMD FMCMD 0 Reset 0 0 0 0 0 0 0 0 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 94 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual
175. tion calls continued IAP function IAP call parameters Read Sector CRC Input parameters ACC 05h R7 sector address Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on error clear on no error Read Global CRC Input parameters ACC 06h Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on error clear on no error Read User Code Input parameters 07h R4 address MSB R5 address LSB Return parameter s R7 data 16 17 User configuration bytes A number of user configurable features of the P89LPC9301 931A1 must be defined at power up and therefore cannot be set by the program after start of execution These features are configured through the use of an Flash byte UCFG1 and UCFG2 shown in Table 87 and Table 90 Table 86 Flash User Configuration Byte 1 UCFG1 bit allocation Bit 7 6 5 4 3 2 1 0 Symbol WDTE RPE BOE1 WDSE BOEO FOSC2 FOSC1 FOSCO Unprogrammed 0 1 1 0 0 0 1 1 value Table 87 Flash User Configuration Byte 1 UCFG1 bit description Bit Symbol Description 0 FOSCO CPU oscillator type select See Section 2 Clocks for additional information Combinations other than those 1 FOSC shown in Table 88 are reserved for future use and should not be used 2 FOSC2 3 BOEO Brownout Detect Configurati
176. transition is detected and that interrupt request flag IEn is set IEn is automatically cleared by the CPU when the service routine is called All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 23 of 119 NXP Semiconductors UM10334 3 2 P89LPC9301 931A1 User manual If the external interrupt is level triggered the external source must hold the request active until the requested interrupt is generated If the external interrupt is still asserted when the interrupt service routine is completed another interrupt will be generated It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive it simply tracks the input pin level If an external interrupt has been programmed as level triggered and is enabled when the P89LPC9301 931A1 is put into Power down mode or Idle mode the interrupt occurrence will cause the processor to wake up and resume operation Refer to Section 5 3 Power reduction modes for details Note the external interrupt must be programmed as level triggered to wake up from Power down mode External Interrupt pin glitch suppression Most of the P89LPC9301 931A1 pins have glitch suppression circuits to reject short glitches please refer to the P89LPC9301 931A1 data sheet Dynamic characteristics for glitch filter specifications However pins SDA INTO P1 3 and SCL TO P1 2 do n
177. ubject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 35 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual if a UART break reset occurs or the non volatile Boot Status bit BOOTSTAT 0 1 or the device has been forced into ISP mode Otherwise instructions will be fetched from address 0000H T Timers 0 and 1 The P89LPC9301 931A1 has two general purpose counter timers which are upward compatible with the 80C51 Timer 0 and Timer 1 Both can be configured to operate either as timers or event counters see Table 25 An option to automatically toggle the Tx pin upon timer overflow has been added In the Timer function the timer is incremented every PCLK In the Counter function the register is incremented in response to a 1 to 0 transition on its corresponding external input pin TO or T1 The external input is sampled once during every machine cycle When the pin is high during one cycle and low in the next cycle the count is incremented The new count value appears in the register during the cycle following the one in which the transition was detected Since it takes two machine cycles four CPU clocks to recognize a 1 to 0 transition the maximum count rate is 4 of the CPU clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it
178. uence r p r TO WATCHDOG XTALWD DOWN COUNTER after one prescaler 001 t del PRE2 010 9818y 011 PRE1 DECODE 100 E 101 PREO 110 111 002aae092 Fig 41 Watchdog Prescaler 14 2 Feed sequence The watchdog timer control register and the 8 bit down counter See Figure 42 are not directly loaded by the user The user writes to the WDCON and the WDL SFRs At the end of a feed sequence the values in the WDCON and WDL SFRs are loaded to the control register and the 8 bit down counter Before the feed sequence any new values written to these two SFRs will not take effect To avoid a watchdog reset the watchdog timer needs to be fed via a special sequence of software action called the feed sequence prior to reaching an underflow UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 85 of 119 NXP Semiconductors U M1 0334 UM10334 P89LPC9301 931A1 User manual To feed the watchdog two write instructions must be sequentially executed successfully Between the two write instructions SFR reads are allowed but writes are not allowed The instructions should move A5H to the WFEED 1 register and then 5AH to the WFEED2 register An incorrect feed sequence will cause an immediate watchdog reset The program sequence to feed the watchdog timer is as fol
179. umber of data bytes in the record The P89LPC9301 931A1 will accept up to 64 40H data bytes The AAAA string represents the address of the first byte in the record If there are zero bytes in the record this field is often set to 0000 The RR string indicates the record type A record type of 00 is a data record A record type of 01 indicates the end of file mark In this application additional record types will be added to indicate either commands or data for the ISP facility The maximum number of data bytes in a record is limited to 64 decimal ISP commands are summarized in Table 83 As a record is received by the P89LPC9301 931A1 the information in the record is stored internally and a checksum calculation is performed The operation indicated by the record type is not performed until the entire record has been received Should an error occur in the checksum the P89LPC9301 931A1 will send an X out the serial port indicating a checksum error If the checksum calculation is found to match the checksum in the record then the command will be executed In most cases successful reception of the record will be indicated by transmitting a character out the serial port All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 99 of 119 NXP Semiconductors UM10334 UM10334 P89LPC9301 931A1 User manual Table 83 In s
180. ved bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a repeated START condition Since a repeated START condition is also the beginning of the next serial transfer the I2C bus will not be released The P89LPC9301 931A1 device provides a byte oriented I C interface It has four operation modes Master Transmitter Mode Master Receiver Mode Slave Transmitter Mode and Slave Receiver Mode UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 55 of 119 NXP Semiconductors U M1 0334 UM10334 10 1 10 2 P89LPC9301 931A1 User manual Rp Rp P1 3 SDA P1 2 SCL OTHER DEVICE OTHER DEVICE WITH I2C BUS WITH 2C BUS P89LPC9301 931A1 INTERFACE INTERFACE 002aae455 Fig 24 1 C bus configuration The P89LPC9301 931A1 CPU interfaces with the 1 C bus through six Special Function Registers SFRs I2CON I C Control Register I2DAT 12 Data Register I2STAT 12C Status Register IZADR 12C Slave Address Register I2SCLH SCL Duty Cycle Register High Byte and I2SCLL SCL Duty Cycle Register Low Byte I C data register I2DAT register contains the data to be transmitted or the
181. y 2 2 AO MOV C bit Move direct bit to carry 2 1 A2 MOV bit C Move carry to direct bit 2 2 92 BRANCHING ACALL addr 11 Absolute jump to subroutine 2 2 116F1 LCALL addr 16 Long jump to subroutine 3 2 12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LUMP addr 16 Long jump unconditional 3 2 02 SJMP rel Short jump relative address 2 2 80 JC rel Jump on carry 1 2 2 40 JNC rel Jump on carry 0 2 2 50 JB bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1 and clear 3 2 10 JMP A DPTR Jump indirect relative DPTR 1 2 73 JZ rel Jump on accumulator 0 2 2 60 JNZ rel Jump on accumulator 0 2 2 70 CJNE A dir rel Compare A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne relative 3 2 B4 CJNE Rn d rel Compare register immediate jne relative 3 2 B8 to BF CJNE Ri d rel Compare indirect immediate jne relative 2 B6 to B7 DJNZ Rn rel Decrement register jnz relative 2 2 D8 to DF DJNZ dir rel Decrement direct byte jnz relative 3 2 D5 MISCELLANEOUS NOP No operation 1 1 00 UM10334 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 113 of 119 NXP Semiconductors UM10334 18 Legal information P89LPC9301 931A1 User manual 18 1 Definitions Draft The docum
182. ystem Programming ISP hex record formats Record type 00 01 02 Command data function Program User Code Memory Page nnaaaa00dd ddcc Where nn number of bytes to program aaaa page address dd dd data bytes checksum Example 100000000102030405006070809DC3 Read Version Id 00xxxx01cc Where xxxx required field but value is a don t care cc checksum Example 00000001FF Miscellaneous Write Functions 02xxxx02ssddcc Where xxxx required field but value is a don t care ss subfunction code dd data cc checksum Subfunction codes 002 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 0C Security Byte 4 00 Security Byte 5 OE Security Byte 6 OF Security Byte 7 10 Clear Configuration Protection Example 020000020347B2 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 2 5 November 2010 100 of 119 NXP Semiconductors U M1 0334 P89LPC9301 931A1 User manual Table 83 In system Programming ISP hex record formats continued Record type Command data function 03 Miscellaneous Read Functions 01xxxx03sscc Where xxxx required field but value is a don t care ss subfunction code cc checksum Subfunction codes 002 UCFG1

UM10334 P89LPC9301/931A1 User manual

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