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1. 2S i g amp me gt gt loom IK GSS 0 venore 9 Project Navigator ja x bd VGA Controller img RAM v abd VGA Controller VGA Controller v abd VGA Controller VGA OSD RAM v bi VGA Controller VGA PLL v bo AUDIO DAC v bd PC AV Config v be C_Controller v b b b b b b m 3 LCD Controller v 3 LCD TEST v Reset Delay v 3 SEG7_LUT v 8 SEG7_LUT_8 v 3 VGA_Audio_PLL v Es Hardware Setup USB Blaster USB 0 Enable real time ISP to allow background programming for MAX II devices Analysis amp Synthesis Fitter Assembler Classic Timing Analyzer pl Start m Stop dy Auto Detect X Delete b Add File 15 Change File be Save File Add Device d up Down Y Info Configuring device index 1 4 Info Device 1 contains JTAG ID code 0x020B40DD i Info Configuration succeeded 1 device s configured i Info Successfully performed operation s i Info Ended Programmer operation at Tue May 28 11 58 53 2013 1 Program Blank Security ISP e JEEE es EEE kl EA EP2C35F672 0034E 34F FFFFFFFF Critical Warning 1 Suppressed 9 Flag System 27 Processing 191 Extra Info Info 94 Warning 35 IT ge a X Quartus I C U A y EEOTAIU DSPDesi CH Google Dich G p
2. 8 h23 8 h24 8 h25 8 h26 8h27 sine 16 h19ef sine l6 hlb5c sine 16 h1ccs sine 16 hle2a sine 16 h1f8b sine 16 h20 6 sine 16 h223c sine 16 h238d sine 16 h24d9 sine 16 h261f sine 16 h275f sine 16 h2899 sine 16 h29cc sine 16 h2afa sine 16 h2c20 sine 16 h2d40 sine 16h2e59 sine 16h2f6b sine 16 h3075 sine 16 h3178 sine 16 h3273 sine 16 h3366 sine 16 h3452 35 8 h28 8 h29 8h2a 8 h2b Ss h2c 8 h2d S h2e 8 h2f 8 h30 8h31 8 h32 8 h33 8 h34 8 h35 8 h30 8 h37 8 h38 8 h39 8 h3a 8 h3b 8 h3c 8 h3d 8 h3e sine 16 h3535 sine 16 h3611 sine 16 h36e4 sine 16 h37ae sine 16 h3870 sine 16 h3929 sine 16 h39da sine 16 h3a81 sine 16 h3b1f sine 16 h3bb5 sine 16 h3c41 sine 16 h3cc4 sine 16 h3d3d sine 16 h3dad sine 16 h3el4 sine 16 h3e70 sine 16 h3ec4 sine 16 h3f0d sine 16 h3f4d sine 16 h3f83 sine 16 h3fb0 sine 16 h3fd2 sine 16 h3feb 36 8 h3f sine 16 h3ffa 8 h40 sine 16 h3fff 8 h41 8 h42 8 h43 8 h44 8 h45 8 h46 8 h47 8 h48 8 h49 8hda 8 h4b Ss h4c 8 h4d 8hde 8 h4f 8 h50 8h51 8 h52 8 h53 8 h54 8 h55 sine 16 h3ffa sine 16h3feb sine 16 h3fd2 s
3. 1 1 1 0000000000000 ARNS detente 20 20 128 2 2 2 2 2 2 2 2 2 2 2 2 2 212121212121212 1 121 1 2 2 2 12 2 1 2 1 1 12 1 2 4 5 Verto DE Desien RSRS 00101001011 21 6 e 00 24 CHAPTER 00 25 EXPERIMENT AND RESULTS asus a a 25 4 EXDETIMEN 0 IMs 25 27 101010 010 0 2 3 GOT A TITTEN 29 REFERENCES 00010101010100 30 AA A 31 LIST OF FIGURE Figure 1 Block diagram of AM modulation scheme using direct digital synthesis 1 7 8 12 Figure gt Block d1asram OT Dasis DDS 2 aa a ae nk 10 Fruto TREDE Board A 1 sea 14 Figure 6 Flowchart of AM modulation scheme using direct digital synthesis 1 7 19 Pieure 7 The Verlos HDL toplevel inician 22 Eisure 8 Quartus LI compilation rep rt aaa nA WA ATA 23 Figure 9 Loading sof file into DE2 board une 24 Eisure 10 Effecto DAC Resolution 6 una a a 25 Figure 12 DDS sine wave carrier with the frequency of 500 KHZ 27 Figure 13 DDS sine wave carrier with the frequency of 1 MHZ 28 rene AM modulio ntes sacana re 29 CHAPTER I INTRODUCTION 1 Background AM transmitter is a transmitter or radio transmitter using amplitude modulation Amplitude modulation AM is a technique used in electronic communication most commonly for transmitting information via aradio carrier wave AM works by varying the strength of the
4. S hes 8 he9 8 hea 8 heb 8 hec 8 hed S hee S hef 8 hf0 8 hfl 8 hf2 8 hf3 8 hf4 8 hf5 8 hf6 sine 16 hd2c0 sine 16 hd3e0 sine 16 hd506 sine 16 hd634 sine 16 hd767 sine 16 hd8al sine 16 hd9el sine 16 hdb27 sine 16 hdc73 sine 16 hddc4 sine 16 hdfla sine 16 he075 sine 16held6 sine 16 he33b sine 16 he4a4 sine 16 he611 sine 16 he783 sine 16 hesfs sine 16 hea71l sine l6 hebed sine 16 hed6d sine 16 heeef sine 16 hf074 44 endcase end endmodule 8 hf7 8 hf8 8 hf9 S hfa 8 hfb hfc 8 hfd hfe 8 hff sine 16 hflfb sine 16 hf384 sine 16 hf510 sine 16 hf69d sine 16 hf82b sine 16 hf9bb sine 16 hfb4b sine 16 hfcdd sine 16 hfe6e 45
5. transmitted signal in relation to the information being sent For example changes in signal strength may be used to specify the sounds to be reproduced by a loudspeaker or the light intensity of television pixels 2 Project Aims The goal of this project was to build an AM transmitter on an FPGA with a carrier frequency at IMHz The direct digital synthesis DDS unit for the carrier should run at a clock of 50 MHz or lower The DDS for the audio can run at the same rate The transmitter output should be generated as 16 bit 2 s complement numbers and then converted to 10 bit offset binary and sent to the VGA DAC channel The hardware will be use for AM transmitter on an FPGA is DE2 board PHASE ACCUMULATOR N AM lt gt N OUTPUT REGISTER ES MULTIPLIER VREF Figure 1 Block diagram of AM modulation scheme using direct digital synthesis 1 7 3 Project objectives The project objective of this thesis is e Using direct digital synthesis to generate a 1 0 MHz sine wave as a carrier e Multiply the carrier with an audio signal consisting of either a 400 Hz from a direct digital synthesis unit or audio from the audio codec e Use Verilog language to design the soft radio transmitter e Implement the radio transmitter on an FPGA with the VGA output of the ADV7123 330 MHz triple 10 bit high speed video DAC e Verify the functionality of the AM modulated radio transmitter CHAPTER II BACKGROUND 1 Direct
6. Digital Synthesis Direct digital synthesis DDS 1s a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced to a fixed frequency precision clock source The tuning word enables a DDS implementation to provide good output frequency tuning resolution DDS 1s an alternative to traditional analog synthesizer solutions For many applications the DDS solution holds some distinct advantages over the equivalent analog frequency synthesizer employing PLL circuitry DDS advangtages e digitally controlled micro hertz frequency tuning and sub degree phase tuning capability e extremely fast hopping speed in tuning output frequency or phase phase continuous frequency hops with no overshoot undershoot or analog related loop settling time anomalies e the digital architecture of DDS eliminates the need for the manual tuning and tweaking related to component aging and temperature drift in analog synthesizer solutions and e the digital control interface of the DDS architecture facilitates an environment where systems can be remotely controlled and optimized with high resolution under processor control Theory of operation As shown in the DDS block diagram in Fig 2 the main components of direct digital synthesis are a phase accumulator a means of phase to amplitude conversion often a sine look up table and a DAC ACCUMULATOR ANGLE TO AMPLITUDE DAC ANALOG
7. FREQUENCY SINE WAVE TUNING WORD SYSTEM CLOCK PHASE TRUNCATION N P Figure 2 Block diagram of basis DDS 2 2 The basic DDS requires two inputs A system clock signal with Fs denoting its frequency and a digital numeric value denoted by FTW comprising a frequency tuning word The system clock serves as a timing reference for the DDS while the FTW controls the output frequency tuning word The accumulator and angle to amplitude converter together constitute a numerically controlled oscillator or NCO The output of the NCO is a time series of digital words that occur at a rate equal to the system clock frequency The time series of digital words represent a sinusoidal waveform sampled at a rate of Fs and proccessing a frequency dictated by the FTW The DAC converts the time series of digital words produced by the NCO to an analog waveform yielding a so called real world signal at the DAC output N P and D constitute the width of the interconnecting buses in bits That is the accumulatior buses are N bits wide as is the FTW the input to the angle to amplitude converter 15 P bits wide and its output is D bits wide as is the input to the DAC Phase accumulator The heart of the system is the phase accumulator whose contents is updated once each clock cycle Each time the phase accumulator is updated the digital number FTW stored in the delta phase register is added to the number in the phase accumulator register Assume that t
8. May 28 12 22 13 2013 u ee ot KELK Quartus ll Version 7 2 Build 151 09 26 2007 SJ Web Edition Py e t KIR abd 3 80 Assembler a oe en j abd PC AV Configv amp 0 Timing Analyzer 1 abd PC Controlerv Family Cyclone Il if i EP2C35F672C6 i bd LCD Controller v pba LCD_TEST v Final ped Reset Delay v No j Pd SEG7_LUT v 310133216 lt 1 j bd SEG7_LUT_8 v 291 33 216 lt 1 p VGA_Audio_PLL v 224 33 216 lt 1 224 425 475 89 0 8 192 483 840 2 ents 2 70 3 Full Compilation 1 4 25 Analysis amp Synthesis Fitter Assembler Classic Timing Analyzer 4 J r Critical Warning Timing requirements for slow timing model timing analysis were not met See Report window for details Info Quartus II Classic Timing Analyzer was successful 0 errors 5 warnings Info Quartus II Full Compilation was successful 0 errors 347 warnings J J S System 30 A Processing 191 Extra Info Info A PA A A AM AAA Warning 96 Critical Warning 1 Error Suppressed 9 Flag a an gt o Ca e iS xxx Pa Reportthesis Thu Wi Schroeder s Rever 3 ee C Us WAS Guidelines4FinalP a Br ie call m 12 22 PM 28 05 2013 Figure 8 Quartus 11 compilation report After building successful hardware using Quartus II I continue to load the sof file which includes all hardware design information on DE2 board 23 Is Window Help
9. SW Toggle Switch 17 0 7 SEG Display output 6 0 HEXO Seven Segment Digit 0 output 6 0 HEX1 Seven Segment Digit 1 output 6 0 HEX2 Seven Segment Digit 2 output 6 0 HEX3 Seven Segment Digit 3 output 6 0 HEX4 Seven Segment Digit 4 output 6 0 HEXS Seven Segment Digit 5 output 6 0 HEX6 Seven Segment Digit 6 output 6 0 HEX7 Seven Segment Digit 7 LED output 8 0 LEDG LED Green 8 0 output 17 0 LEDR LED Red 17 0 UART output UART_TXD UART Transmitter Status ANE input UART RXD UART Receiver Mode nn output IRDA_TXD IRDA Transmitter input IRDA_RXD IRDA Receiver SDRAM Interface o inout 15 0 DRAM DQ SDRAM Data bus 16 Bits 2 output 11 0 DRAM ADDR SDRAM Address bus 12 Bits output DRAM LDQM SDRAM Low byte Data Mask output DRAM UDQM SDRAM High byte Data Mask E mastossa DAM TE AT 11 CDNDAM ti E mn Ia 4 m 4 Message Processing A Extra Info ing Critical Warning Suppressed PP me e eos Z xx IF q F Le TO AM a gt PHUONG G uments Ol ON Introduction G Wi uongcolen do AG n s thesis repor gt ee a O I 01 06 2013 7 Figure 7 The Verilog HDL top level file Using Verilog HDL file of Quartus II software a system had to be built on the chip that would interconnect all the Verilog modules as physical components on the FPGA board to create an AM transmitte
10. designed an AM transmitter on FPGA successfully Beside studying and understanding the technology of Direct Digital Synthesis to generate sine wave I used a DDS module as a carrier to modulate AM I achieved the goal of the project 29 REFERENCES 1 MT 085 TUTORIAL Fundamentals of Direct Digital Synthesis DDS Analog Devices Inc 2009 Available FTP http www analog com staticimported files tutorials MT 085 pdf 2 The Accumulator Digi Key Corp MN 56701 USA 1995 2013 Available FTP http dkc1 digikey com ca en tod ADI Accumulator_NoAudio Accumulator_NoAudio html 3 Communication system 4 Edition Simon Haykin John Wiley amp Sons Inc 4 DE2 Development and Education Board User Manual Altera Corp Version 1 4 2006 Available FTP ftp ftp altera com up pub Webdocs DE2_UserManual pdf 5 ADV7123 CMOS 330 MHz Triple 10 Bit High Speed Video DAC Norwood U S A Rev D 2010 Available FTP http www analog com staticimported files data sheets ADV7123 pdf 6 A Technical Tutorial on Digital Signal Synthesis Analog Devices Inc 1999 Available FTP http www eee li pdf essay dds pdf 7 Angle to Amplitude converter Digi Key Corp MN 56701 USA 1995 2013 Available FTP http dkc digikey com us en tod A DI Angle to Amplitude Converter Angle to Amplitude Converter html 8 Digital to Analog Converter Digi Key Corp MN 56701 USA 1995 2013
11. value Thus the horizontal distance between the vertical lines represents the sample period Note the deviation between the DAC output signal and the perfect sine wave The vertical distance between the two traces at the sampling instants is the error introduced by the DAC as a result of its finite resolution This error is known as quantization error and gives rise to an effect known as quantization distortion To understand the nature of the quantization distortion note the sharp edges in the DAC output signal These sharp edges imply the presence of high frequency components superimposed on the fundamental It 15 these high frequency components that constitute quantization distortion In the frequency domain quantization distortion errors are aliased within the Nyquist band and appear as discrete spurs in the DAC output spectrum 4 Bit Dac Spectrum E 811 DAC Spectrum Mim H Normalized Magnitude dB Normalized Magnitude dB 4 il Relative Frequency Relative Frequency Figure 11 4 Bit vs 8 Bit DAC output spectra 6 6 As the DAC resolution increases the quantization distortion decreases 1 e the spurious content of the DAC output spectrum decreases This makes sense because an increase in resolution results in a decrease in quantization error This in turn results in less error in the reconstructed sine wave Less error implies less distortion 1 e less spurious content This is graphically depicted in
12. Available FTP http dkc 1 digikey com hk en tod A DI Digital to Analog NoAudio Digital to Analog NoAudio html 30 APPENDICES The main codec of AM transmitters audio stuft M A TMAH output to audio DAC wire signed 15 0 audio_outL audio_outR input from audio ADC wire signed 15 0 audio_inL audio inR make a direct digital systnesis accumulator and output a 10 bit sine wave to the VGA plug set carrier frequency to 1 MHz DDS_incr 32 h51EB84C set modulation to 400 Hz 85E7 DDS hardware increment 85 8993 desired freq SOMHz sample rate reg 31 0 DDS accum carrierl wire signed 15 0 carrierl out reg 31 0 DDS accum modi wire signed 15 0 mod1_out modulation wire signed 15 0 xmit_out wire 9 0 xmit_out_10bit always O posedge CLOCK 50 begin transmitter DDS accum carrierl lt DDS accum carrierl 32 h51EB84C 31 DDS accum modi DDS accum modl 32 h85E7 400 hz End hook up the ROM table for carriers sync rom carrierl table CLOCK 50 DDS_accum_carrier1 31 24 carrierl_ out hook up the ROM table for modulation sync rom modi Table CLOCK 50 DDS accum mod1 31 24 mod1 out choose modulation assign modulation SW 0 audio_inL modl_out balanced modulation signed_mult xmitl xmit out carrierl out modulation 16 h4000 convert 16 bit 2 comp to 10 bit offset binary for DAC assign xmit_out_10bit xmit_out 15 6 10 d512 use the VGA DA
13. C for an AM modulated RF signal assign VGA_R xmit_out_1Obit assign VGA SYNC 1 assign VGA BLANK 1 assign VGA_CLK CLOCK 50 endmodule 32 MI signed mult of 0 16 format 2 comp LLL module signed mult out a b output 15 0 out input signed 15 0 a input signed 15 0 b wire signed 15 0 out wire signed 31 0 mult out assign mult_out a b assign out mult_out 31 mult_out 29 15 assign out mult_out 31 16 endmodule MA MN Sin Wave ROM Table 1 MAMA produces a 2 s comp 16 bit approximation of a sine wave given an input phase address module sync_rom clock address sine input clock 33 input 7 0 address output 15 0 sine reg signed 15 0 sine always posedge clock begin case address 8 h01 8 h02 8 h03 8 h04 8 h05 8 h06 8 h07 8 hO8 8 h09 h0a 8 hOb hOc 8 hUd 8 h0e 8 hOf 8h10 8 h00 sine 16h0000 sine 16 h0192 sine 16 h0323 sine 16 h04bS sine 16 h0645 sine 16 h07d5 sine 16 h0963 sine 16 hOaf0 sine 16 hOc7c sine 16 h0e05 sine 16 hOf8c sine 1661111 sine 16 h1293 sine 16h1413 sine 16h158f sine 16 h1708 sine 16 h187d 34 8h11 8h12 8h13 8h14 8h15 8h16 8h17 8h18 8h19 8hla 8h1b hlc Shld 8hle Shit 8 h20 8 h21 8 h22
14. Figure 11 Note that the spurs associated with the 8 bit DAC are generally lower than those of the 4 bit DAC 26 2 Results Figure 12 DDS sine wave carrier with the frequency of 500 KHz On the oscilloscope I set the value of TIME DIV 1 microsecond we can see on this picture the value of frequency carrier base the formula T 27 ee CAPS 0 Figure 13 DDS sine wave carrier with the frequency of 1 MHz The same with the DDS sine wave carrier above I also set the TIME DIV 1 microsecond and VOLTS DIV 0 2 V After the test DDS carrier through VGA channel I will show you the result of AM transmitter on FPGA also via VGA and modulate DDS carrier with 400 Hz DDS unit 28 Rek 3 on i a El a i ei aa o P us E LERLE a i a aha ola jo aloja lala la alani E UEM m me me m pi e ia Figure 14 AM modulation test As the figure 14 the first figure shows the AM modulation with set TIME DIV 2 mS and VOLTS DIV 0 1 V The second figure shows the AM modulation with set TIME DIV 1 microsecond and VOLTS DIV 0 1 V To implement on the DE2 board Altera DE2 board is connected to power and to the PC as specified in the evaluation board description the toggle switch on the left edge of the board marked Run Prog is in the Run position and it is left there at all times The FPGA will program in the Run position 3 Conclusion Based on the results above I
15. VIETNAM NATIONAL UNIVERSITY HOCHIMINH CITY THE INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRICAL ENGINEERING FPGA Based Soft Radio Transmitter By Nguyen Thi Thuy Phuong Advisor Udo Klein PhD A thesis submitted to the School of Electrical Engineering in partial fulfillment of the requirements for the degree of Bachelor of Electrical Engineering FPGA Based Soft Radio Transmitter APPROVED BY Udo Klein Ph D ACKNOWLEDGMENTS It is with deep gratitude and appreciation that I acknowledge the professional guidance of Udo Klein This project would not have been possible without his instructive comments and evaluation at every stage of the project I am also grateful for his support and patience with all the problems and numerous revisions which rose up during all the past three months I am also thankful for his extraordinary experiences throughout the work that can help me to be better in the future career ABSTRACT FPGA technology contains both memory and logic elements along with an intellectual property IP processor core to implement a computer and custom hardware for system on chip SOC applications This approach has been termed system on programmable chip SOPC This project carriers out a sophisticated design of a digital system using techniques along with a variety of digital and analog interface technologies to build a device I have implemented a soft radio transmitter using AM modulation techniques The Video G
16. ated In this project I will use 14 bit MSBs which does not significantly affect the frequency resolution The output of the phase accumulator is linear and cannot directly be used to generate a sine wave or any other waveform except a ramp Therefore a phase to amplitude conversion a lookup table is used to convert a truncated version of the phase accumulator s instantaneous output value into sine wave amplitude information that is presented to the D A converter Most DDS architectures exploit the symmetrical nature of a sine wave and utilize mapping logic to synthesize a complete sine wave cycle from 1 4 cycle of data from the phase accumulator The phase to amplitude lookup table generates all the necessary data by reading forward then back through the lookup table Ary Amplitude Sine Conv Algorithm DIA Converter Tuning word specifies output frequency as a fraction of Ref Clock fraquency au Sin XX In Digital Domain Figure 5 Signal flow through the DDS architecture 6 6 17 The phase truncated in this project is 14 bit MSBs A Verilog ROM module is used to generate a 16 bit sine wave The table is designed to generate a sine wave with only 14 bits of amplitude so that two sine waves can be added without further scaling to prevent overflow The table is designed by Matlab program with 14 bit of amplitude and 8 bit address SADO Sim SCS TO 1 01 65 2 s compl
17. ement do do X AREAS E tenpo O for 1 xX LL gt 76 y i 2 16 y i end Torinci veye HE Bine Lo nl end ENA y SAT py 12 For output through the VGA DAC I will need to convert the 16 bit 2 s comp to 10 bit offset binary 18 2 AM Modulation in DDS Phase Accumulator Sine lookup table Audio codec 1 NY output DAC 400 Hz DDS unit 0 Figure 6 Flowchart of AM modulation scheme using direct digital synthesis 1 7 Figure 6 shows the AM modulation in DDS system In this project we can multiply the carrier by an audio signal consisting of either a 400 Hz DDS unit or audio from the audio codec module e Using a 400 Hz DDS unit which is the same as the DDS carrier and only change the frequency of it Following the equations we calculate the phase increment of 400 Hz 2 FTW 34360 It will use the same lookup table of the carrier After that we multiply carrier with 400 Hz DDS unit Both of them use 8 bits e Using audio codec to modulate The DE2 board provides high quality 24 bit audio via the Wolfson WM8731 audio CODEC This chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz We provide the music from mobile phone laptop via the line in port on DE2 board using The hardware audio interface is a Wolfson WMS8731 is controlled by an DC interface which is connected to pins on the Cyclone IT FPGA After that we do such a
18. example a network switch a microprocessor or a memory or a simple flip flop This just means that by using a HDL one can describe any digital hardware at any level In this project Verilog HDL is used to describe an AM transmitter on FPGA The top level Verilog file is called DE2 Default v which defines ports that correspond to all of the user accessible pins on the Cyclone IT FPGA The table below describes each Verilog module DE2_Default The top level module for our project Included in this module are instantiations of the modules listed below Reset_Delay Needed to run the phase lock loop VGA_Audio_PLL Used for generating the clocks used to run all of the modules specifically AUD_CTRL_CLK DC AV Config Needed to use the Audio Codec AUDIO_DAC_ADC Module to run the inputs and outputs to the Audio Codec sync_rom Look up table for the synthesized sinusoids The module takes accumulators which are increased at varying frequencies as inputs and it outputs the corresponding sine values 21 abe File Edit View Project Assignments Processing Tools Window Help x D 2 li 8 sima eme IK r r vn AAN Project Navigator x L a Clock ETT Es dd Cyclone I EP2C35F672C6 input CLOCK 27 27 MHz Gebs DE2 Default Aa input CLOCK 50 50 MHz E en input EXT_CLOCK External Clock Push Button input 3 0 KEY Pushbutton 3 0 DPDT Switch input 17 0
19. hc57f sine 16 hc4el sine 16 hc44b 41 8 hb2 8 hb3 8 hb4 8 hb5 8 hb6 8 hb7 8 hb8 8 hb9 8 hba 8 hbb 8 hbc 8 hbd 8 hbe 8 hbf 8 hcO Ss hcl hc2 8 hc3 hc4 8 hcS 8 hc6 8hc7 8 hc8 sine 16 hc3bf sine 16 hc33c sine 16 hc2c3 sine 16 hc253 sine 16 hclec sine 16 hc190 sine 16 hcl3c sine 16 hc0f3 sine 16 hc0b3 sine 16 hcO7d sine 16 hc050 sine 16 hc02e sine 16 hc015 sine 16 hc006 sine 16 hc001 sine 16 hc006 sine 16 hc015 sine 16 hc02e sine 16 hc050 sine 16 hcO7d sine 16 hc0b3 sine 16 hc0f3 sine 16 hcl3c 42 8 hc9 8 hca 8 hcb 8 hcc 8 hcd 8 hce S hcf 8 hdo 8 hdl 8 hd2 8 hd3 8 hdd 8 hd5 8 hd6 8 hd7 8 hds 8 hd9 8 hda 8 hdb 8 hdc 8 hdd 8 hde 8 hdf sine 16 hc190 sine 16 hclec sine 16 hc253 sine 16 hc2c3 sine 16 hc33c sine 16 hc3bf sine 16 hc44b sine 16 hc4el sine 16 hc57f sine 16 hc626 sine 16 hc6d7 sine 16 hc790 sine 16 hc852 sine 16 hc9Ic sine 16 hc9ef sine l6 hcacb sine l6 hcbae sine 16 hcc9a sine 16 hcd amp d sine 16 hces8 sine 16 hcf amp b sine 16 hd095 sine 16 hdla 7 43 8 hel S hel he2 8 he3 he4 S heS 8 he6 S he
20. he number in the delta phase register is 00 01 and that the initial contents of the phase accumulator is 00 00 The phase accumulator is updated by 00 01 on each clock cycl e If the accumulator is 32 bits wide 2 clock cycles over 4 billi on are required before the phase accumulator returns to 00 00 and the cycle repeats 10 Angle to Amplitude converter Angle to amplitude lookup table is used to convert a truncated version of the phase accumulator sinstantaneous output value into the sinewave amplitude information that 1s presented to the D A converter DAC Digital to Analog converter The DAC converts the time series of digital words produced by the phase to amplitude conversion to an analog waveform yielding a so called real world signal at the DAC output 2 AM Modulation Amplitude modulation AM is a technique used in electronic communication most commonly for transmitting information via a radio carrier wave The amplitude of a sinusoidal signal with fixed frequency and phase is varied in proportion to a given signal The output signal of a AM modulator is given by Am V t A 1 m cos i cos 0 of ACOS 0 pt cos o t cost O Where is the modulated signal frequency 18 the RF carrier frequency gt gt mas defined as the modulation index 0 lt m lt l 11 Carrier UUM UU nn Modulating Wave A Message Wave Envelope 50 Modulation Car
21. ine 16 h0963 sine 16 h07d5 sine 16 h0645 sine 16 h04bS sine 16 h0323 sine 16h0192 sine 16h0000 sine 16 hfe6e sine 16 hfcdd sine 16 hfb4b 39 8 h84 8 h85 8 h86 8 h87 8 h88 8 h89 8 h8a 8 h8b 8h8c 8 h8d 8h8e 8 h8f 8 h90 8 h91 8 h92 8 h93 8 h94 8 h95 8 h96 8 h97 8 h98 8 h99 8 h9a sine 16 hf9bb sine 16 hf82b sine 16 hf69d sine 16hf510 sine 16 hf384 sine 16 hflfb sine 16 hf074 sine 16 heeef sine 16 hed6d sine l6 hebed sine 16 hea71l sine 16 he818 sine 16 he783 sine 16 he61 1 sine 16 he4a4 sine 16 he33b sine l6 held6 sine 16 he075 sine 16 hdfla sine 16 hddc4 sine 16 hdc73 sine 16 hdb27 sine 16 hd9el 40 8 h9b 8 h9c 8 h9d 8 h9e 8 h9f 8 hab S hal ha2 8 ha3 8 had has ha6 S ha S has 8 hab S haa 8 hab S hac 8 had S hae S haf 8 hbO 8 hbl sine 16 hd8al sine 16 hd767 sine 16 hd634 sine 16 hd506 sine 16 hd3e0 sine 16 hd2c0 sine 16 hdla 7 sine 16 hd095 sine 16 hcf8b sine 16 hces8 sine 16 hcd8d sine 16 hcc9a sine 16 hcbae sine 16 hcacb sine 16 hc9ef sine l6 hc9lc sine 16 hc852 sine 16 hc790 sine 16 hc6d7 sine 16 hc626 sine 16
22. ine 16 h3fb0 sine 16 h3183 sine 16 h3f4d sine 16 h3f0d sine 16 h3ec4 sine 16 h3e70 sine 16 h3el4 sine 16 h3dad sine 16 h3d3d sine 16 h3cc4 sine 16 h3c41 sine 16 h3bbS sine 16 h3b1f sine 16 h3a81 sine 16 h39da sine 16h3929 sine 16 h3870 sine 16 h37ae 37 8 h56 8 h57 8 h58 8 h59 8 h5a 8 h5b Ss h5c 8 h5d 8 h5e 8 h5f 8 h60 8 h61 8 h62 8 h63 8 h64 8 h65 8 h66 8 h67 8 h68 8 h69 8 h6a 8 h b 8 h6c sine 16 h36e4 sine 16 h3611 sine 16h3535 sine 16 h3452 sine 16 h3366 sine 16 h3273 sine 16 h3178 sine 16 h3075 sine 16h2f6b sine 16 h2e59 sine 16h2d40 sine 16 h2c20 sine 16 h2afa sine 16 h29cc sine 16 h2899 sine 16 h275f sine 16 h261f sine 16 h24d9 sine 16 h238d sine 16 h223c sine 16 h20 6 sine 16 h1f8b sine 16 hle2a 38 8 h6d 8 h e 8 h6f 8 h70 8h71 8h72 8h73 8h74 8h75 8 h76 8h77 8 h78 8 h79 8 h7a 8 h7b Ss h7c 8 h7d S h7e 8 h7f 8 h80 8 h81 8 h82 8 h83 sine 16 hlcc 5 sine l6 hlb5c sine 16 hl9ef sine 16 h187d sine 16 h1708 sine 16h158f sine 16h1413 sine 16 h1293 sine 1661111 sine 16h0f8c sine 16 h0e05 sine 16 hOc7c sine 16 hOaf0 s
23. r The purpose of this part is e Using Verilog HDL file to design AM transmitter in Quartus II software e Implement the design on DE2 board All we need to do is instantiate the Verilog HDL file the Verilog module generated by the Verilog HDL file is in the file DE2_Default v in the directory of the project connect inputs and outputs of the parallel I O ports as well as the clock and reset inputs to the appropriate pins on the Cyclone series device Note that the name of the Verilog module is the same as the system name specified when first using the top level design entity for this project 22 After successful compilation of AM transmitter on Quartus II the files that were required to program the DE2 board were obtained It was then programmed using the Quartus II programmer All the Verilog modules were successfully programmed into the board E File Edit View mr Assignments Window Help alx AAA CI DE2_Default lt TE gt rol D e Compilation Report Flow Summary E Legal Notice BE Flow Summary me 8E Flow Settings ER Flow Non Default Global Se BEE Flow Elapsed Time dem i E VGA Controller VGA Param h be B VGA_Controller img_DATA hex j bd VGA Controller lmg RAM v bd VGA_Controller VGA_Controller v o y rg VGA_Controller VGA_OSD_RAM v B Flow tog Flow Status Successful Tue
24. raphics Array VGA Digital to Analog converter DAC can process sampling rates above 50 Msamples sec It is therefore possible to directly generate an amplitude modulation radio signal in the standard AM band of 530 kHz to 1700 kHz I will have used direct digital synthesis DDS to generate a 1 0 MHz sine wave for a carrier then multiplied the carrier by an audio signal consisting of either a 400 Hz direct digital synthesis unit or audio from the audio codec With this project I have implemented the AM modulator with the directly synthesized carrier and the audio baseband signal on an FPGA As the high frequency output the VGA output with the ADV7123 330 MHz triple 10 bit high speed video DAC is used TABLE OF CONTENTS CHAPTER Lippi diane aes RB 7 NER 0000 7 le Backoround eldesi 1 12 1 1 1 1 Ve VA Ve E y k va VA Ve e 90a 0 ku k U d A VA Ve ek n Q ea Yek 7 0020 0 ORAR u R wa HENA VE asalet del 7 De Project OD ICCUVES lt u wa i Gay 0 0000 8 CHAPTER 00000000 9 BACKGROUND n n Ko aki adoraria eia a asli Sadna al il akay da ipa ini b A 9 1 Direct Dicital Synthesis 1 1 2 2 lt 2 lt 2 2 2 ei kei 9 2 ANEMOUUAHONS 00173 11 CHAPTER ji li ii id 15 DESIG N zana 00010101012 di BEWE te SE ga allen 15 1 Design of Direct Digital Synthesis 22000000000000000000000000000ssnnnnnnnnnnnnnnnssssnssssnnsssnsnnse 15 2 AM Modulation m DDS 0000 19 3
25. rier Wave Amplitute Time 100 Modulation Amplitute 2 ya BER ess ao pures L a Li kara r 5 La FA E Time 150 Modulation Amplitute 7 cee geese eee ee e ym i m pm Pa 0 5 m mp e m m ore mam nee kl m m ur gt m Jon n hun n a 0 5 2 EEL Eb b44 Ai n An EE E A Mise LE me mi abl El a Time Figure 3 AM modulation 3 12 The AM modulation index is the measure of the amplitude variation surrounding an unmodulated carrier As with other modulation indices in AM this quantity also called modulation depth indicates how much the modulation varies around its original level For AM it relates to variations 1n carrier amplitude and is defined as nes peak value of m t M 1 A a where bf and are the message amplitude and carrier amplitude respectively So if 0 5 carrier amplitude varies by 50 above and below its unmodulated level for h 1 0 it varies by 100 To avoid distortion modulation depth must not exceed 100 percent Transmitter systems will usually incorporate a limiter circuit to ensure this However AM demodulators can be designed to detect the inversion or 180 degree phase reversal that occurs when mod
26. s in figure shown multiply the carrier by audio codec module On the other hand There are a set of modules which are needed for all of the test programs below which interface to the audio codec They are DC AV Config v PC Controller v Reset Delay v AUDIO DAC ADC v All of it is written in Verilog HDL 3 User Interface In order to adjust modulation of AM modulate with 400 Hz DDS unit or audio codec the SWO switches on the DE2 board are used to control the AM modulation output When SWO is not pressed modulate with 400 Hz DDS unit when SWO is pressed modulate with audio codec 4 VGA Output Because the wave generator outputs pure voltage values through the VGA interface without the need for any sort of framing or timing the code required to configure the VGA module is very simple We merely connect the output of the DDS lookup table mux to the VGA_R pin drive VGA_BLANK and VGA_SYNC to 1 and assign the main system clock to VGA_CLK The FPGA will program in the run position This design will make on the Altera Cyclone II 20 DE2 board The major advantage of DE2 board was it supports the hardware components needed such as the basic FPGA support circuitry power supply programming etc as well as switches and buttons for user input along with VGA output port 5 Verilog HDL Design Verilog is a Hardware Description Language HDL A hardware description language is a language used to describe a digital system for
27. sing various components Also software 1s provided for a number of demonstrations that illustrate the advanced capabilities of the DE2 board In order to use the DE2 board the user has to be familiar with the Quartus II software The necessary knowledge can be acquired by reading the tutorials Getting Started with Altera s DE2 Board and Quartus II Introduction which exists in th ree versions based on the design entry method used namely Verilog VHDL or schematic entry This project will use Cyclone IT 2C35 FPGA Clock inputs VGA output to do the project 14 CHAPTER III DESIGN 1 Design of Direct Digital Synthesis DDS is a commonly used method for periodic waveform synthesis using a given reference frequency a lookup table phase to amplitude conversion an N bit adder and associated accumulator and an FTW bit phase increment value The top O bits of the accumulator are used as an index to the lookup table which stores pre computed samples of a single period of the desired output waveform sinusoid Adjusting the phase increment value the amount added to the accumulator value on each cycle of the reference clock allows us to adjust the fundamental frequency of the output waveform The output frequency can be determined by the phase increment using the following expression 2 FTW fout 2N fs Additionally the phase increment for a desired frequency 15 2 N 2 FTW fout fs fout desired frequenc
28. ulation exceeds 100 percent they automatically correct for this defect citation needed Variations of a modulated signal with percentages of modulation are shown in Fig 3 In each image the maximum amplitude is higher than in the previous image note that the scale changes from one image to the next 13 3 Hardware The Altera DE2 Board USB U g USB Ethemet Video VGAVideo 10 100M Por Pot 5 232 Port Me in in Qu rc LITE tf t 27 MHz Oscillator U E 24 bit Audio Codec L l m 3 2 o h u i gt 25 2 Keyboard Mouse Port VIGA 10 21 DAC vE am Ethemet 10 1004 Controller em 1 Expansion Meader 2 JP2 Power ON OFF Switch i USB Host Siave Controller TY Decoder NTSC PAL Altera USB Blaster Controller Chipset Expansi n Header 1 JP1 Altera EPCS16 Configuration Device ss Altera Cyclone E FPGA RUNPROG Switch for JTAGIAS Modes 1612 LCD Module SD Card Shot 7 Segment Displays 8 Green LEDs Transe 18 Rod LEDs ENTE SMA External Clock 18 Toggle Swichas 4 Detounced Pushtution Swiss 50 MH2 Oscilator BNIB SDRAM 512 KB SRAM 4 MB Flash Memory Figure 4 The DE2 board 4 4 The DE2 board has many features that allow the user to implement a wide range of designed circuits from simple circuits to multimedia projects In addition to these hardware features the DE2 board has software support for standard I O interfaces and a control panel facility for acces
29. y fs system clock N phase accumulator 15 FTW Frequency tuning word where exact equality cannot be assured due to the fact that M is an integer value and therefore cannot exactly replicate all frequency values R My design uses a 32 bit accumulator a 31 bit increment and an 8 bit accumulator output The accumulator output indexes into 256 entry lookup tables for sine wave lookup The 10 bit output connected to the VGA_R output of the DE2 board In DDS carrier phase accumulator 15 very important My design uses 32 bit accumulator 50 MHz system clock and 1 MHz desired frequency of carrier Based on the equation above we calculate the phase increment for DDS N 32 fs 50 x 10 fout 10 32 1 6 50 x 106 0 85899345 92 FTW Because the value of M must be an integer so that the value of M use for phase accumulator of DDS will be FTW 85899346 The actual DDS output frequency is 85899346 6 33 50 x 10 1 000000000931 l fou gt 16 Each time the phase accumulator is updated the digital number FTW is added to the number in the phase accumulator register The phase accumulator 1s updated by 85899346 on each clock cycle The frequency resolution of the system is equal to E For N 32 the resolution is greater than one part in four billion In a practical DDS system all the bits out of the phase accumulator are not passed on to the lookup table but are trunc
30. z is M ee wi ar caran emmek ae een pe o we Figure 9 Loading sof file into DE2 board The output would be available through the VGA port using the VGA_Red channel for the output signal 6 Test Due to the limited required functionality of the wave generator The key points of the design were the DDS unit AM modulation and the VGA output Testing was carried out using the oscilloscope to verify correctness of frequency and waveform shape 24 CHAPTER V EXPERIMENT AND RESULTS 1 Experiment The signal I want to detect is the signal resulting from only on the VGA_Red channel Based on the socket looking at the edge of the board we connect the oscilloscope to get the signal output On the other hand The resolution of a DAC is specified by the number of its input bits For example the resolution of a DAC with 10 input bits is referred to as having 10 bit resolution The impact of DAC resolution is most easily understood by visualizing the reconstruction of a sine wave s He ed AAA UAM DOAR NN BINERIN UPA 89 A A CR A TTL Ms U allel R A Map ras 12 TL 0 63 Time Figure 10 Effect of DAC Resolution 6 25 Consider Fig 10 in which a 4 bit DAC quantized black trace 15 used to reconstruct a perfect sine wave smooth red trace The vertical lines are time markers and identify the instants in timeat which the DAC output is updated to a new

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