complete Application Note
Contents
1. 25 COSTA IO c 25 J sns 26 Typical Mistakes and Misunderstandings a 28 Torms and ADB06vRUIIONULLUUULILIIII la EEE Ap nE a i eiaa inienn 29 More L yi G C T a A E E E 29 ppen ix uu k Ra O 30 Fest Propran TOR Check Up onactieuiuetiiimotsuMdosotanei Sure auum biu mere EE dust ledim Muda fuc BI M CUR 30 Op A EROR 34 a COPEL electronic Application Note Testbus Basics Introduction The Boundary Scan JTAG Test utilizes a serial transfer protocol It s error free transmission requires some conditions that if not fulfilled make the test useless or even impossible This document helps to recognize the failures and to understand the reactions of the system properly A guideline for troubleshooting in different situations is contained Basic knowledge on Standard IEEE 1149 1 and knowledge on basic operation of the system CASCON are assumed to be known All in the document used screenshots are based on CASCON version 4 4 2 Conditions for the perfect BScan JTAG Testbus 1 All BScan ICs understand the signals TMS and TCK such that all of them are in t2. 1 THEN WRITE F LD taililag 0 ELSE WRITE END END WRITELN WRITELN T 5 WRITELN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 WRITELN be ok as des WRITE FOR v 2 160 TO 239 DO 60 MHz TCK v 2 IRSHIFT IF failflag 1 THEN WRITE F LD failflag 0 ELSE WRITE END END WRITELN WRITELN WRITELN ol 62 63 0424 65 66 67 868 69 70 Il 72 13 74 75 76 77 78 TS GOT WRITELN aaen area EE WRITE FOR wv 2 280 TO 319 DO 80 MHz TCK uox IRSHIFT IF failflag 1 THEN WRITE F LD fa lflag 0 ELSE WRITE END END END a 13 Feruaperrexp rpcxpvurppXPPPTPEPTUPEETPPUSPETSES T als SI sa kuya ana a Paya Pasa A me ee kaea ad ae eo ee s ee od we ol wee eel eee log PROC pLoopZ0 MHz BEGIN WRITELN 1 2 3 4 3 6 7 8 9 10 11 12 15 18 15 16 17 18 19 20 WRITELN elere emal sa rr ama ew ppp leew ppp E LOOP vLoopCnt DO CALL pTAP3 END WRITELN Leselueeksheeelesebeseleseqeesleeelbeseleeebeseeweelses9 ee2 s erlwexexdexexbexzjexsc d AY WRITELN 1 2 3 4 5 6 7 9 9 10 11 12 13 14 15 16 17 18 19 20 WRITELN END PROC pActionSelect BEGIN READSELECTION Action select vSel 1 x 80 MHz 100 x 20 Moz 1000 x 20 Moz Exit GOPEL electronic Application Note SWITCH vSel CASE 0 CALL p_TAP_TEST CASE 1 vLoopCnt 100 CALL pLoop20MHz CASE 2 vL
3. a COPEL electronic Application Note Name AE0032GV PDF Version 1 4 Author Gerhard Vieweg Create 01 03 2013 eMail g vieweq qoepel com Subject BScan JTAG Testbus Failures how to tackle This Application Note explains Testbus failure reports gives suggestions and comments for design and troubleshooting The sections FAQ as well as Typical Mistakes and Misunderstandings should be understood as further help Some special cases from the practice are discussed too a COPEL electronic Application Note Content Tes p s pasipu qu uuu ua ua aasawa E seuvoiddedtuasaccasusedecaseecdecautcbincastwcatvardasauuertscaumeiccasiats 3 li lil TO RTL 3 Conditions for the perfect BScan JTAG Testbus 3 Testbus Design Needs and MISfaK esS uu aaa aasasasasakasakawasqussaqwqunkaasasaskwsawahyanauwaqksskaqupansauwaqaqikawaq 4 TO SCDUS FATES 5 Detection of Testbus Failures 5 ill 5 Fhe Testbus Palure Message uuu uuu ra e eea EE EE e E Aa n Eia APAE 5 Reasons for Testb s Faures u uuu u uz aukasaqkawaqaqakaqpaswaqauqqapaskawssisbanaskasasnik
4. E g D rra ol 1 merre 1 saw GOPEL electronic Application Note Step 3 Interconnection CAS zb LDI Ue Extest Debugger az LDI Ul Extest 43 IrShifl Drive 1 J 44 Options IDE Gbt ck At Low Test alle Leitungen werden aut High geset Insert DrShifts 46 2 Testschritte ay Test is called after the line 65 46 Switch level of pins pel DL U2 IOz23 O IO22 O0 IOoZ21 O0 IOZzO0 O IO422 0 50 DL Ul PB02 07 0 PBD2 04 0 PEOZ 03 0 PBD1 17 0 PBD1_ D End DH U2 1035 0 IO33 0 1031 0 IO30 O0 IOz8 O IO25 0 IO 52 DH i IO6 0 IO5 O0 IO3 O IOZ O IO3370 1043 0 53 DH Ul PB03 17 0 PROS 16 0 PROS 15 0 PROS 14 0 PROS 1 54 DH PROS 07 0 PB03 06 0 PROS 057 0 PROS 04 0 PBD3_ SS DH i F BOZ 15 0 PBUZ 14 0 PB OZ 13 0 PBD2 12 0 PBD2_ 56 DH PRO2 00 0 PBU1 16 0 PBD1 15 0 PBD1 14 0 PBD1_ E DH i PBO1 07 0 PBU1 06 0 PEO1 5 0 PBD1 00 0 PBOO 58 DH i PROO 10 0 PB00 08 0 PROO 07 0 P OO 06 0 PEOD DrShift ATG Drive 2 Measure 1 a 60 Enable pins B dl DH U2 1035 C IO33 C IOS1 C IO30 C IOZ28 C IOZz5 C IQ 62 DH i IO6 C IO5 C IOS3 C IO2 C IO4J4 C IO43 C IO42 3 DH U1 PBD3 17 C PBD3 16 C PROS 15 C PBD3 14 C PROD 1 64 DH i PROS OF C PROS 5 C PROS O5 C PBD03 O4 C PROS 65 DH PRO2 15 C PB Z 14 C PBUZ 13 C P BOZ 1z C PB Z E TH r Dean mayer DAN mae Dan n4 Deon Anse CENT Step 4 CASCON GALAXY 4 4 1a CASLAN Debugger i
5. It would not be a good idea to chose a Good TCK for testing Instead the reason must be found and fixed 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 z Z sis S Tos IS s yl Ql yl su s uwa EEE A Ps Sc Tys s s TSS Ts sol FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I EPEN czxluulaxel sual A EEE won EE EES EA EES A ETS EET Wa aa FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 2242 43 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 sew utelwet OEE EIES lane Perel coulwan Lawes eee lao lane OI weal SI PERES DONES KERSE shal FFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PERE TERR EER EE soulwes EAE EATEN EA EE sen PA PA EA asa As EAE EIEE A OE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 l l 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF a COPEL electronic Application Note The ADYCS settings can ENS i IF ar E made by hand Ye version Module 2 23 Starting from CASCON 4 4 1 x version File 2 25 the ADYCS parameter can be checked by the system under Pre power m Power
6. Static Testbus Failures There is no relation between the TCK frequency and the pattern of defect The defect is constant Typical cases EMT PPP Diagnose TDO Test Data Out of the Wrong BSDL File Register Diagnosis in Debugger TCK Step UUT provides different pattern lengths Instruction register or Mode is possible when the however they are different from Data registers differ difference is small There is a 0 or 1 chance to recognize the dislocated Testbyte provided the actual chain length is shorter When it is longer a few or all bits of the Testbyte are Swallowed so the diagnosis becomes unsure A dummy BSDL with large Boundary Scan register can help to find the location of the Testbyte Diagnosis by BCcan Probe see section Further Possibilities by the Boundary Scan Probe TDO Test Data Out of the Design mistake of the Check if TDO of the BScan IC is UUT drives constant 0 or 1 TAP cable active only in the TAP states Design mistake on TAP SHIFT IR SHIFT DR of the board Compliance Pattern not satisfied System Reset or TRST active TDO is shorted to GND or driver with fix level IRSHIFT is failure free Wrong BSDL file See 1 related to the data register DRSHIFT is faulty after loading Length of the BScan Register selected by the previously loaded the instruction SAMPLE or differs instruction EXTEST GOPEL electronic Dynamic Testbus Fail
7. Step 1 lt 0101 gt Testbus failure at DRShift Diagnosis by IBShift LOW starting at Uz Failure report check BScan Controller TDT and UZ TOA TMS IDO 118 4 DRSHIFTs and 1 DRSHIFTS ATG have been executed Schritt 2 Interconnection CAS 63 DH PB03 O7 C PBOS O6 C PBO3 D5 C PBO3 D4 C PBO3_ Debugger 65 DH PBOZ 15 C PBO2 14 C PBOZ 13 C PBD2 12 C PBO2_ 56 DH PBD2 03 C PBOZ O2 C PBO2 D1 C PBO2 DO C PEOL 67 DH PBO1 10 C PBO1 D9 C PBO1 D8 C PBD1 D7 C PBD1 No breakpoints are set Options 68 DH PEDO 14 C PROO 13 C PROO 12 C PBROO 11 C PBOQ for Pin Toggler are de activated 55 DH PBDO D3 C PBOD Oz C PBOD DO1 C PBDO DO C 7O IGH Us Boundary Fal IGH U1 Boundary Start the test in the normal way 72 DrShitft j s Em Test cancels at Drive 3 EM gt x 1 75 EH i 2 The yellow arrow indicates 6 EH i e lt 0101 gt Testbusfehler bei DRShift Diagnose durch IRShift 5 which Drishifevas causing tha mm EH il LOW ab U2 BScan Cantraller TDI und U2 TCK TMS TOO pr fen 3 75 EH failure c EH Arrow to left the line has been a EH executed 81 EH u 82 EH PBO1 OO I PBOO 17 I PBOO 16 I PBOO 15 I PBOO_ 83 EH PBOD O6 I PBOO D5 I PBOO 04 1 PBOO 03 1 PBOO_ o4 Disable pins 85 DL U2 I013 C IO18 C IO15 C IO14 C IO13 C a6 DL Ui PROS i7 c PROS 16 0 PROS 15 C PROS 14 2 PROS 13 87 DL i PBD3 O5 C PBD1 DD C B8B DrShift ATG Drive 3 Measure 2
8. 6 genene IO TAC Modes Pe eS eager Measure TCK TDO Delay at Generic IO 1 Z PIP 1 2 3 300 V SEX T AP transceivers Generic IO 2 Z PIP 3 4 3 300 v Generic IO 3 Z TDIs TAP 1 Delay 3 degene IO PF2C oglan Pre power fest I Generic IQ 1 2 disabled Generic IO 2 Z Pre pomer test 2 Generic IO 3 z disabled Delay 3 TAPs Measure TCE TDO delay TCK TDO delay delta 1 ns Second panel TCK TDD delay Max TCK Frequency 30 MHz Max Frequency of devices 10 000000 MHz Iv TAP 1 TCK TOO delays TAP 1 24 ns TEE TOO delay delta 2 ns Activate delay values Maximize TEK frequency Found max Frequency MHz Use TEE Frequency Far the project OK Cancel Tests on TDO Output Debugger TCK Step Mode Get the Step Mode in Debugger via these two Step Mode possible ways v TCK E Statement Options Step Mode 7 IR Shift callReturn Click on the right lower edge in Debug window The highest priority has T CK the options R and DR are not treated then a x not tested TLE stmt IR DR Jmp CIR DR SHIFT E a COPEL electronic Application Note Signal names and headlines correspond to the signals of the controller Alternating colors for different BScan ICs and the Testbyte makes the pattern easier to understand Reset Irshift Runldle The Testbyte is shifted out 5 of the controller first It s 2 SelectDRH 1 x vector is S2
9. BSDL file Faulty BSDL File Create 3 individual library models Detect IR and BScan register lengths Create 2 Dummy models later those Ics will be held in mode Global Extended Generator Settings EGS DEVICES DEV ss INSTRUCTION BYPASS Design failure on chip Disable the Testbyte in SAMPLE mode afterwards activate it again Global Extended Generator Settings EGS CASLAN PRESHIFI U SEI TESI BYTE OFE PREEXTEST SEI IESI BYTE O52155 Design failure on chip Generate Options Time between Update and Capture Fast 2 5 TCK Application error Compliance Pattern has not been fulfilled TMS320C6713 Reset_Z did not get a LOW because of the prevention of Flash access by that GOPEL electronic type name protected by NDA The operation hangs up in TAP state PAUSE DR continue of operation with Test Logic Reset only Difficult to explain Testbus failures when checking by scope on TDO sometimes proper and sometimes midrange levels can be seen Xilinx Spartan 3E causes Testbus failure everytime the Instruktion SAMPLE is loaded Application Note Compliance pattern The IC vendor guarantees the function only when the compliance patterns are met Change the board design make a separation between TMS320C6713 Reset_Z and Flash Reset To avoid the TAP state PAUS DR there are two restrictions the UUT must have only one TAP in TestProgram Generator I
10. Caslan File Name TCK Check Up CAS Date 15 04 2005 Author vieweg Version Date Change 0 15 04 2005 Creation LII 13 12 2006 Update compressed output format ese Te 21 12 2006 Update TAP selection 1 4 01 03 2013 Update TAP selection according to CON file PROGRAM TCK Check UP VAR v TCK INT A a INI v 3 LOs vSel S Loy failflag to 1 vLoopCnt s SIBI LABEL NewSelect PROC pTAP3 procedure keyword PROC and name ProcName BEGIN place procedure code between begin and eng WRITE FOR v_TCK 1 TO 79 DO 20 MHz pues FOR v TCK 1 TO 39 DO J10 MHZ TCK v TCK IRSHIFT IF failflag 1 THEN WRITE F LD failflag 0j ELSE WRITE END TAPRESET END WRITELN END PROC p TAP TEST BEGIN WRITELN WRITELN 1 2 3 4 g 6 7 8 9 l0 dl 12 13 14 15 16 17 Le 19 20 WRITELN Sa ae hae ae papaq ae ae ee ae ae haga dasa dasa leeetle sete eed eeelleecqdeecdasged oe WRITE DF FOR v_2 1 TO 79 DO 20 MHz TCK vV 2 IRSHIFT IF failflag 1 THEN WRITE F LD failflag 0 ELSE WRITE Application Note END END WRITELN WRITELN WRITELN Zl 22 23 24 25 20 27 20 29 20 gl 24 22 24 25 26 327 329 39 40 WRITELN ara pepa papa cb as aces b aces T aya alee axa axa sex eel x1 eee evel eee wx eee l xS WRITE FOR v_2 BU TO 159 DO 40 MHz TCK V 2 IRSHIFT IF failflag
11. Compliance pins TRST or testbus pins If one of the question get a no the Testbus works at least partially and based on the functional part further diagnosis steps ca be added Failure Message Testbus Failure how is it defined A Testbus failure happens if the Testbyte has not been detected properly One bit difference is enough for that The exitcode is always 65534 The testbyte is a CASCON built in feature to check for transparency of the Testbus It is provided in extra to the actual on the board existing chain length during SHIFT DR and SHIFT IR Because the Testbyte is issued in addition at first leaves the controller it has to arrive at the end of the shift operation Shift on the serial output of the UUT The Testbyte is a 100 guarantee for the synchronization of the BScan ICs on the board and the controller However it is no 100 guarantee for the total failure free Testbus operation because also single bits apart from the Testbytes can be falsified anyway Fortunately this happens more seldom Prove by the testbytes is therefore a good option to prove the chain length The calculated chain length is given in the BScan ICs within the chain and their actual situation The CASLAN instructions for activating the Testbus are IRSHIFT and DRSHIFT They result in a walkthrough graph ranges IR Scan and DR Scan Note The chain length is constant at IRSHIFT but depends on the previously chosen data register at DRSHIFT A
12. File wiew Help Debugger i F 11 c ts ca pn te a d e d re nol Pin Properties MetList Navigator Commands Copy line 65 to Command Window and insert device name Run DH U1 PBOZ 15 0 PBD2 14 C PBD2 13 C PBO Z 127C PROZ 11 C PE DRSHIFT DRSHIFT Continuo Insert 2x DRSHIFT Step Stop GOPEL electronic Application Note Step 5 Interconnection CAS pes Irshiftt i Drive 1 44 Debugger eee ere Tet BCASCON GALAXY 4 4 1a CASLAN Debugger File view Help 46 lz Teatschritte T Source Window x uu e ce HE US amp He QR Ul EC evel ot PTESPPUI swuHHk il i lil iii i iY i UWV ill iS Set breakpoint to line 65 49 DL U2 1023 0 Iozz f Pin Properties BI Net List Navigator 50 DL Ui PBO2 07 0 FBC 51 DH U2 1035 0 I1033 d H mn cn a ts te t7 te 52 DH To6 o IQ5 DH U1 PBDO2 15 C PBD2 14 C PBD2 1 53 DH j U1 PBD3 17 0 PBC DRSHIFT DRSHIFT 54 DH PROS 07 0 F 55 DH i PROZ 15 0 F 56 DH PROZ 007 0 F 57 DH i PROL 07 0 F 58 DH FEDO 10 0 F 59 Prshiftt ATG Drive 60 Enable pins 4 61 DH U2 1O35 C IO33 C 62 DH To 6 c ras c 63 DH U1l1 PBD3 17 C PBC 64 DH PROS D 7 C F 65 DH PROZ 15 C PBO2 14 C PBD2 13 C PBD2 12 C PBD2 66 DH PROZ O3 C PBD2 D2 C PBD2 O1 C PBD2 DD C PBD1_ 67 DH PROL 10 C PBO1 o9 Cc PBD1 D8 C PBD1 D7 C PBD1 1 68 DH PBOD 14 C PBOD 13 C PBOD i2 C PBOO 11 C
13. PBOO Step 6 CASCON GALAXY 4 4 14 CASLAN Debugger E x File View Help amp FG ES Fal 5 E Pin Properties J el pm en cn ee on eon Debugger Run DH U1 PBO2 15 C PBO2 14 C PBOZ 13 C PBU2 12 C PBO2 11 C DRSHIFT DRSHIFT lt ae Debugger Netlist Navigator Debugger Reset Command Window Set the cursor on first line Run Check for FAIL lt lt 0101 gt Testbusfehler bei DRShiFt Diagnose durch IR Shift LOW ab Ue BScan Cantraller TDI und LIz TCkK TMS TOO pr fen GOPEL electronic Application Note C45CON GALAXY 4 4 14 CASLAN Debugger I zl Step 7 File View Help jek Die Halt the line Fe Pin Properties Netlist Navigator Kg commands x if e pL r2 pn ra m cn a cen cd a DH U1 PBD2 15 C PBOZ 14 C PBOZ 13 C PBO02 12 C PBOZ 1 DRSHIFT DRSHIFT Debugger Reset Debugger Run Run ms Continuous Run Step Command Window Set cursor on first line Run Check for FAIL Step 8 Debugger S ER OQ E Pin Properties Commands Command Window E per rn ea e cer rer ted nor DH U1 PB02 15 C PBOZ 14 C PBO2 13 C PBOZ 12 C PBOZ 1 Repeat steps check at which B ODRSHIFT DRSHIFT E DH DL no longer FAIL occurs Step Here the U1 PB02_15 C is the causer Step 9 Check the circuitry why U1 PB02_15 C can disturb the Testbus GOPEL el
14. connected Compliance Pattern not satisfied Testbus failure occurs in certain Check over current check the data base of the board against faulty tests only wrong models for BScan ICs or non BScan ICs There is a Ground Bounce effect match settings of test generator Faulty board current peaks at short circuits There is TCK frequency ADYCS setting not optimized dependency Testbus not terminated properly GND on TAP cable or termination not optimal the situation only Testbus failure im Intercon the BScan hangs up itself by switching off the board internal power causing DRSHIFT seems to be supply the power does not break down immediately unstable in Debugger DRSHIFT Check power consumption step mode the failure appears earlier What happens if BScan pins Those pins are normally detected and kept in stable inactive state drivers are connected to TAP automatically They will not get a Drive function lines Solution Load the IDCode instruction Advanced Options Generate Infra structure Test Options Mrs IDCODE instruction preload lt Debug Test USERCODE registers Execute Test BOUNDARY registers separately Write statements in BOUNDARY registers test Don t use statement CheckIdcade Testbus failure in INFRA test only Possibly a BScan IC with IDCODE register is not compliant to the Standard and the ID Code register is not selected by default GOPEL electronic FAQs Is it possible to utilize
15. driver The level is not defined when the driver is not connected but this can be compensated by parallel connection with a high omic resistor ideal case Rt Zo Rt Low ohmic serial resistor on the driver output is possible but works only well for single receiver Rs E scenarios There is a voltage drop along the line Ji Minimum load for the driver T Note there is voltage drop along Rs This should be avoided 1 Too many BScan ICs in parallel on TCK and TMS Rule of thumb Spend one buffer for 5 ICs 2 Direct neighborhood of TCK to other signals including TAP signals on cables or on the board over long distance 3 Direct coupling of TRST and System reset Star wiring of TAP signals TCK and TMS 5 Complicate jumper scenarios in order to achieve a certain scan chain design Misunderstandings can easily a time waster a COPEL electronic Application Note Testbus Failures Detection of Testbus Failures Testbus Failures are detected only when executing CASLAN tests and during IEEE 1532 programming Along every scan instruction DRSHIFT IRSHIFT a Testbyte is transferred in addition to the actual required data stream In other words The Testbyte is put through the UUT s scan chain In the case the Testbyte comes back faulty a Testbus failure message is generated and the test is aborted If the faulty scan operation was a DRSHIFT automatically an IRSHIFT will follow in order to allow deeper diagnosis For more
16. is not a matter of shielding but GND must carry back the driver current Cable design TDI mismatched with TDO Testbus cable no twisted Pair nor flat cable with GND Signal GND Signal scheme GND connection on the UUT side is not close to the TCK connection if the distance is too large the current back is overlaid by current of other sources Testbus signals are not terminated on UUT side this results in line reflections that causes over and under shoots More than 5 BScan ICs in parallel on the same TCK and TMS lines this can result in spikes dips in the Ground Bounce problem not handled source of Testbus failures during test execution TCK frequency is close to the maximum usable one sporadic Testbus failures pseudo data failures Testbyte de activated possible Testbus failures are not detected and will lead to a wrong diagnosis with a number of nets being reported faulty in Intercon RAM Intercon and Cluster test Testbyte de activated in order to get a partly result of the INFRA test the result has no value at all BScan activates the System reset on the board BScan switches off board internal power supply BScan controls buffers for the Testbus Drivers drive against each other defect or poor data set preparation Library model assembly versions CAD data Extended Generator Settings BScan driver pins drive actively on Testbus lines Not enough wait time after activating the power supply extern or on board Assumption
17. shows a source of problems for unstable synchronisation on the Testbus Because of no observance of the fan out there are dips that may be treated as extra clocks Such spikes can be sometimes very small and are visible only by means of scopes with a high bandwidth Ch3 Kopplung Ch3 Kopplunq amp Impedanz SU uad H20 0ns A Ch3 19 80 eun Position Offset Tastkopt 2 0 5 1 04 div 0 000V einsteling Kopplung Invertier Bandbreite DC Aus div 2 10 X Voll For effective search for the Testbus failure reason some questions get answered before using additional measurement technique For this sometimes a few extra tests are required Does the Testbus failure occur with the first DRSHIFT IRSHIFT 2 Does the failure message contain HIGH or LOW and Controller TDI 3 Does the Testbus failure occur in all retries Does the Testbus failure occur in all tests 5 Does the Testbus failure occur at low frequencies TCK lt 1 MHz 6 Does the Testbus failure occur on all boards a COPEL electronic Application Note If all questions get a yes there is typically a general problem because the Testbus does not show any reaction at all Here mainly as the failure reasons are faulty wiring static asynchronous reset in particular due to missing power and strange pins on Testbus Alternatively can be the last IC in the chain that is driving the TDO of the UUT the reason Check
18. 4 PARK 5 SHIFT 6 PARK 7 PARK 8 PARK WRITELN TESTING TAP5 CALL pActionSelect CASE 51 WRITELN chosen TAP does not exist JMP NewSelect SCANPATH 1 PARK 2 PARK 3 PARK 4 PARK 5 PARK 6 SHIFT 7 PARK 8 PARK a COPEL electronic Application Note WRITELN TESTING TAP6 CALL pActionSelect CASE 60 WRITELN chosen TAP does not exist JMP NewSelect SCANPATH 1 PARK 2 PARK 3 PARK 4 PARK 5 PARK 6 PARK 7 SHIFT 8 PARK WRITELN TESTING TAP7 CALL pActionSelect CASE 73 WRITELN chosen TAP does not exist JMP NewSelect SCANPATH 1 PARK 2 PARK 3 PARK 4 PARK 5 PARK 6 PARK 7 PARK 8 SHIFT WRITELN TESTING TAP8 CALL pActionSelect CASE 8 STOP 1007 WRITELN END WRITELN JMP NewSelect END a COPEL electronic Application Note Literature 1 Software description SYSTEM CASCON User Manual User Interface Selected Topics Version 4 6 2c GOEPEL electronic GmbH 2013 www goepel com 2 Boundary Scan Probe Technical Description Version 1 0 GOEPEL electronic GmbH 2008 www goepel com 3 Application Note Usage of Boundary Scan Probe Version 1 7 GOEPEL electronic GmbH 2007 www goepel com 5 Application Note Implementation of Boundary Scan during ASIC
19. ShittlA LI1 IR 2 1 0 Testbyte 2 The un modified value of that 2E ShAHAR 0 UTIR IS 1 D 0 Testhyte 3 27 Shi 0 4 1 1 1 Testbute 4 vector 52H proves the correct 28 Sh 0 UNIRI 1 0 o NERO function of the Scan chain 23 shitln 0 UTIR E 1 1 1 Testbyte E and the identity between 30 shitlh 1 U1 IR 7 1 D 0 Testhyte 7 EE b library model BSDL and 32 UpdatelR 0 m reality regarding IRSHIFT 33 L Step Cursor End Save Executed steps 33 Remaining steps 0 Errors 0 z GOPEL electronic Application Note The Boundary Scan Probe allows the check of a TDO output for correct function In debugger TCK Step Mode an IRSHIFT is executed Check for the TDO is active only in the TAP state ShiftIR ShiftDR the first two bits at ShiftIR are 01b LSB 1 This is because of the fact that the two LSB bits capture values of the instruction register are constant and defined according to the Std with O1b This behavior is identical on all BScan ICs All BScan ICs provide simultaneously on TDO O1b that may be checked by the debugger Just the following bits are depending on the chip design and can be found in the BSDL file Library Instruction Capture Values This check proves the correct function of the device under test 9 9 9 TCK TMS TDO Chip power supply Reset of the TAP controller 1s here not active In case of diffe
20. a low TCK frequency can compensate a poor Testbus cable design ringing and over under shoots are not depending on the frequency The program TCK Check up is applied on a not connected in CON not described TAP here the result is always PASS CON has been created manually but the order is wrong Possibly INFRA has PASS in particular in cases when no IDCode registers exist or identical device types are assembled in the chain High number of faulty nets in Intercon even BS pins that are connected to GND or VCC show the opposite level often Testbus failure due to driver conflicts wrong Testbus voltage settings on TAP Transceiver can cause High Low failures on the Testbus ignoring Testbus faults as the user is interested in the measure results from the UUT only a COPEL electronic Application Note Terms and Abbreviations gt az Test Access Port the interface for the testbus TAP Controller TAP control unit inside a BScan IC TAP State state of the TAP controller Ground Bounce Rise of the GND level internally in the chip on silicon due to simultaneous change of a high number of outputs the TAP controller can lose the synchronization Testbus signal Test Clock Testbus signal Test Mode Select Testbus signal Test Data In TDO Testbus signal Test Data Out TRST Testbus signal Test Reset ADYCS Active Delay Compensation CASCON property to compensate signal delay along Testbus lines buffers CASCON s programm
21. an chain are properly described in the Scanpath Configuration File CON The same is required for possible Scan Router ICs 5 Existing Scan Router ICs are applied with the correct address given in the CON file a COPEL electronic Application Note Testbus Design Needs and Mistakes Observe the board design in the run up for 1 TAP connection They can be fed via a special connector via the system connector or via fixture probes In any case however GND connections must be provided as well 2 The TAP cable requires on both sides GND connections It is not a matter of shield but of carry back the current of the TAP signals 3 GND connections should be located close to the TAP connections They should be available independent from Power Supply GND connections 4 Line terminations shall be ideally located on the end For small or medium size boards the can be closed to the edge connector for the TAP Possible Variants of line termination This variant ensures Low level when the driver is not Zo connected It is the most popular scenario ideal case Rt Zo VCC GND Here the termination resistor is split in two individual RH resistors Due to RF parallel connection of VCC and x GND by bypass capacitors both resistors can be gt z treated as parallel connection The logic level is High when the driver is not connected ideal case Rt1 Rt2 ENP The scenario on the left ensures a particular low load for the
22. and PCB Design Version 1 0 GOEPEL electronic GmbH 1999 www goepel com 6 Application Note DFT Rules for Boundary Scan Samples Version 1 0 GOEPEL electronic GmbH 1999 www goepel com
23. ant is that the BScan ICs can synchronise among each other And this is guaranteed as long as there is no essential delay between two ICs in terms of TCK arrives too early The controller s TDI can be also considered as a BScan IC s TDI and normally it would have a delay problem as discussed above because the controller would use the controller s TCK that 1s connected to the UUT But ADYCS compensates exactly this You can see only the delay between the last IC and controller s TDI will be compensated Conclusion a COPEL electronic Application Note Buffers on the backplane are good for signal quality There is no effect difference between different buffer types with different delay for the TAP buffers on the backplane because all boards will see the same delay The only time critical detail is the delay along the line between the last IC of a board routed to the TDI of the next one Do not use buffer there This delay could be compensated if you would delay TCK and TMS for the next board by buffer Here is the real limit but this can be measured calculated z GOPEL electronic Application Note Typical Mistakes and Misunderstandings gt 9 9 9 9 9 The Testbus failure report is not red by the operator carefully However it points very often to a particular failure location and moreover it generates hints for Troubleshooting Testbus cable s GND line is connected only on one side it
24. details see section 0 Testbus Failure how is it defined Specialities 1 In multiple TAP scenarios the individual scan chains get their own Testbyte This ensures a TAP depending failure message 2 Inscenarios with ScanRouters implicit DRSHIFT and IRSHIFT instructions are used within the LOCALPATH instructions 3 For Multidrop configurations based on ScanBridges or Addressable Scan Ports for every ScanRouter an individual Testbyte is used 4 Because of missing information there is no diagnosis for Testbus failures possible during FLASH programming The Testbus Failure Message Example more examples in section 0 Typical Testbus Failure Messages by CASCON 0104 Testbus failure at DRShift Diagnosis by IRShift HIGH starting from Ul check UZ TDI and UI TCK TMS TDO 117 12 DRSHIFTs have been executed Possible Value Art der failurehaften Scanoperation Testbus failure at DRSHIFT Diagnosis by IRSHIFT without Testbus failure LOW starting fromm j ATL starting from Failure localization within the Scan chain Check U2 TDI and U1 TCK TMS TDO x Check devl TDI and lt dev2 gt TCK TMS TDO BEEN dev1 and dev2 are adjacent scan components One of them can be the controller program For more details about failure message see section F Reasons for Testbus Failures The possible Testbus failures can be sorted in categories as shown below For more detailed diff
25. ectronic Application Note Troubleshooting at dynamic Failures by means of Scope This proves if the TDO changes on falling TCK as expected Definition The rising TCK edge loads the parallel inputs of the cells Capture falling one changes outputs Update Note red TCK blue TDO Correct operation TDO changes on falling edge Faulty operation sometimes is Update with falling edge sometimes with rising and falling one The reason can be a reflection or spikes on TCK Also signal rise times can be critical Observe the datasheet for that 200V Chi 2 00v W10 0us A Ch V 1 16V Special Cases in Practice Those cases are not representative however they show that difficult cases can happen Often the behavior has not been compliant to the Standard Chip Vendor Failure image Reason Work Around lt type name protected by NDA gt Instead of 1 there are 3 BScan cores inside one package Only one of them is usable for JTAG mode lt type name protected by NDA gt The length of the BScan register in mode SAMPLE PRELOAD is shorter than in EXTEST the function however is correct Infineon MPC8548E 1333 CFCBGA PGEQI At the TAP transition from Update DR gt Run Test Idle gt Select DR Scan gt there is no UPDATE if the mode EXTEST has been loaded Texas Instruments TMS320C6713 Sporadic Testbus failure often PASS after reset Sporadic FAIL then the length of the BScan register does not match the
26. epending on the length of the stub Chi Freq Explanation CENT san The open line causes reflection Also this line has a capacitive load due to wiring in the fixture Blue TCK signal of the faulty IC Essential spikes on the edges therefore there is no chance for synchronization The voltage range of the spikes is critical they appear to IC1 as extra clocks Red Also here spikes are visible However due to the serial resistor they are transferred to a non critical voltage range However it is an indicator fort he trouble described above TCK from controller 4 Solution Cut the connection to the fixture Here we have a BScan combination with a MDA Tester The Testbus is instable we see sporadic Testbus failures ATTI MCLK The TCK check by Scope on the UUT proves mee The Testbus signals are heterodyned a clock of 12 MHz The clock generator is on the UUT Explanation A bi level fixture on Testpoint X is assembled with a wrong size of probe As a result the clock signal is transferred down to the fixture and interferes there the TAP signals Solution Avoid connection of those signals during BScan test by choosing short sizes of fixture probes 1 00 V H 1 00ys a COPEL electronic Application Note Question Catalog Index Hyperlinks Question Catalog p Failure Images amp Questions Failure Reasons Hints Testbus failure ist stable Testbus cable System Reset active TRST not
27. erentiation see the following sections Typical Pattern of Defect Manufacturing defect Happens only on certain boards Wrong parameterization Can be excluded by low frequency 1 MHz or less and TCK frequency delays voltages setup of the voltages 3 poor Testbus signal quality Typically change of fault locations and messages At lower TCK frequencies better but not error free a COPEL electronic Application Note function Wrong wiring Controller UUT in particular Every test fails at the first SHIFT TDI TDO mismatched LOW starting from TDO Device of the ULI and controller TDI Low High depends on Pull Down Up resistor Asynchronous Reset of the Testbus Reset can be active static then the same as faulty wiring TRST Power Compliance Pins Watchdog At dynamic resets the Testbus failure happens typically always on the same position of CASLAN exception Watchdogs and on the same H W position in the Scanchain Wrong modelling description Testbus failure constant on the same position in Scanpath Configuration File BSDL Files CASLAN when wrong register lengths occur IRSHIFT mostly failure free possible asynchronous reset due to wrong cell port allocation strange external pins on the Testbus The same as asynchronous reset buffer in Testbus not transparent other pins active illegally Board design failure 8 Non compliant behavior of components Failure when utilizing certain registers
28. ge 117 0 DRSHIFTs have been executed Scan Bridge Address 3H not found This message contains two information e Testbus failure for the Scan Router own Scanpath primary TAP and addressing failure e UUT no Power supply e Testbuscable is defective e Address is wrong Meaning possible Failure a COPEL electronic Application Note lt OL0G gt Testbus failure ac IRNI HIGH Starting rom UZU Check Uz0s I01l and UZUR rMS TD QO Oo V lt 117 gt 2 DRSHIFTs have been executed e U202 has no TMS or TCK eo e U202 in Reset Mode E E e U202 Compliance Pattern not satisfied S e e Connection U202 TDO gt U203 TDI has problems a COPEL electronic Application Note Further Analysis Trouble Shooting Strategy These questiones needs to be answered Question Use Run Continuous Run 2 Does the content of the failure message change Yes Check stability of the Testbus see section 3 Is the failure TCK frequency depending Check ADYCS check cable design Does the failure occur only on certain test programs Yes continue with 5 No Check Sie die Stability des Testbus see section CASLAN Program TCK Check Up Does the failure occur at the begin of the testprogram Yes continue with Section Static Testbus Does the failure occur in the middle of the Yes continue with 7 testprogram Is the faulty test step constant and independend from Yes continue with Section Tr
29. h j SelectH x BEN Capiucl 0 r x J mi The LSB comes out first 5 ShitlH Testhyte D D 11 1 uei E Shitlh 0 Testhyte 1 1 U UZR Thes e signal names of the 7 Shitlh Testhwte 2 0 1 1 UFR 8 Shift Testbyte 3 D UZR TCK Step Window 9 ShitlH Testbyte 4 1 1 1 HZ 4 correspond to the controller T Shitlh 0 Testhyte 5 o fo Dp USRG signals This means TDO 11 shitlR 0 Testhwte E 1 1 1 UZIR E j a 32 C Sh Testbyte 7 0 8 o URI is the TDO of the controller 13 shilhR 0 U2Z R 0 1 1 UZIR 8 and so on 14 shilh oO UzIR I 1 D UZR 1E shilR 0 UZ R 2 1 1 1 URO 1E Sh 0 UZ IR 3 1 D UtirlJ 1 Sh oO UzIR 4 1 z UR 18 shilh 0 UZ 5 1 z OF UIA 18 Chit ri 12 B TRI 1 M 1 LIR 31 Step Cursor End Save Executed steps 33 Remaining steps Eros 0 Reset gt IrShift gt Runidle D x Step TAP state TMS OUT Dev Register Pin Cell TDO EXP TDI IN Dev Register Pin Cel Since 8 bit are shifted in 17 shih 0 UZIR 4 1 x 0 OUR addition to the actual chain 18 shitlh 0 UZ 5 1 x UIA 18 shitlh 0 UZ 6 1 z UR length on the board the 20 shitln D U2 I 7 1 0 URS Testbyte must arrive at the 2 ShittlA UZIR 8 1 0 D OXIR B end of the transport in the 22 shilh U2Z R 3 1 D HUi l 7 23 shitlR 0 UH1 IR 0 1 D 0 Testhyte U controller 24 shitlh OSCR 1 1 1 1 Testbute 1 25
30. has no TMS or TCK E E e Ul stays in Reset Mode S S e UI Compliance Pattern not satisfied lt O101 gt Iesrbus rarilure at DER Nirti Diagnosis by TP birth LOW starting fron Bocan controller check U1 IDI and Bb5oaH conLtroller ILA LMS IDO Message L i DESHIETIS have Deu excited e Connection controller TDO gt U1 TDI has problems Meaning possible Failure a COPEL electronic Application Note 001 IBSsrDHS railure at DR Niri Diagnosis by IBS2BDLIrt LOW starting from Ue Check Bocan controller IDI sud BZI ICK LIMS Ti QO Oo V 117 1 DRSHIFTs have been executed e UUT no Power supply SFX TAP module of the UUT not allocated SEX TAP module wrong TAP voltage settings Testbus cable defective Connection U2 TDO gt Controller TDI has problems U2 has no TMS or TCK U2 stays in Reset Mode U2 Compliance Pattern not satisfied Meaning possible Failure e o o o o Example 2 Scanpath multidrop by SCANPATH 1 Scanrouter IC SCANROUTER U100 scanstall2 BO CON ADDRESS 03h LOCALPATH 7 DEV U204 XC9536XL 10VQ44C LOCALPATH 6 LOCALPATH 5 DEV U203 XCR3064XL VQ44C LOCALPATH 4 DEV U202 XC9572XL 10Vo44C LOCALPATH 3 LOCALPATH 2 DEV U201 XCR3064XL VQ44C LOCALPATH 1 DEV U200 XC9536XL 10VQ44C UID3S Testbous ranrlurse at IBShitrti LOW starting irom UlIlDO Check Bocan controller TDI and ULOD ICK IMS IDO Messa
31. he same TAP state This requires TCK and TMS have to be connected in parallel to all BScan ICs on the board 2 The maximum applied TCK frequency is chosen to such value that the clearance of minimum 3 MHz to the maximum TCK of the slowest BScan IC in the chain 3 The settings of signal delay compensation AD Y CS are chosen to such levels that the system operation is guaranteed over the complete range between TCK min and TCK max 4 The voltage levels are defined to needs of the respective BScan ICs If needed level shifters are applied 5 There is no crosstalk between the Testbus lines 6 There is no crosstalk between Testbus lines and other signals on the board Dynamic Conditions 1 The signal quality des TCK is such that no essential ringing can occur For this a good cable design and an appropriate line termination is required 2 Thesignal quality des TCK such that signal edges are free of dips For this the fan out of the drivers must be considered 3 The ADYCS parameters are optimized This will allow the system to sample the data coming from the UUT at the correct time Static Conditions 1 The actual length of the data registers and the instruction register correspond to the BSDL File 2 The relationship between instructions and herewith selected data register is according to the BSDL File 3 Possible Compliance Patterns are defined in the BSDL file and are realized on board 4 Count and order of the BScan ICs in the sc
32. ing language source code of tests e TMS CASLAN SVF Serial Vector Format simple vector description format for TAP activities de facto Standard Vector description format more flexible than SVF standardized Termination here Line termination of correct impedance Testbyte A byte to verify the chain length a CASCON feature Fan out Driver parameter defines the maximum number of inputs that can be safely driven Compliance Pattern Side conditions to get access to BScan in the case the JTAG port is used for both purposes Debug Emulating and JTAG test ICs for splitting of Scan paths Boundary Scan Description Language File Instructions register Scan Path Configuration File CASCON file the IC mentioned on top is connected with it s TDO to the controller s TDI S Least Significant Bit UUT Unit Under Test JAM STAPL Scan Router BSDL ES a Z More Help needed If all work steps described in this application note you need the support by Goepel electronic Our application team will assist you For this please use BScan support goepel com Excluded from this support is the supply of BSDL files For this please contact in any case the chip vendor a COPEL electronic Application Note Appendix Test Program TCK Check Up ITAP Note Starting from CASCON 4 6 0 you need CON depending versions of the test program The version below reflects version for TAP1 only
33. is is done with the CASLAN test TCK Check Up moreover the Frequency and PASS FAIL information is displayed The Debugger Command Window allows to use directly IRSHIFT in a test program Exceptions In System Programming FLASH SVF JAM STAPL For this just launch the program in Debug mode open the Command Window and type in IRSHIFT a COPEL electronic Application Note Debugger start the program waits at the 18 first instruction 13 Begin 20 zi 22 LDI UZ ae LDI Ul 24 IrShift Open the Command Window type in CASCON GALAXY 4 4 2 beta03 CASLAN Debugger IRSHIFT File View Help 2 FEE FS Fi E IQ A ES 993 gt Pin Level z B Commands 1 21 R 31 4 IRSHIFT CASLAN Program TCK Check Up That test program can be imported in any CASCON project because no IC is addressed The kernel is the two instructions IRSHIFT and TCK The Testbyte is disabled exceptionally in order to recognize possible interruptions of PASS ranges For the CASLAN code see the appendix The content of the result window consists of a TCK frequency scale and underneath a dot for PASS or F for FAIL FAIL happens when the measured Instruction register s Capture value is different from the expected one Optimum setting there is no essential interruptions of the PASS stream Faulty line termination or wrong ADYCS setting There are alternating Good and Bad sections
34. n instruction selects a data register that is connected between TDI and TDO for following DRSHIFTs A data register is selected by an Instruction or is selected per default as defined in the Standard The default data register is the Idcode register if exist otherwise the Bypass register Caution Do not disable the Testbyte when executing tests Otherwise you lose the safety for the UUT during the test execution Only in rare exceptions those are technically required can must the Testbyte temporarily disabled A Testbus failure can be stable However it can behave dynamically See following chapters for more failure cases and their typical reasons a COPEL electronic Application Note Typical Testbus Failure Messages by CASCON Example 1 simple test set up SCANPATH 1 CON DEV U2 EPM7032AETCA44 DEV UL ACES 722A IOIUO Testing boundary register U2 lt 0108 gt Testbus rallure at DRShiEE 1PFSRBi1fE without Testbus o failure 2 FAIL starting from Bocan controller check UI IDI and Bocan S controller TCK TMS TDO lt 117 gt 4 DRSHIFTs have been executed e Length IR OK data register here the BScan register wrong length oo Q gt e Check BSDL and Compliance Pattern oe eem Sa OIDJI Iestbus failure at DBoShirc Diagnosis by IBSBIEZES o HICH carting Crom Ul chock U T ano PE I PES an e S eP UR AET Tao Deene e e e Connection U1 TDO gt U2 TDI has problems x e Ul
35. ntercon RAM Intercon Time between Update and Capture Normal Test Execution z Parallel Time between UpdateDR IR and CaptureDR f Normal about 1 ms Fast 2 5 TCKs disadvantage Missing Pull resistors sometimes cannot be detected Failure on board design There were planned resistors for different assembly scenarios however the actually mounted one was different Due to this two TDOs have been connected in parallel Failure on board design The TRST pin was connected just to an IO of the Spartan 3E in addition there was an Pull Up of 4k7 No connection to the BScan controller s TRST output Xilinx Support It is expected to see I Os pulled up down with unconfigured device when SAMPLE instruction is loaded and the TAP controller switch to Update IR state If HSWAP is high you will see all I O pulled down but if HSWAP is low you will see all I Os pulled up The workaround we give to customer is then to use BSDLAnno and set the I O as needed if the pull up down effect is problematic a COPEL electronic Application Note One BScan IC shows Testbus failure the others in FAIL PASS PASS the same chain are error free The faulty IC IC1 is connected through a serial resistor in the TCK line moreover from there 1s connection to a fixture line The opposite end of 100R that line is open stub The period time of ringing shown in the clock diagram blue signal Wire to fixture after edges is directly d
36. oopCnt CALL pLoop20MHz CASE 3 STOP 200 1000 END END PROC p FAIL BEGIN WRITE FAIL LD failflag 1j END KKK KKK Ck kk Ck Ck kk Ck k K kk K OK kk OK KOK K K KOK kk ck MAIN kckck ck ck ck kc kck ck kc kckckckck ck kc kckck ck kckck X k k ck kk BEGIN ON ERROR p FAIL NewSelect LD vSel 0 WRITELN TAP select READSELECTION TAP selec vSel TAP1 TAP2 TAP3 TAP4 TAP5 TAP6 TAP7 TAP8 EXit SWITCH vSel CASE 0 SCANPATH 1 SHIFT 2 PARK 3 PARK 4 PARK 5 PARK 6 PARK 7 PARK 8 PARK WRITELN TESTING TAPI CALL pActionSelect CASE l3 WRITELN chosen TAP does not exist JMP NewSelect SCANPATH 1 PARK 2 SHIFT 3 PARK 4 PARK 5 PARK 6 PARK 7 PARK 8 PARK WRITELN TESTING TAP2 CALL pActionSelect CASE 2 WRITELN chosen TAP does not exist JMP NewSelect SCANPATH 1 PARK 2 PARK 3 SHIFT 4 PARK 5 PARK 6 PARK 7 PARK 8 PARK WRITELN TESTING TAP3 CALL pActionSelect CASE 31 WRITELN chosen TAP does not exist JMP NewSelect SCANPATH 1 PARK 2 PARK 3 PARK 4 SHIFT 5 PARK 6 PARK 7 PARK 8 PARK WRITELN t m eccceccccccc TESTING TAPA CALL pActionSelect CASE 4 WRITELN chosen TAP does not exist JMP NewSelect SCANPATH 1 PARK 2 PARK 3 PARK
37. oubleshooting at the TCK frequency Testbus Failures during Test Run Time No check for asynchrones Reset Does the failure occur on a new board Yes possibly program faulty Debug required Does the failure occur only on certain boards Yes possibly manufacturing defect 0 Is the failure location at the begin of the chain TDI Yes cable to controller possibly level UUT 11 Is the failure location at the end of the chain TDO Yes continue in section Static Testbus ps UUT UA General Guideline for Troubleshooting A simple method is the execution of one IRSHIFT instruction in a manually written test program No particular instruction code is required This will result in loading the instruction BYPASS by default As also no IC name is addressed all scan components will get the instruction BYPASS Sequence Executables Manually New test name CASLAN BEGIN Files CASLAN IBSHIFT END For check versus TCK frequency dependency you may change in Execute options of the test the TCK Use Special TCK Frequency Recording Test Execution _ Teststep Recording The target is to see if there are TCK ranges without Fail Yalues faults write Failed Pins to the Result File _ write Failed Groups to the Result File Testbus IM Permanent Testhus Check using a Testhyte Use special TCK Frequency 1 000000 MHz More efficient is to change the TCK frequency inside the test program Th
38. r all speed grades including regarding ADYCS speedgrade A Why is the measure result one step DRSHIFT after the DRSHIFT updatng the driver Is there a way to check a TDO pin for tristate or active Why do all ICs simultaneously issue on their TDO O1b when executing IRSHIFT How can we fix solve Ground Bounce problems Topic TAP Connections on Backplane Scenario 8 similar boards on which there are 3 Boundary Scan FPGAs to test the back panel connectors Some cables connect the boards with each other this creates a long boundary scan chain Question What is the best way to route the TCK line Capture occurs before Shift and Update after That s why the controller gets the measure result with the next DRSHIFT High omig voltage devider e g 2x 10 kOhm nagainst GND and VCC 0V 1 2 VCC VCC observe by DMM or scope BScan Probe LEDs show the state directly Since all ICs are supplied with the same TCK and TMS the must be always in the same TAP state Therefore at TAP state Shift IR all ICs clock out their Capture value of the Instructions register starting with LSB And this is according to the Std O1b CASCON offers in the Generate options the feature to reduce the number of output pins that change their level simultaneously and split the instead to several DrShifts The ideal scenario is when all signals coming from the controller have the same delay The delay itself is not important Import
39. rences check the signal levels logic and voltages In particular at constant 0 or 1 check for possible short circuits to power nets or to active drivers Further Possibilities by the Boundary Scan Probe Beside the obove mentioned features you may use the Boundary Scan Probe use also for 9 9 9 to check the lengths of IR and data registers to check the IDCode to check the relation between IR code and data register length to check the allocation of BScan register cells and pins to trace the signals TMS TCK and TDO on a board For further informationen see the section a COPEL electronic Application Note a COPEL electronic Application Note Troubleshooting at Testbus Failures during Test Run Time In the beginning the Testbus is error free but is disturbed before normal end of the test Because of the cancelation the diagnosis report cannot be generated Just the Testbus failure message is generated Use the following method when the failure appears constantly at the same test step Note In case of time pendent failures the faulty step can be changed when operating the Debugger Find out which BScan driver causes the problem Strategy See in Debugger which test step which BScan driver which level Method Insert in CAS additional DRSHIFT automatic in debugger from CASCON 4 4 1 Find the CAS line Debugger STEP mode Find the BScan driver Debugger Command Window break up the CAS line Procedure
40. the full PASS TCK range detected in TCK Check up test for other test programs Which TCK frequency for which executable type makes sense Application Note Not really In that test program only an IRSHIFT is executed In Extest mode and in DRSHIFT differences can happen For experience Reduce down by 3 MHz the found maximum TCK frequency Infra Intercon RAM Intercon Cluster SVE 1 3 MHz or higher High TCK frequencies in Intercon can cause pseudo errors for Pull resistors RAM with many DRSHIFTs e g DDR2 SDRAM and Flash actions As high as possible however 3 MHz below the maximum TCK When is it advisable to apply a controller Speed Grade If you want to program more than just a few kbyte of B or Speed Grade C Why appears in the Testbus failure report often Diagnosis with IRSHIFT Even when a test program executes just a DRSHIFT in the case of a Testbus failure an IRSHIFT is issued too data down to a parallel FLASH in short time seconds then use Speed Grade B or C controller IRSHIFT is the only possibility get back constant vectors from BScan ICs More precise The Capture value of the IR is constant and has to be 01b for LSB according to the Std So opens on TDI and TDO can be detected This is an automatic element in CASCON M The IRSHIFT can help to locate the possible failure location see above How does the SFX controller of Speed Grade A act ADYCS is active fo
41. ures Application Note The TAP Test Access Port operation is based on edge triggered protocol The TCK signal serves for synchronization That s why it is the moist critical signal among the TAP ones In particular ringing caused by wrong or missing termination of the signal line can be interpreted as extra clocks Cable design between controller and UUT and UUT design itself shall follow the rules of RF design Dynamic Testbus failures show a relation to the TCK frequency Change of the TCK frequency can result in PASS or FAIL MC MN Tek stopped 1159 Acquisitions Trigger Level 2 06 V amp x sas 5 r k r k k k n r s s st r s s s s m r gt s s 5 st t t t rt 0 t t r Ch1 Freq HZ Level TL 2 06 V found 7 Chi Pk Pk ity oe We ee ee ee 5 24 V Set to TTL 4 xj y Set to ECL Set to 50 M 5 00ns Chis 2 06 V SOn coupline Slope Level mace Type i i amp m Ch DC WIJBA noidott Over and under shots the most often reason for instable Testbus In the examples the termination is obviously missing There is no chance for synchronisation epicuri teris Also the change of the TCK frequency does not have any effect 19 80 amp Feinskal 2 00 V H200ns A Ch3 2 16 V Kopplung Invertier Bandbreite D Aus Voll div Analysis Methods of Testbus Failures Position Offset 2 04 div 0 000 V TCK Signal This image
42. uskakoqsauqapaybakuqayayqqwqupuykaqhasaq 5 Dll T O bil l TET Emm 6 Dynamic MES ie RETI u uuu EE TO OO Te 7 Analysis Methods of Testbus Failures a nn nn nennen nnns 7 Faure N O Q a E TET ET nuan 52 sus 8 Testbus Failure HOW is it defined cisrscccopesinzesativansiedsenadioydceedind a TT SE E aT E aN 8 Typical Testbus Failure Messages by CASCON aocscccccsscsseecesavevecatadiveateresscodsbecesssavesevancadedauseonseedssaddeectenesates 9 Further Analysis Trouble Shooting SAP V i uu eei a ei p Pei isni paid desk a se si pu II P Hess ra nans PIED EU D MM IEEE 12 General Guideline for Troubleshooting aa 12 C ASEAN Prosram PC CHOCK Up ussiisa a ad piste FOR OSmpsein ium SI aidai 13 6S on TDO Bi M S 14 Further Possibilities by the Boundary Scan Probe 16 Troubleshooting at Testbus Failures during Test Run Time 18 Troubleshooting at dynamic Failures by means of Scope 22 PE C1 C O TE Ti KK eeen oo aatiun ative denned ETE 22 Question Catalog Index Hyperlinks
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