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DNA PPCx PowerDNA Cube Manual - United Electronic Industries

1. Figure 1 1DNA PPCx Cube Specifications A eee Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap1 fm 6 DNA PPCx PowerDNA Cube Manual Chapter1 7 Introduction 14 DC Power Table 1 1 below describes the DC power thresholds for DNA PPCx PowerDNA Thresholds Cubes Table 1 1 DC Power Thresholds for DNA PPCx Cubes Backplane Power Rail Voltage Turn on V1 Reset V Turn off V Notes Logic Power 3 3V 2 5V 8 8 8 4 7 7 Supply Analog Power 24V 8 5 7 8 Supply Fan Power 12V 8 8 8 4 Supply On layer VIn 7 8 to 8 8 7 5 8 5 Varies with the DC DCs that layer used use input power 1 Turn on V The value of Vin at which corresponding DC DCs turn on 2 Turn off V The value of Vin at which corresponding DC DCs turn off NOTE A DNA PPC core module consumes only 240mW when Vin is below 7 7V Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 Hhited Flecironic ndustnes Ine Date December 2012 File PowerDNA _Chap1 fm DNA PPCx PowerDNA Cube Manual Chapter 2 Installation and Configuration Chapter2 Installation and Configuration Installation consists of e PowerDNA software package installation e Cube hardware setup e Configuration 2 1 Initial This section outlines the steps to be taken in Section 2 2 Installation
2. Bit Name Description Reset 31 DQ_STR_EN When read as 1 indicates that CR is enabled in CTO_CTR 0 DO CTR_EN bit 30 DQ STR _BUSY When read as 1 indicates that CR is counting or 0 if current 0 counting operation is complete 29 DQ_STR_CROL When read as 1 indicates that current value of CR lt CRO 0 28 DQ_STR_CROGE When read as 1 indicates that current value of CR gt CRO 0 27 DQ_STR_CR1 When read as 1 indicates that current value of CR gt CR1 0 26 DQ_STR_INO Report current value of direct input pin 0 25 DQ_STR_GTO Report current value of direct gate pin 0 24 DQ_STR_IN1 Report current value of de bounced input pin 0 23 DQ_STR_GT1 Report current value of de bounced gate pin 0 22 DQ_STR_IHL When read as 1 indicates that 1 0 transition was detected on the 0 input pin since last read from CTx_STR This bit will be automatically cleared after each read 23 DQ_STR_ILH When read as 1 indicates that 0 1 transition was detected on the 0 input pin since last read from CTx_STR This bit will be automatically cleared after each read 22 DQ_STR_GHL When read as 1 indicates that 1 0 transition was detected on the 0 gate pin since last read from CTx_STR This bit will be automatically cleared after each read 19 DQ_STR_GLH When read as 1 indicates that 0 1 transition was detected on the 0 gate pin since last read from CTx_STR This bit will be automatically cleared after each read 18 DQ_STR_OU Report curren
3. if this field lt 32 or gt 2048 read all2048 bytes sernum serial number pad to 07d when printing mfgdate manufacturing date Oxmmddyyyy user access caldate calibration date oxmmddyyyy calexpd calibration expired Oxmmddyyyy header is followed by device specific data structures DQEECMNDEVS pDQEECMNDEVS uint32 CALSET_xxx_ contains layer calibration information Firmware writes this infor mation automatically upon entering initialization mode OPMODEPRM xxx_ contains layer parameters for operation mode For example Al 201 has the following parameters stored typedef struct uint32 uint32 uint32 uint32 chlst AI201_ CHAN channel list full conf control word layer API flags cvclk CV clock clclk CL clock trig trigger configuration DOOPMODEPRM_201_ pDQOPMODEPRM 201 O Copyright 2009 all rights reserved United Electronic Industries Inc This structure varies from one major firmware revision to another When the firmware switches the layer into operation mode it processes stored configuration information as it would process configuration parameters received from host All working fields in the internal device information structure are filled and the unit is ready to switch into operation mode By programming the DQOP MODEPRM structure ahead of time and storing it into E 2PROM you can avoid programming the IOM every time before sw
4. Cancel Apply STEP 8 Click on the DNS tab Leave blank the Host Name and Domain fields STEP 9 Click OK to close the Microsoft TCP IP Properties window STEP 10 Click Close to close the Network control panel STEP 11 Restart your computer STEP 12 You should now be able to access network based services A 4 Configuringa A Set Up Your Ethernet Card NIC Second If you installed your Ethernet card before or at the same time as you installed Ethernet Card Windows 95 98 ME then the system should have automatically detected it and Under you should proceed to the next section Install TCP IP Optionally you may Windows 95 98 follow steps 1 3 below to confirm that your card is recognized SE ME If you obtained an Ethernet interface after Windows 95 98 Me was already on your computer then do the following STEP 1 From the Start menu select Settings and then select Control Panel STEP 2 Double click on the System icon then click on the tab labeled Device Manager ES O Copyright December 2012 Tel 508 921 4600 www ueidaq com Vers 3 6 Y e Ad Date December 2012 File PowerDNA_Appendix fm DNA PPCx PowerDNA Cube Manual 81 STEP 3 Double click on Network adapters to display a list of the network interfaces that are installed on your computer If you see two entries other than the Dial Up Adapter one is your second Ethernet card Skip ahead to Install TCP IP If you do not see your second Ethernet car
5. Cal Date Jan 21 2005 Enabled a Reference 24 0 i tine A ha v 1 Levet 16 8 V Output Shutdown Name Value J pOutt2 E Doul3 DOutt4 DOut15 DOut6 DOut17 DOutt8 Douga DOut20 DOut21 DOut22 DOut23 Figure 3 14 Example DIO 405 Layer Outputs Reference is a reference voltage 0 level 1 level are hysteresis values described fully in the DIO 401 2 5 section of this manual Input Output Initialization Shutdown tabs switch between settings for init and shutdown states as well as operation mode configuration and display of cur rent data All tabs contain the following columns e The unnamed first column contains the channels e Name is a user defined string e Value contains 0 or 1 It is a drop down menu for output channels allow ing you to select 0 or 1 The DI 401 layer just has Reference and 0 and 1 Level controls and Input tab The DO 402 layer just has Output Initialization and Shutdown tabs no Refer ence value or Level sliders The DIO 403 layer is different because it groups 8 bits at a time into ports and three ports into two channels For the sake of abstraction in PowerDNA Explorer we ll call all the ports channels A OSSOS Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap3 fm DNA PPCx PowerDNA Cube Manual Chapter 3 37 PowerDNA Explorer 2 Po
6. f The version is given in the FW Ver field 2 PowerDNA Explorer 0 x File Network View Help ee m Host PC o llom_10238 Name 10M_10238 Model 1008 Motorola ColdFire 5272 CPU 100 Base T PN Ver 3 0 16 SN 0010238 MAC 23 F8 90 7B 19 40 IP 192 168 100 2 Mode Configuration If the FW Ver field has is version 2 x x or 3 x x let x be any version number you should follow the Firmware Update Instructions CM5 CM8 section below For other versions of firmware e g 1 x x refer to the user manual on the CD Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap2 fm DNA PPCx PowerDNA Cube Manual Chapter 2 20 Installation and Configuration that accompanied your device when you purchased it 2 2 8 Firmware Before using a new release of the libraries and applications to communicate Update with your PowerDNA cube you must install the latest version of the firmware on Instructions the PowerDNA cube The version of the firmware must correspond to the ver sion of the PowerDNA Software Suite mismatched versions cause an error Instructions for updating the PowerDNA Cube via PowerDNA Explorer over an Ethernet LAN line and over an MTTTY serial line follow To upload firmware with PowerDNA Explorer over LAN do the following STEP STEP 2 Connect the PowerDNA cube to its network STEP 3 Start PowerDNA Explorer on the Microsoft Windows de
7. 0 0 0 0 0c eee 50 5 2 3 Interfacing to the CM Module Using a Serial Interface 50 5 3 How to Update Firmware 00 0 ccc eee eee 55 5 3 1 Clock and Watchdog AcceSS 0 00 eee eae 55 5 4 Common Layer Interface saser eia aradeni a ratae e 55 5 4 1 Channel E N E EE E T titre E ETEA radia EET 55 5 4 2 Configuration Flags euer vere spuir SEVAER teas 57 5 4 3 EEPROM User Area ACCESS o ooocooocnonno eee 58 5 4 4 PowerDNA Layer Signaling oooocccoccccooo eee 60 5 5 Register Map and Description anana a aaae ee 62 5 6 Register Descriptions 3 Lasa eka A RA E ee 63 5 6 1 Valid EM CM Combinations for Non Buffered Modes 68 5 6 2 FIFO ACCESS vita a ii a oh daa 70 5 6 3 Command Mode syede dora REER a ad 71 APDEA AICA a A A AA A AAA EG 72 A 1 Configuring a Second Card under Windows XP 0 00 e eee eee 72 A 2 Configuring a Second Card under Windows 2000 0 00 75 A 3 Configuring a Second Card under Windows NT 20220000 e ee 78 A4 Configuring a Second Card under Windows 95 98 SE ME 80 List of Figures Chapter T Introduction ordea e a wie ee ane a a ole ee aes 1 1 1 DNA PPCx Cube Specifications ooooociciccinnnnonconccncnnncnncnnncnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnns 6 Chapter 2 Installation and Configuration 00 00 cece eee 8 2 1 Typical MT TTY Startup Screen cccccccccecceeeeeeeec
8. 3 6 Hhited Electronic Industties Ine Date December 2012 File PowerDNA _Chap2 fm 2 2 3 O Copyright 2009 all rights reserved United Electronic Industries Inc DNA PPCx PowerDNA Cube Manual Chapter 2 Installation and Configuration Initial Boot up This procedure is needed to prepare for network configuration Do the following steps STEP 1 Familiarize yourself with front panel layout Note that all connections are made on front of the unit no rear access is required in a rack mounted configuration STEP 2 Attach the serial cable to the host PC and to the DNA Cube RS 232 port a Run a terminal emulation program MTTTY on the PC Any terminal emulation program may be used MTTTY Minicom TeraTerm etc Note that Hyper Terminal probably will not work with a PowerDNA Cube b Verify that COM parameters are set 57600 baud 8 bits no parity 1 stop bit c Click Connect in MTTTY or use the commands on one of the other terminal emulation programs to establish communication with the Cube STEP 3 Power up the Cube 9 36V DC by attaching the Molex type power connector leading from the bundled DNA PSU 24 a user supplied source or a daisychained line from another PowerDNA Cube Note that the DNA PSU 24 plugs into a 100 240V 50 60 Hz outlet Also note that the Cube does not have an On Off switch STEP 4 As soon as the Cube powers up it runs through self diagnostic mode and generates output on the termina
9. Access 5 4 Common Layer Interface 5 4 1 Channel List DNA PPCx PowerDNA Cube Manual Chapter 5 55 Programming Layer specific Functions on the back of the PowerDNA cube along with factory MAC address After the IP address is set the user can establish communication with the Pow erDNA cube using the PowerDNA Explorer See the Appendix for this information To show and set up the date and time use the time command as follows DO gt time Current time 17 39 22 11 01 2004 To set up time of the day enter DQ gt time 17 40 00 To set up date enter DQ gt time 11 03 2004 Date and time are stored in the battery backed real time clock chip The Common Layer Interface is the protocol used in a PowerDNA cube for communication between the IOM and its layers A channel list specifies what channels and in which sequence each should be acquired output Every layer has its own specific set of channel list flags The firmware takes care of this hardware dependency Please see the specific layer description to find out what channel list flags are supported Users should use the following flags generalized for all layers Channel list entries definition lower 16 bits are reserved for channel number gain and special module specific settings define DQ LNCL NEXT 1UL lt lt 31 channel list has next entry define DQ LNCL INOUT 1 define DQ LNCL SS1 ab define DQ LNCL SSO 1UL lt lt 28 subsystem lo
10. An introduction to the cube e Chapter 2 Installation and Configuration Provides instructions for installing and configuring the cube e Chapter 3 The PowerDNA Explorer Provides an overview of PowerDNA Explorer Main Window menu bar toolbar Device Tree setting panel IOM settings and Device layer set tings e Chapter 4 PowerDNA Core Module Describes the function and architecture of the CPU and NIC layers e Chapter 5 Programming Layer specific Functions Describes device architecture memory map startup sequence setting parameters updating firmware common layer interface Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap1 fm O lo 1 1 PowerDNA Overview O Copyright 2009 all rights reserved United Electronic Industries Inc DNA PPCx PowerDNA Cube Manual Chapter 1 Introduction Appendix Provides an overview of how to determine the version of PowerDNA update the firmware and configure the Ethernet card in various Win dows OS and Linux installations e Index Alphabetical listing of the topics covered in this manual NOTE Refer to the DAQBIOS Protocol Manual for detailed information about Host IOM Communication how DAQBIOS works the DAQBIOS Engine Real Time Operation with an IOM and Asynchronous Operation with an IOM Conventions To help you get the most out of this manual and our products please note that we use the following conventions Tips are designed
11. Authenticate IOM_22813 Enter user password to unlock IO module 10M_22813 Figure 3 6 Password dialog box for Store Config and Store All Configs Authenticate IOM_22813 xi Enter super user password to unlock lO module 10M_22813 Figure 3 7 Password Dialog Box for Update Firmware 3 2 3 View Menu Show Wiring Diagram is a friendly reminder of the connector pins for a specific layer All layers have this option and we display this one as an example The wiring diagrams in PowerDNA Explorer match the wiring diagrams in this man ual in the sections for each layer Copyright 2009 alll rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap3 fm DNA PPCx PowerDNA Cube Manual Chapter 3 30 PowerDNA Explorer Wiring Diagram x Al 201 37 pin D sub ar ee Alnts BEYER ains Alnto EJER Anz BAER Ans T Aln24 EJEA Aina Aln22 EEES ainio Aln23 ee ev EIE Aono Ki acno Figure 3 8 Example of a Wiring Diagram 3 2 4 Help Menu About PowerDNA Explorer shows the About box which shows the pro gram icon program name version number company name and copyright notice 3 2 5 Toolbar The toolbar contains the following buttons Scan Network Reload Config Store Config Store All Configs Read Input Data and Show Wiring Dia gram They duplicate the functionality of the corresponding menu items as described above 3 2 6
12. IOMs Cubes distrib uted throughout a process large piece of equipment facility or other structure 2 Cubes connected via copper or fiber optic cables to 3 a host PC with a dedicated Ethernet interface card and running Windows Linux or an RTOS Cubes may also be operated in stand alone data logger mode The PowerDNA Cube is available in either a 5 or 8 layer configuration Two of these layers are occupied by the Core Module The Core Module consists of the CPU Layer and the NIC network interface control Layer with connectors for either 100Base T copper or 100Base FX fiber optic cable The remaining 3 or 6 slots in the Cube are factory configured with your selection of I O Layers For information on these data acquisition layers visit www ueidaq com This document gives further details about the features and functions of various system components Details on programming the system are contained in the companion document s the PowerDNA API Reference Manual and various layer manuals Who should read this manual This manual has been written to make the installation configuration and opera tion of the PowerDNA cube as straightforward as possible However it assumes that the user has basic PC skills and is familiar with the Microsoft Win dows XP 2000 NT 9x QNX or Linux RTLinux RTAI Linux operating environ ments Organization of this manual This PowerDNA User Manual is organized as follows e Chapter 1 Introduction
13. TMR1 CLIN CV IN CL OUT CV OUT Start Trig Stop trig Time Stamp DqAdvAssignlsoDio selects direction level and connection between signals DqAdvSetClockSource DqAdvSet TriggerSource Figure 5 2 CM Interconnection Diagram e DIOO CLKIN pin 3 on the FJIO1 DB 37 connector By default this pin is an input connected to the ISO_EXTO synchronization line and through this line to the NIS logic e DIO1 TRIGIN pin 4 on the FJIO1 DB 37 connector By default this pin is an input connected to the ISO_EXT1 synchronization line and through this line to the NIS logic e DIO2 CLKOUT pin 22 on the FJIO1 DB 37 connector By default this pin is an output connected to the ISO_INTO line from the NIS logic The PowerDNA API exposes six specially designated functions to control these lines as follows Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Flecironic ndustnes Ine Date December 2012 File PowerDNA _Chap5 fm O Copyright 2009 all rights reserved United Electronic Industries Inc NOTE DNA PPCx PowerDNA Cube Manual Chapter 5 Programming Layer specific Functions DgAdvSetClockSource This function selects external clock source for CL or CV clock The clock can be selected from internal sources EXTx lines signals from the isolated side and SYNCx interface signals inputs DgAdvSetTriggerSource This function selects external clock sourc
14. is initially blank until you invoke Refresh Data unless auto refresh is activated in the preferences dialog The table has three columns e The unnamed first column contains the channel names e Name is a user defined string Value shows the current value A eee Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap3 fm DNA PPCx PowerDNA Cube Manual Chapter 3 PowerDNA Explorer 3 5 Counter We ll use the CT 601 as an example Timer Layer Settings 2 PowerDNA Explorer of x File Network View Help AONNE E Host PC a 0 CT 601 Info Counter Timer 8 units SIN 0021169 Mfg Date Jun 4 2004 Cal Date Jun 4 2004 v Enabled Counter 0 mode Quadrature w Start Min Gate Pulse Width 0 psec _ Input Pre inversion Min Clock Pulse Width 0 psec _ Gate Pre inversion _ Output Post inversion Relative Position counts Counter 1 mode Quadrature w Start Min Gate Pulse Width 0 psec _ Input Pre inversion Figure 3 22 Example CT 601 layer The CT 601 layer has 8 counters Each counter can be set to one of four differ ent modes Quadrature Bin Counter Pulse Width Modulation PWM or Pulse Period When you change the mode of a counter using the mode combo box the controls for that counter will change to those appropriate for the mode Counter 0 mode Quadra
15. 6 United Elecironie Indusines Inc Date December 2012 File PowerDNA _Chap2 fm 2 2 Initial Installation Start to finish Guide 2 2 1 Inspect the package 2 2 2 Install Software STEP 4 STEP 2 O Copyright 2009 all rights reserved United Electronic Industries Inc DNA PPCx PowerDNA Cube Manual Chapter 2 Installation and Configuration This section reviews how to perform an initial hardware and software setup when you first receive a PowerDNA Cube Inspect the contents of the shipping package With a standard PowerDNA Cube you should find e The PowerDNA Cube itself preinstalled with your selection of I O Lay ers e The DNA PSU 24 universal powerline brick which plugs into an outlet and provides 24V dc output The supply comes with a plug for the mains an adapter cable ending in a Molex connector for plugging into the DNA Cube and a daisychaining cable for supplying additional Cubes with power from the same supply max of three Cubes total e Serial cable for initial hardware configuration and firmware download ing e CD ROM with support software This section describes how to load the PowerDNA software suite onto a Win dows or Linux based computer and run some initial tests The latest PowerDNA support software is online at www ueidag com download a known working copy is also on the PowerDNA Software Suite CD A Software Install Windows 9x 2000 XP The PowerDNA CD provides two installers e Powe
16. File PowerDNA _Chap5 fm DNA PPCx PowerDNA Cube Manual Chapter 5 Programming Layer specific Functions Bit 28 Name DQ_CCR_EC1 DQ_CCR_ECO Description nable re load of the y the value loaded in when It reaches end of count End of count is limited by one of the combinations of DQ CCR_EC2 1 0 bits 30 DQ CCR EC2 Set end of count mode 0 0 000 DQ EM CRO end when it reaches CRO CR CRO 1 001 DQ EM CR1 end when it reaches CR1 CR CR1 2 010 DQ EM FFF end when it reaches OxFFFFFFFF 3 011 DQ EM PC end when X periods of the signal are captured X is defined via CTx_PC 0x2018 register In width 1 2 period measurement mode end when positive part of the input signal is captured 4 100 DQ EM TBR end when the time base counter reaches 0 Note All other modes are reserved for future use and will be recognized as a mode 0 Reset State 24 27 DQ_CCR_CRM3 DQ_CCR_CRM2 DQ_CCR_CRM1 DQ_CCR_CRMO O Copyright 2009 all rights reserved United Electronic Industries Inc Set counter mode 0x0 0000 DO_CM_CT counter CR acts as a standard count up counter 66MHz base clock used as a PS source 0x8 1000 DQ CM ECT counter CR acts as a standard count upcounter debounced CLKIN clock used as a PS source 0x9 1001 DO cM HP capture period mode CR captures Y period of the input signal starting from the rising edge of the de glitched input and copies it int
17. IP address If the computer sees a DHCP network connected to the Ethernet port it will use the primary IP configuration and negotiate an IP address with your company network as required If you are in the office and you want to check your email Plug in the Ethernet cable for your company s network connection into your computer and either power up your computer and log onto the network as you normally do or if your computer is already powered on perform a Windows Log Off and then a Log Or and log onto your company network as you normally do If you are working in the field with a PowerDNA cube or DNR 12 Plug in the Ethernet cable from the data acquisition system into your computer and make sure that the data acquisition system is powered on Then either power up your computer and bypass your network log on screens or if your computer is already powered on perform a Log Off and then a Log On and bypass your network logon screens A 2 Configuring a This section describes procedures for configuring a second Ethernet Card under Second Windows 2000 Ethernet Card The procedure is as follows Under Windows 2000 ES O Copyright December 2012 Tel 508 921 4600 www ueidaq com Vers 3 6 Y e Ad Date December 2012 File PowerDNA_Appendix fm A Set Up Your Ethernet Card NIC Windows 2000 will normally detect and install your Ethernet card and TCP IP automatically To check that your card has been installed run through the
18. amp 0xf lt lt 8 set gain LNCL GETGAIN E LNCL_GETCHAN E E EXTRACT SS flags EXTRACT DIR flags SS DIR ss dir s E amp Oxf00 gt gt 8 pull out gain amp Oxff pull out channel flags amp LNCL SS1 LNCL SSO gt gt 28 flags LNCL INOUT gt gt 30 s lt lt 1 dir The configuration flags serve various functions DQ _LNCL NEXT specifies that there is a following channel list entry in the channel list A channel list entry without this flag set is considered the last one Advanced and ACB functions add this flag automatically DQ _LNCL_INOUT specifies whether this is an input or output channel for mul tifunction layers DQ _LNCL S81 specifies the subsystem to which the channel belongs Do not use for single subsystem layers DQ LNCL Sso specifies the subsystem to which the channel belongs Do not use for single subsystem layers DQ _LNCL IRQ causes the layer to fire an IRQ upon processing this entry Required for special real time cases DQ LNCL NOWAIT causes the layer to temporarily forget about the CV clock and start execution of the next channel list entry right after the current one is completed DQ LNCL SKIP prohibits storing the data specified in this channel list entry into the data output FIFO or prohibits advancing the data input FIFO pointer This flag is used to increase the settling time DQ LNCL CLK causes the channel list machine to wait for the next
19. channel list clock Normally the state machine executes the whole channel list on a sin gle CL clock DQ LNCL CTR perform a pulse on the selected line This flag is used for syn chronization purposes DQ LNCL WRITE write the output to the double register but do not propagate the physical signal to the output DQ _LNCL UPDALL clock all output channel double registers to update them simultaneously This entry is usually used with the DQ_LNCL_ WRITE entry when the user needs to write data to the output channels sequentially and update them at the same time In this situation the user should use the DQ LNCL WRITE flag for every entry To update all outputs with previously writ ten values the DQ_LNCL_ WRITE flag should be combined with the DQ LNCL UPDALL flag Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap5 fm DNA PPCx PowerDNA Cube Manual Chapter 5 57 Programming Layer specific Functions DQ LNCL_TSRO insert a timestamp into the output data DQ _LNCL SLOW double the settling time for this channel DQ LNCL DIFF acquire the channel in differential mode rather than single ended or pseudo differential The channel number occupies the first eight bits of the channel list entry The maximum number of channels on one device cannot be larger than 256 Bits 11 8 contain gain information The number of gains and the gain are specific for every layer type See powerdna h for lay
20. e Name is a user defined string e In Out contains toggle switches to select whether the channel is to be used for input or for output 2 PowerDNA Explorer File Network View Help ee y lee BE tel x lom_20977 0 DIO 403 Model Info Sm a Mfg Date Cal Date DIO 403 D In Out 48 channel 6 ports of 8 0021391 Nov 30 0002 Nov 30 0002 Y Enabled Initialization 7 els 4 3 2 1 o Name Mode DICO Input Input Output Figure 3 19 Example DIO 403 Layer Initialization Initialization Shutdown tabs allow you to set a port as input or output and set output values They contain the following columns e The unnamed first column contains the channel names e Name is a user defined string Mode specifies whether the channel is input or output e 7 through 0 contain the values 0 or 1 They are checkmarks for output channels that allow you to select 0 unchecked or 1 checked Copyright 2009 all rights reserved United Electronic Industries Inc Tel 508 921 4600 Vers 3 6 Date December 2012 File PowerDNA _Chap3 fm www ueidaq com 39 DNA PPCx PowerDNA Cube Manual Chapter 3 40 PowerDNA Explorer 3 3 Analog We ll use the AO 302 as an example Output Layer Settings NOTE Use Network gt gt Rea
21. fre quency equal 6 875Hz 2 where n 0 9 To receive an exactly 500Hz data stream from this layer one should specify that this layer be updated upon a timer tick DQ LN _IRQEN use interrupts to retrieve data from the layer output buffer via packets This is preferable mode of operation Every I O layer has an E PROM chip that contains 2048 bytes of layer specific information Model and option numbers identify every layer The model number is hard coded inside layer logic and option numbers are stored inside E PROM E PROM is divided into certain access areas some of them can be missing in different layer types typedef struct DQEECMNDEVS ee DQCALSET xxx calset DQOPMODEPRM xxx _ opmodeprm DOINITPRM_ xxx initprm DQSDOWNPRM xxx _ sdownprm DQCNAMES xXxx_ cname DEVEEPROM xxx_ pDEVEEPROM xxx_ Copyright 2009 all rights reserved United Electronic Industries Inc The first part of the layer E2PROM is common device information defined as Tel 508 921 4600 www ueidag com Vers 3 6 Date December 2012 File PowerDNA _Chap5 fm typedef struct header is standard for all devices uint16 uint16 uint16 uin uin uin uin t32 t32 t32 t32 DNA PPCx PowerDNA Cube Manual Chapter 5 59 Programming Layer specific Functions superuser access model device model to verify EEPROM identity option device option total total EEPROM size EEPROM read is expensive
22. immediately CTO_ICR Bit description The ICR bits match IER ISR Tel 508 921 4600 Date December 2012 www ueidaq com Vers 3 6 File PowerDNA _Chap5 fm 71 DNA PPCx PowerDNA Cube Manual 72 A 1 Configuring a To configure a second Ethernet card for your system use the following Second procedure Ethernet Card Under Windows XP A Set Up Your Ethernet Card NIC If you already have an Ethernet card installed skip ahead to the next section Configure TCP IP If you have just added an Ethernet card to install it do the following STEP 1 From the Start menu select Control Panel and click Printers and Other Hard ware STEP 2 From the menu on the left click Add Hardware and follow the on screen instructions NOTE We recommend that you allow Windows XP to search for and install your Ethernet card automatically If Windows XP does not find your Ethernet card you will need to install it manually by following the manufacturer s instructions Once your Ethernet card has been installed continue to the next section B Configure TCP IP STEP 1 From the Start menu select Control Panel STEP 2 Under the heading Pick a Category click Network and Internet Connections STEP 3 Under pick a Control Panel icon click Network Connections STEP 4 If you see an icon under LAN or High Speed Internet heading for your second NIC skip ahead to step 10 STEP 5 If there is no icon under LAN or High Speed Internet for your s
23. isolates the cube from problems with the switch Straight through II Cross over X For a fast connection in the field you may connect a straight through cable to the NIC Out jack as shown below Use the NIC In jack to connect out to the LAN The reason that this works is that in the NIC Out jack the Rx Tx lines are SSS E ee ae Copyright 2009 alll rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 United lectronic industngs Ae Date December 2012 File PowerDNA _Chap2 fm DNA PPCx PowerDNA Cube Manual Chapter 2 24 Installation and Configuration crossed over for you so the wiring acts like a cross over cable for you Straight through Il I to LAN A crossover cable is the same as a straight through except the Rx Tx lines are inverted as shown below PC STRAIGHT THRU HUB PC CROSSOVER PC T1 1 Re TX 1 4 TX 2 TX 3 RX 4 5 6 RX TO 7 TX 2 GG 2 RX TX 2 RX 3 E 3 TX RX 3 4 D 4 4 5 HAS 65 5 RX G GE G TX RX 6 7 C_x See 8 3 R 8 NOTE The above configurations work with CM and PPC not FCM or FPPC when used in conjunction 8 wire Category 5 copper cabling i e CAT5 CAT5e less than 100meters in length and a 10 100Mbit NIC or switch Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Ine Date December 2012 File PowerDNA _Chap2 fm DNA PPCx PowerDNA Cube Manua
24. layer stores configuration data along with a user application user app is compiled on a host PC Updated firmware is periodically released to introduce new features and to improve the performance of existing features Updated releases of the firmware are bundled with the entire PowerDNA Software Suite available for download at any time from the UEI web site www ueidaq com CAUTION If you update the firmware in a Cube be sure to use the PDNA Explorer from the same release as that new firmware After installing the PowerDNA Software Suite browse to the installation s Firm ware directory e g C Program FileslUENPowerDNAlFirmware The directory may contain MTTTY updated firmware installation instructions Firmwarelnstall html and two sub directories containing the firmware Choose the sub directory corresponding to the architecture of your cube ColdFire CF CM with extension S19 or PowerPC PPC with extension MOT Determining the version of your PowerDNA cube with PDNA Explorer Before updating the firmware of a PowerDNA cube check the cube version to determine which update method to use a Supply power to the PowerDNA cube Connect the PowerDNA cube to its network c Start PowerDNA Explorer on the Microsoft Windows desktop from Start gt gt Programs gt gt UEI gt gt PowerDNA gt gt PowerDNA Explorer d Choose Network gt Scan Network e Select the PowerDNA cube you wish to query by clicking the cube
25. of samples available in the output FIFO of the CTUO 0x1818 0x203C RD CTO_FDTO CTUO Output FIFO Data Input Register 32 bit read only register for the input FIFO 0x2040 WR CTO_IER CTUO Interrupt Enable Register Interrupt generation unit in every CTU is similar to the IGU in PDNA CLI logic except it does not have interrupt mask register for the simpler operation Inter rupt from any of the available sources if enabled latched in ISR 0x2040 RD Interrupt Status register and forces IRQ request into logic HIGH state IRQ line remains in HIGH state until all IRQ requests are cleared via ICR 0x2044 WR Interrupt Clear Register The IER register is a bit field in which each bit enables one interrupt source The following are the CTO_IER Bit descriptions Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap5 fm DNA PPCx PowerDNA Cube Manual Chapter 5 Programming Layer specific Functions Bit Name Description Reset State 31 DQ_IR_CPT Request interrupt if counter completes current 0 operation 30 DQ_IR_CROL Request interrupt if current value of CR lt CRO 0 29 DQ_IR_CROGE Request interrupt if current value of CR gt CRO 0 28 DQIR_CR1 Request interruptif current value ofCR gt CR4 o0 27 DQ_IR_LHI Request interrupt if low high transition was detected 0 on the input pin deglitched 26 DQ_IR_LHG Request interrupt if low high transitio
26. read write DQ_CTU_CR Count Register Current value of the count register read DQ_CTU_LR Program Load Write access sets new value of the load register LR also copying Register the same value into the count register CR write DQ_CTU_IDBC Clock Debouncing Program input clock debouncing register IDBC CTU will expect Register input clock to remain stable for the specified number of 66MHz clocks before processing qualifying it write DQ_CTU_IDBG Gate Debouncing Program input gate debouncing register IDBG CTU will expect Register input gate line to remain stable for the specified number of 66MHz clocks before processing qualifying it write DQ_CTU_PC Period Count Period count register PC is used in ameasurement modes when Register averaging for the multiple periods is required because of the high speed or unstable nature of the incoming signal Results of the measurement are accessible only after specified number of periods on the incoming signal are detected read write DQ_CTU_CRH CTU Capture Read Provide access to the capture register high Write Set value DQ_CTU_CRO Register High of the compare register 0 read write DQ_CTU_CRL CTU Capture Read Provide access to the capture register low Write Set value DQ_CTU CRA Register Low of the compare register 0 read write DQ_CTU_TBR Time Base TBR defines time base divider for the time based capture modes Register Bit 31 MSB of the TBR write DQ_CTU_FCNTI Input FIFO Count CTU Inp
27. the CV clock determines the delay between converting channels i e setting time IS Isolated Side DQ LN STRIGEDGEO DQ LN STRIGEDGE1 define the start trigger edge and source The source can be either software command or external trigger edge DO LN PTRIGEDGEO DQ LN PTRIGEDGE1 define the stop trigger edge and source The source can be either software command or external trigger edge DQ LN _TSCOPY copy timestamp at the end of every channel list DQ _LN MAPPED set this flag to declare DMap mode DQ LN STREAMING set this flag to declare ACB mode DQ LN RECYCLE this flag affects output operation If this flag is set and layer does not receive output data it will recycle old data until new data is available otherwise the layer will stop at the last value output DQ LN GETRAW tells the layer to return uncalibrated unconverted data This flag makes sense only for layers with software calibration Al 225 for example Moving calibration and conversion of data to host unloads IOM processor DQ LN _TMREN use a real time timer to retrieve data from the PowerDNA cube When this mode is selected the firmware programs the layer to store one channel list worth of data in the buffer On a timer tick the firmware transfers this data from the layer output buffer to the packet This function is used when the hardware allows only a selected set of update rates but the user needs something in between For example Al 225 can convert data with fixed
28. the channels e Name is a user defined string e 7 through 0 contain the values 0 or 1 For the output tab they are checkmarks for output channels allowing you to select 0 unchecked or 1 checked olx Hast PC lom_20977 lt 0 DIO 403 2 PowerDNA Explorer File Network View Help ofa G 6 e DIO 403 Info D In Out 48 channel 6 ports of 8 SIN 0021391 Mfg Date Nov30 0002 Cal Date Nov 30 0002 vi Enabled 7 6 5 4 3 2 1 0 DIOD oe a OOO DIO1 DIO2 DOMINO DIO3 OOOO DIO4 m a DIOS OJD olx Host PC lom_20977 0 DIO 403 Copyright 2009 all rights reserved United Electronic Industries Inc AQ f Info D In Out 48 channel 6 ports of 8 SIN 0021391 Mfg Date Nov 30 0002 Cal Date Nov 30 0002 Vi Enabled Configuration DIOD O DIO1 10 DIO2 Oo DIO3 O DIO4 oO DIOS O Figure 3 18 Example DIO 403 Layer Configuration Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap3 fm 38 DNA PPCx PowerDNA Cube Manual Chapter 3 PowerDNA Explorer Configuration tab gets sets the current input output directions per port It con tains the following columns e The unnamed first column contains the channels
29. using the optional DIN rail clip DNA DR A nor connections mal DIN rail comes with screws you can use to mount the rail onto another sur face or piece of equipment However because the Cubes are designed to fit into applications where space is at a premium it may sometimes be difficult to attach the rail in this way For such cases we include a special adhesive tape for attaching the rail to any desired surface CAUTION Take care when deciding on which surface you plan to mount a Cube For example using the adhesive strip you can normally attach the DIN rail to a wall without causing any damage as shown below unless the wall has a sensitive coating such as delicate paint or wallpaper HS NIC In NIC Out Pe ace 1 gs A ih im 1 aro sae of DO 50 Card HE wor ROY STS RO E IEC e ROY STS ROY STS EA EEE ae Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Ine Date December 2012 File PowerDNA _Chap2 fm DNA PPCx PowerDNA Cube Manual Chapter 2 23 Installation and Configuration 2 4 Wiring 100BaseTX 100BaseFX Wiring Configurations Typical wiring configurations for 100BaseTX 100BaseF X networks are shown in the following figures Cubes may also be connected with standard straight through lines through a switch Alternatively a cross over cable may be used to directly connect to a cube as shown below This improves performance and
30. A Explorer Demo The demo is just a simulator for users without cubes or for new users who want to explore the PowerDNA Explorer program without reading writing to real hardware Run this program and hover your mouse over the buttons to read the tool tips and learn through interacting with the program Some quick notes MVI Touse the layer the Enabled check box should be set VI To read from a layer click the second to last button Read Input Data MI Towrite to the layer change the value and click the third or fourth button with the red arrow on top of the cube Store Configuration The cube with the blue arrow above it restores the configuration M To change the IP change the number deselect the field and Store Configuration Take care not to set the IP Address to outside of the network s configuration subnet or to an IP address that is currently in use as the cube will then become unreachable See Chapter 3 PowerDNA Explorer for additional information and instruction SSS E ae Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Ine Date December 2012 File PowerDNA _Chap2 fm 2 2 7 Updating Firmware O Copyright 2009 all rights reserved United Electronic Industries Inc DNA PPCx PowerDNA Cube Manual Chapter2 19 Installation and Configuration Firmware in a PowerDNA Cube s CPU
31. Chapter 5 51 Programming Layer specific Functions name IOM 22811 model 0x1005 serial 0022811 mac 00 0C 94 00 59 1B fwct 1 2 0 0 srv 192 168 0 229 ip 192 168 0 67 gateway 192 168 0 1 netmask 255 255 255 0 udp 6334 This command displays current values of every major PowerDNA cube parame ter To change parameters use set command type set for set command syn tax DQ gt set Valid set options name lt Device name gt model lt Model id gt serial lt Serial gt mac lt my ethernet address gt fwct lt autorun runtype portnum umports gt srv lt Host IP address gt ip lt IOM IP address gt gateway lt gateway IP address gt netmask lt netmask IP address gt udp lt udp port dec gt For example to set a new IP address type DQ gt set ip 192 168 100 100 DO gt store Flash 1212 bytes of 1212 stored Other parameters can be changed the same way Once parameters are set however you have to store them into non volatile flash memory CRC 0x8975E34A Old 0x8975E34A Configuration stored DO gt DQ gt reset Stopping DaqBIOS C UEI Built on 16 39 15 Oct Initialize uC OS II After parameters are stored the you should reset the firmware start firmware execution from the beginning without full hardware reset 2001 2004 Running PowerDNA Firmware 1 2004 Real Time Kernel v 252 Configuration recalled 3 device detected Copyright 2009 all rights r
32. Cube Manual Chapter 3 32 PowerDNA Explorer MAC shows the MAC address It cannot be changed and thus is informational only IP Address shows the IP address of the IOM It can be changed Mode shows the mode the PowerDNA cube is in nitialization Configuration Operation or Shutdown These modes are described in the section OM Modes See A ee et ee E AA A NN ae et Copyright 2009 alll rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap3 fm 3 2 7 2 Device Layer Settings 2 PowerDNA Explorer File Network View Help DNA PPCx PowerDNA Cube Manual Chapter 3 33 PowerDNA Explorer Figure 3 1 shows the screen for displaying device layer settings Ox MOOIE Host PC g 10M_19675 8 lom_20977 lt 0 Al 201 lt 1 Al 201 lt 2 Al 201 lt 3 Al 201 Copyright 2009 all rights reserved United Electronic Industries Inc Model Al 201 Info A In 24 channel SIN 0022432 mfg Date Aug 1 2004 Cal Date Aug 17 2004 Z Enabled Figure 3 11 Example of Device Layer Settings for a Layer Each layer has the following settings e Model shows the model number of the layer Info shows some key features of the layer A for analog D for digital In for input Out for output and a number of channels available e S N shows the layer s serial number e Mfg Date sho
33. Cx PowerDNA Cube Manual Chapter 1 Introduction family from the ground up to provide the best possible features reliability and performance at an economically sound price 1 1 1 What s inthe Inspect the package Included you should find Package The PowerDNA Cube Preinstalled with your selection of I O Layers Power supply DNA PSU 24 100 240V 50 60Hz to 24VDC Ethernet cable with either RJ 45 connector for copper or SC type for fiber optic 100 Base FX cable ES qn Serial cable for initial configuration Additional accessories may be included depending on your order 1 2 Overview The PowerDNA system consists of a hardware Cube and software suite The software suite is located both on the PowerDNA PowerDAQ CD shipped with the Cube and on the website www ueidaq com The software that supports the system consists of two components PowerDNA low level driver a PowerDNA Explorer and a PowerDNA Software Suite demo Example code for C amp Java Additional example code amp docs DLL Fi for UEIDAQ Framework C C C VB NET ActiveX VB6 Del phi MATLAB LabVIEW DASYLab LabWindows CVI OPC The Windows PowerDNA Software Suite contains the following software PowerDNA low level driver The interface between the cube hardware and higher level languages AA U u eS tl Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 united Elect
34. Device Tree When the application is first launched the tree contains just a root item repre senting the host computer When you select Scan Network from the Network menu or the toolbar the device tree gets populated with all central controllers IOMs and device layers accessible from the network as filtered through the Network Ranges dialog Central controllers if any appear as children of the Host PC item IOMs that are connected to the PC without use of a central con troller also appear as direct children of the Host PC item Each item has an icon indicating whether it is a central controller IOM or layer The text label for each item is the device s model number name and serial Copyright 2009 alll rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap3 fm 3 2 7 Settings Panel 3 2 7 1 IOM Settings 2 PowerDNA Explorer File Network View Help DNA PPCx PowerDNA Cube Manual Chapter 3 PowerDNA Explorer number Layers are also labeled with their layer number in parentheses Host PC g 10M_19675 lOM_20977 lt 0 Al 201 1 Al 201 lt 2 Al 201 3 Al 201 Figure 3 9 Example of the Device Tree When an item is selected in the tree the settings panel changes to reflect the settings for that device The first time an item is selected the device is queried as though you had invoked the Read command On subsequent selection
35. Explorer Quick Start 000 00 cee eee 17 2 2 8 Firmware Update Instructions 0 0 0 0 0 ccc cee ee eee 20 2 3 Mounting and field connections 00 eee 22 2 5 Peripheral Terminal Panel Wiring 2 02 eee eee eee eens 25 Chapter 3 PowerDNA Explorer 000 e eee eee 26 3 1 Whe Main WiINdOWes lt a al ee ale Weed dk toda decker ied ana etek 26 3 2 Menu Ball cans cdots Suna Ee ae le Bt A leiden Oe ae 26 3 2 1 Ele Mentir Es ta A a A a o EE IE eC A e AR 26 3 2 2 Network MeN it ss a ee ee Oe LA eae at oa 26 3 2 3 VIEW Mentes tsa ran cates asus Do lr ents eam E EA Ora ye aa ek 29 3 2 4 Help Menu ec 52 2344 a eee Be eee eee ee eid 30 3 2 5 MOOIDARS feral A O Se anh kn E cee a edie OS 30 3 2 6 DEVICE Tre 200 A ee ata aE aa rant ALE een Soe curt tel lata 30 3 2 7 Settings Fanell reyr ane e EEE e a NE e Raha aia 31 3 2 8 Digital Input Output Layer Settings 0 0 0 00 00 cee 34 Chapter 4 The PowerDNA Core Module 0 cece cece eee eee eens 45 4 1 Device Architecture of DNA CM 0 0 000000 earki fp alee ee ee 46 4 1 Device Architecture of DNA PPC 00 0000000 cece eee 47 Chapter 5 Programming Layer Specific Functions 00ee eee eeeee 48 5 1 OVENVICW ck clei Bane da da nA Se aa es aly hehe ag a Nats baie oh apn Ae 48 5 2 Memory Maps vest es A bates eee ee a adie egy 48 5 2 1 Startup sequence DNA CM 5 8 00 0 0 eee 49 5 2 2 Startup Sequence DNA PPC 5 8
36. I O Layers 5 8 x 4 1 x 4 0 Core Module 2 layers at the top The CPU Layer PowerPC Coldfire Integrated CPU with real time kernel in firmware Cube can operate as a standalone unit The NIC Layer 100BaseT Fiber 100 Base FX Can Link cube to any PC over commercial Ethernet Daisychain 64 Cubes over one Ethernet network Optional O layers refer to www ueidaq com for details Resolutions to 24 bits read write to a Cube s I O Layers every 1 msec Analog Input High gain amp low gain Strain Gauge module Simultaneous Sampling module Analog Output with optional current voltage booster add in card Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap1 fm DNA PPCx PowerDNA Cube Manual Chapter1 5 Introduction e Controller Area Network CAN Bus layer e Counter Timer e Digital I O e Power Conversion layer Chapter 2 details the configuration and operation of the cube s Core Module Chapter 4 details the behavior and architecture of the cube s Core Module Detailed information on the hardware layers is found in the layer specific manu als and on the website www ueidaq com See e A A A E AA A NN NN a TES O Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 Ynited PIE e Date December 2012 File PowerDNA _Chap1 fm DNA PPCx PowerDNA Cube Manual Chapter 1 Introduction 1 3 Specifi Figure 1 1 lists the Technical Specifications for the
37. M2 COM3 then hit Connect and press Enter Reboot the cube The start up screen should display upon restart If all else fails contact UEI support at support ueidaq com XK REKEKRKKE EE Type show to verify the Cube s IP Subnet Mask and Gateway AAA A ae Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 united Electronic Indusintes Ine Date December 2012 File PowerDNA _Chap2 fm 2 2 6 PowerDNA Explorer Quick Start STEP 4 DNA PPCx PowerDNA Cube Manual Chapter2 17 Installation and Configuration M Ensure that the computers are on a valid subnet and have valid IPs Mi Finally contact UEI for support at support ueidaq com PowerDNA Explorer does just what its name implies it explores the LAN looking for connected PowerDNA Cubes Chapter 3 covers the PowerDNA Explorer in detail This section page only provides a quick start guide The PowerDNA Explorer identifies PowerDNA Cubes on a selected network the discovered Cubes are listed on the left hand side pane Select a cube to display pertinent hardware and firmware information Select a layer of a specific cube to manipulate its inputs or outputs In brief this useful tool lets you verify that the Cube is communicating with the host and that the I O Layers are func tioning properly To scan the network for PowerDNA Cubes provide a set of addresses to scan Do the following Select Network gt gt Address Ranges
38. MB EXT_DEV_ADDRESS2 Layer CS3 0xA0100000 OxAFFFFFFC 256M EXT_DEV_ADDRESS3 Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries ne Date December 2012 File PowerDNA _Chap5 fm 48 DNA PPCx PowerDNA Cube Manual Chapter 5 Programming Layer specific Functions 49 Start Device Address End Address Size Description SDRAM 0x0 0x8000000 128MB SDRAM_ADDRESS Flash OxFFCO0000 OxFFCOFFFF 64kB Parameters 64 sectors parameters Flash firmware OxFFC10000 OxFFEFFFFF 3MB Firmare 3MB 64kB Falsh U Boot OxFFFO0000 OxFFFFFFFF 1MB U Boot 5 2 1 Startup sequence DNA CM 5 8 Two address ranges are interesting for host software Layer Address Space 0xA0000000 OxAOOFFFFC and 0xA0100000 OxAFFFFFFC The first address range is dedicated to devices located on CS2 line and accommodates sixteen layers with 64k memory map each The second address range is designated for fast devices located in CS3 line and it accom modates fifteen devices with 16MB memory map each After reset the processor starts monitor execution from flash memory The monitor initializes the processor and the address map retrieves information from the parameter sector of the flash memory and tests system memory and other system resources If fwgo parameter is set to autorun the monitor waits for three seconds for the user to send Ctrl A whi
39. NA Cube Manual Chapter 5 53 Programming Layer specific Functions Using the serial interface you can set up the following parameters lt Device name gt lt Model id gt lt Serial gt lt my ethernet address gt lt autorun runtype portnum umports gt lt Host IP address gt lt IOM IP address gt lt gateway IP address gt lt network mask gt lt udp port gt Name sets the device name up to 32 characters Model sets the device model factory programmed do not change Valid val ues are 0x1005 100 Base T five layer PowerDNA cube 0x1008 100 Base T eight layer PowerDNA cube 0x1105 100 Base FX fiber optics five layer PowerDNA cube 0x1108 100 Base FX eight layer PowerDNA cube Serial sets the PowerDNA cube s serial number factory programmed do not change MAC sets the PowerDNA cube s MAC Ethernet address factory pro grammed do not change fwct defines the behavior of the monitor upon boot up Valid values for auto run are zero stay in monitor after initial boot sequence or one copy firm ware to SDRAM memory location and execute from there Valid values for runtype are TYPE_lOM 2 TYPE_AUTO 4 and TYPE_SA 8 For normal operation use TYPE_IOM portnum and umports parameters are reserved in the current release and should be set to zero Srv sets the host IP address You have to set the host IP address only if raw Ethernet prot
40. Overview STEP 1 Install the PowerDNA software suite The latest software suite can be found online at www ueidag com download a copy is also included on the CD STEP 2 Connect the serial cable from Cube RS 232 port to the host computer serial port a Starta TTY client Start gt gt Programs gt gt UEI gt gt PowerDNA gt gt MTTTY b Change the Baud rate to 57600 and Click Connect STEP 3 Connect the power supply to the Cube STEP 4 The Cube comes pre configured with an IP address Using MTTTY type Enter to test the prompt for Coldfire DQ gt for PPC gt Then type DO gt show ip 192 168 100 2 netmask 255 255 255 0 STEP 5 optional The recommended method of connection to the Cube is via a direct Ethernet cable connected to an external NIC Connecting the cube directly to a LAN usually requires a change of IP address on the Cube For example your system administrator has assigned you the unused IP 192 168 0 65 Here is how to change the IP to this example IP DQ gt set ip Sets this Cube s IP to 192 168 1 10 192 168 0 65 Saves the newly changed configuration DQ gt store Reboots the cube for the new IP to take DO gt reset effect To make sure that the PowerDNA Cube is alive ping it C gt ping n 1 192 168 0 65 STEP 6 Use PowerDNA Explorer for graphical configuration see Chapter 3 A Se A ra a A a a a e a O Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3
41. PowerDNA PPCx Cubes cations Technical Specifications Standard Interfaces To Host Computer 10 100Base T standard RJ 45 connector Daisy chain output 10 100Base T standard RJ 45 connector Config General RS 232 9 pin D Sync Custom cable to sync multiple cubes DNA PPC8 6 slots DNA PPC5 3 slots Host Communications Distance from host 100 meters max CAT5 cable Ethernet data 2 megabyte per second transfer rate Analog data up to 1 megasample per sec 16 bit samples transfer rate DMAP I O mode update 1000 1 0 channels analog and or digital in less than 1 millisecond guaranteed CPU Freescale MPC5200 400 MHz 32 bit Memory 128 MB not including on board Flash Memory which contains OS kernel 1 O driv ers and firmware Status LEDs Attention Read Write Power Communications Active Environmental Temp operating Tested to 40 C to 85 C Temp storage 40 C to 100 C Humidity 0 to 95 non condensing Vibration IEC 60068 2 64 10 500 Hz 5 g rms Broad band random IEC 60068 2 6 10 500 Hz 5 g Sinusoidal Shock IEC 60068 2 27 50 g 3 ms half sine 18 shocks at 6 orientations 30 g 11 ms half sine 18 shocks at 6 orientations Altitude 70 000 feet maximum Physical Dimensions DNA PPC5 4 1 x 4 0 x 4 0 DNA PPC8 4 1 x 4 0 x 5 8 Power Requirements Voltage 9 36 VDC AC adaptor included Power Dissipation 4 W at 24 VDC not including I O boards
42. RS bit is cleared and triggered mode is selected DO_CM_Txx 21 DQ_CCR_ENC This bit complements DO_CCR_TRS bit and works only in a triggered mode if set 1 enables auto clear of the DQ_CTR_EN bit at the end of the current operation 5 6 1 Valid EM CM Combinations Refer to the table below for the possible EM CM combinations x valid mode for Non Buffered Modes o WL Xx 5 5 E e E a 7 nl 7 a a e a Notes DQ_CM_CT Xx X X x Use DQ _EM CRO for single clock pulse DQ_CM_ECT generation DO_EM_ CR1 for PWM mode DQ_CM_TCT DQ_EM_FFF for wrap around counter DQ_CM_TECT DQ_CM_HP xX DQ_CM_NP DQ_CM_THP DQ_CM_TNP DQ_CM_QE x x x x For continuous non buffered operation of QE it is recommended you use DQ_EM TBR mode but disable timebase counter by writing 0x1 to TBR Copyright 2009 all rights reserved United Electronic Industries Inc 0x2008 WR CTO_PS CTUO Prescaler Set value of the pre scaler Prescaler is a 32 bit count down counter output of which is used to clock counter register CR Source for the prescaler is auto matically selected based on current value of the CCR_CRMx bits Note that if Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap5 fm 68 O Copyright 2009 all rights reserved United Electronic Industries Inc DNA PPCx PowerDNA Cube Manual Chapter 5 69 Programming Layer speci
43. UPPORT DEVICES OR SYSTEMS Products sold by United Electronic Industries Inc are not authorized for use as critical components in life support devices or systems A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Any attempt to purchase any United Electronic Industries Inc product for that purpose is null and void and United Electronic Industries Inc accepts no liability whatsoever in contract tort or otherwise whether or not resulting from our or our employees negligence or failure to detect an improper purchase NOTE Specifications shown in this document are subject to change without notice Check with UEI for current status Table of Contents Chapter 1 Introduction 00occcccccc eee eee eens 1 1 1 PowerDNA Overview 0 0000 0c ee ee ee 2 1 1 1 What s in the Package 1 1 eae 3 1 2 OVERVICW i adaa dd St diac wees ds dd Artes a dh dah inane 3 Chapter 2 Installation and Configuration 000 cee ee 8 2 1 Initial Installation Overview 0 00000 00000 ee eee 8 2 2 1 Inspect the packages ici a oe ety dt tena Dated wad 9 2 2 2 Install SottWare uo dt SAS ed Bae ed ete eo ads wih ees 9 2 2 4 IP Addresses on the PowerDNA Cube 0 00000 e eee eee 12 2 2 5 Improving Network Performance 0 00 e eee tee 13 2 2 6 PowerDNA
44. United ES Electronic Y Industries The High Performance Alternative DNA PPCx PowerDNA Cube Manual December 2012 Edition PN Man PPCx 1212 Version 3 7 O Copyright 1998 2012 United Electronic Industries Inc All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without prior written permission Information furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringements of patents or other rights of third parties that may result from its use All product names listed are trademarks or trade names of their respective companies See UEl s website for complete terms and conditions of sale http www ueidaq com company terms aspx Contacting United Electronic Industries Mailing Address 27 Renmar Avenue Walpole MA 02081 U S A For a list of our distributors and partners in the US and around the world please see http www ueidaq com partners Support Telephone 508 921 4600 Fax 508 668 2350 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidaq com Web Site www ueidaq com FTP Site ftp ftp ueidaq com Product Disclaimer WARNING DO NOT USE PRODUCTS SOLD BY UNITED ELECTRONIC INDUSTRIES INC AS CRITICAL COMPONENTS IN LIFE S
45. WM controls o ooooocnnnnnnincnnnnnncconnnnnnnnncancnrcnnnn nn 43 3 26 Example Pulse Period controls ooooocionninnncccccnccncccncccccononnnnonnnnnonncnnnnnnnnnnnnnnnnnnnn nn nnnnnn 43 3 27 Example of Started Counter sera a a aea aa ae nEaN 44 Chapter 4 The PowerDNA Core Module 000 0s cece eee eee eee 45 4 1 PowerDNA Core Module CPU and NIC 0occcccconooccccccnononcnononanoncnononano canario naar o ncnrcnnnnnno 45 4 2 FreeScale ColdFire Controller Architecture cccccecceceeeeeeeeeeeeeceecaeeeeeeeeeeeeeeeees 46 4 3 PowerPC Controller Architecture ooooooocncccccccnnnnncononccnncnnononcnnnnnnnnn no nnnnnnnnnnnnnnnnnnnns 47 Chapter 5 Programming Layer Specific Functi0NS ooooooroooocron 48 5 1 Changing the IP Address 2 ini aie end Gin nea a ees 54 5 2 CM Interconnection Diagram es ssena aan A EEE AAEE 60 Chapter 1 O Copyright 2009 all rights reserved United Electronic Industries Inc DNA PPCx PowerDNA Cube Manual Chapter 1 Introduction Introduction This document is intended to serve as a user manual for a PowerDNA Cube system lt describes the PowerDNA Cube Distributed Network Acquisition sys tem its components specifications and instructions for set up and operation PowerDNA is the umbrella name that describes a real time distributed I O sys tem with exceptional flexibility and performance PowerDNA system consists of three parts 1 Input Output Modules a k a I O Modules
46. a LAN where e High sampling rate is not necessary e Some samples may be dropped due to network congestion and colli sions The cube should be accessible by multiple parties on the LAN e Multiple Cubes operate and interact on the same network Alternatively if you plan to use the Cube for high speed measurements where reliability is necessary a direct connection between the host PC and a NIC is recommended For a direct connection see the following section Improving Network Performance How to change the IP Both PowerDNA Explorer and a terminal emulation program can change the IP Consult your system or network administrator to obtain an unused IP Let s say for example that your system administrator assigns you the IP 192 168 0 65 To change the IP from the terminal program enter the following commands 1 NIC Network Interface Controller a commercially available Ethernet i e IEEE 802 3 adapter Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap2 fm DNA PPCx PowerDNA Cube Manual Chapter2 13 Installation and Configuration DQ gt set ip Sets this Cube s IP to 192 168 0 65 192 168 0 65 The default password is powerdna Enter user password gt powerdna Saves the newly changed configuration DQ gt store Reboots the cube for the new IP to DQ gt reset take effect You can set any parameters listed with the show command in this manner C
47. aixi General r Connection Status Connected Duration 02 25 00 Speed 10 0 Mbps r Activity sent SF Received Packets 7e8 458 A Properties Disable Close STEP 4 Click once on Internet Protocol TCP IP Then click Properties 21 General Connect using E3 AMD PCNET Family PCI Ethernet Adapter Components checked are used by this connection A a MY Intemet Protocol TCP IP eet Instal Uninstall Properties ES O Copyright December 2012 Tel 508 921 4600 www ueidaq com Vers 3 6 Y e Ad Date December 2012 File PowerDNA_Appendix fm DNA PPCx PowerDNA Cube Manual 78 STEP 5 Select Use the following IP address and type 192 168 100 1 In the Subnet mask box type 255 255 255 0 Leave the Default Gateway box blank Internet Protocol TCP IP Properties 2x General YS pera IP addons EEEE Suhr mash SS arse A Dein orteriny ara STEP 6 6Select Use the following DNS server addresses and Make sure the Preferred DNS server box and the Alternate DNS server boxes are blank m Se server addresses 4 STEP 7 Click OK click OK in the TCP IP Properties window click OK in the Local Area Connection window and click Close in the Local Area Status window STEP 8 Close the Network and Dial up Connections window A 3 Configuringa A Set Up Your Ethernet Card NIC Second If you installed your Ethernet interface before or at the same time as you Ethernet Card installed Windows NT then the system s
48. al start trigger is selected DQ LN PTRIGEDGE1 external stop trigger is selected If internal sources are selected for those signals all external signal configura tions do not affect layer clocking The same interface applies to the CPU layer The CPU layer has one external input and one output routable to the SYNCx interface as well as multiple clocks It is possible to include an IEEE 1588 implementation with an atomic clock 1us resolution in the future Tel 508 921 4600 www ueidag com Vers 3 6 Date December 2012 File PowerDNA _Chap5 fm DNA PPCx PowerDNA Cube Manual Chapter 5 Programming Layer specific Functions 5 5 Register Map All CTU registers are located at addresses starting at Base DO_CLI_CTUXS and where x is the CTU number 0 7 The I O FIFO uses the standard PowerDNA Description FIFO locations starting at Base 0x1800 Register Offset Name Description DQ_CTU_STR CTU status Counter timer status register contains status bits related to CTU register functionality read DQ_CTU_CTR CTU control Counter timer control register contains control bits related to CTU register functionality write DQ_CTU_CCR CTU counter Counter timer Counter Control register defines mode of the control register operation of the counter and prescaler write DQ_CTU_PS Prescaler Divider Program prescaler divider PS default value 0 and read back current value of the prescaler counter
49. apter in the host PC Let s also assume that host IP address on this dedicated network is IP address 192 168 100 28 Network mask 255 255 255 0 Gateway ignored DNS ignored Internet Protocol TCP IP Properties General You can get IP settings assigned automatically if pour network supports this capability Otherwise you need to ask your network administrator for the appropriate IP settings Obtain an IP address automatically IP address 192 168 100 28 Subnet mask 255 29 20 0 Default gateway E Obtain DNS server address automatically Use the following DNS server addresses Preferred DNS server a E Advanced Alternate DNS server Figure 5 1 Changing the IP Address Set PowerDNA cube address to any address in the range of 192 168 100 1 through 192 168 0 254 excluding 192 168 100 28 the host IP address For example type DO gt set ip 192 168 0 2 Then DQ gt store This sequence of commands stores a new IP address in the flash parameter sector Then you have to reset the PowerDNA cube PowerDNA cubes come from the factory with IP addresses already preset for 192 168 x x network The factory IP address can be found on the label located Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap5 fm 5 3 How to Update Firmware 5 3 1 Clock and Watchdog
50. assword before calling these functions The PowerDNA API Reference Manual notes which functions are password protected Another useful command is devtbl This command displays all I O layers found and initialized by firmware along with assigned device numbers Use these device numbers in host software to address these devices Priority tells in which order device drivers are located in the device stack A device with a lower priority number receives a shared interrupt first The firm ware sets up device driver priorities when it registers device drivers simod is a command for system initialization and module calibration simod 0 is used to initialize initial layer parameters serial number option etc We do not recommend use of this command in the field simod 1 allows layer calibration Different layers have different calibration procedures explained in respective sections of this document simod 3 allows you to perform factory tests this is a non destructive com mand WARNING Once you use the simod 0 command the layer warranty is void Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 United Electronic Industries Ine Date December 2012 File PowerDNA _Chap5 fm 5 2 4 Setting Parameters name model serial mac fwet srv ip gateway netmask udp Copyright 2009 all rights reserved United Electronic Industries Inc DNA PPCx PowerD
51. bit register is used to store results of the measurements in N period mea surement modes In N periods N is defined by the value stored in the PC reg ister measurement mode provides accumulated number of 66MHz counts during the negative low part of all periods measured 0x2020 WR CTO_CR1 CTUO Set Value of the Compare Register 1 32 bit compare register one CR1 is used to define shape of the output signal In all modes except quadrature encoder and measurement modes counter reg ister CR counts up from the value loaded in LR register and output toggles from low to high when CR CRO then output stay high until CRO lt CR lt CR1 Depending on the other configuration parameters selected counter may con tinue count restart itself or stop when the value of the CR reaches the value stored in CR1 register CR1 may be used in conjunction with CRO for the com plex PWM waveform generation 0x2024 WR CTO_TBR CTUO Time base Divider Register 32 bit TBR write only register defines time base divider for the time based capture modes 0x1800 0x2028 RD CTO_FCNTI CTUO Input FIFO Count Register 9 bit LSB valid return number of samples available written from the host to layer in the input FIFO of the CTUO 0x1808 0x2030 WR CTO_FDTI CTUO Input FIFO Data Input Register 32 bit write only register for the input FIFO 0x1810 0x2034 RD CTO_FCNTO CTUO Output FIFO Count Register 9 bit LSB valid returns number
52. c Indusintes Ine Date December 2012 File PowerDNA _Chap2 fm DNA PPCx PowerDNA Cube Manual Chapter 2 Installation and Configuration Ethernet adapter NIC1 Local Area Connection Connection specific DNS Suffix IP Address 192 168 1 10 Subnet Mask 255 255 255 0 Default Gateway 192 168 1 1 Linux users can use the more verbose ifconfig command instead Here the subnet range 192 168 1 0 192 168 1 255 is being used by NIC1 IP Addressing The range of usable addresses is defined by the IP address and subnet mask An IP address is a number that is split into the range of 0 0 0 0 and 255 255 255 255 Here the IP address is 192 168 1 10 The subnet mask indicates where an address stops For example a subnet mask 255 255 255 240 has 15 usable addresses 255 255 255 255 255 255 255 240 Here the subnet is 255 255 255 0 or 255 addresses The subnet limits from anything anything anything 0 up to the max The usable range for 192 168 1 10 255 255 255 0 is 192 168 1 1 to 192 168 1 254 192 168 1 0 and 192 168 1 255 are reserved for Router and Broadcast messages The usable range for 192 168 0 4 255 255 0 0 is 192 168 0 1 to 192 168 255 255 The usable range for 192 168 100 2 255 255 255 0 is 192 168 100 1 to 192 168 100 254 Not every IP address from 0 0 0 0 to 255 255 255 255 is usable however these three ranges of IP addresses are guaranteed open
53. ch is transmitted over the serial interface If sent the monitor aborts loading firmware into memory and brings up the monitor command prompt to load a new firmware version for example Otherwise the monitor reads the firmware from the flash memory and stores it in RAM Then the monitor executes the firmware The following parameters are critical to copy firmware and start it from the proper address fwad OxFFE40000 fwgo 0x1 fwsz 0x100000 fwcp 0x20000 fwst 0x20400 O Copyright 2009 all rights reserved United Electronic Industries Inc These parameters can be reviewed using the show command while at the monitor gt prompt fwad is the initial address where firmware is stored This address shall be set before storing firmware or executing it fwgo defines whether the monitor should load firmware 1 or should display a command prompt fwsz defines the size of the stored firmware Default value is 0x100000 one megabyte fwcp defines the address to which the monitor copies firmware from flash memory The default is Ox20000 Firmware is compiled to run from this address fwst defines firmware entry point Firmware entry point follows vector table and is located with offset 0x400 from the beginning of the firmware code These parameters are pre programmed at the factory and there is no known reason for a user to change them The monitor command fwjmp causes the monitor to loa
54. circuitry freezes its current operation which may be re enabled by writing a one to the DQ CTR_EN bit Reset 0 30 DQ CTR IFE Input FIFO enable 1 disable 0 Depending on the operation mode when enabled fetches one 32 bit word from the input FIFO to the CRO at the same time the counter register is reloaded with LR value 29 DQ_CTR_IFS Input FIFO transfer size Used only when DQ CTR_IFE 1 0 1 word 1 2 words Defines one CRO or two words CRO CR1 and is loaded whenever a time end of count condition is detected 29 DQ_CTR_IIE Enable 1 Disable 0 inversion of the input pin Value of the pin is inverted at the input before debouncing circuitry 28 DQ_CTR_GIE Enable 1 Disable 0 inversion of the gate pin Value of the pin is inverted at the input before debouncing circuitry 27 DQ_CTR_OIE Enable 1 Disable 0 inversion of the output pin When enabled output pin polarity is inverted at the last stage of creating the output 26 DQ CTR OU Current value of the output pin in GPIO mode valid if DQ_CTR_EN bit 0 and DQ_CTR_GPIO 1 25 DQ_CTR_OFE Output FIFO enable 1 disable 0 Depending on the operation mode when enabled copies one or two 32 bit words from the input CR or CRH CRL into the output FIFO when counter reaches end of count condition 24 23 DQ CTR CLFI DQ_CTR_CLFO If this bit is set during write to CTR all input paths will be clear
55. ction M Y Intemet Protocol TCP IP _ gt Install Uninstall Propertie STEP 5 If Internet Protocol TCP IP is not listed click on Install A X Copyright December 2012 Tel 508 921 4600 www ueidaq com Vers 3 6 Y Brie Electronic Inqusties Ic Date December 2012 File PowerDNA_Appendix fm DNA PPCx PowerDNA Cube Manual 76 DNA PPCx PowerDNA Cube Manual 77 STEP 6 In the next window double click on Protocol Select Network Component Type Click the type of network component you want to install El Client B Service i Protocol Description A protocol is a language your computer uses to communicate with other computers STEP 7 Select Internet Protocol TCP IP and click OK I x Dick the Network Protocol thet you want to metal then chek OK H you have ST aninataiation dik for thes component ciek Have Dish Notok Protocol Appie ab Protocol DLC Protocol NaBEUI Protocol Notveosk Monitor Daves NW Link IP ISPMeABIOS Compatible Tranapest Protocol STEP 8 Make sure the box beside nternet Protocol TCP IP contains a check mark and proceed to the next section Configure TCP IP C Configure TCP IP STEP 1 From the Start menu select Settings and then select Network and Dial up Con nections STEP 2 Inthe Network and Dial up Connections window double click on the Local Area Connection 2 icon STEP 3 Inthe Local Area Connection 2 Status window click Properties
56. d continue to step 4 to install it System Properties x General Device Manager Hardware Profiles Performance View devices by type C View devices by connection CDROM H E Disk drives a Display adapters Floppy disk controllers Hard disk controllers H E Keyboard Modem Monitor Py Mouse E EFE Netuork Adapters E EF AMD PCNET Family Ethernet Adapter PCI amp ISA 3 Dial Up Adapter STEP 4 Ifan entry for your second Ethernet card appears here you probably do not need to run any software included with your card but keep the software handy just in case you need it later to resolve a problem STEP 5 Note the name of your second Ethernet card STEP 6 Close the System Properties window the Control Panel window should still be open STEP 7 Open the Add New Hardware control panel and follow the on screen instructions We recommend that you allow Windows to search for and install your card automatically STEP 8 Restart your computer if Windows gives you the option to do so Then continue with Install TCP IP B Install TCP IP To determine whether TCP IP software is already installed on your computer follow these steps STEP 1 From the Start menu select Settings and then Control Panel STEP 2 Double click on the Network icon Click on the Configuration tab if it is not already selected ES O Copyright December 2012 Tel 508 921 4600 www ueidaq com Vers 3 6 Y e Ad Date December 2012 File PowerDNA_Appen
57. d Input Data to see immediate input values in Input tabs Use Network gt gt Store Config to save values to the layer 2 PowerDNA Explorer ol x File Network View Help ee JA A0 302 Modet 10m_19675 0JAL201 Info A Out 8 channel 1 A 201 sa 0021031 lt 2180 302 Mfg Date Dec 1 2003 2 10mM_20977 Cal Date Jan 19 2004 v Enabled j Output Range 10 10 Volts v Output Initalization Shutdown Name Value AQUIO AAA 0 0 AQutl Hr 0 0 AOut2 0 0 AOut3 0 0 AOut4 g 00 AOut5 eg 00 AQUt6 0 0 AQUI a 0 Figure 3 20 Example AO 302 layer You can change output initialization and shutdown values You can also change Output Range using the combo box and this only affects values dis played in initialization and shutdown tabs You can then choose Network gt gt Store Config to apply all changes to the layer Output Range is a popup allowing you to choose between 10 0V 0 10V and 10 10V Output Initialization Shutdown tabs switch between settings for init and shut down states as well as operation mode configuration The Output Initialization and Shutdown tabs contain the channel list table which has the following columns e The unnamed first column contains the channel names e Name is a user defined string e Value contains a slider to set the voltage to output from the channel and the
58. d and execute firm ware Vers 3 6 File PowerDNA _Chap5 fm Tel 508 921 4600 Date December 2012 www ueidaq com 5 2 2 Startup Sequence DNA PPC 5 8 DNA PPCx PowerDNA Cube Manual Chapter 5 50 Programming Layer specific Functions After reset the processor reads the boot up sequence located at Oxfffff100 This command sequence is a part of U Boot code U Boot initializes all major subsystems of the CM including DDRAM and Ethernet interface After initializing U Boot performs a command list stored in its environment sec tor under the bootcmd entry Standard commands to launch firmware are either fwjmp or go Oxffc10000 depending on the version of U Boot installed U Boot then gives up control to the firmware code located at Oxffc10000 Firm ware self expands into the DDRAM initializes exception table and starts exe cution United Electronic Industries Inc Date December 2012 5 2 3 Interfacing to There are two ways to set up CM parameters The first one is the use of serial the CM interface and the second one is the use of DaqBlOS calls Module Using To connect to the serial interface the user should connect an extender 9 wire a Serial serial cable to the PowerDNA cube plug male connector and your PC COM1 Interface serial port plug female connector Some cables have a female to female con nector If so you should use a gender changer Set up your terminal to the proper serial port 57600 bit rate no parity
59. dix fm DNA PPCx PowerDNA Cube Manual 82 Network lx Configuration Identification Access Control The following network components are installed E Client for Microsoft Networks if SMD PENET Family Ethernet Adapter PCI ISA 9 Dial Up Adapter YY TCP IP gt AMD PCNET Family Ethernet Adapter PCI ISA T TCP IP gt Dial Up Adapter Add Remove Properties STEP 3 Look in the box labeled The following network components are installed STEP 4 Ifyou see IPX SPX compatible Protocol or NetBEUI in the list select it then click the Remove button to delete it These protocols are used by some networked applications especially games but they may interfere with your Ethernet connection STEP 5 Ifyou don t see TCP IP for your second Ethernet card her continue with step 4 If you do see TCP IP for your second Ethernet card skip ahead to Configure TCP IP Do these steps only if you do not see TCP IP listed in your Network control panel for your second Ethernet card STEP 6 In the Network control panel click the Add button STEP 7 In the Select Network Component Type window choose Protocol and click the Add button Click the type of network component you want to install Protocol is a language a computer uses Computers must use the same protocol to communicate STEP 8 Inthe Select Network Protocol window select Microsoft under Manufacturer and TCP IP under Network Protocols ES O Copyrigh
60. dule Chapter4 The PowerDNA Core Module The top two slots of any 5 or 8 slot cube are occupied by the Core Module The Core Module consists of a CPU and peripheral devices RS 232 NIC SD etc The NIC is either a copper 100BaseT or a Fiber optic 10 100Base FX interface The CPU is either FreeScale ColdFire DNA CM or PowerPC CPU DNA PPC In addition an RS 232 port is provided for configuration and activ ity lights for status Figure 4 1 PowerDNA Core Module CPU and NIC This chapter focuses on the device architecture of the Core Module no lay ers A HH SSSL Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap4 fm DNA PPCx PowerDNA Cube Manual Chapter 4 46 The PowerDNA Core Module 4 1 Device The CM controller architecture can be represented as follows Architecture of DNA CM 9 36V DC Input Out Motorola ColdFire CPU Figure 4 2 FreeScale ColdFire Controller Architecture The core of the system is a FreeScale formerly Motorola ColdFire MCF5272 processor The processor is directly connected to the following components Network interface MII port e RS 232 port e IrDA port e 2MB user flash memory e 4MB system flash memory e 64MB of SDRAM e Bus bridge e Control logic LEDs e Watchdog timer with real time clock battery backed Not all components are available for control fro
61. e Update Progress Dialog Box Each cube is updated in three steps First the firmware is transferred to the cube Second the firmware is written to the flash memory During this step the R W light on the front of the cube is lit in addition to the PG light Third the cube is reset During this step the ATT COM and PG lights are lit and the R W light will turn on and off periodically When the cube is finished resetting only the PG light is lit To upload firmware over serial port using a terminal client MTTTY do the fol lowing Under DNA CM5 and DNA CMB8 Establish communications between the PC and a Cube over the serial link Press the Hardware Reset switch on the front of the Cube to reset the CPU Layer While the Cube is starting up again press lt Ctrl gt lt A gt to activate the download screen indicated by a gt prompt If you get to the DQ gt prompt you waited too long and must return to Step 2 Enter the dl command to enter the firmware download routine Transfer the file Depending on which terminal emulation package you decide to run you usually initiate the download with a command similar to send In MTTTY go to the top menu and select Transfer gt gt Send file text When it asks for a file go to the PowerDNA Firmware directory and select the S19 or MOT firmware file The download procedure will take roughly a minute To tell the Cube to save the new firmware into EPROM en
62. e for start and stop trigger Clock can be selected from internal sources EXTx lines signals from the isolated side and SYNCx interface signals inputs DqAdvAssignIsoDio This function selects direction and signal assignment for external DIO line EXTO 1 lines are assigned to DIOO 1 lines when DIO lines are in the input state DqAdvAssignIsoSync This function selects signal assignment for INT lines This function allows selecting what signal from isolated side of the layer logic will be assigned to INTx lines Signals can be selected from internal clock sources and SYNCx lines DqAdvAssignSyncx This function selects a signal for each of the SYNCx lines When a SYNC line is selected it switches to the output state All other layers lis ten to this command on the system bus and release that SYNC line from use switch to the input mode This organization prevents two lay ers from driving the same line DqAdvWriteSignalRouting This function writes and activates selected signal routing This function transfers created configuration to the cube and activates it Cube sends current synchronization configuration as a reply Please note that to take advantage of using external clocks for the layer clock and or trigger the source should be selected as external This means that in clocking configurations the following bits should be set up DQ LN CLCKSRC1 external CL clock is selected DQ LN STRIGEDGE1 extern
63. e layer Clicking the Start button for a counter will start that counter on the layer The Start button will turn into a Stop button and the other controls for that counter will become disabled until you click Stop While the layer is running you can choose Network Read Input Data to retrieve runtime values from the counter which will display in the read only text field s of the counter control panel Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 united Electronic Indusintes Ine Date December 2012 File PowerDNA _Chap3 fm DNA PPCx PowerDNA Cube Manual Chapter 3 44 PowerDNA Explorer 2 PowerDNA Explorer File Network View Help bo OG E Host PC 1om_20030 Mode CT 601 lt 0 CT 501 Info Counter Timer 8 units SN 0021169 Mfg Date Jun 4 2004 Cal Date Jun 4 2004 v Enabled Prescaler Value Min Gate Pulse Width Min Clock Pulse Width Counter 1 mode Counter Counter Value 1773034 Stop usec usec Input Pre inversion C Gate Pre inversion L Output Post inversion C Use External Clock Counter 2 mode Quadrature vw Figure 3 27 Example of Started Counter Copyright 2009 all rights reserved Tel 508 921 4600 United Electronic Industries Inc Date December 2012 www ueidaq com Vers 3 6 File PowerDNA _Chap3 fm DNA PPCx PowerDNA Cube Manual Chapter 4 45 The PowerDNA Core Mo
64. econd NIC proceed to step 4 STEP 6 From the menu on the left click Create a new connection to launch the New Connection Wizard STEP 7 Click Next and proceed to the Network Connection Type window STEP 8 Select Connect to the Internet and click Next New Connection Wizard Network Connection Type What do you want to do Connect to the Internet Connect to the Internet so you can browse the Web and read email STEP 9 Select Set Up My Connection Manually and click Next STEP 10 Select Connect Using a Broadband Connection that is always on and click Next STEP 11 Click Finish ES O Copyright December 2012 Tel 508 921 4600 www ueidaq com Vers 3 6 Y United Electronic Industries Inc Date December 2012 File PowerDNA_Appendix fm DNA PPCx PowerDNA Cube Manual 73 STEP 12 Inthe Network Connections window double click the second icon under LAN or High Speed Internet STEP 13 In the next window see illustration below click Properties 4 Local Area Connection Status General Support Connection Status Connected Duration 02 08 34 Speed 10 0 Mbps Signal Strength Activity gt Sent PA Received Udh Packets 5 689 4 664 STEP 14 Click the General tab click once on Internet Protocol TCP IP then click Properties STEP 15 Click the General tab click Use the Following IP Addresses and in the corresponding boxes enter 192 168 100 1 for the IP address 255 255 255 0 for the Subnet Mask and leave bla
65. ed CRH CRL and input FIFO FIFO will contain O samples and CRH CRL will be set to 0 Reset input FIFO before initiating any HOST gt CTU transfers If this bit is set during write to CTR all output paths will be cleared CRO CR1 LR and output FIFO FIFO will contain O samples and all registers affected will be set to 0 Reset output FIFO before initiating any CTU PHOST transfers 22 DQ_CTR_CLR If this bit is set during write to CTR CTUX will be reset to the default state and all registers FIFO will be cleared O Copyright 2009 all rights reserved United Electronic Industries Inc Tel 508 921 4600 www ueidaq com Date December 2012 File PowerDNA _Chap5 fm Vers 3 6 65 DNA PPCx PowerDNA Cube Manual Chapter 5 66 Programming Layer specific Functions Bit Name Description Reset 21 DQ_CTR_GPIO Ifthis bit is set GPIO operation of the clkout pin is enabled 0 DQ_CTR_EN DQ_CTR_GPI DQ_CTR_OU clkout O 0 0 x Remains in a last state 1 0 0 0 1 1 1 1 x x Defined by the current CTU mode 20 0 Reserved 0 0x2004 WR CTO_CCR CTUO Counter Control Register The CTU Counter Control register is used to set current mode for the counter and pre scaler The following table lists the CTO_CCR Bit descriptions O Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 Unileg Flecironic ndustnes Ine Date December 2012
66. eeeceecaecaeeeeeeeeeeeeeeseceeecsuaeeeeeeeeeees 11 2 2 PowerDNA Explorer Startup SCreen cececceeceecceeeeeeeeeeeeeeeeeceecceeaaeeeeeseeeeeetseeteees 17 2 3 Update Firmware Menu Item ooooooocccccncccccccccnccnnonnonconononnnnnnnnnnnnnnnnnn non nnnnnnnnnnnnnnnnnannnnnns 20 2 4 Password Dialog BOX cicciociciociiaadiaia iii dada id oia dec 20 2 5 Firmware Update Progress Dialog BOX ooooooccccnnnnnoccccconoconcccccnncnnnncncnnno nc coronan o ncnr nana 21 Chapter 3 PowerDNA Explorer oooooccccoccnrr eee 26 3 1 PowerDNA Explorer Main Window oooocccccccnncnconooocnnccnnnnnccnnnnnnnnnnnnnnnncnnnnnnnnnnninnnannnnnns 26 3 2 RrelerenceSs 4 is tates ae e E AE ee E 26 3 3 Address Ranges Dialog Box cccccceceeessecceteeeseseeeetestsnnecesenaeeneeeseeesenceeeeeesendeetenenenee 27 3 4 Edit Address Ranges Dialog BOX ooooocccccconoocccccconocncccccononcnnccnanonannnccnno nan cnc nnnnnrnnrnnnnnnna 27 3 5 After a Network gt gt Scan Network ooooocococccoconcooconccoconocccncnnnnnnnnnnnnnnnnncnnnnnnnnnnnannnnnnnnnnnnos 28 3 6 Password dialog box for Store Config and Store All CONfiYS ooooccnnnnnninnnnnonicccnnncnnss 29 3 7 Password Dialog Box for Update Firmware ooccconoccccccnnnonccoconanoncnccnnnnnnnnn conan ncnnncnnnos 29 3 8 Example of a Wiring Diagram ooooccoonocccoccconocccoccnanoncnnnnnnnnn nn n cnn nnn nn nr nan rra 30 3 9 Example of the Device Trennis i i ar a a aa aa aa ai aa aiana 31 3 10 Example of IOM Settings Pa
67. eight data bits and one stop bit Alternately using Start 2Run on the Microsoft Windows desktop type Program FileslUENPowerDNA Firmware mttty exe Click File gt Connect Once a connection to the PowerDNA cube is established tap Enter once The PowerDNA cube should respond with either a pos prompt this is firmware prompt or a gt prompt monitor prompt Once you see the po prompt you can type help lt enter gt to receive the list of all available commands The following commands are available DQ gt help help Display this help message help set Set parameter set option value show Show parameters show store Store parameters flash store mw Write wr lt addr gt lt val gt hex mw mr Read rd lt addr gt hex mr time Show Set time time mm dd yyyy hh mm ss pswd Set password pswd user su ps Show process state ps value test Test something test test number simod System Init Module Cal simod routine reset Reset system reset all daping Send DQ ECHO to lt mac addr gt daping MAC IP age Set current mode mode init config oper shutdown log Display log content log start end 1 clear ver Show firmware version ver devtbl Show all devices layers devtbl netstat Show network statistics netstat One of the most useful commands is show DQ gt show Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 File PowerDNA _Chap5 fm DNA PPCx PowerDNA Cube Manual
68. er specific gain macros 5 4 2 Configuration Configuration flags occupy a 32 bit configuration word The upper part of the Flags configuration word contains layer specific flags Standard part lower 16 bits of layer configuration word Please notice that for multiple subsystem layers one should pass multiple configuration uint32s in config io define DQ LN TSCOPY 1L lt lt 18 4 CORY timestamp along with the data define DQ LN MAPPED 1L lt lt 15 For WRRD DMAP devices define DQ LN STREAMING 1L lt lt 14 For RDFIFO devices stream the FIFO data automatically For WRFIFO do NOT send reply to WRFIFO unless needed define DQ LN RECYCLE 1L lt lt 13 if there is no data taken available overwrite reuse data define DQ LN GETRAW 1L lt lt 12 force layer to return raw oer unconverted data define DQ LN TMREN 1L lt lt 11 enable layer periodic timer define DQ LN IRQEN 1L lt lt 10 enable layer irgs define DQ LN PTRIGEDGE1 1L lt lt 9 stop trigger edge MSB define DQ LN PTRIGEDGEO 1L lt lt 8 stop trigger edge 00 software 01 rising 02 falling define DQ LN STRIGEDGE1 1L lt lt 7 start trigger edge MSB define DQ LN STRIGEDGEO 1L lt lt 6 start trigger edge 00 software 01 rising 02 falling define DQ LN CVCKSRC1 1L lt lt 5 CV clock source MSB define DQ LN CVCKSRCO 1L lt lt 4 CV clock s
69. ernate Configuration tab located under the Windows XP network configuration screen located in the Windows XP Control Panel ES O Copyright December 2012 Tel 508 921 4600 www ueidaq com Vers 3 6 Y Brie Electronic Inqusties Ic Date December 2012 File PowerDNA_Appendix fm DNA PPCx PowerDNA Cube Manual 75 Network Connections Local Area Connection Properties General Authentication Advanced Qe E Search Folders F3E Connect using EEL a RA E9 Intel R 82559 Fast Ethernel LAN on Molheiboard E Network Tasks LAN or High Speed Int This connection uses the following items Local Area Connection 4 Y NWLink NetBIOS a gt 4 ENW Link IPX SPX NetBIOS Compatible Transport Prot Local Area Connection Status Y Intemet Protocol TCPAP General Support Internet Protocol TCP IP Properties Connection General Atemate Configuration Status Duration 06 45 54 Speed O Automatic private IP address User configured Received IP address 192 168 100 1 122715 GS EE AA Default gateway Select Alternate Configuration tab a os Enter IP address and Subnet mask as shown Once you have this configuration in place your computer will look for the attached device on your Ethernet port during Boot Up or during a Windows Log On operation If it sees a powered on PowerDNA cube connected to the Ethernet port it will automatically switch to using the secondary
70. eserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Ine Date December 2012 File PowerDNA _Chap5 fm DNA PPCx PowerDNA Cube Manual Chapter 5 52 Programming Layer specific Functions Address Irq Model Option Phy Virt S N Pri DevN 0xA0000000 2 205 1 phys 0023115 10 O 0xA0010000 2 205 ill phys 0023117 20 1 0xA0020000 2 205 I phys 0023119 30 2 Current time 18 53 45 11 01 2004 IOM TCP IP DQ stack MAC 00 0C 94 00 59 1B To perform a full hardware reset use DQ gt reset all The full reset performs a_physical reset of the CPU and initiates the whole startup sequence Some commands mr mw set and store particularly require entering a user password Once the password is entered these commands become enabled until firmware reset There are two levels of password protection avail able The first is user level and the second is super user level Super user level is currently used only for updating firmware over the Ethernet link DQ gt pswd user sets up a user level password First you ll be asked about your old password and then if it matches to enter the new password twice DQ gt pswd su sets up a super user level password First you ll be asked about your old super user password and then if it matches to enter the new super user password twice PowerDNA cubes come with the default password set to powerdna Some DaqBlOS commands require clearing up user or super user passwords Use DqCmdSetP
71. ess lors e eas a a ee ee 92 16871 10 Subnet Mask 468 5 255 255 255 0 Default Gateway 192 168 1 1 Ethernet adapter NIC2 Local Area Connection 2 Connection specific DNS Suffix IP Address b 192 168 100 3 Subnet Mask 255 255 255 0 Default Gateway 192 168 100 3 STEP 5 Setup the PowerDNA Cube to use the same subnet namely Cube IP 192 168 100 2 this is the factory default Gateway 192 168 100 3 Netmask 255 255 255 0 To do this from a serial terminal emulation program enter the following com mands when you get the DQ command prompt Sets this Cube s IP address to 192 168 100 2 Sets this Cube s Gateway to 192 168 100 3 Sets the subnet mask to 255 255 255 0 DQ gt set ip 192 168 100 2 DQ gt set gateway 192 168 100 3 DQ gt set netmask Y XX gt Tk WT SSA 255 255 255 0 Saves the newly changed configuration DQ gt store Reboots the cube for the new IP to DO gt reset take Q gt effect STEP 6 Connect the PowerDNA Cube to your PC s second NIC using the bundled CAT5 cable The green lights should light up try the other port otherwise STEP 7 Ping the cube to make sure that it is alive C gt ping n 1 192 168 100 2 Pinging 192 168 100 2 with 32 bytes of data Reply from 192 168 100 2 bytes 32 time lt lms TTL 128 Ping statistics for 192 168 100 2 Packets Sent 1 Received 1 Lost 0 0 los
72. fic Functions pre scaler is loaded with O it will be by passed and an input signal will be used as an input clock for the count register CR but GATE pin if used will still affect the counter 0x2008 RD CTO_PS CTUO Prescaler Current Value Read current 32 bit value of the prescaler 0x200C RD CTO_LR CTUO Load Register 32 bit value stored in the load register LR will be loaded into the main counter CR at the beginning of each counting cycle 0x200C RD CTO_CR CTUO Count Register Current Value Current value of the count register latched at the time of the read 0x2010 WR CTO_IDBC CTUO Input Pin Debouncing Filter Counter Reg ister Program input clock debouncing register 32 bit register IDBC CTUO will expect input clock to remain stable for the specified number of 66MHz clocks before processing qualifying it 0x2014 WR CTO0_IDBG CTUO Gate Pin Debouncing Filter Counter Reg ister Program input gate debouncing register IDBG CTUO will expect input gate line to remain stable for the specified number of 66MHz clocks before processing qualifying it 0x2018 RD CTO_PC CTUO Current Value of the Period Counter Register 32 bit current value CTUO period count register CTO_PC Set CTUO period count register Period count register PC is used in a measurement mode when averaging for multiple periods It is required because of the high speed or unstable nature of the incoming signal Results of the meas
73. following steps STEP 41 From the Sfart menu select Settings and then select Network and Dial up Con nections STEP 2 Ifyou see a Local Area Connection icon your Ethernet card has been detected and installed skip ahead to the section Configure TCP IP If you do not see this icon proceed to step 3 STEP 3 From the Start button select Settings then Control Panel Double click on the Add Remove Hardware icon and follow the on screen instructions We recommend that you allow Windows 2000 to search for and install your Ethernet card automatically If Windows 2000 does not find your Ethernet card you will need to install it manually by following the manufacturer s instructions STEP 4 Once your Ethernet card has been installed click OK and continue with the next section B Install TCP IP STEP 41 From the Start menu select Settings and then select Network and Dial up Con nections STEP 2 Inthe Network and Dial up Connections window double click on the Local Area Connection 2 icon STEP 3 Inthe Local Area Connection 2 Status window click Properties 21 General r Connection Status Connected Duration 02 25 00 Speed 10 0 Mbps peg Sen E ES Packets 768 458 A m STEP 4 If Internet Protocol TCP IP is listed make sure the box next to it contains a check mark and go to Configure TCP IP 21x General Connect using B3 AMD PCNET Family PCI Ethernet Adapter Components checked are used by this conne
74. for private use 10 0 0 0 10 255 255 255 177 2 163 023 08 gt 172 31 2552509 192 168 0 0 192 168 255 255 You need not use the entire set STEP 2 Install the secondary NIC card STEP 3 Setup a network that does not overlap the existing one The address space 192 168 1 0 192 168 1 255 is used The IP address block 192 168 2 1 192 168 2 255 is available and in the private range Let us choose 192 168 100 1 192 168 100 255 for the PC s secondary NIC LPS 192 168 100 3 Netmask 255 255 255 0 Gateway 192 168 100 3 Using the Network Connections in the control panel Start gt gt Programs gt gt Control Panel gt gt Network Connections Right click the adapter to bring up the properties window Open the TCP IP properties of the adapter and edit to your liking Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronie Industnies Ing Date December 2012 File PowerDNA _Chap2 fm 14 DNA PPCx PowerDNA Cube Manual Chapter 2 15 Installation and Configuration NOTE Refer to the Appendix at the end of this document Configuring a Second Ethernet Card for step by step instructions on how to do this STEP 4 Confirm the network configuration at the Command Prompt Start gt gt Programs gt gt Accessories gt gt Command Prompt C gt ipconfig Ethernet adapter NIC1 Local Area Connection Connection specific DNS Suffix IP Addr
75. from the menu ile Network View Help Address Ranges Scan Network Ctrl N I Reload Config trl F Store Config l i Store All Configs Read Input Data rl Start Data Logging tem Windows XP 402 ARRAN 32 ad it 2 Address Ranges x IP Addresses Update Firmware 192 168 100 2 6334 Add STEP 2 STEP 3 Copyright 2009 all rights reserved United Electronic Industries Inc Edit Delete Figure 2 2 PowerDNA Explorer Startup Screen Add the IP address of the PowerDNA Cube e g 192 168 100 2 click Done Now scan the LAN for PowerDNA Cubes Network gt gt Scan Network One or more gray cube like icons will display in the left hand side of the cube If no cube icons are displayed see the Troubleshooting note in the previous sec tion Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap2 fm DNA PPCx PowerDNA Cube Manual Chapter2 18 Installation and Configuration STEP 4 Double click a cube to see its information and list the layers PowerDNA Explorer File Network View Help Host PC 10M_10238 Model 11 205 lt 0 Al 201 Info 4 In 4 channel 1 A1 225 SIN 0029176 2 AR205 Mfg Date Mar 1 2006 lt 3 AO 302 E Se 4 DIO 403 Cal Date Mar 1 2006 Enabled Input Range 100 100V The screenshot above is from the PowerDN
76. hould have automatically detected it Under and you should proceed to the next section Install and Configure TCP IP di Optionally you may follow steps 1 3 below to confirm that your interface is Windows NT recognized If you obtained an Ethernet interface after Windows NT was already on your computer do the following STEP 1 From the Start menu select Settings and then select Control Panel STEP 2 Double click on the Network icon STEP 3 Click on the tab labeled Adapters You should then see an entry for your Ethernet card If you do not see one continue to step 4 to install it Otherwise click OK and skip ahead to Install and Configure TCP IP STEP 4 Click Add and follow the on screen instructions Select your Ethernet card from the list shown or if it is not included in the list click Have Disk and insert the diskette that came with the card Even if your card does appear in the list it s a good idea to use the diskette to make sure you have the latest drivers STEP 5 Restart your computer if Windows gives you the option to do so Wait for the system to restart before continuing with the next section ES O Copyright December 2012 Tel 508 921 4600 www ueidaq com Vers 3 6 Y e Ad Date December 2012 File PowerDNA_Appendix fm STEP 4 STEP 2 STEP 3 STEP 4 STEP 5 STEP 6 STEP 7 O Copyright December 2012 United Electronic Industries Inc DNA PPCx PowerDNA Cube Manual B Install and Configu
77. iew Help to b ADD m Host PC i System Windows XP IP 10 102 226 7 Figure 3 1 PowerDNA Explorer Main Window The Main Window is the window you see when the PowerDNA Explorer is first launched and is where you do most of your work lt has four main parts the Menu Bar the Toolbar the Device Tree and the Settings panel The Menu Bar contains the following menus and menu items Preferences brings up the preferences dialog The preferences dialog allows you to specify the network timeout interval This is the length of time PowerDNA Explorer will wait for response from a Pow erDNA cube before giving up with an error It defaults to 100 milliseconds Network timeout 0 msec Figure 3 2 Preferences Exit exits the application If there are unsaved device settings changes you are prompted for confirmation 3 2 2 Network Menu Address Ranges brings up the Address Ranges dialog allowing you to specify Copyright 2009 all rights reserved United Electronic Industries Inc Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap3 fm DNA PPCx PowerDNA Cube Manual Chapter 3 27 PowerDNA Explorer where to scan for devices Address Ranges x IP Addresses 192 168 100 2 192 168 100 10 6334 Figure 3 3 Address Ranges Dialog Box The Address Ranges dialog allows you to specify the IP addresses and UDP port to use to find devices You can specif
78. itching into operation mode INITPRM_xxx_ contains initial I O directions and output levels The firmware sets up the direction and the level on every output line on entering initialization state SDOWNPRM_xxx_ contains final I O directions and output levels The firmware sets up the direction and the level on every output line on entering shutdown state CNAMES_xxx_ contains channel names The length of the channel names depends on the layer type Only 512 bytes are allocated for channel names Thus Al 205 layer four channels can have channel names as long as 32 char acters while DIO 403 channel names 48 channels cannot be longer then 10 characters There is a set of functions written to read write and store these parameters into E7PROM Functions DqCmdGet Parameters DqCmdSet Parame Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap5 fm DNA PPCx PowerDNA Cube Manual Chapter 5 Programming Layer specific Functions ters access modal parameters while DqCmdSaveParameters stores parameters into E PROM 5 4 4 PowerDNA Setting up triggering synchronization and clocking lines Layer Most PowerDNA layers have the following interconnection diagram Signaling DqAdvAssignIsoSync DagAdvAssignSyncx DIO 0 gin 3 CLKIN SYNCO A IS Logic E Logic sync _ pin 4 TRIGIN SYNC2 pa DIO 2 SYNC3_ _ pin 22 CLKQUT V
79. l Chapter 2 25 Installation and Configuration For FCM and FPPC cubes use a fiber NIC as shown below In this diagram NIC1 is a copper NIC connecting the PC to the LAN optional NIC2 is an Intel network card in the PC used to connect to the cube s built in fiber ports A multi mode optical cable with SC type plugs like this one is used to connect to the Tx Rx plugs In 100Base FX mode the maximum transmis sion range without a repeater is 2km at full duplex or 400m at half duplex The cube uses an HFBR 5803 transmitter capable of communication at 100Mbps 2 5 Peripheral Refer to the companion layer manuals for proper wiring to layers Terminal Panel Wiring __x_QIxzxE gt mmm __ ___z_z_ gt ___ CRp p gt _ pe ee sss eee ee O Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic ndustes ng Date December 2012 File PowerDNA _Chap2 fm Chapter 3 3 1 The Main Window 3 2 Menu Bar 3 2 1 File Menu DNA PPCx PowerDNA Cube Manual Chapter 3 26 PowerDNA Explorer PowerDNA Explorer PowerDNA Explorer simplifies configuration and setup of a PowerDNA cube under Microsoft Windows This section describes the various menus in PowerDNA Explorer NOTE The PowerDNA Explorer DEMO lets you safely explore the menus and layer screens without the need for using actual PowerDNA cubes The Main Window of the PowerDNA Explorer is shown in Figure 3 1 2 PowerDNA Explorer File Network V
80. l program A typical readout might be e ES File ITY Transfer Help Port Baud Parity Data Bits Stop Bits TIESTO No com z 57600 y None y fe y fi y IV Display Errors I ng CR gt CR LF F No 5 Font Comm Events Flow Control Timeouts Disconect I Autowrap re it Gratis CS Detecting memory Detected 67108864 bytes SDRAM Testing Press Ctrl A to boot into dBUG Esc to skip memory test 32 8 Memory test lt 64MB gt has passed Restart Hard Reset SDRAM Size 64M lt C gt 2001 2004 UEI Inc MCF5272 PowerDNA Firmware v4e 1a 5b lt Build 46936 on Sep 36 2004 17 28 18 gt Copying and starting firmware Bx284BB DaqBIOS lt C gt UEI 2001 2005 Running PowerDNA Firmware Built on 14 28 14 Jan 9 20806 Initialize uC OS II lt Real Time Kernel v 28 gt Configuration recalled 4 device detected Address Irq Model Option Phy Virt S N Pri DeuN GxAGG0G808 2 201 160 phys 4021888 16 xAGG19006 2 1 BxABB2000B 2 404 1 phys 0025443 38 2 6x666036606 A 500 1 phys 13195808 116 3 Current time 21 56 56 02714 21055 IOM TCP IP DQ stack MAC 0 6C 94 060 64 AD Enter help for help DQ gt v 4 F CTS Y DSR I RING I RLSD CD I CTSHod M XOFF Hold I TXChar aoa eaea REAK I DSR Hold J XOFF Sent TX Chars fo S EVENT CTS 7 RLSD Hold J EOF Sent Px Chars 0 Modem Status Comm Status Figure 2 1 Typical MTTTY Startup Screen The boot process displays the model serial
81. m the CPU The CPU can pro gram flash memory set the LEDs set up the watchdog timer set the real time clock and use 256 bytes of backed up memory in the watchdog timer chip All functions are available at the firmware level only described in iom c iom h A ee O Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap4 fm DNA PPCx PowerDNA Cube Manual Chapter 4 47 The PowerDNA Core Module 4 1 1 Device The PowerPC controller architecture can be represented as follows Architecture of DNA PPC 9 36V DC Input Power Out AS Freescale PowerPC Isolation ce Ge Figure 4 3 PowerPC Controller Architecture The core of the system is a FreeScale PowerPC MPC5200 400MHz processor The processor controls the following components Network interface MII port e RS 232 port e SYNC port e 4MB system flash memory e 128MB of 266MHz DDRAM e Bus bridge All functions are available at the firmware level only iom c iom h Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap4 fm Chapter 5 5 1 Overview DNA PPCx PowerDNA Cube Manual Chapter 5 Programming Layer specific Functions Programming Layer specific Functions This chapter describes tools and facilities used for programming module spe cific functio
82. n was detected 0 on the gate pin deglitched 25 DQ_IR_HLI Request interrupt if high low transition was detected 0 on the input pin deglitched 24 DQ_IR_HLG Request interrupt if high low transition was detected 0 on the gate pin deglitched 23 DQ_IR_CRH Request interrupt if data is available in CRH 0 22 DQ_IR_CRL Request interrupt if data is available in CRL 0 21 DQIR_IFE Request interruptifinputFIFO is empty 0 20 DQ_IR_IFH Request interrupt if input FIFO is at least full 0 19 DQ_IR_IFF Request interrupt if input FIFO is full 0 18 DQ_IR_OFE Request interrupt if output FIFO is empty 0 17 DQ_IR_OFH Request interrupt if output FIFO is at least Y full 0 16 DQ_IR_OFF Request interrupt if output FIFO is full 0 15 0 Reserved 0 5 6 3 Command Mode Copyright 2009 all rights reserved United Electronic Industries Inc 0x2040 RD CTO_ISR CTUO Interrupt Status Register This register should be used to define source of the interrupt from the CTU It will show 1 in the bits that are the source for the interrupt The ISR keeps its value until cleared by a write to the ICR or by system reset CTO_ISR Bit description The ISR bits match IER 0x2044 RD CTO_ICR CTUO Interrupt Clear Register Writing one to any of the bits in ICR will clear matching bit in ISR thus clearing the interrupt request based on that bit Note that if the interrupt condition still exists and is enabled it will be fired again
83. nel for a PowerDNA cube 0oooccccccccccccccccconcccnnnnoncnnnonnnnos 31 3 11 Example of Device Layer Settings for a Lay8T oonnoocccnnnicocicnnncconccnnonanancnnnonnnnnnnrnnnnnnos 33 3 12 Screen from Network gt gt Read Input Data ooooooococccncnnccccccccncccconcononnccnononcnonnnnnannnnncnnnos 34 3 13 Example DIO 405 Layer IMputS oooooconicnnnicoconoconcnncnnncocnnnnnnnnnnnnonnnnnnnnnnnnnnnnnnnnnnnnnnnnnnos 35 3 14 Example DIO 405 Layer Outputs ooooccccccnocoooconococcnnccnnconononnnnnnnnnnnnnnnnnnnnnnnnnnnannnnnnnncnnn 36 3 15 Example of DIO 403 Layer IMputS ooooonccncncccccnccnncccccccccconcnnonnnononncnnnnnnnnnnnnnnnannnnnnncnnnno 37 3 16 Example of DIO 403 Layer OuUtputS oooococcccccconccnccccccccccconnonnonnnnconnnnnnnnnnnnnnnnnnnnnnnnnncnnnos 37 3 17 Example of DIO 403 Layer Outputs oooconcccccconccccccccccccccnnnonnonnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnccnnnos 38 3 18 Example DIO 403 Layer Configuration ooooccccnnnncccnnnnnnccccncnnononannnnnonnno nana rc nnnnnncnn rana 38 3 19 Example DIO 403 Layer InitialiZatiOD oonnnnnnnninnnnnnccccnnnnnncacnnnnonnncrrnnrrnnnrrrnnn rra 39 3 20 NOIA eee a a TE E AAEE RTA 40 3 21 Example Alt201 Tayari an r a 41 3 22 Example CT 601 layer iren E AAE AE E O EE E 42 3 23 Example Quadrature Contool Se aea aaa aaa eaa a aaa aa a a a iaaea 42 3 24 Example Bin Counter controls oooooonocicnionocconcccncnncnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnannnnnnnncnnn 43 3 25 Example Pulse Width Modulation P
84. nk the router or default gateway information STEP 16 Click Use the Following DNS Server Addresses STEP 17 Make sure the Preferred DNS Server box and the Alternate DNS Server box are blank STEP 18 Click OK or Close until you return to the Network Connections window STEP 19 Close the Network Connections window C Troubleshooting If you encounter problems connecting to the network first check to make sure the Windows XP Internet Connection Firewall is turned off Follow the instructions below STEP 1 From the Start menu select Control Panel STEP 2 Under the heading Pick a Category click Network and Internet Connections STEP 3 Under pick a Control Panel icon click Network Connections STEP 4 Double click the icon under LAN or High Speed Internet In the next window click Properties ES O Copyright December 2012 Tel 508 921 4600 www ueidaq com Vers 3 6 Y e Ad Date December 2012 File PowerDNA_Appendix fm DNA PPCx PowerDNA Cube Manual 74 STEP 5 Click the Advanced tab and uncheck the box Protect My Computer and Network by limiting or preventing access to this computer from the Internet see illustration below 4 Local Area Connection Properties General Authentication Advanced Internet Connection Firewall C Protect my computer and network by limiting or preventing access to this computer from the Internet Learn more about Internet Connection Firewall STEP 6 Click OK or Close
85. ns memory maps for various CPUs register descriptions proce dures for startup setting parameters loading updating firmware setting up triggers synchronization and clock lines 5 2 Memory Map The ColdFire based CM has the following memory map Start Device Address End Address Size Description SDRAM 0x0 0x4000000 64MB SDRAM_ADDRESS Interrupt table 0x0 0x400 1024 Processor address map Firmware load 0x20000 End address and size depends on address firmware size Firmware start 0x20400 First execution instruction of firmware address IMM 0x10000000 Memory map register 1mm ADDRESS On board PLD 0x60000000 0x61000000 1MB EXT_SRAM_ADDRESS Watchdog timer 0x60008000 IOM_WDTIMER Within PLD access space Processor 0x80000000 RAMBAR User flash 0x90000000 0x90400000 4MB FLASHAUX_ADDRESS memory Layer CS2 0xA0000000 OxAOOFFFFC 1MB EXT_DEV_ADDRESS2 Layer CS3 0xA0100000 OxAFFFFFFC 256M EXT_DEV_ADDRESS3 The PowerPC based CM has the following memory map Start Device Address End Address Size Description SDRAM 0x0 0x8000000 128MB SDRAM_ADDRESS Exception table 0x0 0x3000 12k Processor address map IMM 0x10000000 Memory map register 1mm ADDRESS On board logic OxA00E0000 OxAOOEFFFC 64kB EXT_SRAM_ADDRESS Watchdog timer 0xA00E8000 IOM_WDTIMER Within PLD access space Processor 0x80000000 RAMBAR Layer CS2 OxA0000000 OxAOOFFFFC 1
86. number and position of layers Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap2 fm 11 2 2 4 DNA PPCx PowerDNA Cube Manual Chapter2 12 Installation and Configuration Type show lt CR gt to display information about cube configuration DO gt show IOM or I O Module is another name IOM 1234 name for a Cube model 0x1005 Core Module gt Model Number 1005 serial 0012345 mac 00 00 11 AA BB CC ColdFire Core Module gt Serial Number S N of Cube Core Module gt NIC Layer gt MAC fwct 1 2 0 0 Address Srv Define Cube procedure on startup 192 168 100 3 ip IP Address of firmware server NACHA IP Address of this Cube gateway IP Address of gateway 192 168 100 1 IP Subnet Mask of this Cube netmask UDP Port to receive commands on 255 255 255 0 udp 6334 IP Addresses on the PowerDNA Cube Copyright 2009 all rights reserved United Electronic Industries Inc All parameters can be changed most notably the cube s configured IP gate way and subnet mask netmask The PowerDNA Cube ships with a preconfigured factory default IP address in nonvolatile memory usually 192 168 100 2 This is a static IP address the PowerDNA Cube never retrieves its IP address from a DHCP server This section describes why and how to change the default IP address Should you change the IP Yes if you plan to use the Cube on
87. numerical voltage value which you can input directly The actual voltage depends on the selected output range Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap3 fm DNA PPCx PowerDNA Cube Manual Chapter 3 41 PowerDNA Explorer 3 4 Analog Input We ll use the Al 201 as an example to start with The Al 202 and Al 205 are Layer similar Settings NOTE Use Network gt Read Input Data to see immediate input values in Input tabs Use Network gt Store Config to save values to the layer 2 PowerDNA Explorer File Network View Help 1616 01 KA Hast PC o lOM 19675 Model Al 201 0 ia Info A In 24 channel 0 A 201 SIN 0022432 lt S 1 Al 201 E y 2 41 201 Mfg Date Aug 1 2004 tal x lt 3 Al 201 4 Cal Date Aug 17 2004 V Enabled Input Range 15 15 Volts Name Value AINO 10 0007 Alnt 0 0011 Aln2 0 0016 Aln3 0 0021 Aln 10 0025 Aln5 0 003 Aln6 0 0034 Aln 10 0039 Ans 0 0043 Alng 0 0048 Anio 0 0053 Aln11 10 0057 Aln12 0 0062 Alnt3 0 00686 Aln14 10 0071 0 0076 0 008 0 0085 Figure 3 21 Example Al 201 layer Input Range shows the specified input range It cannot be changed and thus is informational only The Data table contains the values currently coming into the device The table
88. o CRH 0xA 1010 DQ cM _NP capture full period CR captures length of the full period copies positive part of the period into CRH and negative low into CRL if CTx_PC gt 0 continue this process increasing CRH CRL for the length of positive negative part of every period OxB 1011 DQ CM QE quadrature encoder mode 0x4 0100 DQ cM TCT same as 0x0 but with trigger 0xC 1100 DQ CM TECT same as 0x8 but with trigger 0xD 1101 DQ CM _THP same as 0x9 but with trigger OxE 1110 DQ CM TNP same as 0x9 but with trigger Note that all modes except mode 0 are using debounced CLKIN pin as a clock source for the pre scaler Trigger source Harware Software is selected using DQ_CCR_TRS bit Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap5 fm 67 DNA PPCx PowerDNA Cube Manual Chapter 5 Programming Layer specific Functions Name Bit Reset Description State nable sable ardware gate on the prescaler If enabled GATE input when positive enables pre scaler counter Note that DO_CTR_EN bit in CTR may be effectively used as a software gate when DQ _CCR_PSG 0 22 DQ_CCR_TRS Select Hardware 1 Software 0 trigger source for the triggered 0 modes Hardware triggered modes will start at low high transition on the GATE input In software trigger mode DQ_CTR_EN bitin CTR should be used as a trigger DQ_CTR_EN will be cleared at the end of the counting operation if CCR_T
89. ocol is in use used in homogenous IOM networks only This parameter is ignored when the PowerDNA cube is used over the UDP protocol or from the host IP specifies the IOM IP address This is the most important parameter a user must change to allow the PowerDNA cube to be visible on the network The PowerDNA cube responds to every UDP packet containing a DaqBlOS prolog sent to this address Since the current release does not support DHCP the user should set up the IP address gateway specifies where the PowerDNA cube should send an IP packet ifa requested IP packet exists outside of the PowerDNA cube network defined by the network mask Ask your system administrator if you use your PowerDNA cube on the office network netmask specifies what type of subnet the PowerDNA cube is connected to The factory sets netmask to type C IP network 254 nodes maximum udp specifies what port the firmware should use if a network packet originated from this PowerDNA cube without a previous request from the host side If the PowerDNA cube replies to a DaqBlOS packet it uses the source IP address from the IP packet header and source UDP port from UDP packet header Let s assume that user wants to connect a PowerDNA cube to the dedicated Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap5 fm DNA PPCx PowerDNA Cube Manual Chapter 5 54 Programming Layer specific Functions network secondary NIC ad
90. onnect the PowerDNA Cube to your switch with the bundled CAT5e cable If you can establish communications with a Cube but later want to modify the IP address you can also do so from within PowerDNA Explorer After the exploratory process go to the field where the application displays the IP address Enter the new IP address and then hit lt Return gt This action down loads the new IP address into the Cube s non volatile memory You might also need to change the gateway and network mask to match settings on your LAN 2 2 5 Improving To improve PowerDNA network performance we recommend that you use a Network separate commercially available network interface controller NIC card and set Performance up a dedicated mini network for PowerDNA The goal of this section is to facilitate creation of such a network NIC1 to Intranet Out to rest of network NIC2 to Cube s For example assume that your office uses a Class C network the class intended for small networks with fewer than 256 devices and your host is con figured with a static IP or via DHCP Dynamic Host Configuration Protocol a protocol for assigning dynamic IP addresses to devices on a network STEP 1 Obtain your networking configuration by using the Command Prompt Start gt gt Programs gt gt Accessories gt gt Command Prompt C gt ipconfig E A ae O Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 united Electroni
91. ource 01 SW 10 HW 11 EXT define DQ LN CLCKSRC1 1L lt lt 3 CL clock source MSB define DO LN CLCKSRCO 1L lt lt 2 CL clock source 01 SW 10 HW 11 EXT define DQ LN ACTIVE IL lt lt 1 STS LED status define DQ LN ENABLED 1L lt lt 0 enable operations DQ_LN ACTIVE is needed to switch on the STS LED on CPU layer DO LN ENABLE enables all operations within the layer DO LN _CLCKSRCO selects the internal channel list clock CL source as a time base Al 201 supports the CL clock only where the time between consecutive channel readings is calculated by the rule of maximizing setup time per chan nel If you d like to clock the CL clock from an external clock source such as SYNCx line set the DO_LN_CLCKSRC1 flag as well Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 United Electronic Industries Ine Date December 2012 File PowerDNA _Chap5 fm 5 4 3 EEPROM User Area Access DNA PPCx PowerDNA Cube Manual Chapter 5 Programming Layer specific Functions DQ LN _CVCKSRCO selects the internal conversion clock CV source as a time base Setting CV clock allows having an equal time period between conver sions of different channels It is mostly used when the user is interested in a phase shift between different channels The user can select either the CL or CV clock as a time base If both clocks are selected the CL clock is taken as a time base and
92. rDNA Software Suite low level driver and PowerDNA tools e UEIDAQ Framework high level programming examples optional Both installers automatically search for third party IDE and testing suites and add themselves as tools to the found suites Install third party applications e g LabVIEW MsVS2003 before installing the PowerDNA Software Suite or UEIDAQ Framework To install the PowerDNA Software Suite do the following Log in as Administrator Run Setup a Insert the PowerDNA Software Suite CD into your CD ROM drive Windows should automatically start the PowerDNA Setup program An installer with the UEI logo and then PowerDNA Welcome screen should appear If none appears run setup exe from the CD drive Start gt gt Run gt gt d setup exe gt gt OK If you downloaded the most recent executable from www ueidaq com double click to run the executable b Choose the PowerDNA Software Suite option c Unless you are an expert user and have specific requirements we advise you to select Typical installation and accept the default Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap2 fm DNA PPCx PowerDNA Cube Manual Chapter2 10 Installation and Configuration configuration The Software Suite installer requires and automatically installs Sun s Java VM JRE for you in addition to the full complement of tools As an alternative use the custom option to display and ensure that all of
93. re TCP IP From the Start menu select Settings and then Control Panel Double click on the Network icon then click the Protocols tab In the list of Network Protocols look for TCP IP Protocol If you don t see it click Add select TCP IP Protocol and then click OK Select TCP IP Protocol in the list of Network Protocols and then click Properties A Microsoft TCP IP Properties window will open Network 21x Identification Services Protocols Adapters Bindings Network Protocols Add Remove Properties Update Click on the IP Address tab if it is not already selected Make sure that the radio button next to Specify an IP address is selected Enter 192 168 100 1 for IP Address 255 255 255 0 for Subnet Mask and leave blank the Gateway Address in the Default Gateway box Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA_Appendix fm DNA PPCx PowerDNA Cube Manual 80 Microsoft TCP IP Properties 121 x IP Address DNS WINS Address Routing An IP address can be automatically assigned to this network card by a DHCP server If your network does not have a DHCP server ask your network administrator for an address and then type it in the space below Adapter 3Com Fast EtherLink XL NIC 3C905B T gt Obtain an IP address from a DHCP server Specify an IP address IP Address A Subnet Mask Default Gateway Advanced
94. read from TESTO returns 0x01234567 read DQ_CTU_TEST1 Test Register1 TEST1 is a reserved test read only register In current implementation read from TEST1 returns OxABCD0123 read 5 6 Register The following table shows Counter Timer Units 0 7 registers with 0x80 offset increment representations 0x2000 0x207C DQ_CLI_CTUOS CTUO I O registers 0x2080 0x20FC DQ_CLI_CTU1S CTU1 I O registers 0x2100 0x217C DQ_CLI_CTU2S CTU2 I O registers 0x2180 0x21FC DQ_CLI_CTU3S CTU3 I O registers 0x2200 0x227C DQ_CLI_CTU4S CTU4 I O registers 0x2280 0x22FC DQ_CLI_CTU5S CTU5 I O registers 0x2300 0x237C DQ_CLI_CTU6S CTU6 I O registers 0x2380 0x23FC DQ_CLI_CTU7S CTU7 I O registers This section lists bit descriptions for various status registers Descriptions Copyright 2009 all rights reserved United Electronic Industries Inc 0x2000 RD CTO_STR CTUO Status Register The CTU Status register is used to report current operational status of the coun ter timer unit via dedicated bits for every status condition reported The Status register mirrors some of the ISR interrupt status register bits but it reports cur rent status while ISR reports latched status of the fired interrupts Tel 508 921 4600 Date December 2012 Vers 3 6 File PowerDNA _Chap5 fm www ueidaq com 63 DNA PPCx PowerDNA Cube Manual Chapter 5 Programming Layer specific Functions
95. ronic Indusintes Ine Date December 2012 File PowerDNA _Chap1 fm 3 O Copyright 2009 all rights reserved United Electronic Industries Inc DNA PPCx PowerDNA Cube Manual Chapter 1 Introduction PowerDNA Explorer The essential tool for configuring and testing the cube See Chapter 3 for use Multi Threaded TTY Client For initial setup of the cube on the network upgrades and calibration Example C amp Java code Facilitates jumping in and learning this code will compile and execute on the cube In addition to the examples in the PowerDNA Software Suite the UEIDAQ Framework contains example code for higher level languages C VB Java and also several graphical programming languages e g LabVIEW DASY Lab The framework facilitates and expedites test development an experiment can be set up in less than twenty lines of code The framework function calls are portable between programming languages The Linux software package includes DAQLib Library for writing programs using PowerDNA IO modules cubes UeiPalLib Platform abstraction library needed for building the DAQLib DAQLib_Samples Example programs demonstrating how to use the DAQLib to work with various layer types Instructions on use can be found in the readme txt of the package The hardware PowerDNA cube is composed of External casing in two compact sizes Core Module 3 I O Layers 3 95 x 4 1 x 4 0 Core Module 6
96. rties STEP 9 Click on the Gateway tab Make sure the box labeled New gateway is blank TCP IP Properties STEP 10 Click the OK button to return to the Network control panel STEP 11 Click OK to exit the Network control panel STEP 12 Restart your computer if Windows gives you the option to do so Zs Copyright December 2012 Tel 508 921 4600 www ueidaq com Vers 3 6 Y a ed Date December 2012 File PowerDNA_Appendix fm DNA PPCx PowerDNA Cube Manual Index C modifying 12 C class network 13 M Configuring a Second Ethernet Card Under Win Mounting 22 dows 95 98 SE ME 80 N Configuring a Second Ethernet Card Under Win dows NT 78 Network mask 13 Network performance Configuring a Second Ethernet Card Under XP 72 improving 13 D P DHCP 13 Power supply DIN rail 22 for Cubes 9 DNA DR 22 PowerDNA Explorer 26 DNA PSU 24 9 R Documentation 2 Repairs 25 F Reset button 21 Field connections 22 Ss Firmware Self diagnostics 11 updating 19 Setup program 9 Front panel layout 11 show command 12 G Subnet 15 Gateway T i mask 13 Terminal emulation program 11 U I O layers Upgrades 25 modifying 25 oe IP address Windows default 12 Registry 10 modify 13 85 AAA A EE A IA E A A lt AA O Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date October 2010 File DNA_PPCx_ManuallX fm
97. s The above is a successful response A Request Timed Out message indicates error Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 Hnited Electronic Indusines Inc Date December 2012 File PowerDNA _Chap2 fm DNA PPCx PowerDNA Cube Manual Chapter 2 16 Installation and Configuration STEP 8 The Cube should now be configured as follows where NIC1 uses a straight through and NIC2 uses a cross over cable to the NIC In or a straight through cable will connect to NIC Out NIC1 192 168 1 10 Out to rest of network NIC2 192 168 100 192 168 100 2 STEP 9 You may now use PowerDNA Explorer to access the cube See Chapter 3 2 2 5 1 Trouble The following checklist may assist you in troubleshooting a Cube shootin 9 MV The PG Power Good LED is on the Cube plugged in using 9 36V DC V The green lights on NIC In or NIC Out are blinking CAT5e cable is connected M Use the command prompt to ping lt cube IP gt e g ping 192 168 100 2 Disable temporarily the firewall on the secondary NIC ba b Check the secondary NIC network settings c Check the cube s network settings Use MTTTY and hit Connect Press Enter to display the DQ gt or gt prompt No prompt indicates that you are not connected Verify that the serial cable is firmly connected to the RS 232 port Verify the settings 57600 baud no parity 8 data bits 1 stop bit Try COM1 CO
98. s of the same item the last settings are re displayed Thus if you made changes but did not write them to the device the changes are remembered Invoking the Read command will re read the device and overwrite the current settings in the settings panel Devices whose settings have changed but have not been written are displayed in bold italics in the tree to provide a visual cue Changed devices that become missing on a subsequent invocation of Scan Network turn red in the tree Unchanged items that become missing are simply removed from the tree The settings panel presents a set of controls that allow you to change the set tings of the device currently selected in the device tree The settings panel has the following controls when an IOM is selected in the tree lolx ae 001 05 Q Hast PC 10M_19675 10M_20977 O Copyright 2009 all rights reserved United Electronic Industries Inc Name iom_20977 Model 1008 FWVer 1 7 6 Sim 20977 i MAC 00 0C 94 00 51 C1 IP 10 102 226 87 Mode Configuration Figure 3 10 Example of IOM Settings Panel for a PowerDNA cube Name shows the IOM name It can be changed Model shows the model number of the IOM FW Ver shows the version of the firmware installed on the PowerDNA cube S N shows the serial number of the IOM Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap3 fm 31 DNA PPCx PowerDNA
99. s panel for the current device Read will replace those settings with the device s current settings after prompting for confirmation Store Config writes the currently selected device s changed settings to the device The button is disabled for devices that haven t been modified Store All Configs writes all of the changed devices settings to the devices The button is disabled if no devices have been modified Read Input Data is enabled when the currently selected device is an input device layer It reads the current input values to the device and causes them to be displayed in the settings panel Update Firmware loads a firmware update file to all connected PowerDNA cubes if Host PC is selected It updates only one PowerDNA cube when the specific PowerDNA cube is updated More details about this can be found in the section Updating firmware in a version 2 0 PowerDNA cube Note that writing certain configuration changes to a PowerDNA cube running firmware 2 0 16 will bring up a password dialog box More information about passwords can be found in the Interfacing to the CM module using a serial interface section of this manual PowerDNA cubes come with the default pass word set to powerdna A OSSOS Copyright 2009 alll rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap3 fm DNA PPCx PowerDNA Cube Manual Chapter 3 29 PowerDNA Explorer lx
100. sktop from Start gt gt Programs gt gt UEI gt gt PowerDNA gt gt PowerDNA Explorer STEP 4 Choose Network gt gt Scan Network STEP 5 Select the PowerDNA cube to be updated Supply power to the PowerDNA cube STEP 6 Select Network gt gt Update Firmware from the menu Update Firmware Ctrl F Figure 2 3Update Firmware Menu Item STEP 7 Click on Yes when you see the prompt Are you sure you want to update firmware STEP 8 Double click on the dq_ram S19 file STEP 9 Enter the password to continue More information about passwords can be found in the Interfacing to the CM module using a serial interface section of this manual PowerDNA cubes come with the default password set to powerdna Authenticate IOM_00000 x Enter user password to unlock IO module 10M_00000 powerdna Figure 2 4Password Dialog Box EA O ae O Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 pitied Electronic Indusintes Ine Date December 2012 File PowerDNA _Chap2 fm DNA PPCx PowerDNA Cube Manual Chapter 2 21 Installation and Configuration STEP 10 Wait for the progress dialog to complete The PowerDNA cube will then be STEP STEP STEP STEP STEP STEP STEP STEP STEP updated and running the new firmware Firmware Update Progress x Writing flash of IOM_00000 i Cancel Figure 2 5 Firmwar
101. t Store Config to save them previous values can be re read from the layer using Network gt gt Reload Config Al 205 and Al 225 layer screens are same as the Al 201 layer but with different input ranges and number of channels In addition digital and analog output layers have settings specific to their layer types 3 2 8 Digital Input We ll use the DIO 405 as an example to start with then show how the DI 401 Output Layer DO 402 and DIO 403 are different Settings NOTE Use Network gt gt Read Input Data to see immediate input values in Input tabs Use Network gt gt Store Config to save values to the layer O Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap3 fm DNA PPCx PowerDNA Cube Manual Chapter 3 35 PowerDNA Explorer erDNA Explorer Doute o Doug Doug pout Figure 3 13 Example DIO 405 Layer Inputs Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries ifie Date December 2012 File PowerDNA _Chap3 fm DNA PPCx PowerDNA Cube Manual Chapter 3 36 PowerDNA Explorer 2 PowerDNA Explorer A x File Network View Help E A JANE ir lom_20977 Moder DI0 405 lt 0 DIO 405 Info D In Out 12 input 12 output lines SN 0023192 A Mfg Date Jan 21 2005
102. t December 2012 Tel 508 921 4600 www ueidaq com Vers 3 6 Y e Ad Date December 2012 File PowerDNA_Appendix fm STEP 9 STEP 10 STEP 1 STEP 2 STEP STEP STEP STEP oa p STEP 7 S O Copyright December 2012 Y United Electronic Industries Inc DNA PPCx PowerDNA Cube Manual Select Network Protocol Click the OK button to return to the Network control panel then click the OK button again to exit the control panel Restart your computer if Windows gives you the option to do so Then continue with Configure TCP IP Configure TCP IP From the Start menu select Settings and then Control Panel Double click on the Network icon Click the Configuration tab if it is not already selected In the box labeled The following network components are installed select TCP IP TCP IP is listed at least twice so choose the one followed by the name of your second Ethernet card do not choose TCP IP gt Dial up Adapter Click the Properties button In the TCP IP Properties window click on the IP Address tab Make sure that Specify an IP address is selected Enter 192 168 100 1 for IP Address and 255 255 255 0 for Subnet Mask TCP IP Properties Click on the DNS Configuration tab Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA_Appendix fm DNA PPCx PowerDNA Cube Manual STEP 8 Select Enable DNS Make sure the Host and Domain information is blank TCP IP Prope
103. t value of output pin 0 17 DQ_STR_IRQ Read as 1 if interrupt was requested 0 16 DQ_STR_CRH Report 1 if data is available in CRH 0 15 DQ_STR_CRL Report 1 if data is available in CRL 0 14 DQ_STR_IFE Report 1 if input FIFO is empty 0 13 DQ_STR_IFH Report 1 if input FIFO is at least Y full 0 12 DQ_STR_IFF Report 1 if input FIFO is full 0 11 DQ_STR_OFE Report 1 if output FIFO is empty 0 10 DQ_STR_OFH Report 1 if output FIFO is at least full 0 9 DQ_STR_OFF Report 1 if output FIFO is full 0 O Copyright 2009 all rights reserved United Electronic Industries Inc 0x2000 WR CTO_CTR CTUO Control Register The CTU Control register is used to set and control some parameters of the operation mode of the counter timer via specific bits and bit fields Note that the generic interrupt mask enable control status is reported via layer IER 0x1C IMR 0x20 ISR ICR 0x24 registers Layer specific bits are described later in the section Status conditions that lead to the interrupt request are enabled dis Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap5 fm 64 DNA PPCx PowerDNA Cube Manual Chapter 5 Programming Layer specific Functions abled via CTx_CTR register The following are the DQ_CTO_CTR bit descriptions for the CTUO register Bit 31 Name DQ_CTR_EN Description Enable 1 Disable 0 counter register When disabled CR along with pre scaler and de bouncer
104. ter the commands upuser lt CR gt update Enter go to complete the firmware update procedure and return to the DQ gt prompt Under DNA PPC5 and DNA PPC8 Establish communications between the PC and a Cube over the serial link Press the hardware Reset switch on the front of the Cube to reset the CPU Layer or type reset all STEP 3 While the Cube is starting up again Press ESC to go into u_boot Copyright 2009 all rights reserved United Electronic Industries Inc Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap2 fm DNA PPCx PowerDNA Cube Manual Chapter 2 22 Installation and Configuration STEP 4 Type the command to erase firmware download area in the Flash memory gt erase all gt loads romimage mot loads stores firmware into the flash while downloading it STEP 5 Transfer the Motorola firmware file Use Transfer Send File and select Program FileslUENPowerDNAl Firmware_PPC romimage_3_x_y mot A progress bar will appear in the lower left corner of MTTTY indicating progress STEP 6 Wait for the upload to complete it may take a few minutes STEP 7 After the process finishes enter the fwj mp command The PowerDNA cube will then be updated and running the new firmware At this point only the PG light on the cube remains lit 2 3 Mounting and Mount the Cube directly to the application hardware either by screwing it field directly to the machine or by
105. the packages necessary are installed d Companion Documentation Quick Start Guide Configuration amp Core Module I O Layer Manuals Low level Programming Guide e SDK includes lib for C Java examples and Sun s JRE The SDK is not the UeiDaq Framework f PowerDNA Apps PowerDNA Explorer MTTTY g PowerDNA Components incl DLL files h PowerDNA Firmware i Click Next to continue through the dialogs j Click Finish to complete installation restart the computer This Software Suite installed the bare minimum tools needed in later steps MTTTY PowerDNA Explorer and the low level driver UEIDAQ Framework provides the structure for developing applications under C C C VB NET ActiveX VB6 Delphi MATLAB LabVIEW DASYLab LabWindows CVI OPC and other programming languages NOTE Because the installation process modifies your Windows registry you should always install or uninstall the software using the appropriate utilities Never remove PowerDNA software from your PC directly by deleting individual files always use the Windows Control Panel Add Remove Programs utility B Software Install Linux Linux The PowerDNA_ tgz file in the CD Linux folder contains the software package for Linux To extract the file to a local directory enter tar xjvf path to powerdna tgz Follow the instructions in the readme txt contained therein O Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers
106. to highlight quick methods to get the job done or to reveal uncommon knowledge and ideas NOTE Notes alert you to important information CAUTION Caution advises you of precautions to take to avoid injury data loss or a system crash Text formatted in bold typeface generally represents text that should be entered verbatim For instance it can represent a command as in the following exam ple Instruct operator of how to run setup using a command such as setup exe Other PowerDNA Documentation This PowerDNA User Manual is one part of the documentation set available for the PowerDNA system We offer other resources you might want to read before programming an application They are available either on the PowerDNA Soft ware Suite CD or can be downloaded from the UEI web site In particular we recommend the PowerDNA API Reference Manual Pow erDNA Quick Start Manual UEIDAQ Framework Reference Manual UEIDAQ Framework User Manual and the UEIDAQ Framework Getting Started Manual Feedback We are interested in any feedback you might have concerning our products and manuals Comments and recommendation can be sent by email to sup port ueidaq com This chapter provides an overview of the key features of the PowerDNA sys tem and how the system works Thank you for purchasing a PowerDNA Cube system We designed this product Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap1 fm DNA PP
107. ture start Min Gate Pulse Width 0 psec _ Input Pre inversion Min Clock Pulse Width 0 psec _ Gate Pre inversion _ Output Post inversion Relative Position counts Figure 3 23 Example Quadrature controls eee Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap3 fm 42 DNA PPCx PowerDNA Cube Manual Chapter 3 43 PowerDNA Explorer Counter 0 mode Bin Counter M Start Min Gate Pulse Width 0 psec _ Input Pre inversion Min Clock Pulse Width 0 psec _ Gate Pre inversion Prescaler Value 33 _ Output Post inversion _ Use External Clock Counter Value Figure 3 24 Example Bin Counter controls Counter 0 mode PWM y Start Duty Cycle 50 _ Output Post inversion Output Frequency 1000 Hz Actual Freq 1000 Hz Figure 3 25 Example Pulse Width Modulation PWM controls Counter 0 mode Pulse Period start Min Gate Pulse Width 0 psec _ Input Pre inversion Min Clock Pulse Width 0 psec _ Gate Pre inversion Period Counter 0 _ Output Post inversion Positive Count Period Frequency Hz Nenative Count Perind Figure 3 26 Example Pulse Period Controls After setting the configuration for a counter you can choose Network Store Config to store the settings on the device Clicking the Start button will also write you configuration to th
108. until you return to the Network Connections window STEP 7 Close the Network Connections window D Using the Windows XP Alternate Configuration Setting If you re using a computer with only one Ethernet port such as a laptop you can configure Windows XP to automatically switch settings depending on which network it s connected Windows XP users have the ability to configure a second IP address setting under the Control Panel that will allow Windows to pick the correct computer IP setting based on the device that it finds connected to the Ethernet port Under this configuration your primary IP setting is configured for Obtain IP Address Automatically for connection to your company Network and your secondary IP setting Alternate Configuration is configured for 192 168 100 1 with a subnet mask of 255 255 255 0 for connection to the PowerDNA cube or DNR 12 The following steps allow you to configure your alternate IP address starting at the Control Panel STEP STEP STEP STEP STEP STEP STEP STEP STEP Double click on Network Connections Double click on Local Area Connections Click on the Properties button Select Internet Protocol TCP IP and click on the Properties button Select the Alternate Configuration tab Select User Configured Enter 192 168 100 1 for the IP address Enter 255 255 255 0 for the Subnet mask NE E m Close all open configuration windows using OK or Close Use the following screen to configure the Alt
109. urement will be accessible only after specified number of periods on the incoming signal are detected Start of the period is assumed to be a rising edge of the de bounced input CLKIN line 0x201C RD CTO_CRH CTUO Capture Register HIGH This 32 bit register is used to store results of the measurements in 7 or N period measurement modes In N periods N is defined by the value stored in the PC register measurement mode provides accumulated number of 66MHz counts during the positive part of all periods measured 0x201C WR CTO_CRO CTUO Set Value of Compare Register 0 32 bit compare register zero CRO is used to define shape of the output signal In all modes except quadrature encoder and measurement modes counter reg ister CR counts up from the value loaded in LR register and output toggles from low to high when CR CRO Depending on the other configuration parameters selected counter may continue count restart itself or stop when value of the CR reaches value stored in CRO register CRO may be used in conjunction with Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap5 fm 5 6 2 FIFO Access O Copyright 2009 all rights reserved United Electronic Industries Inc DNA PPCx PowerDNA Cube Manual Chapter 5 70 Programming Layer specific Functions CR1 for the complex PWM waveform generation 0x2020 RD CTO_CRL CTUO Capture Register LOW 32
110. ut FIFO FIFOO Count read Register DQ_CTU_FIRQI Input FIFO IRQ CTU Input FIFO FIFOO IRQ write Level DQ_CTU_FDTI Input FIFO Data ICTU Input FIFO FIFOO Data In write Register DQ_CTU_FCNTO Output FIFO CTU Output FIFO FIFO1 Count read Count Register O Copyright 2009 all rights reserved United Electronic Industries Inc Tel 508 921 4600 Date December 2012 Vers 3 6 File PowerDNA _Chap5 fm www ueidaq com DNA PPCx PowerDNA Cube Manual Chapter 5 Programming Layer specific Functions Register Offset Name Description DQ_CTU_IRGO Output FIFO IRQ CTU Output FIFO FIFO1 IRQ level reserved write Level DQ_CTU_FDTO Output FIFO Data CTU Output FIFO FIFO1 Data Out read Register DQ_CTU_ISR Interrupt Status ISR shows current status of the enabled interrupts read Register DQ_CTU_IER Interrupt Enable JIER is used to specify specific interrupt conditions should generate Register an interrupt write DQ_CTU_ICR Interrupt Clear ICR allows clearing of fired interrupt bits If interrupt condition Register persists interrupt will be fired again write DQ_CTU_FDDO Output Data FIFO FDDO is a reserved register used for the time sequencer version of Register CTU implementation write DQ_CTU_TESTO Test RegisterO TESTO is a reserved test read only register In current implementation
111. w define DQ LNCL IRQ 11 define DQ LNCL NOWAIT 1 input or output subsystem subsystem high fire IRQ execute this step but don t wait for the next CV define DQ LNCL SKIP 1UL lt lt 25 execute this step and discard data for the next CV define DQ LNCL CLK 1UL lt lt 24 wait for the next channel list clock define DQ LNCL CTR 1UL lt lt 23 clock counter once define DQ LNCL WRITE 1UL lt lt 22 write to the channel but not a update AE A E EEE ee eee eee O Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 Hate es Ine Date December 2012 File PowerDNA _Chap5 fm define DO Hdefine DO define DQ define DO define DO define DQ define DQ_ define DQ define DQ define DQ define DQ define DQ define DQ Copyright 2009 all rights reserved United Electronic Industries Inc DNA PPCx PowerDNA Cube Manual Chapter 5 56 Programming Layer specific Functions LNCL UPDALL 1UL lt lt 21 update all written channels LNCL TSRQ 1UL lt lt 20 copy TS along with data i 2 LNCL_ SLOW 1UL lt lt 19 slow down operation LNCL_RSVD2 1UL lt lt 18 reserved LNCL_RSVD1 1UL lt lt 17 reserved LNCL_RSVDO 1UL lt lt 16 reserved LNCL_DIFF 1UL lt lt 15 differential mode There are a few helper macros defined to simplify setting gain and subsystem flags LNCL_GAIN G G
112. werDNA Explorer 101 File Network View Help ANDA Host PC lom_20977 0 DIO 403 Mode DIO 403 a Info D In Out 48 channel 6 ports of 8 SN 0021391 Mfg Date Nov 30 0002 Cal Date Nov 30 0002 Enabled Figure 3 15 Example of DIO 403 Layer Inputs 2 PowerDNA Explorer Pale ES File Network View Help 26 6 181 Hast PC lom_20977 lt 0 DIO 403 DIO 403 Info D In Out 48 channel 6 ports of 8 SIN 0021391 Mfg Date Nov 30 0002 Cal Date Nov 30 0002 Z Enabled Output Q QO o OOC olooooos olooooos olooooos Hoo oooooos ooooooe oloooools 9 on Figure 3 16 Example of DIO 403 Layer Outputs Input Output Configuration Initialization Shutdown tabs switch between settings for init and shutdown states as well as operation mode configuration and display of current data Input Output tabs get set the current input output values They contain the fol lowing columns O Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap3 fm 2 PowerDNA Explorer File Network View Help DNA PPCx PowerDNA Cube Manual Chapter 3 PowerDNA Explorer e The unnamed first column contains
113. ws the manufacturing date of the layer e Cal Date shows the date of the last calibration done to the layer Enabled is a checkbox that when unchecked excludes the device from configuration The device is excluded from the Store All Configs com mand and the Reload Config command is disabled Also the device appears gray in the tree All devices are enabled by default Tel 508 921 4600 www ueidaq com Vers 3 6 Date December 2012 File PowerDNA _Chap3 fm DNA PPCx PowerDNA Cube Manual Chapter 3 34 PowerDNA Explorer e Select Network gt gt Read Input Data to update the Value column of any layer as shown below 2 PowerDNA Explorer Ox File Network View Help POODE Hast PC 3 A 10m_19675 i Al 201 Q lOM_20977 E E A In 24 channel 0 A 201 0022432 lt S 1 Al 201 E 2 A 201 Mfg Date Aug 1 2004 e 3 A 201 Cal Date Aug 17 2004 iv Enabled Input Range 15 15 Volts Name AlnO Aln1 i Aln2 Aln3 Aln4 Aln5 Alnb Aln Aln8 Alng Alnio Aln11 Aln12 Aln13 Aln14 Aln15 Aln16 Alni Alnta Figure 3 12 Screen from Network gt gt Read Input Data At the screen shown above you can add edit channel names After editing names choose Network gt gt Store Config to save changes to the layer This is true for all layers Also if you have changed a configuration value but have not chosen Network gt g
114. y individual addresses as well as address ranges The specified items appear in a list that can be added to and deleted from This list defaults to a single range item that specifies the range 192 168 100 2 192 168 100 10 Edit Address Range x To make a single address leave the to field blank Address 192 168 100 2 to 192168 100 10 UDP Port 6334 ox e Figure 3 4 Edit Address Ranges Dialog Box Scan Network scans the network for devices and populates the device tree How much of the network is scanned depends on the settings in the Network OUOU SSS Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 3 6 United Electronic Industries Inc Date December 2012 File PowerDNA _Chap3 fm DNA PPCx PowerDNA Cube Manual Chapter 3 28 PowerDNA Explorer Ranges dialog PowerDNA Explorer File Network Wiew Help fs e e 6 E Host PC z IOM_209FF IP 10 102 226 7 Figure 3 5 After a Network gt gt Scan Network If you choose Scan Network when the device tree is already populated any new devices discovered will be added to the tree Any existing devices that are missing will be removed from the tree unless you have made unsaved changes to such a device s configuration in which case it will be marked in the tree as missing Reload Config re reads the configuration of the current device selected in the Device Tree If you have made changes to the settings in the setting

DNA PPCx PowerDNA Cube Manual - United Electronic Industries

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