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PA72 User Manual

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1. S wen normal pretriggred PA72BUS 6 7 Memory The module contains a 8 M word capture memory The capture memory array size must be a multiple of two For more information about the memory operation please see section 4 3 P PA72 Series User manual Rev 1 10 Page 24 of 51 6 8 Module auto calibration For optimum performance it is recommended to observe a warming up period of at least one hour after power up The module auto calibration should be run at least every 3 months An auto calibration can be started with the driver function pa72_Calibrate or using the calibration software tool by PA72 Series User manual Rev 1 10 Page 25 of 51 7 PA72G14180 waveform generator module 7 1 Board block diagram The PA72G14180 module is a 14 bit 180MSps Arbitrary Waveform Generator for high frequency waveform generation H features differential outputs with independently configurable output offsets The module has four proportional ranges Clock and trigger are sourced by the main board cal_ Or Q lt Proportional cal Range setting SEAN fdl 14 bit Ch haler DAC SS n os lt L30Mhz LPF address Filter switched HL Range i cal REF calbus ca 7 2 Output voltage and available signal ranges Clock Distribution Mainboard PA72 Control iH The common mode output voltage covers the maximum signal
2. Mainboard PA72 calbus Figure 1 PA72D14130 block diagram 8 2 Input voltage and available signal ranges The common mode input voltage independent of the chosen signal range Range Input Range Vpp Range Vp Common mode input voltage number range 0 7 2 Vpp 3 6 Vp 3 6V DC 1 5 4 Vpp 2 7 Vp 3 6V DC 2 3 6 Vpp 1 8 Vp 3 6V DC 3 2 7 Vpp 1 35 Vp 3 6V DC 4 1 8 Vpp 0 90 Vp 3 6V DC 5 1 35 Vpp 0 675 Vp 3 6V DC 6 0 90 Vpp 0 450 Vp 3 6V DC 7 0 675 Vpp 0 3375 Vp 3 6V DC The range is set with the driver function pa72_SetRange The voltage difference between the inputs can be the given input range in Vp 8 3 Filter section One of the two third order Butterworth low pass filters can be switched into the signal path The available filters have a cut off frequency of resp 15MHz and 30MHz A filter bypass path may also be chosen The filter path is configured with the pa72_SetFilter driver function B PA72 Series User manual Rev 1 10 Page 29 of 51 8 4 Clocks and trigger In configuration mode the module can accessed from the PA72 mainboard The address counters and memory logic run on the 33MHz PCI bus clock The ADC however is always connected to the PA72 sample clock When a single voltage is measured with the ADC using pa72_GetVoltage there should be a valid clock running at the
3. 1 for each module 16 bit 2kHz to 400MHz PLL clock with backplane 10MHz sync capability DC to 400MHz 8M words 0 32Vp 0 425Vp 0 64Vp 0 85Vp 1 28Vp 2 56Vp 0 64Vp 0 85Vp 1 28Vp 1 9Vp 2 56Vp 5 12Vp 2 56 to 2 56V gt 14 bit resolution 500 Single Ended or Differential DC to 80 140MHz depending on range Bypass 30MHz 60MHz 250ynV 0 1 of range 0 1 of value 0 006 69dB f out 1MHz BW 0 80MHZz 67dB f out 10MHz BW 0 80MHz 84dB f out 1MHz 73dB f out 10MHz 82dB f out 1MHz Additional power requirement for a single module 3 3 Volt 5 Volt 12V 12V PXI 980 mA 610 mA 55 mA 55 mA 11 4 Specification PA72D16180A module Channels Resolution Sample rate Pattern depth Input configurations Input ranges Vp DC offset voltage Input bandwidth Input filters Absolute accuracy Relative accuracy SNR 180Msps 500 4Vpp diff SNR 180Msps 500 4Vpp diff THD 180Msps 500 4Vpp diff THD 180Msps 500 4Vpp diff SFDR 180Msps 500 4Vpp diff was 1 for each module 16 bit 1MHz to180MHz 64M words 500 or 1MQ AC or DC coupled Differential or Single Ended 500 0 256 0 384 0 512 0 768 1 024 1 536 2 048 3 072 1MQ 0 256 0 384 0 512 0 768 1 024 1 536 2 048 3 072 5 12 7 86 10 24 15 36 the input range 16 bit resolution DC to 95 175MHz typical depending on range
4. Figure 6 Internal single write action Ons 25ns 50ns 75ns 100ns 125ns 150ns 175ns ie 225ns LE Pa ee Sie i oP ei Tn STE all UP als ll Wd all Se te ee TI ek Was et H EK Ma HS Il PAZ3 Module IO vbd single read action wait 0x00 clk KH A A g 4 P rd_en N V P gt Figure 7 Internal single read action Ons 25ns 50ns 75ns 100ns 125ns 150ns 175ns 200ns a ILE Oa Ce a Ge Gs ee Od es Fem ey Hc De TI PT OS ee kb ie Me EB Pei a SDI aI eS ake PA72_Module_l0 vhd single read action with latency of 2 clk S j Foo m 4 H rd_en A Pi S Gei Figure 8 Internal single read action with latency 2 f hy PA72 Series User manual Rev 1 10 Page 36 of 51 9 3 2 2 Burst read and write actions Beside the single read and write actions the PA72 mainboard can also setup a DMA transfer to the host The DMA transfer is completely done by the PA72 mainboard and the daughter cards only sees a multiple read action or burst transfer A burst transfer is setup to one address For example During the burst transfer to a memory a counter needs to count the memory address The following pictures showing the burst write and read timing All FPGA actions are rising edge clocked Ons I I I l 50ns 100ns 150ns 200ns 250ns 300ns eee S Comers ae 3 bk 3 II PA72_Module_lO vhd burst write action DMA start
5. 11 6 Specification PA72D14130 module Channels Resolution Sample rate Memory depth Input ranges span Input operating area Input configurations Input impedance DC offset voltage Input bandwidth Input filters Absolute accuracy Relative accuracy INL SNR 130Msps 3 2Vpp diff SNR 130Msps 3 2Vpp diff THD 130Msps 3 2Vpp diff THD 130Msps 3 2Vpp diff SFDR 130Msps 3 2Vpp diff hy PA72 Series User manual Rev 1 10 1 for each module 14 bit 1MHz to 1830MHz 64M Words 0 3375Vp to 3 6Vp in 8 ranges 3 6V to 3 6V Differential or single ended 10kO or 500 DC or AC 3 6V to 3 6V 65MHz typical Bypass 30MHz 15MHz 250UV 0 05 of range 0 1 of value 0 025 of range 66dB f in 1MHz BW 0 60MHz 64dB f in 10MHz BW 0 60MHz 78dB f in 1MHz 74dB f in 10MHz 80dB f in MHz Page 45 of 51 11 7 Specifications PA72DIOS6016 module FPGA Logic cells CLB Flip Flops Front connector Max TTL LVCMOS I Os Max differential inputs Max differential outputs I O voltages I O configurations DDR Memory size DDR Memory frequency Total block RAM Block RAM max frequency Differential signals as input only hy Xilinx Spartan6 XC6SLX16 14579 18224 VHDCI SCSI 5 2 5V and 3 3V LVTTL LVCMOS PCI SSTL B _LVDS LVPECL and more 1Gbit 800MHz 576kBit 320MHz PA72 Series User manual Rev 1
6. Bypass 60MHz 30MHz 250uV 0 1 of range 0 2 of value 0 006 69dB f in 1MHz BW DC to 80MHz 67dB f in 10MHz BW DC to 80MHz 85dB f in 1MHz 81dB f in 10MHz 83dB f in 1MHz Additional power requirement for a single module 3 3 Volt 5 Volt 12V 12V PXI 535 mA 1090 mA 0 mA 50 mA hy PA72 Series User manual Rev 1 10 Page 44 of 51 11 5 Specification PA72G14180 module Channels Resolution Update rate with PA72 clock Update rate external clock Pattern depth Output ranges Vp single ended DC offset voltage Output configuration Bandwidth Output filters Absolute accuracy Relative accuracy INL SNR 180Msps 3 2V gt diff SNR 180Msps 3 2V gt diff THD 180Msps 2 0Vp diff THD 180Msps 2 0Vp diff SFDR 180Msps 2 0V gt diff 1 for each module 14 bit 2kHz to 180MHz DC to 180MHz 64M words Four proportional ranges 409 6mV 819 2mV 1 6384V and 3 2768 V 2 56V to 2 56V 50Q Single ended or Differential DC to 9OMHz Bypass 30MHz 15MHz 250UV 0 1 of range 0 1 of value 0 025 of range 68dB f out 1MHz BW 0 70MHz 64dB f out 10MHz BW 0 70MHz 81dB f out 1MHz 70dB f out 10MHz 82dB f out 1MHz Additional power requirement for a single module 3 3 Volt 5 Volt 12V 12V PXI 605 mA 285 mA 40 mA 40 mA
7. V signal is the voltage programmed to the 14 bit signal DAC Vacbase1 is the voltage programmed to the 16 bit dc offset DAC connected to the positive output buffer Vacbasez2 iS the voltage programmed to the 16 bit dc offset DAC connected to the negative output buffer Vacbase iS programmed using driver function pa72_SetOffsetVoliage or pa72_SetOffsetVolitages The DAC output voltage Vsignai is either set by the contents of the stimulus memory or when the module operates in configuration mode directly with driver function pa72_SetVoliage 7 4 Filter section One of the two third order Butterworth low pass filters can be switched into the signal path The available filters have a cut off frequency of resp 15MHz and 30MHz A filter bypass path may also be chosen The filter path is configured with the pa72_SefFilter driver function 7 5 Clocks trigger and stimulus In configuration mode the module can be accessed from the PA72 mainboard The address counters and memory logic run on the 33MHz PCI clock The DAC however is always connected to the PA72 clock When a single voltage is programmed to the signal DAC using pa72_SetVoliage there should be a valid clock running at the PA72G14150 clock input Be sure that the PLL clock is initialized In case of direct clocking modus a valid clock source should be present at the PA72 front clock input In measurement mode the card memory cannot be accessed from the PA72 bus Now the memory addres
8. Appendix C Module dimensions Module side view rir 94 50 gt 79 50 68 50 55 50 Board edge to front Module front panel view zj 2 02mm Front edge to board bottom side edge ni lt 3 70mm Front edge to board top side edge A Re base board gt 112 85 79 30 55 30 68 30 31 2 44 30 7 1 lt gt 12 0 L hy PA72 Series User manual Rev 1 10 Page 49 of 51 Appendix E Cross reference A I address counter 7 13 14 19 24 27 30 instrument 5 analog edge triggering 10 L auto calibration 25 47 LED front 11 B baseboard 5 7 M Bus Address Range 40 measurement mode 7 11 12 13 14 19 20 24 27 e 28 30 memory 7 12 13 14 15 17 19 20 24 27 30 31 calibration 10 25 47 32 33 37 38 calibration ADC 10 11 47 module 5 7 calibration procedure 47 o capture memory 7 12 13 14 24 30 channel phase 19 operation mode 12 clock skew 8 9 clock sources 8 P clock synchronization 9 19 pa72d14130 29 common mode 21 22 23 pa72d16180 21 configuration mode 7 12 19 20 24 27 28 30 pa72d16180a 21 continuous mode 12 PA72DIOS6016 6 31 40 41 46 48 custom signal 17 pa72g14150 26 D pa72g16400 18 PLL 6 7 8 9 10 19 24 27 30 43 44 DC offset DAC 18 23 24 26 pre triggering 14 digitizer 14 bit 29 R digitizer 16 bit 21 DMA transfer 37 reference clock 6 8 driver 6 7 8 9
9. arraysize T izna 0 or signal Or E E EE Geen arraysize q q l sample periods r The use of the signal definition command is best described following some examples Example 1 Desired output signal on a PA72G16400 sine wave 3 84Vpp 1kHz fsamp 500kHz in 65536 samples Used range 2 56Vp The desired output stimulus signal is a sine wave 3 84Vpp centred in the output range of the signal AWG signal DAC Note that the DC offset DAC adds an extra offset independent from the signal definition The value of the dc offset Dac is therefore disregarded in this example There is only one harmonic so only one signal definition should be entered for this signal item The generating module is a PA72G16400 set in the 2 56Vp range In the sine definition the amplitude is defined in Volts peak The desired peak amplitude of a 3 48Vpp sine wave is 1 92V Only one sine is defined so use index number 0 index 0 The signal type is an analog sine type 3 The amplitude parameter param7 for the signal definition is calculated desiredAmplitude Vp _ 0 5 Amplitude Vpp param DACrange DACrange param EWE 0 75 2 56 The offset parameter param2 Offset Vo 10 lt p lt param 0 5 0 lt DACrange param2 0 5 Ouse 0 5 nae DACrange 2 56V The frequency of the sine wave is determined by the total number of samples param3 the number of periods param4 and the sample frequency param4 8
10. clk E Fi W idl wr_en ECH w data V DATAO Y DATA ys DATA2 X Dan X DAT Destination address written address_dec ADDRESS rd_en Figure 9 Internal burst write action Ons 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns III III III IR Hl 1 III Io III III PA72_Module_l0 vhd PA72 burst read action clk A y if H X V 4 rd_en Z P b P V ee em N H Gel addr_dec X ADDRESS il Figure 10 Internal burst read action Ons 50ns 100ns 150ns 200ns 250ns 300ns PA72_Module_lO vhd PA72 burst read action with latency 2 clk 4 By e P rd_en h 4 P H P H gt Figure 11 Internal burst read action with latency 2 hy PA72 Series User manual Rev 1 10 Page 37 of 51 9 3 3 Accessing the on board EEPROM Connected to the FPGA there is a Two Wire serial EEPROM To access this non volatile memory an 12C core is needed that converts the parallel interface to a 12C communication bus In the example files a working example core is used to access this device 9 3 4 Accessing the on board DDR2 SDRAM On the PA72DIOS6016 board a DDR2 memory available To access the DDR2 memory this FPGA uses the Xilinx Spartan6 dedicated embedd
11. generating There is a trigger latency between trigger active and actual DAC update This latency is divided in a fixed latency and a variable latency gt e Clock D A A Trigger gg ID K DAC output Eeer A lt gt lt gt N h tex Nxtek The fixed latency n 26 and is caused by a couple of register stages in the stimulus signal logic The variable latency his programmed in a hold off counter The hold off counter is set with driver function pa72_SetHoldOffCounter Note that the hold off delay h appears only the first trigger event after measurement at start of the stimulus generation When the trigger is set inactive only the fixed n latency is applied In measurement mode the stimulus signal repetition is determined by the setting of the running mode In the so called continues mode the stimulus signal is repeated until the trigger is disabled or the module is set in configuration mode In Counter mode the stimulus is repeated by the sum of values set in the settle measurement loop counters The following driver functions control this repetition pa72_SetContinuousMode Set module continuous mode When set to value 0 the loop counters determine the stimulus repetition counter mode When set to value 1 the stimulus is repeated until trigger is inactive or the module is set back in configuration mode pa72_SetSettleLoopCounier Set module settle loop counter value pa72_SetMeasuremen
12. phase number of samples etc Driver function pa72_SignalConfigure is used configure the signal pa72_SignalConfigure vi index type param1 param2 param3 param4 param5 parame where index Vilnt32 type ViUInt32 param1 6 ViReal64 In this function analog signals should be normalized between 0 and 1 Parameters index The signal definition index number it selects the signal definition to be defined Value 0 9 All signals configurations will be added Value 1 Use value 1 to clear all 10 configurations hy PA72 Series User manual Rev 1 10 Page 14 of 51 type defines the signal type 0 clear signal configuration for this index analog ramp defined by endpoints and number of steps 11 digital ramp defined by endpoints and number of steps param1 start value of ramp param2 end value of ramp param3 number of ramp steps param4 settle steps at start of ramp param5 repeat ramps param6 not used 2 analog ramp defined by start point increments and number of steps 12 digital ramp defined by start point increments and number of steps param1 start value of ramp param2 increment value param3 number of ramp steps param4 settle steps at start of ramp param5 repeat ramps total number of the ramps in this definition param6 not used 3 analog sine wave 13 digital sine wave param1 amplitude peak value not peak peak param2 offset param3 number of samples param4
13. Ki SSTL18_II ODT K6 SSTL18_II H2 SSTL18_II CLK G3 DIFF_SSTL18_II H1 SSTL18 1l CLK Gi DIFF_SSTL18_II DQ6 J3 SSTL18_II Table 4 DDR2 FPGA pin locations hy PA72 Series User manual Rev 1 10 Page 33 of 51 9 2 6 SCSI connector in and output The FPGA has 32 differential pairs routed to the SCSI connector They are connected to FPGA BankO and Bank1 The IOs are programmable in the FPGA firmware as in or outputs and as well single or differential bus standards Due to IO resource limitations in the FPGA bank 1 does not support differential output standards The IOs that are connected to bank 0 indicated in purple are the only lines that can also be used as a differential output such as LVDS Pin Description FPGA pin location Pin Description FPGA pin location 1 DO_P I O C15 35 DO_N I O A15 2 D1_ P I O D11 36 D1_N I O C11 3 D2_P I O B16 37 D2_N I O A16 4 D3 P I O F11 38 D3_N I O E11 5 D4 P I O C17 39 D4_N I O C18 6 D5 P I O G11 40 D5_ N I O F10 7 D6_P I O D17 41 D6_N I O D18 8 D7_P I O B11 42 D7_N I O A11 9 D8 P I O E16 43 D8_ N I O E18 10 D9 P I O B12 44 D9 N I O A12 11 D10_P I O F17 45 D10_N I O F18 12 D11_P I O B14 46 D11_N I O A14 13 D12_P I O G16 47 D12_N I O G18 14 D13_P I O D12 48
14. PA72D14130 clock input Be sure that the PLL clock is initialized In case of direct clocking modus a valid clock source should be present at the PA72 front clock input In measurement mode the card memory cannot be accessed from the PA72 bus Now the memory address counter is clocked by the clock from the PA72 main board The actual clock source selection is set on the main board The applied clock signal from the Base board will be used as sample clock and as a clock for the capture memory address counter and will not be divided on this module The applied clock frequency is equal to the sample frequency The trigger signal comes from the base board where it is synchronized with the sample clock of module 1 before being distributed to both modules by PA72 Series User manual Rev 1 10 Page 30 of 51 9 PA72DI0S6016 DIO module 9 1 Board description The PA72DIOS6016 is a multifunctional digital design core The FPGA allows for implementing many different custom applications The connector has 64 Input Output pins which can be assigned as TTL I O or as differential inputs 20 of these pins also support differential output mode 128 MByte of DDR2 memory is available to the FPGA and an onboard EEPROM allows for storing values in non volatile memory The I O bank voltage can be FPGA selected between 2 5 and 3 3 Volt PLL Lock Timing Cal 1Gbit 800MHz Xilinx Spartan 6 XC6SLX16 PA72 local bus pp a E o VI See
15. available pa72_SetMemoryAddress Configure instrument memory address counter position pa72_SetMemoryEndAddress Configure instrument memory end address position pa72_SetMemoryReturnToAddress Configure instrument memory return to address pa72_SetPreTriggerModeStatus Enable or disable pretrigger mode pa72_SetPreTriggerPostCounter Configure the pretrigger counter pa72_SetMemoryPointers Configure the pretrigger mode using the above functions pa72_GetAnalogSignal Read captured signal from capture memory pa72_GetAnalogSignal Pretrig Read captured signal in pretrigger mode from capture memory 4 4 Stimulus signal definition The stimulus signal definition is a result of a summation of one or more signal definitions The figure shows the sequence to define a signal and load them in the module stimulus memory First the signal should be configured Depending on the measurement type the signal can be configured as a ramp a sine a triangle or a square wave A signal can also be the sum of up to ten separate signal definitions pa72_SignalConfigure pa72_SignalToModule pa72_SetMemoryReturnToAddress pa72_SetMemoryEndAddress FILL MEMORY pa72_SetMemoryAddress Initiate address counter mm pointer P wb Io Point at first stimulus stimulus data point signal ready for use pointer gt A signal definition is a collection of parameters that define the type of signal and accompanying signal properties like amplitude
16. c H 5 KI D E O ke a be 5 2 UO voltage aa EEPROM selection 3 3Ve 512Kbit Figure 2 PA72DIOS6016 block diagram 9 2 Hardware description 9 2 1 I O voltage selection and clamping The PS72DIOS6016 module supports multiple I O standards such as LVTTL LVCMOS PCI SSTL B LVDS and LVPECL When the I Os are configured as output the differential I O standards are not available for all pins The FPGA I O bank voltage can be programmed to 2 5V or 3 3V this is controlled by a line from the FPGA Although the maximum I O voltage for the FPGA is 3 3V the front inputs can accept 5V TTL levels thanks to the internal input protection clamping circuit Please note that when selecting 2 5V I O levels for the FPGA the levels applied at the front are not clamped down to 2 5V but should match the selected standard P PA72 Series User manual Rev 1 10 Page 31 of 51 9 2 2 Module Clocking There are multiple clock inputs that can be used to clock the logic from the FPGA The PA72 baseboard drives two clocks to the DIOS6016 the 33 MHz local bus communication clock and a low jitter module clock that can be programmed up to 900MHZz This clock is connected to the FPGA and also has a direct connection to the front SCSI connector see Figure 2 On the DIOS6016 module there is a 200MHz LVPECL oscillator that can be used for the DDR2 memory clocking or other non synchronized functions Some pins on the front SCSI c
17. green blinking 5Hz Channel is connected and running in measurement mode trigger active red Remains red after an initialization error hy PA72 Series User manual Rev 1 10 Page 11 of 51 4 General module memory structure and signal definition In general all modules described in the subsequent chapters have the same digital hardware i e memory and trigger structure and signal definition method The 16 bit modules PA72G16400 and PA72D16180A are equipped with a 8M words SDRAM memory The 14 bit modules have a larger 64M words DDR memory Basically the concept of operation and control for both memory types are the same This section describes the operational concept the general memory architecture how to define stimulus signal and the way to prepare a capturing module i e a digitizer module for capturing a signal 4 1 Module Operational modes Basically a module has two operational modes Configuration mode and Measurement mode In configuration mode the module can be configured Configuration of stimulus memory contents Memory counter parameters clock and trigger configurations can be accessed After complete configuration the module can be switched to measurement mode In this mode the module is ready to receive a trigger and start the measurement While in measurement mode the module memory cannot be accessed by driver functions Once the measurement is completed the instrument is switched back to configuration mo
18. input can be set separately to one of the following input configurations The pa72_SeitConnection driver function selects the input configuration pa72_SetConnection vi connect Parameters vi visa session connect see table Connect can be seen as an 8 bit value of which the least significant nibble represents the P input configuration The highest nibble represents the N input configuration Value shifted 4 bits to the left which is a 16x multiplication Nibble Connect Value Connect Value Input configuration value N input P input 0x0 Opec 0x00 Opec 0x00 Open input is loaded 1MQ AC coupled 0x1 16pec 0x10 1 pec 0x01 500 DC coupled 0x2 32pec 0x20 2pec 0x02 500 AC coupled 0x3 48pec 0x30 3pec 0x03 Input connected to DC Offset DAC 0x4 64pec 0x40 Ange 0x04 Input internally connected to GND 0x5 80pec 0x50 5pec 0x05 1MQ DC coupled 0x6 96pec 0x60 6pec 0x06 TIMO AC coupled Examples 1 To connect input N to the DC Offset DAC and input P 500hms DC Connection 48pec 1 pec 49pec or 0x30 logically OP ed with 0x1 0x31 2 To connect input N and input P 500hms AC Coupled Connection 32pec 2pec 34pec or 0x20 logically OR ed with 0x2 0x22 3 To connect input N to GND and input P 50Ohms DC Coupled Connection 64pec 1 pec 65pec or 0x40 logically OR ed with 0x1 0x41 Because the available input ranges are dependent on the input i
19. of calibration data or other parameters The I2C device address for the EEPROM on this board is bin 1010 000 IOC SCL B3 LVCMOS IOC SDA A2 LVCMOS Write Protect A3 LVCMOS Table 3 EEPROM FPGA pin locations DIOS6016 two wire serial EEPROM I2C Atmel AT24C512B 512kbit 65k x 8bits dh PA72 Series User manual Rev 1 10 Page 32 of 51 9 2 5 On board DDR2 SDRAM On the DIOS6016 board a DDR2 memory is available for volatile storage of large amounts of data The DDR2 memory is connected to FPGA bank3 The FPGA has a dedicated embedded memory controller block MCB connected to this port Table 4 shows the DDR2 to FPGA pin locations DIOS6016 DDR2 Memory type Elpida EDE1116AEBG 1 Gbit 64M x 16bits SSTL18_II SSTL18_II J6 SSTL18 1l DQ8 M3 SSTL18_II H5 SSTL18_Il Dag M1 SSTL18_II L7 SSTL18_II DQ10 N2 SSTL18_Il F3 SSTL18_II DQ11 N1 SSTL18 H H4 SSTL18_II DQ12 T2 SSTL18 H H3 SSTL18 1l DQ13 T1 SSTL18_Il H6 SSTL18_II DQ14 U2 SSTL18_Il D2 SSTL18_II DQ15 U1 SSTL18_Il Di SSTL18_II LDQS L4 DIFF_SSTL18_II F4 SSTL18 1l LDQS L3 DIFF_SSTL18 II D3 SSTL18 1l UDQS P2 DIFF_SSTL18_II G6 SSTL18_Il UDQS P1 DIFF_SSTL18 II F2 SSTL18_II LDM K3 SSTL18_II F1 SSTL18 1l UDM K4 SSTL18_Il E1 SSTL18_II WE E3 SSTL18_II L2 SSTL18_II RAS L5 SSTL18_II L1 SSTL18 1l CAS K5 SSTL18_II K2 SSTL18_Il CKE H7 SSTL18_Il
20. range plus the 2 56V offset voltage range for each output In hardware there are 4 switched signal ranges 3 2768Vp 1 6384Vp 819 2mVp and 409 6mVp single ended values but the range can be set proportionally by adjusting the signal DAC reference voltage Depending on the desired range the most DAC efficient switch setting and reference DAC combination is set by the driver The range is set with the appropriate software driver function pa72_SetRange The prompted voltage is the voltage single ended Voltage peak value Example pa72_SetRange vi 3 10 sets a voltage range of 3 10 Vp single ended This is equal to 6 20Vpp single ended measured between one output and GND and 12 4 Vpp differential measured between the two outputs The voltage difference between the outputs is twice the programmed output voltage Note mentioned range voltages apply to an open output 7 3 DC offset The DC offset is added by a so called DC offset DAC Each output has an DC offset DAC that can be set independently The voltage range is from 2 56V to 2 56V programmable in a 78 125 uV resolution The offset is always connected to the signal path The output voltage is composed as follows outpos Vignal SS Le LEE V igual Victasse by PA72 Series User manual Rev 1 10 Page 26 of 51 Voutpos is the output voltage relative to ground on the positive force output Voutneg is the output voltage relative to ground on the negative force output
21. results are stored The architecture is a bit different from the stimulus memory The return address pointer is loaded immediately at the start of the measurement when the module enters measurement mode So there is no need to assign the return to address It is simply equal to the address value at the start of the measurement The end address should still be assigned The converter results are stored between the start and end address CAPTURE MEMORY a E ADDRESS COUNTER P fo fo D 2 H a The capturing can be in two modes Normal capturing mode and pre triggered capturing mode In normal capturing mode the capturing stops when the address counter reaches the defined end address A trigger event starts the capture The trigger event may be delayed by a hold off counter B PA72 Series User manual Rev 1 10 Page 13 of 51 In pre triggered capturing mode the capturing starts immediately after the module is set in measurement mode When the address counter has reached the end address the address counter is reloaded with the start address The contents of the memory is overwritten with new data On a trigger event the current address counter value is stored in a trigger address register Now a pre loaded pre trigger counter starts to count down The Capturing stops when the pre trigger counter has reached zero For a capture memory the following driver functions are
22. 0 9 PA72DIOS6016 DIO ul TN 31 9 1 ele Be Ee le EE EN 9 2 Hardware GeSCription ecccccceesenceceeeeeeeeeeeeeeeseeeeeseeecaaesesecaaeseseaaeeesecaaeeeseeaeseseeseneeeeesenaeess 31 9 2 1 I O voltage selection and camping 31 32 Mod le Clocking as sisikian eenean easda aaan AEA aa SCANARE Aaa ENAK eege EEEREN 32 9 2 3 Module ge Le ne es ee T 32 9 24 1120 EEPROM ege icasi neinean oeni naonin eaaa EENS EES EEN EKRA ERNES 32 9 2 5 On board DDR2 GDDAM cece ee eeeeeeaaeeeeeeeseeeecaaeeesaaeseeeeeseaeeesaeeeeaeeeneeeee 33 9 2 6 SCSI connector in and output cee ceeece cece ceteeeeeeeeeeee cents cage eeeeaeeeeeeeseeeesaeeetaeseeneeee 34 9 3 FPGA logic description ccccceceeeeeenceceeeeeeeaeeeeaae cence ceaeeeeaaesaeaeeceeeeeaaesgeaaeeeeeeseaeeeeaaeseeneeee 35 9 3 1 Top file and Constraints file ccccccececececeeeeeceeeeeaeeeeeeeeceaeeecaaeeseaaeseeeeeseaeeesaeeeeaeetennees 35 9 3 2 BUS communication block 36 9 3 3 Accessing the on board EEPDROM 38 9 3 4 Accessing the on board DDR2 GDDAM nt 38 9 4 FPGA logic development 38 9 4 1 Programming file Generation ce eeeeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeaeeeeeeaaeeeeeeaaeeeeeeaaeeeeeeaaeeeeeeaaes 38 9 4 2 In system Drogrammimg a EET R S 40 9 5 Software description 40 9 5 1 Low level COMMUNICATION ue 40 9 5 2 leiw gd 41 9 6 Example firmware and software sssesesssesssrressrnesrsnnnstennnennnnnnttnnnnnnnnnntannnnnnnnnnnnnnnnnnnannan nnana 41 10 FPGA firmwa
23. 000 J Sur CH PROM P xcf04s SystemACE Create PROM File PROM File Formatter 7 WebTalk Data xc sk16 dios6016 bit iMPACT Processes EEN dios6016 bit Available Operations are ie gt Generate File H S a V d S f a S S d 7 H Generate Succeeded 0x0007_FFFF H P PROM File Formatter Xilinx Flash PROM T 8 Step3 Create SVF file in Xilinx ISE Impact Select Boundary scan and add Xilinx device in the boundary Scan window Select the generated MCS file and select the right prom XCFO4S Select output gt SVF File gt Create SVF file Give SVF file a name Select the PROM and program Do not check load FPGA File is written now Select Output gt SVF file gt stop writing SVF file NLO Ol E SVF file is now generated iMPACT Flows O gx H 2 Boundary Scan SystemACE E Create PROM File PROM File Formatter w WebTalk Data xcf04s dios6016_test iMPACT Processes O x Available Operations are Program a Verify Erase Blank Check Readback Get Device ID m Get Device Checksum m Get Device Signature Usercode One Step SVF One Step XSVF L PROM File Formatter Xilinx Flash PROM 2 Boundary Scan Step 4 Create ACE File The SVF file can be converted to an ACE file using the Xilinx tool SVF2ACE The download link for t
24. 024 End address 1023 Before setting the module in measurement mode the address counter should be set to the position of stimulus signal start This does not always have to be the same as the return to address Optionally a leading and not repeated pattern may be programmed in the signal memory locations preceding the return to address Again the address counter should be programmed to a multiple of eight positions from the return to address Next the end address pointer should be set the loop counters or continuous mode should be set The stimulus signal is the repeated by either the sum of the settle loop and measurement loop counters or it is repeated continuously until the measurement mode or trigger is reset Next when the module is set in measurement mode the address counter clock is switched to the sample clock logic After receipt of the trigger the counter starts to increment and stimulus data is written to the DAC The stimulus signal marked by return to address and end address is repeated For a stimuli memory the following driver functions are available pa72_SetMemoryAddress Configure instrument memory address counter position pa72_SetMemoryEndAddress Configure instrument memory end address position pa72_SetMemoryReturnToAddress Configure instrument memory return to address 4 3 Module Capture memory architecture A capturing module has a capture memory in which during the measurement the converted
25. 10 12 13 14 15 17 18 19 20 return address 13 21 22 23 25 26 27 28 29 38 40 41 47 return to address 12 13 14 20 E A end address 12 13 14 signal custom 17 external clock 24 30 signal definition 14 F software 40 specifications 43 filters 6 19 27 29 stimulus memory 12 firmware 34 38 41 stimulus signal definition 14 FPGA 19 31 32 33 34 35 36 37 38 39 46 48 storage 32 33 front clock 8 43 T G trigger input 6 9 generator 14 bit 26 trigger latency 10 20 27 generator 16 bit 18 trigger sources 9 H trigger timing 10 hold off delay 20 28 B PA72 Series User manual Rev 1 10 Page 50 of 51 Appendix F Document history Version Date Editor Changes 1 0 Initial version 10 11 2014 JvW PXle added in the power consumption list 26 11 2014 JvW JvdV Added PA72DIOS016 chapter Expanded cross reference Added chapter on FPGA firmware update 1 10 16 02 2015 JvdV Fixed incorrect description of availability of differential I Os in 9 1 and 9 2 1 hy PA72 Series User manual Rev 1 10 Page 51 of 51
26. 10 Page 46 of 51 Appendix A Calibration procedure The actual voltage level of the PA72 board reference is measured externally with a calibrated high precision voltmeter and stored as calibration value in the module EEPROM On the backside of the PA72 card there are two test points over which this reference voltage is measured Once this voltage is stored the PA72 calibration ADC auto calibration can be started During an auto calibration the ADC offset and gain are calibrated first by measuring the known reference voltage level and the reference ground level Now the calibration ADC can measure three different voltage levels on each module Board reference ground Positive channel output Negative channel output To measure an output level a relative measurement is done Module driver functions are available to start the module auto calibration Driver function pa72_ Calibrate Note the PA72D16180A and PA72D1 4130 digitizer modules require a connection between the positive input and the negative input for calibration This connection is not on the board so before calling the calibration function connect both inputs together with a short coaxial cable Calibration interval table Calibration Type of cal Recommended Calibration time effort interval PA72 reference voltage Manual Every year Approx 5 minutes PA72 mainboard AD converter Auto cal Every three months 5 seconds PA72D16180A Auto cal Ever
27. A APPLICOS MEASUREMENT amp CONTROL amp CONTROL PA72 series User Manual Revision 1 10 February 2015 APPLICOS bv Veldkampseweg 1 8181LN Heerde The Netherlands Table of Contents Table OF GOnte nt isisisscesseisdscnctecscesscniives vadeasoiaunas cancacunnensvesaveisensaastaanassinndasasenaissaniausasaues 2 1 KC lee VE 5 2 MFO TE e n E 6 3 ce baee DOGG scsictcscssctssaciscisnnenssenaauascacacetadovnacncvssnnensincadssazainnadesmsaneesessiendaneaaes 7 3 4 Base board Block dagi aiM sssrini twtr rtivestel sete tive irae degen tans 7 32 eet 8 EC SN pute Te E 9 3 3 1 Biel ul E 10 3 4 eeler NR LEET 10 3 4 1 Modu le Calibfatlon ccc scteccs sue SEENEN yates dios aerated eee 11 3 5 Front panel channel LEDS ersa E E 11 4 General module memory structure and signal definition ssscseeeeeee 12 4 1 Module Operational modes A 12 4 2 Module Stimulus memory architecture cccceeececeeeceeeeeeeeeeeceeeeecaeeesaaeeeeeeeseaeeesaeeeeeeeeenees 12 4 3 Module Capture memory architecture ccccceeceeceeeeeeeeeeeeeeceeeeecaeeesaaeeeeneeseaeeesaeeseaeesenees 13 4 4 Stimulus signal definition c ce ececeeeeeeeceeeeeeeeeeeeeeeeeaeeeeeaeeeeaeeseeeeseaeeesaaeeseeeeseeeeesnaeeeeaeeseaees 14 5 PA72G16400 waveform generator MOUIEC ccescceceseeeeeseeeensneeeeseeeeeseeeeeeees 18 5 1 Board DIOCK Cha grant E 18 5 2 Output voltage and available signal ranges ccccceceeeeeeeeeeeeeeceeeeeeeaeee
28. D13_N I O C12 15 D14 P I O H17 49 D14_N I O H18 16 D15 _P I O D14 50 D15_N I O C14 17 D16_P I O J16 51 D16_N I O J18 18 D17_P I O F15 52 D17_N I O F16 19 D18 P I O K17 53 D18_N I O K18 20 D19_ P I O F14 54 D19_N I O G14 21 D20_P I O L17 55 D20_N I O L18 22 D21_P I O H13 56 D21_N I O H14 23 D22_P I O M16 57 D22_N I O M18 24 D23_P I O H15 58 D23_N I O H16 25 D24_P I O N17 59 D24 N I O N18 26 D25 P I O K15 60 D25 N I O K16 27 D26_P I O P17 61 D26_N I O P18 28 D27_P I O L14 62 D27_N I O M13 29 D28_P I O T17 63 D28 _N I O T18 30 D29_P I O M14 64 D29_N I O N14 31 D30_P I O U17 65 D30_N I O U18 32 D31_P I O N15 66 D31_N I O N16 33 GND 67 GND 34 Clock Out P 68 Clock Out_N Table 5 Connector pinning and FPGA pin location Bank 0 Bank1 hy PA72 Series User manual Rev 1 10 Page 34 of 51 9 3 FPGA logic description With this card a basic FPGA start project is provided This project can be used as starting point for your design It already locks all the pin positions and has a bus interface block for communication with the PA72 Baseboard Figure 4 shows the hierarchy of the basic start file This basic project includes DIOS6016_top vhd The top file with all the board IO s PA72_Module_lO vhd Communicates with the PA72 Baseboard AddressDecoderV100 vhd Address decoder file PXIMain_Package v
29. Hz A filter bypass path may also be chosen The filter path is configured with the pa72_SetFilter driver function 5 5 Clocks trigger and stimulus In configuration mode the module can accessed from the PA72 mainboard The Address counters and memory logic run on a local 33Mhz clock then The DAC however is always connected to the PA72 sample clock When a single voltage is programmed to the signal DAC using pa72_SetVolitage there should be a valid sample clock running at the PA72G16400 clock input Be sure that the PLL clock is initialized In case of direct clocking modus a valid clock source should be present at the PA72 front clock input In measurement mode the card memory cannot be accessed from the PA72 bus Now the memory address counter is clocked by the clock from the PA72 main board The actual clock source selection is set on the main board TRIG gt _ Stop address Startaddress H MMODE CLK 7 DAC REG Settle Meas Loop Loop counter counter CONTINUOUS The clock will be used as sample clock and as clock for the stimulus address counter It will not be divided on the PA72G16400 module The applied clock frequency is equal to the sample frequency When two identical modules are placed on one main board it can be important to have t
30. M File Fon Step 1 Select Storage Target Step 2 Add Storage Device s Step 3 Enter Data Fil p SE Device Type PROM Family Platform Flash General File Detail Value Xilinx Flash PROM mme Checksum Fill FF Non Volatile FPGA Device bits xcf04s 4M Value Spartan3AN ees SPI Flash Add Storage Device Remove Storage Device Te POSED 16 test Configure Single FPGA Ge BE Output File Configure MultiBoot FPGA xcf04s 4M Location 0560 16 Xilinx DIOS6016_Empty CG BPI Flash Configure Single FPGA Configure MultiBoot FPGA E EN Flash PROM File Property Value Configure from Paralleled PROMs File Format MCS Generic Parallel PROM Dal Add Non Configuration Data Files No E Auto Select PROM Description In this step you will enter information to assist in setting up and generating a PROM file for the targeted storage device and mode Checksum Fill Value When data is insufficient to fill the entire memory of a PROM the value specified here is used to calculate the checksum of the unused portions Output File Name This allows you to specify the base name of the file to which your PROM data will be written Output File Location This allows you to specify the directory in which the file named above will be created i can he nenerated in anu i pon hy PA72 Series User manual Rev 1 10 Page 38 of 51 IMPACT Flows 08x lt 2 Boundary Scan a 0x0000_0
31. When the trigger is set inactive only the fixed n latency is applied In measurement mode the stimulus signal repetition is determined by the setting of the running mode In the so called continues mode the stimulus signal is repeated until the trigger is disabled or the module is set in configuration mode In Counter mode the stimulus is repeated by value set in the measurement loop counter The following driver functions control this repetition pa72_SetContinuousMode Set module continuous mode When set to value 0 the loop counters determine the stimulus repetition counter mode When set to value 1 the stimulus is repeated until trigger is inactive or the module is set back in configuration mode pa72_SetMeasurementLoopCounter Set module settle loop counter value hy PA72 Series User manual Rev 1 10 Page 28 of 51 8 PA72D14130 waveform digitizer module 8 1 Board block diagram The PA72D14130 module is a 14 bit 130MSps Waveform Digitizer for high frequency waveform digitizing It features differential inputs with a programmable DC offset on the negative input The module has eight input ranges Clock and trigger are sourced by the main board AC DC Range ilte c E Bypass 4 wo a E J E d s Ler lt TA 2 cal E a 30Mhz LPF ype CLOCK Clock Distribution Stop address JI Start address 1 t Addresscounter
32. a single ended connection and a differential connection mode single ended input differential inout configuration 2 048Vp vax 1 024 S input A input ov Ge Vom AN e inpu Seed gt Ka kg CO N i input gt Vern sem input 1 024V gt The allowable common mode offset is the average value between the two inputs Vina Vins Vy IN IN When the differential mode input signal is 100 of the input range the common mode level can still be varied between the specified limits Example In the case of the 4 096Vpp range available in the 500 connection mode the common mode offset level of the signal should remain between 1 76V and 4 40V This could be for example e A single ended sinewave signal with an amplitude of 4 096Vpp and an offset of 8 8V Yo Vw 7 Nu _ 0 0V SEN A Au 2 But also e A differential sinewave signal with an amplitude of 4 096VPP and an offset of A AN Ma Viv _ 44V 4 4V V 4 4V CM 2 2 6 3 Filter section To reduce the bandwidth of the input signal one of the two third order Butterworth low pass filters can be selected These filters have a cut off frequency of 30MHz and 60MHz A filter bypass selection is also available which is the default configuration The filter path is configured with the driver function pa72_SetFilter hy PA72 Series User manual Rev 1 10 Page 22 of 51 6 4 Input connection configuration The connection of each
33. de in order to read the capture memory or to setup another measurement 4 2 Module Stimulus memory architecture A generating module like the PA72G16400 contains 8M word stimulus memory in which one or more stimulus signals may be stored The stimulus signal is marked by defining a so called return to address and end address The stimulus signal definition in between these two markers is repeated looped a user defined number of times The repetition of the stimulus is set with the function pa72_SetContinuousMode When set to value 0 the stimulus signal is repeated by the sum of the settle loop and measurement loop counter value When pa72_SeiContinuousMode is set to 1 the stimulus is repeated continuously until the trigger is set inactive or the module is set back in configuration mode STIMULUS MEMORY Dee ADDRESS COUNTER DATA 3 DATA 2 DATA 1 RETURN ADDRESS END ADDRESS Note that for the PA72G16400 the return to address should always be a multiple of eight and the number of signal steps should also be a multiple of eight Consequently the end address value is End address Return to address Number of signal steps 1 Where Return to address and Number of signal steps is always a multiple of eight B PA72 Series User manual Rev 1 10 Page 12 of 51 Example Return to address address 0 Number of signal steps 1
34. driver functionspa72_SetAnalogEdgeTriggerMode and pa72_SetAnalogTriggerLevel to setup analog edge triggering for digitizer modules 3 3 1 Trigger timing TRIG SYNC clock Module tigger The actual trigger timing is dependent of the clock source chosen Due to trigger to sample clock synchronisation the actual trigger moment falls somewhere within one clock period time tc of the chosen clock frequency When the PLL clock is used as clock source this actual trigger delay time time tdb has a random value within tc When the bypassed front clock is used in combination with the trigger the actual trigger timing can be predicted The internal front clock delay between the front clock connector and trigger sync register should be anticipated when applying a trigger signal close to the rising edge of the applied clock The daughter module adds an additional trigger latency in time steps that equal the sample clock s cycle period The number of cycles for the trigger latency depends on the module type and programmed value for the trigger latency counter on that module Refer to the appropriate section describing the triggering of the module 3 4 Calibration ADC The PA72 base board has a 24 bit calibration ADC for auto calibration and self test purposes The ADC has an 8 input mux from which 2 inputs are used to calibrate the ADC for offset and gain The actual voltage level of this reference is measu
35. e ended The range is set with the software driver function pa72_SetRange Range number Output range Vp single ended Output range Vp differential 0 2 56V 5 12V 1 1 28V 2 56V 2 850mV 1 70V 3 640mV 1 28V 4 425mV 850mV 5 320mV 640mV The voltage difference between the outputs is twice the programmed output voltage 5 3 DC Offset The DC offset is added by a so called DC Offset DAC The voltage range is from 2 56V to 2 56V programmable in a 78 125 uV resolution The offset is always connected to the signal path The output voltage is composed as follows Le signal Mac oe V V outneg signal DC Offset Voutpos S the output voltage relative to ground on the positive force output Voutneg S the output voltage relative to ground on the negative force output Vigna is the voltage programmed to the 16 bit signal DAC Voc ortset iS the voltage programmed to the 16 bit DC Offset DAC by PA72 Series User manual Rev 1 10 Page 18 of 51 V Dc offset iS programmed using driver function pa72_SetOffset Voltage The DAC output voltage Vsignai is either set by the contents of the stimulus memory or when the module operates in configuration mode directly with driver function pa72_SetVoltage 5 4 Filter section One of the two third order Butterworth low pass filters can be switched into the signal path The available filters have a cut off frequency of resp 30MHz and 60M
36. e used The following Bus Address Ranges BAR are in use BARO Access PA72 baseboard registers BAR2 Access PA72 daughter card registers For module position 1 the address range is 0x00 OxOF For module position 2 the address range is 0x10 Ox1F an offset of 0x10 hy PA72 Series User manual Rev 1 10 Page 40 of 51 9 5 2 Instrument driver Because the functionality of the PA72DIOS6016 module is not fixed by Applicos it can be used for a broad range of applications The instrument driver provided by Applicos covers the basic functionality such as register based read and write functions Although the source code of the PA72 driver is provided it is not recommended to make firmware specific adjustments in the PA72 driver Instead a separate driver could be created which uses the PA72 driver register access functions and wraps this to the functionality matching the firmware in use Application layer PA72 driver VISA low level driver Figure 12 Suggested driver topology 9 6 Example firmware and software On the disc that is provided with your PA72DIOS6016 are some example firmware software applications The examples have very basic functionality and are intended to provide some guidance in developing firmware and software by showing how to achieve tasks like writing module registers generating or capturing data to or from the front SCSI connector accessing the EEPROM etc Each example is accompani
37. eaeeseneeeseaeeseaaeeeeneeees 18 5 3 Ree EE 18 oy Sm Le EE EE 19 5 5 Clocks trigger and stimulus cececeeeeeeeeeeeeeeeeeceeeee ee aeeeeeaeeeeeeeseeeeeeaaeseeaaeseneeeseaeeesaeeeeneees 19 BiB MGI ORY E 20 6 PA72D16180A Waveform digitizer MOCUIC cccseeceeteeeeseeeeeeeeeeeseeeeeeeeees 21 6 1 Board block diagram enescu nated EE dE EEN en 21 6 2 Input ranges and common mode LANES ceceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeteeeeeeeeeeeaeeseeeeaeees 21 O3 SINS Le TEE 22 6 4 Input connection Copfiguraton eee cece ee eeteee ee eeeeeeeeeeaeee sete aeeeeeteaeeeeeeeaeeeeesaeeeeeeeeaeeeeeenaeees 23 6 5 Klee 23 6 6 CIOCKS ANG Kee TEE 24 Or M ttgtwzesiogegcgeggedesg a a E A S E E 24 6 8 Module auto calbratiON ecreronanianiniri R AA OR 25 7 PA72G14180 waveform generator MOUIEC ccescceeeseeeeeeeeeenseeeeeseeeeeseeeeeeeees 26 7 1 Board Melle e Ee Tu EE 26 7 2 Output voltage and available signal ranges eccceceeeeeeseeceeeeceeeeeeaeeeeaeeseeeeeseaeeeeaeeeeneeeea 26 CC WEN Klee 26 LA ET Le E 27 Zb Clocks trigger and Stimulus gue kdubeEEe ENEE tli aerate dai 27 8 PA72D14130 waveform digitizer MOCUIC c eecceeseeeeeseeeenseeeeeseeeeeseeeeeeeees 29 8 1 Board DIOCK dagr aTi a a E AE A E 29 8 2 Input voltage and available signal ranges AA 29 8 3 ET Le EE 29 hy PA72 Series User manual Rev 1 10 Page 2 of 51 8 4 COCKS and tigger ceniris aAa a aa aaaea E aaan aae AEAT 3
38. ed memory controller block MCB The MCB block is configured and enabled by the ISE core generator A generated MCB Block for the on board memory is available in the basic start file folder under the coregen folder The memory block is not implemented in the example files because the use and control of this block is very application dependent For more information see the Memory controller user guide from Xilinx UG388 9 4 FPGA logic development The FPGA program development can be done with any FPGA development tool that can output a bit file It is recommended to use a tool that supports Xilinx Spartan6 because of the use of specific Xilinx building blocks With the PA72DIOS6016 board several examples and a basic start file are included The supplied examples and basic start file are written in VHDL using Xilinx ISE Project navigator 14 7 9 4 1 Programming file generation The PA72 baseboard is equipped with an ACE file programmer as in Xilinx Application Note XAPP424 that allows you to upload and program your firmware to the FPGA loading PROM This programmer can be accessed using a PA72 driver function or using the PA72 tools application Step 1 Generate bit file Generating the bit file for the spartan6 XC6SLX16 3CSG324 with Xilinx ISE Xilinx Vivado or another tool Step 2 Generate PROM file Generate the PROM file for a XCF04S device with the PROM File Formatter in Xilinx ISE impact 7 L PRO
39. ed with a descriptive document by PA72 Series User manual Rev 1 10 Page 41 of 51 10 FPGA firmware update The PA72 daughter boards FPGA firmware can be updated in the field The PA72 instrument driver exports the function pa72_ProgramFPGA which accepts a path to an ACE file to upload to the daughter card FPGA loading EEPROM A more convenient way of updating the FPGA firmware is using the PA72 tools application pictured below Instrument s PX122 0 INSTR 7 refresh Active Module Module 1 pa72dios6016 dio 16 fpga i o module ID 0x80011001 driver revision 1 00 Calibration FPGA update Miscellaneous ace file E Browse D Doorgeef DI0S60 16 HS ADC Example DIOS6016_LTC2641 ace Start update Searching for instruments Location PXI22 0 INSTR ID 0x22020001 driver revision 1 14 instrument revision NA Module 1 pa72dios6016 dio 16 fpga i o module ID 0x80011001 driver revision 1 00 Module 2 NA NA ID OxFFFFFFFF driver revision NA 1 instrument found 3 Clear D Copy save Abort The steps are easy Start the PA72 Tools application Click Refresh to search for installed PA72 cards Select the tab FPGA update Enter the path to the ACE file or find it using the Browse button Click the Start update button to start the FPGA firmware update The output window shows the progress of the FPGA updating process Ore
40. ency Sync possibilities PLL lock time Jitter Front clock input impedance Front clock threshold level Front clock input hysteresis Front clock input frequency Triggering Trigger sources Front trigger impedance Front trigger threshold level Front clock PLL clock on base board 2kKHz 945MHz 10MHz backplane or 10MHz external clock 250ms 1s depending on loop filter BW 0 5ps typical 50 Q DC 1 02 Volt 5 60mV typical As direct clocking OHz 945MHz As PLL reference 10MHz only PXI trigger 0 6 PXI star trigger Front trig Software trigger 1 kQ DC 1 02 Volt 5 Front trigger hysteresis 60mV typical Max input level 0 5V to 5 5V Power requirements Typical power consumption 3 3 Volt 12V PXlexpress 750 mA 165 mA Note for each module an additional supply current should be added refer to appropriate module power consumption specification hy PA72 Series User manual Rev 1 10 Page 43 of 51 11 3 Specification PA72G16400 module Channels Resolution Update rate with internal clock Update rate with external clock Pattern depth Output ranges Single ended Output ranges Differential DC Offset voltage Output configuration Bandwidth Output filters Absolute accuracy diff Relative accuracy SNR 200Msps 5Vpp diff SNR 200Msps 5Vpp diff THD 200Msps 5Vpp diff THD 200Msps 5Vpp diff SFDR 200Msps 5Vpp diff
41. es possible to program the DC Offset DAC outside of the input operating range the input operating range of the selected input range should still be observed The DC Offset DAC is programmed using the function pa72_SetOffsetVoliage 6 6 Clocks and trigger In configuration mode the module can accessed from the PA72 mainboard The address counters and memory logic run on the 33MHz PCI clock The ADC however is always connected to the PA72 sample clock When a single voltage is measured with the ADC using pa72_GetVoliage there should be a valid clock running at the PA72D16180A clock input pins Be sure that the PLL clock is initialized In case of direct clocking modus a valid clock signal should be present at the PA72 front clock input In measurement mode the card memory cannot be accessed from the PA72 bus Now the memory address counter is clocked by the clock from the PA72 main board The actual clock source selection is set on the main board The applied clock signal from the Base board will be used as sample clock and as a clock for the capture memory address counter and will not be divided on this module The applied clock frequency is equal to the sample frequency The trigger signal comes from the base board where it is synchronized with the sample clock of module 1 before being distributed to both modules Start address Stop address Hold off counter or Pretrigger counter STOP Bref i START
42. ese ranges can be found in the tables below 500 DC coupled input Range nr Input range Vin Vin Allowable common mode offset 0 6 144 Vpp 0 220V 0 550V 1 4 096 Vpp 0 220V 0 550V 2 3 072 Vpp 0 440V 1 100V 3 2 048 Vpp 0 440V 1 100V 4 1 536 Vpp 0 880V 2 200V 5 1 024 Vpp 0 880V 2 200V 6 0 768 Vpp 1 760V 4 400V 7 0 512 Vpp 1 760V 4 400V 1MQ DC coupled input Range nr Input range Vin Vin Allowable common mode offset 0 30 720 Vpp 0 220V 0 550V 1 20 480 Vpp 0 220V 0 550V 2 15 360 Vpp 0 440V 1 100V 3 10 240 Vpp 0 440V 1 100V 4 7 680 Vpp 0 880V 2 200V 5 5 120 Vpp 0 880V 2 200V 6 3 072 Vpp 2 200V 5 500V 7 2 048 Vpp 2 200V 5 500V 8 1 536 Vpp 4 400V 11 000V hy PA72 Series User manual Rev 1 10 Page 21 of 51 9 1 024 Vpp 4 400V 11 000V 10 0 768 Vpp 8 800V 22 000V 11 0 512 Vpp 8 800V 22 000V The input range is specified as the voltage between the In and the In inputs Vin Vin This means that for an rangeof 4 096Vpp this can be e a 2 048V signal on the In input with a single ended connection but also e a 1 024V signal on both the In and the In inputs with a differential connection Example The figure below shows the maximum possible signal amplitude for the 4 096 Vpp range for both
43. hd VHDL package file with constants DIOS6016 ucf Constraints and pin location file Figure 4 FPGA basic start project hierarchy 9 3 1 Top file and Constraints file The top file DIOS6016_top vhd holds all the IO pins that are connected on the DIOS6016 board These pins are constrained in the DIOS6016 ucf file In the design phase the pin constraints for the XIO_P and XIO_N pins to the SCSI connector needs to be adjusted to the used IO pin standard with the corresponding pin voltage The user project files can be added to this top file to access the lO pins L hy PA72 Series User manual Rev 1 10 Page 35 of 51 9 3 2 Bus communication block The bus communication block PA72_Module_ O vhd handles all the board write and read actions from the PA72 baseboard and converts them to a simple internal read and write bus The PA72 baseboard uses two types of data transport single read write and DMA read and write If the read data is not available on the next clock edge the read actions can be delayed with the wait value input signal PA72 Bus IO side Internal r w signals Figure 5 PA72 Module IO 9 3 2 1 Single read and write actions The following pictures show the single write and read timing All FPGA actions are rising edge clocked Ons 25ns 75ns 100ns 125ns 150ns PA72_Module_ 0O vhd single write action l a E A e gege h Pi wr_en P gt
44. he output of the channels running perfectly in phase when using the same clock frequency for both channels To achieve this with the PA72G16400 the clock on both modules have to be synchronized using driver function pa72_SyncClock after changing the clock frequency There are however a few limitations to this synchronization In the following cases clock syncing will not be successful or will not be reliable e Module PCB revision older than 2 e Module PCB revision 2 with FPGA revision older than 5 e Module PCB revision 2 with FPGA revision 5 or above using a sample clock between 92 MHz and 93 MHz or between 267 MHz and 288 MHz In these cases the driver function will return a warning This warning message is based on the programmed PLL frequency When using an external clock directly as sample clock i e not as 10 MHz PLL reference the driver does not know the clock hy PA72 Series User manual Rev 1 10 Page 19 of 51 frequency and might five a false warning To avoid this program the PLL to the same frequency as the sample clock The trigger signal is synchronized on the PA72 main board on the positive edge of the sample clock Once the card is triggered it will keep running until it has finished it s pattern or when the Instrument Mode is returned to Configuration mode If the Continuous Mode pa72_SetContinuousMode is enabled setting the Instrument Mode to Configuration Mode is the only way to stop the card from
45. his tool can be found in the Xilinx Application Note XAPP424 found on the Xilinx website On the software disc delivered with the PA72DIOS6xxx a batch file Generate Ace bat is included that can help in passing the right parameters to this tool hy PA72 Series User manual Rev 1 10 Page 39 of 51 Generate ACE bat EJ CREM REM This batch file can be used to convert SVF files to ACE files using the Xilinx SVF2ACE utility CREM TITLE Convert SVF to ACE file REM Location of input SVF file and output ACE file SET inputfile D Doorgeef DIOS6016 HS ADC Example DIOS6016_AD9244 svf SET outputfile D Doorgeef DIOS6016 HS ADC Example test_Capture ace REM Location of SVF2ACE EXE utility SET svf2aceloc svf2ace exe REM Execute conversion Ssvf2aceloc i inputfile o outputfile tck 3000000 TITLE Convert SVF to ACE file Ready ECHO GECHO PAUSE 9 4 2 In system programming On the PA72 Baseboard an ACE file programmer is available so the file can be programmed in the PROM by software See chapter 10 FPGA firmware update for details 9 5 Software description 9 5 1 Low level communication When the PA72 driver is installed to your system the operating system matches the found hardware PA72 baseboard to a VISA driver The PA72 daughter cards do not need a separate driver To interface the PA72DIOS6016 module on register level a tool like NI VISA Interactive Control can b
46. igitizer and Generator modules are available Also Multifunctional Programmable Digital I O modules and Filter modules are available Any combination of available modules is possible The configuration of a PA72 module is determined as follows PA72 nm n represents module 1 top position m represents module 2 bottom position for n and m the following module codes are available empty no module placed PA72G16400 16 bit 400Msps Analog Waveform Generator PA72G14180 14 bit 180Msps AWG PA72D16180A 16 bit 180Msps Digitizer PA72D14130 14 bit 130Msps Digitizer PA72DI0S6016 Multifunctional programmable Digital I O PA72DI0S6100 Multifunctional programmable Digital I O PA72BPF Filter daughter board specify filter requirements separately MEeODUN AO For example a PA72 15 is a PA72 base board with a 16 bit 400Msps AWG in the top position and a 16 bit 180Msps Digitizer in the bottom position The main board has an advanced PLL sample clock generator featuring less than 0 4ps jitter The sample frequency is programmable from 2 kHz to 945 MHz and can be locked to the 10MHz PXI back plane clock or to an external reference clock Also external clocking is possible via the front panel clock input Triggering is possible by software PXI triggers PXI star trigger panel trigger input or edge triggering on the analog signal of one of the digitizers This document provides guidelines to using the PA72 hardware It contains some
47. mentMode is used to switch between configuration and measurement mode The composition of modules determine the ultimate function of the PA72 board Before a module is addressed i e for initialization the driver selects one of the two installed modules using driver function pa72_SetActiveModule The Eeprom and PLL clock logic is controlled by an TC serial bus An on board eeprom carries calibration data for the reference and calibrator DVM The PA72 carries the front trigger and clock connections and front LEDs For a description of the modules please refer to the appropriate section in this manual L hy PA72 Series User manual Rev 1 10 Page 7 of 51 3 2 Clock sources The figure shows a functional block diagram of the clock logic The PA72 board carries an ultra low jitter PLL clock multiplier that can generate a clock in the range from 2kHz to 945MHz The block containing the PLL dividers and output clock skew control is actual a one chip device controlled over a serial bus Several PLL and divider settings are done over the i2c bus and are covered in the PA72 card driver The desired PLL chip settings are calculated in the driver functions and programmed in the appropriate PLL device registers The PLL clock frequency is set using the pa72_SetClockFrequency function pa72_SetClockFrequency vi frequency1 frequency2 targetfrequency waitforlock locktimeout Parameters vi visa session frequency1 requested PLL out
48. mpedance selection the range selection is reset to 0 every time the driver function pa72_SetConnection is called for the PA72D16180A Therefore it is advisable to set the range using the pa72_SetRange function every time after the connection mode is set In the PA72 Soft Front Panel application some of this is done automatically but it is not always possible to preserve the range selection When for instance switching from the 500 6 144 Vpp range to a 1MO connection the 6 144V pp range is not available Here the soft front panel will switch over to range 0 30 72Vpp to make sure the input circuitry is not damaged Please note that when selecting disconnected input selection the input circuitry is not fully disconnected a 1MQ AC coupled load remains at the cards input terminal 6 5 DC Offset source The DC Offset source is a 16 bit DAC which can be programmed and internally connected to either one of the inputs to compensate for a common mode level on the other input The programmable range is depending on the selected input range by PA72 Series User manual Rev 1 10 Page 23 of 51 The table below describes the voltage ranges for the DC Offset DAC Input Range nr Range voltage DC Offset range impedance 1MQ Range 0 5 30 72Vpp 5 12 Vpp 25 6V 25 6V 1MQ Range 6 12 3 072Vpp 0 512Vpp 2 56V 2 56V 500 Range 0 7 6 144Vpp 0 512Vpp 2 56V 2 56V Although it is in most cas
49. number of periods param5 phase degrees param6 not used 4 analog triangle wave 14 digital triangle wave 5 analog square wave 15 digital square wave param1 amplitude param2 offset param3 number of samples param4 periods param5 phase degrees param6 symmetry 0 100 To load the stimulus signal into the stimulus memory the driver function pa72_SignalToModule can be used In this function the start address of the stimulus signal can be assigned This way more than one signal can be stored into one stimulus memory to eliminate memory load time during tests The resulting stimulus signal after the stimulus memory is filled is a summation of all indexed signals defined with the above described signal configuration function For analog signal definitions this summation results in a stimulus signal with an amplitude that is clipped at value 0 0 and 1 0 Value 0 0 corresponds to the minimum scale and 1 0 corresponds to the maximum scale of the stimulus signal DAC In fact an analog signal definition results in a multiplier that is multiplied with the output range of the DAC by PA72 Series User manual Rev 1 10 Page 15 of 51 The frequency of a signal is determined by the total number of samples or array size q the number of periods r and the sample frequency fsampie f ES I sanpite periods gt I came r r sig or Alternatively the number of periods can calculated with Signal
50. odule trigger can be switched to trigger signals from the front panel and from the PXI backplane including PXI TRIGGERO 6 and PXI STAR TRIGGER Alternatively when trigger timing is not an issue there is a software initiated trigger The diagram below illustrates the trigger circuit The trigger signal coming from the trigger selection mux is then synchronized with the sample clock for module 1 to give more precise control over the trigger timing of both modules e TRIGGER aoe TRIG SYNC PXI STAR PXI TRIG O 8 PXI TRIG 6 8 Front Trigger EE SYNC clock adar4 b0 b3 The front panel trigger input uses normal TTL logic levels with a 1 volt threshold level with a 60mV input referred hysteresis The hysteresis rejects noise and prevents oscillations on low slew input signals The logic levels for PXI TRIGGERS 6 are inverted and thus are low active This is true for both the PXI and PXI Express versions of the baseboard except for PXI baseboard versions with PCB revision below 5 The software trigger is controlled with driver function pa72_SetSoftwareTrigger Use driver pa72_SetTriggerSource to select the trigger source hy PA72 Series User manual Rev 1 10 Page 9 of 51 Note A digitizer can also generate a trigger from an edge on the input signal This trigger is generated on the module but can be routed to the mainboard s trigger circuitry to simultaneously trigger the two channel Use
51. onnector can also be used as a clock input for the FPGA to be used as data clock i e when an ADC is connected All FPGA global clock inputs and their origins are listed in the table below PA72 Bus Clock 33 MHz GCLK12 A10 PCI33 PA72 module clock 0 900 MHz GCLK19 GCLK18 D9 C9 LVPECL On board oscillator 200 MHz GCLK17 GCLK16 B9 A9 LVPECL SCSI XIO1_P 0 200 MHz GCLK15 D11 Diff or single SCSI XIO1_N 0 200 MHz GCLK14 C11 programmable SCSI XIO14_P 0 200 MHz GCLK5 H17 Diff or single SCSI XIO14 N 0 200 MHz GCLK4 H18 programmable SCSI XIO25_P 0 200 MHz GCLK9 K15 Diff or single SCSI XIO25 N 0 200 MHz GCLK8 K16 programmable Table 1 Clocking FPGA pin locations 9 2 3 Module Triggering The cards on the PA72 board are triggered with a trigger signal coming from the PA72 baseboard On the baseboard this module trigger signal is synchronized with the module clock for the upper daughter card position see block diagram in paragraph 3 1 For a stable trigger design the trigger needs re synchronization with the module clock at the FPGA input block The trigger source is selectable on the PA72 baseboard 500ps max gt lt Module Clock LVPECL JTULUUUI Module Trigger LVPECL gem Figure 3 Trigger timing PA72 Module trigger B4 A4 LVPECL Table 2 Trigger FPGA pin locations 9 2 4 12C EEPROM The DIOS6016 module has an on board 12C EEPROM for the storage
52. paran3 t sample To get a 1kHz sine wave with a sample freq of 500KHZ tsampie 2US using 65536 samples the number of periods can be calculated param4 Doran tanpe 110 65536 2 10 131 sample When defining a sine wave it is best to choose a prime number of periods 131 happens to be a prime number Otherwise param4 could be replaced with the nearest prime number resulting in a slightly different signal frequency by PA72 Series User manual Rev 1 10 Page 16 of 51 Summary index 0 type 3 param1 0 75 param2 0 5 param3 65536 param4 131 Example 2 Sine wave with amplitude Vpp 60 of full scale around midscale 1kHz added sine wave of 10 of full scale 10kHz fsamp 500kHz 65536 samples used First the 1kHz is defined Then define the signal parameters for the 1kHz sine Index 0 type s3 for analog sine param1 0 3 amplitude peak is 30 of full scale param2 0 5 sine should be located around halve param3 65536 number of samples param4 131 131 periods in 65536 samples and fs 500khz result in 0 99945kHz Then define the signal parameters for the 10kHz sine in signal configure index1 Index 0 type s3 for analog sine param1 0 05 amplitude peak is 5 of full scale param2 0 5 sine should be located around halve param3 65536 number of samples param4 1307 1307 periods in 65536 samples and fs 500khz result in 9 97162kHz To load a custom stimulus signal into the stimulus memory the dri
53. put frequency kHz for daughter module 1 frequency2 requested PLL output frequency kHz for daughter module 2 targetfrequency 0 PLL is set to approach frequency1 as close as possible 1 PLL is set to approach frequency2 as close as possible waitforlock wait until PLL is locked 0 don t wait 1 wait locktimeout maximum time to wait for lock ms TRIGGER SYNC DN p Module 1 Clock SE Mai DN PXI CLK 10 cK ES ES Threshold level a i direct inn Skew amA TXAN U E E F gt Module 2 Clock The PLL circuit uses a 10MHz reference clock As reference clock the on board 10MHz precision clock can be chosen When synchronisation with other cards is desired the front clock or the 10MHz PXI clock can be chosen The Front clock should be 10MHz when it is used as PLL reference clock The Module clock can either be derived from a divided PLL clock or the bypassed front clock Direct clocking The selected clock source is chosen for both channels simultaneously Only in PLL mode the channel may work with different clock frequency and or phase pa72_SetClockSource vi source Select the clock source for both daughter modules Parameters vi visa session Source module clock source 0 PLL clock with 10MHz on board oscillator 1 PLL clock with 10MHz backplane clock 2 PLL clock with 10MHz fron
54. re update saanunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn mnnn nnnn nnmnnn mnnn nna 42 11 Specifications iitawccsadcencsnntuicescbinbsnsctaadeinetanivsadiomesmniunbspaalunbeinatanavandoanvemuipadalsiicinens 43 11 1 Specification PA72 base board cccecececeeeeeeeeeeeeeee eee eeeaaeeeeeeeseaeeeseaeeeeaaeseeeeeseaeeeeaeeseaeeeeaes 43 11 2 Specification PA72e base board cecececeseeeeeeceeeeeeeaeeeeaaeeeeeeeseaeeeseaeeeeaaeseeeeeseaeeesaeeseaeeeeaes 43 11 3 Specification PA72G16400 module cece ceeeceeeeeeeeeeeeeeeaeeeeeeeseaeeeseaeeeeaaeseeeeeseaeeesaeeseaeeenaes 44 11 4 Specification PA72D16180A module 44 11 5 Specification PA72G14180 module eee ceeeee cece ee eee eeeaeeeeeeeeseaeeecaaeeecaaeseeeeeseaeeesaeeseeeeeaes 45 11 6 Specification PA72D14130 module 0 22 cece ce eeeeeeeeeeceeeeeeeaeeeeeeeceaeeeseaeeecaaeseeeeeseaeeesaeeseaeeeeaes 45 11 7 Specifications PA72DIOS6016 module essseesseeseeeseessnresnnssrnssrnsnnssrnssrnsstnnsrnnsnnnsrnnsrnnnnnne 46 Appendix A Calibration procedure csssccsssessessseeesseeessneeenseeenseeeeeseeeeeseeeaes 47 Appendix B Module IDSivsicicccsiccccsiesesccniescinncdseseneesnnsenssnassentassavinasiaeuncucineswavanneventinuen 48 Appendix C Module dimensions ccseeccsseeeceseeeeeseeeeeenseeeensneeenseeeeeseeeeeseeeeeseees 49 Appendix E Cross EECHER 50 Appendix F Document NiStOry ccceecceseeceseeeeeseeeeeeneeeeeeeeeeenseeesnseeeenseeeeeseeeeeseeeee
55. red externally with a calibrated high precision voltmeter and stored as calibration value in the module EEPROM On the backside of the PA72 base board there are two test points over which this reference voltage is measured The measured voltage should be applied to the pa72_SetAdc24CalVoliage driver function This function sets the measured voltage as calibration data and also starts an ADC auto calibration by PA72 Series User manual Rev 1 10 Page 10 of 51 During an auto calibration the ADC offset and gain are calibrated first by measuring the known reference voltage level and the reference ground level The ADC has a 24 bit resolution The input range is from 4 167 to 8 333 Volt resulting in a 0 754uV LSB voltage The expected ADC Code at OV 0x555555 3 4 1 Module calibration Now the calibration ADC can measure on three different nodes on each module Board reference ground Positive channel output Negative channel output To measure an output level a relative measurement is done Driver function pa72_Calibrate starts a complete module auto calibration measuring several levels on the calibration nodes After calibration the calibration values and date can be stored using pa72_SioreCalibrationData and pa72_SetCalibrationDate 3 5 Front panel channel LEDs The front panel LEDs reflect the channel status and connection The Channel gate led off Channel is disconnected green Channel gate relay is connected
56. references to software driver functions but is not intended as a full documentation of the driver Please see PA72 Driver Source Help pa72 chm documentation for a reference on the driver functions P PA72 Series User manual Rev 1 10 Page 6 of 51 3 PA72 Base board In this section the Base board of the PA72 is described in detail 3 1 Base board block diagram TRIGGER SELECTION PXI STAR PXI TRIGO lt PXI TRIG 6 CLOCK SELECTION pxicikio U MULTIPLYER eg DIVIDER serial bus As shown in the block diagram the base board basically consists of the following PXI bus interface Two module slots Clock source and PLL management Trigger selection and synchronisation Precision reference voltage Accurate DVM function for auto calibration and self test purposes The PXI bus is transferred to an on board local bus controlling two module slots Basically a module operates in two states In configuration mode the module can be accessed from the PA72 Then it can be initialized and the stimulus or capture memory may be filled or read To perform a measurement with a module it is necessary to switch the module to the so called measurement mode In measurement mode the card memory cannot be accessed from the PA72 bus Now the memory address counter is clocked by the clock from the PA72 main board Driver function pa72_Seitlnstru
57. ro o a The FPGA is loaded with the new content of the loading EEPROM after a power down Therefore once the updating process is finished the system needs to be powered off before changes will become active hy PA72 Series User manual Rev 1 10 Page 42 of 51 11 Specifications All specifications Ta 25 C 11 1 Specification PA72 base board Clock generator Clock sources Output frequency Sync possibilities PLL lock time Jitter Front clock input impedance Front clock threshold level Front clock input hysteresis Front clock input frequency Triggering Trigger sources Front trigger impedance Front trigger threshold level Front clock PLL clock on base board 2kKHz 945MHz 10MHz backplane or 10MHz external clock 250ms 1s depending on loop filter BW 0 5ps typical 50 Q DC 1 02 Volt 5 6OmV typical As direct clocking OHz 945MHz As PLL reference 10MHz only PXI trigger 0 7 PXI star trigger Front trig Software trigger 1 kQ DC 1 02 Volt 5 Front trigger hysteresis 6OmV typical Max input level 0 5V to 5 5V Power requirements Typical power consumption 3 3 Volt 5 Volt 12V 12V PXI 720MA 120mA 10mA 10mA Note for each module an additional supply current should be added refer to appropriate module power consumption specification 11 2 Specification PA72e base board Clock generator Clock sources Output frequ
58. s 51 B PA72 Series User manual Rev 1 10 Page 3 of 51 LIABILITY DISCLAIMER The product described in this manual is warranted in accordance with the terms as set forward in applicable quotations or purchase orders Product performance is affected by configuration application software control and other factors The suitability of this product for a specific application must be determined by the customer and is not warranted by APPLICOS APPLICOS shall not be liable for any special incidental or consequential damage Information in this manual is intended to be accurate and reliable However APPLICOS assumes no responsibility for any errors which may appear in this document nor does it make any commitment to update the information contained herein by PA72 Series User manual Rev 1 10 Page 4 of 51 1 Terminology This chapter describes some of the abbreviations and terms that are used in this document Baseboard The multi purpose PXI board developed to carry two PA72 modules Module PA72 Daughter board mounted on the Baseboard A module can either be a waveform digitizer or a waveform generator Instrument A complete assembly of a Baseboard equipped with one or two modules by PA72 Series User manual Rev 1 10 Page 5 of 51 2 Introduction The PA72 is an integrated one slot PXI card consisting of main board carrying one or two modules The choice of modules is user configurable Waveform D
59. s counter is clocked by the clock from the PA72 main board The actual clock source selection is set on the main board E MMODE SZ DAC REG Meas Loop counter CONTINUOUS The clock will be used as sample clock and stimulus address counter clock and will not be divided on the PA72G14150 module The applied clock frequency is equal to the sample frequency The trigger signal is synchronized on the PA72 main board on the positive edge of the chosen sample clock The triggering is level sensitive This means that in measurement mode the stimulus address counter and the DAC start to update after the trigger signal is set logic high When the trigger level is set low again the DAC and stimulus address counter stop There is an trigger latency between trigger active and actual DAC update This latency is divided in a fixed latency and a variable latency dy PA72 Series User manual Rev 1 10 Page 27 of 51 Clock x A A Trigger d a 4 DAC output i amp lt ____ gt lt gt N h tek Nxtek The fixed latency n 4 and is caused by a couple of register stages in the stimulus signal logic The variable latency his programmed in a hold off counter The hold off counter is set with driver function pa72_SetHoldOffCounter Note that the hold off delay h appears only the first trigger event after measurement at start of the stimulus generation
60. t clock 3 Front clock bypass PLL clock by PA72 Series User manual Rev 1 10 Page 8 of 51 Clock channel to channel skew When the PLL clock is used as clock source the clock skew can be set with a minimum step size that ranges between 1ns and 2 ns dependent of internal PLL frequency set an the several clock divider settings A skew is set in fractions of that internal PLL clock period time With driver function pa72_GetClockSkewResolution the actual clock skew resolution step in ns can be retrieved After setting a different PLL frequency this resolution step may change Now to set a desired clock skew the clock skew setting can be calculated SkeWresirea MS Skewphase Skew solution S Driver function pa72_SetClockSkew programs the calculated skew phase value in the appropriate skew registers For each channel the value may be in the range from 128 to 127 pa72_SetClockSkew vi skew1 skew2 Set module input clock skew phase offset value range from 128 to 127 The front clock threshold level can be set to either OV for AC sine shaped clocks or 1V for TTL level clock sources When two identical modules are placed on one main board it can be important to have the output of the channels running perfectly in phase when using the same clock frequency for both channels To achieve this with the PA72G16400 see chapter 5 5 on page 19 3 3 Trigger The Baseboard accepts several trigger sources The m
61. tLoopCounter Set module settle loop counter value 5 6 Memory The memory of the PA72G16400 works with block sizes of 8 words So the start address and return to address should always be a multiple of eight The number of signal steps should also be a multiple of eight B PA72 Series User manual Rev 1 10 Page 20 of 51 6 PA72D16180A Waveform digitizer module The PA72D16180A module is a 16 bit up to 180MSps Waveform Digitizer for high frequency waveform digitizing It succeeds the PA72D16180 but adds a 1MQ input selection and has significantly improved bandwidth Some of the information in this chapter may not be applicable for the PA72D16180 Contact Applicos for details 6 1 Board block diagram AC DC Clock CLOCK TRIGGER Distribution Range Filter 4 Bypass z SS I E HS soMhz LPF lt DC OFFSET enkt LPF Range Filter Start address 16 bit resscounter E ADC TTT TTT TMO D z Ia SA Be z 30Mhz LPF 500 VE BEES 60Mhz LPF OFFSET DAC REFERENCE y calbus 6 2 Input ranges and common mode ranges The input range is selected with the software driver function pa72_SetRange Control HH Mainboard PA72 address REF cal The available input ranges and the common mode input ranges are dependent on the selected input impedance Th
62. ver function pa72_SetDigitalSignal or pa72_SetAnalogSignal can be used pa72_SetDigitalSignal accepts digital codes main DAC codes where pa72_SetAnalogSignal accepts a signal normalized between 0 0 minimum output voltage of range and 1 0 maximum output voltage of range by PA72 Series User manual Rev 1 10 Page 17 of 51 5 PA72G16400 waveform generator module 5 1 Board block diagram The PA72G16400 module is a 16 bit 400MSps Arbitrary Waveform Generator for high frequency waveform generation It features differential outputs Clock and trigger are sourced by the main board cal se x SA Gl ale LPF Na H en H 60Mhz LPF Range Filter DC DAC 16 bit Range Filter DAC 4 4 Bypass 4 50 A lt L vs 30Mhz LPF Slonalmemon _ E cal es AN 60Mhz LPF cal 4 Bypass 4 ECH 4 HESE ATTN MU UX Clock Distribution cal Stop address Start address T Addresscounter PA72 Mainboard Control aii address ATTN MUX MUX REF cal callus 5 2 Output voltage and available signal ranges The output voltage range is 5 12V to 5 12V for each output The output signal range Signal DAC voltage swing relative to ground can be set to 320mV 425mV 640mV 850mV 1 28V 2 56V ranges are Vp singl
63. y three months PA72D14130 Auto cal Every three months PA72G16400 Auto cal Every three months Approx 10 minutes PA72G14180 Auto cal Every three months Approx 1 minute All calibrations should be started at least halve an hour after power up hy PA72 Series User manual Rev 1 10 Page 47 of 51 Appendix B Module IDs The PA72 baseboard modules and daughter cards all have an ID register at offset address 0x0 The description of the bits in this register is explained below PA72 e baseboard ID register Bit 31 29 28 24 23 16 15 0 Description b000 for PA72 b001 for PA72e Geographical address in PXI chassis Printed Wire Board revision FPGA revision PA72 PCB revision 5 or above or PA72e only PA72 daughter card ID registers Bit 31 30 24 23 16 15 12 11 8 7 0 Description 0 24 bit bus reserved FPGA Printed Wire reserved Module type 1 32 bit bus revision Board revision ID register bits 7 0 can be a value from the table below ID register bits 7 0 Module type 0x01 PA72DIOS6016 0x02 PA72DIOS6100 0x12 PA72G14180 0x13 PA72G16400 0x22 PA72D14130 0x23 PA72D16180 0x51 0x52 PA72BPF Example ID 0x800A2022 e 32 bit data bus e FPGA revision 0x0A 10 e PWB revision 0x2 2 e Module type 0x22 D14130 hy PA72 Series User manual Rev 1 10 Page 48 of 51

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