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Tegra K1 Embedded Platform Design Guide

1. NVIDIA Table 84 CSI Configurations Including optional use of DSI_B pins as additional CSI lanes Stereo Rear facing PAREN CETER dual dab waha config Gamera Tegra Ball Names CSI Signals gt 1 lane 1 lane Left RF Right RF up to x4 up to x4 up to x4 up to x4 x1 CSI_A_CLK_N P CSI_A_CLK_N P J T CSI A D 1 0 N P CSI A D 1 0 N P NG NG CSI B D 1 0 N P CSI B D 1 0 N P J NG DSI B CLK N P CSI C CLK N P NG A DSI_B_D 1 0 _N P CSI_C_D 1 0 _N P J T DSI B D 3 2 N P CSI D D 1 0 N P J 4 CSI_E_CLK_N P CSI_E_CLK_N P i CSI_E_D_N P CSI_E_D_N P J CSI Design Guidelines Table 85 MIPI CSI Interface Signal Routing Requirements Parameter Requirement Units Note Max Frequency Data Rate per data lane 750 1500 MHz Mbps Number of Loads 1 load Max Loading per pin 10 pF Reference plane GND or PWR See Note 1 Breakout Region Impedance Diff pair Single End 90 45 55 Q 15 Max PCB breakout delay 48 ps Trace Impedance Diff pair Single End 90 45 55 Q Via proximity Signal to reference lt 3 8 24 mm ps See Note 2 Trace spacing Microstrip Stripli 2x 2x dielectric Max Trace Delay 1620 ps See Note 3 Max Intra pair Skew 1 ps See Note 3 Max Trace Delay Skew between DQ amp CLK 10 ps See Note 3 Note If PWR 0 01uF decoupling cap required for return current 1 2 Up to 4 signal vias can share a single GND return via 3 Include Package amp PCB routing delays for Max trace delays and
2. Ball Name Type Termination Description LVDSO_TXD 4 0 _P O LVDS CLK Data Lanes See eDP LVDS Pin Assignment IN Options table or diagrams for correct connection to display connector LVDSO_RSET A 1KQ 1 to GND LVDS Current Reference Connect to resistor to GND AVDD_LVDSO_IO P Note 1 LVDS IO Power Rail Connect to 1 05V supply AVDD_LVDSO_PLL P Note 1 LVDS Dedicated PLL Power Rail Connect to 1 8V for LVDS Table 74 LVDS eDP Interface Package Delays Signal Name Ball Pkg Delay ps Signal Name Ball Pkg Delay ps LVDSO_TXDON AJ2 50 LVDSO_TXD3N AG1 46 LVDSO_TXDOP AJ3 51 LVDSO_TXD3P AG2 47 LVDSO_TXD1N AG3 44 LVDSO_TXD4N AF3 38 LVDSO_TXD1P AG4 45 LVDSO_TXD4P AF4 38 LVDSO_TXD2N AG5 30 LVDSO_RSET AK3 46 LVDSO_TXD2P AG6 30 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 61 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 3 5 2 MIPI DSI Tegra supports eight total MIPI DSI data lanes and two clock lanes allowing up to two 4 lane interfaces Each data channel has peak bandwidth up to 1 5Gbps Additional Functions Tearing Effect input to allow the display controller to synchronize to panel drivers with their own timing controllers Backlight PWM Various GPIOs to support display power sequencing power management etc Figure 27 DSI 2 x 4 Lane Connection Example Tegra DSI DSI 1 2V_RUN_AVDD
3. Clocks DSI SDMMC Strapping Pins DRAM LVDS 12S Thermal Diode USB eDP 12C PCle HDMI SPI SATA CSI UART HSIC DTV JTAG Note Unless otherwise noted all resistor values are 5 amp trace impedance values are 15 Signal Name Conventions The following conventions are used in describing the signals for Tegra Signal names use a mnemonic to represent the function of the signal i e Secure Digital Interface 3 CMD signal is SDMMC3_CMD written in bold to distinguish it from other text Active low signals usually have an underscore followed by capital N _N after the name i e SYS_RESET_N Differential signals are identified as a pair with the same names that end with _P and _N or just P and N for positive and negative respectively For example USB1_DP and USB1_DN indicate a differential signal pair 1 0 Type The signal I O type is represented as a code to indicate the operational characteristics of the signal The table below lists the I O codes used in the signal description tables Table 12 Signal Type Codes Code Definition A Analog DIFF 1 0 Bidirectional Differential Input Output DIFF IN Differential Input DIFF OUT Differential Output 1 0 Bidirectional Input Output l Input 0 Output OD Open Drain Output 1 OD Bidirectional Input Open Drain Output P Power General SFIO Special Function 10 amp GPIO General Purpose IO selection The SFIO
4. Tegra eDP LVDS eDP ose Nt TE 41 05V RUN AVDD 550 HON on i FO 01uF 3 3V LPO T poo voso pu 0 01uF EFREN 0 01uF 0 01uF D 1kQ 1Y6 100kQ HV 3 3V LPO Note Filters on the DSI signals are not recommended If EMI is a concern other solutions such as using PCB GND layers or other shielding is preferred If EMI devices are necessary they must be tuned to minimize the impact to signal quality which must meet the timing amp Vil Vih requirements at the receiver amp not introduce glitches on the signal edges Any ESD solution must also maintain signal quality and meet requirements for the frequencies supported by the design See the Power Decoupling Guidelines section for power rail decoupling and filter requirements Figure 26 LVDS 4 Lane Connection Example Tegra LVDS LVDS eDP 1 05V RUN AVDD TY m 3 3V LPO 1kQ 1 3 3V_LPO VDDIO 1V8 Note Filters on the DSI signals are not recommended If EMI is a concern other solutions such as using PCB GND layers or other shielding is preferred If EMI devices are necessary they must be tuned to minimize the impact to signal quality which must meet the timing amp Vil Vih requirements at the receiver amp not introduce glitches on the signal edges Any ESD solution must also maintain signal quality and meet requirements for the frequencies supported by the design See the Power Decoupling Guidelin
5. PEX TERNP is shared by PCle amp USB3 blocks See routing requirements in USB section Table 54 PCle Signal Connections Ball Name Type Termination Description PEX USB3 TXOP N DIFF OUT PEX TX 4 2 P N Series 0 1uF capacitors Differential Transmit Data Pairs Connect to PCle TX P pins of PCle device connector through AC cap according to supported configuration See Note 1 PEX USB3 RXOP N DIFF IN PEX RX 4 2 P N Series 0 1uF caps only if direct device connection Differential Receive Data Pairs Connect to PCle RX P pins of PCle device connector through AC cap according to supported configuration PEX L 1 0 CLKRE l QN PCle Clock Request Connect to CLKREQ pins on device connector s PEX_L 1 0 _RST_N l PCle Reset Connect to PERST pins on device connector s PEX_WAKE_N l 100KQ pullup to 3 3V_LPO PCle Wake Connect to WAKE pins on device or connector supply PEX_TERMP A 2 49KO 1 to GND PCle Calibration Connect to GND through termination resistor PEX_REFCLKP N DIFF OUT PCle Reference Clock Unused connect to GND See note 1 PEX_TSTCLKP N DIFF OUT PCle Test Clock Unused Leave NC DVDDIO_PEX P PCle Digital I O Power Rail Connect to 1 05V supply AVDDIO PEX P PCle Analog I O Power Rail Connect to 1 05V supply through bead AVDD PEX PLL P PCle Analog Power Rail for Transmit PLL Connect to 1 05V supply HVDD PEX P PCle High Voltage Power Rail Co
6. Parameter Requirement Units Note Reference plane GND if possible See note 1 Trace Spacing 3x Dielectric Max Trace Delay Minimum See note 3 Note If GND reference is not feasible as may be the case with GSSG stack up keep the routing distance very short and have GND areas traces next to the rails Use reference platform layout as a guideline for routing amp location of bypass capacitors amp filters Avoid routing signal traces or other power traces areas directly above below or in parallel with these critical rails 3 2 2 Additional PLL Power Noise Coupling Reduction Guidelines See the Tegra PLL Power Design Guidelines section 7 for a detailed descriptions and informative figures showing design practices to minimize noise coupling between some of the critical PLL power rails and other noisy power rails The following tables contain the measureable guidelines that should be followed in addition to other recommendations in section 7 Table 15 PLL Power amp I O Power Via Coupling Requirements PLL PWR Via Victim PLL Power Rail Via Minimum Distance PCB Height Other Requirements Aggressor Via center to via center PLLM PWR Pin K16 1 35V_LPO_VDDIO_DDR_AP 1 3 mm lt 40mil PLLM PWR Pin K16 1 35V_LPO_VDDIO_DDR_AP 1 5 mm gt 40mil PLLA PLLP PLLC2 1 05V_DDR_AVDD Pin A17 1 1mm ALL PWR pins on edge GND via must be placed in PLLC3 PWR Pin of die to less between two Power VIAS B17 const
7. 2014 2015 NVIDIA Corporation All rights reserved Page 97 of 115 Tegra K1 Embedded Platform A Design Guide NVIDIA 7 1 2 1 Power Merging Strategy for PLLAPC2C3 Power and 1 05V_DDR_AVDD_HS Following section will provide a strategy to merge the two power supplies while still providing adequate isolation to coupling The merging will happen at the bottom layer of the PCB and the high frequency noise will be filtered by then The PLL and the HS are driven by the same PMIC on the PCB so eventually there will have to a shorting connection between the two powers Instead of shorting the vias directly to a plane a better isolation strategy can be achieved by routing each power rail through a power trace filtered by a 1uF and 0 1uF capacitor when merging the two rails refer figure 10 Figure 54 Provides a bad case and a good case in how to merge the power rails on the bottom layer Bad Case Merging Rails still strong coupling GOOD Case Merging Rails good isolation Bad Case Merging has the PTH power VIAS shorted by a plane while the good case will have some trace to capacitors on a plane to provide more isolation PLL PWR VIA amp HS PWR VIA 7 2 Other Design Considerations Avoid Routing PLL power traces below or above noisy planes Figure 14 PLLM Power Trace Layer 4 and 1 8V Power Plane Layer 5 Bad Routing PLLM PWR Trace Grey Plane is 1 8V routed above PLLM Tegra K1 DG 07508 001v03 Copyright 20
8. NVIDIA Table 62 HSIC_REXT Routing Requirements Parameter Requirement Units Note Reference plane GND if possible See note 1 Trace Impedance 50 Q 15 Max Trace Delay 140 ps Include Package amp PCB routing delays Keep HSIC related traces including HSIC_REXT away from other signal traces or unrelated power traces areas or power supply components Note 1 f stack up makes GND reference difficult keep routing distance very short amp have GND areas next to HSIC REXT trace 2 Use reference platform layout as a guideline for routing amp location of HSIC REXT resistor 3 Avoid routing signal traces directly below and in parallel with these critical rails Table 63 HSIC Signal Connections Ball Name Type Termination Description HSIC 2 1 STRO 1 0 0Q series resistors for early designs HSICx Strobe Connect to STROBE pins on HSIC device BE HSIC 2 1 DAT I O Same as above HSICx Data Connect to DATA pins on HSIC device A HSIC_REXT A 1 0KQ 1 to GND HSIC External Reference Resistor Connect to termination to GND Table 64 HSIC Interface Package Delays Signal Name Ball Pkg Delay ps HSIC1_DATA AF18 54 HSIC1_STROBE AE18 55 HSIC2_DATA AG18 57 HSIC2_STROBE AD18 82 HSIC_REXT AH18 58 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 55 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 3 5 Display Te
9. TX amp RX routing to minimize Xtalk 1 Ideal solution is to breakout TX amp RX breakout on different layers 2 Ifin same layer recommend not interleaving TX amp RX traces for minimizing NEXT If routing on the same layer increase inter pair spacing using the methods below a Use the recommended trace dimension for breakout amp main route tt length limitation from the table below PCB HDI Standard Line Type Stripline Stackup GSSG Micro strip Section breakout main trace breakout main trace Trace Widths 1x 1 32x 1 32x 1 32x Inter S Within Pair 1 167x 1 68x 1 32x 1 32x Inter Syexr Between TX RX 4 85x 53X 1 32x gt 4x wS Between TX TX or siz Six 1x pa Length lt 11mm lt 170mm Lyox lt 4mm lt 170mm Lox all Nx values in the table are for trace spacing in terms of the minimum dielectric height Lork is the breakout trace length Note z If the TX RX sequence cannot be non inerleaved in the breakout all the inter pair spacing should follow the rule of inter SNEXT Having different trace dimensions for breakout amp main route provides optimal near end Xtalk suppression Strongly suggest to have non interleaved sequence in the main route Since breakout route is much shorter than main route min trace width should be selected for breakout trace to increase inter pair spacing z Having different trace dimensions for breakout amp main route provide optimal near end Xtalk
10. HBR2 5x 7x spacin 750 900 ps 150ps inch delay assumption for Max Propagation Delay HBR2 5x 7x spa microstrip Max number of signal vias RBR HBR HBR 4 2 HBR2 One more test via right after AC cap OK PCB pair pair spacing RBR HBR HBR 4x 5x 7x dielectric height PCB main link to AUX Spacing 5x dielectric height Signal Skews Stripline or Microstrip Max Intra pair within pair Skew 1 ps See Note 1 amp 2 Max Inter pair pair pair Skew 150 ps See Note 1 amp 2 Note Max Trace Delay amp Max Trace Delay Skew matching must include substrate pin delays unless otherwise specified Recommend doing trace length matching to lt 1ps before vias or any discontinuity to minimize common mode conversion Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 58 of 115 D Tegra K1 Embedded Platform Design Guide NVIDIA Table 67 Additional eDP Requirements Recommendations Parameter Requirement Units Note Max PCB via distance from BGA RBR H No requirement HB 7 63 0 3 mm in Max signal transition vias 2 Recommend lt 2 for predominately stripline routing amp lt n 4 for predominately microstrip routing Main Trunk routing Stripline Recommended Max GND transition via distance lt 1x diff pair For signals switching reference layers add pitch symmetrical ground stitching via near signal vias AC coupling cap 100 nF Discrete
11. Level shifters used when required 12C are of type DD which do not require level shifters to support up to 3 3V devices Pull up resistors are provided on all I2C I F segments including on either side of any level shifters Pull up resistor values based on reference design or section 7 1 of the NXP Philips I2C bus specification amp user manual Version 3 PWR GEN1 GEN2 CAM 12C SCL SDA connect to SCL SDA pins of devices Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 111 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA Description Same Diff NA 12C pull ups to same rail as block I2C I F is on or to rail up to 3 3V given all devices on bus segment support the higher voltage DDC_SCL SDA connect to CLK Data pins of devices 1 8K pull ups to 5V HDMI If 12C6 function used eDP panel or other VDDIO_HV is from 2 8 3 3V Tegra K1 SPI Clock SPIx_SCLK connects to Peripheral CLK pin SPI Master Out Slave In SPIx_MOSI connects to Peripheral MOSI pin SPI Master In Slave Out SPIx_MISO connect to Peripheral MISO pin SPI Chip Selects SPIx_CSx connects to Peripheral CS pin UARTx_TXD connects to Peripheral RXD pin of device UARTx_RXD connects to Peripheral TXD pin of device UARTx_CTS_N connects to Peripheral RTS_N pin of device UARTx_RTS_N connects to Peripheral CTS_N pin of device Table
12. SE Impedance Diff Impedance at x Dielectric Height Spacing Single ended SE impedance of trace along with differential impedance for diff pairs is achieved by spacing requirement Spacing is multiple of dielectric height Dielectric height is typically different for microstrip amp stripline Note 1 mil 1 1000th of an inch Note Trace spacing requirement applies to SE traces or differential pairs to other SE traces or differential pairs It does not apply to traces making up a differential pair For this case spacing trace widths are chosen to meet differential impedance requirement General Routing Guidelines Pay close attention when routing high speed interfaces such as DDR HDMI USB HSIC or DSI CSI Each of these interfaces has strict routing rules for the trace impedance width spacing total delay and delay flight time matching The following guidelines provide an overview of the routing guidelines and notations used in this document Controlled Impedance Each interface has different trace impedance requirements amp spacing to other traces It is up to designer to calculate trace width amp spacing required to achieve specified single ended SE amp differential Diff impedances Max Trace Lengths Delays Trace lengths delays should include main PCB routing where Tegra resides and any additional routing on a Flex secondary PCB segment connected to main PCB The max length delay should be from Tegra to the a
13. Tegra PCle Available for 2 USB 3 0 or PEX x4 Lane GigE LAN REFCLK_P REFCLK_N CLKREQB PERSTB HS1P HS1N HSOP HSON LANWAKEB 1 05V RUN AVDD 3 3V LPO Available for PEX x2 x4 Lane Note See the Power Decoupling Guidelines section for power rail decoupling and filter requirements Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 48 of 115 A NVIDIA PCle Design Guidelines Table 52 PCle Interface Signal Routing Requirements Tegra K1 Embedded Platform Design Guide Parameter Requirement Units Note Max Frequency UI Period 5 0 200 Gbps ps 2 5GHz half rate architecture Topology Point point Unidirectional differential Configuration Device Organization 1 Load Max Load per pin N A pF See return loss spec in PCle 2 0 spec Termination 50 Q To GND Single Ended for P amp N Reference plane GND Breakout Region Width line spacil 4 Mils Maximum pair spacing of 500 mils pair spacil 10 Trace Impedance differential Single End 90 Q 15 45 60 Pair to Pair Trace Spacing Stripline Microstr 3x 4x Dielectric Tx to Rx spacing Recommend Tx amp Rx signals routed on separate layers w GND between for isolation See note 1 Spacing to planes cap pads Stripline Microsty 3x 4x Dielectric Max Trace Length Delay 10
14. 5V_HDMI 1200 100mhz bead amp 0 1uF HDMI 5V supply to connector Connect through filter to decoupling capacitor 5V on HDMI Connector Table 83 HDMI Interface Package Delays Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Delay Delay Delay Delay ps ps ps ps HDMI_TXCN AF5 29 HDMI_TXDON AD5 29 HDMI_TXD1N AD4 38 HDMI_TXD2N AD2 49 HDMI_TXCP AF6 29 HDMI_TXDOP AD6 29 HDMI_TXD1P AD3 39 HDMI_TXD2P AD1 50 HDMI_RSET AF2 43 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 68 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 3 6 Video Input Interfaces 3 6 1 MIPI CSI Camera Tegra supports three MIPI CSI interfaces allowing a variety of device types and combinations to be supported Up to two quad lane amp one single lane connections are available Each data channel has peak bandwidth of up to 1 2Gbps The figure below shows the configuration supported on the Jetson TK1 platform supporting two CSI imagers Camera 1 amp 2 Camera 1 uses 4 CSI lanes CSIA 1 0 amp CSIB 1 0 Camera 2 uses a single lane CSIE 0 Other combinations are possible and listed in the CSI Configurations table Figure 31 Camera Connection Example 1 05V_RUN_CAM_REAR ee eee Camera 1 1200 100MHz i 412V GEN Avpp CSI 47uF iH 2 8V_RUN_CAM 120Q 100MH
15. DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 88 of 115 Tegra K1 Embedded Platform Design Guide A NVIDIA 5 0 Unused Interface Terminations 5 1 Unused Muxed Standard CMOS Pad Interfaces The following interfaces use the I O pins that support multiple special functions SFIO and GPIO capabilities Any unused interfaces or portions of these interfaces that are not used can be left unconnected or used for other SFIO functions or as GPIOs Any of the power rails associated with these interfaces that are not used for any purpose can be left as no connects or connected to GND Function Interface Block Power Rail SDMMC1_x SDMMC1 VDDIO_SDMMC1 SDMMC2_x GMI VDDIO GMI SDMMC3 Xx SDMMC3 SYS VDDIO SDMMC3 VDDIO SYS SDMMC4 Xx SDMMC4 VDDIO SDMMC4 I2Sx Various Various Ux3 IR3x UART Various Various SPIx Various Various PWFMx Various Various EXTPERIPHx CLK Various Various GPIOx Various Various 12Cx 12CPMU DDC Various Various SPDIFx HV VDDIO_HV DTVx GMI UART VDDIO_GMI VDDIO_UART DCAx SYS VDDIO SYS PEX CTL PEx CLKREQ L PEXx RST L PEX WAKE L PEX CTL VDDIO PEX CTL SOC THERM 0C 3 0 N GMI SYS VDDIO GMI VDDIO_SYS CLDVFSx AUDIO GMI SYS VDDIO_AUDIO VDDIO_GMI VDDIO_SYS USB VBUS EN 2 0 PEX CTL HV VDDIO PEX CTL VDDIO HV DP HPD HV VDDIO_HV VGP 5 3 CAM VDDIO_CAM VIMCLK_x VIMCLK2_x CAM VDDIO_CAM TRAC
16. DR DQ 49 DR D0 54 DR D0 51 DR D0 52 DR_DQ 48 DR D0 55 DR DO 50 DR_DQS6P DR_DQS6N DR DM 6 DR D0 46 DR DQ 47 DR D0 42 DR DQ 44 DR DQ 40 DR DQ 41 DR DQ 45 DR D0 43 DR_DQS5P DR DOS5N DR DM 5 DR DQ 61 DR_DQ 60 DR_DQ 57 DR D0 62 DR_DQ 56 S o alu nv ry AQALALASALO ALA aloalo a A RA uju wo sya mj m m m had oj oj o Sly Flr ne 0 DDR A 84 DR A1 4 o DDR BA 2 2 DDRA I2 AN N7 JA 7 DR_DQ37 _CAS_ AS_L jm B21 DDR DO38 ESET_L DR_DQ39 DR_DQS4P DR_DQS4N DTI DR_DM4 DR_DQ40 DR_DQ41 DR_DQ42 DR_DQ43 DR_DQ44 ODTO DR_DQ45 ODT1 DR_DQ46 ODTO DR DQ47 SL DR_DQS5P Sears Paes DR_DQS5N DR_DM5 DR_DQ48 DR_DQ49 DR_DQ50 DR_DQ51 DR_DQ52 DR DQ53 DR_DQ54 E27 B26 C26 g AA Ka a proa oa 1 o AZZ o pras proas 1 FS oa Q O pras poas 1 Hs pRa pra r DR D055 DR_DQS6P 05 _ DDR_DQSON__ DDR_DQSON 1 G3 _ LOQS L DZ3__ DDR_DOS6N ci pooo DDR _OM o 1 _ DR DNS DR_DQ56 a13 DR D057 010 DR D058 ar DR D059 E Ran poroa 1 07 bos C31_ DDR_DQ60 DR_0Q61 DR D0 59 oo DoR Dara DoR DA DR_DQ62 DR D0 58 Es popas DDR Do z0 1 a on DR DALES unas j DR DQS7P DDR DQS7P H9 DOR DaSIN DDR DaN 89 o C E UDM C23 F24 C29 0 9 9 9 9 9 9 mi e O felis I2 fe i OIN ad ul par nn g o o Note The DDR pin remapping must be followed exactly as shown above Tegra K1 DG 07508 001v03 Copyright 2014
17. HS PLLP_OUTO 408MHz 3 0x2 3 0x2 7 1 Not allowed Table 107 12C Interface Package Delays Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Delay Delay Delay Delay ps ps ps ps CAM_I2C_SCL AF8 51 GEN1_I2C_SCL P6 61 GEN2 12C SCL Y2 74 PWR_I2C_SCL J4 70 CAM_I2C_SDA AG8 55 GEN1_I2C_SDA M6 61 GEN2_I2C_SDA AA2 87 PWR_I2C_SDA J3 70 3 10 UART Tegra has multiple UART controllers See the Tegra K1 Data Sheet Multiplexing tables for where these interfaces are available Work closely with your NVIDIA support team when choosing which location to ensure there are no conflicts and the configurations are fully supported by the software Figure 36 Basic 4 wire UART Connections Tegra UART Peripheral UART Table 108 UART Signal Connections Ball Name Type Termination Description UART1 x TXD O UART Transmit Connect to Peripheral RXD pin of device UART1 x RXD UART Receive Connect to Peripheral TXD pin of device UART1 x CTS l UART Clear to Send Connect to Peripheral RTS_N pin of device UART1 x RTS O paka Request to Send Connect to Peripheral CTS pin of evice Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 82 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 3 11 SPI Tegra has multiple SPI controllers Jetson uses SPI4 on the GMI block f
18. N 1 0 CSI A B Differential Data Lanes Connect to Dn amp Dp pins of P Camera 1 CSI B D 1 0 N P CSI_E_CLK_N P CSI E Differential Clock Connect to CLKn amp CLKp pins of Camera 2 CSI_E_D_N P 1 0 CSI E Differential Data Lanes Connect to Dn amp Dp pins of Camera 2 CSI DSI RDN A 49 90 to GND DSI CSI Voltage Reference Pull down Connect through termination to GND CSI DSI RUP A 4530 to 1 2V GEN AVDD DSI CSI Voltage Reference Pull up Connect through termination indicated to same rail as AVDD CSI DSI AVDD CSI DSI P MIPI DSI amp CSI Shared Power Rail Connect to 1 2V GEN AVDD supply Note Depending on the mechanical design of the platform and camera modules ESD protection may be Table 88 Miscellaneous Camera Connections necessary Any ESD solution must be compatible with the frequency required by the design Ball Name Type Termination Description CAM 12C SCL Pull ups to 1 8V RUN CAM Camera I2C Interface Connect to I2C SCL amp SDA pins of cameras CAM 12C SDA CAM MCLK Camera 1 Master Clock Connect to Camera 1 reference clock input GPIO_PBBO CAM2_MCLK Camera 2 Master Clock Connect to Camera 2 clock input GPIO_PBB3 CAM_RST_L Camera Reset Connect to Camera reset inputs GPIO_PBB4 CAM_FLASH Camera Flash Connect to Flash driver enable if Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 71 of 115 A Tegra K
19. Pkg Delay ps THERM_DN U29 63 THERM_DP U28 62 JTAG is not required but may be useful for new design bring up Regardless of whether JTAG is implemented the JTAG_TCK pull down resistor shown in the figure is required Note that JTAG TRST N is not used as a conventional JTAG reset line Instead this pin selects whether JTAG is to be used for communicating with the Tegra CPU complex or for Test Scan purposes When JTAG_TRST_N is pulled low the JTAG interface is enabled for access to the CPU complex When high it is in Test Scan mode For normal operation JTAG_TRST_N must be pulled low Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 85 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA Figure 40 JTAG Connections Option to pull JTAG_TRST_N high to enter Scan Mode Leave resistor out for normal operation or JTAG connection to CPUs AVP AHB Tegra VDDIO_1V8 To Degug JTAG Connector VDDIO_1V8 Note See the Power Decoupling Guidelines section for power rail decoupling and filter requirements Table 115 JTAG Signal Connections Ball Name Type Termination Description JTAG_TMS l JTAG Mode Select Connect to TMS pin of connector JTAG_TCK l 100kQ to GND JTAG Clock Connect to TCK pin of connector JTAG_TDO O JTAG Data Out Connect to TDO pin of connector JTAG TDI l JTAG Data In Connect to TDI pin of conne
20. Table 91 DTV Signal Connections Function Name Type Termination Description DTV_CLK l DTV Clock Connect to Tuner CLK pin DTV_DATA l DTV Serial Data input Connect to Tuner DATA pin DTV_VALID l DTV Valid input Connect to Peripheral Tuner VALID pin DTV_ERR_PSYNC l DTV Error packet indicator or packet sync input Connect to Tuner ERROR or PSYNC pin Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 73 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 3 7 SDMMC Tegra has four SD MMC controllers Jetson uses SDMMC3 for an SD Card interface and SDMMC4 to interface to an eMNC device one of the boot options SDMMC1 is available to use as SDIO to connect to a WiFi controller SDMMC2 on the GMI block is available for SDIO use as well For the SD card and SDIO interfaces SDMMC 3 1 support up to UHS 1 For eMMC SDMMC4 supports up to HS200 3 7 1 eMMC Figure 33 Jetson eMMC Device Connections VDDIO_1V8 VDDIO 1V8 Tegra eMMC 4 7K eMMC 3 3V_RUN CLK VCC CMD VDDIO 1V8 SDMMC4 DAT 70 DATATO veca ESOM NN q4VDDIO 1v8 sommea come Po AAA Reset from PMU gt RST Note An EMI filter on SDMMC4_CLK or other eMMC signals is not recommended If EMI is a concern other solutions PCB GND layers external shielding etc are preferred If EMI devices are used they must be tuned such that the signals meet
21. 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 006 006 060 000 009 009 000 000 DDR3L 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 009 009 000 000 006 000 000 000 X16 Sco sa Sco 990 Sco 800 Soo 800 006 009 000 060 009 009 600 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 009 000 000 000 000 000 060 000 000 000 000 000 000 000 000 000 006 ooe 060 ooe 000 ooe 000 000 A1 A1 A1 A1 The following tables show the connections from TK1 out to the four DDR3L DRAM devices The tables include columns that contain the TK1 symbol ball number the net name used to connect to the DRAM which device the net is going to the DDR ball number and finally the DDR ball name All of these should be duplicated on a design The same symbol ball out same net names associated with each ball etc should be used to ensure the connections match and can be easily verified against the table and or reference design Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 28 of 115 A NVIDIA Tegra K1 Embedded Platform Design Guide Table 21 DRAM Pin Multiplexing Option 14 DDR3L 4x16 2 Top 2 Bottom Vertical Tegra Tegra DDR3L DDR DDR DDR Tegra Tegra DDR3L DDR DDR DDR Ball Ball Name Net Name Device Ball Ball Name Ball Ball Name Net Name Device Ball Ball Name D
22. 1700 in ps For trace with loss lt 0 4dB in 2 5GHz See note 2 amp 3 Max Within Pair Trace Delay Skew 1 ps See note 3 amp 4 Max Pair to Pair Trace Delay Skew 600 ps See note 3 amp 4 RX to RX or TX to TX Within Link Trace Width Options 4 5 6 Mils See note 2 Note 1 If routing in the same layer is necessary route group TX amp RX separately wo mixing RX TX routes amp keep distance between nearest TX RX trace amp RX to other signals 3x RX RX separation 2 For with trace loss gt 0 7dB in 2 5GHz the max trace length should be 7 5 inches To reduce trace loss ensure the loss tangent of the dielectric material amp roughness of the metal are tightly controlled 3 Include Package amp PCB routing delays for Max trace delays and max trace delay skew parameters 4 Do trace length matching before the vias to transition to different layers or any discontinuity to minimize common mode conversion Table 53 Additional PCle Interface Signal Routing Guidelines Maximum of Vias Maximum of 4 vias per TX traces and 2 vias per RX trace Routing signals over the antipad Not allowed Routing over voids When signal pair approaches vias the maximal trace length across the void on the plane is 50mil Serpentine line rule For microstrip line minimal spacing between each turn is 4x dielectric For stripline it is 3x dielectric height 3x of thinner of above amp below PT
23. 2015 NVIDIA Corporation All rights reserved Page 30 of 115 a gt Tegra K1 Embedded Platform Design Guide NVIDIA DDR3L Design Guidelines Note o The topology for each signal must be followed exactly as shown in the figures included for each signal group The Requirements are 32 bit channel except the DDRO CLKP DDRO CLKN to DDR1_CLKP DDR1_CLKN requirement 5 New Skew requirement term definitions o Center mean the skew is measured from the clock strobe center signal to the related signals either before or after the strobe clock and must meet the required max value o Absolute mean the maximum skew between any of the signals listed is within the required max value o Load to Load means that the skew is the total of the path from Tegra out to the destination load for each signal involved in the requirement This allows for asymmetric routing of the different branches in T topologies as long as the total lengths delays are within the requirement value Figure 15 Single Rank 16 bit DDR3L DQ DOS DQM Point Point Topology Used w 2 T Address Topology Main Trunk Tegra HOOD DDR3L Table 23 DDR3L 4x16 Data Signal Group Routing Requirements Parameter Requirement Units Note Max Frequency Data Rate 933 1866 MHz Mbps See note 1 Switching Period T 0 5 T Topology Direct Configuration Device Organization
24. 72 GPIO PK3 SDMMC2 DAT4 R2 71 SDMMC3 CLK LB OU T1 77 SDMMC1 COMP PU J7 63 T F4 73 GPIO_PK4 SDMMC2_DAT5 SDMMC3_COMP_PD E5 86 GPIO_PI2 SDMMC2_DAT6 v1 76 SDMMC3_COMP_PU E2 77 GPIO_PI6 SDMMC2 DAT7 R1 74 SDMMC2 COMP PD R6 78 SDMMC2 COMP PU U5 54 3 8 Audio Tegra supports Multiple PCM I2S audio interfaces amp includes a flexible audio port switching architecture Jetson uses DAP2 to interface to an audio Codec The Codec receives a master audio reference clock from the DAP_MCLK1 pin on Tegra Figure 35 Audio Device Connection Example Tegra Audio Codec Headphone Out Jack BCLK1 LRCK1 Mic Jack DACDAT1 ADEDATL AVDD VDDIO_1V8 MCLK DBVDD VDDIO 1V8 SCL CPVDD SDA DACREF CODEC IRQ L GPIO1_IRQ SPRYBDL SPKVDDR Q 5V_SYS LDO1_EN HEAD_DET_L IN2N_JD2 From Headphone Out Jack Detect Available for PCM Modem if Pins DAPIjX not used for other Functionality C DBA Available for 12S if Pins not used for other Functionality Available for PCM Bluetooth if Pins U DAP4FX not used for other Functionality Note Seethe Power Decoupling Guidelines section for power rail decoupling and filter requirements Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 78 of 115 A NVIDIA 12S Design Guidelines Table 100 12S Interface Signal Routing Requirements Tegra K1 Embedded Plat
25. All rights reserved end of the DSI section Page 72 of 115 Tegra K1 Embedded Platform A Design Guide NVIDIA 3 6 2 Digital TV DTV Tegra has a DTV interface to support compatible DTV DVB D amp ISDB T tuners The interface is located on the GMI block as shown in the figure below Figure 32 Basic DTV Connections Tegra DTV Tuner GMI GPIO PH7 kaDTV CLK CLK GPIO_PH6 lag DTV DATA DATA GPIO_PHO kagDTV VALID VALID VDDIO_GMI 1 8V GPIO_PI7 kg PTVLERR PSYNC PSYNC ERROR Note See the Power Decoupling Guidelines section for power rail decoupling and filter requirements DTV Design Guidelines Table 90 DTV Interface Signal Routing Requirements Parameter Requirement Units Note Max Frequency 32 MHz Configuration Device Organization 1 load Max Loading total of all loads 15 pF Reference plane GND Breakout Region Impedance Minimum width amp spacing Max PCB breakout delay 75 ps Trace Impedance 50 60 Q 15 Via proximity Signal to reference lt 3 8 24 mm ps See Note 1 Trace spacing Microstril 4x dielectric Striplin 3x Max Trace Delay 850 5 ps in See Note 2 Max Trace Delay Skew 30 ps See Note 2 DATA VALID amp ERR PSYNC to CLK Note 1 Up to 4 signal vias can share a single GND return via 2 Include Package amp PCB routing delays for Max trace delays and max trace delay skew parameters
26. Common Mode Choke Requirements Optional Only used if rare EMI issue is seen Parameter Requirement Units Note Common mode impedance at 100MHz j 65 Q N 90 Rdc Max 0 3 Q Differential mode impedance ZO at 2 5GHz 90 Q 15 Differential insertion loss Sdd21 at 2 5GHz lt 2 22 dB Common to Common insertion loss Scc21 at 2 5GHz gt 19 2 dB Table 51 USB 3 0 Interface Package Delays Signal Name Ball Pkg Delay ps Signal Name Ball Pkg Delay ps USB3_RXON AL21 43 PEX_USB3_RX1N AL23 46 USB3_RXOP AK21 43 PEX_USB3_RX1P AK23 46 USB3_TXON AJ21 36 PEX_USB3_TX1N AG21 26 USB3_TXOP AH21 35 PEX_USB3_TX1P AF21 26 PEX TERMP AL22 54 Note If the USB 3 0 interface is coming from the SATA balls get the package delays from the table at the end of the SATA section Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 47 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 3 4 2 PCle Tegra contains two PCle controllers that support up to 5 lanes and 2 separate interfaces These narrow high speed interfaces can be used to connect to a variety of high bandwidth devices The example below is from the Jetson TK1 design See the table USB 3 0 PCle amp SATA Lane Mapping Use Cases at the beginning of the USB PCle SATA Interfaces section for other PCle options Figure 21 Jetson PCle Connections
27. Connections Ball Name Type Termination Description SATA LO TXP N DIFF OUT Series 0 01uF caps Differential Transmit Data Pair Connect to SATAN P pins of SATA device connector through termination capacitor SATA_LO_RXP N DIFF IN Series 0 01uF caps Differential Receive Data Pair Connect to SATAN P pins of SATA device connector through termination capacitor SATA_TERMP A 2 49KO 1 to GND SATA Calibration Connect to GND through termination resistor SATA_TSTCLKP N DIFF OUT SATA Test Clock Unused Leave NC VDDIO_SATA P SATA I O Power Rail Connect to 1 05V supply AVDD SATA PLL P SATA Analog Power Rail for Transmit PLL Connect to 1 05V supply HVDD SATA P SATA High Voltage Power Rail Connect to 3 3V supply Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 53 of 115 A NVIDIA Table 60 SATA Interface Package Delays Tegra K1 Embedded Platform Design Guide Signal Name Ball Pkg Delay ps Signal Name Ball Pkg Delay ps SATA_LO_RXN AH27 44 SATA_LO_TXN AK27 50 SATA_LO_RXP AJ27 44 SATA_LO_TXP AL27 49 SATA_TERMP AL25 55 3 4 4 HSIC Tegra supports two HSIC interfaces These 2 pin 1 2V CMOS interfaces can connect to compatible modems Wi Fi controllers USB PHYs etc The example below from the Jetson design brings the HSIC1 interface to the General Expansion Header Figure 23 Jetson HSI
28. DDR1_CS 1 0 _N DDR1_CKE 1 0 tt DDR1_ODT 1 0 nets connect to CS CKE ODT pins of all DRAM used in the upper 32 bits VDDIO_DDR_HS connects to 1 05V supply ZQ 1 0 on DRAM device connect to 2400 1 pull downs to GND Decoupling on VDD for each DRAM device is 3 0 1uF amp 1 4 7uF capacitors Decoupling on VDDQ for each DRAM device is 3 0 1uF amp 1 4 7uF capacitors 900 2 45 30 1 between CLK_P amp N pins 0 01uF cap center tapped to GND Connected at end of main trunk 2 2pf capacitor between CLKP amp CLKN close to Tegra pins DDR_A 15 6 2 0 nets connect to A 15 6 2 0 pins of all DRAMs DDRO_A 5 3 nets connect to A 5 3 pins of all DRAM used in the lower 32 bits DDR1_A 5 3 nets connect to A 5 3 pins of all DRAMs used in the upper 32 bits DDR_BA 2 0 nets connect to same BA pins of all DRAMs DDR_CAS_N DDR_RAS_N DDR_WE_N nets connect to CAS_N RAS_N amp WE_N pins respectively of all DRAMs DDR_COMP_PU pulled up with 340 1 to 1 35V amp DDR_COMP_PD pulled down with 340 1 to GND VDDIO_DDR VDDIO_DDR_MCLK amp DRAM VDD VDDQ connect to 1 35V supply VSS VSSQ on DRAM devices connect to GND Decoupling on VDD for each DRAM device is 3 0 1uF amp 1 4 7uF capacitors Decoupling on VDDQ for each DRAM device is 3 0 1uF amp 1 4 7uF capacitors Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 106 o
29. DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 115 of 115
30. DSI B D1 P AD12 48 CSI DSI RUP AF11 61 DSI A DIN AD14 50 DSI B CLK N AJ11 68 DSI B D2 N AL12 74 DSI A D1 P AE14 51 DSI B CLK P AH11 67 DSI B D2 P AK12 73 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 64 of 115 A NVIDIA 3 5 3 HDMI Tegra K1 Embedded Platform Design Guide A standard HDMI V1 4b interface is supported Figure 28 HDMI Connection Example 3 3V LPO 3 3V RUN Q Backdrive Prevention See Note 1 1 05V_RUN Q Load Switch FETs Note VDD_LPO 5V_HDMI Tegra HDMI 162KQ 1 HV 1kO 1 THOMIRSET NAW The backdrive block associated w AVDD_HDMI is used to prevent current passing back through Tegra when the 3 3V supply is off but the device is connected to a powered display Any ESD solution must also maintain signal integrity amp meet the HDMI requirements for the modes to be supported Ensure AVDD_HDMI supply can handle gt 100mA as there can be an increase in power consumption for 1second when the HDMI cable is unplugged from the display device before SW has a chance to disable the HDMI pads Filters on HDMI Clock Data lines are not recommended If EMI devices are necessary they must be tuned to maximize signal quality which must meet the HDMI specification for the modes to be supported See the Power Decoupling Guidelines section for p
31. Figure 45 Layer 3 Breakout W NG ail as KG Wi Mill JQ Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 93 of 115 Tegra K1 Embedded Platform Kg Design Guide NVIDIA Figure 47 Layer 5 Breakout Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 94 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 7 0 Tegra PLL Power Design Guidelines The following sections provide a detailed guideline for the sensitive PLL power rails The sensitive PLL power rails were determined by empirical lab measurement data The PLL CLK output jitter was recorded before and after stress test and the increase in jitter was used to determine its sensitivity to noise The spectrum of the CLK jitter was analyzed in relationship to the suspected I O rail noise to determine that the PLL noise was caused by coupling from an I O rail and not the self generated noise of the PLL itself 7 1 PLL Power Routing Design Guide The following section covers the power routing guidelines and provide a detailed tradeoff for best routing practices to minimize the coupling 7 1 1 PLLM PLL Power Routing Coupling Minimization Routing PLL PLL Power Rail PLL Power PIN Aggressor Rail PLLM 1 05V_RUN_AVDD K16 1 35V_LPO_VDDIO_DDR_AP Objective Increase the distance between the Vias White arrows to minimize the coupling 1 35V BGA
32. GND Trace Impedance 50 Q 15 Max Trace Delay 75 ps Include only PCB routing delay Table 58 Additional SATA Interface Signal Routing Guidelines Preferred routing layer for through hole SATA Connector Place AC caps on bottom layer if possible PCB trace connecting AC cap amp SATA connector should be on bottom layer as microstrip PCB trace connecting the Chip to the AC caps should be on the top layer Tegra Microstrip TX RX Top side Connector TX RX AC Cap Microstrip Bottom side In case AC cap has to be put on the top layer because of design constraints then the PCB trace connecting the connector to the AC cap should be on the bottom layer as shown below Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 52 of 115 A NVIDIA Tegra K1 Embedded Platform Design Guide Tegra Microstrip TX RX Top side Connector Microstrip Bottom side Preferred routing layer for SMT SATA Connector For SMT connector AC caps should be on top layer PCB trace connecting AC caps amp SATA connector amp Tegra to AC caps should be on top layer as microstrip Tegra Microstrip TX RX Top side Connector AC Cap TXIRX Microstrip Bottom side Recommendations for SMT Connector GND plane under signal pad should be voided for better differential mode amp common mode return loss Size of void should b
33. If PWR 0 01uF decoupling cap required for return current Include Package amp PCB routing delays for Max trace delays and max trace delay skew parameters If routing to SD SDIO device socket includes a flex or 2 PCB the max trace amp skew calculations must include all the PCBs flex routing Maximum frequencies may not be achievable even if max trace amp skew delays met due to impact on signal quality caused by additional connector amp dependent on flex design Parameter Requirement Units Note Reference plane GND Trace Impedance 50 Q 15 Max Trace Delay 240 ps Include Package amp PCB delays Note Keep SDMMCx_COMP_PU PD routing away from other traces on same layer or on adjacent layers Table 98 SD SDIO Signal Connections Function Signal Name Type Termination Description SDMMC 3 1 _CLK O See note for ESD protection SDMMC Clock Connect to CLK pin of device or socket SDMMC 3 1 CMD 1 O No external pull ups required SDMMC Command Connect to CMD pin of device or socket See note for ESD protection SDMMC 3 1 DAT 3 0 1 0 No external pull ups required See note SDMMC Data Connect to Data pins of device or socket for ESD protection SDMMC2_DAT 7 0 SDMMC3_CLK_LB_OUT IN SDMMC3 Loopback Clock Out In Route trace out from SDMMC3_CLK_LB_OUT and back to SDMMC CLK LB IN Length should match SDMMC3_CLK Average of SDMMC3_DAT 3 0 SDMMC 3 1 _COMP_PU A 33 20 1 t
34. LDO 6 3 3V_RUN 12C PMU Off 3 1 05V RUN CAM RE Rear camera 1 05V supply 1 05 PMU LDO 7 1 8V_VDDIO 12C PMU Off AR 3 3V_RUN_TOUCH High voltage touch rail 3 3 PMU LDO 9 5V_SYS 12C PMU Off 2 8V RUN CAM AF Camera autofocus rail 2 8 PMU LDO 10 5V_SYS 12C PMU Off 1 8V RUN VPP FUS Tegra VPP FUSE rail 1 8 PMU LDO 11 3 3V RUN 12C PMU Off 8 E 3 3V_AVDD_HDMI_A Tegra 3 3V HDMI rail 3 3 Dual FET backdrive 3 3V_RUN 1 05_RU 10 P_GATED prevention N Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 8 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Power Rails Usage V Power Supply or Source Enable Time Note Gate ms 1 05V_RUN_AVDD_ Tegra AVDD_HDMI_PLL 1 05 Dual FETs as load 1 05V_RUN Tegra OFF 7 HDMI_PLL_AP_GATE or switch 1 05V GPIO 1 2 1 2V_GEN_AVDD 1 2V VDD_1V5_MPCIE 1 5V Mini PCle supply 1 5 APL5910 LDO 5V_SYS 3 3V_LP 7 0 5V USB HS VBUS USB 3 0 Type A 1 5 0 TPS2065 Load SW 5V SYS Tegra Off GPIO USBO VBUS SW VBUS USB 2 0 Micro AB 5 0 TPS2065 Load SW 5V SYS Tegra Off GPIO 5V HDMI CON 5V to HDMI conn 5 0 TPS2553DRV Load 5V_SYS Tegra Off SW GPIO 3 3V SD CARD SD Card socket rail 3 3 TPS2553DRV Load 3 3V_SYS Tegra Off SW GPIO 5V_SATA SATA connector rail 5 0 SLG5NV 1430V 5V_SYS Tegra Off Gate GPIO Note Includes AVDD_USB VDDIO_HV HVDD_PEX HVDD_PEX_PLL_E VDDIO_PEX_CT
35. PLLM Typically used for DRAM controller OSC AVDD_PLLM nternal PLLC4 OSC AVDD_PLL_C4 nternal PLLX Used for CPU OSC AVDD_PLLX nternal PLLE PLL_REFE Used for USB3 PCle amp SATA blocks OSC AVDD_PLL_EREFE nternal PEX_PLL Used for USB3 PCle PHYs OSC AVDD_PEX_PLL nternal SATA_PLL Used for SATA PHY OSC AVDD_SATA_PLL Output VIMCLK Used for Camera 1 master reference clock Various CAM_MCLK VDDIO_CAM Output VIMCLK2 Used for Camera 2 master reference clock Various GPIO_PBBO VDDIO_CAM Output EXTPERIPH1_CLK Used for Audio MCLK etc Various DAP_MCLK1 VDDIO_AUDIO Output EXTPERIPH2_CLK Used for Touchscreen Clock etc Various CLK2_OUT VDDIO_SDMMC1 Output EXTPERIPH3_CLK General purpose clock output Various CLK3_OUT VDDIO_UART Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 23 of 115 Tegra K1 Embedded Platform Design Guide A NVIDIA Figure 10 Tegra External Clocking Block Diagram PMU T CLK32K 32 768 KHZ 3 2 1 Oscillator amp PLL Power Routing Tegra 12 MHz Audio Codec MCLK etc Touch Controller Clock etc Available Clock Output The routing requirements in the table below apply to the following critical clock power rails AVDD_OSC AVDD_HDMI_PLL AVDD PLL APC2C3 AVDD_PLL_X AVDD_PLL_M AVDD_PLL_UTMIP AVDD_PLL_C4 AVDD_PLL_CG AVDD_PLL_EREFE AVDD_PLL_UD2DPD Table 14 Clock Power Routing Requirements
36. VDDIO_SYS SYS2 1 8V_VDDIO must be valid before other Tegra I O rails All rails required for boot 32KHz clock amp OSC System Clock must be valid before SYS_RESET_N goes high See Tegra K1 Series Data Sheet for more details on power sequencing 2 3 Power Decoupling Guidelines See Checklist table at end of document for Decoupling requirements 2 4 Decoupling Capacitor Placement For VDD_CPU GPU CORE VDDIO_DDR amp DRAM power rails use areas on multiple layers to reduce the routing resistance from supply to power balls See the figures in this section for examples General Power Routing Guidelines Route power using thick areas duplicated on multiple layers where possible Minimize distance from supply to destination Connect overlapping areas on different layers with multiple vias to reduce resistance impedance CPU GPU CORE amp DRAM Routing amp Decoupling Placement Tegra decoupling capacitors should be placed on the bottom just below the power ball arrays For DRAM decoupling they can be below the power balls or next to the power balls on the same side of the PCB Use 35 40 mil width traces from the balls to the decoupling capacitors Make sure that the 35 40mils shape has a GND references on the adjacent layer Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 15 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA Figure 4 CPU CORE GPU amp DRAM
37. are not authorized for use as critical components in life support devices or systems without express written approval of NVIDIA Corporation Trademarks NVIDIA the NVIDIA logo and Tegra are trademarks or registered trademarks of NVIDIA Corporation in the United States and other countries Other company and product names may be trademarks of the respective companies with which they are associated Copyright 2014 2015 NVIDIA Corporation All rights reserved NVIDIA Corporation 2701 San Tomas Expressway Santa Clara CA 95050 1 408 486 2000 www nvidia com A NVIDIA Revision History Tegra K1 Embedded Platform Design Guide Version Date Description 01 NOV 24 2014 Initial Release 02 DEC 3 2014 Unused Interface Pins Added missing Special Function section in checklistPower Power Added missing VPP_FUSE section Added missing PLL Power Design Guide in appendix Video Input Added missing DTV section UART Added section 03 FEB 06 2015 Power Added note under Power Allocation table indicating correct PMU OPT version Updated Power tree to show all three power stages for VDD_CPU DRAM Removed text in various places in DRAM section related to DDR symbol being different from Data Sheet Updated DDR3L Pin Multiplexing tables to remove column for different Jetson TK1 ball names amp added related note identifying first reference schematic with matching T
38. i Decoupling for VDDIO SYS2 is Decoupling for VDDIO BB is Decoupling for VDDIO UART amp VDDIO_GMI together is Decoupling for VDDIO_SDMMC1 is Decoupling for VDDIO_SDMMC3 is Decoupling for VDDIO_SDMMC4 is Decoupling for VDDIO_AUDIO is o o o o o o o o o o o o o o o o o o Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 105 of 115 Design Guide A Tegra K1 Embedded Platform NVIDIA 2 2uF 4 7uF Same Diff NA Sapa 0 1uF 1uF Description 0201 0201 aun o Decoupling for VDDIO_CAM is 1 0 0 1 Decoupling for VPP_FUSE is 1 0 0 0 Table 122 DRAM Checklist Description Same Diff NA Pin re mapping matches configuration table in section 3 3 1 exactly DDR DQ 63 0 nets connect to same DQ pins of all DRAMs corresponding to the appropriate byte lane groupings DDR_DM 7 0 nets connect to same DM pins of all DRAMs corresponding to the appropriate byte lane groupings DDR_DQS 7 0 P N nets connect to same DQS DQS pins of all DRAMs matching the appropriate byte lane groupings DDRO_CLKP N connect to CK CK pins of all DRAMs used in the lower 32 bits DDR1_CLKP N connect to CK CK pins of all DRAMs used in the upper 32 bits DDRO CS 1 0 N DDRO_CKE 1 0 tt DDRO ODT 1 0 nets connect to matching CS CKE ODT pins of all DRAM used in the lower 32 bits
39. of PMU VDD_CORE_SENSE connects to FB_SD1_P pin of PMU GND_CORE_SENSE connects to FB_SD1_N pin of PMU VDD_GPU_SENSE connects to FB_SD6_P pin of PMU GND_GPU_SENSE connects to FB_SD6_N pin of PMU Power Tree Matches Jetson TK1 board TPS51220 3 3V SW used for 3 3V_SYS TPS51220 5 0V SW used for 5V_SYS SDO AS3728 Power Stage used for VDD_CPU SD1 AS3728 Power Stage used for VDD_CORE SD6 AS3728 Power Stage used for VDD_GPU PMU LX_SD 3 2 used for 1 35V LPO PMU LX_SD4 used for 1 05V_RUN PMU LX_SD5 used for 1 8V_VDDIO PMU LDOO used for 1 05V_RUN_AVDD PMU LDO1 used for 1 8V_RUN_CAM PMU LDO2 used for 1 2V_GEN_AVDD Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 103 of 115 A NVIDIA Tegra K1 Embedded Platform Design Guide Description Same Diff NA PMU LDO3 used for 1 05V_LPO_VDD_RTC PMU LDO4 used for 2 8V_RUN_CAM PMU LDO5 used for 1 2V_RUN_CAM_FRONT PMU LDO6 used for VDDIO_SDMMC3 PMU LDO7 used for 1 05V_RUN_CAM_REAR PMU LDO9 used for 3 3V_RUN_TOUCH PMU LDO10 used for 2 8V_RUN_CAM_AF PMU LDO11 used for 1 8V_RUN_VPP_FUSE Pre PMU PMU Switcher connections match reference design PMU Power Stage CPU CORE GPU connections match reference design PMU DC DCs connections match reference design PMU LDOs connect
40. suppression b Do not perform serpentine routing for intra pair skew compensation in the breakout region Y Pattern Via If TX amp RX vias are near each other place the pairs orthogonally as shown in figure to the right Recommended Placement TX amp RX vias placed in alighment increases Xtalk Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 44 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Serpentine a Use more serpentine runs to minimize the intra pair b Do not compensate for inter pair skew to Guideline spacing variation amp provide more spacing to other avoid increasing trace length adjacent traces Connector Connector used must be USB IF certified Table 44 USB_REXT Routing Requirements Parameter Requirement Units Note Reference plane GND if possible See note 1 Trace Impedance 50 Q 15 Max Trace Delay 75 ps Include only PCB routing delay Note 41 if GND reference is not feasible as may be the case with GSSG stack up keep the routing distance as short as possible amp have GND areas traces next to the USB_REXT trace 2 Use reference platform layout as a guideline for routing amp location of USB_REXT resistor 3 Avoid routing signal traces directly below and in parallel with these critical rails Table 45 PEX_TERMP Routing Requirements required for
41. that receives the output signal The particular part selected is an OnSemi NCS2202SQST2G This device has an open drain active low output which is pulled low when the VDD_SYS voltage drops below the selected threshold The open drain output is pulled up by an internal pull up resistor on the Tegra KB ROW15 pin Figure 9 Voltage Monitor Connections Voltage Monitor 619k0 196 NCS2202SQ2T2G VDD_SYS ING VCC CA YvDD sys 0 1uF DROOP ALERT Tegra your gt KB_ROW15 VDD 118 O VVV t IN VEE 270kQ 100nF Threshold Selection The exact threshold target for the circuit is dependent on the specific system characteristics There are a number of contributors to the ESR resistance of the system from the battery to the input of the system PMU A higher system ESR will result in a higher IR drop for a specific current level for a specific total amount of power being consumed from the battery The voltage threshold should be set based on the minimum system voltage plus a voltage delta This voltage delta represents the maximum droop below the voltage comparator threshold that is expected for high transient workloads possibly concurrent with modem transmit cycles 2 10 Deep Sleep Wake Considerations Certain events are required to generate a wake condition This can vary depending on Operation System Check to see which of the signals in the table below are required as wake events The wake pins used in the Jetso
42. the PMIC and CPU When the external temperature monitor detects that the TDIODE temperature is above a pre programmed Tshutdown the monitor s THERM output signals the PMIC to shut down the system without any software control This is a back up mechanism to the internal sensor based shutdown so its Tshutdown is intentionally margined to a higher temperature to avoid contention with internal sensor based shutdown Figure 39 External Thermal Diode Connection Example Temp Sensor 3 3V RUN 1 8V_VDDIO THERMD P 002 TMP451 To Tegra Hare D vcc OVERHEAT Indicator THERMD_P N THERMD N 002 d 5 0 1UF 3 Connect to THERM aq THERMD_N A RA Td n THERM AP OVERHEAT L pin on PMU GEN1 12C SCL To Tegra CA SCLK GEN1 INC GEN 2C SDA pin ALERT TEMP ALERT L Tegra GPIO PI6 GMI Block Table 112 Thermal Diode Temperature Sensor Interface Signal Routing Requirements Parameter Requirement Units Note Configuration Device Organization 1 load Reference plane GND Breakout Region Impedance Min width spacing Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 84 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Parameter Requirement Units Note Max PCB breakout delay 100 ps minimum spacing rules Trace Impedance Differential Single el 90 Nominal Q 15 Via proximi
43. the timing tt electrical requirements of the eMMC specification If included the filter should be near Tegra 5 See the Power Decoupling Guidelines section for power rail decoupling and filter requirements SDMMC4 eMMC Design Guidelines Table 92 SDMMC4 Interface Signal Routing Requirements Parameter Requirement Units Note Max Frequency Standard Mode 26 26 MHz w 8 bit width High Speed Modes 52M 52 52 MB s See Note 1 DDR 52M 52 104 HS200 200 200 Topology Point to point Max Loading 10 pF Reference plane GND or PWR See Note 2 Breakout Region Impedance 45 50 Q 15 Max PCB breakout delay 30 ps Trace Impedance 45 50 Q 15 Via proximity Signal to reference lt 3 8 24 mm ps See Note 3 Trace spacing Microstrip Stripli 4x 2x dielectric Max Trace 730 ps See Note 4 Max Trace Delay Skew in between CLK amp CMD DAT 50 ps See Note 4 Note 1 Actual frequencies may be lower due to clock source divider limitations Where frequencies cannot be achieved the next lower divider option will be used The clock source used for all but HS200 is PLLP at 408MHz 2 If PWR 0 01uF decoupling cap required for return current Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 74 of 115 A NVIDIA 3 4 parameters Up to 4 signal vias can share a single GND return via Include Package amp PCB routing delays for M
44. to Via Route in a manner to create maximum separation from the PLLM Via 7 1 1 1 Case Study for 3 different BGA to VIA Breakout Strategies The following provides examples of 3 different layouts that have varying degrees of isolation between the PLLM Power and the 1 35V power Case 1 Worst Coupling Isolation Case 2 Bad Coupling Isolation Case 3 Good Coupling Isolation Advised to reference Case 3 Breakout Strategy Figure 49 Case 1 Worst PCB Breakout Strategy VIAs Larger Circular areas Pads Smaller Circular areas Green GND Blue Etch Yellow PLL Power Connection Magenta 1 35V VDDIO DDR Power Connection Orange VDD CORE Power Breakout Shape from BGA to VIA for two signals open up the area of the PLLM power shape can be routed for more separation between PLLM and DDR Power Worst due to proximity of PTH VIAS of PLLM to the DDR Power PTH VIAS but good signal breakout strategy to breakout PLLM Power Connection Further Away Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 95 of 115 a gt Tegra K1 Embedded Platform Design Guide NVIDIA Figure 50 Case 2 Bad PCB Breakout Strategy better due to distance of PTH VIAS of PLLM to the DDR Power PTH VIAS VIAs Larger Circular areas Pads Smaller Circular areas Green GND Blue Etch Yellow PLL Power Connection Magenta 1 35V VDDIO DDR Power Connection Orange VDD CORE Power Breakout Sh
45. used for C C 2 DL Crystal Drive Level 300 uw 1 6 ESR Equivalent Series Resistance 100 Q 2 4 Start Time From AVDD_OSC on or Tstart SYS_CLK_REQ active coming out of Deep lt 6 10 mS Sleep T Tegra Oscillator Buffer drive strength register TBD 7 BUF_DRV value RBias Bias resistor value 2 MQ Note 1 Fo Fro C and DL are found in the Crystal Data Sheet 2 ESR RM 1 CO CL 2 where RM Motional Resistance CO Shunt Capacitance from Crystal Data Sheet Data Sheets may specify ESR directly consult manufacturer if unclear whether ESR or RM are specified 3 C Load capacitance Crystal Data Sheet CPCB is PCB capacitance trace via pad etc 4 Crystals with lower ESR and C requirements are recommended 5 Load capacitor values CLx can be found with formula C CL1xCL2 CL1 CL2 CPCB Or since CL1 and CL2 are typically of equal value CL CLx 2 CPCB CLx CL CPCB x 2 6 DL 0 5 ESR 2m x Fp x CL x V 2 V AVDD_OSC 1 8V 7 If other drive strength settings are used XTAL OUT swing should reach below 200mV tt above 1 3V over all conditions Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 25 of 115 A NVIDIA Table 18 Crystal Interface Signal Routing Requirements Tegra K1 Embedded Platform Design Guide Parameter Requirement Units Note Topology Point to Point Number of loads 1 load
46. vrercal DOS 1 0 DQS 1 0 vss DM 1 0 vssa DO 15 0 l DDR3L 4 CLK CLK_L CS 1 0 A 15 0 BA 2 0 RAS CAS WE CKE 1 0 ODT 1 0 RESET DQS 1 0 DQS 1 0 DM 1 0 DO 15 0 See the Power Decoupling Guidelines section for power rail decoupling and filter requirements for 4x0 1uF 4 7uF 2409 1 2409 1 1 35V 1kQ 1 1kO 1 2x0 1 uF 4 7ul 4x0 1uF 4 7uF 2409 1 2409 1 1 35V 1kKQ 1 1kQ 1 Per DRAM 3 amp 4 Page 27 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA Figure 13 Configuration Option 14 DDR3L 4x16 2 Top 2 Bottom Vertical Placement Example Dev 2 Dev 3 Dev 4 Dev 1 Byte3 amp 1 Byte 4 amp 6 Byte5 amp 7 Byte 2 amp 0 000 000 000 000 c00 c00 000 888 383 889 828 898 288 a99 DDR3L 3 283 333 288 B33 283 333 3 888 Ef 388 S99 388 888 x16 S 888 8 333 299 883 388 o c00 900 000 000 000 ooo o 000 000 000 000 c00 000 3 883 833 888 888 283 888 83 223 SoS 299 888 383 ees 000 000 000 000 000 c00 tole o ooe 000 eL 000 ooe ooe A1 A1 A1 Top View with DRAM on top with Tegra Bottom View DRAM on bottom amp Tegra outline A1 A1 Figure 14 Configuration Option 10 DDR3L 4x16 1x4 Top Inline Placement Example Dev 1 Dev 2 Dev 3 Dev 4 Byte 0 amp 2 Byte 3 amp 1 Byte 6 amp 4 Byte 7 amp 5 000 000 000 000 000 000 000 000 009 009 000 000
47. 0402 Max Distance from AC cap to conn RBR H No requirement RBR and HBR no requirement HB 0 5 in HBR2 less than 0 5 inch AC cap pad voiding RBR H No voiding HBR2 Voiding the plane directly under the pad 3 4 HB required mils larger than the pad size is recommended Voiding required Connector voiding RBR H No voiding HBR2 Standard DP HB required Connector Voiding T tan N Voiding required requirement is stack up dependent For typical stack ups voiding on the layer under the connector pad is recommended to be 5 7mil larger than the connector pad ESD protection device ESD protection required to meet device testing beyond 2kV HMM human metal model direct pin injection test Table 68 eDP Auxiliary Channel Signal Routing Requirements Parameter Requirement Units Note Termination Reference plane Max Same as Main Link breakout Impedance Max trace length Max Vias PCB pair to pair spacing BStripline Microstr 2x 3x dielectric height Max Intra pair within pair Skew Same as Main Link Max Inter pair pair pair Skew No requirement Table 69 LVDS Signal Routing Requirements Parameter Requirement Units Note Max Frequency Bit Rate 135 945 MHz Mbps Number of Loads 1 load Topology Point Point or Multi drop Differential Unidirectional Termination 100 Q At the receiver on die or on board Reference Plane GND
48. 05V supply AVDDIO_PEX P PCle USB PHY Analog Power Rail Connect to 1 05V supply AVDD PEX PLL P PCle USB PHY PLL Power Rail Connect to 1 05V supply HVDD PEX P PCle USB 3 0 High Voltage Power Rail Connect to 3 3V supply HVDD PEX PLL P PCle USB 3 0 PLL High Voltage Power Rail Connect to _E 3 3V supply VDDIO_PEX_CTL P PC le USB Control Block Rail Connect to 3 3V supply Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 46 of 115 a gt Tegra K1 Embedded Platform Design Guide NVIDIA Table 49 USB 3 0 ESD Protection Device Requirements Parameter Requirement Units Note Recommended ESD protection device SEMTECH RClamp0524p Max Reverse Stand Off Voltage Vawm 5 v Any O pin to GND Min Reverse Breakdown Voltage Ver 6 v It 1mA Any I O pin to GND Max Reverse Leakage Current lr 1 uA Vrwm 5V T 25C Any I O pin to GND Max Clamping Voltage Vc 15 V Ipp 1A tp 8 20us Any I O pin to GND Typ Max Junction Capacitance C 0 3 0 4 pF Vpz0V f 1MHz Between I O pins Max Junction Capacitance C 0 8 pF Vr 0V f 1MHz Any I O pin to GND Note The junction capacitance of ESD devices has an effect on signal integrity Choose components with low capacitance with package optimized for high speed links SEMTECH Rclamp0524p has been well verified with its 0 3pF capacitance See detailed characteristics above Table 50 USB 3 0
49. 1 0402 4 7uF 0201 0402 Same Diff NA Decoupling for VDD_RTC is 1 Decoupling for AVDD_OSC is 0 AVDD_OSC has power filter Ferrite Bead 300 100MHz Decoupling for VDDIO_DDR_MCLK VDDIO_DDR together is Decoupling for VDDIO_DDR_HS amp AVDD_PLL_APC2C3 is Decoupling for AVDD_PLL_M is Decoupling for AVDD_PLL_CG amp AVDD_PLL_X together is Decoupling for AVDD_PLL_C4 is Decoupling for AVDD PLL UD2DPD is Decoupling for AVDD PLL EREFE is O O lO O0 O O UU Decoupling for VDDIO HV amp AVDD_HDMI together is Decoupling for AVDD HDMI PLL is Decoupling for AVDD CSI DSI is Decoupling for AVDD USB is Decoupling for AVDD PLL UTMIP is OD O O0 O0 O0 0 O0 0 0 O0O ojo ojojo AVDD_PLL_UTMIP has filter Ferrite Bead 300 100MHz Decoupling for HVDD_PEX_PLL_E amp HVDD_PEX together is Decoupling for AVDDIO PEX DVDDIO PEX amp AVDD_PEX_PLL together is AVDD_PEX_PLL has filter Ferrite Bead 300 100MHz Decoupling for VDDIO_SATA amp AVDD_SATA_PLL together is Decoupling for AVDD SATA PLL has filter Ferrite Bead 300 100MHz Decoupling for HVDD_SATA amp VDDIO_PEX_CTL together is Decoupling for VDDIO_PEX_CTL is Decoupling for AVDD LVDSO IO is Decoupling for AVDD_LVDSO_PLL is o o o o AVDD_LVDS_PLL has filter Ferrite Bead 300 100MHz Decoupling for VDDIO_HSIC is Decoupling for VDDIO_SYS
50. 1 Embedded Platform Design Guide NVIDIA Ball Name Type Termination Description supported GPIO_PBB5 CAM1_PWND Camera 1 Powerdown Connect to Camera 1 powerdown input GPIO_PBB6 CAM2_PWND Camera 1 Powerdown Connect to Camera 2 powerdown input GPIO_PBB7 CAM1_AF_PWND Camera 1 Autofocus Powerdown Connect to Camera 1 Autofocus powerdown input GPIO_PCC1 CAM1_GPIO Camera 1 General Purpose IO Available GPIO for Camera 1 GPIO_PCC2 CAM1_GPIO Camera 2 General Purpose IO Available GPIO for Camera 2 Note Depending on the mechanical design of the platform and camera modules ESD protection may be necessary Any ESD solution must be compatible with the frequency required by the design Table 89 CSI Interface Package Delays Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Delay Delay Delay Delay ps ps ps ps CSI A CLK N AE11 46 CSI A D1 N AE9 61 CSI B DIN AJ9 66 CSI E DO N AF9 57 CSI A CLK P AD11 46 CSI A D1 P AD9 62 CSI B D1 P AH9 67 CSI E DO P AG9 58 CSI A DO N AK9 81 CSI B DO N AK8 78 CSI E CLK N AJ8 67 CSI DSI RDN AG11 61 CSI A DO P AL9 81 CSI B DO P AL8 79 CSI E CLK P AH8 68 CSI DSI RUP AF11 61 Note If additional CSI pins are used from the DSI block the package delays for those can be found at the Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation
51. 1 load Termination VTT amp ODT None Reference plane GND Max PCB breakout length 6 35 mm Via proximity Signal to reference lt 3 8 24 mm ps See note 2 Capacitance Min Input Output Capacitance DQ DM DQS 1 4 pF Max Input Output Capacitance DQ DM DQS 2 1 pF Input Capacitance Delta DQSP amp DQSN Min Max O 0 15 pF Input Capacitance Delta DQ DM DQSP DQSN Min Max 0 5 0 3 pF Impedance Spacing Trace Impedance DQ DM 40 50 option Q 15 Options are for DQS Single Ended 45 50 option 400 450 800Q or DQS Differential 80 90 option 500 500 900 Trace Spacing Microstrip Stripline 3x 2x dielectric Max Via Count Max Number of Vias Tx to Rx Per device Tx to all loads 2 Trace Lengths Delays Max Trace Length Delay PCB Main Trunk 33 34 210 mm ps Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 31 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Parameter Requirement Units Note Skew Matching Max Trace Length Delay Skew from DQS to DQ DM 1 575 Center mm ps 10 Max Trace Length Delay Skew from DQSP amp DQSN 0 32 2 mm ps Max Trace Length Delay Skew from CLK to DQS load to load 25 40 160 mm ps PCB Main Trunk Branch CLK compared withPCB Main Trunk DQS Max Trace Length Delay Skew from DQ to DQ within byte 3 18 Absolute 20 mm ps Max Trace Length Delay S
52. 129 Miscellaneous Description Same Diff NA GEN1_I2C_SCL SDA connect to SCLK SDATA on Thermal Sensor THERMD P N connect to a thermal sensor NCT72 TMP451 1000pf cap between signal pair 1000 series resistors THERM from Temp sensor goes to PMU THERM pin with 100kQ to 2 5V AON RTC ALERT from thermal sensor to Tegra GPIO_PI6 pin with 100kQ to 1 8V_VDDIO JTAG_TMS connects to TMS pin of connector JTAG_TCK connects to TCK pin of connector 100kQ GND JTAG_TDO connects to TDO pin of connector JTAG_TDI connects to TDI pin of connector JTAG_RTCK connects to RTCK pin of connector For normal operation JTAG TRST N is NC or pulled down recommend external 100K pull down For Scan test mode JTAG_TRST_N pulled high 100k0 to VDDIO_SYS or connect to JTAG connector TRST N pin USB Recovery Mode GPIO_PI1 is pulled down to GND through resistor no larger than 2 2KQ when system powers on Normal operation GPIO PI1 is pulled up to VDDIO GMI Boot from secondary device with a 10kQ to 100kQ resistor GPIO_PG 7 4 straps for RAM Code 100kQ or stronger pull ups to VDDIO GMI or pull downs to GND Fewer straps possible if fewer tables required for DRAM Boot Device Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 112 of 115 A NVIDIA Tegra K1 Embedded Platform Design Guide Description Same Diff N
53. 14 2015 NVIDIA Corporation All rights reserved Page 98 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 7 3 PLL Design Guide Specific Checkout List See the Additional PLL Power Noise Coupling Reduction Guidelines portion of the Clocks section which provides tables containing the minimum via distances that need to be met and other related details to be considered Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 99 of 115 A NVIDIA 8 0 Design Guideline Glossary Tegra K1 Embedded Platform Design Guide The Design Guidelines include various terms The descriptions and diagrams in the table below are intended to show what these terms mean and how they should be applied to a design Table 118 Layout Guideline Tutorial Max Breakout Delay z Routing on Component layer Maximum Trace Delay from inner ball to point beyond ball array where normal trace spacing impedance can be met A to B z Routing passes to layer other than Component layer Trace delay from ball to via via delay Beyond this normal trace spacing impedance must be met C to D Max Total Trace Delay a Package route A to B Trace from ball to Device pin B to C a This max length delay must include routing on the PCB where Tegra resides and any other Flex or secondary PCB Delay is from Tegra to the final connector device Cables such as for HDMI or USB are not included Intra Pa
54. 17 53 DDR_CS_BO_N B18 78 DDR_DQ28 A10 82 DDR_DQ58 C27 73 DDR_A_B4 E20 80 DDR_CS_B1_N A19 77 DDR_DQ29 B11 70 DDR_DQ59 A29 86 DDR_A_B5 F17 55 DDR_CSO_N B14 76 DDR_DQ3 C2 Ha DDR DQ6 C3 91 DDR A0 E14 63 DDR CS1 N A12 84 DDR_DQ30 F11 53 DDR_DQ60 C31 97 DDR A1 D14 65 DDR DMO C1 79 DDR DQ31 D11 71 DDR DQ61 A27 82 DDR A10 D18 56 DDR DM1 B9 85 DDR_DQ32 G21 58 DDR_DQ62 C30 86 DDR A11 G17 51 DDR DM2 B6 76 DDR_DQ33 A21 85 DDR DQ63 A28 88 DDR A12 A16 81 DDR DM3 C11 76 DDR_DQ34 E21 55 DDR_DQ7 A5 84 DDR A13 C20 64 DDR DM4 F21 69 DDR_DQ35 F20 63 DDR_DQ8 C9 71 DDR A14 E17 64 DDR DM5 B24 79 DDR_DQ36 G20 56 DDR DQ9 F9 55 DDR A15 E18 55 DDR DM6 F23 67 DDR DQ37 D21 70 DDR_DQSON D5 79 DDR_A2 E15 63 DDR_DM7 B27 76 DDR_DQ38 B21 73 DDR_DQSOP C5 77 DDR A3 E12 57 DDR DQO A3 87 DDR_DQ39 C21 70 DDR_DQS1N H9 63 DDR_A4 D12 66 DDR_DQ1 A4 77 DDR DQ4 B3 78 DDR DQS1P G9 60 DDR A5 F12 59 DDR DQ10 G8 84 DDR DQ40 D24 77 DDR DQS2N D8 71 DDR A6 C12 62 DDR DQ11 F8 71 DDR DQ41 C24 71 DDR_DQS2P C8 69 DDR A7 F14 57 DDR DQ12 E9 65 DDR DQ42 E27 71 DDR_DQS3N G11 64 DDR A8 D15 67 DDR DQ13 A9 84 DDR DQ43 A24 93 DDR_DQS3P H11 66 DDR A9 B12 76 DDR DQ14 D9 59 DDR DQ44 E26 62 DDR DQS4N H20 62 DDR BAO F18 51 DDR DQ15 E8 70 DDR DQ45 B26 79 DDR_DQS4P H21 59 DDR_BA1 D20 65 DDR_DQ16 A8 84 DDR_DQ46 A25 85 DDR_DQS5N D26 76 DDR_BA2 H15 55 DDR DQ17 B8 71 DDR DQ47 A26 g2 DDR_DQS5P C26 75 DDR_CAS_N C14 61 DDR_DQ18 C6 79 DDR_DQ48 A22 83 DDR_DQS6N D23 63 DDR_CKE_BO A20 78 DDR_DQ19 E6 73 DDR_DQ49 E24 63 DDR_DQS6P E23
55. 2 4 f G2 pgs The DDR pin remapping must be followed exactly as shown above z The DDR Devices 1 2 3 4 in the table above correspond to DDR U7B1 U4B1 U4C1 U7C1 respectively on the Jetson TK1 platform Table matches the Jetson TK1 Development Platform Schematics Revision 4 03 or later Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 29 of 115 ee Tegra K1 Embedded Platform Design Guide NVIDIA Table 22 DRAM Pin Multiplexing Option 10 23x23mm DDR3L 4x16 1x4 Top Inline Tegra Tegra Ball DDR3L Net DDR DDR DDR Tegra Tegra Ball DDR3L Net DDR DDR DDR aang ame Name _ Device gaits paliname nas name Name Device ung Bait Name es por D017 or Dae 2 3 po Hig DDR_CLKB DORI CLKP IK IKN 766 por Dar DOR DAMS E5 pra pawe 03 wE De DDR_DQ22 DR_DQI13 DR_DQ23 DR 00112 DR_DQS2P_ DDR_DOSTP D8 Bo il Kr DR DOS2N DDRDOSIN DR_DM2 DR DMT DR D074 DR_DQL25 DDR_RAS_L DR_DQ25 DR_DQ 31 B12 prao pooR Ae Al R8 DR D026 DR D0 25 Ha DR DAZE 2 A13 E11 DDR DQ27 DR_DQ28 DR_DQ29 DR_DQ30 DR_DQ31 DR DOS3P G11 DDR DOS53N DR DM3 DR_DQ32 DR_DQ33 DR_DQ34 DR_DQ35 DR_DQ36 DDR A1 3 NG P2 3 N7 DR_DQ 30 DR_DQ 27 DR_DQ 28 DR D0 24 DR_DQS3P DR_DQS3N DR DM 3 DR D0 34 DR D0 35 DR D0 32 DR D0 38 DR D0 36 DR D0 37 DR D0 33 DR D0 39 DR_DQS4P DR DOS4N DR DM 2 DR D0 53
56. 2 amp 3 Max Inter Pair pair to pair Skew 150 ps See Note 2 amp 3 Note 1 Zz parameters 3 Microstrip routing is recommended for HDMI due to limited eye height and has longer MAX length Include Package amp PCB routing delays for Max trace delays and max trace delay skew If routing to HDMI connector includes a flex or 2 4 PCB the max trace delay amp skew calculations must include all the PCBs flex routing Figure 30 Example HDMI high speed trace amp component layout Tegra Ball Keep connecting trace very short or overlay ESD pad on signal trace Pad 1 ESD Pad 2 Sor HDMI Connector Pad Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 66 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Table 80 Additional HDMI Requirements Recommendations Parameter Requirement Units Note Max signal transition vias 2 Recommend lt 2 for predominately stripline routing amp lt n 4 for predominately microstrip routing Stripline routing Recommend routing near bottom layer to minimize via stub lengths GND transition via lt 1x diff For signals switching reference layers add symmetrical ground pair stitching via near signal vias GND via distance should be lt 1X pitch diff pair via pitch Padstack of signal via 0 45 0 25 0 8
57. 3 PEX AA Ak USBSS TX0P USBSS_TXON USBSS_RXOP 8 3V_LPO USBSS_RXON 2 49KO 1 Note 1 The connections for Tegra USBO VBUS shown above differ from the reference design Instead of USBO_VBUS being tied directly to 3 3V_LPO a buffered version of VBUS from the connector is used This allows SW to detect when a host is connected disconnected Ensure bulk capacitance meets USB 3 0 requirements for Type A connector Any ESD solution must also maintain signal quality amp meet USB requirements See Reference design for details on ID connections If USB Wake w USB DP DN mechanisms is required for connected devices AVDD_USB must be powered in Deep Sleep If USB 3 0 Wake on USB3_TXx RXx Using USB mechanisms is required HVDD_PEX must be powered in Deep Sleep AVDDIO_PEX amp DVDDIO_PEX do not need to be powered amp are recommended to be off in Deep Sleep 6 See the Power Decoupling Guidelines section for power rail decoupling and filter requirements 7 Connector used must be USB IF certified gs KILO Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 42 of 115 A NVIDIA USB 2 0 Design Guidelines Table 41 USB 2 0 Interface Signal Routing Requirements Tegra K1 Embedded Platform Design Guide Parameter Requirement Units Note Max Frequency High Speed Bit Rate UI period Frequend 480 2 083 240 Mbps ns MHz Max Loading High Sp
58. 65 DDR_CKE_B1 B20 78 DDR_DQ2 B5 75 DDR_DQ5 B2 83 DDR_DQS7N B29 87 DDR_CKEO A13 82 DDR DQ20 A7 89 DDR_DQ50 A23 78 DDR_DQS7P B30 85 DDR CKE1 A14 81 DDR DQ21 A6 86 DDR_DQ51 C23 78 DDR ODT BO C18 74 DDR CLK G14 57 DDR DQ22 D6 67 DDR_DQ52 B23 70 DDR ODT B1 A18 77 DDR CLK N H14 59 DDR DQ23 F6 88 DDR DQ53 G23 52 DDR ODTO A15 79 DDR CLKB H18 78 DDR DQ24 G12 57 DDR DQ54 F24 67 DDR ODT1 B15 71 DDR CLKB N G18 80 DDR DQ25 H12 61 DDR_DQ55 H23 83 DDR_RAS_N G15 46 DDR_COMP_P D D17 67 DDR_DQ26 A11 70 DDR_DQ56 D27 74 DDR_RESET_N F15 52 DDR_COMP_P U C17 W DDR_DQ27 E11 57 DDR_DQ57 C29 77 DDR_WE_N C15 65 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 40 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 3 3 2 Component Vias Component vias also called Rat T vias are used to replace T points which are unstable amp tend to move around on the board layout The designer must keep relocating the T points back to the correct location Component vias stay in the location they are placed amp are easier to manage when routing or creating topologies Creating Component Vias A component via is simply a single pin IC symbol For Allegro a component via is created for each via in the library including test points amp via pad stack data is used for the IC pin For Concept schematic capture create one component via symbol amp add a different component via JEDEC ty
59. A GPIO PG 3 0 Boot Select straps if straps used for boot select 100kQ pull up to VDDIO GMI or 100kQ pull down to GND For eMMC selection using straps use setting of 1011 on GPIO PG 3 0 for eMMC x8 BootModeOFF JTAG Access mode GPIO PK7 tt GPIO PJ7 have 100k or stronger resistors to GND even if JTAG not supported GPIO_PIO is pulled to VDDIO GMI with a 100kQ or stronger resistor Any Strapping pins used as GPIOs in design will be in correct strap state when SYS RESET N goes high Additionally GPIO PIO will be high during exiting Deep Sleep Pinmux completed including GPIO usage direction initial state Ext PU PD resistors Deep Sleep state SFIO usage matches reference platform where possible Each SFIO function assigned to only one pin even if function selected in Pinmux registers is not used or pin used as GPIO GPIO usage matches reference platform where possible Any ESD protection devices used on USB 3 0 DSI eDP LVDS HDMI TMDS CSI or SDMMC3 SD Card are suitable for highest frequency modes supported has low capacitive load lt 1pf recommended Any EMI control devices used on USB 3 0 DSI eDP LVDS HDMI TMDS CSI or SDMMC3 SD Card are suitable for highest frequency modes supported has low capacitive load 1pf recommended Table 130 Unused Special Function Interface Pins Checklist Description Same Diff NA Ball Name Termination DD
60. A NVIDIA NVIDIA Tegra K1 Embedded Platform Design Guide Description This document contains recommendations and guidelines for engineers to follow to create a product that is optimized to achieve the best performance from the common interfaces supported by NVIDIA Tegra K1 series processors February 2015 DG 07508 001 Version 03 Notice ALL NVIDIA DESIGN SPECIFICATIONS REFERENCE BOARDS FILES DRAWINGS DIAGNOSTICS LISTS AND OTHER DOCUMENTS TOGETHER AND SEPARATELY MATERIALS ARE BEING PROVIDED AS IS NVIDIA MAKES NO WARRANTIES EXPRESS IMPLIED STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS AND ALL EXPRESS OR IMPLIED CONDITIONS REPRESENTATIONS AND WARRANTIES INCLUDING ANY IMPLIED WARRANTY OR CONDITION OF TITLE MERCHANTABILITY SATISFACTORY QUALITY FITNESS FOR A PARTICULAR PURPOSE AND ON INFRINGEMENT ARE HEREBY EXCLUDED TO THE MAXIMUM EXTENT PERMITTED BY LAW Information furnished is believed to be accurate and reliable However NVIDIA Corporation assumes no responsibility for the consequences of use of such information or for any infringement of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of NVIDIA Corporation Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied NVIDIA Corporation products
61. A Corporation All rights reserved Page 11 of 115 a gt Tegra K1 Embedded Platform Design Guide NVIDIA Table 5 Critical VDD GPU Switcher Components Recommendations Two Power Stages Components MFG MFG Part Qty Parameter Symbol Conditions Value Units PMIC Ctrlr AMS Switching f 1 35 MHz AS3722 1 Frequency 2 phase per Pwr AMS AS3728 2 Max Current 10 A Stage Inductor TDK SPM4015 R68M 4 Inductance L 0 68 uH DC Resistance DCR 32 7 mQ Size LxWxH 4 4x4 1x1 5 mm RMS Current Irms 40C rise 4 7 A Saturation Current Isat 30 drop 8 A Output Taiyo JMK212BJ476MG T 3 per Power Data Sheet C 47 uF Capacitor Yuden Stage Capacitance Size LxW 0805 mm Dielectric X5R Code Rated Voltage Vv 6 3 V Input Taiyo TMK316BJ106KD 4 per Power Data Sheet C 10 uF Capacitor Yuden TD Stage Capacitance Size LxW 1206 mm Dielectric X5R Code Rated Voltage v 25 V Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 12 of 115 D Tegra K1 Embedded Platform Design Guide NVIDIA Table 6 Critical VDD_CORE Switcher Components Recommendations One Power Stage Components MFG MFG Part Qty Parameter Symbol Conditions Value Units PMIC Ctrlr AMS AS3722 1 Switching Frequency f 1 35 MHz 2 phase per Pwr AMS AS3728 1 Max Curre
62. C connections Tegra HSIC 1 2V_GEN_AVDD Note 1 0KO 1 Expansion Connector Powering off on VDDIO_HSIC will require re enumeration of the HSIC interface VDDIO_HSIC must remain powered in Deep Sleep if connected device must maintain connection 5 Series resistors near Tegra are recommended for early builds for use as test points or possible signal conditioning See the Power Decoupling Guidelines section for power rail decoupling and filter requirements HSIC Design Guidelines Table 61 HSIC Interface Signal Routing Requirements Parameter Requirement Units Note Max Frequency High Speed Bit Rate Ul period Fra 480 2 083 240 Mbps ns MHZ Input Buffer Loading 1 5 pF Reference plane GND Max PCB breakout delay 17 ps Trace Impedance 50 Q 15 Via proximity Signal to reference lt 3 8 24 mm ps See Note 1 Trace spacing Microstrip Stripli 4x 3x dielectric Trace Delay Min M 133 667 ps See Note 2 Max Trace Delay Skew between HSIC 2 1 STROBE amp 15 ps See Note 2 DATA Note 1 Up to 4 signal vias can share a single GND return via 2 Include Package amp PCB routing delays for Max trace delays and max trace delay skew parameters Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 54 of 115 A Tegra K1 Embedded Platform Design Guide
63. D DRAM Compensation Pull down See termination requirement VDDIO_DDR P DRAM Interface I O Power Rail Connect to 1 35V supply for DDR3L VDDIO_DDR_MCLK P DRAM Clock I O Power Rail Connect to 1 35V supply for DDR3L VDDIO DDR HS P DRAM Interface High Speed Power Rail Connect to 1 05V supply Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 39 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Table 37 Miscellaneous DDR Connections DDR3L Ball Type Termination Description Name VREF_DQ Resistor Divider with one end to 1 35V DRAM Voltage Reference Data amp Command Address VREF_CA amp other end to GND Recommend one Connect both VREF CA and VREF DQ pins of DRAM each to per DRAM See note under Connection center of voltage divider described in Termination column diagram ZQO ZQ1 2400 1 to GND DRAM Zero Compensation pins Connect each ZQ 1 0 pin to a separate resistor and then to GND as described in Termination column VDD VDDQ DRAM Power Rails Connect to same source as VDDIO_DDR VSS VSSQ DRAM Ground pins Connect to GND Table 38 DRAM Interface Package Delays Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Delay Delay Delay Delay ps ps ps ps DDR_A_B3 H
64. DIA Boot Select can be selected via Fuses instead of straps GPIO_PI1 FORCE RECOVERY strap has internal Pull up 50KQ enabled at boot Pull down resistor must be strong enough to overcome the internal resistor 2 2KO is recommended External Pull up on GPIO_PIO is optional has internal Pull up See the Power Decoupling Guidelines section for power rail decoupling and filter requirements Table 116 Power on Strapping Breakdown Strap Options Strap Pins Description USB_RECOVERY GPIO_PI1 0 USB Recovery Mode 1 Boot from secondary device Reserved GPIO_PIO 0 Not Allowed 1 Normal Operation JTAG_ARM1 GPIO_PK7 00 Serial JTAG chain MPCORE and AVP JTAG_ARMO GPIO_PJ7 01 MPCore only JTAG 10 AVP only JTAG 11 Reserved RAM_CODE 3 0 GPIO_PG 7 4 3 2 Selects secondary boot device configuration set within the BCT 1 0 Selects DRAM configuration set within the BCT BOOT_SELECT_CODE 3 0 GPIO_PG 3 0 Software reads value and determines Boot device to be configured and used 1000 SPI Flash 1011 eMMC x8 BootModeOFF 1111 Use fuse data Others Reserved Nvidia Test Mode TESTMODE EN Tie to GND for normal operation Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 87 of 115 a gt Tegra K1 Embedded Platform Design Guide NVIDIA 4 0 Pads Controls The MPIO pins have output drive amp input related controls that ar
65. DR_CLK DDRO_CLKP 162 J7 ck fm E12 DDRA3 3 DDR A0 4 162 P8 AA D15 DDR A8 DDR_RAS_L Auf J33 Rasi fm B12 DDRA9 DoRA 6 All f R8 fas DDR CKE BO DDR1_CKEO CKEO ES UA aaa aa aa A4 DDRDQ1 DDR DO 22 1 Hs pa G2 D F7 b 1 a DR_DQSON__ DDR_DQS2N_ 1 G3 iDosi a C9 F9 DDRDQ9 DDR DOT 1 c2 poan E9 DDR DQ12 borba 1 f c8 baion DDR_DQ13 DDR_DQ 1 1 B8 Dois lm D9 DDR D014 boR Da 1 f D7 bas E8 DDR DQ15 DDR Daja 1 f C3 pa B9 Dorm borom 1 p3 TUM Note B8 DDRDQI7 DDR_DQ 24 2 E3 bao E6 DDR_DQI9 DDR DO 31 2 F8 pa A7 DDR_DQ20 DDR DO 30 2 G2 bas A6 DDR_DQ21 DDR DO 27 2 Hs bas D6 DDR DQ22 DDR DO 29 2 H3 Da4 D8 DDR_DQS2N__ DDR_DQS3N_ 2 G3 flbost B6 DDR_DM2 DDR DM 3 2 E7 LDM_ H12 DDR DQ25 DDR DO 15 2 c3 pga F11 DDR DQ30 DDR DO 12 2 f c8 baio H11 DDR DOS3P DDR DQsiP 2 C7 fubas 3 Da9 E27 DDR_DQ42 DDR DO 38 3 G2 DQ A26 DDR_DQ47 _ DDR DO 34 3 E3 DQo DDR DQS5P DDR_DQSSN DDR DQ48 DDR DO 62 4 C3 fba DDR_DQ49 DDR_DQ50 DDR_DQ51 DDR DO 60 4 c2 fban DDR_DQ52 DDR_DQ53 DDR_DQ54 DDR DO 61 4 c8 baio DDR_DQ55 D27 DDR_DQ56 DDR DO 45 4 F7 ogi A27 DDR_DQ61 DDR DO 43 4 E3 bao C30 DDR DQ62 DDR DO 4
66. EX GMI VDDIO GMI SYS CLK REQ SYS VDDIO SYS SATA DEV SLP SATA LED ACTIVE SATA DA AUDIO PEX CTL VDDIO AUDIO VDDIO PEX CTL 5 2 Unused Special Function Interfaces See the Unused Special Function Pins section in the Checklist at the end Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved of this document Page 89 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 6 0 PCB Pad Layout Recommendations Pad Size Recommendations Recommended pad etc sizes for two outer rows of pads not including 1 pad in each corner See note amp associated diagram z PAD 0 25mm wide amp 0 35mm tall oval 7 SOLDERMASK 0 30mm wide amp 0 40mm tall oval z PASTEMASK 0 25mm wide amp 0 35mm tall oval Pad Size Soldermask Pastemask Pad Pastemask Soldermask Note Oval pads on outer two rows are outlined in dotted lines in figure below Pad in inner second row Recommended Pad etc Sizes for All Other Pads PAD 0 30mm round a SOLDERMASK 0 35mm round PASTEMASK 0 30mm rount Pad Size Soldermask Pastemask gt 030mm 035mm e gt 030mm lt lt Pastemask Soldermask Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 90 of 115 A Tegra K1 Embedded Platform NVIDIA 6 1 PCB Stack up Figure 42 Design Stack up Desired overall thickness with Soldermask 1 564 MM of Layers 6 Special Ma
67. F29 63 SDMMC4 DAT3 H31 71 SDMMC4 DAT6 E29 71 SDMMC4 COMP PU H30 75 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 75 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 3 7 2 SD Card Connections The Figure shows a standard Micro SD socket An SD Card should use SDMMC3 which includes a loopback clock feature to improve read timing The internal Pull up resistors on the SDMMC Data CMD lines are strong see Tegra K1 Data Sheet for values so external pull ups are not required Figure 34 Jetson TK1 SD Card Connections VDDIO SDMMC3 Tegra SD Card SD Connector omma a ___________ gt eK SOME MD IB omme Dao eao 33 20 1 SDMMC31COMPIPU AMW G VDDIO SDMMC3 33 20 1 ISDMMC3COMP PD AW 4 3 3_sp_cARDb _ DDE SYS connector closely matching flight path of SDMMC CLK plus average of DAT 3 0 L wos sommca_co_n sab Note VDDIO_1V8 If EMI devices are used they must be tuned so the signals meet the timing amp electrical requirements of the SD specification for the modes supported If included the filter should be near the Tegra processor 5 See the Power Decoupling Guidelines section for power rail decoupling and filter requirements 5 Any supply used to power the SD Card must be current limited if the supply is shorted to GND Table 96 SDMMC 3 1 Interface Signal Routin
68. FCLKN P Connect to GND not used PEX_TESTCLKN P Leave NC not used PEX_TERMP Leave NC if neither USB 3 0 interface used DVDDIO_PEX AVDDIO_PEX AVDD_PEX_PLL HVDD_PEX HVDD_PEX_PLL_E SATA_LO_TXN P Connect to GND if USB 3 0 amp PCle interfaces are not used Leave NC if not used SATA_LO_RXN P Connect to GND any unused RX lines or leave NC if SATA interface not used SATA_TESTCLKN P Leave NC not used VDDIO_SATA AVDD_SATA_PLL HVDD_SATA HSIC 2 1 _DATA Connect to GND if SATA interface not used Leave NC if HSIC interface not used HSIC 2 1 STROBE Leave NC if HSIC interface not used HSIC REXT Leave NC if HSIC interface not used VDDIO_HSIC DSI A CLK N P DSI_A_D 3 0 N P DSI B D 3 0 N P Leave NC or connect to GND if HSIC interface not used Leave NC any unused DSI A or B Data Lanes or entire interface if neither DSI A tt B used CSI_A_CLK_N P CSI A D 1 0 N P CSI B D 1 0 N P Leave NC any unused CSI A or B Data Lanes or entire interface if neither CSI A tt B used CSI E CLK N P CSI E DON P Leave NC CSI E if not used CSI_DSI_RDN CSI DSI RUP Leave NC if neither DSI or CSI is used AVDD_CSI_DSI LVDSO_TXD 4 0 _P N Leave NC if neither DSI or CSI is used Leave NC any eDP or LVDS lanes not used LVDSO_RSET Leave NC if eDP LVDS interface not used AVDD_LVDSO_IO AVDD_LVDSO_PLL Leave NC or connect to GND if eDP LVDS inter
69. Guidelines section for power rail decoupling and filter requirements Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 51 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Table 56 SATA Signal Routing Requirements Parameter Requirement Units Note Max Frequency Bit Rate 3 0 333 3 Gbps ps 1 5GHz Topology Point to point unidirectional differential Configuration Device Organization 1 load Max Load per pin 0 5 pf Termination 100 Q On die termination Reference plane GND Breakout Region Impedance Trace Width Line separati g mils Trace Impedance Differential Pair Single End o Q 15 Pair to Pair Trace Spacing Stripline Microst 3x 3x Dielectric Max Trace Delay 1360 8 ps in See Note 1 amp 2 Max Intra Pair Trace Delay Skew 1 ps See Note 1 amp 2 Keep critical PCle SATA related traces such as PCle SATA_TX RX PCle SATA_TERMP etc away from other signal traces or unrelated power traces areas or power supply components Note 1 If routing to SATA device or SATA connector includes a flex or 2 PCB the total routing including all PCBs flexes must be used for the max trace amp skew calculations 2 Include Package amp PCB routing delays for Max trace delays and max trace delay skew parameters Table 57 SATA_TERMP Routing Requirements Parameter Requirement Units Note Reference plane
70. H Plated Through hole Vias Keep GND via as close as possible Ground sliver between BGA pads Remove ground slivers between BGA pads amp feedthrus to via to reduce the capacitive loading of BGA pad DC Blocking capacitor location Place DC blocking capacitors on Tegra TX lines within 0 3 of the connector if one exists For direct Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 49 of 115 A NVIDIA Tegra K1 Embedded Platform Design Guide Device connection place DC blocking capacitors on all lines Recommendation is for capacitors to be located near TX for both Tegra amp Device Alternatively capacitors can be located at either end but should be near either Tegra or Device Ground plane under AC cap pads Remove GND plane under AC blocking capacitor pads If board has ICT pads remove plane under those as well Void is size of pad ring equal to dielectric thickness Serpentine line rule 7 Avoid tight bends No 90deg bends impact to loss and jitter budgets S Keep angles gt 135deg a 7 maintain adequate air gap gt A gt 4x trace width Lengths of B C gt 1 5x trace width w Serpetines length is at least 3w for jog E v o Keep critical PCle SATA related traces such as PCle SATA TX RX PCle SATA TERMP etc away from other signal traces or unrelated power traces areas or power supply components
71. I RDN CSI DSI RUP amp AVDD CSI DSI connections can be found in Display DSI section If Tegra GPIO used for flash control one of the GPIO_PBBx pins are used Appropriate power filtering decoupling provided for camera supplies Privacy LED included in design if required by OS provider amp powers on when camera is operating not controlled by SW Table 127 Audio Checklist Description Same Diff NA Tegra I2C_SCL amp SDA connect to Codec SCL amp SDA pins amp pull up resistors to voltage level of Tegra block I2C pins reside DAP1 pins used for Primary Modem I F if required DAP2 pins used for Codec DAP3 pins used for 2nd 125 I F on Primary Modem if required DAP4 pins used for Bluetooth if required DAP 4 1 _SCLK connects to SCLK pin of audio device see Pins_EMI_ESD section for related checks DAP 4 1 FS connects to WS 125 or FS SYNC PCM pin of audio device DAP 4 1 _DOUT connects to Data Input pin of audio device SPDIF_IN connects to TOSLINK optical or other 1 8V 3 3V compatible source SPDIF_OUT connects to RCA or TOSLINK optical Connector If RCA connector series 100nF capacitor series 2650 resistor 2200 pulldown resistor tt 100pF capacitor to GND required in path Table 128 12C SPI UART Checklist Description I2C devices on same 12C IF do not have address conflicts ensure comparisons are done 7 bit to 7 bit format or 8 bit to 8 bit format Same Diff NA
72. IF certified Single lane PCle interfaces are be located at Lane 2 PEX_TX TX2N P Cont 1 amp or Lane 4 PEX_TX TX4N P Cont 0 Dual Lane PCle interface are be located at Lanes 4 3 PEX_TX TX 4 3 N P Cont 0 Quad Lane PCle interface are be located at Lanes 4 1 PEX_TX TX 4 1 N P Cont 0 PCle controller 0 is associated with PEX_CLK1P N PEX_LO_CLKREQ_N amp PEX_LO_RST_N PCle controller 1 is associated with PEX_CLK2P N PEX_L1_CLKREQ_N amp PEX_L1_RST_N PCle TX lanes PEX_USB3_TXOP N PEX_TX 4 2 P N connect to TX_P pins of PCle device connector through 0 1uF caps Connector case PCle RX lanes PEX_USB3_RXOP N PEX_RX 4 2 P N connect to RX_P pins of PCle connector Direct Device case PCle RX lanes PEX_USB3_RXOP N PEX_RX 4 2 P N connect to RX_P pins of PCle device through 0 1uF caps PEX_L 1 0 _CLKREQ_N connects to CLKREQ pins on device connector s PEX_L 1 0 _RST_N connect to PERST pins on device connector s PEX_WAKE_N connects to WAKE pins on device or connector w 100KQ pullup to 3 3V_LPO supply Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 107 of 115 Design Guide A Tegra K1 Embedded Platform NVIDIA Description Same Diff NA PEX_TERMP connects to GND through 2 49KQ 1 termination resistor to GND PEX_REFCLKP N are Unused amp connected to GND PEX_TSTCLKP N are unused amp left
73. IP VDDIO_SYS SYS2 AUDIO UART SDMMC1 SDMMC4 VDDIO_CAM BB GMI 1 8 ON ON ON 1 2 VDDIO_DDR 1 35 OFF ON ON 3 AVDD_PLL_x VDDIO_DDR_HS 1 05 ON ON OFF AVDD_HDMI_PLL DVDDIO_PEX AVDDIO_PEX AVDD_PEX_PLL VDDIO_SATA AVDD_SATA_PLL 1 05 OFF OFF OFF 4 5 AVDD_CSI_DSI VDDIO_HSIC 1 2 OFF OFF On 6 AVDD_HDMI 3 3 OFF OFF OFF 7 AVDD_USB HVDD_PEX HVDD_PEX_PLL_E VDDIO_HV VDDIO_PEX_CTL 3 3 See Note See Note See Note 4 5 1 8 2 8 VDDIO_SDMMC3 3 3 OFF OFF OFF VPP_FUSE 1 8 OFF OFF OFF 3 8 Note Rail must be on in Deep Sleep if any of the Wake capable pins on these blocks are used for wake VDDIO_AUDIO UART SDMMC1 SDMMC4 BB are typically combined with other 1 8V rails such as AVDD_OSC amp VDDIO_SYS SYS2 so would be ON in all three modes shown If they come from a separate supply they are not required to be on unless any pins are used for wake or pulled driven high in Deep Sleep mode Do not power until SYS_RESET_N is asserted amp VDD_RTC VDD_CORE have reached their nominal level Violating this constraint may permanently damage Tegra AVDD_USB Required for Boot for Force Recovery Mode If USB 2 0 Wake Using USB mechanisms is required AVDD_USB must be powered If USB 3 0 Wake on USB3_TXx RXx Using USB mechanisms is required for connected USB 3 0 devices HVDD_PEX must be powered in Deep Sleep AVDDIO_PEX amp AVDD_PEX_PLL do not need to be powered amp are recommended to be off in Deep Sleep VDDIO_HSIC must be
74. Inner Layer Main Power Routing aa Na oldie dy a d4 VDD_CORE supply decoupling capacitors just 7 below the Tegra power balls VDD_CPU supply decoupling capacitors just below the VDD_GPU supply decoupling Tegra power balls capacitors just below the Tegra power balls Note Decoupling capacitors located on the bottom of the PCB just below the power balls they are associated with Figure 6 DRAM Decoupling Capacitor Placement DDR Power decoupling capacitors placed next to package near DRAM power balls Zee Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 16 of 115 o Tegra K1 Embedded Platform Design Guide NVIDIA 2 5 Remote Power Sense Guidelines Tegra processors support remote power sense functionality for the VDD CPU VDD CORE amp VDD GPU rails For each of the rails there is a positive SENSE amp negative SENSE line VDD CPU SENSE amp GND CPU SENSE VDD CORE SENSE amp GND CORE SENSE VDD GPU SENSE amp GND GPU SENSE The SENSE balls are routed on the Tegra package die to power rail locations near each load amp to provide feedback to the PMU Regulators so they can adjust to any voltage variances The SENSE balls are routed on the Tegra package die to GND locations near each load General Guidelines Keep Sense lines away from noisy components such as power inductors and noisy signal traces Do not ro
75. L Includes AVDD_LVDSO_PLL Includes AVDDIO_PEX AVDD_PEX_PLL DVDDIO_PEX source for FETs to AVDD_HDMI_PLL 1 Uk 3 AMS 3722 PMU OTP version 09 required 4 5 Includes AVDD_OSC AVDD_PLL_UTMIP VDDIO_SYS VDDIO_SYS2 VDDIO BB VDDIO_SDMMC1 VDDIO_SDMMC4 VDDIO_AUDIO VDDIO_UART VDDIO_CAM amp VDDIO GMI 6 Includes AVDD_PLL_UD2DPD AVDD PLL C4 AVDD_PLL_CG AVDD PLL X AVDD PLL APC2C3 AVDD LVDSO O AVDD PLL X AVDD PLL EREFE 7 The supply for AVDD HDMI PLL must have a discharge circuit The PMU Switchers have this feature but since an external load switch is used ensure it has a discharge circuit 8 Initial designs should include series 00 resistor between VPP FUSE supply amp Tegra to allow current measurements during Fuse Audit Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 9 of 115 Tegra K1 Embedded Platform Design Guide A NVIDIA 2 2 CPU GPU CORE amp DDR Supply Considerations The total power solution for the CPU GPU CORE amp DDR supplies must meet the requirements listed in the Tegra K1 Data Sheet including Voltage steps required by DVFS software Maximum EDP current Minimum voltage ramp rates In addition in order to meet the full EDP max current care must be taken in selecting the critical components that make up each supply circuit These components including the PMU switcher or external regulators must meet the current requirements an
76. MU LDO 6 PMU LDO 11 F1 2V GEN AVDD 1 8V RUN VPP FUSE 1 8V_VDDIO 3 3V_LPO 3 3V_RUN 3 3V_RUN 3 3V_AVDD_HDMI_AP_GATED Backdrive Circuit Load Switch Load Switch 5V_USB_HS USB 3 0 Type A PEE USB 2 0 Micro AB D 3 3V_LPO PMU LDO 4 2 8V_RUN_CAM PMU LDO 7 PMU LDO 10 PMU LDO 1 PMU LDO 5 1 05V_RUN_CAM_REAR Camera s 2 8V_RUN_CAM_AF 1 8V_RUN_CAM 1 2V_RUN_CAM_FRONT 1 2V_GEN_AVDD PMU LDO 2 HSIC 1 8V_VDDIO 3 3V_RUN eMMC 45V SYS 1 8V_VDDIO 3 3V_RUN_TOUCH Display Touch 3 3V_SYS PMU LDO 9 1 8V_VDDIO SPI ROM p H 8V VDDIO AUDIO s Load Switch AA A HDMI Load Switch ar SD Card k DO 4VDD_1V5_MPCIE x T 3 3V_LPO Mini PCle Half Socket sar Gbit LAN SAPA TEMP SENSOR J Lane Load Switch SATA Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 7 of 115 A NVIDIA Tegra K1 Embedded Platform Design Guide The table below shows the allocation of supplies used in the Jetson TK1 platform design amp available for use in Embedded designs Table 2 Power Supply Allocation Power Rails Usage V Power Supply or Source Enable Time Note Gate ms
77. NC DVDDIO_PEX AVDDIO_PEX amp AVDD_PEX_PLL connect to 1 05V_RUN supply HVDD_PEX amp HVDD_PEX_PLL_E amp VDDIO_PEX_CTL Connect to 3 3V_LPO supply SATA_LO_TXP N connect to TX_P pins of SATA device connector through 0 1uF caps Connector case SATA_LO_RXP N pins connect to RX_P pins of SATA connector Direct Device case SATA_LO_RXP N pins connect to RX_P N pins of SATA device through 0 1uF caps SATA_TERMP connects to GND through 2 49KQ 1 termination resistor to GND SATA_TSTCLKP N are unused amp left NC VDDIO_SATA amp AVDD_SATA_PLL connect to 1 05V_RUN supply HVDD_SATA connects to 3 3V LPO supply HSIC 2 1 _STROBEs connect to STROBE pin on HSIC device s HSIC 2 1 _DATA connect to DATA pin on HSIC device s Series resistor pads placed near Tegra on STROBE DATA highly recommended for early designs in case signal tuning required HSIC_REXT connects through 1 0kQ 1 resistor to GND VDDIO_HSIC connects to 1 2V supply Table 124 SDMMC Checklist Description SDMMC4_CLK connects to CLK pin of eMMC device See Pins_EMI_ESD section for related checks Same Diff NA SDMMC4_CMD connects to CMD pin of eMMC device External 4 7KQ pull up resistor to the 1 8V rail used for VDDIO_SDMMC4 SDMMC4_DAT 7 0 connect to DAT pins of eMMC device No external pull ups required SDMMC4_COMP_PU connect to 49 90 1 to 1 8V same supply as VDDIO_SDMMC4
78. Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Delay Delay Delay Delay ps ps ps ps DAP1_DIN H28 66 DAP2_DIN L30 69 DAP3_DIN AF17 56 DAP4 DIN P3 66 DAP1_DOUT L28 58 DAP2_DOUT J29 61 DAP3_DOUT AE17 53 DAP4_DOUT P5 61 DAP1 FS J28 59 DAP2_FS R30 78 DAP3_FS AE15 55 DAP4 FS P1 72 DAP1_SCLK P31 82 DAP2_SCLK M29 64 DAP3_SCLK AJ17 66 DAP4 SCLK N1 71 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 79 of 115 a gt Tegra K1 Embedded Platform Design Guide NVIDIA 3 9 12C Tegra has six I2C controllers PWR_I2C I2C1 GEN1 12C I2C2 GEN2 12C I2C3 CAM_I2C I2C4 DDC tt I2C6 eDP option The following assignments should be used for the I2C interfaces 12C Pins Function Controller 1 O Block Use GEN1_I2C 12C1 UART General use Codec Sensors etc GEN2 12C 12C2 GMI Touch Screen Battery Pack CAM I12C 12C3 CAM Cameras tt camera related functions AF etc DDC 12C4 HV HDMI PWR_I2C 12C5 SYS PMU Ext CPU Regulator if required See PWR 12C Usage Restrictions section 12C6 on DP AUX CHO P N pins HV eDP 12C6 can only operate with VDDIO HV at 2 8 3 3V 12C Design Guidelines Care must be taken to ensure I2C peripherals on same I2C bus connected to Tegra do not have duplicate addresses Addresses can be in two forms 7 bit with th
79. R_CS1 DDR_CS_B1 DDR_CKE1 DDR_CKE B1 DDR_ODT1 DDR_ODT_B1 Leave NC if only single Rank is implemented ODT1 may not be required even for dual rank devices If not used leave NC Note that in this case this is the signal function after the DDR pin remapping not the actual ball name DDR_CAS_N DDR_RAS_N DDR_WE_N DDR_RESET_N DDR_BA 2 0 DDR_A 15 10 USBO_DP N These functions are not used with LPDDR3 DRAM but many are remapped to support the 2 Address Command channel See LPDDR3 DDR pin remapping table Required for all designs for Recovery Mode USB 2 1 _DP N Leave NC if USB1 or USB2 not used USBO_ID Leave NC if not used USBO_VBUS Required for all designs for Recovery Mode USB_REXT Required for all designs for Recovery Mode AVDD_USB AVDD_PLL_UTMIP USB3_TX 1 0 _P N Required for all designs for Recovery Mode Leave NC any unused TX lines USB3_RX 1 0 _P N Connect to GND any unused RX lines or leave NC if no USB PCle Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 113 of 115 A NVIDIA Tegra K1 Embedded Platform Design Guide Description Same Diff NA Ball Name Termination interfaces used PEX_TX 4 2 N P Leave NC if not used PEX_RX 4 2 N P Connect to GND any unused RX lines or leave NC if no USB PCle interfaces used PEX_CLK 2 1 N P Leave NC if not used PEX_RE
80. Reference plane GND Including Crystal itself Breakout Region Max Delay Min width spacing Trace Impedance Different 90 Q 20 See Note 1 Single end 55 Trace Spacing to other nets Microst 3x dielectric Include keep out area around Stripli 2x crystal itself Max Trace Delay 400 ps Max Trace Intra pair XTAL_OUT to XTAL_IN Skew 6 microstrip ps 7 stripline Note Keep XTAL_IN OUT traces away from other signal traces or unrelated power traces areas or power supply components Use proper GND isolation around and above below these sensitive signals Max Trace Delay amp Max Trace Delay Skew matching must include substrate pin delays unless otherwise specified Routing as differential pair provides better noise immunity Table 19 XTAL_IN OUT Signal Connections Ball Name Type Termination Description XTAL_IN A Load capacitors from XTAL_IN amp XTAL_OUT to GND Crystal Input and Output Connect toa XTAL_OUT Typically 12pF but depends on PCB loading amp Crystal 12MHz Crystal Specs Table 20 Crystal Interface Package Delays Signal Name Ball Package Delay ps XTAL_IN E3 72 XTAL_OUT E4 70 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 26 of 115 A NVIDIA 3 3 DRAM Tegra K1 Embedded Platform Design Guide Tegra supports the remapping of the Address Command Control pins i
81. SDMMC4_COMP_PD connects to 49 90 1 to GND PMU Reset output connected to eMMC Reset SDMMC1_CLK connects to CLK pin of device SDMMC1_CMD connects to CMD pin of device No external pull ups required SDMMC1_DAT 3 0 connect to DAT pins of device No external pull ups required SDMMC1_COMP_PU connect to 33 20 1 to same supply as VDDIO_SDMMC1 SDMMC1_COMP_PD connects to 33 20 1 to GND Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 108 of 115 Design Guide A Tegra K1 Embedded Platform NVIDIA Description SDMMC2_CLK connect to CLK pin of device See Pins_EMI_ESD section for related checks Same Diff NA SDMMC2_CMD connect to CMD pin of device External Pull ups as required by peripheral SDMMC2_DAT 7 0 connect to DAT pins of device External Pull ups as required by peripheral SDMMC2_COMP_PU connect to 33 20 1 to 1 8V same supply as VDDIO GMI SDMMC2_COMP_PD connects to 33 20 1 to GND SDMMC3_CLK connects to CLK pin of socket See Pins_EMI_ESD section for related checks SDMMC3_CMD connecst to CMD pin of socket No external pull ups required SDMMC3_DAT 3 0 connect to DAT pins of socket No external pull ups required SDMMC3_COMP_PU connect to 33 20 1 to same supply as VDDIO SDMMC3 SDMMC3_COMP_PD connects to 33 20 1 to GND SDMMC3 Loopback Clock Out In is routed as a loop out from SDMMC3
82. Supply Connect to USB2_VBUS_SW VBUS supply for Micro AB connector through load switch USBO_ID A 1000 series resistor 100kQ pull up USB Identification Connect to USB Micro AB ID pin Also to 5V_SYS amp ESD Protection near connect ID pin from connector to PMU PWM_CLK2 pin connector through FETs See reference design for details USB_REXT A 1KQ 1 to GND see Note External Reference Connect through resistor to GND AVDD_USB P USB PHY Power Rail Connect to 3 3V LPO supply AVDD PLL UTMIP P 300 100MHz ferrite bead to 1 8V USB PHY PLL Power Rail Connect to 1 8V_VDDIO_LPO_OFF supply through filter Table 47 USB 2 0 Interface Package Delays Signal Name Ball Pkg Delay ps Signal Name Ball Pkg Delay ps USBO_DN AH20 80 USB2_DN AE20 64 USBO_DP AJ20 80 USB2_DP AD20 63 USB1_DN AF20 74 USB_REXT AL19 76 USB1_DP AG20 74 Table 48 USB 3 0 Signal Connections Ball Name Type Termination Description USB3_TXON P DIFF Series 0 1uF caps close to connector USB 3 0 Differential Transmit Data Pair Connect to USB 1 O ESD Protection between cap tt conn to 3 0 connector GND USB3_RXON P DIFF ESD Protection between cap amp conn to USB 3 0 Differential Receive Data Pairs Connect to USB I O GND 3 0 connector PEX_TERMP A 2 49KO 1 to GND PCle USB3 Calibration Connect through resistor to GND DVDDIO_PEX P PCle USB PHY Digital Power Rail Connect to 1
83. T m Available for additional lanes for a x8 DSI interface as a 2 x4 DSI interface or for an additional CSI x4 interface oso ojpor nye 4530 196 1 2V RUN AVDD VDDIO 1V8 VDDIO 1V8 Note Filters on the DSI signals are not recommended If EMI is a concern other solutions such as using PCB GND layers or other shielding is preferred If EMI devices are necessary they must be tuned to minimize the impact to signal quality which must meet the timing amp Vil Vih requirements at the receiver amp not introduce glitches on the signal edges Any ESD solution must also maintain signal quality and meet requirements for the frequencies supported by the design See the Power Decoupling Guidelines section for power rail decoupling and filter requirements Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 62 of 115 A NVIDIA MIPI DSI and CSI Design Guidelines Table 75 MIPI DSI amp CSI Interface Signal Routing Requirements Tegra K1 Embedded Platform Design Guide Parameter Requirement Units Note Max Frequency Data Rate per data lane 750 1500 MHz Mbps Number of Loads Max Loading per pin 1 10 Load pf Reference plane GND or PWR See Note 1 Breakout Region Impedance Diff pair Single End 90 45 55 Q 15 Max PCB breakout delay 48 ps Trace Impedance Diff pair Single End 90 45 55 Q Via pr
84. Termination see note on ESD Description HDMI_TXCN P O HDMI Differential Clock Connect to CN CP pins on HDMI Connector HDMI_TXD 2 0 N O HDMI Differential Data Connect to D 2 0 pins HDMI P Connector HDMI_INT l Series 1KQ resistor HDMI Interrupt Hot Plug Detect Connect to HP_DET on HDMI Connector w termination described HDMI_CEC 1 OD See reference schematics for details HDMI Consumer Electronics Control Connect to CEC on HDMI Connector through circuitry shown in connection Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 67 of 115 a gt Tegra K1 Embedded Platform Design Guide NVIDIA Ball Name Type Termination see note on ESD Description example HDMI_RSET A 1KO 1 to GND HDMI Current Reference Connect to resistor to GND AVDD_HDMI P Dual FET back drive blocking HDMI I O Power Rail Connect to 3 3V supply gated by circuitry See HDMI Connection AVDD HDMI PLL see note under connection figure Example diagram AVDD_HDMI_PLL P HDMI PLL Power Rail Connect to 1 05V lt 165MHz or 1 2V gt 165MHz supply through FET load switch enabled by GPIO_PH7 DDC_SCL SDA 1 OD 1200 100mhz bead amp 1 8KQ pull up DDC Interface Clock and Data Connect to SCL SDA on resistor to 5V_HDMI supply each HDMI Connector w termination described VDDIO_HV P High Voltage Tolerant I O Power Rail Connect to 3 3V_LPO supply
85. Trace Impedance Diff pair Single Endg 90 45 55 Q 15 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 59 of 115 a gt Tegra K1 Embedded Platform Design Guide NVIDIA Parameter Requirement Units Note Max Trace Length Stripline Microstr 10 12 in See Note 1 PCB pair to pair spacing Stripline Microstr 3x 4x dielectric 3x of the thinner of above and below height Max Intra pair within pair Skew 5 ps See Note 1 Max Inter pair pair pair Skew 100 ps See Note 1 Note Include Package amp PCB routing delays for Max trace delays and max trace delay skew parameters Table 70 LVDS Multi drop Signal Routing Requirements Parameter Requirement Units Note Stub length lt 15 of rise time External termination resistor 100 Q Placed at the far end last receiver On chip termination receiver 90 lt ZL lt 132 Q Total load Table 71 LVDSO_RSET Routing Requirements Parameter Requirement Units Note Reference plane GND if possible See note 1 Trace Impedance 50 Q 15 Max Trace Delay 40 ps Include only PCB routing delay Note If stack up makes GND reference difficult keep routing distance very short amp have GND areas next to LVDSO_RSET trace Common eDP LVDS Routing Guidelines Guideline If routing to eDP or LVDS device includes a flex or 2 PCB the max trace amp skew ca
86. USB3 or PCle Parameter Requirement Units Note Reference plane GND if possible See note 1 Trace Impedance 50 Q 15 Max Trace Delay 75 ps Include only PCB routing delay Note 1 If GND reference is not feasible keep the routing distance as short as possible amp have GND areas traces next to the PEX_TERMP traces 2 Use reference platform layout as a guideline for routing amp location of PEX_TERMP resistor 3 Avoid routing signal traces directly below and in parallel with these critical rails Common USB Routing Guidelines Guideline If routing to USB device or USB connector includes a flex or 2 PCB the total routing including all PCBs flexes must be used for the max trace amp skew calculations Keep critical USB related traces such as USB3_TX RX USB_REXT amp PEX_TERMP etc away from other signal traces or unrelated power traces areas or power supply components Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 45 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Table 46 USB 2 0 Signal Connections Ball Name Type Termination Description USB 2 0 _DP DIFF 900 common mode chokes close to USB Differential Data Pair Connect to USB Micro AB USB 2 0 _DN I O connector ESD Protection between connector D D pins choke amp connector on each line to GND USBO_VBUS A USB Bus 5V
87. VDD_MUX Main power Supplies PMU 12 na Power Jack na amp various external supplies 5V_SYS Main 5V supply 5 0 TPS51220 Switcher VDD_MUX PMU EN5V O 3 3V_SYS Main 3 3V supply 3 3 TPS51220 Switcher VDD_MUX PMU 0 GPI02 3 3V_LPO Gated 3 3V supply On in 3 3 SLG5NV 1430V 3 3V_SYS REGEN1 7 1 D Sleep Gate 3 3V_RUN Gated 3 3V supply Off in 3 3 SLG5NV 1430V 3 3V_SYS REGEN3 10 2 D Sleep Gate VDD_CORE Tegra VDD_CORE rail Var AS3728 PWR Stage 5V_SYS PMU GPIO 2 SD1 x1 VDD_CPU Tegra main CPU complex Var AS3728 PWR Stage 5V_SYS PMU GPIO Off SDO x2 VDD_GPU Tegra GPU Var AS3728 PWR Stage 5V_SYS PMU GPIO Off SD6 x2 1 35V_LPO DDR3L rails Tegra amp DDR 1 35 PMU Switcher 5V_SYS Pwr on 8 3 SD2 3 Seq 1 05 RUN HDMI amp PEX USB 1 05 rails 1 05 PMU Switcher SD4 5V_SYS 12C PMU Off 4 7 1 8V VDDIO Main 1 8V supply 1 8 PMU Switcher SD5 5V_SYS Pwr on 7 5 Seq 1 05_RUN_AVDD Tegra 1 05V PLLs amp LVDS 1 0 1 05 PMU LDO O 1 35V_LPO Pwr on 9 6 rails Seq 1 8V RUN CAM Camera 1 8V rail 1 8 PMU LDO 1 3 3V RUN 12C PMU Off 1 2V GEN AVDD Tegra AVDD_DSI_CSI 1 2 PMU LDO 2 1 8V_VDDIO 12C PMU Off 7 VDDIO_HSIC 1 05V LPO VDD RT Tegra VDD RTC Var PMU LDO 3 1 35V_LPO Pwr on 1 C VDD CORE or Seq 3 3V_SYS 2 8V RUN CAM High voltage Camera rail s 2 8 PMU LDO 4 3 3V_SYS 12C PMU Off 1 2V RUN CAM FRO Front Camera 1 2V rail 1 2 PMU LDO 5 1 8V_VDDIO 12C PMU Off NT VDDIO_SDMMC3 Tegra SD Card rail 1 8 3 PMU
88. _CLK_LB_OUT amp back to SDMMC_CLK_LB_IN SD Card Detect Connect SDMMC3_CD to CD pin on socket SD Card Write Protect Full size SD socket Connect to KB_COL4 Adequate bypass caps provided on SD Card VDD rail matches reference design Table 125 Display Checklis Description DSI A CLK N P Clock connects to CLKn tt CLKp pins of DSI receiver Same Diff NA DSI A D 3 0 N P Data Lanes connects to up to 4 sets of Dn amp Dp pins of DSI receiver DSI B CLK N P Clock connects to CLKn tt CLKp pins of upper half of 8 lane primary DSI receiver or to 2nd receiver See Note DSI B D 3 0 N P Data Lanes connect to upper half of 8 lane primary receiver or up to 4 lanes of 2nd receiver See Note CSI_DSI_RDN connects to 49 90 1 resistor to GND CSI DSI RUP connects to 4530 1 resistor to AVDD_DSI_CSI 1 2V AVDD_CSI_DSI connects to 1 2V supply KB_ROW6 used for TE Tearing Effect signal from display if supported LVDS_TXDO_N P connect to Lane 2 of eDP panel connector through 0 1uF AC capacitors LVDS_TXD1_N P connect to Lane 1 of eDP panel connector through 0 1uF AC capacitors LVDS_TXD2_N P connect to Lane 0 of eDP panel connector through 0 1uF AC capacitors LVDS_TXD4_N P connect to Lane 3 of eDP panel connector through 0 1uF AC capacitors DP AUX CHO N P connect to Aux Lane of eDP panel connector through 0 1uF AC capacitors Tegra K1 DG 07508 001v03 Copy
89. al A nd Layer ap Reference 4 gt Trace jt Layer Spacing Microstrip Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 100 of 115 A NVIDIA Tegra K1 Embedded Platform Design Guide Dielectric height Ref Layer 1 Dielectric height x Ref Layer 2 gt Trace iq Spacing Reference Layer 1 Signal Layer Signal Layer Reference Layer 2 p Trace Height Stripline i i i Pair to Pair Pair to pair spacing gt Pace E z Spacing between differential traces DN Signal Layer Dielectric Heighi Ground Reference Layer Differential Pairs Breakout spacing 5 Possible exception to board trace spacing above is shown in figure to right where different spacing rules are allowed under Tegra in order to escape from Ball array 7 This includes spacing between adjacent traces amp between traces vias or pads under the device in order to escape ball matrix Outside device boundary normal spacing rules apply Min Breakout Spacing O O OO gt Min Breakout Spacing Reference Return Ground Reference Return Via amp Via proximity signal to reference Signals changing layers amp reference GND planes need similar return current path Accomplished by adding via tying both GND layers together Via proximity sig to ref is distance between signal amp reference return vias Signa
90. and GPIO usage should match those used on Jetson TK1 or alternative Use case options shown in the Jetson TK1 Pinmux spreadsheet Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 21 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Routing Guideline Format The routing guidelines have the following format to specify how a signal should be routed Breakout traces are traces routed from BGA ball either to a point beyond the ball array or to another layer where full normal spacing guidelines can be met Breakout trace delay limited to 500 mils unless otherwise specified After breakout signal should be routed according to specified impedance for differential single ended or both for example HDMI Trace spacing to other signals also specified Follow max amp min trace delays where specified Trace delays are typically shown in mm or in terms of signal delay in pico seconds ps or both For differential signals trace spacing to other signals must be larger of specified x dielectric height or inter pair spacing Spacing to other signals pairs cannot be smaller than spacing between complementary signals intra pair Total trace delay depends on signal velocity which is different between outer microstrip amp inner stripline layers of a PCB Signal Routing Conventions Throughout this document the following signal routing conventions are used
91. ape from BGA to VIA is not optimal for DDR signals as it congests the space of breakout for PLLM power Follow Case 1 DDR breakout to via strategy for these two signals Better due to separation of PTH VIAS of PLLM to the DDR Power PTH VIAS but not good signal BGA to VIA breakout strategy that limits the space where PLLM power VIA can be placed Figure 51 Case 3 Good PCB Breakout Strategy good isolation between DDR Power and PLL PTH Vias VIAs Larger Circular areas Pads Smaller Circular areas Green GND Blue Etch Yellow PLL Power Connection Magenta 1 35V VDDIO DDR Power Connection Orange VDD CORE PEEM Power ume PTH isolation strategy for case 3 eliminates the PTH VIAS pertaining to the 2 BGA Pins Note it is imperative to make up for those lost PTH VIAS still to not impact the PDN of the DDR power Best isolation due to breakout strategy of not having PTH VIAS for particular BGA However the PTH VIAS must still be accounted for 7 1 2 PLLA P C2 C3 PLL Power Routing Coupling Minimization Routing PLL PLL Power Rail PLL Power PIN Aggressor Rail PLLA PLLP PLLC2 1 05V_DDR_AVDD B17 1 05V_DDR_AVDD_HS PLLC3 Powered same BALL Objective Increase the distance between the Vias White arrows to minimize the coupling PCB Case B is far superior to PCB Case A Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 96 of 115 a gt Teg
92. ax trace delays and max trace delay skew Table 93 SDMMC4_COMP_PU PD Routing Requirements Tegra K1 Embedded Platform Design Guide Parameter Requirement Units Note Reference plane GND if possible See Note Trace Impedance 50 Q 15 Max Trace Delay 240 ps Include Package amp PCB routing delays Note Table 94 SDMMC4 eMMC Signal Connections Keep SDMMC_COMP_PU PD routing away from other traces on same layer or on adjacent layers Function Signal Name Type Termination Description SDMMC4_CLK O eMMC Clock Connect to CLK pin of device SDMMC4 CMD 1 0 4 7KQ pull up to VDD 1V8 eMMC Command Connect to CMD pin of device 1 0 No external pull ups required eMMC Data Connect to Data pins of device SDMMC4_DAT 7 0 SDMMC4_COMP_PU SDMMC4_COMP_PD A 49 90 1 to VDD_1V8 49 90 1 to GND SDMMC4 Compensation Pull up Pull down Connect as shown in termination column eMMC RST eMMC Reset Connect PMU system reset output same as used for Tegra SYS_RST_IN to RST_N line of eMMC device Table 95 SDMMC4 Interface Package Delays Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Delay Delay Delay Delay ps ps ps ps SDMMC4_CLK G31 74 SDMMC4_DAT1 F30 71 SDMMC4_DAT4 D31 79 SDMMC4_DAT7 F28 62 SDMMC4_CMD E31 85 SDMMC4_DAT2 E28 66 SDMMC4_DAT5 E30 79 SDMMC4_COMP_PD H29 67 SDMMC4 DATO
93. ctor JTAG_RTCK l JTAG Return Clock Connect to RTCK pin of connector JTAG_TRST_N l 100kO to GND JTAG Reset Repurposed to select Normal JTAG or Scan mode Normal operation Pulldown only Scan test mode Pull strongly 1kQ to 1 8V_VDDIO 3 14 Strapping Pins The straps are sampled at the rising edge of SYS_RESET_N and must remain valid for gt 12 5us Figure 41 Power on Strapping Connections 100kQ ForceRecovery Test Point k to enter Force Recovery Tegra Strappin 1 8V 4 GND Force R FORCE_RECOVERY_N RRL L8V Reserved JORKO O JTAG ARM1 100k0 t t NYX z 7229 So 2329 JTAG_ARMO 100 wow s gt s 3 H o 08909 3 0 Bc 8 RAM_CODE3 4 RAM_CODE2 RAM_CODE1 RAM_CODEO T T T RAM CODE straps SY S2 Z Z 2S2 2 2 a o o a a ao a a Default strapping shown S5 o O oeg o O wg BOOT SELECT CODE3 BOOT_SELECT CODE2 BOOT_SELECT_CODE straps 1 8V BOOT_SELECT CODE1 Default setting 1011 for Z wom BOOT_SELECT CODEO eMMC x8 BootModeOFF Note _ The strap pins can be used for other purposes GPIOs or SFIOs if supported as long as any connected device does not keep them from being at the correct strap level when SYS_RESET_N goes high amp for 12 5us afterward Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 86 of 115 o Tegra K1 Embedded Platform Design Guide NVI
94. ctual connector i e USB HDMI SD Card etc or device i e onboard USB device Display driver IC camera imager IC etc Trace Delay Flight Time Matching Signal flight time is the time it takes for a signal to propagate from one end driver to other end receiver One way to get same flight time for signal within signal group is to match trace lengths within specified delay in the signal group Except for DRAM or if otherwise stated always include Tegra substrate trace delay or propagation delay in all trace delay or flight time matching calculations Total trace delay substrate trace delay board trace delay Do not exceed maximum trace delay specified For six layers or more it is recommended to match trace delays based on flight time of signals For example outer layer signal velocity could be 150psi ps inch amp inner layer 180psi If one signal is routed 10 inches on outer layer amp second signal is routed 10 inches in inner layer difference in flight time between two signals will be 300ps That is a big difference if required matching is 15ps trace Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 22 of 115 A NVIDIA Tegra K1 Embedded Platform Design Guide delay matching To fix this inner trace needs to be 1 7 inches shorter or outer trace needs to be 2 inches longer In this design guide terms such as intra pair amp inter pair are used when descr
95. d AVDD_HDMI_PLL connects to 1 05V supply VDDIO_HV connects to 1 8 2 8 3 3V supply 2 8 3 3V used if DDC connected to HDMI connector If VDDIO_HV connects to 1 8 the only SFIO function supported is DDC 12C DDC_SCL SDA connect to corresponding pins of HDMI Connector through 330 series resistors 1 8K pull ups to VDD_HDMI 5V supply HDMI_CEC connects to CEC on connector through gating circuitry Table 126 Video Camera CSI Input Cecklist Description Same Diff NA CSI A CLK P N Clock connects to CLKn tt CLKp pins of primary camera CSI A D 1 0 P N amp CSI_B_D 1 0 _P N pins connect to up to 4 lanes of primary camera CSI E CLK P N Clock connects to CLKn amp CLKp pins of secondary camera CSI E DO P N pins connect to up to secondary camera CAM_MCLK connects to primary camera Small Test Points added to CSI_xxx lines near Tegra Connections from test points to signal very short Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 110 of 115 o Tegra K1 Embedded Platform Design Guide NVIDIA Description Same Diff NA CAM_MCLK2 GPIO_PBBO connects to secondary camera CAM_I2C_SCL SDA from Tegra connect to Primary amp Secondary cameras CAM_I2C_SCL SDA have 1 8kQ pull ups or values based on section 7 1 of the NXP Philips 12C bus spec tt user manual Version 3 CSI DS
96. d RAS_N CAS_N WE_N amp RESET_N 2 T Topology Branch 2 DDR3L 1 Branchi Main Trunk DDR3L 2 Tegra CD CD CD DDR3L 3 C DDR3L 4 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 32 of 115 a gt Tegra K1 Embedded Platform Design Guide NVIDIA Table 25 DDR3L 4x16 Address Command Signal Routing Requirements Parameter Requirement Units Note Max Frequency Data Rate 466 5 466 5 MHz Mbps Note 1 Switching Period T 2 T Topology T T Configuration Device Organization 4 load Reference Pplane GND Max PCB breakout length 6 35 mm Via proximity Signal to Reference lt 3 8 24 mm ps See Note 2 Capacitance Input Capacitance Min M 0 75 1 2 pF Input Capacitance Delta All Add Cmd Min M 0 4 0 4 pF Impedance Spacing Trace Impedance 50 Q 15 Trace Spacing Microstrip Stripli 3x 2x dielectric Max Via Count Max Number of Vias Tx to Rx Per device Tx to all 4 8 loads Trace Lengths Delays Max Trace Length Delay PCB Main Trunk 41 28 260 mm ps Max Trace Length Delay Branch 1 14 29 90 mm ps Max Trace Length Delay Branch 2 14 29 90 mm ps Max Trace Length Delay Asymmetry for Branch 1 7 17 45 mm ps Max Trace Length Delay Asymmetry for B
97. d the 7 maximum tolerance allowed at the Tegra power balls including supply DC tolerance ripple amp voltage transients variations in voltage caused by changes in load Impedance simulations should use all the output capacitors large capacitor s just beyond DC DC inductor as source and all the power pins as sinks 2 2 1 Power Impedance Specifications Figure 2 Target Impedance Definitions for PCBs Zerp_HF_Target Target Impedance Impedance at High Frequency l DCR DC Resistance Zero RES Target Max impedance at Z RES_Target takers ae l resonance peaks below 10MHz Target Impedance for Board Resonance Zero HF target Max impedance at 100MHz This specifies the inductance limit of current path to high performance ceramic capacitors gt Frequency 10MHz 100MHz 100KHz Table 3 CPU GPU CORE amp DDR Power Impedance Specification VDD_CORE VDD CPU VDD GPU VDD DDR Comments DCR mO 13 3 13 5 11 2 11 0 Resonance Peak Impedance ZBRD RES Target mQ 12 5 7 2 7 7 11 0 lt 10MHz Z5ro HF Target mO 82 5 105 2 108 6 120 0 100MHz Note VDD DDR includes Tegra VDDIO DDR amp DRAM supplies for full 64 bit memory interface The components shown in the tables on the following pages were selected to meet the above voltage tolerance requirements for each supply In addition to actual part numbers critical parameters amp values for the components a
98. dcenascecnecsassdensecsodvecsscedsectadscessaadndenszsdednactaceacessastcdecnceocecexeccuassccesdeasnasaccecescedcdsnansieeees 7 2 2 CPU GPU CORE amp DDR Supply Considerations na 10 2 2 4 Power Impedance Specifications naaa NGALAN GINA NAA nen BADING ALALA ADAN 10 2 2 21PowerSequenGiNg panakaw KANAN NANA KANA NA ABRA ADIK GANAN NALNG ANN iaa kara 15 2 3 Power Decoupling Guideline 5 aaa GARA ANA 15 2 4 Decoupling Capacitor Placement sasa AASA GAARAA aa 15 2 5 Remote Power Sense Guidelines ciiscssccscscesseccscssnssvessssccvecasscsvesassesscansecsveesccesssececssenscesensecsessstecesensascesasceress 17 2 6 VPP FUSE SUPDIV EE T E ETTE EAR 17 2 7 Thermal Throttling SOC _THERM ccssscsseeeseeeesseeeeseeeeneeeneeeesaeeeneeeesaeeeaeeaeaseeeaseasaseesaseasaseaeaseeeaseeeaseaenee 18 2 8 5V Input Considerallons a canceescdezceceesteesanccesuadasccaesaceesoaesenceccages cacerscessctaeseneesaueeseuedeacedecaeesat 18 2 9 Power Voltage Monitors mana nanaman aa 18 2 9 1Power MONTON ttrian aei BINIGANARNGNBALNG BANA RALN NIAN ALA LANA LLANA Ah aala 18 2 9 2 Voltage MONITO nakak ND ANNA Eara aida LANA ANG aaa en AA hse tas 19 2 10 Deep Sleep Wake Considerations manaananananaaanasananaaaaasar nananana 19 2 11 General Power Routing Guideline nanna nn na 20 3 0 Interface Routing Guideline sciscciscccceccsssscecsessecsdasscceecssscesadecteddedsectasacsccassactecesantestestectecda
99. e 5 mils larger than SMT SATA connector pad in each direction If space is available use 2 GND vias for 1 GND pad to decrease differential mode far end cross talk as well as mode conversion when void is enlarged as described above Delay Matching Do trace delay matching before the vias to transition to different layers Maximal of vias Maximum of 4 vias per TX traces and 2 vias per RX trace Routing over voids Where signal pair approaches vias maximal trace length across void on plane is 1 27mm Serpentine line rule For microstrip line minimal spacing between each turn is 4x dielectric For stripline it is 3x dielectric height 3x of thinner of above amp below DC Blocking capacitor location Place DC blocking capacitors less than 12 5mm from connector If direct device connection the capacitors are recommended to be located next to each transmitter on Tegra and Device DC Blocking capacitor GND removal Remove plane underneath the DC blocking capacitor pads If board has ICT pads remove plane under those as well Void is size of pad ring equal to dielectric thickness Anti pad for connector pin Not required if PCB trace connecting AC cap amp connector is on bottom layer In case PCB trace connecting AC cap amp connector is on top layer increase size of anti pads for connector pins to 35mm amp void out ground planes whenever there are solder pads Table 59 SATA Signal
100. e Read Write bit removed or 8 bit including the Read Write bit Be sure to compare I2C device addresses using the same form all 7 bit or all 8 bit format Note Due to the general purpose design of the I2C drivers the strong drive strengths of the Tegra pads violate the minimum fall time specification for FM mode amp minimum rise fall time specification for HS mode We do not expect the faster rise fall times to cause any functional failures for I2C but to be fully compliant with the NXP I2C V 3 specifications implement the following board level solution 5 For FM mode Include a provision to add a shunt capacitor close to the Tegra drivers before the pull up resistors Ensure the total minimum capacitance on the SCL SDA signals is 350pF The total capacitance includes capacitance of the slave devices trace capacitance amp any required shunt capacitance Calculate the value of the shunt capacitance accordingly 5 For HS mode Include a provision to add an RC circuit close to the Tegra drivers before the pull up resistors Ensure the series resistor of the RC circuit has a resistance of 150 Ohms Ensure the total capacitance on the SCL SDA signals is 100pF The total capacitance includes capacitance of the slave devices trace capacitance amp any required shunt capacitance Calculate the value of the shunt capacitance of the RC circuit accordingly PWR 12C Usage Restrictions The PWR_I2C interface latencies must be controlled therefore the f
101. e on a Pin Config group basis The control options available for the Pin Config groups are HSM High Speed Mode Enable Disable For better matching of rise fall delays in outbound amp inbound paths for driver amp receiver May be useful for clocks amp high speed signaling where matching timings are critical SCHMT Schmitt Trigger Enable Disable Optional Schmitt Trigger mode for improved noise immunity DRVDN UP Drive Down Up Up to 5 bits 32 settings of output drive strength control see note DRVDN UP_SLWR Drive Down Up Slew Rate 4 levels of falling rising edge Drive Down up signal slew controls Note Schmitt Trigger mode should not be enabled for the OD type pads Used for DDC_SCL SDA amp HDMI_INT as this may result in Vj Vjy levels not meeting the DC Characteristics specifications in the Data Sheet Not all controls listed in the table are available for all pin groups The table below provides estimated output drive values across minimum maximum DRVUP DRVDN settings There are values for 1 8V 2 8V and 3 3V power rail voltages Table 117 Output Drive Current Estimates across Pad Output Control settings 1 8V 2 8V 3 3V Drive current mA Drive current mA Drive current mA DRVUP DRVDN Min Typ Max Min Typ Max Min Typ Max 00000 7 2 15 5 23 8 11 9 22 2 32 5 16 5 28 3 40 0 11111 14 7 23 4 32 1 28 7 39 8 50 8 36 5 48 3 60 0 Tegra K1
102. e primary set routes to DDR3L devices 1 amp 2 while the secondary set routes to 3 amp 4 Table 31 DDR3L 4x16 Clock Routing Requirements Parameter Requirement Units Note Max Frequency 933 MHz Note 1 Switching Period T 0 5 T Topology T Branch Configuration Device Organization 2 load Reference plane GND Max PCB breakout length 6 35 mm Via proximity Signal to reference lt 3 8 24 mm ps See Note 2 DDR_CLK CLK_N AC Source Termination Max Length Delay 2 54 16ps mm ps 2 2pF capacitor between CLK from Capacitor to Tegra amp CLK_N Capacitance Input Capacitance Min N 0 75 1 2 pF Input Capacitance Delta CLK P CLK N Min NO 0 15 pF Impedance Spacing Trace Impedance Single Ended Differen 50 90 Q 15 Trace Spacing Microstrip Stripl 3x 2x dielectric Max Via Count Max Number of Vias Tx to Rx Per device Tx to all loads 4 8 Trace Lengths Delays Max Trace Length Delay PCB Main Trunk 30 16 190 mm ps Note 5 Max Trace Length Delay Branch 14 29 90 mm ps Note 5 Max Trace Length Delay Asymmetry for Branches 7 14 45 mm ps Absolute Max Trace Length Delay Term A 12 7 80 mm ps Absolute Max Trace Length Delay Term B 3 18 20 mm ps Absolute Max Trace Length Delay Term C 3 18 20 mm ps Absolute Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corp
103. eaeeseeeeaeeseeseeessaeseneeeeaees 95 7 1 2 PLLA P C2 C3 PLL Power Routing Coupling Minimization Routing c cescceeceeeteeeeeeeeeeseeeeeeeseaeeseeeseeessneseaneneaees 96 7 2 Other Design Considerations ccsecccseccsseesseesseeeseneeesseeeeseessseeesneeseseeenseesasnaeaseesaseasaseesaseasaseesaseaeasnesaeeaenss 98 7 3 PLL Design Guide Specific Checkout List cccsecceseseseessseeesseeeeseeenseeesseaenseeseseesaseeeaseasaeeeseseesaseesaseaeass 99 8 0 Design Guideline Glossary asana 100 9 0 Design Checklists ic c cccccectecacesseciesecnescaiessecedsecesececaseesteccestesneseacecascuccndesvectecscaeecsecs sacesceeve sutaczandessucveanessecedeeenss 103 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 4 of 115 D Tegra K1 Embedded Platform Design Guide NVIDIA 1 0 Introduction 1 1 Abbreviations and Definitions The following table lists abbreviations that may be used throughout this document and their definitions Table 1 Abbreviations and Definitions Abbreviation Definition BT Bluetooth CEC Consumer Electronic Control DDR3L Double Data Rate DRAM Third generation eMMC Embedded MMC GNSS Global Navigation Satellite System GPS Global Positioning System HDMI High Definition Multimedia Interface HSIC High Speed Inter Chip Interface I2C Inter IC 12S Inter IC So
104. ebeci ns E E NANA NANANA RN mana 69 3 6 2 Digital TV DTV csscssssssessessessessessessessecsessussussusssssussusssssiseacssstasssesasssetssesetssssussessessessussussusssssessissessistatesetisesersseseeseeed 73 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 3 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 3 7 SDOMMG GANG 74 Bie MMC ANAN ANA AA E TE Amana 74 3 72 SD Card GOnMGCtiOnS a NINANG GAGA ENEA LA EEEE DIBDIB TAK NAHIRANG UNAN 76 KEAN PAA AA 78 BQ 2G aa GAGA A 80 Kc a LE a A 82 3 11 SP nnaman E ANN nma hahaa NAA 83 3 12 Thermal Senso naan AA AN diecceeneeteadevaSaciedcennaedi ct bee veuesSeneteeneasunevenusededbcncwieedeectaeteenweane 84 3 13 JTA Qus aasa 85 3 14 Strapping PINS aasa NGABA AA 86 4 0 Pads COntrol Si naaa AIRA GANA RAR 88 5 0 Unused Interface Terminations AA 89 5 1 Unused Muxed Standard CMOS Pad Interfaces 11 110mannananananaaaaananaaasaaasaa nanna 89 5 2 Unused Special Function Interfaces nannan 89 6 0 PCB Pad Layout Recommendations 1 naaa 90 6 1 PCB StaCk u o E A 91 6 2 Breakout Examples aman 92 7 0 Tegra PLL Power Design Guidelines 110777020 asaararaaaa nann nnnn nananana nn 95 7A PLL Power Routing Design Guide 1 1 mnamananaaanaaaaaa nannan 95 7 1 1 PLLM PLL Power Routing Coupling Minimization ROUutiINg c ccecceeeseeeeeseneeseeeeeeeseaeeeaees
105. eed Full Speed Low Speg 10 150 600 pF Reference plane GND Breakout Region Impedance Min width spacing Trace Impedance Diff pair Single Ende 90 50 Q 15 Via proximity Signal to reference lt 3 8 24 mm ps See Note 1 Max Trace Delay Microstrip Striplin 1280 8 1150 7 ps in See Note 2 Max Intra Pair Skew between USBx DP amp USBx DN 2 5 ps See Note 2 Note 1 Up to 4 signal vias can share a single GND return via 2 Max Trace Delay amp Max Trace Delay Skew matching must include substrate pin delays unless otherwise specified 3 Default USB drive strength slew rate termination values are fused at the factory for each Tegra device Default fused settings will meet USB Electrical specification using max trace delays listed in table above If adjustments to the settings are required they MUST be done as an offset to default values instead of overwriting those values Consult AE amp CE team for assistance USB 3 0 Design Guidelines The requirements following apply to the USB 3 0 controller PHY interface USB3_RXON P amp USB3_TXON P Table 42 USB 3 0 Interface Signal Routing Requirements Parameter Requirement Units Note Data Rate UI period 5 0 200 Gbps ps Max Number of Loads 1 load Termination 90 differential Q On die termination at TX amp RX Reference plane GND Breakout Region Max leng 7 62 mm 4x dielectric spacing preferred Via proxi
106. egra DDR symbols 3 Removed LPDDR3 support Reduced max DRAM size supported to 4GB USB PEX SATA Updated USB Connections figure notes to show more ID connection details 7 Added note describing differences in USBO_VBUS connections between diagram amp reference schematics Removed text related to locations of series capacitors for PCle amp SATA from all locations except routing guidelines amp updated guidelines with location recommendations for direct connect cases HDMI Relaxed max trace length for highest freqency Strapping Removed special requirements for GPIO_PIO 7 Added note describing limitations for using strapping pins for other purposes after boot Unused IF Pins Updated to add more detail for PEX_CTL signals amp added missing SATA DCA functions Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 2 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA Table of Contents 1 0 Introduction oiicicseicccccesdccsancnncecittescncansdeccteccsdsacascecaneasaacedacucuerscevancancgeesaeisuuanasecendesseuanecnescedsasnaaadencessezandececcaesesscnencn 5 1 1 Abbreviations and Definilons aaa RA NNNANA NA NLNG RANA AN 5 LON TATE naaa R GN T E E T E 6 1 3 Tegra K1 Block Diagram wis ic cccisstessicecceccsascesccddeecestntececeidescasasandescescedseanansieccesscnsbendeodeadeessdcunnecadtecesscccentardesens 6 2 0 Power ANGAT ARA 7 24 Power Thee isis cicicezccsacsaceectdce
107. es section for power rail decoupling and filter requirements Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 57 of 115 A NVIDIA eDP Design Guidelines Table 66 eDP HBR2 Main Link Signal Routing Requirements Tegra K1 Embedded Platform Design Guide Parameter Requirement Units Note Max Data Rate per data lane HBR2 HBR R 5 4 2 7 1 62 Gbps Min UI HBR2 HBR RE 185 370 617 ps Number of Loads 1 load Topology Point Point Differential Unidirectional Termination 100 Q On die at TX RX Reference plane GND Max PCB breakout length 7 63 0 3 mm in Trace Impedance Diff pair Single Ended 90 45 60 Q 15 Stripline Routing for Main Trunk Max trace length from Tegra TX pin to See Note 1 connector 215 8 5 mm in baga 165 6 5 mm in HBR 1137 ps 175ps inch delay assumption for Max Propagation Delay HBR stripline Max number of signal vias RBR HBR HBR 4 2 HBR2 One more test via right after AC cap OK PCB pair to pair spacing 3x dielectric height 3x of the thinner of above and below PCB main link to AUX Spacing 3x dielectric height 3x of the thinner of above and below Max stub length on the Vias Allowed Rout below core to minimize stub length Nicrostrip Routing for Main Trunk Max trace length from Tegra TX pin to See Note 1 connector 215 8 5 mm in RBR HB 127 5 152 4 6 mm in
108. f 115 o Tegra K1 Embedded Platform Design Guide NVIDIA Table 123 USB PCle SATA HSIC Checklist Description USBO available to be used as device for USB recovery at a minimum Same Diff NA GPIO_PI1 can be pulled to GND before SYS RESET N rises to enter recovery mode USBO_VBUS connected to output of 5V VBUS supply through load switch enabled by AVDD_USB supply USB 2 0 _DP N connect to USB connector Mini Card Socket Hub etc See Pins_EMI_ESD section for related checks USB ID from conn is pulled to 5V VBUS supply 100K Q amp connects to PMU PWM_CLK2 pin through FETs matches reference design USB_REXT connect through 1kQ 1 resistor to GND AVDD_USB connects to 3 3V Supply If USB Wake using USB mechanism required AVDD_USB is powered in Deep Sleep amp not connected to other rails that must be off AVDD_PLL_UTMIP connects to 1 8V Supply USB3 RXO P N tt PEX_USB3_RX1_P N connect to USB 3 0 connectors etc USB3_TXO_P N amp PEX_USB3_TX1_P N connects to USB 3 0 connector etc through 0 1uF series capacitors PEX_TERMP connect through 2 49kQ 1 resistors to GND AVDDIO_PEX DVDDIO_PEX amp AVDD_PEX_PLL required for USB3 amp PEX connect to 1 05V supply HVDD_PEX connects to 3 3V supply If USB 3 0 Wake using USB mech is required HVDD_PEX is powered in Deep Sleep tt not connected to other rails that must be off If USB 3 0 Connector used it must be USB
109. face not used DP_AUX_CHO_P N HDMI_TXCN P Leave NC or connect to GND if eDP or 12C6 interfaces not used Leave NC if HDMI interface not used Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 114 of 115 A NVIDIA Tegra K1 Embedded Platform Design Guide Description Same Diff NA Ball Name Termination HDMI_TXD 2 0 N P Leave NC if HDMI interface not used HDMI_INT Leave NC or use as GPIO HDMI_RSET Leave NC if HDMI interface not used AVDD_HDMI AVDD_HDMI_PLL SDMMC4_COMP_PU PD SDMMC3_COMP_PU PD SDMMC2_COMP_PU PD SDMMC1_COMP_PU PD Leave NC or connect to GND if HDMI interface not used Leave NC COMP_PU PD pins for any SDMMC interface not used for SDMNC functionality SDMMC3_CLK_LB_IN OUT Leave NC if SDMMC3 not used for SDMMC functionality THERM_DN DP VVDD_CPU_PROBE VVDD_GPU_PROBE VVDD_CORE_SENSE JTAG_TCK 100KQ to GND whether JTAG interface used or not JTAG_TDI Leave NC if JTAG interface not used JTAG_TDO Leave NC if JTAG interface not used JTAG TMS Leave NC if JTAG interface not used JTAG TRST N 100KQ to GND whether JTAG interface used or not JTAG RTCK Leave NC if JTAG interface not used Leave NC if external sensor connected to Tegra not used Leave NC Not used HDMI CEC Leave NC if not used OWR Leave NC Not supported Tegra K1
110. form Design Guide Parameter Requirement Units Note Configuration Device Organization 1 load Max Loading 8 pF Topology Point to Point Reference plane GND Breakout Region Impedance Min width spacing Trace Impedance 50 Q 20 Via proximity Signal to reference lt 3 8 24 mm ps See Note 1 Trace spacing Microstrip Stripli 2x 2x dielectric Max Trace Delay 3600 22 ps in See Note 2 Max Trace Delay Skew between SCLK amp 250 1 6 ps in See Note 2 SDATA_OUT IN Note 1 Upto 4 signal vias can share a single GND return via 2 Include Package amp PCB routing delays for Max trace delays and max trace delay skew parameters Table 101 12S Signal Connections Tegra Ball Name Function Name Type Termination Description DAP 4 1 SCLK 12S 3 0 SCLK 1 0 DAP Serial Clock Connect to 25 PCM CLK pin of audio device DAP 4 1 FS 125 3 0 LRCK 1 0 DAP Field Select Word Select for 12S Connect to WS 12S or FS SYNC PCM pin of audio device DAP 4 1 DOUT 12S 3 0 O DAP Data Output Connect to Data Input pin of audio SDATA OUT device DAP 4 1 DIN 125 3 0 SDATA IN l DAP Data Input Connect to Data Output pin of audio device DAP_MCLK1 EXTPERIPH1_CLK O External Peripheral 1 Clock Connect to MCLK pin of Audio device if reference clock required Table 102 DAP 4 1 I2S 3 0 Interface Package Delays Signal
111. g Requirements Parameter Requirement Units Note Max Frequency 3 3V Signaling DJ 25 12 5 MHz MB s See Note 1 Hg 50 25 1 8V Signaling SDR14 25 12 5 SDR24 50 25 SDR5 100 50 SDMMC1 tt SDMMC3 only SDR104 208 104 SDMMC1 amp SDMMC3 only DDR5 50 50 SDMMC1 amp SDMMC3 only Topology Point to point Max Loading 10 pF Reference plane GND or PWR See Note 2 Breakout Region Impedance 45 50 Q 15 Max PCB breakout delay 30 ps Trace Impedance 45 50 Q 15 Via proximity Signal to reference lt 3 8 24 mm ps Up to 4 signal vias can share 1 GND return via Trace spacing Microstrip Stripl 4x 2x dielectric Max Trace Delay SDR12 SDR25 SDH 1100 ps See Note 3 amp 4 SDR 745 Max Trace Delay Skew in between CLK amp CMD DAT See Note 3 amp 4 SDR12 SDR25 SDR 100 SDR 20 ps Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 76 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Parameter Requirement Units Note Loopback Clock Routing 150 ps LB_OUT to LB_IN CLK length Average of DAT 3 0 Keep SDMMC CLK CMD DATA COMP amp Loopback traces away from other signal traces or unrelated power traces areas or power supply components Note Table 97 SDMMC 3 1 _COMP_PU PD Routing Requirements Actual frequencies may be slightly different due to clock source divider limitations
112. gra supports eDP LVDS or DSI for embedded displays as well as HDMI for external displays The Jetson TK1 design provides access to the eDP LVDS display options on the Display Touch Expansion header Figure 24 Jetson Display Block Diagram Display Touch Tegra Display Connector Enable x4 gt Available for 2 x4 DSI interfaces 1 x8 4 DSI interface or DSI B can be used for x4 gt J an additional CSI x4 interface HDMI Connector 3 5 1 eDP LVDS Jetson supports up to a 4 lane single link LVDS interface or up to a 4 lane eDP interface The maximum resolution supported with LVDS is 1920x1200 60fps 24bpp color depth With eDP the maximum supported using the full 4 lanes is 3840x2160 60fps LVDS and eDP are multiplexed on the same pins See LVDS eDP Pin Assignment Options table below for pin assignments for each interface Table 65 eDP LVDS Pin Assignment Options Tegra Ball LVDS 3 lane LVDS 4 lane eDP LVDSO_TXDO_P N LVDS lane 0 LVDS lane 0 eDP lane 2 LVDSO_TXD1_P N LVDS lane 1 LVDS lane 1 eDP lane 1 LVDSO_TXD2_P N LVDS lane 2 LVDS lane 2 eDP lane 0 LVDSO_TXD3_P N N A LVDS lane 3 N A LVDSO_TXD4_P N LVDS clock lane LVDS clock lane eDP lane 3 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 56 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA Figure 25 eDP 4 Lane Connection Example
113. ibing differential pair delay Intra pair refers to matching traces within differential pair for example true to complement trace matching Inter pair matching refers to matching differential pairs average delays to other differential pairs average delays General PCB Routing Guidelines For GSSG stackup to minimize crosstalk signal should be routed in such a way that they are G not on top of each other in two routing layers see diagram to right s EE k SE e G Do not route other signals or power traces areas directly under or over critical high speed interface signals 3 2 Clocks Table 13 Tegra Clock Input amp General Output Tree Type Clock Description Typical Use Source Tegra Pin Power Rail nput 32kHz 32 768kHz clock Used by PMC PMU CLK_32K_IN VDDIO_SYS SYS2 nternal OSC Oscillator Main Tegra clock source XTAL or XTAL_IN OUT AVDD_OSC External XTAL_OUT only VDDIO_SYS SYS2 nternal PLLA PLLP PLLA Used for Audio PLLP used for a variety of OSC AVDD_PLL_APC2C3 PLLC2 PLLC3 peripheral blocks PLLC2 C3 are multi purpose PLLs nternal PLLC PLLG PLLG used for Graphics Engine PLLC is a multi OSC AVDD_PLL_CG purpose PLL nternal PLLU PLLD PLLU used for USB 2 0 PLLD D2 used for OSC AVDD_PLL_UD2DPD PLLD2 PLLDP Display amp MIPI DSI amp CSI PLLDP used for eDP nternal
114. ing strategy Easier to relocate components amp busses to different areas of board 3 4 USB PCle SATA Interfaces Tegra has three USB 2 0 controllers Controller 1 can drive a USB 2 0 PHY supports USB Recovery mode Device amp Host modes are supported Controller 2 can support either a USB 2 0 PHY or HSIC Only Host mode is supported for the PHY Controller 3 can be configured to drive either a PHY or HSIC IF Only Host mode is supported for the PHY The XUSB3 controller supports up to two USB 3 0 interfaces and can also be configured to drive the USB 2 0 PHYs Two PCle controllers supporting up to 5 PCI lanes two interfaces and a single SATA controller interface is provided See the table below for possible USB 3 0 PCle amp SATA lane mappings Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 41 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA Table 40 USB 3 0 PCle amp SATA Lane Mapping Use Cases USB3_TXO PEX_USB3_T PEX_TX2 PEX_TX3 PEX_TX4 SATA_TX USB3 RXO X1 PEX RX2 PEX RX3 PEX RX4 SATA RX PEX USB3 R X1 re Ka Ju ree 3 4 1 USB Figure 20 TK1 USB Connections 5V_SYS Q igi NBUS SW 5y sys USB VBUS ENO pay Note EN HO x 3 3V LPO Tegra x 3 3V LPO To PMU PWM CLK2 x 3 3V LPO USB 2 0 USB0 DP USB0O DN Mod To Mini PCle Connector 1 8V_VDDIO_LP0_OFF 1kQ 1 p 1 05V_RUN_AVDD USB
115. ions match reference design PMU Power Control GPIOs connections match reference design External Supply connections match reference design Supply Considerations VDD_CPU inductors amp output caps matches or exceeds specs of device in 2 2 CPU GPU CORE amp DDR Supply Considerations VDD_GPU inductors amp output caps matches or exceeds specs of device in 2 2 CPU GPU CORE tt DDR Supply Considerations used SOC Therm connections match reference design VDD_CORE Inductor amp output caps matches or exceeds specs of device in 2 2 CPU GPU CORE amp DDR Any additional peripheral devices have dedicated supply or load switch to allow it to be shut off when not shown in section 2 9 Power monitor implemented if 5V or Single cell design Device connections matche Reference Design shown in section 2 9 2 Voltage monitor implemented if 5V or Single cell design Device connections matches Reference Design Table 121 Power Decoupling Filtering Checklist Descripiion o 1 Na i l Caor Caor Same Diff NA Decoupling for VDD_CORE is 3 0 0 7 Decoupling for VDD_CPU is 4 0 0 8 Decoupling for VDD_GPU is 3 0 0 6 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 104 of 115 A NVIDIA Tegra K1 Embedded Platform Design Guide Description 0 1uF 0201 1uF 0201 2 2uF 020
116. ir Skew within pair Package PCB E Difference in delay between two traces in differential pair 5 Includes package die to pins amp PCB routing pin to destination In example this is A B C verses D E F or G H I verses J K L lt Shorter routes may require indirect path to equalize delays Inter Pair Skew pair to pair Package PCB Difference between two or possibly more differential pairs Includes package die to pins amp PCB routing pin to destination g In example Average of A B C tt D E F verses average of G H I amp J K L Here both G H I tt J K L required indirect path to match other pair Microstrip vs Stripline ia Microstrip Traces next to single ref plane Stripline Traces between two ref planes Trace Impedance 5 Impedance of trace determined by width amp height of trace distance from ref plane amp dielectric constant of PCB material z For differential traces space between pair of traces is also a factor Board trace spacing Spacing to other nets a Minimum distance between two traces Usually specified in terms of dielectric height which is distance from trace layer to reference layer aes PCB Route Bj o Oh OO OO Gogo OG O po Goo wooo O Be O e Device 10 93UU09 JO 9149q Trace Trace Width PL E Height Dielectric 1 4 IA Sign
117. kew from DQ to DQ within same 32 bit 12 70 80 mm ps partition Max Trace Length Delay Skew from DQ Lower 32 bit partition to 12 70 80 mm ps DQ Upper 32 bit partition General DQ DM DQS Routing Considerations DQ DM DQS in each byte should be kept on same layer Note ils achievable PLL frequency used to clock the EMC block 2 Up to 4 signal vias can share a single GND return via Table 24 DDR3L 4x16 Data Signal Group Connections Max frequency is target Actual frequency may depend on characterization results and Signal Name Type Termination Description DDR DQ 63 0 1 0 No VTT or ODT On Data Connect to DQ pins of all DRAMs see table below DDR_DM 7 0 O Die Termination Data Mask Connect to DM pins on DRAMs see table below DDR_DQS 7 0 P DIFF 1 O Required Data Strobes Connect to DQSxP DQSXN pins of all DRAM table below N Byte Lanes Groupings per channel Data Data Mask Data Data Data Mask Data Strobe Strobe DQ 7 0 DMO DQSOP N DQ 39 32 DM4 DQS4P N DQ 15 8 DM1 DQS1P N DQ 47 40 DM5 DQS5P N DQ 23 16 DM2 DQS2P N DQ 55 48 DM6 DQS6P N DQ 31 24 DM3 DQS3P N DQ 63 56 DM7 DQS7P N Note The Tegra DRAM ball names may not correspond to the signal brought out on that ball Use the DRAM Pin Multiplexing table to select the correct Tegra ball to connect to each DDR3L ball Figure 16 DDR3L 4x16 Address A 15 6 2 0 Comman
118. l Via to GND Via Proximity Layer 1 SIG gt E CI eee Layer 2 GND Layer 3 SIG Praa Go ao Layer 4 SIG Soma Ca CD Layer 5 PWR i Layer 6 SIG SC oo oa Layer 7 GND Layer 8 SIG gt E Via connecting GND layers near CP signal via provides good return path GND reference via for Differential Pair Where a differential pair changes GND reference layers return via should be placed close to amp between signal vias example to right Signal to return via ratio z Number of Ground Return vias per Signal vias a For critical interfaces ratio is usually 1 1 For less critical interfaces several trace vias can share fewer return vias i e 3 2 3 trace vias amp 2 return vias Slots in Ground Reference Layer When traces cross slots in adjacent power or ground plane Return current has longer path around slot Longer slots result in larger loop areas Avoid slots in GND planes or do not route across them Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 101 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA Routing over Split Power Layer Reference Layers When traces cross different power areas on power plane Return current must find longer path usually a distant bypass cap 5 If possible route traces w solid plane GND or PWR or keep routes across single area If traces must cros
119. lculations must include all the PCBs flex routing Keep critical eDP LVDS related traces including differential clock data traces amp RSET trace away from other signal traces or unrelated power traces areas or power supply components Table 72 eDP Signal Connections Ball Name Type Termination Description LVDSO_TXD 4 0 _P O eDP Series 0 1uF capacitors eDP LVDS CLK Data Lanes See eDP LVDS Pin N Assignment Options table or diagrams for correct connection to display connector LVDSO_RSET A 1KQ 1 to GND eDP Current Reference Connect to resistor to GND AVDD_LVDSO_IO P Note 1 eDP IO Power Rail Connect to 1 05V supply AVDD LVDSO PLL P Note 1 eDP Dedicated PLL Power Rail Connect to 3 3V supply for eDP DP AUX CHO P N O 100KQ pull downs on both lines near eDP Auxiliary Channel Connect to AUX CH P N on Tegra series 0 1uF capacitors then display connector 100KQ pull down on AUX P amp 100KO pull up on AUX N Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 60 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Ball Name Type Termination Description DP_HPD 1 0D eDP Hot Plug Detect Connect to HPD on display connector Note DP AUX CHO P N I2C6 tt DP_HPD only supported when IF block powered by VDDIO_HV is from 2 8 3 3V Table 73 LVDS Signal Connections
120. ll Name Type Termination Description DSI_A_CLK_N P O DSI Differential A Clock Connect to CLKn tt CLKp pins of receiver DSI A D 3 0 N P 1 0 DSI Differential A Data Lanes Connect to up to 4 sets of Dn amp Dp pins of Primary DSI display DSI_B_CLK_N P O Differential B Clock Connect to CLKn tt CLKp pins of secondary receiver Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 63 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Ball Name Type Termination Description DSI_B_D 3 0 _N P 1 0 Differential B Data Lanes Connect to up to 4 sets of Dn amp Dp pins of secondary DSI display or second set of 4 lanes to primary display CSI_DSI_RDN A 49 90 1 to GND DSI CSI Voltage Reference Pulldown CSI DSI RUP A 4530 1 to 1 2V DSI CSI Voltage Reference Pull up AVDD CSI DSI P MIPI DSI amp CSI Shared Power Rail Connect to 1 2V supply Table 78 DSI Interface Package Delays Signal Name Ball Pkg Signal Name Ball Pkg Signal Ball Pkg Signal Ball Pkg Delay Delay Name Delay Name Delay ps ps ps ps DSI_A_CLK_N AJ14 66 DSI A D2 N AL15 75 DSI B DO N AH12 67 DSI B D3 N AF12 55 DSI A CLK P AH14 66 DSI A D2 P AK15 75 DSI B DO P AJ12 67 DSI B D3 P AG12 56 DSI A DON AK11 76 DSI A D3 N AG14 56 DSI B D1 N AE12 47 CSI DSI RDN AG11 61 DSI A DO P AL11 75 DSI A D3 P AF14 57
121. lock the EMC block 2 Up to 4 signal vias can share a single GND return via w Control DDR 1 0 _CS 1 0 DDR 1 0 _CKE 1 0 amp DDR 1 0 _ODT 1 0 Table 30 DDR3L 4x16 Control Signal Group Connections Signal Name Type Termination Description DDRO_CS 1 0 O Chip Select Connect to CSx pins of all DRAM in lower 32 bit data DDR1_CS 1 0 Chip Select Connect to CSx pins of all DRAM in upper 32 bit data DDRO_CKE 1 0 O Clock Enable Connect to CKEx pin of all DRAM in lower 32 bit data DDR1 CKE 1 0 Clock Enable Connect to CKEx pin of all DRAM in upper 32 bit data DDRO ODT 1 0 O On Die Termination Control Connect to ODTx pin of all DRAM in DDR1_ODT 1 0 lower 32 bit data On Die Termination Control Connect to ODTx pin of all DRAM in upper 32 bit data Note The Tegra DRAM ball names may not correspond to the signal brought out on that ball Use the appropriate DRAM Pin Multiplexing tables included after each placement diagram to select the correct connections Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 36 of 115 a gt Tegra K1 Embedded Platform Design Guide NVIDIA Figure 19 DDR3L 4x16 Clock 1 T Topology Branch A DDR3L 1 or 3 Tegra 2 2pF 459 1 O CLK N gD GND VV GED Branch B DDR3L 2 or 4 Note There are two sets of differential clock signals Th
122. m ps Center Clk Branch A B Max Trace Length Delay Skew Any Add to any other Add for 25 4 160 mm ps Absolute A 5 3 amp A_B 5 3 this requirement is within each group not between the groups Note 1 Max frequency is target Actual frequency may depend on achievable PLL frequency used to clock the EMC block 2 Up to 4 signal vias can share a single GND return via 3 Address DDR A 15 0 DDR_A_B 5 3 DDR_BA 2 0 Command DDR_RAS DDR_CAS amp DDR_WE Table 28 DDR3L 4x16 Address A 5 3 for 32 bit partitions 1 0 Signal Group Connections Signal Name Type Termination Description DDR_A 5 3 O Address 5 3 Connect to matching Ax pins of DRAM in lower 32 bit data DDR_A_B 5 3 O Address B 5 3 Connect to matching Ax pins of DRAM in upper 32 bit data Note The Tegra DRAM ball names may not correspond to the signal brought out on that ball Use the appropriate DRAM Pin Multiplexing tables included after each placement diagram to select the correct connections Figure 18 DDR3L 4x16 Control 1 T Topology Main Trunk Tegra an DOR i 1 or 3 CD id D I 2 or 4 DDR3L Note There are two sets of control signals Primary set routes to DDR3L devices 1 amp 2 Secondary set routes to 3 amp 4 Table 29 DDR3L 4x16 Control Signal Routing Requirements Parameter Requirement Unit
123. max trace delay skew parameters Table 86 CSI_DSI_RDN RUP Routing Requirements Parameter Requirement Units Note Reference plane GND if possible See note 1 Trace Impedance 50 Q 15 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 70 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Parameter Requirement Units Note Max Trace Delay 40 ps Include only PCB routing delay Note 1 2 3 If stack up makes GND reference difficult keep routing distance very short amp have GND areas next to CSI_DSI_RDN RUP traces Use reference platform layout as a guideline for routing amp location of CSI DSI RDN RUP resistors Avoid routing signal traces directly below and in parallel with these critical rails Additional CSI Routing Guidelines Guideline If routing to DSI or CSI device includes a flex or 2 PCB the max trace amp skew calculations must include all the PCBs flex routing Keep critical DSI CSI related traces including DSI CSI clock data traces amp RDN RUP traces away from other signal traces or unrelated power traces areas or power supply components Table 87 MIPI CSI Signal Connections Ball Name Type Termination Description CSI A CLK N P l CSI A Differential Clock Connect to CLKn amp CLKp pins of Camera 1 CSI A D 1 0
124. mity Signal to reference lt 3 8 24 mm ps See note 1 Trace Spacing Microstrip Striplin 4x 3x dielectri To Ref plane tt capacitor pd 5x 3x c To unrelated high speed signa 5x 4x Max Trace Length 152 mm See Note 2 Max PCB Via distance from BGA ball 7 62 mm Max Intra Pair Skew RX TXN to RX TXP 0 15 1 mm ps See Note 2 Intra pair matching between subsequent 0 15 1 mm ps See note 3 discontinuities Via placement GND Via distance lt 1x Diff via See note 3 pitch Max Number of Vias 4 Via stub length lt 0 4 mm Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 43 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Parameter Requirement Units Note AC coupling capacitor 0 1 uF Discrete 0402 AC coupling capacitor Location lt 8 53 mm ps From adjacent discontinuities e g connector SMT Connector GND Voiding GND plane under signal pad should be voided Size of void should be the same size as the pad Note 1 Up to 4 signal vias can share a single GND return via 2 Include Package amp PCB routing delays for Max trace delays and max trace delay skew parameters 3 Recommend trace length matching to lt 1ps before Vias or any discontinuity to minimize common mode conversion 4 Place GND Vias as symmetrically as possible to data pair Vias Table 43 Additional USB 3 0 Routing Guidelines
125. mm Recommended to reduce capacitance and loss Guideline pad drill antipad 6 intended for PTH Plated Through Hole Vias Connector voiding Voiding GND below the signal lanes 5 7mil a tte N larger than the pin itself is recommended see figure N ESD protection device ESD protection required to meet device testing beyond 2kV HMM human metal model direct pin injection test Filter Capacitor on 5V 100 pF 0402 size capacitor on the 5V output is required for EMI reduction Routing Over void not allowed Exception is anti pad at connector pins which causes voids Route traces w min void references Routing away from sources of noise Keep critical HDMI related traces including differential clock data traces amp RSET trace away from other signal traces or unrelated power traces areas or power supply components Table 81 HDMI_RSET Routing Requirements Parameter Requirement Units Note Reference plane GND if possible See note 1 Trace Impedance 50 Q 15 Trace Spacing 2x dielectric Max Trace Delay 75 ps Include only PCB routing delay Note 1 2 Be If stack up makes GND reference difficult keep routing distance very short amp have GND areas next to HDMI_RSET trace Use reference platform layout as a guideline for routing amp location of HDMI_RSET resistor Avoid routing signal traces directly below and in parallel with these critical rails Table 82 HDMI Signal Connections Ball Name Type
126. n TK1 reference design are indicated Table 11 Signal Wake Events Potential Wake Event Tegra Ball Assigned Touch Screen Interrupt GPIO_W3_AUD Modem to AP Wake GPIO_PVO Battery Charger Interrupt GPIO_PJO System Overcurrent Alert GPIO_PJ2 Skin Temperature Alert GPIO PI6 PCle Wake PEX WAKE N Power Button KB COLO GPU Overcurrent Interrupt KB ROW15 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 19 of 115 a gt Tegra K1 Embedded Platform Design Guide NVIDIA Potential Wake Event Tegra Ball Assigned Headphone Insertion Detection KB_ROW7 Audio Codec pin SD Card Card Detect SDMMC3_CD_N PMIC Interrupt to AP PWR_INT_N Low Battery Alert KB_COL5 Wi Fi Interrupt GPIO_PU5 Available Bluetooth Interrupt GPIO_PU6 HDMI Hot Plug Detect HDMI_INT HDMI Consumer Electronic Control HDMI_CEC 2 11 General Power Routing Guideline Avoid routing critical signals near power components or noisy power traces areas whether on the same layer or above below the components or power traces areas Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 20 of 115 A NVIDIA 3 0 Interface Routing Guidelines 3 1 Overview Tegra K1 Embedded Platform Design Guide This section contains the PCB routing and other guidelines for the following Tegra interfaces
127. n order to make routing easier cleaner A table is provided for each DRAM configuration option supported that shows how the Address Control Command Data pins should be routed to the DRAM devices This table must be followed exactly 3 3 1 DDR3L Figure 12 DDR3L Connections Refer to 4x16 DDR3L DRAM Pin Remapping 0 01uF 1 35V Tegra 349 1 349 1 1 35V 1 05V able il 30 196 0 CLKP 0 CLKN 0 CS 1 0 A 15 6 2 0 P A 45 30 19 0 CKE 1 0 0 ODT 1 0 DDR3L 1 DOS 1 0 P DQS 1 0 N DM 1 0 DO 15 0 CLK CLK L CS 1 0 A 15 0 BA 2 0 CKE 1 0 ODT 1 0 RESET DQS 1 0 DQS 1 0 DM 1 0 DO 15 0 DDR3L 3 1Yo IH 39 1 mrs o 0 a 45 1 CKE 1 0 1_ODT 1 0 DOS 5 4 P DOS 5 4 N DM 5 4 DO 47 32 Note Tegra Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved CLK CLK L CS 1 0 A 15 0 BA 2 0 CKE 1 0 ODT 1 0 RESET DQS 1 0 DQS 1 0 DM 1 0 DO 15 0 0 CLKP 0 CLKN 0 CS 1 0 0 CKE 1 0 0 ODT 1 0 Per DRAM 1 amp 2 DOS 3 2 P DOS 3 2 N DM 3 2 DO 31 16 1 CLKP 1 CLKN 1 CS 1 0 1 CKE 1 0 1 ODT 1 0 DOS 7 6 P DOS 7 6 N DM 7 6 DO 63 48 DDR3L 2 CLK CLK L VDDi Cs 1 0 a A 15 0 BA 2 0 BAG zaol CAS zail WE CKE 1 0 ODT 2 0 VREFDQ RESET
128. n that enables visual computing in low power devices 1 3 Tegra K1 Block Diagram Opt From DSI Byte x4 N Cellular Modem NFC yro Acce M Barometer Ambient Light Snsr Tegra K1 USB 2 0 3 0 COMPLEX Tegra K1 Quad Core Cortex A15 Processor with NEON L1 Cache 32KB I Cache 32KB D Cache L2 Cache 2MB Unified Low Power Companion Cortex A15 IMAGE PROCESSING HIGH DEFINITION VIDEO DECODE amp ENCODE ENGINE LOW POWER AUDIO CONTROLLER CAMERA INPUT CONTROLLER PCle CONTROLLER x4 k i O E x1 ki i O Cameras DTV Receiver Pad Screen LED Driver A x4 lane gt LVDS eDP x4 lane gt B x4 lane gt TosLink or RCA Amp Solution Audio Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 6 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 2 0 Power 2 1 Power Tree Figure 1 TK1 Embedded Power Tree Jetson TK1 Platform Example Eo VDD_MUX i PMU Switcher SD2 1 35V_LPO H gt PMU Switcher SD3 TPS51220 1 Switcher PMULDOO 1 05V_RUN_AVDD 4VDD_CORE PMU LDO 3 1 00V LPO VDD RTC 2V STBY Wai PMU Switcher SD4 108V RUN 5V_STBY 1 05V_RUN_AVDD_ HDMI PLL AP GATE 3 3V_AON 1 8V VDDIO PMU Switcher SD5 PMU LDO 2 VDDIO_SDMMC3 3 3V q P
129. nnect to 3 3V supply HVDD_PEX_PLL_E PCle High Voltage Power Rail for Transmit PLL Connect to 3 3V supply VDDIO_PEX_CTL P PCle Control I O Block Power Rail Connect to 3 3V supply Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 50 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA Table 55 PCle Interface Package Delays Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Delay Delay Delay Delay ps ps ps ps PEX_USB3_TX AG21 26 PEX_RX3N AK24 45 PEX_CLK1N AG26 73 1N PEX_TX4N AH26 39 PEX_USB3_TX AF21 26 PEX_RX3P AL24 45 PEX_CLK1P AF26 72 1P PEX_TX4P AJ26 39 PEX_CLK2N AC27 67 PEX_RX2N AE21 39 PEX_TX3N AG23 29 PEX_TERMP AL22 54 PEX_CLK2P AC26 64 PEX_RX2P AD21 38 PEX_TX3P AF23 28 PEX_USB3_RX PEX_RX4N AL26 49 1N AL23 46 PEX TX2N AJ23 37 PEX_USB3_RX PEX_RX4P AK26 48 1P AK23 46 PEX TX2P AH23 36 3 4 3 SATA A Gen 2 SATA controller is implemented on Tegra The example below is from the Jetson design which brings this interface to a standard SATA connector amp provides control for an LED amp power connector Figure 22 Jetson SATA Connections Tegr 1 05V RUN AVDD SATA egra SATA 3 3V_LPO C 2 49KQ 1 Tee cia sa Switch 1 8v_vopDio AUDIO ON Note See the Power Decoupling
130. nt l 10 A Stage Inductor TDK SPM4015 R68M 2 Inductance L 0 68 uH DC Resistance DCR 32 7 mQ Size LxWxH 4 4x4 1x1 5 mm RMS Current Irms 40C rise 4 7 A Saturation Current Isat 30 drop 8 A Output Taiyo JMK212BJ476MG T 3 Data Sheet C 47 uF Capacitor Yuden Capacitance Size LxW 0805 mm Dielectric X5R Code Rated Voltage Vv 6 3 V Input Taiyo TMK316BJ106KD 4 Data Sheet C 10 uF Capacitor Yuden TD Capacitance Size LxW 1206 mm Dielectric X5R Code Rated Voltage Vv 25 V Table 7 Basic Tegra Power Control Connections Ball Name Type Termination typical Description CLK_32K_IN l 32 768kHz Clock input for 32kHz clock used by RTC amp PMC blocks SYS_RESET_N l System Reset Reset input for Tegra PWR_I2C_SCL SD O B 1KQ pull up resistor to Power 12C Connect to PMU A VDDIO_SYS CORE PWR REQ O Core Power Request Connect to CORE PWRREQ on PMU CPU PWR REQ O CPU Power Request Connect to CPU PWRREQ on PMU PWR INT l Power Interrupt Connect to XINT pin on PMU Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 13 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Table 8 Recommended States for Tegra Power Rails Typical grouping shown Power Rail Voltage Early For Boot Deep Note V Power on Sleep VDD_CORE Variable ON ON OFF VDD_CPU amp VDD_GPU Variable OFF OFF OFF VDD_RTC Variable ON ON ON AVDD_OSC PLL_UTM
131. o VDDIO SDMMC3 SDMMC Compensation Pull up Pull down SDMMC 3 1 _COMP_PD 33 20 1 to GND Connect as shown in termination column SD Card Detect See note for ESD protection SDMMC Card Detect Connect GPIO to Card Detect pin on socket Use Wake capable pin if wake required on insertion Note ESD protection strongly recommended for SDMMC3 when used as the SD Card socket interface SDMMC3_COMP_PU PD resistors can be 49 90 1 if limited to SDR25 50MHz operation Table 99 SDMMC 3 1 Interface Package Delays Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Delay Delay Delay ps ps ps SDMMC1_CLK L7 97 SDMMC3_CLK F5 63 GPIO_PK1 SDMMC2_CLK R3 63 SDMMC1_CMD L8 86 SDMMC3_CMD F2 76 GPIO_PH7 SDMMC2_CMD U2 71 SDMMC1_DATO L2 68 SDMMC3_DATO H2 74 GPIO_PH4 SDMMC2_DATO R5 80 SDMMC1_DAT1 L3 68 SDMMC3_DAT1 H1 89 GPIO_PI5 SDMMC2_DAT1 U7 52 SDMMC1_DAT2 L1 69 SDMMC3_DAT2 F1 77 GPIO_PH5 SDMMC2_DAT2 R4 67 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 77 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA Signal Name Ball Pkg Signal Name Ball Pkg Signal Name Ball Pkg Delay Delay Delay ps ps ps SDMMC1_DAT3 J8 90 SDMMC3_DAT3 G1 72 GPIO_PH6 SDMMC2_DAT3 U8 52 SDMMC1_COMP_PD L6 56 SDMMC3_CLK_LB_IN F3
132. ollowing restrictions must be observed Devices do not stretch clock pulses exception is any stretching performed by the approved PMUs which have been evaluated amp do not risk increasing the latency significantly enough to be a concern Limit the number of devices on the PWR_I2C bus to lower bus capacitance in order to hit Fast mode Plus FM speeds gt 1Mbps Only external CPU regulator or possibly Pre PMU should be on the bus with the PMU All slave devices on the physical PWR_I2C bus should support Fm bus speeds Table 103 12C Interface Signal Routing Requirements for Standard Fast tt HS High Speed Modes Parameter Requirement Units Note Max Frequency Standard Fast Mode Fast Mode P 100 400 1000 kHz See Note 1 High Speed Mo 3 4 MHz Topology Single ended bi directional multiple masters slaves Max Loading Standard Fast Mode Fast Mode P 400 pF Total of all loads High Speed Mo 100 Reference plane GND or PWR Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 80 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Parameter Requirement Units Note Trace Impedance 50 60 Q 15 Trace Spacing 1x dielectric Max Trace Delay Standard Mo 3400 20 ps in Include Package amp PCB routing Fast Mode Fast Mode Plus amp HS Mod 1700 10 delays Note 1 7 35 DDC supports only
133. on in Deep Sleep if used for Modem or possibly WiFi amp connection must be maintained AVDD_HDMI must be off in Deep Sleep to pass Voff compliance Do not combine with 3 3V rails that need to be on VPP_FUSE must be off in Deep Sleep or damage can occur This rail should be off at all times unless actively being used to burn fuses Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 14 of 115 Tegra K1 Embedded Platform Design Guide NVIDIA 2 2 2 Power Sequencing Figure 3 Power up Sequence Oms ims 2ms 3ms 4ms 5ms 6ms 7ms 8ms 9ms 21ms a It Power ON Button N 5V SYS TPS51220 Switcher KE 1 05V_LP0_VDD_RTC 1 00V PMU LDO3 tt VDD CORE Var AS3728 Boost SD1 3 tt 1 8V_VDDIO PMU Switcher SD5 re 3 3V_LPO SLG5NV 1430V Gate re CLK 32K IN From PMU CLK32K 32KHz 32KHz System Clock XTAL Ramp OSC 1 35V_LPO0 PMU Switcher SD2 3 tt 1 05V RUN AVDD 1 05V PMU LDOO re SYS_RESET_N PMU XRES_OUT _ Other Supplies amp Control Signals Ur nee W Note 1 8V_VDDIO Includes AVDD_OSC PLL_UTMIP LVDSO_PLL amp VDDIO_SYS SYS2 BB SDMMC1 SDMMC4 AUDIO UART GMI S 1 05V_RUN_AVDD Includes AVDD_PLL_UD2DPD PLL_C4 PLL_CG PLL_X PLL_APC2C3 LVDSO_IO PLL_X PLL_EREFE Critical relationships Tegra VDD_RTC 1 05V_LPO_VDD_RTC tt VDD_CORE VDD_CORE must be valid before other Tegra rails Tegra
134. or a SPI ROM optional boot device and SP11 for an interface option to a touchscreen controller SPI2 is also available for use amp is located on the ULPI data lines on the BB block Figure 37 Jetson SPI ROM Connections VDDIO_1V8 Tegra SPI ROM 5PIROM VDDIO_ 1V8 SPI4 SCK SPI4 MOSI SK MEG DI a a DO x cs m we HOLD Figure 38 Jetson Touchscreen Connector Connections Touchsceen VDDIO_1V8 Teg ra Touch 3 3V RUN TOUCH Connector TS SPI SCK TS SPI MOSI TS SPI MISO TS SPI Cs L TS SHDN L TS RESET L SPI Design Guidelines Table 109 SPI Interface Signal Routing Requirements Parameter Requirement Units Note Max Frequency 50 MHz Max Loading total of all loads 15 pF Reference plane GND Max PCB breakout delay 75 ps Trace Impedance 50 60 Q 15 Via proximity Signal to reference lt 3 8 24 mm ps See Note 1 Trace spacing Microstrip Stripl 4x 3x dielectric Max Trace Delay 890 5 ps in See Note 2 Max Trace Delay Skew between MOSI DOUT MISO DIN amp 50 ps CS to SCK Note 1 Up to 4 signal vias can share a single GND return via 2 Include Package amp PCB routing delays for Max trace delays and max trace delay skew parameters Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 83 of 115 a gt Tegra K1 Embedded Platf
135. oration All rights reserved Page 37 of 115 A NVIDIA Tegra K1 Embedded Platform Design Guide Parameter Requirement Units Note Skew Matching Max Trace Length Delay Skew CLK CLK_N Main Trunk T Branch A B 0 79 5 mm ps Absolute Max Trace Length Delay Skew from DDR_CLK DDR_CLK_N lower 32 bit clock pair to DDR_CLKB DDR_CLKB_N upper 32 it clock pair 4 76 30 mm ps Absolute Note 1 Table 32 DDR3L 4x16 Clock Connections Max frequency is target Actual frequency may depend on characterization results and achievable PLL frequency used to clock the EMC block Up to 4 signal vias can share a single GND return via 450 AC load termination resistors should be on top layer without any vias 0 01uF capacitor from resistors should be on top layer with single via to GND Max Trace Length Delay for PCB Main Trunk Branch amp the Max Trace Length Delay Branch requirements must be met The Max Trace Length Delay PCB Main Trunk can be exceeded as long as the Branch is adjusted to meet the Max Trace Length Delay for PCB Main Trunk Branch requirement Signal Name Type Termination Description DDRO_CLKP DIFF OUT 900 between CLKP amp CLKN amp 0 01uF cap center Differential Clock for Lower 32 bit Channel DDRO_CLKN tapped to GND 2 x 450 closest 1 value Connect CLK_P CLK_N pins of DRAM for 2 2pF cap between the CLKP amp CLKN line
136. orm Design Guide NVIDIA Table 110 SPI Signal Connections Function Name Type Termination Description SPIx SCK 1 0 SPI Clock Connect to Peripheral CLK pin SPIx MOSI 1 0 SPI Master Out Slave In Connect to Peripheral MOSI pin SPIx MISO 1 0 SPI Master In Slave Out Connect to Peripheral MISO pin SPIx CSx 1 0 SPI Chip Selects Connect to Peripheral CS N pin per Table 111 SPI Interface Package Delays Signal Name SPI1A Touch etc Ball Pkg Delay Signal Name SP14 SPI ROM etc Ball Pkg Delay ps ps ULPI NXT SPI1A_SCK AK17 71 GPIO PG5 SPI4_SCK AA3 66 ULPI STP SPI1A_CSO AL16 75 GPIO PI3 SPI4_CSO V7 54 ULPI CLK SPITA DOUT AK17 71 GPIO PG6 SPI4 DOUT Y8 64 ULPI DIR SPI1A DIN AL18 80 GPIO PG7 SPI4 DIN V3 69 3 12 Thermal Sensor External Thermal Sensor Tegra contains a single on die thermal diode that is accessed via an external i2c temperature monitor TI TMP451 The same temperature monitor IC used for accessing the thermal diode also contains an internal temperature sensor whose sensed temperature is referred to as Tboard This temperature is correlated to the internal PCB temperature and not entirely dominated by the Tegra temperature This board sensor is a required and essential part of the Tskin estimation and governing mechanisms It is recommended that the external thermal sensor should be located 15 20mm from Tegra and between
137. ower rail decoupling and filter requirements HDMI Design Guidelines Figure 29 HDMI Differential Clock amp Data Topology Tegra Main trunk SegA HDMI Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 65 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Table 79 HDMI Interface Signal Routing Requirements Parameter Requirement Units Note Max Frequency 297 MHz Data rate 1 U1 is ten times larger than the pixel frequency 1 T_pixel Topology Point to point Termination At Rece 50 Q To 3 3V at receiver On bd 500 To GND near connector Reference plane GND Max Breakout Length Delay 7 62 52 5 mm ps Trace Impedance Diff pair Single En 90 45 60 Q 15 Trace spacing Microstrip Strip 4x 3x dielectric See Note 1 Max Trunk Delay 297 Micros 140 5 5 850 mm in ps See Note 2 amp 3 Strip 152 6 1050 Max Trunk Delay 225 Micros 254 10 1500 mm in ps See Note 2 amp 3 Strip 204 8 1400 Max Trunk Delay 165 Micros 320 12 5 1870 mm in ps See Note 2 amp 3 Strip 254 10 1500 Max distance from ESD to connector Seg A 12 7 87 mm ps Max distance from signal line to ESD pad Seg B 6 35 37 5 mm ps Keep stub connecting ESD to signal trace very short or overlay pad on signal trace See example layout figure below table Max Intra Pair within pair Skew 1 ps See Note
138. oximity Signal to reference lt 3 8 24 mm ps See Note 2 Trace spacing Microstrip Stripli 2x 2x dielectric Max Trace Delay 1620 ps See Note 3 Max Intra pair Skew 1 ps See Note 3 Max Trace Delay Skew between DQ amp CLK 10 ps See Note 3 If routing to DSI or CSI device includes a flex or 2 PCB the max trace amp skew calculations must include all the PCBs flex routing Keep critical DSI CSI related traces including DSI CSI clock data traces amp RDN RUP traces away from other signal traces or unrelated power traces areas or power supply components Note 1 If PWR 0 01uF decoupling cap required for return current 2 Up to 4 signal vias can share a single GND return via 3 Include Package amp PCB routing delays for Max trace delays and max trace delay skew parameters Table 76 CSI_DSI_RDN RUP Routing Requirements Parameter Requirement Units Note Reference plane GND if possible See note 1 Trace Impedance 50 Q 15 Max Trace Delay 40 ps Include only PCB routing delay Note 1 next to CSI_DSI_RDN RUP traces 2 Use reference platform layout as a guideline for routing amp location of CSI_DSI_RDN RUP resistors If stack up makes GND reference difficult keep routing distance very short amp have GND areas 3 Avoid routing signal traces directly below and in parallel with these critical rails Table 77 MIPI DSI Signal Connections Ba
139. pe in Parts table Once the schematic has been loaded the designer will be able to select which component via is best for the design When to use component vias A component via is used wherever a T point is needed or when trying to control trace delays mid route The net topology is controlled by dividing it up into multiple segments Each section has a maximum delay associated In addition after each T branches also have relative delay skew requirements To control these items component vias are added to divide the nets into main trunk amp the two branches as shown below Branch A DDR3L 1 Main trunk Tegra Cvi Branch B DDR3L 2 The above example indicates the location of the component vias CV1 Each via must be added to the schematic before loading it into the layout file The final outcome is shown below Table 39 Example Segment Measurements using Component Vias Max Delays Measurement mm Max Skews Measurement mm Tegra to CV1 45 CV1 to DRAM 1 12 CV1 to DRAM1 verses CV1 to DRAM2 6 CV1 to DRAM 2 12 The cost of using component vias is the time required to add each via to the schematic and place them on the layout The benefits are many though Flowing T point issue is eliminated Easier to see the how topology is to be routed amp to perform routing checks amp to see topology in Constraint manager Easier to move component vias to maximize rout
140. peed mode 2 If the DDC SCL SDA interface is not used for HDMI DDC not used or used as an I2C interface to a device that operates at 1 8V VDDIO_HV can operate at 1 8V 3 GEN 2 1 _I2C CAM_I2C PWR 12C amp I2C6 are 3 3V tolerant If all devices on one of these 12C interfaces require 3 3V levels the bus can be pulled up to 3 3V instead of the normal 1 8V power rail voltage DDC is 5V tolerant 4 If some devices require a different voltage level than others connected to the same 12C bus level shifters are required 5 Disable OD Open Drain option for I2C interfaces pulled up to 1 8V Enable for I2C interfaces Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved pulled up to 2 2 8V Page 81 of 115 a gt Tegra K1 Embedded Platform Design Guide NVIDIA De bounce The tables below contain the allowable De bounce settings for the various 12C Modes Table 105 De bounce Settings Fast Mode Plus Fast Mode amp Standard Mode Source Clock 12C Source KAG De bounce 12C Mode Clock Source Freq Divisor SM FM Divisor Value 12C SCL Freq 0 1016KHz FM PLLP_OUTO 408MHz 5 0x04 10 0x9 5 1 905 8KHz 7 6 816KHz FM PLLP_OUTO 408MHz 5 0x4 26 0x19 7 0 392KHz SM PLLP_OUTO 408MHz 20 0x13 26 0x19 7 0 98KHz Table 106 Debounce Settings High Speed Mode Mode Source PLLP_OUTO 12C Source Div HS Div De bounce 12C Freq 0 3 48MHz
141. ps See note 3 Note 2 Be 1 If GND reference is not feasible as may be the case with GSSG stack up keep the routing distance very short and have GND areas traces surrounding the DDR_COMP_PU PD traces Use reference platform layout as a guideline for routing amp location of the DDR_COMP_PU PD resistors Avoid routing signal traces directly below and in parallel with this critical rail Table 35 DRAM VREF_DQ CA amp ZQ Routing Requirements Parameter Requirement Units Note Reference Plane GND if possible See note 1 Max Capacitance 5 pF VREF amp ZQ only See note 2 Trace Spacing 3x Dielectric To other signals Max Trace Delay Minimum See note 3 Note If GND reference not feasible keep routing distance very short amp have GND areas traces next to rails Maximum external load capacitance on ZQ pin including package PCB resistor ft DRAM device s Use reference platform layout as a guideline for routing amp location of bypass caps amp resistors ZQ amp VREF Avoid routing signal traces directly below and in parallel with this critical rail Locate capacitors amp resistors related to VREF amp ZQ very near associated DRAM balls Table 36 Miscellaneous Tegra DDR Connections Ball Name Type Termination Description DDR_COMP_PU A 340 1 to VDDIO_DDR DRAM Compensation Pull up See termination requirement DDR_COMP_PD A 340 1 to GN
142. ra K1 Embedded Platform Design Guide NVIDIA Easier to do than PLLM since the BGA are at the edge of the BGA and not in the middle where other signal nets must breakout Figure 52 BALL to Via Breakout Strategy Keep two power rail Vias as far as possible in the breakout PCB Case A PCB Case B Double spacing between the via separation GND Via in between the two vias to drastically reduces the mutual coupling The PLL and the HS are driven by the same PMIC on the PCB Goal is to keep them isolated on the PCB breakout and only connect them on the BOTTOM layer of the PCB away from BGA area to reduce the coupling interaction Keep the distance between the two PTH Vias at least 1 5mm and add a GND Via in between the 2 PTH PWR Vias if possible There is no option not to have a Via for the BGA because only 1 BALL is dedicated for each rail TheVDD 1 05 HS power the trimmers and during DPD Data Power Down Mode will generate a transient current and will couple over to the PLL power rail Figure 53 BALL to Via Breakout Strategy Keep two power rail Vias as far as possible in the breakout Ele kak vert Horz Acq Ing Depay Qusor Mea Myk Mah aop MyScope Liites Heb Button pai Scope Shot Showing the Self Generated noise from Power Down Mode Coupling over to the PLL Rail Note the absolute magnitude is filtered since measured at PCB Clearly see coupling Noise and the goal is to reduce it Tegra K1 DG 07508 001v03 Copyright
143. raints Table 16 PLL Power Trace to Power Plane Broadside Coupling Requirements PLL PWR Via Victim PLL Power Rail Trace Aggressor Routing Restriction PLLM amp PLLAPC2C3 PWR Trace Power 1 8V I O Power tt 1 35V 1 0 PLL power trace not allowed directly below or above the I O power plane to avoid broadside coupling Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 24 of 115 Tegra K1 Embedded Platform A Design Guide NVIDIA 3 2 3 32 768kHz Clock The 32 768kHz clock is provided by the PMU This clock is input on the CLK_32K_IN pin which is referenced to the VDDIO_SYS rail See the Tegra K1 Data Sheet for details on the requirements for this clock 3 2 4 Oscillator Clock A crystal is connected to XTAL_OUT and XTAL_IN to generate the reference clock internally A reference circuit is shown in Figure 11 The table contains the requirements for the crystal used the value of the parallel bias resistor and information to calculate the values of the two external load capacitors C and C shown in the circuit Figure 11 Crystal Connection Tegra XTAL_IN XTAL_OUT Table 17 Crystal and Circuit Requirements Symbol Parameter Min Typ Max Unit Note Fp Parallel resonance crystal Frequency 12 MHz 1 Frol Frequency Tolerance 50 ppm 1 CL Load Capacitance for crystal parallel resonance 5 12 pF 1 3 5 Typical values
144. ranch 2 7 17 45 mm ps Skew Matching bng Trace Length Delay Skew between Addr Cmd amp 25 4 160 mm ps PCB Main Trunk Branch 1 Branch 2 Max Trace Length Delay Skew between any Add Cmd 25 4 160 mm ps to any other Add Cmd Note 1 Max frequency is target Actual frequency may depend on characterization results and achievable PLL frequency used to clock the EMC block 2 Up to 4 signal vias can share a single GND return via 3 Address DDR A 15 6 2 0 DDRO_A 5 3 DDR1 A 5 3 DDR BA 2 0 Command DDR RAS DDR CAS amp DDR WE Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 33 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Table 26 DDR3L 4x16 Address Command Signal Group Connections Signal Name Type Termination Description DDR_A 15 6 2 0 O Address 15 6 2 0 Connect to matching Ax pins of all DRAM DDR BA 2 0 O Bank Address Connect to BAx pins of all DRAMs DDR CAS O Column Add Strobe Connect to CAS pins of all DRAMs DDR_RAS O Row Address Strobe Connect to RAS pin of all DRAMs DDR WE O Write Enable Connect to WE pin of all DRAMs DDR RESET N O Reset Connect to RESET pin of all DRAMs Note The Tegra DRAM ball names may not correspond to the signal brought out on that ball Use the DRAM Pin Multiplexing table to select the correct Tegra ball to connect to each DDR3L ball Fig
145. re listed These should be taken into consideration if different components are used It is important to work closely with the power supply vendor to ensure that any components selected meet the voltage current requirements of the supply and Tegra Impedance simulations should use all the output capacitors large capacitor s just beyond DC DC inductor as source and all the power pins as sinks Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 10 of 115 a gt Tegra K1 Embedded Platform Design Guide NVIDIA Table 4 Critical VDD CPU Switcher Components Recommendations Three Power Stages Components MFG MFG Part Qty Parameter Symbol Conditions Value Units PMIC Ctrlr AMS AS3722 1 Switching Frequency f 1 35 MHz 2 phase per Pwr AMS AS3728 3 Max Current l 2x10 A Stage Inductor TDK SPM4015 R68M 6 Inductance L 0 68 uH DC Resistance DCR 32 7 mQ Size LxWxH ee mm RMS Current Irms 40C rise 4 7 A Saturation Current Isat 30 drop 8 A Output Taiyo JMK212BJ476MG 4 per Power Data Sheet C 47 uF Capacitor Yuden T Stage Capacitance Size LxW 0805 mm Dielectric X5R Code Rated Voltage Vv 6 3 V Input Taiyo TMK316BJ106KD 4 per Power Data Sheet C 10 uF Capacitor Yuden TD Stage Capacitance Size LxW 3 5 mm Dielectric X5R Code Rated Voltage Vv 25 V Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDI
146. required at VPP_FUSE or the supply must provide an equivalent pull down A 0 1uF bypass capacitor is also recommended on this line Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 17 of 115 o Tegra K1 Embedded Platform Design Guide NVIDIA Figure 7 EFUSE Connection Example using Switched 1 8V Rail Tegra O VPP FUSE lt 10KQ max ott 2 7 Thermal Throttling SOC_THERM Tegra has external over current OC detection mechanisms to monitor devices outside Tegra such as PMIC battery and on board power sensors and provides OC alarm signals to the Tegra processor These are routed to SOC_THERM to throttle the system in these events and are available on the following pins Table 10 SOC_Therm Pin Usage SOC_THERM Pin Typical Usage KB_ROW15 Single Cell Design Battery Voltage VDD_SYS Monitor Dual Cell Design GPU Power Thermal Events GPIO_PKO Modem Power Report GPIO_PJ2 Power Monitor Output CLK_32K_OUT CPU Power Thermal Events may be covered by Power Monitor instead or in addition to this SOC_THERM 2 8 5V Input Considerations For designs that choose to use 5V input instead of 12V a power amp voltage monitor are highly recommended to monitor and alert the system software of potential issues that could cause the supply to drop below acceptable levels 2 9 Power Voltage Monitors 2 9 1 Power Monitor A Power Monitor such as sho
147. right 2014 2015 NVIDIA Corporation All rights reserved Page 109 of 115 o Tegra K1 Embedded Platform Design Guide NVIDIA Description Same Diff NA 100KQ pull downs on both DP AUX CHO N P lines near Tegra 100KQ pull down on DP AUX CHO P amp 100KO pull up on DP AUX CHO N near Connector Device DP HPD on VDDIO_HV block connects to HPD pin of eDP panel connector LVDSO_RSET connects to 1 0KQ 1 resistor to GND AVDD_LVDSO_IO connects to 1 05V supply AVDD_LVDSO_PLL connects to 3 3V supply LVDS LVDSO_TXD 2 0 _N P connect to Lanes 2 0 of LVDS panel connector LVDSO_TXD3_N P connect to Lane 3 of LVDS panel connector if required for 4 lane panel LVDSO_TXD4_N P connect to Clock Lane of LVDS panel connector KB_ROW6 used for TE Tearing Effect signal from display if supported LVDSO_RSET connects to 1 0KQ 1 resistor to GND AVDD_LVDSO_IO connects to 1 05V supply AVDD_LVDSO_PLL connects to 1 8V supply HDMI HDMI_TXCN P connect to CP CP pins on HDMI Connector See Note HDMI_TXD 2 0 N P connect to D 2 0 D 2 0 pins on HDMI Connector HDMI_RSET connects to 1kQ 1 resistor to GND HDMI_INT connects to HP DET pin on HDMI Connector through 1KQ series resistor AVDD_HDMI connects to 3 3V supply with Backdrive circuit Ensure supply for AVDD_HDMI can handle up to 100mA short term spike when display disconnected while Tegra device powere
148. s Note Max Frequency Data Rate 933 933 MHz Mbps Note 1 Switching Period T 1 T Topology T Branch Configuration Device Organization 2 load Reference Pplane GND Max PCB breakout length 6 35 mm Via proximity Signal to Reference lt 3 8 24 mm ps See Note 2 Capacitance Input Capacitance Min 40 75 1 2 pF Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 35 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Parameter Requirement Units Note Input Capacitance Delta All Ctrl Min 1 0 4 0 2 pF Impedance Spacing Trace Impedance 50 Q 15 Trace Spacing Microstrip Stripl 3x 2x dielectric Max Via Count Max Number of Vias Tx to Rx Per device Tx to all loads 4 8 Trace Lengths Delays T Topology Max Trace Length Delay PCB Main Trunk 42 86 270 mm ps Max Trace Length Delay Branch 14 29 90 mm ps Max Trace Length Delay Asymmetry for Branches 7 14 45 mm ps Absolute Skew Matching Max Trace Length Delay Skew Ctrl amp Clk PCB Main Trunk 12 7 80 mm ps Center Clk Branch A B Max Trace Length Delay Skew in Branch A B 7 14 45 mm ps Absolute Ay ae Length Delay Skew Any Ctrl to any other Ctrl within 25 4 160 mm ps Absolute bit half Note 1 Max frequency is target Actual frequency may depend on achievable PLL frequency used to c
149. s near Channel 0 Tegra DDR1_CLKP DIFF OUT Same as for CLKP CLKN above Differential Clock for Upper 32 bit Channel DDR1_CLKN Connect to CLK_P CLK_N pins of DRAM for Channel 1 Note The Tegra DRAM ball names may not correspond to the signal brought out on that ball Use the appropriate DRAM Pin Multiplexing tables included after each placement diagram to select the correct connections Miscellaneous DDR3L Guidelines Table 33 General DDR Guidelines Guideline Description Illustration Avoid routing over voids in the GND reference in the ball out area The figure to the right shows a GOOD example where the GND continues between the BGA balls with the DDR CLK routing staying over the GND Avoid the BAD example where the GND has a break and the signal passes over this break or Void This guideline should be used for DDR Clock and if possible Data DQS DM GOOD Net Dari Ck N BAD Separate critical DDR traces CLK DQ DQS DM VREF COMP etc from other signal traces or unrelated power areas or power supply components Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 38 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Table 34 DDR_COMP_PU PD Routing Requirements Parameter Requirement Units Note Reference plane GND if possible See note 1 Trace Impedance 50 Q 20 Max Trace Delay 19 120 mm
150. s two or more power areas use stitching capacitors S Placing one cap across two PWR areas near where traces cross area boundaries provides high frequency path for return current Cap value typically 0 1uF amp should ideally be within 0 1 of crossing Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 102 of 115 D Tegra K1 Embedded Platform Design Guide NVIDIA 9 0 Design Checklists The checklists below is intended to help ensure that the correct connections have been made in a design The check items describe connections for the various interfaces and the Same Diff NA column is intended to be used to indicate whether the design matches the each item description is different or is not applicable to the design Table 119 Clocking Checklist Description Same Diff NA XTAL_IN XTAL_OUT connect to terminals of external 12MHz crystal XTAL_IN amp XTAL_OUT have 12pF Load caps to GND AVDD_OSC connects to 1 8V CLK_32K_IN connected to PMU 32kHz output clock Table 120 Power Checklist Description Same Diff NA Control PWR_I2C_SCL SDA connect to PMU with 1Kohm pull up resistors to 1 8V_VDDIO PWR_INT_N connects to Interrupt pin on PMU CORE_PWR_REQ connects to CORE PWRREQ of PMU CPU_PWR_REQ connects to CPU_PWRREQ of PMU VDD_CPU_SENSE connects to FB SDO P pin of PMU GND_CPU_SENSE connects to FB SDO N pin
151. scervsansecessaccctssascteddectens 21 Sil OVOIVIOW aNG NANANA ANAN E 21 EO oe KS E chi sist A waa casaseatesscacaudeusideucsdaaususesdacuees saaudesssueiexeuabedersasbussvassuevseasecssseseies 23 3 2 1 Oscillator amp PLL Power Routing c ceeeceeeeeeeeeeeeeeeeeeeceaeecaeeeeaeeesaeseaeesseeesseeseaeesaeseaeesnaeesaeeseaeeseeeseaeesiaeseeeseeeeneeneaees 24 3 2 2 Additional PLL Power Noise Coupling Reduction Guidelines ecceeceeeseseneeseeeeeeeeeeeeeeeeseaeeseeseaeesieeeeeeseaeseneeeeaees 24 3 2 3 32 768kKHZ GIOCK Ka GANU NIAN seossaadydes sadecassdesdedes angcudehadacudedsahddalanatelaauducoadesiecabadacecaadceevasakeuasveagielgeeaiad 25 3 2 4 Oscillator Clock Stee ccscvadssisvigdl seis vessdeant heaved as a ied Heel TABANG RNGA AA a een ee 25 3 3 DRAM sissscttscsesccscesssceesencectsasccceessescsesaeeiesssasecdecaescaeccaseesescacesduaceessaduces sasansccessacacdssvassesseasensesabeusedvancesscaseer eatenests 27 Go cM DID RG AA AA cmc ee eo bn AA AA nce pan cates cnt teat AA AA AA AA 27 3 3 2 C0Mponen Nas aaa Aa ain aii DNA NE a E AEE NE NG 41 3 4 USB PC le SATA Interfaces NAGGING ANAN ANAND 41 eM AS AA AA 42 e AA A 48 Bi SATA EPE A E E E A E EERE E E E AYA A E A E E 51 3 44 AA 54 3 5 DISPlay eee 56 SARIE D a A D E A ET E T EAE E EE E E T EE 56 eKA IDS E E A A E E E aa sags A A E 62 SASE H m D T E E ET E A E A EE N 65 3 6 Video Input Interfaces maana AA 69 3 631 MIPIGSI Gamera pinana lana N nested a nd
152. terial requirements None Design Guide Line Width DIFF Line DIFF Line SE Impedance DIFF Impedance T TOP Signal 1 2 oz loo SO 0 401 0160 0261 50 0o 0 099 0 350 0 449 50 q8 CE AA a 015 a 4 10 131 0 170 0 301 44 TJ 80 Signal 1 oz Signal 1 oz 6 BOTTOM Signal 1 2 oz Note Impedance tolerances are 15 unless otherwise specified Not all line widths listed may be present on a particular layer Overall board thickness is 10 5 Individual layer thickness is 10 2 Dielectric means PrePreg Core or Core PrePreg o If unspecified then preferred copper fill is 1 2 oz copper for signal layers and 1 oz copper for planes S See FAB Drawing for additional information Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 91 of 115 Tegra K1 Embedded Platform Kg Design Guide NVIDIA 6 2 Breakout Examples Several of the main critical power rails are highlighted as follows VDD CPU Red VDD GPU _ VDD CORE Orange VDDIO DDR DRAM IO Rail GND Green Figure 43 Jap ati Breakout ZA va i be t 7 i INI NA JO kali iil a bi ee pau sill Figure 44 Layer 2 Breakout Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 92 of 115 o Tegra K1 Embedded Platform Design Guide NVIDIA
153. ty Signal to reference lt 3 8 24 mm ps See Note 1 Trace spacing Microstrip Striplit 4x 3x dielectric See Note 2 Max Trace Delay 1700 10 ps in See Note 3 Max Trace Intra pair Skew 5ps ps C all discontinuities amp overall See ote Note WN Table 113 Thermal D Up to 4 signal vias can share a single GND return via Keep switch mode supply as distant as possible Include Package tt PCB routing delays for Max trace delays and max trace delay skew parameters iode Signal Connections Ball Name Type Termination Description THERMD_P N_ DIFF IN 1000pF cap between signals amp 1000 Series resistors Thermal Diode Connect THERMD_P N pins to sensor D GEN1_I2C_SC OD Pull up resistor to VDDIO_UART See I2C 12C Clock tt Data Connect to I2C interface on L OD section for appropriate values based on Thermal Sensor for configuration and to read GEN1 12C SD frequency tt load temperature data A ALERT OD 10KO to GPIO rail depends on GPIO used Thermal Alert Notification Connect to appropriate Sensor not required in Phone case using GPIO on Tegra GPIO X6 AUD THERM OD Critical Thermal Indication Connect to PMU or Sensor other circuitry that will power off device in case of critical Thermal issue Table 114 Thermal Sensor Interface Package Delays Signal Name Ball Pkg Delay ps Signal Name Ball
154. und Interface KBC Keyboard Controller LCD Liquid Crystal Display LDO Low Dropout voltage regulator LVDS Low Voltage Differential Signaling Interface MMC Multi Media Card High Speed MMC PCle Peripheral Component Interconnect Express interface PCM Pulse Code Modulation PHY Physical Interface i e USB PHY PMC Power Management Controller PMU Power Management Unit RF Radio Frequency RTC Real Time Clock SATA Serial AT Attachment interface SDIO Secure Digital 1 0 Interface SPI Serial Peripheral Interface UART Universal Asynchronous Receiver Transmitter ULPI UTMI Low Pin count Interface USB Universal Serial Bus WLAN Wireless Local Area Network Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 5 of 115 A NVIDIA 1 2 Overview Tegra K1 Embedded Platform Design Guide The Jetson platform is based on the NVIDIA Tegra K1 application processor Tegra K1 processors integrate a power optimized version of the same Kepler GPU architecture that powers the highest performing graphics cards and systems in the world By optimizing this industry acclaimed graphics architecture Tegra K1 processors are first to enable features like OpenGL 4 4 DirectX 11 1 and CUDA GPGPU for extremely low power use cases This high performance applications processor coupled with the unique Tegra 4 PLUS 1 architecture DirectTouch and PRISM2 technologies is the foundatio
155. up to Fast Mode Plus speeds Avoid routing I2C signals near noisy traces supplies or components such as a switching power regulator No requirement for decoupling caps for PWR reference Table 104 12C Signal Connections Function Name Type Termination Description PWR 12C SCL SD OD Pull up see note 1 to 1 8V Power 12C Clock tt Data Connect to CLK tt Data pins of any A devices GEN1 12C SCL S OD Pull up see note 1 to1 8V orup Generic I2C 1 Clock amp Data Connect to CLK amp Data pins of DA to 3 3V any devices GEN2 12C SCL S OD Pull up see note 1 to 1 8V orup Generic I2C 2 Clock amp Data Connect to CLK amp Data pins of DA to 3 3V any devices CAM 12C SCL SD OD Pull up see note 1 to 1 8V orup Camera I2C Clock amp Data Connect to CLK amp Data pins of any A to 3 3V devices DDC SCL SDA OD Pull up see note 1 to VDDIO_HV DDC I2C 2 Clock tt Data Connect to DDC CLK amp Data pins of level 2 8V 3 3V See note 2 if any devices level shifters used 5V if direct to HDMI connector 12C6 12C 6 interface on DP AUX CHO P N pins See eDP connections Note 1 To determine pull up resistor values for SCL SDA for various loading conditions refer to section 7 1 of the NXP Philips 12C bus specification amp user manual Version 3 1KQ pull up resistors recommended for the most common loading conditions for Standard Mode Fast Mode and Fast Plus Mode and 7500 pull up resistors for High S
156. ure 17 DDR3L 4x16 Address A 5 3 for 32 bit partitions 1 0 1 T Topology Branch DDR3L 1 or 3 Main trunk Tegra Branch DDR3L 2 or 4 Table 27 DDR3L 4x16 Address A 5 3 for 32 bit partitions 1 0 Signal Routing Requirements Parameter Requirement Units Note Max Frequency Data Rate 466 5 466 5 MHz Mbps Note 1 Switching Period T 2 T Topology T Branch Configuration Device Organization 2 load Reference Pplane GND Max PCB breakout length 6 35 mm Via proximity Signal to Reference lt 3 8 24 mm ps See Note 2 Capacitance Input Capacitance Min N 0 75 1 2 pF Input Capacitance Delta All Add Cmd Min N 0 4 0 4 pF Impedance Spacing Trace Impedance 50 Q 15 Trace Spacing Microstrip Stripl 3x 2x dielectric Max Via Count Max Number of Vias Tx to Rx Per device Tx to all loads 4 8 Trace Lengths Delays Max Trace Length Delay PCB Main Trunk 42 86 270 mm ps Max Trace Length Delay Branch 14 29 90 mm ps Max Trace Length Delay Asymmetry for Branch 7 17 45 mm ps Absolute Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 34 of 115 A Tegra K1 Embedded Platform Design Guide NVIDIA Parameter Requirement Units Note Skew Matching Max Trace Length Delay Skew Addr amp Clk PCB Main Trunk 12 7 80 m
157. ute Sense lines directly under or over noisy power rails Route Sense lines with GND reference plane If possible route GND traces on either side of the Sense pairs Table 9 General Power Sense Routing Guidelines Parameter Requirement Note Topology Point to Point Number of loads 1 load Reference plane GND where possible Trace Routing Route as pseudo differential pair with min 4 4 4 trace widths spacing Max Trace Delay As short as possible Trace Spacing to other nets 3x dielectric Note Strongly recommend review of sense line routing amp other critical items related to VDD_CPU GPU CORE supplies by PMU Regulator vendor 2 6 VPP FUSE Supply Designs must provide a way to supply a 1 8V power source to the VPP_FUSE pin on Tegra to allow fuses to be burned unless fuses are only to be burned before assembly This supply is only required when fuses are burned and should be powered off during normal operation VPP_FUSE must be powered OFF when Tegra is in Deep Sleep mode The supply for VPP_FUSE can be provided using one of several options Test point for external supply does not support Over the Air updates Output of on board LDO or Switched 1 8V supply controlled by a Tegra GPIO Output of PMU controlled by PWR_I2C from Tegra The power source must provide a nominal voltage of 1 8V and be able to supply a minimum of 120mA When not powered either a pull down resistor lt 10KQ is
158. wn below is highly recommended where Tegra is used in a 5V design Figure 8 Typical Power Monitor Connections Sense 7 Resistors Power Monitor VDD BAT CHG P pamana a l VODED 1V5 VINIP E Si gt f Battery Monitor GEN2 2C SCL WNN Ng VDD BAT CHG M i Tegra Gene pe soba SCL BAI OIG iy GEN2_l2C 2_12C_SDA i GH PSDA P VDD_SYS_CPU_P aNg Tegra PG 0G NM iQ VDD USBO 5VO Monitor Bp lt CRIT VIN2N GG USB VBUS Supply GPIO_PJ2 TA l VDD_SYS_CPU_M iy ner eT VDD_SYS_DDR GPU_P i gt LL i VDD SYS MDM Monitor H Modem Supply Source VAEN l VDD_SYS_DDR GPU_M iy kana Note In order to support short and long term average power limiting thru the Power Monitor the CRIT tt WARN pins should be tied together and routed to the SOC THERM input GPIO PJ2 Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 18 of 115 o Tegra K1 Embedded Platform Design Guide NVIDIA 2 9 2 Voltage Monitor For 5V input design a voltage monitor should be connected to the VSYS rail that supplies the system PMIC and other components requiring the VSYS level input This device will generate an alert quickly if the rail droops below an acceptable level The voltage monitor circuit is implemented with a fast voltage comparator supplied by VDD SYS Battery Charger level with a 1 8V VDD_1V8 reference common with the Tegra IO domain
159. z i 4 7uF 4530 1 H 2 8V_RUN_CAM_AF 1200 100MHz i 4 7uF 49 90 1 AA T CAM 1 8V_RUN_CAM 1200 100MHz i 4 7uF 1 2V_RUN_CAM_FRONT Camera 2 1 2V_RUN_AVDD 1200 100MHz i 4 7uF 2 8V_RUN_CAM 120Q 100MHz CSI 4 7uF x1 8V RUN CAM 120Q 100MHz l 4 7uF F 1 2V RUN AVDD ngi Available for an additional CSI x4 interface if not used for a display Note 1 Filters on CSI MCLK amp I2C signals are not recommended If EMI is a concern other solutions PCB GND layers external shielding etc is preferred If EMI devices are used they must be tuned such that the signals meet the timing amp electrical requirements of the related specification for the frequencies to be supported 2 If Tegra is providing flash control as shown above GPIO PBB 4 must be used 3 Care must be taken to ensure any ESD and or EMI solution must support the frequencies required in the design 4 A privacy LED may be a requirement in some designs Ensure the LED is on whenever the camera is active such that this cannot be disabled through software means 5 See the Power Decoupling Guidelines section for power rail decoupling and filter requirements Tegra K1 DG 07508 001v03 Copyright 2014 2015 NVIDIA Corporation All rights reserved Page 69 of 115 A Tegra K1 Embedded Platform Design Guide

Tegra K1 Embedded Platform Design Guide

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