32-Channel 12-bit Analog Output Board with Built-in
Contents
1. 14 2 124 26 IO TVAZ692I 8502 1449 OUTPUT SELECT LINES DAC OUTPUT 50 to 52 ENB 3 STRB OUT 31 STRB OUT 23 H STRB OUT 15H STRB OUT 07 H SO to S2 1 to 8 MUX ENB DISTR CH 00 to CH 31 ONE OF 32 OUTPUT BUFFERS uonnqrnsiq mdmo So euy 6 1814 8502 1449 uoypsadg fo 09 4224 II t FROM ANALOG DISTRIBUTION BUFFERS S amp H AMP BIT MONITOR SELECT SWITCH ONE OF 32 CHANNELS P3 Axx Cxx SOYSUMS pue s1ogng mdmo p p 101814 4 12 Built in Test BIT Multiplexers and ADC Logic The signal routing paths and multiplexers involved in the board s loopback testing are shown in Figure 4 5 on page 4 13 The 32 analog outputs are switched by the output monitor demultiplexer onto a single line This line is connected to a buffer and then to the on board Analog to Digital Converter ADC This arrangement permits any one of the analog outputs to be tested by the ADC It also verifies the operation of the analog input multiplexers by exercising them with known signal levels By routing the analog outputs through the test demultiplexers all of the active components on the board are exercised in a loopback arrangement The controlling processor can perform a loopback test in either the on line or off line mode by sending a voltage level code to a specific output channel and then verifying that the ADC produces th2. SHORT IO vmic4132 base address vmic4132 gt csr LED OFF OUTPUTS ONLINE init dac outputs board id read id vmic4132 read board id register status read csr vmic4132 read control status register write dac 0 0x100 vmic4132 write dac channel 0 with 100 hex init adc control word and read back dac output with adc converter adc cword data in LED OFF START CONVERT OUTPUTS ONLINE START SETTLING read 0 cword vmic4132 data in read adc 0 adc cword vmic4132 end main 2058 Chapter 3 Programming 3 13 xx ma 4132 function primitives word read_id vmic4132_reg board return gt word read_csr vmic4132_reg board return board gt csr void write_dac word chan word data vmic4132_reg board board gt dac chan data word read adc word chan word ctrl vmic4132_reg board board gt csr ctrlt chan while board gt csr amp NEW DATA READY test new data ready bit return gt IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT User s Manual December 2001 2058 Chapter Theory of Operation 4 This chapter describes the internal organization of the Analog Output Board reviews the general principles of operation and is divided into the following sections Internal Functional Organization
3. 1 2 FS 2 5000 V 5 0000 V 1111 1100 0000 0000 C00 3 4 FS 3 7500 V 7 5000 V 1111 1010 0000 0000 A00 FS 1 LSB 4 9976 V 9 9951 V 1111 1000 0000 0001 801 FS 5 0000 V 10 000 V 1111 1000 0000 0000 800 STRAIGHT BINARY Vo Vgsg D1 4096 D1 Dec equiv of HEX value OFFSET BINARY Vo D1 4096 Vise 2 D2 Dec equiv of HEX value 2 s COMPLEMENT Vo Vrsr D2 4096 Vesp 2 D2 Dec equiv of HEX value 800 Zero binary or extended sign 2 s comp Exclusive OR d with Chapter 3 Programming 3 12 For any offset binary converter output code BIPOLAR RANGE the associated output voltage is obtained with the expressions OUTPUT Volts E 2 Ej X OUTPUT DATA IN DECIMAL 4096 FSR The output voltage for a straight binary code UNIPOLAR RANGE is OUTPUT Volts E X OUTPUT DATA IN DECIMAL 4096 Where is the full scale range voltage E g E 10 V for the 5 V range For example the output voltage for a HEX value of 51A is found like this 1 Convert 51A HEX to its decimal equivalent which is 1306 2 Identify the Range you are using for example 5 V This range uses the bipolar equation with E 10 V 3 Compute the result by substituting these numbers in the equation OUTPUT Volts 10 2 10 x 1306 4096 5 10 x 32 2 1 81 V IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 20
4. 2 13 2 14 Figure 2 7 P3 Connector Pinout lt HS HS N N N N N NN G O O O O Q O CO nm 6 00000000000000000000000000000000 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O NO Q O PC Board M 1C697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT User s Manual December 2001 GFK 2058 Chapter Programming 3 This chapter contains programming instructions for the Analog Output Board and is divided into the following sections Introduction to Controlling the Analog Output Board Control and Status Register Descriptions nitialization Controlling the Analog Outputs Testing the Analog Output Channels BIT Program Example 2058 3 1 3 2 Introduction to Controlling the Analog Output Board Communication with the Analog Output AO Board takes place through 64 contiguous 16 bit register locations mapped into the VMEbus short I O address space The short I O address space consists of all locations within the address range from NNNN0000 HEX to NNNNFFFF The functions of the board s registers are summarized in Table 3 1 on page 3 5 These functions will be discussed in more detail later in this section The base address of the board holds the Board Identification Register It is a read only register t
5. VMEbus Interface Channel Control Logic Analog Outputs Analog Output Buffers and Switches Data RAM and Refresh Logic Built in Test BIT Multiplexers and ADC Logic Built in Power Converter 2058 4 1 4 2 Internal Functional Organization The Analog Output Board is designed to operate in a standard VMEbus system The board contains a 12 bit Digital to Analog Converter DAC dedicated on board registers to store the output data sample and hold buffers S amp H to place the voltage on the cable and loopback analog switches to support Built in Test features The BIT uses an on board Analog to Digital Converter ADC therefore no additional equipment is needed to test this board The Analog Output Board is a flexible I O element in a VMEbus system which offers Built in Test and off line operating features not found in many other products The Analog Output Board is divided into the following functional categories as illustrated in Figure 1 1 on page 1 3 All of these functions will be discussed in detail in this section of the manual VMEbus Interface e Analog Outputs DAC and Analog Distributor e Analog Output Buffers and Switches e Data RAM and Refresh Logic e Multiplexers and ADC Logic Power Converter IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 VMEbus Interface 2058 board s Analog Outp
6. implied or statutory with respect to and assumes no responsibility for the accuracy completeness sufficiency or usefulness of the information contained herein No warranties of merchantability or fitness for purpose shall apply The following are trademarks of GE Fanuc Automation North America Inc Alarm Master Genius PROMACRO Series Six CIMPLICITY Helpmate PowerMotion Series Three CIMPLICITY 90 ADS Logicmaster PowerTRAC VersaMax CIMSTAR Modelmaster Series 90 VersaPro Field Control Motion Mate Series Five VuMaster GEnet ProLoop Series One Workmaster Copyright 2001 GE Fanuc Automation North America Inc All Rights Reserved Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 GFK 2058 Contents Introduction Description and Specifications 1 1 Reference Material and Other GE Fanuc 1 1 General Description eot eI usss eb rte Deci eerie 1 2 Functional Description l u a a ene rennen eerte nnne 1 3 Safety Summary 1 4 Configuration and Installation 2 1 Physical Installati n 2 2 Before Applying Power Checklist 2 3 Base Address 2 4 o m
7. Board analog network is supplied by two DC to DC converters shown in Figure 4 6 below These converters transform the 5 V logic power into regulated and isolated 15 VDC power with a load capacity of approximately 600 mA on each 15 V bus Thus the user only needs a 5 V power supply when using this board Figure 4 6 DC to DC Converters 4 14 IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 Chapter Maintenance 5 This chapter provides information relative to the care and maintenance of the Analog Output Board product If the product malfunctions verify the following e Software e System configuration e Electrical connections e Jumper or configuration options e Boards fully inserted into their proper connector location Connector pins are clean and free from contamination e components of adjacent boards are disturbed when inserting or removing the board from the VMEbus card cage e Quality of cables and I O connections User level repairs are not recommended Contact GE Fanuc for a Return Material Authorization RMA Number This RMA Number must be obtained prior to any return 2058 5 1
8. accessed During ADC conversions the refresh logic is disabled This is to prevent the digital noise generated by this logic from injecting errors in the loopback data When the ADC is converting a voltage 15 usec maximum delay will be added to the output update time IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 8502 1449 019 90 fo Koay p 4214 Lh TP2 12 OUTPUT ANALOG gt DATA STATIC DISTRIBUTOR 10811 to IDBOO Pcie 21807 OMUOD So euy c p enar 5 CTRL LINES RAM A4 to AO 7 DAC CTRL REGD A6 to 1 AND REFRESH 6 LOGIC BD CTRL LINES Analog Output Buffers and Switches 4 8 Voltage levels processed by the analog distributor and stored by the sample and hold caps are buffered and then switched to the P3 connector for routing through the system I O cables The output buffers are low leakage precision operational amplifiers which can supply 10 mA of drive current over the full available output voltage range of 10 V These buffers can withstand sustained short circuits to ground without damage Figure 4 4 on page 4 11 shows the S amp H buffer with its protection circuit and the switches used to control the output connector and the loopback test voltage source The output switches can disconnect the output buffers from P3 for off line testing and for low impedance single point analog I O system ap
9. data is in offset binary form When a zero is written here the data is in two s complement form Outputs On Line Control When this bit is a one the output buffers are driving the cable and loopback buffers monitor the P3 pins When it is a zero the outputs are disconnected from the cable and the loopback buffers monitor the output amps Not used Not Used Fast Refresh This speeds up the DAC control logic when a one is written here so the outputs get updated faster Not Used GFK 2058 User s Manual December 2001 006 Start Settling or Settling Busy Writing a one here and at D13 begins a loopback conversion Reading a zero tells the host that the signal settling time is done Bit 005 Scan Halt Writing a one here will stop the output sequencer and disable the A D converter This bit must be cleared before normal operations can begin 004 MUX A4 Loopback input channel select multiplexer control line Bit D03 MUX A3 Loopback input channel select multiplexer control line Bit D02 MUX A2 Loopback input channel select multiplexer control line Bit 001 MUX A1 Loopback input channel select multiplexer control line Bit DOO MUX AQ Loopback input channel select multiplexer control line The MUX signals are address lines A decoder takes the state of these lines and selects the loopback buffer to convert 2058 Chapter 3 Programming 3 7 Controlli
10. located at an offset of 02 from the base address of the board Chapter 4 Theory of Operation 4 3 4 4 The interface logic determines the bus control of the board but the CSR contains the board level operating controls and status flags for the system Static controls such as the LED ON line are stored in the Control Register and are used primarily to establish the operating mode of the board Status flags such as NEW DATA RDY necessary for monitoring and controlling the analog input multiplexer and the ADC are read through the Status Register The Control and Status Registers are referred to collectively as the Control and Status Register or CSR since they are at the same address The WRITE signal determines which one is accessed while most of the Control Register outputs can be monitored directly through the Status Register In the CSR three of the control lines are strobes These signals are START CONV H SHORT SETTLING H and START SETTLING H They are valid only during the write operation to the CSR Once written these signals become status flags for the Analog to Digital Converter The host CPU can monitor these lines to determine when the ADC is done and data is ready to be read Each of the 32 analog output channels is controlled by writing a 12 bit right justified data word into a dedicated 16 bit read write register The 32 analog Output Control Registers constitute the VME port of a 32 word dual port memory The other memory po
11. will be lost After the board decides it is to respond the following three groups of VMEbus signals control the board Data Bus lines DOO to D15 e Address lines A01 A02 A03 A04 05 and A06 e Bus Control Signals 1l WRITE 2 DS0 and DS1 3 SYS CLK Data Bus lines are bi directional and move data to or from the board through a pair of 8 bit data transceivers They are controlled by board select the WRITE line and the data strobes 050 and DS1 The data transceivers serve as a buffer between the internal data bus which interconnects all data devices on the board and the VMEbus Although the board will respond to byte operations word transfers are recommended Byte transfers can cause erratic behavior in the outputs Address lines A01 through A06 map the 64 Data Registers into a 128 byte range within the VMEbus address space Chapter 3 The control signals determine whether data is to be moved to the board a write cycle or from the board a read cycle provide the necessary data strobes DSO DS1 and supply a 16 MHz clock SYS CLK for use by the on board timers However SYS RESET input overrides all of the board s functions resets all the timers and clears all of the flags in the CSR A Board ID Register located at the base address of the board has a fixed value of 17 HEX in the even byte location This register can be used by automatic system configuration software to identify the board in a system The CSR is
12. 0 0000 0000 C00 1 2 FS 2 5000 V 5 0000 V 0000 1000 0000 0000 800 1 4 FS 1 2500 V 2 5000 V 0000 0100 0000 0000 400 1 LSB 0 0012 V 0 0024 V 0000 0000 0000 0001 001 ZERO 0 0000 V 0 0000 V 0000 0000 0000 0000 000 IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 2058 BIPOLAR RANGE OFFSET BINARY INPUT 5 V 10 V D15 D00 HEX VEsR 10 v VEsr 20 v FS 1 LSB 4 9976 V 9 9951 V 0000 1111 1111 1111 FFF 3 4 FS 3 7500 V 7 5000 V 0000 1110 0000 0000 E00 1 2 FS 2 5000 V 5 0000 V 0000 1100 0000 0000 C00 1 4 FS 1 2500 V 2 5000 V 0000 1010 0000 0000 A00 1 LSB 0 0024 V 0 0048 V 0000 1000 0000 0001 801 ZERO 0 0000 V 0 0000 V 0000 1000 0000 0000 800 1 4 FS 1 2500 V 2 5000 V 0000 0110 0000 0000 600 1 2 FS 2 5000 V 5 0000 V 0000 0100 0000 0000 400 3 4 FS 3 7500 V 7 5000 V 0000 0010 0000 0000 200 FS 1 LSB 4 9976 V 9 9951 V 0000 0000 0000 0001 001 FS 5 0000 V 10 000 V 0000 0000 0000 0000 000 BIPOLAR RANGE 2 s COMPLEMENT INPUT 5 V 10 V D15 D00 HEX VEsR 10 v VEsr 20 v FS 1 LSB 4 9976 V 9 9951 V 0000 0111 1111 1111 3 4 FS 3 7500 V 7 5000 V 0000 0110 0000 0000 600 1 2 FS 2 5000 V 5 0000 V 0000 0100 0000 0000 400 1 4 FS 1 2500 V 2 5000 V 0000 0010 0000 0000 200 1 LSB 0 0024 0 0048 V 0000 0000 0000 0001 001 ZERO 0 0000 V 0 0000 V 0000 0000 0000 0000 000 1 4 FS 1 2500 V 2 5000 V 1111 1110 0000 0000 E00
13. 10 As delivered from the factory all calibration adjustments are sealed against accidental movement However the seals are easily broken for recalibration All adjustments should be resealed with a suitable fast curing sealing compound after recalibration has been completed Note Do not install or remove this board with power applied to the system Equipment Required Digital Voltmeter DVM A meter with 1 0000 VDC and 10 000 VDC ranges 5 or more digits accuracy of 0 005 percent and 10 MQ minimum input impedance e Chassis VMEbus backplane or equivalent with 71 and J2 connectors a VMEbus master controller a 5 VDC 0 25 VDC power supply and one slot allocated for testing the Analog Output Board e Extender board One VMEbus extender board Test cables Test cables for the equipment listed above 2058 Chapter 2 Configuration and Installation 2 9 2 10 Figure 2 6 Calibration and Test Points IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT User s Manual December 2001 GFK 2058 Analog Output Calibration Procedure 1 9 Install the Analog Output Board on the extender board in the VMEbus backplane Remove any jumper from J1 This sets the outputs to 20 V full scale Place the jumper at J2 to the 2 3 position This is the bipolar setting Apply power to the backplane and allow a minimum ten minute warm up time before proceeding Connect the dig
14. 25 74 D A OUTPUT 26 READ WRITE 76 D A OUTPUT 27 READ WRITE 78 D A OUTPUT 28 D A OUTPUT 29 READ WRITE 7 D A OUTPUT 30 READ WRITE TE D A OUTPUT 31 READ WRITE Chapter 3 Programming 3 5 Table 3 2 CSR Bit Definitions MSB Bit D15 Bit D14 Bit D13 Bit D12 Bit D11 Bit D10 Bit D09 Bit D08 Short Start a Settling LED Conversion Two s Outputs Not Not Fast or New Control 2 Complement Oud ane Used Used Refresh Data Converter Control Control Rdy Busy LSB Bit07 Bit D06 Bit D05 Bit D04 Bit D02 Bit 001 Bit DOO Start Not Settling Scan or MUX A4 MUX A3 MUX A2 MUX Al MUX A0 Used Halt Settling Busy Control and Status Register Bit Definitions 3 6 Bit D15 Bit D14 Bit D13 Bit D12 Bit D11 Bit D10 Bit D09 Bit 008 Bit D07 IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT Short Settling or New Data Writing a one here reduces the time assigned for loopback settling from 5 to 3 msec Reading a one here indicates that loopback data is ready for the host to read LED Control This bit turns the LED ON with a logic zero and OFF with a logic one Start a Conversion or Converter Busy Writing a one here and at D06 begins a loopback conversion Reading a zero tells the host that a conversion is done Two s Complement Control When a one is written here the
15. 58 User s Manual December 2001 Program Example The following is a sample program to perform some simple board operations The program is written in C AU VMIVME 4132 sample code header file E typedef unsigned short word data type of word define VME SHORT IO Oxfbff0000 Force Cpu short io define vmic4132 base address 0x0000 Jumper Field J5 6 J7 struct vmivme4132 word bid board ID register word csr control status register word adc ADC converter data register word reserved 29 unused reserved word dac 32 DAC channels 0 31 typedef struct vmivme4132 vmic4132_reg define SHORT_SETTLING 0 8000 CSR control bits write define LED_OFF 0x4000 define START_CONVERT 0 2000 define TWOS COMPLEMENTOx1000 0 1000 define OUTPUTS ONLINE 0x0800 define FAST REFRESH 0x0100 define START SETTLING 0x0040 define SCAN HALT 0x0020 define NEW DATA READY 0x8000 CSR status bits read define CONVERTER BUSY 0x2000 define SETTLING BUSY 0x0040 VMIVME 4132 sample code include Weal 32h 4132 function declarations word read id vmic4132 reg board word read csr vmic4132 reg board void write dac word chan word data vmic4132 reg board word read adc chan word ctrl vmic4132 reg board main word board id status adc cword data in init pointer to 4132 board vmic4132 reg vmic4132 vmic4132 vmic4132 reg
16. AST REFRESH MODE reduces the accuracy of the outputs They are not given enough time to settle to their most accurate levels IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 Testing the Analog Output Channels BIT Built in Test BIT provisions provide loopback testing of the outputs These capabilities permit self contained board level verification of performance The testing is controlled by seven bits in the CSR They are the MUX Address lines the start conversion and start settling bits The ON LINE signal controls the source of the test voltage The two s complement bit dictates the format of the data BIT is available at any time The user picks a channel to monitor and orders a conversion After 5 msec the ADC is read and the read data is compared to the written data to determine the health of the channel If an error is detected the front panel LED can be used to locate the board in a system for troubleshooting Loopback Testing of the Outputs The five least significant bits in the CSR DOO through D04 and bit D11 are used to select the source of the voltage used in the loopback BIT test DOO through D04 are the loopback multiplexer select lines MUX AO through MUX A4 They select the input to be tested Bit D11 the outputs on line control selects where the input sample will be made When this bit is low the loopback test buffers monitor the analog output b
17. Board with Built in Test BIT GFK 2058 User s Manual December 2001 Connector Descriptions Two 96 pin DIN connectors P1 and P2 Figure 2 1 on page 2 5 provide the VMEbus connections to the Analog Output Board P1 contains the address data and control lines and all additional signals necessary to control the VMEbus functions related to the board P2 provides some additional power connections for the board A 64 pin DIN connector P3 is used to connect the analog outputs to the user s system The orientation of the P3 connector is shown in Figure 2 7 on page 2 14 and the signal assignments are listed in Table 2 2 below A twisted pair ribbon cable with an overall shield is recommended for applications involving low level signals in environments with a high degree of electrical noise Table 2 2 P3 Pin Channel Assignments Pin No Row A Assignment Row C Assignment 1 00 GND 2 CH01 GND 3 CH02 GND 4 CH03 GND 5 CH04 GND 6 CH05 GND 7 CH06 GND 8 CH07 GND 9 CH08 GND 10 CH09 GND 11 CH10 GND 12 CH11 GND 13 CH12 GND 14 CH13 GND 15 CH14 GND 16 CH15 GND 17 CH16 GND 18 CH17 GND 19 CH18 GND 20 CH19 GND 21 CH20 GND 22 CH21 GND 23 CH22 GND 24 CH23 GND 25 CH24 GND 26 CH25 GND 27 CH26 GND 28 CH27 GND 29 CH28 GND 30 CH29 GND 31 CH30 GND 32 CH31 GND 2058 Chapter 2 Configuration and Installation
18. E 2 9 Connector Descriptions 2 13 Programming eeeteeeeie ee eo en onore aee eo eS eere sare Re ons Dean Re eene ess 3 1 Introduction to Controlling the Analog Output Board 3 2 Control and Status Register 6561 0 5 3 3 3 4 Controlling the Analog Outputs 3 8 Testing the Analog Output Channels 3 9 Program Example 3 13 Theory of OPerathOMcieciseesssinsceccersoacssaeressscscencevousecssessesnesconstssencssescessncesse 4 1 Internal Functional Organization 4 2 VMEb s ee prr asqa e rere tn EH eig 4 3 Analog Outputs sae i Ice AS Bat ee ete este iet Gaeta 4 6 Analog Output Buffers and 5 4 8 Data RAM and Refresh 4 0 Built in Test BIT Multiplexers and ADC Logic 4 12 Built in Power Converter 4 14 T 5 1 iii Chapter I
19. FANUC GE Fanuc Automation Programmable Control Products IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT User s Manual GFK 2058 514 000436 000 A December 2001 GFL 002 Warnings Cautions and Notes as Used in this Publication Warning Warning notices are used in this publication to emphasize that hazardous voltages currents temperatures or other conditions that could cause personal injury exist in this equipment or may be associated with its use In situations where inattention could cause either personal injury or damage to equipment a Warning notice is used Caution Caution notices are used where equipment might be damaged if care is not taken Note Notes merely call attention to information that is especially significant to understanding and operating the equipment This document is based on information available at the time of its publication While efforts have been made to be accurate the information contained herein does not purport to cover all details or variations in hardware or software nor to provide for every possible contingency in connection with installation operation or maintenance Features may be described herein which are not present in all hardware and software systems GE Fanuc Automation assumes no obligation of notice to holders of this document with respect to changes subsequently made GE Fanuc Automation makes no representation or warranty expressed
20. POLARITY INSTALLED AT 2 3 OUTPUT VOLTAGE RANGE OMITTED IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 2058 Figure 2 1 Jumper and Calibration Point Locations Chapter 2 Configuration and Installation 2 5 Board Address Selection J5 and J7 Jumpers J5 and J7 permit the Analog Output Board to be located on any 64 byte boundary within the short I O address space The short I O address space consists of all the addresses between NNNN0000 HEX and NNNNFFFF HEX The Analog Output Board address is defined by nine lines address bits A07 through A15 Six additional lines are used for programming the on board registers see Chapter 3 for more details In programming the board s base address an installed jumper equals zero 0 and an omitted jumper equals one 1 Figure 2 2 below shows an example base address as well as the factory configured base address Figure 2 2 Base Address Selection A07 A07 J7 J7 A15 A08 A15 A08 JE 9 1 2 2 OOO 2 OOO Example Base Address Factory Configuration NNNN8E80 HEX Board Modifier Selection J6 The I O access mode is programmed by selecting the responding state of the address modifier AM2 with jumper J6 Short supervisory access is the factory configuration and is selected by omitting the jumper Short nonprivileged access is selected by installing the jumper Figure 2 3 below shows the jumper location for th
21. Thus a single write to the CSR can start a conversion Once started the user simply waits 5 msec and then reads the ADC The NEW DATA RDY bit can be used as a pass or fail indicator Polling this bit or any other bit on the board will degrade the loopback readings For example to convert the signal of Channel 0 with the outputs on line using offset binary data format write 7840 HEX to the CSR The low 5 bits select the output channel to monitor Channel 0 in this case The upper 4 bits start the conversion and select the data format Now wait 5 msec to give the multiplexers time to settle In this time the host can do whatever it wants The ADC is read next via the Converter Data Register CDR To check Channel 12 write 784C HEX to the CSR The CDR is a 16 bit read only register at relative address 04 HEX It is used to store the ADC data Data in this register is 12 bits right justified D12 through D15 are always zero in the binary data format and are sign extensions in the two s complement data format The data format depends upon the state of the TWO s COMP L control bit in the CSR Converter output codes that are produced at major points within the full scale ranges shown are summarized in Table 3 4 Table 3 4 Data Codes for Some Selected Output Voltages UNIPOLAR RANGE STRAIGHT BINARY INPUT 5 V 10 V D15 DOO HEX Vrsn s v VFSR 10 v FS 1 LSB 4 9988 V 9 9976 V 0000 1111 1111 1111 FFF 3 4 FS 3 7500 V 7 5000 V 0000 110
22. alog output channels These registers begin at offset address 40 HEX and stop at offset 7E HEX Write the 16 bit value 7840 HEX to the CSR at offset address 02 HEX While reading the ADC a 16 bit word at offset address 04 HEX adjust R15 BIPOLAR OFFSET for a reading of 0000 0001 HEX Write the 16 bit value OFFF HEX to all of the analog output channels These registers begin at offset address 40 HEX and stop at offset 7E HEX While reading the ADC a 16 bit word at offset address 04 HEX adjust R14 GAIN ADJ for an ADC indication that alternates between OFFE and OFFF HEX Repeat steps d through h until no further adjustments are required If the board is to be used in the Unipolar mode perform steps 10 11 12 and 13 Move jumper J3 to the 2 3 position UNIPOLAR OPERATION 11 Write the 16 bit value 0000 HEX to all of the output channels These registers begin at offset 40 HEX and end at offset 7E HEX 12 Write the 16 bit value 7840 HEX to the CSR at offset address 02 HEX 13 While reading the ADC adjust R13 UNIPOLAR ZERO ADJUST for an ADC indication of 0000 x1 HEX 14 For optimum performance the gain may be adjusted To make this adjustment perform steps 8 and 8 above Calibration of the loopback inputs is complete Restore the board to its original configuration Note Steps 5 6 and 8 as well as steps 12 and 13 may require a program to make these adjustments 2 12 1C697VAL301 32 Channel 12 bit Analog Output
23. circuitry will periodically transfer data from the dual port memory s refresh port to the DAC Simultaneously the logic connects the DAC to the appropriate section of the analog output demultiplexer analog distributor The analog output data is placed in the dual port memory by the controlling processor through the VMEbus port Analog Distributor 4 6 The analog distributor consists of the following elements one of 32 output channel decoder e Low charge injection analog demultiplexer 4 one of eight decoders Thirty two capacitive storage elements and buffers The one of 32 decoder receives the same five address lines used to select the dual port memory location used to update the DAC In this manner the converted analog level is always routed by the distributor section to the output buffer which corresponds to the dual port memory location being updated The upper two bits are decoded to yield a select line to choose the correct demultiplexer The three lower bits are used to select the output to pass through the decoder Figure 4 3 on page 4 10 shows the 1 of 32 decoder logic After allowing the DAC to settle the refresh logic enables turns ON the demultiplexer The converted voltage level is transferred to the corresponding storage capacitor Approximately 100 msec of settling time is provided by the REFRESH logic for the sample and hold buffer Then the demultiplexer is disabled and the next channel in the REFRESH sequence is
24. djustment unless another person capable of rendering first aid and resuscitation is present Do Not Substitute Parts or Modify System Because of the danger of introducing additional hazards do not install substitute parts or perform any unauthorized modification to the product Return the product to GE Fanuc for service and repair to ensure that safety features are maintained IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 Chapter Configuration and Installation 2 This chapter provides configuration and installation instructions for the Analog Output Board and is divided into the following sections Physical Installation Before Applying Power Checklist Base Address Configuration Calibration Connector Descriptions Some of the components assembled on GE Fanuc products can be sensitive to electrostatic discharge and damage can occur on boards that are subjected to a high energy electrostatic field When the board is placed on a bench for configuring etc it is suggested that conductive material be placed under the board to provide a conductive shunt Unused boards should be stored in the same protective boxes in which they were shipped Upon receipt any precautions found in the shipping container should be observed All items should be carefully unpacked and thoroughly inspected for damage that might have occurred during shipment The board s
25. e correct code for the output voltage sent see Chapter 3 for more details Converter Controls and Status Flags A conversion sequence is initiated by a single write to the CSR placing a one in the START SETTLING and the START CONV control bits and the channel to be converted The last five bits contain the input channel information The conversion sequence is composed of the following consecutive time intervals e Settling Delay e Tracking Interval Analog to Digital A D Conversion All ADC timing intervals discussed in this section are performed automatically by the on board controller The host writes the CSR with the start settling and the start convert bits set and the desired channel This will switch the demultiplexer to the desired channel and start the settling process The host now waits 5 msec for the board s multiplexers to settle to the new voltage During this time keep any digital activity to this board to a minimum After the data ready bit has been set in the CSR the host can read the data IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 8502 1449 fo 09 4224 IDB800 to IBD11 12 ADC CTRL LOGIC TEST SIGNAL 1 OF 32 MULTIPLEXER s FROM BIT MONITOR 1 of 32 SWITCHES 21801 pouiduus p mr Built in Power Converter Electrical power for the Analog Output
26. e height Eurocard form factor e Individually coded keyed front panel VME DIN connector e Extended ground pin bus connectors IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 Functional Description The analog outputs on this board will supply up to 10 mA of drive current and can be operated off line for both loopback testing and for single point analog output applications Built in Test of all active components is provided by looping back the analog outputs with multiplexers and switches These circuits are used to check either the on line or the off line analog outputs The outputs support several operating voltage ranges The range is selected by the user via jumpers The scan rate is program controlled and can be increased to provide an improved response for complex output functions Figure 1 1 below is a block diagram of the board Figure 1 1 Analog Output Board Block Diagram OUTPUT BUFFERS WITH HOLD CAPS ANALOG DISTRIBUTOR BIT MULTIPLEXERS H DAC ADC 5 z Ec 8 a 9 H tr L tr 415 V 15 V BUS INTERFACE LOGIC zu oz az 45V 4 gt gt l GFK 2058 Chapter 1 Introduction Description and Specifications 1 3 Safety Summary 1 4 Warning The following general safety precautions
27. e outputs the maximum full scale range is 20 V To modify the full scale range for 5 V or 10 V place the jumper at J4 in position 2 3 For 20 V operations put the jumper in position 1 2 Bipolar or unipolar operation is selected with jumper J3 When J3 s jumper is in position 1 2 the board operates in the bipolar mode For unipolar voltages place the jumper in position 2 3 Figure 2 5 Loopback Input Voltage Range Selection J3 J3 Unipolar Mode Bipolar Mode Factory Configuration J4 J4 20 10Vor5V Factory Configuration Do not take readings of any output channel that was updated less than 3 4 msec before or you will read the old value of the outputs The sequencer needs this time to refresh the output S amp H buffer Also give the loopback multiplexer 5 msec after a start convert command before reading the ADC to give the multiplexer time to settle IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 Calibration Before delivery from the factory the Analog Output Board is fully calibrated and conforms to all specifications for bipolar operations Should recalibration be required perform the procedures in Analog Output Calibration Procedure on page 2 11 and Loopback Input Calibration Procedure on page 2 12 with the equipment listed in Equipment Required below The locations of all adjustments and test points are shown in Figure 2 6 on page 2
28. e two different accesses The value NNNN depends on the make and model of the CPU board used Figure 2 3 Address Modifier Selection J6 J6 Short Supervisory Short Nonprivileged Factory Configuration 2 6 IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 Analog Output Voltage Range J1 and J2 The output voltage range is controlled by jumper J1 The factory configuration is the maximum full scale range of 20 V To change this value to 10 V place a jumper in position 1 2 For a range of 5 V place a jumper in position 2 3 Bipolar or unipolar operation of the analog outputs is selected with jumper J2 The board uses unipolar operations if a jumper is in position 1 2 If the jumper is in position 2 3 the outputs operate in bipolar mode factory configuration Figure 2 4 below shows the jumper locations for the different configurations Figure 2 4 Analog Output Voltage Range Selection J1 J J 20 V 10V 5V Factory Configuration J2 J2 Unipolar Mode Bipolar Mode Factory Configuration 2058 Chapter 2 Configuration and Installation 2 7 2 8 Loopback Input Voltage Range J3 and J4 The loopback multiplexers drive an ADC Analog to Digital Converter chip The loopback voltage range and polarity must be the same as the output voltage range If not the ADC produces the wrong values These conditions are controlled by jumpers J3 and J4 As with th
29. equire any special backplanes or analog input boards to test it BIT permits verification of all active components by routing the analog outputs through analog input multiplexers to the on board ADC The 32 analog outputs can supply 10 mA of drive current over the full output range of 10 V Each output has a Sample and Hold buffer S amp H and are protected from shorts and transients The outputs can be unipolar or bipolar in jumper selectable ranges up to 10 V Each channel has an output switch which disconnects the buffer from the field The output switches do not compromise the board s accuracy output impedance is 0 1 When the board is powered up or after a system reset these switches are open and the buffers are disconnected from the field The switches are under software control and can be opened or closed at any time A brief overview of the principal features of this board illustrates the flexibility and the performance that is available with the Analog Output Board e 32 analog output channels with 10 mA drive capability e Resident 12 bit ADC and DAC e Output ranges are jumper selectable as 0 to 5 V 0 to 10 V 2 5 V 5 V 10 V e Output accuracy is 0 05 percent e Program controlled off line operation of analog outputs e input data format is programmable as either binary offset binary or two s complement e Outputs are protected against line transients and short circuits e Front panel user LED e Doubl
30. hat has a fixed value 17xx HEX This register can be used by system initialization or automatic system configuration software All of the other registers on the board are offset from the address assigned to this register The value of NNN depends on the make and model of the controlling CPU IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 Control and Status Register Descriptions The Control and Status Register CSR is located at offset address 02 HEX It contains all of the flags necessary to control and monitor the following board operations Analog outputs on line off line status e Analog outputs refresh rate e Digital to Analog D A conversion e Built in Test BIT and A D control e Analog input channel selection Built in Test only e Front panel LED e A D and D A enable disable Scan HALT The CSR is 16 bits long and is detailed in Table 3 2 on page 3 6 The function of each control bit and status flag is described in detail subsequently in the associated programming discussions 2058 Chapter 3 Programming 3 3 3 4 Initialization When SYSTEM RESET is applied to the board the Control Register and all converter flags are cleared to the LOW state zero This places the board in a known state The D A output sequencer is stopped and the A D converter is disabled The data format is offset binary standard settling time the LED is ON a
31. ital voltmeter s positive lead to TP2 and its negative lead to TP1 Write the 16 bit value 0000 HEX to all of the analog output channels These registers begin at offset address 40 HEX and stop at offset 7 HEX Adjust for a digital voltmeter indication of 0 0000 40 0010 VDC Write the 16 bit value 07FF HEX to all of the analog output channels These registers begin at offset address 40 HEX and stop at offset 7 HEX Adjust R2 for a digital voltmeter indication of 9 9951 0 0010 VDC If the board is to be used in the Unipolar mode perform steps 10 11 and 12 Move the J2 jumper to the 2 1 position and place a jumper on J1 in the 1 2 position Write the 16 bit value 0800 HEX to all of the analog output channels Adjust for a digital voltmeter indication of 0 0000 40 0010 VDC For optimum performance the gain may be adjusted To make this adjustment perform steps 8 and 9 above Calibration of the analog outputs is complete Remove power and all test connections Restore the board to its original configuration 2058 Chapter 2 Configuration and Installation 2 11 Loopback Input Calibration Procedure 9 Perform the Analog Output Calibration Procedure before performing the Loopback Input Calibration Place the jumper at J4 in the 1 2 position This is the 20 V range Place the jumper at J3 in the 1 2 position This is the bipolar setting Write the 16 bit value 0000 HEX to all of the an
32. must be observed during all phases of this operation service and repair of this product Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design manufacture and intended use of this product GE Fanuc assumes no liability for the customer s failure to comply with these requirements Ground the System To minimize shock hazard the chassis and system cabinet must be connected to an electrical ground A three conductor AC power cable should be used The power cable must either be plugged into an approved three contact electrical outlet or used with a three contact to two contact adapter with the grounding wire green firmly connected to an electrical ground safety ground at the power outlet Do Not Operate in an Explosive Atmosphere Do not operate the system in the presence of flammable gases or fumes Operation of any electrical system in such an environment constitutes a definite safety hazard Keep Away from Live Circuits Operating personnel must not remove product covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them Do Not Service or Adjust Alone Do not attempt internal service or a
33. nd the outputs are disconnected from the external circuits In this condition the board is ready to perform loopback tests After the system RESET is removed the D A sequencer starts and the A D converter is enabled The A D and the D A can be disabled under software control Setting the SCAN HALT bit to a one disables the A D and the D A This bit must be cleared before normal operation can begin IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 2058 Table 3 1 Analog Output Board Register Map Offset Address in HEX Register Name Access Mode 00 BOARD ID READ 17 HEX 02 CSR READ WRITE 04 ADC READ 06 to 3E RESERVED 40 D A OUTPUT 00 READ WRITE 42 D A OUTPUT 01 READ WRITE 44 D A OUTPUT 02 READ WRITE 46 D A OUTPUT 03 READ WRITE 48 D A OUTPUT 04 4A D A OUTPUT 05 READ WRITE 4c D A OUTPUT 06 READ WRITE 4 D A OUTPUT 07 50 D A OUTPUT 08 READ WRITE 52 D A OUTPUT 09 READ WRITE 54 D A OUTPUT 10 56 D A OUTPUT 11 READ WRITE 58 D A OUTPUT 12 READ WRITE SA D A OUTPUT 13 5c D A OUTPUT 14 READ WRITE 5E D A OUTPUT 15 READ WRITE 60 D A OUTPUT 16 62 D A OUTPUT 17 READ WRITE 64 D A OUTPUT 18 READ WRITE 66 D A OUTPUT 19 68 D A OUTPUT 20 READ WRITE 6A D A OUTPUT 21 READ WRITE 6c D A OUTPUT 22 6E D A OUTPUT 23 READ WRITE 70 D A OUTPUT 24 READ WRITE 72 D A OUTPUT
34. ng the Analog Outputs The 16 analog output channels appear to the controlling processor as 16 consecutive 16 bit words in the address space assigned to the Analog Output Board The register map shown in Table 3 1 on page 3 5 lists the board relative or offset address of each output channel Each Analog Output Register supports both read and write operations eliminating the need for corresponding shadow latches in the processor Random Access Memory RAM space Writing to the Outputs Output voltage data is recognized in the Analog Output Registers as right justified 12 bit binary data When offset binary data is written to a register the upper four bits D12 to D15 are ignored and not retained for read back If the board is using two s complement data then these bits contain the sign of the output data Each output responds to a new code within 3 4 msec after the code is written to the Output Register 0 85 msec in the FAST REFRESH MODE Be sure to give the board ample time to update the output before reading its value in a loopback test FAST REFRESH 3 8 Setting the FAST REFRESH control bit Table 3 2 on page 3 6 HIGH reduces the analog output REFRESH time from the default value of 3 4 to 0 85 msec The FAST REFRESH MODE raises the output Nyquist frequency maximum output signal frequency from approximately 300 Hz to about 1 2 kHz This is done by reducing the settling time given to the various circuits in the output channels The F
35. ntroduction Description and Specifications 1 This manual describes the installation and operation of the IC697V 301 32 Channel 12 bit Analog Output Board with Built in Test BIT Reference Material and Other GE Fanuc Manuals For a detailed explanation of the VMEbus and its characteristics The VMEbus Specification is available from VITA VMEbus International Trade Association 7825 East Gelding Dr No 104 Scottsdale AZ 85260 480 951 8866 FAX 480 951 0720 Internet www vita com The following Application and Configuration Guides are available from GE Fanuc to assist in the selection specification and implementation of systems based upon GE Fanuc s products Analog I O Products Built in Test Provides assistance in configuring analog I O Configuration Guide catalog number subsystems based on GE Fanuc s analog I O GFK 2084 products including common designs which offer a wide variety of solutions Connector and I O Cable Application Describes I O connections that can be used with Guide catalog number GFK 2085 GE Fanuc s VMEbus products Includes connector compatibility information and examples 2058 1 1 General Description 1 2 The 32 Channel 12 bit Analog Output AO Board with the Built in Test BIT features outputs that can be tested on line or off line with an on board Analog to Digital Converter ADC This self contained testing feature means this board does not r
36. on logic is employed during the transfer of data to the DAC to ensure that only one port is active at any time The REFRESH control logic sequences through the output channels from 0 to 31 It writes the channel s digital data to the DAC at the same time it selects the correct output S amp H buffer It then performs the necessary time delays for each part of the logic DAC multiplexer and output amplifier to settle to the updated value It also arbitrates the access to the RAM When the VMEbus wants to access this RAM it makes sure the output logic is in a state that will tolerate the interruption The VMEbus then places the bus data into the RAM and signals the board interface logic when the transfer is done scanning is then resumed When the loopback ADC is performing a conversion the REFRESH control logic is stopped thereby preventing it from generating noise which gets into the loopback ADC s input This noise can cause a large error in the input voltage making the host erroneously think that the board has failed By freezing the REFRESH logic the noise is eliminated This will add up to 15 usec to the 3 4 msec update rate for each conversion a 44 percent increase This impact should not be a problem for the outputs because the READ software should give 5 msec of settling time for the loopback multiplexers 2058 Chapter 4 Theory of Operation 4 9 1002 42qui222q 8 498 LI jn
37. plications To eliminate the effect of switch resistance on the output impedance the inverting sense input of each output buffer is switched between the load and line side of the output switch during on line and off line operations Thus the output impedance is the switch resistance divided by the open loop gain of the op amp Clamping diodes protect the buffers and switches from line transients by preventing voltage excursions beyond the 15 V supply rails IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 Data RAM and Refresh Logic The dual port memory which services the analog outputs is organized as a 16 bit wide 32 column array Each location can be accessed from either of two ports The random access VME port is used by the VMEbus host to load the analog output digital codes into the memory The digital codes are then transferred sequentially through the DAC port to the Digital to Analog Converter There they are converted into voltage levels and subsequently distributed to the appropriate analog output channel The dual port memory is controlled by the REFRESH control logic which derives its timing from the 16 MHz system clock The REFRESH control logic supervises all data transfers between the memory and the DAC and controls the distribution of the analog voltages to the outputs Because the dual port memory must be accessed through both the VME and DAC ports arbitrati
38. r P3 Refer to Connector Descriptions on page 2 13 for a description of the P3 connector e Calibration has been performed at the factory If recalibration is required refer to Calibration on page 2 9 2058 Chapter 2 Configuration and Installation 2 3 Base Address Configuration Control of the Analog Output Board s base address and I O access mode is determined by field replaceable on board jumpers This section describes the use of these jumpers and their effects on board performance The locations and functions of all Analog Output Board jumpers are shown in Figure 2 1 on page 2 5 and Table 2 1 below Factory Installed Jumpers 2 4 Each Analog Output Board is configured at the factory with the specific jumper arrangement shown in Table 2 1 below The factory configuration establishes the following functional baseline for the Analog Output Board and ensures that all essential jumpers are installed Base short I O address is set at 0000 HEX e access mode is short supervisory e Analog output and loopback ranges set to 10 V full scale Table 2 1 Jumper Functions and Factory Configuration Jumper Name Jumper Function Factory Configuration 17 ADDRESS DECODE OF Bit A07 INSTALLED 16 NONPRIVILEGED SUPERVISORY I O OMITTED 15 ADDRESS DECODE OF Bits A08 to 15 JA LOOPBACK VOLTAGE RANGE INSTALLED AT 1 2 B LOOPBACK VOLTAGE POLARITY INSTALLED AT 1 2 12 OUTPUT VOLTAGE
39. rt is controlled by the analog output refresh logic The data format and the two s complement control bit must be consistent IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 8502 1449 uoyvsadg fo Koay p 4214 S F snq3NA AM5 to AM0 9 A15 to A07 2 to 1 9 LINES 16 4 P 015 to DOO BOARD BASE ADDRESS SELECTION JUMPERS BD ID SELECT LINES CSR RAM ADC CTRL RESET CONTROL LINES LINES DTACK WRITE WRITEL ALL SIGNALS EXCEPT CLK ARE ACTIVE LOW 16 lt gt TO BOARD REGISTERS IDB15 to IDBOO 21807 IWJIAUJ p 211814 Analog Outputs Each analog output has its own sample and hold buffer and a control switch The analog outputs are updated refreshed periodically from the dual port memory by the refresh control logic as illustrated in Figure 4 2 on page 4 7 Each output receives an update once every 3 4 msec in the default refresh mode A program controlled FAST REFRESH control bit can be used to reduce the refresh cycle time to approximately 0 85 msec thereby raising the maximum output sampling rate from 294 Hz to 1 18 kHz These rates assume there is no loopback activity on the board Digital to Analog Converter DAC All 32 analog outputs are serviced by a single 12 bit DAC The DAC is controlled by the refresh control logic As long as the ADC is not converting a voltage this
40. should be checked for broken components damaged printed circuit board s heat damage and other visible contamination All claims arising from shipping damage should be filed with the carrier and a complete report sent to GE Fanuc together with a request for advice concerning the disposition of the damaged item s 2058 2 1 2 2 Physical Installation Caution Do not install or remove board while power is applied De energize the equipment and insert the board into an appropriate slot of the chassis While ensuring that the board is properly aligned and oriented in the supporting board guides slide the board smoothly forward against the mating connector until firmly seated IC697VAL301 32 Channel 12 bit Analog Output Board with Built in Test BIT GFK 2058 User s Manual December 2001 Before Applying Power Checklist Before installing the board in a VMEbus system check the following items to ensure that the board is ready for the intended application e Have the sections pertaining to programming and theory chapters 3 and 4 been reviewed and applied to system requirements e Review Factory Installed Jumpers and Table 2 1 on page 2 4 to verify that all factory installed jumpers are in place To change the board address or address modifier response refer to Board Address Selection 75 and 77 on page 2 6 e Have the I O cables with the proper mating connectors been connected to the output connecto
41. uffers If this bit is high the test buffers monitor the output pins of P3 The loopback multiplexers are always enabled to prevent the ADC from trying to convert a high impedance input instead of a voltage By routing the analog outputs through these loopback multiplexers the operation of all the components on the Analog Output Board can be verified ADC Controls and Flags 2058 timing operations for the ADC performed by on board controller User control of the converter consists of the following control bits flags and registers The control bits and flags in the CSR are summarized in Table 3 2 on page 3 6 They are restated here for clarity Table 3 3 CSR Bit Functions Control Bits a SHORTSETILINGH 0155 b ENSTARTCONVH 0135 c TWO sCOMPLL D12 d START SETTLING H D06 Effective only upon writing strobed Flags Status Register a NEW DATA RDYH D15 b CONV BUSYH D13 c SETTLING BUSYH D06 Set when data is available in the ADC Data Register Chapter 3 Programming 3 9 3 10 The START SETTLING and START CONV controls are essentially strobes They are effective only at the moment of writing to the Control Register Although supplied as two separate control bits they must be written to the register simultaneously along with the operating mode TWO s COMPL L and SHORT SETTLING H bits and the input channel selection
42. ut Data Registers are memory mapped as 32 decimal 16 bit words These registers store the value of the output voltage for the associated output channel These registers are contiguous and are located 40 HEX offset from the base address of the board The board occupies 128 bytes of the VMEbus short I O address space and may be user located on any 128 byte boundary in this region The board can be user configured to respond to short supervisory or short nonprivileged bus access The board supports two additional registers for a user interface These registers are the Board ID and the Control and Status Registers Figure 4 1 on page 4 5 is a block diagram of the bus interface logic The board monitors the VMEbus During any data transfer the board selection comparator determines if there is a match between the on board selection jumpers shown in Figure 4 1 on page 4 5 and the address and address modifier lines on the backplane If there is no match all VMEbus control signals are ignored If there is a match the appropriate board response will occur The open collector DTACK interface signal is then asserted driven LOW Subsequent removal of the read or write command by the Central Processing Unit CPU causes the board generated DTACK signal to return to the OFF state terminating the data transfer cycle Although some of the registers on the board are read only the board will respond to a write command at these locations However the data written
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