PCF8577C - NXP Semiconductors
Contents
1. m CONTROL REGISTER m SEGMENT BYTE REGISTERS J DISPLAY SEGMENT BYTE VECTOR CONTROL SBV A A ms OY LSB MSB LSB T T f T T vs V4 V3 V2 V1 VO 0 l i i l l 1 segment byte register 2 0 1 address EE ES i gt BANK A comparison 4 L L T T 6 l l J lt v v T T gt a2 A1 AO 1 l device subaddress 3 i I gt BANK B 0 BANK A 5 BANK l 1 BANK B 7 iu l J jJ 0 DIRECT DRIVE DISPLAY MODE 1 DUPLEX DRIVE aaa 015163 1 Bits ignored in duplex mode Fig 3 PCF8577C register organization The upper three bits of the SBV V5 to V3 are compared with the hardware subaddress input signals A2 A1 and AO If they are the same then the device is enabled for loading if not the device ignores incoming data but remains active The three least significant bits of the SBV V2 to VO address one of the segment byte registers within the enabled chip for loading segment data All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 5 of 33 NXP Semiconductors PC F8577C PCF8577C 7 4 7 5 LCD direct duplex driver with I C bus interface The control register also has two display control bits These bits are named MODE and BANK The MODE bit selects w2. PCF8577C LCD direct duplex driver with I C bus interface Rev 5 10 October 2014 Product data sheet 1 General description The PCF8577C is an LCD driver which drives up to 32 segments directly or 64 segments in a duplex configuration The two line I2C bus interface substantially reduces wiring overheads in remote display applications C bus traffic is minimized in multiple IC applications by automatic address incrementing hardware subaddressing and display memory switching direct drive mode To allow partial Vpp shutdown the ESD protection system of the SCL and SDA pins does not use a diode connected to Vpp For a selection of NXP LCD segment drivers see Table 13 on page 25 2 Features and benefits Direct duplex drive modes with up to 32 64 LCD segment drive capability per device Operating supply voltage 2 5 V to 6 V Low power consumption I C bus interface Optimized pinning for single plane wiring Single pin built in oscillator Auto incremented loading across device subaddress boundaries Display memory switching in direct drive mode May be used as I C bus output expander System expansion up to 256 segments Power on reset blanks display PC bus address 0111 0100 3 Ordering information Table 1 Ordering information Type number Package Name Description Version PCF8577CT VSO40 plastic very small outline package 40 SOT158 1 leads
3. NXP Semiconductors PCF8577C 3 1 Ordering options LCD direct duplex driver with I C bus interface Table 2 Ordering options Product type number Orderable part number Sales item Delivery form IC 12NC revision PCF8577CT 3 PCF8577CT 3 112 935278866112 tube 3 PCF8577CT 3 PCF8577CT 3 118 935278866118 tape and reel 13 inch 3 4 Marking Table 3 Marking codes Type number Marking code PCF8577CT 3 PCF8577CT 5 Block diagram 32 SCL SEGMENT BYTE REGISTERS BAG LANE INPUT 2C BUS AND AND FILTERS CONTROLLER MULTIPLIES SEGMENT DRIVERS SDA LOGIC S1 BP1 A2 BP2 A1 A0 OSC BERDE ET Er COMPARATOR DIVIDER Vss Fig 1 gh Block diagram of PCF8577C aaa 015162 PCF8577C All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 2 of 33 NXP Semiconductors PCF8577C 6 Pinning information LCD direct duplex driver with I C bus interface PCF8577C 6 1 Pinning Fig 2 32 31 30 S29 S28 S27 S26 S25 S24 s23 10 s22 1 s21 12 s20 13 s19 14 s18 15 s17 16 s16 17 s15 18 s14 19 s13 o PCF8577CT 40 39 38 37 36
4. Table 7 1 C slave address byte Slave address R W Bit 7 6 5 4 3 2 1 0 MSB LSB 0 1 1 1 0 1 0 0 Before any data is transmitted on the I C bus the device which should respond is addressed first The addressing is always done with the first byte transmitted after the start procedure All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 10 of 33 NXP Semiconductors PC F8577C LCD direct duplex driver with I C bus interface 8 3 2C bus protocol The PCF8577C C bus protocol is shown in Figure 10 The PCF8577C is a slave receiver and has a fixed slave address see Table 7 All PCF8577Cs with the same slave address acknowledge the slave address in parallel The second byte is always the control byte and is loaded into the control register of each PCF8577C connected to the I C bus All addressed devices acknowledge the control byte Subsequent data bytes are loaded into the segment registers of the selected device Any number of data bytes may be loaded in one transfer and in an expanded system rollover of the SBV from 111 111 to 000 000 is allowed If a STOP P condition is given after the control byte acknowledge the segment data remains unchanged This allows the BANK bit to be toggled without changing the segment register contents During loading of segment
5. 35 34 33 32 31 30 Ed 28 27 26 25 24 23 22 21 Pin configuration for PCF8577CT SDA SCL Vss A0 OSC A1 Vpp A2 BP2 BP1 1 S2 S3 S4 S5 S6 S7 S8 S9 10 11 12 aaa 015164 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 3 of 33 NXP Semiconductors PC F8577C 7 Functional 6 2 LCD direct duplex driver with I C bus interface Pin description Table 4 Pin description Symbol Pin Type Description S32 to S1 11032 outputs segment outputs BP1 33 input output cascaded sync input backplane output A2 BP2 34 input output hardware address line and cascade sync input backplane output Vpp 35 supply supply voltage A1 36 input hardware address line input A0 OSC 37 input hardware address line and oscillator pin input Vss 38 supply ground supply SCL 39 input I2C bus clock line input SDA 40 input output I2C bus data line input output description PCF8577C 7 1 7 2 Hardware subaddress lines AO A1 and A2 The hardware subaddress lines AO A1 and A2 are used to program the device subaddress for each PCF8577C connected to the I C bus Lines AO and A2 are shared with OSC and BP2
6. NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 20 of 33 NXP Semiconductors PC F8577C LCD direct duplex driver with I C bus interface 15 Packing information 15 1 Tape and reel information For tape and reel packing information see Ref 10 SOT158 1_ 118 on page 27 16 Soldering of SMD packages 16 1 16 2 This text provides a very brief insight into a complex technology A more in depth account of soldering ICs can be found in Application Note AN10365 Surface mount reflow soldering description Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards PCBs to form electrical circuits The soldered joint provides both the mechanical and the electrical connection There is no single soldering method that is ideal for all IC packages Wave soldering is often preferred when through hole and Surface Mount Devices SMDs are mixed on one printed wiring board however it is not suitable for fine pitch SMDs Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder The wave soldering process is suitable for the following Through hole components Leaded or leadless SMDs which
7. PCF8577C All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 13 of 33 NXP Semiconductors PC F8577C LCD direct duplex driver with I C bus interface Table 9 Static characteristics continued Vpp 2 5 V to 6 V Vss 0 V Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit LCD outputs Voc DC component of LCD 20 mV driver lot LOW level output current on pins S1 to S32 4 0 3 mA Vpp 5V Vor 0 8 V lou HIGH level output current jon pins S1 to S32 4 0 3 mA Vpp 5 V Vou Vpp 0 8 V Ro output resistance on pins BP1 BP2 5 0 4 5 kQ Vo Vss or Vpp or Vo Vss Vpp 1 Inputs at Vss or Vpp 2 Resets all logic when Vpp lt Vpon 3 Periodically sampled not 100 tested 4 Outputs measured one at a time 5 Outputs measured one at a time Vpp 5 V load 100 pA PCF8577C All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 14 of 33 NXP Semiconductors PC F8577C LCD direct duplex driver with I C bus interface 12 Dynamic characteristics Table 10 Dynamic characteristics Vpp 2 5 V to 6 V Vss 0 V Tamb 40 C
8. Contact information 30 23 Tables oie EE EE ENE EE ee tix RR SS RR 31 24 Figures lese a rar erae en 32 25 Contents EER x ed ace EE sede ie 33 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP Semiconductors N V 2014 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 10 October 2014 Document identifier PCF8577C
9. Di Generic footprint pattern Refer to the package outline drawing for actual layout GA solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0 760 0 835 12 700 8 300 2 200 0 450 0 600 15 440 8 100 16 100 12 950 sot158 1_fr Fig 18 Footprint information for reflow soldering of SOT158 1 VSO40 of PCF8577CT PCF8577C All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 24 of 33 Jays Lep 12npoid t LOZ 1920190 OL S 9H sjeuirejosip Jeba 0 joefqns s jueuunoop S14 ui papiaoid uoneuuojul JY JO GZ 9449849d pamasa siuDu IV P LOZ N N SIoronpuoorues dXN 18 Appendix Table 13 Selection of LCD segment drivers 18 1 LCD segment driver selection Type name Number of elements at MUX Voo V Vrco V fe Hz Vicp V Vicp V Tamb C Interface Package AEC 11 12 18 14 16 18 1 9 charge temperature aie pump compensat PCA8553DTT 40 80 120 160 2 1 8 to 5 5 1 810 5 5 32 to 256 N N 40 to 105 I2C SPI TSSOP56 Y PCA8546ATT 176 18t05 5 25to9 60to0 300 N N 40 to 95 12C TSSOP56 Y PCA8546BTT 176 1 8105 5 2 5t09 60to 300 N N A0 to 95 SPI TSSOP56
10. JY PCA8547AHT 44 88 l 176 1 81055 2 5t09 60to 3000 JY Y 40 to 95 C TOFP64 JY PCA8547BHT 44 88 l 176 1 8105 5 2 5t09 60to300 Y Y A0 to 95 SPI TOFP64 JY PCF85134HL 60 120 180 240 1 8 to 5 5 2 5t06 5 82 N N 40 to 85 12C LQFP80 N PCA85134H 60 120 180 240 1 8t05 5 2 5t08 82 N N 40 to 95 C LQFP80 Y PCA8543AHL 60 120 240 2 5t05 5 2 5t09 60 to 3000 Y Y 40 to 105 C LQFP80 Y PCF8545ATT 176 252 320 1 8 to 5 5 2 5to 5 5 60 to 3004 N N 40 to 85 IC TSSOP56 N PCF8545BTT 176 252 320 1 8 to 5 5 2 5t0 5 5 60to 3000 N N 40 to 85 SPI TSSOP56 N PCF8536AT 176 252 320 1 8to 5 5 25to9 60 to 300 N N 40 to 85 C TSSOP56 N PCF8536BT 176 252 320 1 8 to 5 5 2 5t09 60to 3000 N N 40 to 85 SPI TSSOP56 N PCA8536AT 176 252 320 1 8105 5 2 5t0 9 60to 300 N N 40 to 95 C TSSOP56 JY PCA8536BT 176 252 320 1 8t05 5 2 5t09 60 to 300l N N 40 to 95 SPI TSSOP56 JY PCF8537AH 44 88 176 276 352 18t05 5 2 5t09 60to 300 JY Y 40 to 85 C TQFP64 N PCF8537BH 44 88 176 276 352 1 8t05 5 2 5109 60to 300 Y Y 40 to 85 SPI TQFP64 N PCA8537AH 44 88 176 276 352 1 8t05 5 2 5t09 60to300l JY Y 40 to 95 C TQFP64 Y PCA8537BH 44 88 176 276 352 1 8t05 5 2 5t09 60 to 300 Y Y A0 to 95 SPI TOFP64 JY PCA9620H 60 120 240 320 480 2 5t05 5 2 5to9 60to300l Y Y 40 to 105 IC LQFP80 Y PCA9620U 60 120 240 320 480 2
11. are glued to the surface of the printed circuit board Not all SMDs can be wave soldered Packages with solder balls and some leadless packages which have solder lands underneath the body cannot be wave soldered Also leaded SMDs with leads having a pitch smaller than 0 6 mm cannot be wave soldered due to an increased probability of bridging The reflow soldering process involves applying solder paste to a board followed by component placement and exposure to a temperature profile Leaded packages packages with solder balls and leadless packages are all reflow solderable Key characteristics in both wave and reflow soldering are Board specifications including the board finish solder masks and vias Package footprints including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead free soldering versus SnPb soldering 16 3 Wave soldering PCF8577C Key characteristics in wave soldering are All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 21 of 33 PCF8577C LCD direct duplex driver with I C bus interface NXP Semiconductors Process issues such as application of adhesive and flux clinching of leads board transport the solder wave parameters and the time during which components are exposed to the wa
12. respectively to reduce pinout requirements 1 Line AO is defined as LOW logic 0 when this pin is used for the local oscillator or when connected to Vss Line AO is defined as HIGH logic 1 when connected to Vpp 2 Line A1 must be defined as LOW logic 0 or as HIGH logic 1 by connection to Vss or Vpp respectively 3 In the direct drive mode the second backplane signal BP2 is not used and the A2 BP2 pin is exclusively the A2 input Line A2 is defined as LOW logic 0 when connected to Vss or if this is not possible by leaving it unconnected internal pull down Line A2 is defined as HIGH logic 1 when connected to Vpp 4 In the duplex drive mode the second backplane signal BP2 is required and the A2 signal is undefined In this mode device selection is made exclusively from lines AO and A1 Oscillator A0 OSC The PCF8577C has a single pin built in oscillator which provides the modulation for the LCD segment driver outputs One external resistor and one external capacitor are connected to the A0 OSC pin to form the oscillator see Figure 13 and Figure 14 For correct start up of the oscillator after power on the resistor and capacitor must be connected to the same Vss Vpp as the chip In an expanded system containing more than one PCF8577C the backplane signals are usually common to all devices and only one oscillator is required The devices which are not used for the oscillator are put into the cascade mode by connecting the A
13. 5t05 5 2 5to9 60 to 300 Y Y 40 to 105 2C Bare die Y PCF8576DU 40 80 120 160 1 8 to 5 5 2 5t06 5 77 N N 40t085 IC Bare die N PCF8576EUG 40 80 120 160 1 8 to 5 5 2 5 to 6 5 77 N N 40 to 85 IC Bare die N PCA8576FUG 40 80 120 160 1 8 to 5 5 2 5108 200 N N 40 to 105 C Bare die Y PCF85133U 80 160 240 320 1 8105 5 2 5 to 6 5 82 110 N N 401085 12C Bare die N PCA85133U 80 160 240 320 E 1 8105 5 2 5t08 82 1102 N N 40 to 95 C Bare die Y OEHEIUI SNq z uu 4eAup xejdnpoeurp A97 JZZS8490d SJOJONPUODIWIIS dXN yoays ejep jonpoJd t LOZ 1920190 OL S 9H sieuirejosip eba 0 1oefqns s jueuunoop S14 ui papiaoid uoneuuojul JY E JO 9c 9449849d pamasa siuDu IV Y LOZ N N S1O ONPUODIWES dXN Table 13 Selection of LCD segment drivers continued Type name Number of elements at MUX Voo V Viep V fr Hz Vreo V Vicp V Tamb C Interface Package AEC 11 12 18 14 1 6 18 1 9 Ee NE ie aron pump compensat PCA85233UG 80 160 240 320 1 8105 5 2 5t08 150 22012 IN N 40 to 105 2C Bare die Y PCF85132U 160 320 480 640 D 1 8to 5 5 1 8t08 60to 90 N N 40 to 85 C Bare die N PCA8530DUG 102 204 408 2 5to05 5 4to 12 45 to 30011 JY Y 40to 105 I2C SPI Baredie Y PCA85132U 160 320 480 640 1 8 to 5 5 1 8t08 60to 90 N N 40 to 95 C Bare di
14. 7 6 Duplex mode The PCF8577C is set to the duplex mode by loading the MODE bit with logic 1 In this mode a second backplane signal BP2 is needed and pin A2 BP2 is used for this therefore A2 and its equivalent SBV bit V5 are undefined The SBV auto increments by one between loaded bytes All of the segment bytes are required to store data for the 32 segment drivers and the BANK bit is ignored All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 6 of 33 NXP Semiconductors PCF8577C LCD direct duplex driver with I C bus interface Duplex mode output waveforms are shown in Figure 5 0 5 V pp V ss V pp V ss OFF OFF ON OFF OFF ON ON ON VDD RE He RE s Vss 0 5 Vop Ves mt ipt ipt ipt T Vss VDD Segment x Sx Vss Vpp Vss 0 5 Vpp Vss 0 l l BP1 Sx 0 5 V pp V ss V pp V ss Vpp V ss O 5 Vpp Vss 0 L 7 L BP2 Sx Fig 5 Von RMs 0 791 Vpp Vss Vottus 0 354 Vpp VSS Duplex mode display output waveforms 1 fLeD aaa 015167 7 7 Display memory mapping The mapping between the eight segment registers and the segment outputs S1 to S32 is given in Table 5 and Table 6 Since only one register bit per segment is needed in the direct drive mode th
15. 77C LCD direct duplex driver with I C bus interface SDA SCL MASTER SLAVE MASTER TRANSMITTER RE VER TRANSMITTER EE Es TRANSMITTER RECEIVER RECEIVER RECEIVER mba605 Fig 8 System configuration 8 1 4 Acknowledge PCF8577C 8 2 The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is not limited Each byte is followed by one acknowledge bit The acknowledge bit is a HIGH level put on the I2C bus by the transmitter whereas the master generates an extra acknowledge related clock pulse A slave receiver which is addressed must generate an acknowledge after the reception of each byte Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse set up and hold times must be taken into account A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition START clock pulse for condition acknowledgement SCL FROM 2 9 DATA OUTPUT gia BY TRANSMITTER DATA OUTPUT se BY RECEIVER mba606 Fig 9 Acknowledgement of the I2C bus Slave address The PCF8577C slave address is shown in Table 7
16. O OSC pin to either Vpp or Vss depending on the required state for AO In the cascade mode each PCF8577C is synchronized from the backplane signals All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 4 of 33 NXP Semiconductors PC F8577C PCF8577C LCD direct duplex driver with I C bus interface 7 3 User accessible registers There are nine user accessible 1 byte registers The first is a control register which is used to control the loading of data into the segment byte registers and to select display options The other eight are segment byte registers split into two banks of storage which store the segment data The set of even numbered segment byte registers is called BANK A Odd numbered segment byte registers are called BANK B There is one slave address for the PCF8577C see Table 7 All addressed devices load the second byte into the control register and each device maintains an identical copy of the control byte in the control register always see C bus protocol Figure 10 i e all addressed devices respond to control commands sent on the 2C bus The control register is shown in more detail in Figure 3 The least significant bits select which device and which segment byte register is loaded next This part of the register is therefore called the Segment Byte Vector SBV
17. PCF8577Cs 20 005 18 Use of PCF8577C as a 32 bit output expander in an l2C bus application 4 19 Package outline SOT158 1 VSO40 of PCF8577CT ooiissi lusus e nises 20 Temperature profiles for large and small COMPONENIS wih bs cam Ie gue Ru yx ey eg wea 23 Footprint information for reflow soldering of SOT158 1 VSO40 of PCF8577CT 24 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 32 of 33 NXP Semiconductors PCF8577C 25 Contents LCD direct duplex driver with I C bus interface OU BOON 8 1 1 8 1 2 8 1 3 8 1 4 8 2 8 3 10 11 12 13 14 15 15 1 16 16 1 16 2 16 3 16 4 17 18 18 1 19 20 General description ssus 1 Features and benefits 1 Ordering information elus 1 Ordering options lisse EE Ee ee 2 Marking cece eee eee RR RR B 2 Block diagram 0 e scence eee eee 2 Pinning information lees 3 PINNING a ice db EO EE ERE RE ed 3 Pin description i socer adis 4 Functional description 4 Hardware subaddress lines AO A1 and A2 4 Oscillator AO OSC 0 000005 4 User accessible registers 5 Auto incremented loading 6 Direct drive mode 20 0 055 6 D
18. S dXN Jays Lep 12npoid t LOZ 1920190 OL S 9H sieuirejosip eba 0 joefqns s jueuunoop SIY ui papiaoid uoneuuojul JY JO 8L 9449849d pamasa siuDu IV v LOZ N N S4O ONPUODIWES dXN DUPLEX LCD DISPLAY 32 33 VDD Cosc Rosc Vss SCL SDA PCF8577C 537 device subaddress A1 A0 00 PCF8577C 55 device subaddress A1 A0 01 PCF8577C 635 device subaddress A1 A0 11 Fig 14 Duplex display expansion to 2 x 128 segments using four PCF8577Cs aaa 015187 OEHEIUI SNA D YUM 4eAup xejdnpoeurp 021 JZZS8490d SJOJONPUODIWIIS dXN NXP Semiconductors PC F8577C LCD direct duplex driver with I C bus interface 32 output lines ey VDD Vss SCL SDA PCF8577C device subaddress A2 A1 AO 000 expansion bo aaa 015188 MODE bit must always be set to logic 0 direct drive Bank switching is permitted BP1 must always be connected to Vss and A0 OSC must be connected to either Vpp or Vss no LCD modulation Fig 15 Use of PCF8577C as a 32 bit output expander in an I2C bus application PCF8577C All information provided in this document is subject to legal disclaimers NXP Semi
19. Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 12 of 33 PCF8577C LCD direct duplex driver with I C bus interface NXP Semiconductors 11 Static characteristics Table 9 Static characteristics Vpp 2 5 V to 6 V Vss 0 V Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Supplies VDD Supply voltage 2 5 6 V Ipp supply current no load Rosc 1 MQ Cosc 680 pF fscL 100 kHz 1 50 125 HA fsCL s0 Hz 0l 25 75 HA Vpop 5 V pI 25 40 uA Tamb 25 C no load D 10 20 HA fsct 0 Hz AO OSC Vpp Vpp 5 V Tamb 25 C VPoR power on reset voltage 2 1 1 2 0 V Logic ViL LOW level input voltage on pin AO 0 0 05 V on pins A1 SCL SDA 0 0 3Vpp V on pin A2 0 0 1 V Vin HIGH level input voltage on pin AO Vpp 0 05 Vpp V on pin A1 0 7Vpp Vpp V on pin A2 Vpp 0 1 2 Vpp V on pins SCL SDA 0 7Vpp V Ci input capacitance 3 pF lot LOW level output current output sink current 3 mA on pin SDA VoL 0 4 V Vpp 5 V IL leakage current Vi Vpp or Vss on pins A1 SCL SDA 1 1 HA on pins A2 BP2 BP1 5 15 HA Vi Voo 1 3 uA on pin A0 OSC lod pull down current Vi Vpp 5 1 5 HA on pin A2 BP2 Istartup startup current oscillator 1 2 5 HA Vi Vss
20. V2 V1 VO Segment 7 6 5 4 3 2 1 0 Backplane Bit MSB LSB Register 1 xttl 0 0 0 0 S8 S7 S6 S5 S4 S3 S2 1 BP1 1 xt 0 0 4 1 S8 S7 S6 S5 S4 S3 S2 1 BP2 1 xti 0 1 0 2 16 15 14 13 12 11 10 S9 BP1 1 xiu 0 1 1 3 16 S15 14 S13 S12 S11 S10 SY BP2 1 xti 1 0 0 4 S24 S23 S22 S21 S20 19 18 S17 BP1 1 x 1 0 1 5 24 S23 22 S21 20 S19 S18 S17 BP2 1 xiu 1 1 0 6 S32 S31 S30 S29 S28 S27 S26 S25 BP1 1 x 1 1d 1 7 S32 S31 S30 829 S28 S27 S26 S25 BP2 1 Don t care PCF8577C Mapping example bit 7 of register 5 controls the LCD segment S24 BP2 7 8 Power on reset At power on reset the PCF8577C resets to a defined starting condition as follows 1 Both backplane outputs are set to Vss in master mode to 3 state in cascade mode 2 All segment outputs are set to Vss 3 The segment byte registers and control register are cleared 4 The 2C bus interface is initialized All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 8 of 33 NXP Semiconductors PC F8577C LCD direct duplex driver with I C bus interface 8 I 2C bus interface 8 1 8 1 1 PCF8577C Characteristics of the I2C Bus The I C bus is for 2 way 2 line communication between different ICs or modules The two lines are a Serial DAta line SDA and a S
21. conductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 19 of 33 NXP Semiconductors PCF8577C 14 Package outline LCD direct duplex driver with I C bus interface VSO40 plastic very small outline package 40 leads SOT158 1 5 scale DIMENSIONS inch dimensions are derived from the original mm dimensions lt detail X UNIT A A1 A2 A3 bp c DO EO e HE 0 3 0 1 2 25 0 25 0 30 0 22 15 6 0 14 15 2 7 6 7 5 11 8 inches 0 01 0 0087 0 61 0 0055 0 60 0 30 0 29 Notes 1 Plastic or metal protrusions of 0 4 mm 0 016 inch maximum per side are not included 2 Plastic interlead protrusions of 0 25 mm 0 01 inch maximum per side are not included OUTLINE VERSION REFERENCES JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT158 1 Ege 95 04 24 03 02 19 Fig 16 Package outline SOT158 1 VSO40 of PCF8577CT PCF8577C All information provided in this document is subject to legal disclaimers
22. data only the selected PCF8577C gives an acknowledge Loading is terminated by generating a STOP P condition acknowledge by acknowledge by acknowledge by all id all ES selected si only ulx a z SEGMENT SEGMENT DATA L control byte L n bytes 1 auto increment segment byte vector aaa 015168 Fig 10 I C bus protocol 9 Safety notes CAUTION A AN This device is sensitive to ElectroStatic Discharge ESD Observe precautions for handling electrostatic sensitive devices Such precautions are described in the ANSI ESD S20 20 IEC ST 61340 5 JESD625 A or equivalent standards AN CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage Vicp is on while the IC supply voltage Vpp is off or vice versa This may cause unwanted display artifacts To avoid such artifacts Vi cp and Vpp must be applied or removed together CAUTION Semiconductors are light sensitive Exposure to light sources can cause the IC to malfunction The IC must be protected against light The protection must be applied to all sides of the IC PCF8577C All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 11 of 33 NXP Semiconductors PCF8577C 10 Limiting values LCD direct duplex driv
23. e Y PCA85232U 160 320 480 640 18t05 5 1 8t08 117 to 1760 IN N 40 to 95 12C Bare die Y PCF8538UG 102 204 408 612 816 918 2 5 to 5 5 4 to 12 45 to 300ll Y Y 40 to 85 I C SPI Baredie N PCA8538UG 102 204 408 612 816 918 2 5 to 5 5 4to 12 45 to 30011 Y Y 40 to 105 I2C SPI Bare die Y 1 Software programmable 2 Hardware selectable OEHEIUI SNq z YUM 4eAup X ldnp 1p A97 JZZS8490d SJOJONPUODIWIIS dXN NXP Semiconductors PC F8577C LCD direct duplex driver with I C bus interface 19 References 1 AN10365 Surface mount reflow soldering description 2 AN10853 ESD and EMC sensitivity of IC 3 AN11267 EMC and system level ESD design guidelines for LCD drivers 4 IEC 61340 5 Protection of electronic devices from electrostatic phenomena 5 IPC JEDEC J STD 020D Moisture Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices 6 JESD22 A114 Electrostatic Discharge ESD Sensitivity Testing Human Body Model HBM 7 JESD22 A115 Electrostatic Discharge ESD Sensitivity Testing Machine Model MM 8 JESD78 IC Latch Up Test 9 JESD625 A Requirements for Handling Electrostatic Discharge Sensitive ESDS Devices 10 SOT158 1 118 VSO40 Reel pack SMD 13 packing information 11 UM10204 I C bus specification and user manual 12 UM10569 Store and transport requirements PCF8577C All information p
24. e BANK bit allows swapping of display information If BANK is set to logic 0 even bytes BANK A are displayed if BANK is set to logic 1 odd bytes BANK B are displayed BP1 is always used for the backplane output in the direct drive mode In duplex mode even bytes BANK A correspond to backplane 1 BP1 and odd bytes BANK B correspond to backplane 2 BP2 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 7 of 33 NXP Semiconductors PCF8577C LCD direct duplex driver with I C bus interface Table 5 Segment byte segment driver mapping in direct drive mode Mode Bank V2 V1 VO Segment 7 6 5 4 3 2 1 0 Backplane Bit MSB LSB Register 0 0 0 0 0 00 S8 S7 S6 S5 S4 S3 S2 1 BP1 0 1 0 0 1 1 S8 S7 S6 S5 S4 S3 S2 1 BP1 0 0 0 1 0 2 16 S15 14 S13 S12 S11 S10 SY BP1 0 1 0 1 1 3 16 S15 14 S13 S12 S11 S10 SY BP1 0 0 1 0 0 4 24 823 22 S21 20 819 S18 S17 BP1 0 1 1 0 1 5 S24 S23 S22 S21 S20 19 18 S17 BP1 0 0 1 1 0 6 S32 S31 S30 S29 S28 S27 S26 S25 BP1 0 1 1 1 1 7 S32 S31 S30 S29 S28 S27 S26 S25 BP1 Mapping example bit 0 of register 7 controls the LCD segment S25 if BANK bit is a logic 1 Table 6 Segment byte segment driver mapping in duplex mode Mode Bank
25. er with I C bus interface Table 8 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit VDD Supply voltage 0 5 8 0 V Vicp LCD supply voltage 11 Vpp 8 0 Vpp V Vi input voltage 0 5 Vpp 0 5 V Vo output voltage on each of the pins il 0 5 8 0 V S1 to S32 and BP1 and BP2 li input current 20 20 mA lo output current 25 25 mA Ipp supply current 50 50 mA Iss ground supply current 50 50 mA IDD LED LCD supply current 50 50 mA Piot total power dissipation 500 mW Po output power 100 mW VESD electrostatic discharge HBM 2 2000 V voltage MM Bl l 200 V liu latch up current 4 100 mA Tstg storage temperature 5 65 150 C Tamb ambient temperature operating device 40 85 C 1 Values with respect to Vpp 2 Pass level Human Body Model HBM according to Ref 6 JESD22 A114 3 Pass level Machine Model MM according to Ref 7 JESD22 A115 4 Pass level latch up testing according to Ref 8 JESD78 at maximum ambient temperature Tamp max 5 According to the store and transport requirements see Ref 12 UM10569 the devices have to be stored at a temperature of 8 C to 45 C and a humidity of 25 to 75 PCF8577C All information provided in this document is subject to legal disclaimers NXP
26. erial CLock line SCL Both lines must be connected to a positive supply via a pull up resistor when connected to the output stages of a device Data transfer may be initiated only when the I2C bus is not busy Bit transfer One data bit is transferred during each clock pulse The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time are interpreted as control signals SDA SCL data line change stable of data data valid allowed mba607 Fig 6 Bit transfer START and STOP conditions Both data and clock lines remain HIGH when the I2C bus is not busy A HIGH to LOW transition of the data line while the clock is HIGH is defined as the START condition S A LOW to HIGH transition of the data line while the clock is HIGH is defined as the STOP condition P ED IE be cs START condition STOP condition mba608 Fig 7 Definition of START and STOP conditions System configuration A device generating a message is a transmitter a device receiving a message is the receiver The device that controls the message is the master and the devices which are controlled by the master are the slaves All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 9 of 33 NXP Semiconductors PC F85
27. from competent authorities Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document and as such is not complete exhaustive or legally binding Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b 22 Contact information LCD direct duplex driver with I C bus interface whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconducto
28. hether the display outputs are configured for direct or duplex drive displays The BANK bit allows the user to display BANK A or BANK B Auto incremented loading After each segment byte is loaded the SBV is incremented automatically Thus auto incremented loading occurs if more than one segment byte is received in a data transfer Since the SBV addresses both device and segment registers in all addressed chips auto incremented loading may proceed across device boundaries if the hardware subaddresses are arranged contiguously Direct drive mode The PCF8577C is set to the direct drive mode by loading the MODE control bit with logic 0 In this mode only four bytes are required to store the data for the 32 segment drivers Setting the BANK bit to logic 0 selects even bytes BANK A setting the BANK bit to logic 1 selects odd bytes BANK B In the direct drive mode the SBV is auto incremented by two after the loading of each segment byte register This means that auto incremented loading of BANK A or BANK B is possible Either bank may be completely or partially loaded irrespective of which bank is being displayed Direct drive output waveforms are shown in Figure 4 OFF IU ON Vpp V ss p BP1 Sx V pp V ss aaa 015166 VDD BP1 Vss VDD Segment x Sx fi cp Von RMS Vpp Vss Vort RMs 0 Fig4 Direct drive mode display output waveforms
29. ice at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 29 of 33 NXP Semiconductors PCF8577C Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization
30. ithout further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the dev
31. ns as indicated on the packing must be respected at all times Studies have shown that small packages reach higher temperatures during reflow soldering see Figure 17 PCF8577C All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Rev 5 10 October 2014 22 of 33 Product data sheet PCF8577C LCD direct duplex driver with I C bus interface NXP Semiconductors maximum peak temperature MSL limit damage level temperature minimum peak temperature minimum soldering temperature peak temperature time 001aac844 MSL Moisture Sensitivity Level Fig 17 Temperature profiles for large and small components For further information on temperature profiles refer to Application Note AN10365 Surface mount reflow soldering description 17 Footprint information PCF8577C All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 23 of 33 NXP Semiconductors PC F8577C LCD direct duplex driver with I C bus interface Footprint information for reflow soldering of VSO40 package SOT158 1 0 125 TT 0 125 Y a nU B Ed Y i pa FT 7 7 i 1 E r Ig HY F G i toy I I l I I toy l I I 1 M inue zum D2 4x Bi P1 T Ik
32. onductors PCF8577C LCD direct duplex driver with I C bus interface Sx BP1 BP2 Fig 11 Driver timing waveforms y 0 5V Voo 5 V 0 5V 0 5V Voo 5 V 0 5V ri aaa 015185 SDA SCL HD STA Is SDA tsu STA tHD DAT tHIGH tsu DAT HM tsu STO mga728 Fig 12 I C bus timing diagram rise and fall times refer to Vi and Viy PCF8577C All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 16 of 33 Jays Lep 12npoid t LOZ 1920190 OL S 9H sieuirejosip eba 0 joefqns s jueuunoop S14 ui papiaoid uoneuuojul JY JO ZL 9449849d pamasa siuDu IV Y LOZ N N S1OJONPUO9IUES dXN 13 Application information Fig 13 DIRECT DRIVE LCD DISPLAY 32 33 VDD Cosc ROSC Vss SCL PCF8577C SDA device subaddress device subaddress A2 A1 A0 000 A2 A1 A0 001 PCF8577C backplane 256 A2 A1 A0 111 Direct display driver expansion to 256 segments using eight PCF8577Cs device subaddress aaa 015186 OEHEIUI SNA D YUM 4eAup xejdnpoeurp 021 JZZS8490d SJOJONPUODIWII
33. rovided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 27 of 33 NXP Semiconductors PC F8577C LCD direct duplex driver with I C bus interface 20 Revision history Table 14 Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8577C v 5 20141010 Product data sheet PCF8577C v 4 Modifications The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors Legal texts have been adapted to the new company name where appropriate Removed obsolete product types PCF8577C v 4 19980730 Product data sheet PCF8577C v 3 PCF8577C v 3 19970328 Product data sheet PCF8577C v 2 PCF8577C v 2 19950608 Product data sheet PCF8577C v 1 PCF8577C Product data sheet All information provided in this document is subject to legal disclaimers Rev 5 10 October 2014 NXP Semiconductors N V 2014 All rights reserved 28 of 33 NXP Semiconductors PCF8577C 21 Legal information LCD direct duplex driver with I C bus interface 21 1 Data sheet status Document status 1I2 Product status Definition Objective short data sheet Development This document contains data from the objective specification for product development Preliminary short data shee
34. rs product specifications Translations A non English translated version of a document is for reference only The English version shall prevail in case of any discrepancy between the translated and English versions 21 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I2C bus logo is a trademark of NXP Semiconductors N V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com PCF8577C All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 30 of 33 NXP Semiconductors PCF8577C LCD direct duplex driver with I C bus interface 23 Tables Table 1 Ordering information lusus 1 Table 2 Ordering options 00 eee 2 Table 3 Marking codes 002 cee eee 2 Table 4 Pin description 0 000 cee eee 4 Table 5 Segment byte segment driver mapping in direct drive mode 0 cee eeu 8 Table 6 Segment byte segment driver mapping in duplex mode 000e sneri wis 8 Table 7 C slave address byte 00 10 Table 8 Limiting values 0 0 0008s 12 Table 9 Static characteristics 13 Table 10 Dynamic characteri
35. stics 15 Table 11 SnPb eutectic process from J STD 020D 22 Table 12 Lead free process from J STD 020D 22 Table 13 Selection of LCD segment drivers 25 Table 14 Revision history 00e0 ee 28 PCF8577C All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 31 of 33 NXP Semiconductors PCF8577C 24 Figures LCD direct duplex driver with I C bus interface Fig 1 Fig 2 Fig 3 Fig 4 Fig 5 Fig 6 Fig 7 Fig 8 Fig 9 Fig 10 Fig 11 Fig 12 Fig 13 Fig 14 Fig 15 Fig 16 Fig 17 Fig 18 PCF8577C Block diagram of PCF8577C 2 Pin configuration for PCF8577CT 3 PCF8577C register organization 5 Direct drive mode display output waveforms 6 Duplex mode display output waveforms 7 Bittransfer 00 iiaeie eee 9 Definition of START and STOP conditions 9 System configuration 00000 10 Acknowledgement of the I amp C bus 10 I C bus protocols oeseri soured eese 11 Driver timing waveforms uses 16 I2C bus timing diagram rise and fall times refer to Vy and Vi eee eee 16 Direct display driver expansion to 256 segments using eight PCF8577Cs 0 17 Duplex display expansion to 2 x 128 segments using four
36. t Qualification This document contains data from the preliminary specification Product short data sheet Production This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 21 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the shor
37. t data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 21 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for an
38. to 85 C unless otherwise specified All the timing values are valid within the operating supply voltage and ambient temperature range and refer to Vi and Vj with an input voltage swing of Vss to Vpp Symbol Parameter Conditions Min Typ Max Unit ficp display frequency Rosc 1 MQ 65 90 120 Hz Cosc 680 pF tBs driver delays with test Vop 5V la 20 100 us loads I C bus fscL SCL clock frequency 100 kHz tsw tolerable spike width on Tamb 25 C 100 ns 12C bus tBUF bus free time between a 4 7 us STOP and START condition tsu sTA set up time for a repeated 4 0 us START condition HD STA hold time repeated 4 0 us START condition tLow LOW period of the SCL 4 7 us clock tHIGH HIGH period of the SCL 4 0 us clock tr rise time of both SDA and 1 0 us SCL signals tr fall time of both SDA and 0 3 us SCL signals tsU DAT data set up time 250 ns tHD DAT data hold time 0 ns tsu sTO set up time for STOP 4 0 us condition 1 Typical conditions Vpp 5 V Tamb 25 C 2 Test loads SCL SDA 15k0 32toS1 68kQ VDD Voo Vss 2 pins 39 40 pins 1 to 32 aaa 015184 PCF8577C All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 5 10 October 2014 15 of 33 NXP Semic
39. uplex mode se EE ER cee eee eee 6 Display memory mapping 7 Power on reset 2000e cece eee 8 2C bus interface 0000 cece eens 9 Characteristics of the I C Bus 9 Bit transfer sce eee hae fa ea le 9 START and STOP conditions 9 System configuration ee Ese see 9 Acknowledge ei EE EE ee ee 10 Slave address se EE GE ee se ee 10 I C bus protocol SESSE ESE cane 11 Safety notes issue EE EE MENEER hn 11 Limiting valueS see see see see ka eke 12 Static characteristics se se seke Rae 13 Dynamic characteristics 15 Application information 17 Package outline 20 Packing information 21 Tape and reel information 21 Soldering of SMD packages 21 Introduction to soldering 21 Wave and reflow soldering 21 Wave soldering 0 EE eee eee 21 Reflow soldering 0 e ee ae 22 Footprint information 23 Appendix is asses ss 0 ber aea 25 LCD segment driver selection 25 References slee sse 27 Revision history 00 e cece eens 28 21 Legal information seee 29 21 1 Data sheet status 000 29 21 2 Definitions RE RE RE EE de 29 21 3 Disclaimers SEE EE ee se ee 29 21 4 Trademarks SS SS eee 30 22
40. ve Solder bath specifications including temperature and impurities 16 4 Reflow soldering Key characteristics in reflow soldering are Lead free versus SnPb soldering note that a lead free reflow process usually leads to higher minimum peak temperatures See Figure 17 than a SnPb process thus reducing the process window Solder paste printing issues including smearing release and adjusting the process window for a mix of large and small components on one board Reflow temperature profile this profile includes preheat reflow in which the board is heated to the peak temperature and cooling down It is imperative that the peak temperature is high enough for the solder to make reliable solder joints a solder paste characteristic In addition the peak temperature must be low enough that the packages and or boards are not damaged The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12 Table 11 SnPb eutectic process from J STD 020D Package thickness mm Package reflow temperature C Volume mm lt 350 2 350 2 5 235 220 22 5 220 220 Table 12 Lead free process from J STD 020D Package thickness mm Package reflow temperature C Volume mm lt 350 350 to 2000 gt 2000 1 6 260 260 260 1 6 to 2 5 260 250 245 gt 2 5 250 245 245 Moisture sensitivity precautio
41. y reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof PCF8577C All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use w
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