rgo 32 bit counter manual
Contents
1. DOWN E y DOWN e i DOWN Figure 1 Truth table for a quad b type encoders 2 2 Up down type encoders The basic difference between this and the A quad B encoder are the two encoder outputs O P 1 amp O P 2 With up down encoders the phase detector circuit to determine in which direction the encoder is moving is internal to the encoder If A quad B type encoders are used the decoding circuitry is external and usually defined by the system designer If the up down encoder is moving in a clockwise direction the output will be on O P 1 and O P 2 will remain in a steady state However if the up down encoder moves in an anti clockwise direction the output will be on O P 2 and O P 1 will remain in a steady state The zero reference output on this type of encoder is identical to that described for the A quad B type encoders The decoder circuit for this type of encoder is described in section 4 9 The truth table for this type of encoder is shown in Figure 2 ENCODER O P 1 ENCODER O P 2 COUNT UP DOWN DOWN UP Figure 2 Truth table for up down type encoders 3 Reference and clock input signals 3 1 Input 1 Clock The clock input is a pulse train of 1 uSec wide pulses at a frequency of 20 Hz and is the rate at which the telescope computer system TCS samples data This signal is derived from the observatory Time Service s and is used to transfer the contents of the counter into the Data Output Regis2. isolator that will accept frequencies of at least 500 KHz and pulse widths down to 1 u second 1C35 to IC39 The circuit is capable of operating up to 1 MHz with suitable values for the monostable timing components defined in section 4 2 Schmidt trigger inverters IC28 29 40 amp 41 have been incorporated to ensure that all input pulse edges are sharp LK1 to LK7 provide the means to select between DC or AC coupling of the inputs By making the respective link the input is DC coupled and AC coupled when the link is removed For compatibility with existing drive circuits the nominal input current will be 5 mA and a 270 2 resistor is connected in series in the signal positive line Reverse voltage protection diodes have been provided D3 to D12 The signal return lines should not be linked or grounded 5 PAL programming information uses program RGO3DV1 the device is 825100 Checksum 5FE1 Manufacturer Signetics IC2 uses program 9003 5 the device 15 N82S23 Checksum 1c47 Manufacturer Signetics IC4 uses program 9003BA the device is N82S23 Checksum 1DE8 Manufacturer Signetics IC31 uses program 9004V0 the device is 16L8 Checksum 5753 Manufacturer Signetics 1C32 uses program 9005VO the device is 16L8 Checksum 5780 Manufacturer Signetics 1C33 uses program 9002V1 the device is 16R4 Checksum 2C76 Manufacturer Signetics 1C34 uses program 9002V1 the device is 16R4 Checksum 2C76 Manufacturer Signe
3. M status register before the mask Read the 8 bit LAM mask register Read the active LAM s after the mask Read and clear the LAM status register Test LAM Clear the counter Clear all LAM s Clear the LAM mask register Bitwise set the LAM mask register Bitwise clear the LAM mask register Disable the zero marker counter facility Disable the LAM This kills all LAM s enabled Disable the encoder zero reference strobe Enable the zero marker counter facility Enable LAM enables all mask enabled LAM s Enable the encoder zero reference strobe Test the zero marker counter clear facility Test the LAM enable flag Test the encoder zero reference strobe enable flag Q 1 X 1 Q 1 X 1 Q 1 X 1 Q 1 X 1 Q 1 X 1 Q 1 X 1 1 LAM unmasked Q 1 X 1 Q 1 X 1 Q 1 if LAM is set and enabled X 1 Q 0 X 1 Q 0 X 1 Q 0 X 1 Q 1 X 1 I status bit enabled Q 1 X 1 O status bit cleared Q 0 X 1 Q 0 X 1 Q 0 X 1 Q 0 X 1 Q 0 X 1 Q 0 X 1 Q 1 if enabed X 1 Q 1 if enabled X 1 Q 1 if set X 1 12 8 Circuit diagram Copy kept with CAMAC master drawings and manuals in INT Electronics workshop filing cabinet 13
4. R G O 32 BIT CAMAC COUNTER MODULE USER MANUAL C S Amos D J Steel 16th August 1993 Copyright O R G O August 1993 1 General description 2 Encoder formats 2 1 quad B type encoders A 2 2 Up down type ENCOders 3 Reference and clock input signals J1 Input A Roni ata O RD angu 3 2 Input 2 Zero Set marks ROSSAS 3 3 Input 3 Encoder zero reference sees eee eee 3 4 Inputs 4 5 6 amp 7 Datum markers 4 Circuit description 4 1 Power resel saia acide acini ented 4 2 Anti coincidence and timing circuits sees eee eee 4 3 LAM status FALAM mask TESS esa e qa 4 5 COUDES ui tas 4 6 Data OUTPUT ISS 4 7 Data Oul put s aia 4 8 Camac function decoder 4 9 Encoder input phase detector a 4 10 Optically coupled input 1 1 eee 5 PAL programming information 6 Front panel connections 7 Decoded CAMAC function commands 8 Circuit diagram 10 11 12 13 1 General description The Encoder Counter Module is a 32 Bit binary up down counter intended to determine absolute telescope positions from an incremental encoder which may be a rotary optical linear optical or inductive tape encoder The design is based on the 28 bit binary up down counter designed by RGO and manufactured by Grubb Parsons An enhanced ve
5. REGISTER BIT CAMAC READ LINE DESCRIPTION 1 0 R1 CLOCK ZERO SET MARKER ENCODER ZERO REFERENCE DATUM MARKER 4 DATUM MARKER 5 DATUM MARKER 6 DATUM MARKER 7 UNUSED Figure 3 Lam status register bit allocation 4 4 LAM mask register The LAM mask register IC33 amp IC34 designed using two PAL 16R4 IC s may be programmed to allow individual bits within the LAM status register to be masked out or ignored when the status register is read Individual bits in this register may be set using the CAMAC function code F19 A13 followed by the 8 bit mask word or cleared using the CAMAC function code F23 A13 followed by the 8 bit mask word The current stored mask may be read using the CAMAC function code F1 A13 4 5 Counters The 32 bit binary counter is constructed from eight 4 bit binary counters IC10 to IC16 amp IC62 that have been cascaded using the carry and borrow lines If pulses are received from IC48 pin 8 the counter will count up If pulses are received from IC48 pin 6 the counter will count down The counters may be cleared using the CAMAC function code F9 AO or automatically if the zero marker input has been enabled and a pulse is received on that line The outputs of the counters are fed to the Data Output Registers see section 4 6 and also to the front panel LED s 4 6 Data output registers The Data Output Registers 1C17 to IC23 amp IC50 hold information from the counters which is dependant on the
6. it around and is made up of R1 2 3 D2 D13 C3 TR1 and IC47B This circuit ensures that the chip enable lines of IC1 and IC4 are held in the inactive state until the power supply has stabilized 4 2 Anti coincidence and timing circuits 1C24 25 amp IC26 are monostables that have been incorporated to prevent the loss of a count or a false value being transfered into the Data Output Registers in the event of any of the inputs referred to in section 3 being coincident with a count pulse Allowances have also been made for the propagation times through the cascaded counters With the component values shown on the circuit diagram for R24 R25 R27 R28 C18 C19 C20 and C21 the input circuit will operate up to 500 KHz By changing the value of these components it is possible for the input circuit to operate up to 1 MHz 4 3 LAM status register This register IC5 amp IC60 is an 8 bit register which is set if any of the inputs referred to in section 3 become active The LAM status register may be read using the CAMAC function code Fl 12 or F2 12 and cleared using the CAMAC function code F10 AO When this register is read the contents of it is fed onto the CAMAC data bus lines to R8 via the Data Output Buffer The LAM status register may be read in conjunction with the LAM mask register to ignore any of the inputs see section 4 4 below The bit allocation for the LAM status register is shown in Figure 3 INPUT
7. rsion was developed by HYTEC Electronics using PLD technology to rationalise the circuitry this also had the benefit of reducing the size from a triple to a single width module The design was further developed by RGO to give 32 bit counts to satisfy the requirement for the high resolution WHT Azimuth tape encoder experiment Features of the new unit are 32 bit counting C A D design multi layer PCB configurable encoder input circuitry clearer front panel display and legend buffering of all BUS signals and as before PLD technology 2 Encoder formats 2 1 A quad B type encoders A quad B format encoders have two outputs O P 1 amp O P 2 which are 90 electrically displaced and a zero reference output that occurs when the encoder reaches its reference position ie 1 pulse per rev In order to determine the direction in which the encoder is rotating we need to establish which of the two outputs O P 1 or O P 2 is leading the other If O P 1 is leading the encoder is rotating in a clockwise direction and the counter needs to count up When O P 2 is leading the encoder is rotating in an anti clockwise direction so the counter needs to count down The decoder circuit for this type of encoder is described in section 4 9 The truth table for the decoding required for this type of encoder is shown in Figure 1 ENCODER O P 1 ENCODER O P 2 COUNT L UP 1 H 4 UP LEADING y i T L y UP DOWN oP 1 T LAGGING
8. software configuration of the board Register 1 contains the current count from the counters 1 LSB ready to be passed to the CAMAC data bus when this register is read This register is updated when the count changes but is not updated if the register is being read This register may be read by means of two CAMAC function codes as follows FO AO reads the lower 16 bits of the current count FO Al reads the upper 16 bits of the current count Register 2 contains the count at which the zero marker encoder zero reference or any of the datum markers were passed Dependant on which were enabled This register may be read by means of two CAMAC function codes as follows FO A2 reads the lower 16 bits of the marker count FO A3 reads the upper 16 bits of the marker count In Reading either of these registers the output is fed to the Data Output Buffer and then through to the CAMAC data bus The R1 bit of the CAMAC data bus is the LSB in all cases 4 7 Data output buffer The Data Output Buffers 1C45 51 amp IC59 are the interface between the internal data bus on the counter encoder module and the CAMAC data bus The buffers are non inverting and have open collector outputs to drive onto the CAMAC data bus 4 8 Camac function decoder circuit The CAMAC control interface is made through which provides the decoding required for the function codes to activate individual functions within the circuit 1C2 3 4 27 61 and a
9. ssociated components provide the local decoding for the LAM status register mask register and the data output registers 4 9 Encoder input phase detector As defined in section 2 the encoder output format may be up down or A quad B In order to make the counter module universal the user can select which input format is required by means of the X1 X4 mode link on the PCB X4 selected UP DOWN ie For Ferranti encoders X1 selected A QUAD B ie For Baldwins Heidenhain If the A quad B encoder format is selected then each edge from each of the two encoder outputs O P 1 amp 2 will produce a time pulse generated from monostables IC7a IC7b IC8a and IC8b These pulses are then fed into a PAL 14L4 1 9 which has been programmed to operate as a phase detector The phase detector will determine which encoder output O P 1 or O P 2 is leading and hence in which direction the counter is required to count If the counter is required to count up encoder moving clockwise pulses will be fed to the count up line of the counter from IC9 pin 14 with the count down line of the counter from IC9 pin 16 remaining in a steady state However if the counter is to count down encoder moving anti clockwise IC9 pin 14 will be in a steady state and pulses will fed to the count down line on the counter from IC9 pin 16 4 10 Optically coupled input isolators Each input is taken from a twisted pair line to a low input current optically coupled
10. ter 1 3 2 Input 2 Zero set marker The purpose of this input is to indicate when a known position on the telescope has been reached normally the zenith The leading edge of this pulse transfers the counter contents into Data Output Register 2 If this zero set marker signal becomes active and it has been enabled the current counter contents will be transfered into Data Output Register 2 and Data Output Register 1 will be cleared This signal may be enabled using the CAMAC function code F26 AO which will also clear Data Output Register 1 or disabled using the CAMAC function code F24 AO nb This command will also tranfers the contents of DOR 1 into DOR 2 but does NOT clear the contents of DOR 1 3 3 Input 3 Encoder zero reference This signal indicates when a known position on the encoder has been reached ie The 1 pulse per rev signal The leading edge of this pulse transfers the counter contents into Data Output Register 2 Enabling this input can be achieved by using the CAMAC function code F26 A2 or disabled using the CAMAC function code F24 A2 3 4 Inputs 4 5 6 amp 7 Datum markers These signals are all identical in operation to Input 2 the zero set marker except for the ability to zero the count All these signals when active will transfer the counter contents into Data Output Register 2 4 Circuit description 4 1 Power on reset A Power On Reset circuit has been included for the CAMAC function decoder circu
11. tics IC9 uses program 9003V0 the device is GAL16V8 was 1414 Checksum 286b Manufacturer National 10504 10 6 Front panel connections With the exception of the clock all input pulses are made through the 37 way D type plug on the front panel of the module The clock input is made through a tri axial lemo socket type 0650 The pin allocations for the 37 way D type connector are defined in Figure 4 1 DATUM MARKER 7 SIGNAL 20 DATUM MARKER 7 RETURN 2 DATUM MARKER 6 SIGNAL 21 DATUM MARKER 6 RETURN 3 DATUM MARKER 5 SIGNAL 22 DATUM MARKER 5 RETURN 4 DATUM MARKER 4 SIGNAL 23 DATUM MARKER 4 RETURN 5 ENCODER ZERO REF 24 ENCODER ZERO REF RETURN 6 ZERO MARKER 25 ZERO MARKER RETURN 7 ENCODER O P 1 26 ENCODER O P 1 RETURN 8 ENCODER O P 2 27 ENCODER O P 2 RETURN 9 N C 28 N C 10 N C 29 11 N C 30 N C 12 N C 31 NIC 13 N C 32 14 N C 33 15 N C 34 16 N C 35 6V SUPPLY 17 N C 36 COMMON 18 N C 37 GROUND CABLE SCREEN 19 N C FIGURE 4 37 WAY D TYPE PIN ALLOCATIONS 11 7 Decoded CAMAC function commands command function Q and X response F0 AO F0 Al F0 A2 F0 A3 F1 A12 F1 A13 F1 A14 F2 A12 F8 A15 F9 AO F10 AO F11 A13 F19 A13 F23 A13 F24 AO F24 A1 F24 A2 F26 AO F26 A1 F26 A2 F27 AO F27 A1 F27 A2 Read 16 L S B of register 1 Read 16 M S B of register 1 Read 16 L S B of register 2 Read 16 M S B of register 2 Read the LA
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