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GE Fanuc / SBS Power7E Manual

1. 22 PMCIO29 23 SDP1 PMCIO46 VMED24 45 PMCIO30 24 GND PMCIO48 VMED25 PMCIO47 PMCIO31 25 NC 50 VMED26 PMCIO49 PMCIO32 26 GND 52 VMED27 PMCIOS1 PMCIO33 27 NC PMCIO54 VMED28 53 PMCIO34 28 GND 56 VMED29 55 PMCIO35 29 UART 58 VMED30 57 PMCIO36 30 GND PMCIO60 VMED31 59 PMCIO37 31 UART RXI PMCIO62 GND PMCIO61 GND 32 GND PMCIO64 PMCIO63 Asterisks indicate connections that depend on the placement of A B Resistors as indicated on pages 3 2 and 3 3 of this manual A 2 Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 3 Row 2 1 0 An optional version of the P7E has only three rows of pins Row and on the VME 2 connector In order to provide 2 via the P2 connector in this version VART_TX1 is provided A29 UART RXI is provided on pin A31 Therefore it is necessary to verify you use the correct Transition Module Both versions of the P7E TM Transition Module have the 5 Row con nector but the one intended for the 3 Row P7E is modified to accept COM2 I O on row A Pin Row A Row B Row C 1 P2 IOAI PMCIO1 2 P2_IOA2 GND PMCIO3 3 P2 IOA3 NC 5 4 2 4 VMEA24 PMCIO7 5 2
2. rtisan tisan Technology Group is your source for quality new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment EQUIPMENT DEMOS HUNDREDS OF InstraV ea REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED Contact us 888 88 SOURCE sales artisantg com www artisantg com Power E Technical Manual SBS preferred Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS preferred Power E PowerPC VMEbus Single Board Computer Technical Manual Copyright 2002 by SBS Technologies Inc Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www
3. A special interface provides for the generation of any PCI command including type 1 configuration cycles Support for shared memory locally mapped to the processor s ROM or SDRAM using PCI Base Address Registers Buffered PCI writes and supports PCI read pre fetching from local memory Hardware enforced cache coherency PCI bus arbitration using a fixed priority arbitration algorithm 2 2 Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CPC700 incorporates a fixed processor address map that serves the Power PC family of processors The address map has provisions for ROM RAM and Mapping can be performed solely from the processor side or from com bination of the processor and PCI side The address map of the 700 is given on the following page The CPC700 PowerPC and the CPC700 PCI bus interfaces include the follow ing functions 1 CPC700 PowerPC interface Interfaces to PowerPC 750 One level of processor address pipelining Processor Bus Arbiter Bus snooping support during PCI access to local memory 32 byte write buffer to memory Address only cycle support Error tracking status for processor transaction Low latency access path to local memory The CPC700 PCI interface 32 bit PCI address bus PCI bus clock up to 66 MHz 33 MHz synchronous up to 66 MHz asynchronous Processor to PCI ac
4. 5 VMEA25 PMCIO9 6 P2_IOA6 VMEA26 PMCIO11 7 P2_IOA7 VMEA27 PMCIO13 8 P2_IOA8 VMEA28 P2_IOC8 9 P2_IOA9 VMEA29 P2 10 9 10 2 10 VMEA30 P2 0 11 P2 IOAII VMEA31 P2 IOCII 12 P2 12 GND P2 IOCI2 13 P2 13 P2 14 P2 14 VMEDI6 P2 IOCIA 15 P2 15 VMEDI7 P2 IOCI5 16 P2 16 VMEDIS8 P2 16 17 P2 17 VMEDI9 P2 IOCI7 18 P2 18 VMED20 P2 IOCIS 19 PMCIO38 VMED2I P2 19 20 40 VMED22 P2 IOC20 21 PMCIO42 VMED23 P2 IOC21 22 PMCIO44 GND P2 IOC22 23 46 VMED24 PMCIO45 24 48 VMED25 47 25 50 VMED26 PMCIO49 26 52 VMED27 51 27 54 VMED28 53 28 56 VMED29 55 29 UART TXI VMED30 57 30 60 VMED31 59 31 UART RXI GND PMCIO61 32 PMCIO64 63 Appendix VME64 Information Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com M3 This page is intentionally blank Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com rtisan tisan Technology Group is your source for quality new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilize
5. 154 155 156 157 158 159 SCSI Data 7 A or 16 B X 160 162 163 164 SCSI ATN A or PMCIO20 X 165 Printer Data Bit 2 A or PMCIO21 B X Power7E Jumper Definitions 3 2 Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Power7E Resistor configuration options continued from previous page Resistor Description A B 166 SCSI BSY A or PMCIO22 B X 167 Printer Data Bit 3 A or PMCIO23 B x 168 SCSI ACK A or PMCIO24 X 169 Printer Data Bit 4 A or PMCIO25 X 170 SCSI RST A or PMCIO26 B X 172 Printer Data Bit 5 or 27 B X 173 SCSI MSG A or PMCIO28 X 174 Printer Data Bit 6 A or PMCIO29 B X 175 SCSI SEL A or PMCIO30 X 176 Printer Data Bit 7 A or PMCIO31 x 177 Printer INIT A or PMCIO41 B X 178 Printer SLCT A or PMCIO39 B X 179 SCSI C D A or PMCIO32 B X 181 Printer ACK A or PMCIO33 B X 182 SCSI REQ A or PMCIO34 B X 183 Printer BUSY or PMCIO35 X 184 SCSI I O A or PMCIO36 B X 185 PPE or PMCIO37 X 197 L2 Cache 750 or 7400 X Power7E Jumper Definitions Configuration 3 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com This page is intentionally blank Power7E Technical Manual Artisan Technology Group Quality Instrumentation
6. Base Board ID bits see table 5 MO2IDI 0 Mezzanine 2 ID bits see table 5 MIIDI 0 Mezzanine 1 ID bits see table 5 PLDH3 0 PLD revision upper bits represents ones place of revision PLDL3 0 PLD revision lower bits represents tenths place of revision 4 2 Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com DRAM DT DRAM Type Baseboard and Mezzanine 1 8 2 BBID1 BBIDO Meaning M1ID1 M1ID1 21 1 M2IDO 0 0 256M SDRAM 0 1 128M SDRAM I 0 64M SDRAM 1 1 SDRAM FB FlashBank Bit Definition FB1 FBO Meaning 0 0 FlashBank 4 0 1 FlashBank 3 1 0 FlashBank 2 1 1 FlashBank 1 CR Cache Ratio Bit Definition CR2 CR1 CRO Meaning 0 0 0 L2 Clk amp DLL Disabled 0 0 1 1 1 0 1 0 1 5 1 0 1 1 Reserved 1 0 0 22 1 0 1 2 5 1 1 1 0 3 1 1 1 1 Reserved Memory Map 4 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com This page is intentionally blank Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CHAPTER 5 Specifications General Model Description Hardware Compatibility VMEbus Controller Configuration Interrupter Interrupt Handler Requester Arbiter Block Mode Transfer CPU IBM PCI Bus Controller Clock Rate
7. Guaranteed 888 88 SOURCE www artisantg com CHAPTER 4 Chapter Scope Device ID The Power7E memory mapping is extremely flexible There are only a couple of restrictions imposed by the memory controller 1 At least 1M byte of system memory must be mapped to address 0 2 The upper 8M bytes of the CPU address space is reserved for PROM Aside from these two requirements the only restrictions are those imposed by system interoperability issues The PCI devices can naturally per PCI spec be located anywhere in the PCI address space The PCI memory and I O spaces can be located anywhere within the CPU memory space The 8 bit I O devices can be located anywhere within the first 2M of CPU address space Since PCI peripherals are mapped into the PCI memory and I O spaces during system configuration it is only relevant to list the PCI address data lines con nected to IDSEL lines of the PCI peripherals Within the PCI configuration space the following device ID selects are used Device ID Selects ID Select 1 0 Device Device Part Number ADI2 SCSI 53C875 ADI3 Ethernet INTEL 82559ER AD14 VME Bridge Universe IIb 15 PMC Slot Connector P12 16 PMC Slot IDSELB Connector P12 The software will map these devices into PCI memory space at boot time Memory Map 4 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Power On Default The
8. Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 6 4 This page is intentionally blank Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com APPENDIX 64 1 0 Information VME64 P1 1 0 The following table shows the standard VME64 P1 I O Mapping Pin Row Z Row A Row B Row RowD 1 NC VMEDO VMEBBSY VMED8 2 GND VMEDI VMEBCLR VMED9 GND 3 NC VMED2 VMEACFAIL VMED10 NC 4 GND VMED3 VMEBGINO VMED11 NC 5 NC VMED4 VMEBGOUTO VMEDI2 NC 6 GND VMED5 VMEBGINI Z VMEDI3 NC 7 NC VMED6 VMEBGOUTI Z VMED14 NC 8 GND VMED7 VMEBGIN2 VMEDIS5 NC 9 NC GND VMEBGOUT2 GND NC 10 GND VMESYSCLK VMEBGIN3 VMESYSFAIL NC 11 NC GND VMEBGOUT3 VMEBERR NC 12 GND VMEDS1 VMEBRO VMESYSRST NC 13 NC VMEDSO VMEBRI VMELWORD NC 14 GND VMEWR VMEBR2 VMEAMS5 NC 15 NC GND VMEBR3 VMEA23 NC 16 GND VMEDTACK VMEA22 NC 17 NC GND VMEAMI VMEA21 NC 18 GND VMEAS VMEAM2 VMEA20 NC 19 NC GND VMEAM3 19 NC 20 GND VMEIACK GND 8 21 VMEIACKIN NC VMEAI7 NC 22 GND VMEIACKOUT NC VMEAI6 NC 23 NC VMEAM4 GND VMEAI5 NC 24 GND VMEA7 VMEIRQ7 VMEA14 NC 25 NC VMEA6 VMEIRQ6 VMEA13 NC 26 GND VMEAS VMEIRQS VMEA12 NC 27 NC VMEA4 4 28 GND
9. REQ REQ3 GNT GNT3 For further information on the PMC specification refer to PCI Local Bus Specifica tion Revision 2 1 PCI Special Interest Group Draft Standard for a Common Mez zanine Card Family CMC Standards Department P1386 Draft 2 0 and Draft Stan dard Physical and Environmental Layers for PCI Mezzanine Cards PMC IEEE Stan dards Department P1386 1 Draft 2 0 Detailed Description by Device 2 7 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SCSI Interface Parallel Port Exar ST78C36CQ64 2 8 The Symbios 53C875 provides a SCSI 3 interface capable of transferring 40 MB sec in Ultra Wide synchronous mode The SCSI signals are terminated on the Power7E board using Unitrode UC561DP active terminators and are then brought out to the VME P2 connector SCSI peripherals can be plugged into the SCSI interface using an I O module that plugs into the VMEP2 connector behind the VME backplane or through a cable that has a mini DB 50 5 51 2 connector on its front panel The upper 8 bits of the SCSI data bus are routed to the Z row on P2 so use of Ultra Wide SCSI requires a 5 row transition module such as the SBS P7E TM The 53C875 is a PCI peripheral and as such it contains several PCI configuration registers It also contains registers for controlling the SCSI operation known as operating registers The operating registers are also accessible via the PCI
10. Air Operating 40 to 85 Celsius Non Operating Forced Air 100LFM Fan Recommended 10 to 95 Relative Humidity Non Condensing 10 Hz to 500 Hz 2G 20G 6mS Power7E Technical Manual CHAPTER 6 Support Service and Warranty Chapter Scope Warranty Statement If You Have a Problem with an SBS Product The following sections describe SBS Technologies product support program It states our product warranty terms and provides details about what action to take if you experience a problem with the product SBS Technologies VMEbus products come with a return to factory warranty that covers defects in materials and workmanship for a period of two years from the date of product shipment to the customer original purchaser provided the product is unmodified and has been subject to normal and proper use This war ranty applies to all standard board level products that do not incorporate disk drives Products which incorporate floppy or hard disk drives are also warranted for two years with the exception of the drives themselves The drives will be warranted for a period of ninety days as is the normal period for electro mechanical components SBS Technologies Inc makes no warranty or repre sentation express or implied with respect to software its performance quality or fitness for a particular purpose This does not include the media on which the software is distributed which carries a warranty covering defects in mater
11. COP emulator interface to 750 processor is provided via JP1 a keyed 2 Emulator Port x 8 header pinouts of the connector are defined below JTAG 2 x 8 Header Pin Assignments Pin Signal Signal Pin 1 TDO QACK_IN 2 3 TDI TRST 4 5 QREQ OUT 3 3V thru Ohm 6 7 TCK NC 8 9 TMS NC 10 11 SRESET NC 12 13 HRESET Key No Pin 14 15 CKSTP_OUT GND 16 Detailed Description by Device 2 13 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 2 14 This page is intentionally blank Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CHAPTER 3 Configuration Chapter Scope Jumper Configuration This chapter provides information regarding configuration options and require ments for the Power7E Jumper JP2 Boot Flash Select Jumpers JP3 JP4 ems Flash Write t Enable Jumper JP15 SCSI Terminator Select Power7E Jumper Locations Power7E Jumper Definitions Jumper Name Installed Removed JP2 Boot Flash Select Boot to Socketed Device Boot to Soldered device JP3 StrataFlash Write Enable Writes Allowed Write Protected JP4 Boot Flash Write Enable Writes Allowed Write Protected JP15 SCSI Termin
12. If You Have a Problem with an SBS Product Product Repairs Appendix VME64 IO Information VME64 P1 I O VME64 P2 I O 3 Row P2 I O Contents Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 2 1 2 1 2 2 2 2 2 2 2 2 2 4 2 5 2 6 2 6 2 7 2 7 2 8 2 8 2 9 2 10 2 11 2 11 2 12 2 13 2 13 4 1 4 1 4 1 4 2 4 2 4 3 5 1 6 1 6 1 6 1 6 1 6 2 1 1 A 2 A 3 iv This page is intentionally blank Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com cHAPTER 1 Introduction VMEbus 1 Connector VMEbus P2 Connector JTAG COP Connector JP1 2 PMC Expansion Connectors CPU Under Heatsink Memory Mezzanine Connectors N a PMC Access m a Bw E i 7 Area Reset N Bm B LED Displays Ethernet Narrow SCSI Serial Port Connector Connector Overview The Power7E is a high performance 6U VME64 single board computer designed for use in a wide variety of computing applications It provides everything a user could want in a basic computer including a fast CPU a large amount of fast SDRAM memory with ECC a large amount of non volatile storage and a Fast Ethernet interface The Power7E does all t
13. VMEA3 VMEIRQ3 VMEA10 NC 29 NC VMEA2 VMEIRQ2 VMEA9 NC 30 GND VMEIRQI VMEAS8 NC 31 NC 12 NC 12v GND 32 GND Appendix VME64 Information 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com VME64 2 1 0 This table shows the standard VME64 2 I O Mapping Pin Row Z Row A Row B Row C Row D 1 PMCIO39 P2 IOAI PMCIO1 PMCIO2 2 GND P2 IOA2 GND PMCIO3 PMCIO4 3 PMCIO41 P2 IOA3 NC 5 PMCIO6 4 GND P2 IOA4 VMEA24 PMCIO7 PMCIO8 3 PMCIO43 P2 5 VMEA25 PMCIO9 PMCIO10 6 GND P2_IOA6 VMEA26 PMCIO11 PMCIO12 7 SD8 P2_IOA7 VMEA27 PMCIO13 PMCIO14 8 GND P2 8 VMEA28 P2_IOC8 PMCIOI5 9 SD9 P2 IOA9 VMEA29 P2 IOC9 PMCIO16 10 GND 2 10 VMEA30 P2_IOC10 17 11 SD10 P2 11 VMEA31 P2 IOCII PMCIO 18 12 GND P2 12 GND P2 IOCI2 PMCIOI9 13 SD11 P2_IOA13 P2 PMCI O20 14 GND 2 14 VMEDI6 P2 IOCIA PMCIO21 15 SD12 P2_IOA15 VMEDI7 P2 15 PMCIO 22 16 GND P2 IOA16 VMED18 P2_IOC16 PMCIO 23 17 SD13 P2_IOA17 VMEDI9 P2 IOCI7 PMCIO 24 18 GND P2 18 VMED20 P2 IOCIS PMCIO 25 19 SD14 PMCIO38 VMED21 2 19 PMCIO 26 20 GND PMCIO40 VMED22 2 20 PMCIO27 21 SD15 PMCIO42 VMED23 P2 21 PMCIO 28 22 GND 44 GND 2
14. artisantg com SBS preferred Power7E Technical Manual Document Number A 945 MN 04548 01 Part Number 9100 31 046 01 Revision 01 This manual applies to the Power7E Single Board Computer revision 00 and above until superceded Revision Date By Comments 08 27 2001 jev Current Preliminary Manual 09 24 2001 jev Updated CPU speed from 500MHz to 533MHz 11 01 2001 jev Assorted corrections typos and updates 02 21 2002 jev Appendix is updated to account for 3 Row P2 connector 05 02 2002 jev Update Specs and typo corrections 08 29 2002 jev Add JTAG COP to drawing on Page 1 1and Table on Page 2 13 The information contained within this document has been carefully checked and is believed to be entirely reliable and consistent with the product that it describes However no responsibility is assumed for inaccuracies SBS Technologies Inc assumes no liability due to the application or use of any product or circuit described herein SBSTechnologies Inc reserves the right to make changes to any product and product documentation in an effort to improve performance reliability or design Furthermore the information contained herein is of a proprietary nature and is not to be reproduced without prior written consent of SBS Technologies Inc IBM is a trademark of International Business Machines Corporation Tundra and Universe are trademarks of Tundra Semiconductor Inc This manual uses some generally accepted conventions f
15. be in its original shipping carton if possible Otherwise the product should be carefully packaged in a conductive packing material and placed in a cushioned corrugated carton suitable for shipping Please mark the shipping label with the RMA number and return it to Customer Service Department Att RMA put RMA number here SBS Technologies Inc 6301 Chapel Hill Road Raleigh NC 27607 Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Providing Product Defect Report When you are returning a product for repair it is very important to include a written report which details the nature of the problem in order to expedite the repair Please make sure that the following information is included RMA Number Product Serial Number Contact Phone Description of the Problem Defect Warranty Repairs Any product returned and found to be under warranty will be repaired or replaced at the discretion of SBS Technologies Non Warranty Repairs If a product 1s found not to be under warranty we will notify you of the non warranty situation and provide you with a fixed cost and a schedule for the repair Non warranty repairs generally require that a purchase order be issued to SBS Technologies Inc for the amount of the repair before repairs are under taken SBS Technologies Support Service and Warranty 6 3 Artisan Technology Group
16. power on default 8 bit I O addresses for the Power7E 8 bit peripherals are 8 Bit Addresses shown below 8 Bit Peripherals 8 Bit Peripheral 8 Bit Memory Address M48T37 NVRAM FFE8 0000 FFEF M48T37 RTC FFEF FFF0 FFEF FFFF Boot Flash 0000 FFFF Parallel Port Standard Mode FFFF FD00 FFFF FDFF DRAM Type Register FFFF FF00 FlashBank Miscellaneous Register FFFF FF04 Cache Ratio Register FFFF FF08 PLD Revision Register FFFF FFOC Miscellaneous Miscellaneous Registers Register Map 1 0 Address FFFF FFOO FFFF 04 FFFF FF08 FFFF FFOC Name DRAM FlashBank Misc Cache Ratio PLDRev Description See Below See Below See Below See Below Type R W R W R W R W Bit 7 BBIDI X PLDH3 Bit 6 BBIDO 0 X PLDH2 Bit 5 X X X PLDHI Bit 4 X SSLOT X PLDHO Bit 3 M2IDI MISC X PLDL3 Bit 2 M2IDO ULED2 CR2 PLDL2 Bit 1 MIIDI BITF CRI PLDLI Bit 0 MIIDO ULEDI CRO PLDLO Reset Value CC00 110 0000 0000 CCCC X bit value doesn t matter reads as 0 C bit value depends on board configuration CR2 0 Cache Ratio see CR bit definition table 7 FB1 0 Flash Bank bits see FB bit definition table 6 SSLOT 1 indicates that board is installed in System Slot This bit is read only MISC 1 bit R W register 1 turns on BITFAIL LED 0 turns it off ULEDI 1 turns on USERLEDI 0 turns it off ULED2 1 turns on USERLEDJO 0 turns it off BBID1 0
17. 28M base board memory size Mapping for the mezza nine module depends on the baseboard size and mezzanine module memory Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Boot Flash Memory UART A socket 018 provides 512K bytes of flash memory organized as 512K x 8 The socket is a 32 pin PLCC socket The socket can also be used to interface to a ROM emulator The 512K byte flash is an AMD 29F040B or equivalent and resides at FFFO 0000 to FFF7 FFFF when selected as the boot flash following reset the processor begins executing at FFFO_0100 When the processor accesses the flash the memory controller buffers eight accesses before presenting 64 bits of data to the processor It should be noted that the boot flash memory space is partially decoded so duplicate images of the 512K byte flash device exist in the 2M byte boot space provided by the CPC700 memory controller The Power7E also contains an additional 4 16MB of soldered in flash This flash is an INTEL StrataFlash and can be used as the boot flash by removal of a jumper on the board When the Strataflash is used as the boot flash the 512K byte flash chip enable is routed to the on board location and addresses FF80_0000 FF87_FFFF Strataflash are mapped to FFFO 0000 7 FFFF To accomplish this the two flash devices share chip select signals depending on whether the boot jumper on th
18. 8 SOURCE www artisantg com cHAPTER 2 Detailed Description by Device Block Diagram This section describes the Power7E by looking at the individual hardware devices used on the board A block diagram of the Power7E is shown below Backside L2 Cache 1M P2 Connector 8 bit Parallel Port PowerPC Flash Memory 522150 750 Intel 512kB 400 500 MHz 16MB NVRAM RTC Miscellaneous 585 SDRAM SDRAM Board Registers Thompson 64MB 256MB 64MB 256MB Custom Logic M48T37 2 Serial Ports Base Board Mezzanine COM1 front panel COM2 on P2 Bridge IBM CPC700 up to 66 MHz Front Panel and P2 VME Interface PMC Slot with P2 I O SCSI Ethernet Symbios INTEL Tundra 530875 82559ER Universe IIB Detailed Description by Device 2 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CPU IBM PowerPC 750 The Power7e is designed for a PowerPC 750 at 400 500M Hz PowerPC 750 SY SCLOCK is driven at 66M Hz A range of SY SCLK to CPU core speed multipliers is supported as follows PLL Resistor 6x 7 5 Bit 400MHz 500MHz 0 R120 1 0 1 R119 1 0 2 R118 0 0 3 R117 1 1 JTAG Port JTAG Emulator port is provided by a keyed 2 x 8 header on the board JTAG J oint Test Action Group IEEE Standard 1149 1 protocol contains commands to read set the values of the pins and internal registers of devices JTAG fa
19. FF Processor Interface 50 0000 50 0004 Registers Memory Controller FF50_0008 FF50_000C Registers OPB Macro Registers 50 0810 50 0818 PLB Macro Registers FF50_0850 FF50 085 Interrupt Controller FF50_0880 FF50 08A0 Clock and Power FF50 0900 FF50 0914 Management Internal Peripherals FF60 0000 FF7F FFFF 2MB UARTO FF60 0300 FF60 0309 UARTI FF60 0400 FF60 0409 62 0000 62 0010 63 0000 FF63 0010 Timers FF65_ 0000 FF65_ 0024 Local Memory Peripherals FF80_0000 FFDF FFFF 6MB Boot ROM FFEO 0000 FFFF FFFF 2MB The Power7E contains 64M 128M 256M bytes of on board SDRAM The ECC function can be tested using ECC control registers contained in the 700 Pop ulating the memory locations with 8M x 8 devices results in a baseboard memory size of 64M bytes An option is available to install a mezzanine board to increase the amount of memory The mezzanine memory board has a standard SODIMM connector to allow different memory configurations The mezzanine can either be 64M 128M or 256M bytes resulting in a maximum of 512M bytes of SDRAM The memory runs at 66MHz The bank of memory on the baseboard uses CS1 chip select 1 The mezzanine module s will use CS2 CS4 While the memory controller allows any bank to be mapped to any address it is necessary for one bank to be mapped to 1 for the exception handlers In general bank0 CS1 will be mapped to 0 for accesses from 0 07 FFFF for 1
20. IB nc SONNE 3 CPC700 33MHz 33MHz SYM53C895 PMC Slot lt gt Ultra 2 SCSI 40MHz 33MHz Controller Y INTEL 82559 25MHz Ethernet Controller Transceiver Detailed Description by Device 2 11 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Reset Logic A diagram of the Power7E reset logic is shown below Power On Reset ADM707 Manual Push Button Reset VMESYSRST Flash Reset VXSYSRST Flash lt 6 6 VRSYSRST HRST gt 750 SRST PCIRST CPC700 CPC700_RST SCSI lt PMC Slot Universe VMERST M4A3 128 64 CPLD NVRAM RTC WD RESET M48T37 Ethernet 2 12 Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Front Panel LEDs The Front Panel LEDs are numbered through 8 as illustrated below Reset 24 6 8 eK 1 35 7 The Front panel LEDs connected to the following signals LED Assignments Pin Signal Function 1 Green Ethernet Transmit Activity 2 Green 10 100BaseT Link 3 Green VME System Controller 4 Green Select 10 100BaseTx 5 Green Userl 6 Green User2 7 Red VME System Fail 8 Red Bit Fail JTAG COP Diagnostic A JTAG
21. Serial Interface Controller Number Compatibility Connector Parallel Interface Controller Number Connector Disk Drive Interface Hard Disk Ethernet Interface Type Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Power7E VMEbus Single Board Computer VMEbus Dual Eurocard VME64 ANSI VITA 1 1994 Tundra Universe IIB DTB Master Option A32 A24 A16 D32 D16 D08 EO RMW DTB Slave Option A32 A24 A16 D32 D16 D08 EO RMW Programmable 1 of 7 Programmable 1 7 Programmable BR 3 2 1 0 Option ROR and RWD RRS PRI SGL Master Slave BLT and MBLT D64 D32 D16 PowerPC 750 IBM CPC700 33MHz IBM CPC700 2 RS 232 up to 115 kBaud IBM PC Mini DB9 IBM CPC700 1 Parallel Port VME 2 connector I O Ultrafast SCSI 2 Interface Provided Through Front Panel and VME P2 IEEE 802 3 10 100BaseT Twisted Pair Provided Through Front Panel RJ45 connector Specifications 5 1 5 2 Electrical Power Physical Size Weight Construction Environmental Temperature Cooling Humidity Random Vibration Mechanical Shock Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 5VDC with IMB at 400MHz 12VDC 47 mA 12VDC 0mA 160mm x 233mm Dual Eurocard 6Ux4HP 374g Multi Layer Printed Circuit FR 4 with Flammability rating of 94V 0 by UL recognized manufacturers 0 to 55 Celsius Inlet
22. The general purpose timer is fully programmable through memory mapped registers features include Programmable time base counter Maskable time base comparison support for each compare timer Programmable compare timer values Enable disable control of all capture timers Enable disable control of all capture and compare interrupts Mask control of interrupt status bits Programmable capture event edge detection and synchronization For further information on the CPC700 Timer Counter refer to the CPC700 User s manual given on page 2 2 JTAG Port of this document The VME Interface is implemented with the Tundra Universe IIB chip The Uni verse IIB provides a fully compliant 64 bit VME bus interface A32 A24 A16 master amp slave D64 D32 D08 master amp slave MBLT BLT RMW ADOH LOCK programmable DMA controller with independent FIFOs and with linked list support write post and read prefetch FIFOs VME interrupter and handler and VME system controller with automatic system controller capability The Universe IIB chip is a 32 bit PCI peripheral and as such it contains several PCI configuration registers called PCICS PCI Configuration Space Registers It also contains registers for controlling VME and PCI operation known as UCSRs Universe Control and Status Registers The UCSRs are accessible via the PCI I O space note the PCICS registers are also a subset of the UCSRs Universe power up configuration o
23. W R S Cal Calibration FFEF FFF7 Watchdog WDS 4 2 0 RBI FFEF FFF6 Interrupts AFE 0 ABE 0 0 0 0 0 FFEF FFF5 Alarm Date 01 to 31 RPT4 0 Al 10Date Al Date FFEF FFF4 Alarm Hours 00 to 23 RPT3 0 Al 10Hours Al Hours FFEF FFF3 Alarm Minutes 00 to 59 RPT2 Al 10Seconds Al Minutes FFEF FFF2 Alarm Seconds 00 to 59 RPT Al 10Seconds Al Seconds FFEF FFF1 Century 00 to 99 1000 Years 100 Years FFEF FFF0 Flags WDF AF Z Z Z Z Z 2 10 Reads and writes to the Real Time Clock must be coordinated through use of the control register Before reading a Real Time Clock register first the R bit of the control register must be set That freezes the current copy of time in an internal buffer in the M48T37 the internal clock remains counting Then the clock buffer registers can be read Note the clock register buffers will not be updated again until the R bit is reset to zero When any of the real time clock time settings to be modified first the bit of the control register must be set After setting the W bit any or all of the clock buffer registers can be written Note the actual update to the clock time settings do not occur until the bit is reset to zero Also note when the W bit is reset to zero all of the buffer registers are updated to the actual Real Time Clock internal counters not just the buffers that were written For more inf
24. ator Select Front Panel 1 2 VME Connector 2 3 Jumper JP2 is used to select which flash device the board boots from When JP2 is installed the board boots from the socketed device 018 When JP2 is removed booting will take place from the soldered device See page 2 5 for more information on the boot flash Jumpers JP3 amp JP4 are used to enable or disable writes to the flash devices When JP3 JP4 is NOT installed no chip enables are generated for write cycles to the flash devices Configuration 3 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A B Resistor The Power7E is designed with several configuration options selected via the Configuration installation location of what are called A B resistors These are 0805 style surface mount resistors which be installed in one of two locations A or B for a given reference designator for instance Rx can be installed at A or B The resistor location is a manufacturing option and is not intended for end user modification Modifying a resistor location will terminate the warranty unless written consent is given by SBS prior to the modification The various A B resistors and their functions are described below Resistor Description A B 46 Baseboard ID Bit 1 X 63 64 77 92 95 117 118 119 PPC750 Enable X 120 121 122 133 134 140 141 143 144 145 146 147 148 149 151 152 153
25. cess cycles include 1 Single beat PCI I O reads and writes 2 PCI memory single beat and prefetch burst reads and single beat writes 3 Single beat PCI configuration reads and writes type 0 and type 1 4 PCI interrupt acknowledge 5 PCI special cycle buffered 32 read and write as PCI target and master PCI master 64 byte read buffer 6 Error tracking and status The CPC700 memory interface provides support for SDRAM and ROM Periph erals Flexible programmable timing is provided on a per bank basis Up to 5 banks of SDRAM ROM or peripherals can be individually programmed Bank 0 is dedicated to Boot ROM All other banks are defined in programmable con figuration registers Each bank can have a bus width of 8 16 32 or 64 data bits Detailed Description by Device 2 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SDRAM 2 4 CPC700 Address Map Function Sub Function Start Address End Address Size Local Memory Peripherals 0000 0000 2GB PCI Core Space 8000 0000 FFFF 2GB 11MB PCI Memo 8000 0000 F800 0000 PCI T O F800 0000 F800 FFFF Reserved F801 0000 F87F FFFF PCI T O F880 0000 FBFF FFFF Reserved 00 0000 FEBF FFFF PCI Config Regs FECO 0000 FECO 0004 PCI Interrupt ACK FEDO 0000 FEDF FFFF Reserved FEEO 0000 FF3F FFFF PCI local Config Regs FF40 0000 FF40 003C Device Configuration Register DCR Space FF50 0000 FF
26. cilitates board testing as signals not visible at the board connector may be read and set The PLL_CFG bits can be read in the HID 1 register in the 750 For additional information on the PPC 750 refer to the M PC750 RISC icro processor User s M anual M otorola Inc Document Number M PC 750U M A D Level 2 Cache The PPC 750 includes an integrated L2 cache controller with TAG RAM with 1M Byte of L2 cache On the Power7E two Motorola MCM69R737 devices or equivalent provide a 256k x 72 64 bits plus parity ECC Level 2 cache The L2 cache runs at a ratio of the CPU core speed Processor Local PCI The CPC700 contains a bridge from the PowerPC processor to the PCI bus as Bridge CPC700 well as a high speed memory controller internal peripherals and control for external ROM and external peripherals The CPC700 system clock is driven at 33 MHz and is asynchronous with the SDRAM 750 PowerPC 66Mhz bus fre quency The CPC700 supplies the following functions for the Power7E board PowerPC 60x 7xx bus interface operation to 66 MHz Synchronous DRAM interface operating at 66 MHz External peripheral bus PCI Revision 2 1 Compliant Interface Interrupt controller supports interrupts from a variety of on and off chip sources Programmable Timers Two 2 wire 8 bit 16550 compatible UARTS Two independent IIC interfaces Uses standard type 0 PCI configuration register map can act like a device or perform host functions
27. con figuration space as well as the PCI memory and I O spaces The PCI signals specific to the 53C875 are shown below NCR 53C875 Signal PCI Connection IDSEL IRQ REQ GNT The SCLK frequency provided to the 53C875 is 40 MHz In order to operate Ultra SCSI mode the clock doubler on the 53C875 must be enabled The SCSI low 8 bit plus control terminator enable disable pin is connected to the GPIOO pin The high upper data for wide SCSI terminator enable disable pin is connected to the pin For proper operation the following 53C875register settings should be used NCR 53 875 Parameter TBD GPCNTL bits 7 0 TOx10100 TBD GPREG bits 7 0 For further information on the 53C875 refer to SYM53C875 875E PCI Ultra SCSI I O Processor Data Manual Version 4 0 Symbios Logic Inc The ST78C36CQ64 is a monolithic Parallel Port interface It has a software selec table interrupt and an 8 bit DMA channel For further information on the ST78C36CQ64 refer to Exar Corporation Document Number ST78C36 Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Interrupt Logic NVRAM SGS Thomson M48T37Y There are two types of interrupts SMI and INT The processor external interrupt INT can be asserted in two ways 1 CPC700 internally generated interrupts 2 A specific CPC700 control register is written and not masked to cause an
28. d and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment EQUIPMENT DEMOS HUNDREDS OF InstraV ea REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED Contact us 888 88 SOURCE sales artisantg com www artisantg com
29. e board is installed or not When the jumper is installed the 512K byte device is the boot device and the Strataflash chip select is pulled high When the jumper is not installed the Strataflash device is the boot flash and the 512K byte device chip select is pulled high For more information on the boot flash devices refer to AMD 29LV040B data sheet AMD publication 21354 Rev C and INTEL StrataFlash data sheet INTEL publication E28F320J5 100 The CPC700 contains two UARTS that provide two wire full duplex serial interfaces to support communications with serial peripheral devices Each UART is compatible with NS 16550 and includes a 16 byte send and a 16 byte receive FIFO Features of the UART include Compatible with the NS 16550 16 byte send and 16 byte receive FIFO Full duplex operation Programmable baud rate generator Supports 5 to 8 bit word size 1 2 stop bits even odd no parity Two wire transmit receive external interface Detailed Description by Device 2 5 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Timers Counters PCI VME Bridge Universe IIB 2 6 The CPC700 contains a general purpose timer that includes a time base counter and ten system timers The time base counter is 32 bit read write counter and is clocked from the 700 system clock 33MHz The system timers are 32 bits wide and all are capable of interrupting the PowerPC 750
30. er to M48T37 32Kb x 8 TIMEKEEPER SRAM April 1998 Data Sheet ST Detailed Description by Device 2 9 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Real Time Clock ST Power7E contains a battery backed up real time clock and calendar The real M48T37Y time clock is implemented with the ST M48T37Y CMOS Timekeeper SRAM part and is physically located on the ROM bus Processor access to the real time clock is from addresses FFF0 to FFEF FFFF The Real Time Clock device is a byte wide device however the part may be accessed with 8 16 or 32 bit wide reads or writes The ST M48T37Y has a replaceable snappable top hat that contains a battery cell and a crystal plastic tabs hold the top hat secure ly to the main body of the part The SGS Thomson M48T37 is Y2K compliant and contains century year month day of month day of week hour minute and seconds in binary coded decimal registers Corrections for leap year are performed automatically The table below itemizes the Real Time Clock registers Address Function BCD Range D7 D6 D5 D4 D3 D2 D1 FFEF FFFF Year 00 to 99 10 Years Year FFEF FFFE Month 01 to 12 0 0 0 10 M Month FFEF FFFD Date 01 to 31 0 0 10Date Date 01 to 07 0 0 0 0 0 Da FFEF FFFB Hour 00 to 23 0 0 10 Hours Hours FFEF FFFA Minute 00 to 59 0 10Minutes Minutes FFEF FFF9 Second 00 to 59 0 10Seconds Seconds FFEF FFF8 Control
31. his in a single slot The Power 7E is designed to use the IBM PPC750 CPU The PowerPC 750 SYSCLK is driven at 66 MHz A JTAG emulator port is provided by a keyed 2 x 8 header on the PC board The Boot ROM socket U18 provides 512k bytes of flash memory organized as 512k x 8 The socket is a 32 pin PLCC socket Introduction 1 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Features 1 2 Key features of the Power7E are PowerPC 750 running at up to 500 MHz Byte of level 2 cache running at up to 250 MHz 66 MHz system bus 64M 512 MBytes of SDRAM with ECC at 66 MHz On board memory up to 256MB mezzanine memory up to 256MB IBM CPC700 PCI Bridge Local Bus Memory Controller Tundra Universe IIB PCI VME Bridge 512k Byte socketed boot flash memory 16MB on board Strataflash A 53C875 providing an Ultra SCSI port on the P2 Connector amp Front Panel 10 100BaseTX Ethernet Two 16550 compatible UARTs with RS 232 interface supporting up to 115k baud COMI on front panel 2 rear panel I O thru P2 32K bytes NVRAM Y2K compliant real time clock calendar Watchdog timer supporting interrupt or board chassis reset Occupies a single 6U VME slot A PMC expansion slot with PMC I O routed to the VMEbus backplane connector P2 Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 8
32. ials and workmanship for a period of ninety days Free technical support is available by phone fax or email Telephone suppport is available during the following Eastern Time hours Monday through Friday 8 30 am 5 30 pm You can reach technical support at 919 851 1101 voice 919 851 2844 fax or email at support sbs com Support Service and Warranty 6 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Product Repairs 6 2 To expedite assistance for problems be able to provide the following Your Name Phone number and Company e Product with which you are having trouble Serial Number and Revision Operating system you are running Detailed description of your problem and any error messages that have appeared on the screen Depending on the circumstances of the problem it may be deemed necessary to return the product to SBS Technologies for repair In order to return the product for repair the following steps are necessary 1 Obtain a Return Material Authorization number RMA from SBS Cus tomer Support 2 Ship the product prepaid to the designated repair point 3 Provide a written description of the claimed defect with the product Obtaining an RMA Number To obtain a product return authorization number RMA you should call our Customer Service department through our main number Shipping the Product Any product returned to SBS should
33. inter rupt to processor accessible from the PCI bus The interrupt controller in the CPC700 controls interrupts The CPC700 acts as the PCI master interrupt controller The CPC700 performs PCI bus arbitration in addition to servicing interrupt requests from PCI slave devices on the bus All interrupt masking and control is supplied by logic in the CPLD and the CPC700 Fora detailed description of CPC700 interrupt processing refer to the CPC700 User s manual given in section 2 of this document A block diagram of the interrupt logic for the Power7e board is shown below Reserved OO PMC INTB o gt LPT1 IRQ 3 NVRAM RTC IRQ 5 gt INT PMC Slot IRQ CPC700 750 ENETIRQ Universe IRQ 3 SCSI Interrupt Assignments For further information on the interrupt mapping refer to the IBM CPC700 User Manual Power7E contains 32K bytes of battery backed non volatile SRAM The NVRAM is implemented with the ST M48T37Y CMOS Timekeeper SRAM part and is physically located on the ROM bus CPC700 Processor access to the NVRAM is from addresses FFE8 0000 to FFEF FFEF The NVRAM device is byte wide device however the part may be accessed with 8 16 or 32 bit wide reads or writes The ST M48T37Y has a replaceable snappable top hat that con tains a battery cell and a crystal plastic tabs hold the top hat securely to the main body of the part For more information regarding the Power7E NVRAM ref
34. or clarity and accuracy These include The use of an suffix to a number indicates hexadecimal base sixteen notation The use ofa minus suffix to a signal name indicates an active low signal The signal is either true when it is at a logic zero level or the signal initiates actions on a high to low transition Textin Courier Font indicates a command entry or output from an SBS Technologies PC prod uct using its built in character set Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Contents Chapter 1 Introduction Overview Features Chapter 2 Detailed Description by Device Block Diagram CPU IBM Motorola 750 JTAG Port Level 2 Cache Processor Local PCI Bridge CPC700 SDRAM Boot Flash Memory UART Timers Counters PCI VME Bridge Universe Ethernet Interface PMC Slots SCSI Interface Parallel Port Exar ST78C36CQ64 Interrupt Logic NVRAM SGS Thomson M48T37Y Real Time Clock SGS Thomson M48T37Y Watchdog Timer SGS Thomson M48T37Y Clock Circuitry Reset Logic Front Panel LEDs JTAG COP Diagnostic Emulator Port Chapter 3 Configuration Chapter Scope Jumper Configuration A B Register Configuration Chapter 4 Memory Map Chapter Scope Device ID Power On Default 8 Bit Address Miscellaneous Register Map DRAM Type Chapter 5 Specification Chapter 6 Support Service and Warranty Chapter Scope Warranty Statement
35. ormation refer to M48T37 32Kb x 8 TIMEKEEPER SRAM April 1998 Data Sheet ST Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Watchdog Timer ST M48T37Y Clock Circuitry The ST M48T37Y contains a built in watchdog timer On power up the watch dog timer is disabled Once it is enabled by software it can be disabled by writ ing 00h to the watchdog register It can be set for a timeout interval of to 124 seconds The watchdog can be used to generate a system reset For more information on the watchdog timer refer to M48T37 32Kb x 8 TIMEKEEPER SRAM April 1998 Data Sheet ST The Power7E uses a Motorola MPC972 clock chip for the majority of the clock requirements This chip takes a 33 MHz input and generates both 66 MHz and 33 MHz outputs A Quality Semiconductor 5920 distributes the 66 MHz clocks to the SDRAM chips A 33 MHz oscillator is used for PCI devices and a 25 MHz oscillator provides the clock for the Ethernet controller transceiver An additional 40 MHz oscillator is provided for the SCSI controller as well as a 64 MHz oscillator for the UniverselIB VME Bridge The clock for the L2 cache comes from the CPU and is a multiple of the core frequency The different clocks are distributed as shown below SDRAM L2 Cache 66 MHz Core Freq Multiple 33 Motorola 66 MHz MHZ MPC974 gt 750 64MHz 32MM 33 3MHz 33MH Universe I
36. ptions is set as follows Automatic system controller detect Automatic SYSFAILZ assertion PCI register access UCSRs set to PCI I O space 32 bit PCI bus width BI mode disabled The automatic system controller feature works by the Universe monitoring VME signal BGIN3 during SYSRESET deassertion A Power7E in slot 1 sees BGIN3 low and it becomes system controller Logic on the Power7E pre vents the BGIN3 signal from propagating to BGOUT3 thus assuring that no other Power7E boards become system controller Note the BGIN3 method of autosyscon determination is fairly standard how ever care should be taken when other card types co exist in the same VME chassis The PCI signals specific to the Universe are shown below Universe Signal PCI Connection IDSEL AD14 LINT IRQI REQ REQ2 GNTZ GNT2 Power7E Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Ethernet Interface PMC Slots For further information on the Universe refer to Universe User Manual Tundra Semiconductor Corp Document Number 8091142 MD300 01 For further informa tion on the VMEbus standard refer to IEEE Standard for a Versatile Backplane Bus VME64 ANSI VITA 1 1994 Standard The INTEL 82559ER is an Ethernet LAN controller containing an MII port for connection to 100Mbit transceivers The 82559ER consists of the Media Access Controller MAC and the ph
37. ysical layer PHY combined into a single component solution which allows use of both 10Mbit and 100Mbit 100baseT X Ethernet through the same cable connection The transceiver connections are terminated filtered and isolated on the Power7E board and are then brought out to an RJ 45 connector on the front panel A serial EEPROM is used to store the MAC address The 82559ER is a PCI peripheral and as such it contains several PCI configu ration registers It also contains registers for controlling the Ethernet operation known as command and status registers CSRs CSRs are accessible via the PCI memory and I O spaces The PCI signals specific to the 82559ER are shown below INTEL 82559 Signal PCI Connection REQI GNT GNTI For further information on the 82559ER and the MII interface refer to INTEL 82559ER Fast Ethernet Multifunction PCI Cardbus Controller Datasheet INTEL Corp Document Number 738259 001 Rev 1 0 The PMC Slot conforms to draft standards P1386 and P1386 1 as well as being compliant to ProcessorPMC specifications PPMC It allows single width 3 3V expansion boards to be plugged into the Power7E PCI bus via the P11 and P12 connectors P14 is provided to route PMC I O to VMEP2 in the man ner described below The Power7E front panel contains an opening to accept the PMC front bezel The PCI signals specific to the PMC Slot are shown below PMC Slot Signal PCI Connection IDSEL 15 IRQ2

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