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USER`S MANUAL - Dataman Programmers Ltd.

1. SSS 3 End Of Conversion EOC Status Bit A D conversion is progress A D conversion complete 2 1 Clock Source Selection Bits o 0 fxx 4 fosc lt 8MHz fxx fosc lt 2 5 2 0 AID conversion Start Bit Disable operation Start operation NOTE Maximum ADC clock input 2 ELECTRONICS 4 5 CONTROL REGISTERS 3C9484 C9488 F9488 BTCON Basic Timer Control Register DCH RESET Value 0 0 0 0 Read Write R W R W R W R W 7 4 Not used for the S3C9484 C9488 F9488 3 2 Basic Timer Input Clock Selection Bits Basic Timer Counter Clear Bit 1 DUCIT NENNEN Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer 2 o waa Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation the BTCON 1 value is automatically cleared to 0 2 When you write a 1 to BTCON O the corresponding frequency divider is cleared to Immediately following the write operation the 0 value is automatically cleared to O 3 Thefxxis selected clock for system main OSC or sub OSC 4 6 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER CLKCON system Clock Control Register D
2. a fofas o ola Alternative function TXD output Alternative function LCD SEG17 signal output 4 2 P3 1 SEG16 RXD o 0 Input mode with pull up RXD input fo 4 Input mode RXD input Push pull output fo 4 4 Alternative function RXD output Alternative function LCD SEG16 signal output 1 0 P3 0 SEG15 Input mode with pull up Input mode Push pull output Alternative function LCD SEG15 signal output ELECTRONICS 4 21 CONTROL REGISTERS 3C9484 C9488 F9488 P3INT Port 3 Interrupt Control Register EEH RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P3 6 INT3 Interrupt Enable Disable Selection Bits Interrupt Disable Interrupt Enable falling edge 1 Interrupt Enable rising edge 5 4 P3 5 INT2 Interrupt Enable Disable Selection Bits x Interrupt Disable EHE Interrupt Enable falling edge Interrupt Enable rising edge 3 2 P3 4 INT1 Interrupt Enable Disable Selection Bits x Interrupt Disable Interrupt Enable falling edge Interrupt Enable rising edge 1 0 P3 3 INTO Interrupt Enable Disable Selection Bits S x Interrupt Disable alo Interrupt Enable falling edge Interrupt Enable rising edge 4 22 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER P3PND Port 3 Interrupt Pending Register EFH RESET Value E 0 0 0 0 Read Write R W R W R W R W
3. 25 C to 85 C Vpp 2 2V to 5 5 V Test Condition Crystal Vpp 45V to 5 5 V 22V to 45V Ceramic Stabilization occurs when Vpp is equal to the minimum oscillator voltage range External clock Xy input high and low level width typ ty NOTE Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a power on occurs or when Stop mode is ended by a RESET signal 19 10 ELECTRONICS 53 9484 9488 9488 ELECTRICAL DATA 4 1 051 Figure 19 7 Clock Timing Measurement at Xi Table 19 9 Sub Oscillator Frequency fosc TA 25 85 Vpp 22V to 5 5 V clock reuk 7 Test Conation win Max Uni Crystal C1 33 pF C2 33 pF 32 32 768 35 kHz XTIN XT OUT Table 19 10 Sub Oscillator crystal Stabilization Time TA 25 C Vpp 22V to 5 5 V NOTE Oscillation stabilization time is the time required for the CPU return to its normal operation when Stop mode is released by interrupts Table 19 11 LCD Contrast Controller Characteristics TA 25 C to 85 C Vpp 4 5 V to 5 5 V Parameter Symbo Cons wm Tw wax unit a San ia lek Sa L er s Max Output Voltage VLPP IV Vpp 5V VLC1 LCDVOL 8FH ELECTRONICS 19 11 ELECTRICAL DATA 53 9484 9488 9488 19 12 ELECTRONICS 53
4. Power supply input pin 7 16 3 2 1 pee ven Test signal input pin for factory use only 4 must be connected to Vas peri ELECTRONICS 1 9 PRODUCT OVERVIEW 3C9484 C9488 F9488 Table 1 2 Pin Descriptions of 32 SOP and 32 SDIP Continued Pin Pin Description Circuit Shared Type Type Functions SEG3 10 LCD segment display signal output pins H 14 17 28 2 0 2 7 SEG15 18 15 P3 0 H 17 P3 1 RXD P3 2 TXD P3 3 INTO COMO 3 O LCD common signal output pins 16 13 1 7 1 4 ADCO 3 A D converter analog input channels E 1 12 9 1 3 1 2 3 1 1 02 P1 0 TBPWM Serial data RXD pin for receive input and H 17 26 P3 1 SEG16 transmit output mode 0 Serial data TXD pin for transmit output and H 17 27 P3 2 SEG17 shift clock output mode 0 External interrupts P3 3 SEG18 P3 4 TAOUT P3 5 TACK P3 6 TACAP Timer counter A overflow output or TAOUT Timer counter A PWM output TACK Timer counter A external clock input E 3 E TBPWM RESETB Timer B PWM output Clock input and output pins for subsystem clock System reset signal input pin 1 10 ELECTRONICS 53 9484 9488 9488 PRODUCT OVERVIEW PIN CIRCUITS Pull up Enable IN o gt Data Pin Circuit Output Disable Figure 1 5 Pin Circuit Type B RESET Figure 1 7 Pin Circuit Type D 2 Pull up Enable P Channel Data Out Output Disable Output N Channel Disable Ext INT
5. 1 2 Input mode Push pull output Alternative function LCD COMO signal output Input mode Push pull output Alternative function LCD COM1 signal output Input mode Push pull output Alternative function LCD COM2 signal output Input mode Push pull output Alternative function LCD COMSsignal output You must be care of the pull up resistor option Figure 9 4 Port 1 High Byte Control Register PICONH ELECTRONICS 9 7 PORTS 3C9484 C9488 F9488 Port 1 Control Register Low Byte P1CONL 9 R W Reset value 00H P1 3 P1 2 P1 1 P1 0 ADCO ADC1 ADC2 ADC3 BUZ TBPWM Input mode Push pull output Alternative function ADCO input Input mode Push pull output Alternative function ADC1 input Input mode Alternative function BUZ output Push pull output Alternative function ADC2 input Input mode Alternative function TBPWM output Push pull output Alternative function ADC3 input NOTE You must be care of the pull up resistor option Figure 9 5 Port 1 Low Byte Control Register P1CONL 9 8 ELECTRONICS 53 9484 9488 9488 PORTS Port 1 Pull up Resistor Control Register P1PUR D3H R W Reset value FFH ve 1 0 P1 1 P1PUR Pin Configuration Settings 0 Pull up resistor disable 1 Pull up resistor enable Figure 9 6 Port 1 Pull up Resistor Control Register P1PUR ELECTRONICS 9 9 PORTS 3C9484 C948
6. Analog block current 2 lADC AVRE 5 Vpp AVRE 5 AVRE 3 Vpp lt 3 lt Vpp 5V When Power Down mode NOTES 1 Conversion time is the time required from the moment a conversion operation starts until it ends 2 an operating current during A D conversion 19 8 ELECTRONICS 53 9484 9488 9488 ELECTRICAL DATA Reference Voltage Input 10 A Analog ADCO ADC8 Input Pin 3C9484 C9488 F9488 NOTE The symbol R signifies an offset resistor with a value of from 50 to 100 If this resistor is omitted the absolute accuracy will be maximum of 3 LSBs Figure 19 6 Recommended A D Converter Circuit for Highest Absolute Accuracy ELECTRONICS 19 9 ELECTRICAL DATA 3C9484 C9488 F9488 Table 19 7 Main Oscillator Frequency fosc4 ME 25 C to 85 C Vpp 2 2 V to 5 5 V E ee EIM XIN XOUT Crystal oscillation Frequency 2 Crystal 8MHz C1 20 pF C2 20 pF Ceramic oscillation frequency External clock Xy input frequency RC 35 5 V i NOTES 1 We recommend crystal of TDK Korea as the most suitable oscillator of Samsung Microcontroller If you want to know detailed information of Crystal Oscillator Frequency with cap please visit the web site www tdkkorea co kr 2 The value of Crystal 10MHz and Cap 20pF is based on TDK Korea parts Table 19 8 Main Oscillator Clock Stabilization Time
7. CLKCON 4 are cleared to 00B After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H and 0101H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3C9484 C9488 F9488 interrupt structure that can be used to release Stop mode are External interrupts P3 3 P3 6 INTO INT3 Please note the following conditions for Stop mode release f you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged except STPCON register If you use an external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering Stop mode When the Stop mode is released by external interrupt the CLKCON 4 and CLKCON 3 bit pair setting remains unchanged and the currently selected clock value is used external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiat
8. to TACON the counter will increment until it reaches 10H At this point the TA interrupt request is generated the counter value is reset and counting resumes Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TAOUT pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer A data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from OOH Although you can use the match signal to generate a timer A overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TAOUT pin is held to Low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to 256 Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the TADATA register You can select rising or falling edges to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture input by setting the value of the timer A capture input selection bit in the port 3 high by
9. Format Examples dst C _ dst 0 dst 7 _ dst 0 dst n _ dst n 1 n 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C Set if the bit rotated from the least significant bit position bit zero was 1 Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO R E1 IR Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H amp Register 00H 98H C 1 RR 01H Register 01H 02H register 02H 8BH C 1 In the first example if general register 00H contains the value 31H 00110001B the statement RR rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are also set to 1 ELECTRONICS 6 41 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 RRC Rotate Right Through Carry RRC Operation Flags Format Examples 6 42 dst dst 7 _ _ dst 0 dst n _ dst n 1 n 0 6 The contents of the destination op
10. LCD CONTROLLER DRIVER Application With Contrast Control 3C9484 C9488 F9488 LCDCON 7 On NOTE WhenLCDVOL 7 is logic one you can control LCD contrast by writing data to LCDVOL 3 0 Figure 14 7 Internal Voltage Dividing Resistor Connection 1 3 Bias Display On ELEGTRONIGS LCD CONTROLLER DRIVER 3C9484 C9488 F9488 LCD DRIVE VOLTAGE The LCD display is turned on only when the voltage difference between the common and segment signals is greater than Vi cp The LCD display is turned off when the difference between the common and segment signal voltages is less than Vi The turn on voltage Vi cp or Vi is generated only when both signals the selected signals of the bias Table 14 1 shows LCD drive voltages level for static mode 1 3 bias 1 4 bias Table 14 1 LCD Drive Bias Voltages Level Values LCD Power Supply Static Mode 1 3 Bias 1 4 Bias Oo Mo C O x Xs NOTE TheLCD panel display be deteriorated if DC voltage is applied that lies between the and segment signal voltage Therefore always drive the LCD panel with AC voltage 14 8 ELECTRONICS 53 9484 9488 9488 LCD CONTROLLER DRIVER LCD SEG COM SIGNALS The 19 LCD segment signal pins are connected to corresponding display RAM locations at 12 Bits 0 7 of the display RAM are synchronized with the common signal output pins and COM7 When the bit
11. Logical Exclusive OR XOR Operation Flags Format Examples 6 50 dst src dst _ dst XOR src The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a bit is stored C Unaffected Z Setifthe result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to 0 Bytes Cycles Opcode Addr Mode Hex dst src 6 B3 r Ir opc src dst 3 6 B4 R R 6 B5 R IR opc dst src 3 6 B6 R IM Given RO OC7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR RO R1 RO OC5H R1 02H XOR RO R1 RO OE4H R1 02H register 02H 23H XOR 00H 01H Register 00H 29H register 01H 02H XOR 00H Q01H Register OOH 08H register 01H 02H register 02H 23H XOR OOH 54H Register OOH 7FH In the first example if working register RO contains the value OC7H and if register R1 contains the value 02H the statement RO R1 logically exclusive ORs the R1 value with the RO value and stores the result OC5H in the destination register RO ELECTRONICS 53 9484 9488 9488 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The clock frequency generation for the S3C9484 C9488 F9488 by an external crystal can range from 1 MHz to 8 MHz The ma
12. When the master device wants to transmit a block of data to one of several slaves on a serial line it first sends out an address byte to identify the target slave Note that in this case an address byte differs from a data byte In an address byte the 9th bit is 1 and in a data byte it is O The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave then clears its MCE bit and prepares to receive incoming data bytes The MCE bits of slaves that were not addressed remain set and they continue operating normally while ignoring the incoming data bytes While the MCE bit setting has no effect in mode 0 it can be used in mode 1 to check the validity of the stop bit For mode 1 reception if MCE is 1 the receive interrupt will be issue unless a valid stop bit is received ELECTRONICS 12 13 UART 3C9484 C9488 F9488 Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications 1 2 3 12 14 Set all S3C9484 C9488 F9488 devices masters and slaves to UART mode 2 with parity disable Write the MCE bit of all the slave devices to 1 The master device s transmission protocol is First byte the address identifying the target slave device 9th bit 1 Next bytes data 9th bit 0 When the target slave receives the first byte all of the slaves are interrupted because the 9
13. Compare Decrement Increment Subtract with carry Subtract Logical AND Complement Logical OR Logical exclusive OR ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Program Control Instructions CALL dst IRET JP cc dst JP dst JR cc dst RET Bit Manipulation Instructions TCM dst src TM dst src Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst CPU Control Instructions CCF DI EI IDLE NOP RCF SCF STOP ELECTRONI S Instruction Call procedure Interrupt return Jump on condition code Jump unconditional Jump relative on condition code Return Test complement under mask Test under mask Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set carry flag Enter stop mode 6 3 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits that describe the current status of CPU operations Four of these bits FLAGS 4 FLAGS 7 be tested and used with conditional jump instructions FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR
14. Input Normal Figure 1 6 Pin Circuit Type C Figure 1 8 Pin Circuit Type D 4 P3 5 P3 6 ELECTRONICS 1 11 PRODUCT OVERVIEW lt P3 x Data Pull up Alternative output Pin enable TAOUT Circuit Type C Output ui Disable Ext INT Normal Input Figure 1 9 Pin Circuit Type D 5 P3 4 Output Data Output Disable Input Mode Digital Input Alternative I O Enable XTin XTout oscillation circuit Figure 1 10 Pin Circuit Type E P0 0 0 1 3C9484 C9488 F9488 Pull up enable Smart option ELECTRONICS 53 9484 9488 9488 PRODUCT OVERVIEW Pull up Enable Figure 1 11 Pin Circuit 1 P0 3 1 2 1 3 Pull up register 50 kQ typical Pull up enable gt Open drain Smart option Data Output Disable input mode Input Data Figure 1 12 Pin Circuit Type E 2 0 2 ELECTRONICS 1 13 PRODUCT OVERVIEW 3C9484 C9488 F9488 Pull up Enable P1 0 P1 1 Data Buzzer Output TB Underflow Carrier on off P1 0 uM Circuit Port Alternative option Type C Output Disable ADC In EN Data to ADC Figure 1 13 Pin Circuit Type E 3 P1 0 P1 1 ELECTRONI S 53 9484 9488 9488 PRODUCT OVERVIEW SEG COM Figure 1 14 Pin Circuit Type H SEG COM ELECTRONICS 1 15 PRODUCT OVERVIEW 3C9484 C9488 F9488 SEG Output Disable VLC2 Figure 1 15 Pin Circuit Type H 4 Open Drain EN Pull up Enable Data
15. LCD Out EN SEG COM Output Disable Input Figure 1 16 Pin Circuit Type H 14 P1 4 P1 7 P2 P3 0 P4 0 P4 6 1 16 ELECTRONICS 53 9484 9488 9488 PRODUCT OVERVIEW Open Drain EN Pull up Enable Data LCD Out EN SEG Output Disable Ext INT Normal Input Figure 1 17 Pin Circuit Type H 15 P3 3 Open Drain EN Pull up Enable Data yo LCD Out EN COM Output Disable ADC In EN Normal In ADC In Figure 1 18 Pin Circuit Type 16 0 4 0 7 ELECTRONICS 1 17 PRODUCT OVERVIEW 3C9484 C9488 F9488 Open Drain EN Pull up Enable Data LCD Out EN Output Disable Normal Input Figure 1 19 Pin Circuit Type H 17 P3 1 P3 2 1 18 ELECTRONICS 53 9484 9488 9488 ADDRESS SPACES ADDRESS SPACES OVERVIEW 53 9484 9488 9488 microcontroller has two kinds of address space Internal program memory ROM Internal register file A 13 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the internal register file The S3F9488 have 8 Kbytes of on chip program memory which is configured as the Internal ROM mode all of the 8 Kbyte internal program memory is used The 53 9484 9488 9488 microcontroller has 208 general purpose registers in its internal register file 47 bytes the register file are mapped for system and peripheral control functions And 19 bytes in th
16. Push pull output 1 Alternative function LCD SEG11 signal output 5 4 nput mode with pull up Input mode 1 Push pull output 1 Alternative function LCD SEG2 signal output 3 2 P4 1 SEG1 1 0 P4 0 SEGO 0 0 Input mode with putue o O 011 Inputmode Push pull output Alternative function LCD SEGO signal output ELECTRONICS 4 25 CONTROL REGISTERS 3C9484 C9488 F9488 SP stack Pointer D9H RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W 7 0 Stack Pointer Address The stack pointer value is 8 bit stack pointer address SP7 SPO SP value is undefined following a reset STPCON Stop Control Register D7H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 0 STOP Control Bits 10100101 Other values Enable stop instruction Disable stop instruction NOTE Before executing the STOP instruction you must set this STPCON register as 10100101b Otherwise the STOP instruction will not be executed 4 26 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER SYM System Mode Register DFH RESET Value 0 0 0 0 Read Write R W R W R W R W 7 4 Not used for 53 9484 9488 9488 3 Global Interrupt Enable Bit Disable all interrupts Enable all interrupt Page 2 Not used for S3C9484 C9488 F 9488 Page 3 Not used for S3C9484 C9488 F9488 0 Page 4 Not used f
17. UART Baud Rate Data Register BRDATAH DAH R W Reset Value FFH BRDATAL DBH R W Reset Value FFH Baud rate data Figure 12 4 UART Baud Rate Data Register BRDATAH BRDATAL BAUD RATE CALCULATIONS The baud rate is determined by the baud rate data register 16bit BRDATA Mode 0 baud rate fxx 16 x 16Bit BRDATA 1 Mode 1 baud rate fxx 16 x 16Bit BRDATA 1 Mode 2 baud rate fxx 16 x 16Bit BRDATA 1 12 6 ELECTRONICS 53 9484 9488 9488 UART Table 12 1 Commonly Used Baud Rates Generated by 16 bit BRDATA Baud Rate Oscillation Clock BRDATAH BRDATAL 230 400 Hz 115 200 Hz _ 4 ge N ELECTRONICS 12 7 UART 3C9484 C9488 F9488 BLOCK DIAGRAM 5 88 Internal Data Bus MSO 51 Zero Detector Write to tT 2 Shift TxD P3 2 UDATA gt Start Tx Control EN Tx Clock TIP Send TxD P3 2 Rx Clock RIP Receive Rx Control Start Transition Detector Bit Detector Shift UDATA RxD P3 1 5 88 Internal Data Bus Figure 12 5 UART Functional Block Diagram 12 8 ELECTRONICS 53 9484 9488 9488 UART UART MODE 0 FUNCTION DESCRIPTION In mode 0 UART is input and output through the RxD P3 1 pin and TxD P3 2 pin outputs the shift clock Data is transmitted or received in 8 bit units only The LSB of the 8 bit value is transmitted or received first Mode 0 Transmit Procedure 1 2 Select mode 0 by
18. Unsigned greater than 0 AND Z 0 1 Unsigned less than or equal C OR Z 1 NOTES 1 Itindicates condition codes that are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used after a CP instruction however EQ would probably be used 2 Foroperations involving unsigned numbers the special condition codes UGE ULT UGT and ULE mustbe used ELECTRONICS 6 9 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM88RCRI instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction 6 10 ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET ADC Add with Carry ADC dst src Operation dst _ dst src c The sou
19. 01 1 4 duty 1 3bias 01 Dot on signal 1 static 1 Normal display Figure 14 4 LCD Control Register LCDCON 14 4 ELECTRONICS 53 9484 9488 9488 LCD CONTROLLER DRIVER LCD VOLTAGE CONTROL REGISTER LCDVOL The LCD Voltage control register LCDVOL is mapped to RAM addresses D1H LCDVOL is used to control the LCD contrast up to 16 step contrast level LCD contrast control enable disable bit LCDVOL 7 LCD contrast segment output selection bits LCDVOL 0 LCDVOL 3 LCD Voltage Control Register LCDVOL D1H R W Reset OFH Not used Segment Port output selection bits 0000 1 16 step The dimmest level LCD contrast Control 0001 2 16 step enable disable bit 0 Disable LCD contrast control i ene gees 1110 15 16 step vores sone 1111 16 16 step 0010 3 16 step 0011 4 16 step Figure 14 5 LCD Drive Voltage Control Register LCDVOL ELECTRONICS 14 5 LCD CONTROLLER DRIVER 3C9484 C9488 F9488 Application Without Contrast Control Application With Contrast Control 3C9484 C9488 F9488 S3C9484 C9488 F9488 18 steps of voltage LCDVOL 7 NOTE When LCDVOL 7 is logic one you can control LCD contrast by writing data to LCDVOL 3 0 Figure 14 6 Internal Voltage Dividing Resistor Connection 1 4 Bias Display On 14 6 ELECTRONICS 53 9484 9488 9488 Application Without Contrast Control S3C9184 C9488 F9488 Contrast Controller 18 steps of voltage LCD VOL
20. 44QFP Total 36 bit programmable pins 42SDIP Total 26 bit programmable pins 32SDIP 32SOP Basic Timer e One programmable 8 bit basic timer BT for Oscillation stabilization control e 8bit Timers A B 8 bit timer counter Timer A with three operating modes Interval mode capture mode and PWM mode 8 bit timer counter Timer Carrier frequency or PWM generator Watch Timer e Real time and interval time measurement e Four frequency output to BUZ pin e Clock generation for LCD 1 2 53 9484 9488 9488 LCD Controller Driver Optional e 8 COM x 19 SEG MAX 19 digit 4 COM x 19 SEG MAX 8 digit A D Converter e Nine analog input channels e 12 5us conversion speed at 4MHz fapc clock Asynchronous UART e Programmable baud rate generator e Support serial data transmit receive operations with 8 bit 9 bit UART Watchdog Timer e Two oscillation sources selection by Smart option e Safety work for noise interference Low Voltage Reset LVR e Low Voltage Check to make system reset Vivp 2 6V 3 3V 3 9V Voltage Detector for Indication e Voltage Detector to indicate specific voltage e S W control 2 4V 2 7V 3 3V 3 9V Operating Temperature Range e 25 C to 85 Operating Voltage Range e 2 2V to 5 5 V at 4 MHz fosc e 2 7V to 5 5 V at 8 MHz fosc Package Type e 32 pin SDIP 32 pin SOP e 42 SDIP 44 pin QFP Smart Option e Low Voltage Reset LVR level and
21. Cycles 10 10 12 12 14 14 14 14 14 14 Opcode Hex C3 D3 E7 F7 B7 B7 AT B7 of values used in formats 9 and 10 are used to address data memory 2 byte 3 bytes 4 ELECTRONICS Addr Mode dst src r Irr Irr r r XS rr XS rr r r XL rr XL rr r r DA DA r r DA DA r The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 For formats 3 and 4 the destination address XS rr and the source address XS rr are each one For formats 5 and 6 the destination address XL rr and the source address XL rr are each two The DA and r source values for formats 7 and 8 are used to address program memory the second set 6 29 SAM88RCRI INSTRUCTION SET LDC LDE Load Memory LDC LDE Examples Continued Given 3C9484 C9488 F9488 RO 11H R1 R2 01H R3 04H R4 R5 60H Program memory locations 0061 0103H 4FH 0104H 0105H 6DH 1104H 88H External data memory locations 0061H BBH 0103H 0104H 2 0105H 7DH and 1104H 98H LDC RO RR2 LDE RO RR2 LDC note gRR2 RO LDE RR2 RO LDC RO 01H RR4 LDE RO 01H RR4 LDC note 01H RR4 RO LDE 01H RR4 RO LDC RO 1000H RR2 LDE RO 1000H RR2 LDC R0 1104H LDE R0 1104H LDC note 4405H RO LDE 1105H RO RO _ contents of program memory location 0104
22. Disable 1 Enable 3 If Parity disable mode PEN 0 Location of the 9th data bit to be transmitted in UART mode 2 0 or 1 If Parity enable mode PEN 1 even odd parity selection bit for transmit data in UART mode 2 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data ELECTRONICS 4 31 CONTROL REGISTERS 3C9484 C9488 F9488 UARTCON UART Control Register Continued FDH RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 2 If Parity disable PEN 0 location of the 9th data bit that was received in UART mode 2 0 or 1 If Parity enable mode PEN 1 even odd parity selection bit for receive data in UART mode 2 0 Even parity check for the received data 1 Odd parity check for the received data A result of parity error will be saved in RPE bit of the UARTPND register after parity checking of the received data 1 Receive interrupt enable bit Disable Receive interrupt Enable Receive interrupt 0 Transmit interrupt enable bit Disable Transmit interrupt Enable Transmit Interrupt NOTES 1 In mode 2 if the MCE UARTCON 5 bit is set to 1 the receive interrupt will not be activated if the received gth data bit is 0 In mode 1 if MCE 1 the receive interrupt will not be activated if a valid stop bit was not received In mode 0 the MCE UARTCON 5 bit should be 2 descriptions for 8 bit an
23. Execution of STOP Instrction NOTE is the same as 4096 x 16 x 1 fosc Figure 19 3 Stop Mode Release Timing Initiated by RESET 19 6 ELECTRONICS 53 9484 9488 9488 ELECTRICAL DATA Oscillation Stabilization Time 4 34i Stop Mode Idle Mode lt Data Retention Mode gt 4 Execution of STOP Instruction Normal Operating Mode Interrupt is the same as 4096 x 16 x BT clock Figure 19 4 Stop Mode main Release Timing Initiated by Interrupts Oscillation Stabilization Time Idle Mode Normal Execution of Operating Mode STOP Instruction Interrupt NOTE twalT 128 x 16 x 1 32768 62 5 ms Figure 19 5 Stop Mode sub Release Timing Initiated by Interrupts ELECTRONICS 19 7 ELECTRICAL DATA 3C9484 C9488 F9488 Table 19 6 A D Converter Electrical Characteristics TA 25 C to 85 C Vin 22 V to 5 5 V Veg 0 V Parameter Cons min Typ Max Unit mue EI LER Total accuracy EE 5 12V Integral Linearity Error AVggp 5 12V Differential Linearity Error DLE AVgs 0 CPU clock 8 MHz Offset Error of Top E Offset Error of Bottom Offset Error of Bottom of Bottom 50 x fxx 4 fxx 8MHz Analog input voltage input voltage Vian AN poe meses Ales Yes 0 S
24. LD BTCON 0001011B LD CLKCON 00011000B LD SP 0COH LD SYM 00H LD OSCCON 00000000B LD P1CONL 10101001B PWM LD 79 LD TBDATAL 19 LD TBCON 00101111B Fxx REPEAT MODE FLIP FLOP HIGH TIMER START EI MAIN JP MAIN F9488 INT TM TINTPND 04H CHECK WHAT INTERRUPT IS ENABLED JP NC TB UF INT IRET TB UF INT LD TINTPND 0 NOP NOP IRET END ELECTRONICS 11 9 8 BIT TIMER A B 53 9484 9488 9488 NOTES 11 10 ELECTRONICS 53 9484 9488 9488 UART UART OVERVIEW The UART block has a full duplex serial port with programmable operating modes There is one synchronous mode and three UART Universal Asynchronous Receiver Transmitter modes Shift Register I O with baud rate of fxx 16 x 16bit BRDATA 1 8 bit UART mode variable baud rate fxx 16 x 16bit BRDATA 1 9 bit UART mode variable baud rate fxx 16 x 16bit BRDATA 1 UART receive and transmit buffers are both accessed via the data register UDATA is at address FFH Writing to the UART data register loads the transmit buffer reading the UART data register accesses a physically separate receive buffer When accessing a receive data buffer shift register reception of the next byte can begin before the previously received byte has been read from the receive register However if the first byte has not been read by the time the next byte has been completely received the first data byte will be lost Overrun error In
25. The receive operation starts when the signal at the RxD pin goes to low level ELECTRONICS 12 11 UART 3C9484 C9488 F9488 Tx Clock Write to Shift Register UARTDATA Shift id a Ce C E ER ES S TIP Transmit TB8 or Parity bit RB8 or Parity bit Start Bit Bit Detect Sample Time Shift RIP Receive Figure 12 8 Timing Diagram for UART Mode 2 Operation 12 12 ELECTRONICS 53 9484 9488 9488 UART SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3C9 series multiprocessor communication features let a master S3C9484 C9488 F9488 send a multiple frame serial message to a slave device in a multi S3C9484 C9488 F9488 configuration It does this without interrupting other slave devices that may be on the same serial line This feature can be used only in UART mode 2 with the parity disable mode In mode 2 9 data bits are received The 9th bit value is written to RB8 UARTCON 2 The data receive operation is concluded with a stop bit You can program this function so that when the stop bit is received the serial interrupt will be generated only if RB8 1 To enable this feature you set the MCE bit in the UARTCON registers When the MCE bit is 1 serial data frames that are received with the 9th bit 0 do not generate an interrupt In this case the 9th bit simply separates the address from the serial data Sample Protocol for Master Slave Interaction
26. contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Irr even for program memory and odd for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory locations 1033H and 1034H external data memory locations 1033H ODDH and 1034H OD5H LDCI R8 RR6 contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 _ RR6 1 R8 OCDH R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 RR6 is incremented by one RR6 _ RR6 1 R8 ODDH R6 10H R7 34H ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET NOP No Operation NOP Operation No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex 1 4 FF Example When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONICS 6 33 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 OR Logi
27. dst AND src This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to O Bytes Cycles Opcode Addr Mode Hex dst src 6 73 r Ir opc src dst 3 6 74 R R 75 R IR opc dst src 3 6 76 R IM Given RO OC7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM RO R1 RO OC7H R1 02H Z 0 RO R1 RO OC7H R1 02H register 02H 23H 2 0 00H 01H Register 00H 2BH register 01H 02H 2 0 00H 01H 6 Register 00H 2BH register 01H 02H register 02H 23H Z 0 00H 454H Register 00H 2BH Z 1 In the first example if working register RO contains the value OC7H 11000111B and register R1 the value 02H 0000001 0B the statement TM RO R1 tests bit one in the destination register for a value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 49 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 XOR
28. m m 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory location 1033H external data memory location 1033H ODDH LDCD R8 RR6 contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 R6 10H R7 32H RR6 _ RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 _ RR6 1 R8 ODDH R6 10H R7 32H ELECTRONICS 6 31 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 LDCI LDEI LOAD MEMORY AND INCREMENT LDCI LDEI Operation Flags Format Examples dst src dst src m m4 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The
29. to TACON 3 You can start the timer A counter by writing a 1 to 0 The timer A overflow interrupt TAOVF has the vector address 00H 01H When a timer A overflow interrupt occurs and is serviced by the CPU but the pending condition must clear by software To enable the timer A match capture interrupt you must write TACON 1 to 1 To generate the exact time interval you should write TACON 3 and 0 which cleared counter and interrupt pending bit When interrupt service routine is served the pending condition must be cleared by software by writing a 0 to the interrupt pending bit Timer A Control Register TACON F3H R W Reset 00H Timer input clock selection bit Timer A start stop bit 00 fxx 1024 0 Stop timer A 01 fxx 256 1 Start timer 10 fxx 64 11 External clock TACK Timer A match capture interrupt enable bit Timer A operating mode selection bit 0 Disable interrupt 00 Interval mode TAOUT mode 1 Enable interrrupt 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mode OVF interrupt and match interrupt can occur Timer A overflow interrupt enable bit 0 Disable overflow interrupt 1 Enable overflow interrrupt Timer A counter clear bit 0 No effect 1 Clear the timer A counter when write NOTE When th coun
30. to clear the basic timer counter and frequency dividers It is located in address DCH and is read write addressable using register addressing mode A reset clears BTCON to This enables selects a basic timer clock frequency of fyy 4096 The 8 bit basic timer counter DDH can be cleared at any time during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers write a 1 to 0 ELECTRONICS 10 1 BASIC TIMER 3C9484 C9488 F9488 Basic Timer Control Register BTCON DCH R W Reset value 00H Divider clear bit 0 No effect 1 Clear divider Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bit 00 fxx 4096 01 fxx 1024 10 fxx 128 11 Not used Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS 53 9484 9488 9488 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fxx 4096 for reset or at the rate of the preset clock source for an external interrupt When BTCNT 4 overflows a signal is generated to indicate that the stabilization interval
31. 0 255 n 0 15 reg or RRp reg 0 254 even number only where 0 2 14 Rn 0 15 Rn or reg 0 255 0 15 RRp p 0 2 14 RRp or reg reg 0 254 even only where 0 2 14 reg Rn reg 0 255 n 0 15 addr RRp addr range 128 to 127 where 0 2 14 addr RRp addr range 0 8191 where 0 2 14 addr addr range 0 8191 addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction data data 0 255 ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET Table 6 5 Opcode Quick Reference OPCODE MAP LOWER NIBBLE HEX Lx pros sepe e DEC DEC ADD ADD ADD ADD ADD IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 1 RLC RLC ADC ADC ADC ADC ADC IR1 r1 r2 r1 Ir2 R2 R1 2 1 2 INC INC SUB SUB SUB SUB SUB R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 3 SBC SBC SBC SBC SBC IRR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 OR OR OR r1 r2 r1 Ir2 R2 R1 IR2 R1 5 AND AND AND AND IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 6 TCM TCM TCM TCM TCM R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 PUSH PUSH R2 IR2 r1 r2 r1 Ir2 R2 R1 IR2 R1 LD D LH 9 RL L R1 IR1 r2 x r1 CP CP CP CP CP LDC r1 r2 r1 Ir2 R2 R1 IR2 R1 r1 Irr2 xL B CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 r2 Irr2 xL C RRC RRC LD
32. 00H OCH and register 1BH OFH INC RO RO 1CH INC 00H Register OOH ODH INC RO RO register 01H 10H In the first example if destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register OOH assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H ELECTRONICS 6 23 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 IRET Interrupt Return IRET IRET Operation FLAGS _ SP SP _ SP 1 PC _ SP SP _ SP 2 SYM 2 _ 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts Flags All flags are restored to their original settings that is the settings before the interrupt occurred Format IRET Bytes Cycles Opcode Normal Hex opc 1 10 BF 12 6 24 ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET JP Jump JP cc dst Conditional JP dst Unconditional Operation If cc is true PC _ dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply rep
33. 1 RESETB System reset signal input pin 1 8 ELECTRONICS 53 9484 9488 9488 PRODUCT OVERVIEW Table 1 2 Pin Descriptions of 32 SOP and 32 SDIP Pin Description Circuit Shared Type Functions E 2 3 5 XTIN XTOUT RESETB 0 0 PO 1 I O port with bit programmable pins 2 Configurable to input or push pull output mode Pull up resistors can be assigned by software Pins can also be assigned individually as alternative function pins E P1 0 I O port with bit programmable pins E P1 1 P1 3 Configurable to input or push pull output E 1 4 1 7 mode Pull up resistors be assigned H 14 by software Pins can also be assigned individually as alternative function pins 2 0 2 7 I O port with bit programmable pins 17 24 SEG3 SEG10 Configurable to input mode push pull output mode or n channel open drain output mode Input mode with pull up resistors can be assigned by software The port 2 pins have high current drive capability Pins can also be assigned individually as alternative function pins 0 2 port with bit programmable pins 25 31 SEG15 P3 3 Configurable to input or push pull output SEG16 RXD P3 4 mode Pull up resistors can be assigned SEG17 TXD P3 5 by software Pins can also be assigned SEG18 INTO individually as alternative function pins TAOUT INT1 TACK INT2 System clock input and output pins ADC3 TBPWM 1 ADC2 BUZ ADC1 ADCO
34. 4 and CLKCON 3 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed ELECTRONICS 8 5 RESET and POWER DOWN 8 6 NOTES 3C9484 C9488 F9488 ELECTRONICS 53 9484 9488 9488 PORTS I O PORTS OVERVIEW The 53 9484 9488 9488 microcontroller has five bit programmable I O ports PO P4 The port and 4 are 7 bit ports and the others are 8 bit ports This gives a total of 38 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required Table 9 1 gives you a general overview of the S3C9484 C9488 F9488 I O port functions Table 9 1 S3C9484 C9488 F9488 Port Configuration Overview Port Configuration Options I O port with bit programmable pins Configurable to input or push pull output mode Pull up resistors can be assigned by software Pins can also be assigned individually as alternative function pins I O port with bit programmable pins Configurable to input or push pull output mode Pull up resistors can be assigned by software Pins can also be assigned individually as alternative function pins port with bit programmable pins Configurable to input mode push pull output mode Pins can als
35. 5 SEG14 P4 6 SEG15 P3 0 SEG16 RXD P3 1 SEG17 TXD P3 2 33 1 P2 3 SEG6 32 1 P2 2 SEG5 31 P2 1 SEG4 30 P2 0 SEG3 29 L3 P4 2 SEG2 28 L3 P4 1 SEG1 27 L3 P4 0 SEGO 26 L3 P1 7 COMO 25 P1 6 COM1 SEG18 INTO P3 3 C4 1 TAOUT INT1 P3 4 2 SDAT TACK INT2 P3 5 C 3 SCLK TACAP INT3 P3 6 C3 4 24 P1 5 COM2 23 L3 P1 4 COM3 S3F9488 Top View 44 QFP XTIN PO 0 10 TEST VPP r3 9 XTour Po 1 11 3C9484 C9488 F9 488 P1 3 ADCO P1 2 ADC1 P1 1 ADC2 BUZ P1 0 ADC3 TBPWM P0 7 COMA ADCA P0 6 COMS ADC5 P0 5 COM6 ADC6 AVREF P0 4 COM7 ADC7 P0 3 ADC8 P0 2 RESETB Figure 21 1 Pin Assignment Diagram 44 Pin Package 27 ELECTRONICS 53 9484 9488 9488 SEG12 P4 4 SEG13 P4 5 SEG14 P4 6 SEG15 P3 0 SEG16 RXD P3 1 SEG17 TXD P3 2 SEG18 INTO P3 3 TAOUT INT 1 P3 4 SDAT TACK INT2 P3 5 SCLK TACAP INT3 P3 6 VDD Vss XOUT XIN VPP TEST XTiN PO 0 XTour PO 1 RESETB P0 2 AVREF COM6 ADC6 P0 5 COMS ADC5 PO 6 Q N O S3F9488 Top View 42 SDIP O P4 3 SEG11 P2 7 SEG10 P2 6 SEG9 P2 5 SEG8 P2 4 SEG7 P2 3 SEG6 P2 2 SEG5 P2 1 SEG4 P2 0 SEG3 P4 2 SEG2 P4 1 SEG1 P4 0 SEGO P1 7 COMO P1 6 COM1 P1 5 COM2 P1 4 COM3 P1 3 ADCO P1 2 ADC1 P1 1 ADC2 BUZ P1 0 ADC3 TBPWM P0 7 ADC4 COM4 Figure 21 2 Pin Assignment Diagram 42 Pin Package Vss XOUT XIN VPP TEST 0 0 XT our PO 1 RESETB P0 2 AVREF ADC3 TBPWM P1 0 a
36. 7 4 Not used for the 53 9484 9488 9488 3 P3 6 INT3 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 2 P3 5 INT2 Interrupt Pending Bit EN Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 1 P3 4 INT1 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 0 P3 3 INTO Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending ELECTRONICS 4 2 CONTROL REGISTERS 3C9484 C9488 F9488 P4CONH Port 4 Control Register High Byte FOH RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R W R W 7 6 Not used for the S3C9484 C9488 F9488 5 4 P4 6 SEG14 Input mode with pull up Input mode Push pull output Alternative function LCD SEG14 signal output 3 2 P4 5 SEG13 Input mode with pull up Input mode Push pull output 1 Alternative function LCD SEG13 signal output 1 0 P4 4 SEG12 Input mode with pull up Input mode Push pull output Alternative function LCD SEG12 signal output 4 24 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER P4CONL Port 4 Control Register Low Byte RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P4 3 SEG11 EX Input mode with pull up Input mode 1
37. 9484 9488 9488 DESCRIPTIONS PRODUCT OVERVIEW Table 1 1 Pin Descriptions of 44 QFP and 42 SDIP Pin Description 0 0 PO 1 I O port with bit programmable pins 2 Configurable to input or push pull output P0 3 mode Pull up resistors can be assigned P0 4 by software Pins can also be assigned P0 5 individually as alternative function pins P0 6 P0 7 P1 0 I O port with bit programmable pins 1 1 1 3 Configurable to input or push pull output 1 4 1 7 mode Pull up resistors be assigned by software Pins can also be assigned individually as alternative function pins 2 0 2 7 I O port with bit programmable pins Configurable to input mode push pull output mode Input mode with pull up resistors can be assigned by software The port 2 pins have high current drive capability Pins can also be assigned individually as alternative function pins P3 0 P3 2 I O port with bit programmable pins P3 3 Configurable to input or push pull output P3 4 P3 6 mode Pull up resistors can be assigned P3 5 by software Pins can also be assigned individually as alternative function pins 4 0 4 6 I O port with bit programmable pins Configurable to input mode push pull output mode Input mode with pull up resistors can be assigned by software Pins can also be assigned individually as alternative function pins System clock input and output pins clock input and output System clock input an
38. 9484 9488 9488 ELECTRICAL DATA Table 19 12 LVR Low Voltage Reset Circuit Characteristics TA 25 C Parameter sme Tet onion ne we on Bi al T E Power supply voltage rising time Power Power supply voltage off ime voltage off time Tom ELI rout consumption bom Voo BV s 10 kcwem ps pmo NOTES 1 216 fx 8 19ms at fx 8 MHz 2 Current consumed when Low Voltage reset circuit is provided internally 4 torr gt 4 tr Figure 19 8 LVR Low Voltage Reset Timing ELECTRONICS 19 13 ELECTRICAL DATA 53 9484 9488 9488 2 2 2 2 7 Supply Voltage V Minimum instruction clock 1 4 x oscillator frequency Figure 19 9 Operating Voltage Range 19 14 ELECTRONICS 53 9484 9488 9488 ELECTRICAL DATA NOTES ELECTRONICS 19 15 53 9484 9488 9488 MECHANICAL DATA 2 0 MECHANICAL DATA OVERVIEW The S3C9484 C9488 F9488 microcontroller is currently available in 32 SDIP 32 SOP 42 SDIP 44 QFP package 32 SDIP 400 9 10 0 20 27 88 MAX 27 48 0 20 5 08 N o H e 0 51 MIN 3 30 0 30 NOTE Dimensions are in millimeters Figure 20 1 32 SDIP 400 Package Dimensions ELECTRONICS 20 1 MECHANICAL DATA 3C9484 C9488 F 9488 32 SOP 450A 12 00 0 30 8 34 0 20 0 90 0 20 20 30 MAX 19 90 0 20 ILI WI UW LI LI LI LI LI LI Cd HAA AAA
39. C 10 XTout P0 1 11 SEG18 INTO P3 3 1 TAOUT INT1 P3 4 C3 2 Figure 1 2 S3C9484 C9488 F9488 Pin Assignment 44 1 4 ELECTRONICS 53 9484 9488 9488 SEG12 P4 4 SEG13 P4 5 SEG14 P4 6 SEG15 P3 0 SEG16 RXD P3 1 SEG17 TXD P3 2 SEG18 INTO P3 3 TAOUT INT1 P3 4 TACK INT2 P3 5 TACAP INT3 P3 6 VDD Vss XOUT XIN TEST XTiN PO 0 XTour PO 1 RESETB P0 2 AVREF COM6 ADC6 P0 5 COMB ADC5 PO 6 Q N O 53 9484 53 9488 53 9488 View 42 SDIP PRODUCT OVERVIEW P4 3 SEG11 P2 7 SEG10 P2 6 SEG9 P2 5 SEG8 P2 4 SEG7 P2 3 SEG6 P2 2 SEG5 P2 1 SEG4 P2 0 SEG3 P4 2 SEG2 P4 1 SEG1 P4 0 SEGO P1 7 COMO P1 6 COM1 P1 5 COM2 P1 4 COM3 P1 3 ADCO P1 2 ADC1 P1 1 ADC2 BUZ P1 0 ADC3 TBPWM P0 7 ADC4 COM4 Figure 1 3 S3C9484 C9488 F9488 Pin Assignment 42 SDIP ELEGTRONEGS PRODUCT OVERVIEW Vss Xour XIN TEST XTiN PO 0 XTour PO 1 RESETB P0 2 AVREF ADC3 TBPWM P1 0 BUZ ADC2 P 1 1 ADC1 P1 2 ADCO P1 3 1 4 2 1 5 COM1 P1 6 1 7 1 2 3 4 5 6 7 8 9 O 53 9484 53 9488 S3F9488 Top View 32 SOP 32 SDIP 53 9484 9488 9488 VDD P3 6 INT3 TACAP P3 5 INT2 TACK P3 4 INT1 TAOUT P3 3 INTO SEG18 P3 2 TXD SEG17 P3 1 RXD SEG16 P3 0 SEG15 P2 7 SEG10 P2 6 SEG9 P2 5 SEG8 P2 4 SEG7 P2 3 SEG6 P2 2 SEG5 P2 1 SEG4 P2 0 SEG3 Figure 1 4 S3C9484 C9488 F9488 Pin Assignment 32 SOP SDIP ELECTRONICS 53
40. CPU clock oscillation to stabilize The minimum required oscillation stabilization time for a reset is approximately 8 19 ms 2 fosc fosc 8MHz When a reset occurs during normal operation with both VDD and RESETB at High level the signal at the RESETB pin is forced Low and the reset operation starts All system and peripheral control registers are then set to their default hardware reset values see Table 8 1 The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction If watchdog timer is not refreshed before an end of counter condition overflow is reached the internal reset will be activated The S3C9484 C9488 F9488 has a built in low voltage reset circuit that allows detection of power voltage drop of external Vpp input level to prevent a MCU from malfunctioning in an unstable MCU power level This voltage detector works for the reset operation of MCU This Low Voltage reset includes an analog comparator and Vref circuit The value of a detection voltage is set internally by hardware The on chip Low Voltage Reset features static reset when supply voltage is below a reference voltage value you did select at smart option 3FH Thanks to this feature external reset circuit can be removed while keeping the application safety As long as the supply voltage is below the reference value there is an internal and static RESET The MCU can start only when the supply voltage rises over the referen
41. I 1 27 N epos 0 40 0 10 NOTE Dimensions are in millimeters Figure 20 2 32 SOP 450A Package Dimensions ELECTRONICS 53 9484 9488 9488 14 00 0 20 n 1 77 L gt gt NOTE Dimensions are in millimeters i ELECTRONICS 42 SDIP 600 39 50 MAX 39 10 0 20 WW 3 50 0 20 0 51 Figure 20 3 42 SDIP 600 Package Dimensions 5 08 MAX 3 30 0 30 MECHANICAL DATA MECHANICAL DATA 20 4 13 20 0 30 10 00 0 20 3C9484 C9488 F 9488 13 20 0 30 10 00 0 20 0 10 0 15 0 05 44 QFP 1010B N l eo o 2 05 0 10 NOTE Dimensions are in millimeters Figure 20 4 44 QFP 1010 Package Dimensions ELECTRONICS 53 9484 9488 9488 21 OVERVIEW The S3F9488 single chip CMOS microcontroller is the MTP Multi Time Programmable version of the 53 9484 9488 microcontroller It has an on chip Half Flash ROM instead of masked ROM The Half Flash ROM is accessed by serial data format The Half Flash ROM can be rewritten up to 100 times The S3F9488 is fully compatible with the S3C9484 C9488 in function in D C electrical characteristics and in pin configuration Because of its simple programming requirements the S3F9488 is ideal for use as an evaluation chip for the S3C9484 C9488 ELECTRONICS 21 1 MTP SEG7 P2 4 SEG8 P2 5 SEG9 P2 6 SEG10 P2 7 SEG11 P4 3 SEG12 P4 4 SEG13 P4
42. INSTRUCTION SET SCF set Carry Flag SCF Operation Flags Format Example 6 44 C 1 The carry flag C is set to logic one regardless of its previous value C Setto 1 No other flags are affected Bytes Cycles The statement SCF sets the carry flag to logic one 3C9484 C9488 F9488 Opcode Hex DF ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET SRA shift Right Arithmetic SRA Operation Flags Format Examples dst dst 7 _ dst 7 C _ dst 0 dst n _ dst n 1 n 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into bit position 6 Set if the bit shifted from the LSB position bit zero was 1 Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Always cleared to 0 Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 DO R D1 IR Given Register 9AH register 02H register OBCH and 1 SRA 00H Register OOH OCD 0 SRA 02H Register 02H register 0 In the first example if general register 00H contains the value 9AH 10011010B the statement SRA OOH shifts the bit values in register right one bit position Bit zero 0 clears the C flag and bit 7
43. Kbyte on chip The external interface is not automatically configured NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the watchdog timer function which causes a system reset if a watchdog timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of WDTCON ELECTRONICS 8 1 RESET and POWER DOWN 3C9484 C9488 F9488 HARDWARE RESET VALUES The reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values 1 0 shows the reset bit value as logic one or logic zero respectively An means that the bit value is undefined after a reset dash means that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 S3C9484 C9488 F9488 Register Values after RESET Mnemonie ee LCD control register LCD drive voltage control register Port 0 pull up resistor control register Port 1 pull up resistor control register 211 System Clock control register System flags register Oscillator control register STOP control register 215 Voltage Level Detector control register VLDCON 2 Stack pointer register 217 Location DAH DBH not mapped Basic time
44. R W R W R W R W R W 7 Not used for the 53 9484 9488 9488 6 VLD Level Set Bit Vpp is higher than reference voltage Vpp is lower than reference voltage 5 1 Reference Voltage Selection Bits 10110 Vylp 24V 10011 VvLp 2 7 V 01110 Vyp 3 3 V 01011 Vyp 3 9 V 0 VLD Operation Enable Bit EZ Operation off 4 34 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER WDTCON watchdog Timer Control Register E5H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 4 Watchdog Timer Function Enable Bits for System Reset 1 0 1 0 Disable watchdog timer function Other values Enable watchdog timer function 3 0 Watchdog Timer Counter Clear Bits Clear watchdog timer counter ELECTRONICS 4 35 CONTROL REGISTERS 3C9484 C9488 F9488 WTCON watch Timer Control Register F9H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 Watch Timer Clock Selection Bit Main system clock divided by 27 fxx 128 Sub system clock fxt 6 Watch Timer Interrupt Enable Bit Disable watch timer interrupt Enable watch timer interrupt 5 4 Buzzer Signal Selection Bits 0 0 5 kHz buzzer BUZ signal output 0 1 4 kHz buzzer BUZ signal output 1 0 2kHz buzzer BUZ signal output 4 kHz buzzer BUZ signal output 3 2 Watch Timer Speed Selection Bits Fo rjessmem 7 1 Watch Timer Enable B
45. Setting column indicates the electrical short off configuration SMDS2 Selection SAM8 In order to write data into program memory that is available in SMDS2 the target board should be selected to be for SMDS2 through a switch as follows Otherwise the program memory writing function is not available Table 22 2 The SMDS2 Tool Selection Setting suos PEJO 22 4 ELECTRONICS 53 9484 9488 9488 on OFF 3FH 2 3FH 1 3FH 0 3EH 7 Target board revision 1 3FH 7 3FH 0 2 Target board revision 0 1 There is ROM in the EVAchip So smart option is not determined by software but DIP switch 2 Target board revision number is printed on the target board Refer to the Figure 22 2 Figure 22 4 DIP Switch for Smart Option DEVELOPMENT TOOLS sm J 9 3FH 2 XTin XTout enable Normal I O pin enable 3FH 1 Internal RC oscillator Basic Timer overflow used 3FH 0 Normal I O pin enable RESET Pin enable 3EH 7 LVR disable LVR enable ELECTRONICS DEVELOPMENT TOOLS 3C9484 C9488 F9488 SEG18 INTO P3 3 P3 4 INT1 TAOUT TACK INT2 P3 5 P3 6 INT3 TACAP VDD VSS N C N C TEST XTOUT PO 1 P0 2 RESETB ADC8 P0 3 P0 4 ADC7 COM7 AVREF P0 5 ADC6 COM6 COMBS ADCS P0 6 P0 7 ADC4 COM4 TBPWM ADC3 P 1 0 P1 1 ADC2 BUZ ADC1 P1 2 P1 3 ADCO P1 5 COM2 P1 7 COMO P4 1 SEG1 COMS3 P 1 4 COM1 P1 6 SEGO P4 0 SEG2 P4 2 P2 0 SEG3 SEG4 P2 1 P2 2 SEG5 SEG6 P2 3 P2 4
46. When a conversion is completed the end of conversion EOC bit is automatically set to 1 and the result is dumped into the ADDATAH L register where it can be read The A D converter then enters an idle state Remember to read the contents of ADDATAH L before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the A D converter does not use sample and hold circuitry it is very important that fluctuation in the analog level at the ADO AD8 input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to noise will invalidate the result If the chip enters to STOP or IDLE mode in conversion process there will be a leakage current path in A D block You must use STOP or IDLE mode after ADC operation is finished ELECTRONICS 15 1 A D CONVERTER 3C9484 C9488 F9488 CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to set up A D conversion Therefore total of 50 clocks are required to complete an 10 bit conversion When Fxx 8 is selected for conversion clock with an 8 MHz fxx clock frequency one clock cycle is 1 us Each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bits set up time 50 clocks 50 clock x 1us 50 us at 1 MHz A D CONVERTER CONTROL REGISTER ADCON The A D converter control register ADCON
47. XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H R W Carry flag C _ Not mapped Zero flag 2 Sign flag S Overflow flag V Figure 6 1 System Flags Register FLAGS FLAG DESCRIPTIONS Overflow Flag FLAGS 4 V The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Sign Flag FLAGS 5 S Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Zero Flag FLAGS 6 Z For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z flag is set to 1 if the result is logic zero Carry Flag FLAGS 7 C The flag is set to 1 if the result from an arithmetic operation generates carry out from or a borrow to the bit 7 position MSB After rotate and shift operations it contains the last value shifted out of the specified
48. and LDE instructions support Indexed addressing mode for internal program memory and for external data memory when implemented Register File RPO or RP1 Value used in points to Instruction OPERAND Start or working register block Program Memory Two O d Base Address wo Operan _ Point to One of the gt INDEX SEGUE i ee dl o cx Woking Register 21 roa Sample Instruction LD RO BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES 3C9484 C9488 F9488 INDEXED ADDRESSING MODE Continued Register File EUR ae RPO or RP1 RPO or RP1 Selected RP points to start of Program Memory 5 block MM NEXT 2 Bits 4 bit Working y gdst src x L 4 1 Register Register Address oint to Working Pair Register Pair 7 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 ELECTRONICS 53 9484 9488 9488 ADDRESSING MODES INDEXED ADDRESSING MODE Concluded Register File RPO or RP1 RPO or RP1 S
49. and you can control 0 2 by this control register value 2 You must be care of the pull up resistor option Figure 9 2 Port 0 Low Byte Control Register POCONL ELECTRONICS 9 5 PORTS 3C9484 C9488 F9488 Port 0 Pull up Resistor Control Register POPUR D2H R W Reset value FFH ve P1 4 P1 3 POPUR Pin Configuration Settings 0 Pull up resistor disable 1 Pull up resistor enable Figure 9 3 Port 0 Pull up Resistor Control Register POPUR PORT 1 Port 1 is an 8 bit I O port that you can use two ways General purpose I O Alternative function Port 1 is accessed directly by writing or reading the port 1 data register P1 at location E1H Port 1 Control Register P1CONH P1CONL P1PUR Port 1 pins are configured individually by bit pair settings in three control registers located P1CONL low byte E9H P1CONH high byte E8H and P1PUR D3H When you select output mode a push pull circuit is configured In input mode many different selections are available Input mode Push pull output mode Alternative function LCD COM signal output COMO COM1 2 COM3 Alternative function TBPWM output Alternative function BUZ output Alternative function ADC input mode ADCO ADC1 ADC2 ADC3 9 6 ELECTRONICS 53 9484 9488 9488 PORTS Port 1 Control Register High Byte P1CONH E8H R W Reset value 00H COMO
50. disable bit 10100 2 6 V 0 Disable 011102 3 3V 1 Enable 01011 3 9 V ROM Address 003FH P0 0 XTin PO 1 XTout Watchdog timer PO 2 RESETB pin pin function selection bit oscillator select bit selection bit 0 XTin Xtout pin enable 0 Internal RC 0 Nomal I O P0 2 1 Normal I O pin enable oscillator used pin enable 1 Basic Timer 1 RESETB NOTES overflow used Pin enable 1 smart option value of 3DH determine P3 3 P3 6 initial port mode when cpu is reset The value of smart option is the same as normal setting value You can refer to user manual chapter 9 PORT 2 The unused bits of 3CH 3EH 3FH must be logic 1 3 When LVR is enabled LVR level must be set to appropriate value not default value 4 You must determine 0 0 0 2 function on smart option In other words After reset operation you cann t change 0 0 0 2 function For a example if you select xtin P0 0 xtout P0 1 function by smart option you cann t change on Normal I O after reset operation Equally RESETB PO 2 pin function is the same Figure 2 2 Smart Option ELECTRONICS 2 3 ADDRESS SPACES 3C9484 C9488 F9488 REGISTER ARCHITECTURE The upper 64 bytes of the S3C9484 C9488 F 9488 s internal register file are addressed as working registers system control registers and peripheral control registers The lower 192 bytes of internal register file 00 is called the general purpose register space 274 registers in this space c
51. is located at address FCH It has three functions Analog input pin selection bits 4 5 6 and 7 A D conversion End of conversion EOC status bit 3 A D conversion speed selection bits 1 2 operation start bit 0 After a reset the start bit is turned off You can select only one analog input channel at a time Other analog input pins ADCO ADC8 can be selected dynamically by manipulating the ADCON 4 6 bits And the pins not used for analog input can be used for normal I O function A D Converter Control Register ADCON AID input pin selection bits A D conversion start bit 0000 ADCO Di i 0001 ADC1 End of conversion ECO status bit _ 2 tocol 0010 ADC2 0 A D conversion is in progress Start operation Auto clear 0011 ADC3 1 A D conversion complete 0100 ADC4 Clock source selection bits 0101 ADC5 00 fxx 16 fosc 8MHz 0110 ADC6 01 fxx 8 fosc 8 2 0111 ADC7 10 fxx 4 fosc 8MHz 1000 ADC8 11 fxx fosc 4MHz Other values Connected with GND internally Maximum ADC clock input 4MHz Figure 15 1 A D Converter Control Register ADCON 15 2 ELECTRONICS 53 9484 9488 9488 A D CONVERTER Conversion Data Register High Byte ADDATAH FAH Ready only Conversion Data Register Low Byte ADDATAL FBH Ready only Figure 15 2 A D Converter Data Register ADDATAH L INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the anal
52. mode ADC4 ADC5 ADC6 ADC7 ADC8 Alternative function RESETB Alternative function Xtin Xtout ELECTRONICS 9 3 PORTS 9 4 Port 0 Control Register High Byte POCONH ve 5 2 5 s E6H R W Reset value 00H 756515 P0 7 P0 6 P0 5 P0 4 COM4 COM5 COM6 ICOM7 ADC4 ADC5 ADC6 ADC7 00 01 10 11 NOTE Figure 9 1 Port 0 High Byte Control Register POCONH Input mode Alternative function ADC4 Input Push pull output Alternative function LCD COM4 signal output Input mode Alternative function ADC5 Input Push pull output Alternative function LCD COM5 signal output Input mode Alternative function ADC6 Input Push pull output Alternative function LCD COM6 signal output Input mode Alternative function ADC7 Input Push pull output Alternative function LCD COM7 signal output You must be care of the pull up resistor option 3C9484 C9488 F9488 ELECTRONICS 53 9484 9488 9488 PORTS Port 0 Control Register Low Byte POCONL E7H R W Reset value 00H Input mode Push pull output Alternative function ADC8 input Input mode Push pull output Input mode Push pull output Input mode Push pull output NOTES 1 You must determine 0 0 0 2 function on smart option In other word After reset operation you cann t change P0 0 2 function If you selected Normal I O function at smart option After reset operation you can use on Normal I O
53. one s complement all 1s are changed to Os and vice versa Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to O Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 60 R 61 IR Examples Given R1 07H and register 07H OF1H COM R1 R1 OF8H COM R1 R1 07H register 07H OEH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits R1 all logic ones are changed to logic zeros and vice versa leaving the value OF8H 11111000 In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value OEH 00001110 ELECTRONICS 6 17 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 CP Compare CP dst src Operation dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison Flags C Set if a borrow occurred src gt dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source
54. operand cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src 6 r Ir opc src dst 3 6 A4 R R 6 5 R IR opc dst src 3 6 A6 R IM Examples 1 Given R1 02H and R2 CP R1 R2 Setthe C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 6 18 ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET DEC Decrement DEC Operation Flags Format Examples dst dst _ dst 1 The contents of the destination operand are decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if result is negative cleared otherwise V Set if arithmetic overflow occurred that is dst value is 128 80H and result value is 127 7FH cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst o
55. output 1 Alternative function LCD SEG6 signal output 5 4 nput mode with pull up Input mode 1 Push pull output 1 Alternative function LCD SEG5 signal output 3 2 P2 1 SEG4 1 0 P2 0 SEG3 0 0 Input mode with puup o O 011 Inputmode 0 Push pull output Alternative function LCD SEG3 signal output ELECTRONICS 4 19 CONTROL REGISTERS 3C9484 C9488 F9488 P3CONH Port 3 Control Register High Byte ECH RESET Value 5 5 5 5 5 5 5 5 Read Write R W R W R W R W R W R W R W R W 7 6 P3 6 TACAP INT3 0 Input mode with pull up interrupt INT3 input Input mode interrupt INT3 input TACAP Push pull output 5 4 P3 5 TACK INT2 0 0 Input mode with pull up interrupt INT2 input TACK 3 2 P3 4 TAOUT TAPWM INT1 o o mode wih pulp 914 Input mode interrupt INT1 input Pt fe Pupo SSCS 1 0 P3 3 SEG18 INTO EENI Input mode with pull up interrupt INTO input fo 1 Input mode interrupt INTO input Push pull output Alternative function LCD SEG18 signal output NOTE S of reset value mean that reset value is set by smart option 4 20 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER P3CONL Port 3 Control Register Low Byte EDH RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 5 P3 2 SEG17 TXD mamana
56. register Program instructions can set clear or complement the carry flag 6 4 ELECTRONICS 53 9484 9488 9488 INSTRUCTION SET NOTATION SAM88RCRI INSTRUCTION SET Table 6 2 Flag Notation Conventions Flag scription ELECTRONI S Carry flag Zero flag Sign flag Overflow flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Destination operand Source operand Indirect register address prefix Program counter Flags register D5H Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode 6 5 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 Table 6 4 Instruction Notation Conventions Description Condition code Working register only Working register pair Register or working register Register pair or working register pair Indirect working register only Indirect register or indirect working register Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed short offset addressing mode Indexed long offset addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode 6 6 Actual Operand Range See list of condition codes in Table 6 6 Rn n 0 15 RRp p 0 2 4 14 reg or Rn reg
57. setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Setifthe result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 Bytes Cycles Opcode Addr Mode Hex dst src 6 63 r Ir opc src dst 3 6 64 R R 65 R IR opc dst src 3 6 66 R IM Given RO 0C7H R1 02H R2 12H register OOH 2BH register 01H 02H and register 02H 23H TCM RO R1 RO OC7H R1 02H Z 1 TCM RO R1 RO OC7H R1 02H register 02H 23H Z 0 TCM 00H 01H Register OOH 2BH register 01H 02H 2 1 TCM 00H 01H Register 00H 2BH register 01H 02H register 02H 23H Z 1 TCM 00H 34 Register OOH 2BH Z 0 In the first example if working register RO contains the value 11000111B and register R1 the value 02H 00000010B the statement TCM 1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic be tested to determine the result of the TCM operation ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET TM Test Under Mask Operation Flags Format Examples dst src
58. the voltage at Vpp goes to High level and the RESET pin is forced to Low level The RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings S3C9484 C9488 F9488 into a known operating status To allow time for internal CPU clock oscillation to stabilize the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required oscillation stabilization time for a reset operation is 1millisecond Whenever a reset occurs during normal operation that is when both and RESET are High level the RESET pin is forced Low and the reset operation starts All system and peripheral control registers are then reset to their default hardware values In summary the following sequence of events occurs during a reset operation Interrupt is disabled The watchdog function is enabled Ports 0 4 are set to input mode except 0 0 2 P3 3 6 Peripheral control and data registers are disabled and reset to their default hardware values program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed NORMAL MODE RESET OPERATION In normal masked ROM mode the Test pin is tied to Ves A reset enables access to the 4 8
59. underflow Timer B start stop bit 11 Invaild setting 0 Stop timer 1 Start timer B Timer B underflow interrupt enable bit 0 Disable interrupt 1 Enable interrupt Figure 11 6 Timer B Control Register TBCON Timer B Data High Byte Register TBDATAH F6H R W Reset Value FFh Timer B Data Low Byte Register TBDATAL F7H R W Reset Value FFh Figure 11 7 Timer B DATA Registers TBDATAH TBDATAL ELECTRONICS 8 BIT TIMER A B 3C9484 C9488 F 9488 Programming Tip Using Timer A fxx 8MHz 800usec interval INCLUDE VECTOR ORG DB DB DB DB ORG RESET C SKSTUDIO INCLUDE REG S3C9488 REG 00 9488 003CH OFFH OFFH 01100000B 00000011B 100H WDTCON 10101010B BTCON 0001011B CLKCON 00011000B SP 0COH SYM 00H OSCCON 00000000B P3CONH 10101110B TADATA 100 TACON 10001011B DISABLE LVR SUB OSCILLATOR BT OVERFLOW RESET PIN ENALBE TAOUT Fxx 64 INTERVAL MODE TIMER START F9488 INT TA MC INT END TINTPND 01H NC TA_MC_INT TINTPND 0 CHECK WHAT INTERRUPT IS ENABLED ELECTRONICS 53 9484 9488 9488 8 Programming Using Timer fxx 8MHz Duty 2 8 80kHz INCLUDE C SKSTUDIO INCLUDE REG S3C9488 REG VECTOR 00H F9488_INT ORG 003CH DB OFFH DB OFFH DB 01100000B DISABLE LVR DB 00000011B SUB OSCILLATOR BT OVERFLOW RESET PIN ENALBE ORG 100H RESET DI LD WDTCON 10101010B
60. 000 before changing PAGE PAGEO gt PAGE 1 you must disable global interrupt DI and during accessing PAGE1 you don t have to use CALL instruction ELECTRONICS 14 3 LCD CONTROLLER DRIVER 3C9484 C9488 F9488 LCD CONTROL REGISTER LCDCON DOH The LCD control register LCDCON is mapped to RAM addresses DOH LCDCON controls these LCD functions LCD module enable disable control LCDCON 7 LCD Duty and Bias selection LCDCON 5 LCDCON 4 LCD dot on off control bit LCDCON 3 LCDCON 2 LCD clock frequency selection LCDCON 1 LCDCON 0 The LCD clock signal determines the frequency of COM signal scanning of each segment output This is also referred to as the frame frequency Since LCD clock is generated by dividing the watch timer clock fw the watch timer must be enabled when the LCD display is turned on RESET clears the LCDCON register values to logic zero This produces the following LCD control settings LCD clock frequency is the watch timer clock fw 2 256 Hz The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source LCD Converter Control Register LCDCON DOH R W Reset 00H LCD module enable disable bit LCD Clock selection bits 0 LCD module disable 00 fw 27 1 LCD module enable Not used 11 fw 2 LCD Duty and Bias selection bits LCD mode selection bits 00 1 8 1 4 bias 00 Dot off signal
61. 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value 11001101B in destination register ELECTRONICS 6 45 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 STOP Stop Operation STOP Operation Flags Format Example 6 46 The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or External interrupt input For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 The statement LD STOPCON 0A5H STOP NOP NOP NOP halts all microcontroller operations When STOPCON register is not 0A5H value if you use STOP instruction PC is changed to reset address ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET SUB subtract SUB Operation Flags Format Examples ELECTRONICS dst src dst _ dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source o
62. 1 4 Duty 1 3 Bias Display Mode 14 12 ELECTRONICS 53 9484 9488 9488 PROGRAMMING Using The LCD Display INCLUDE LCD_DATAO_P1 ORG ORG RESET LCD CONTROLLER DRIVER C ASKSTUDIO INCLUDE REG S3C9488 REG EQU 00H DB OFFH DB OFFH DB 01100000B DB 00000011B WDTCON 10101010B BTCON 0001011B CLKCON 00011000B SP 0COH SYM 00H OSCCON 00000000B LCDCON 10001000B LCDVOL 10001111B POCONH 0FFH POCONL 11101010B P1CONH 0FFH P1PUR 00H P2CONH 0FFH P2CONL 0FFH P3CONH 10101011B P3CONL 11111111B P4CONH 00111111B P4CONL 0FFH WTCON 02H Smart Option setting 1 8 duty 1 4 bias fw 128 lcd contrast enable 16 16 step COM4 COM7 COM0 COM3 5 7 5 10 5 5 5 18 5 15 5 17 5 12 5 14 SEGO SEG2 SEG11 Watch Timer enable ELEGTRONIGS 14 13 3C9484 C9488 F9488 LCD CONTROLLER DRIVER MAIN LD SYM 01H SELECT PAGE LD RO LCD_DATAO P1 LCD DISPLAY DATA RAMO LD R2 0 LD R3 0 LOOP LDC R1 LCD_DATA RR2 LD RO R1 INC RO INC R3 cP R3 13H JP C LOOP LD SYM 00H SELECT PAGEO JP LCD_DATA DB 00H 48H 34H 0D0H 22H 11H 89H 0E2H 35H 0FFH DB 77H 33H 67H 99H 46H 0F1H 4H 88H 54H END 14 14 ELECTRONICS 53 9484 9488 9488 A D CONVERTER 10 BIT ANALOG TO DIGITAL CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the nine input channels to equi
63. 1H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS 53 9484 9488 9488 ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction The instructions that support RA addressing is JR Program Memory Next OPCODE Program Memory Address Used Current PC Value Displacement Current Instruction OPCODE Signed Po Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES 3C9484 C9488 F9488 IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD Figure 3 14 Immediate Addressing 3 14 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER CONTROL REGISTERS OVERVIEW Control register descrip
64. 21 S3 C9484 C9488 F9488 092003 USER S MANUAL 53 9484 9488 9488 8 bit CMOS Microcontroller Revision 1 ELECTRONICS 53 9484 9488 9488 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C9 SERIES MICROCONTROLLERS Samsung s SAM88RCRI family of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes address data bus architecture a large number of bit configurable I O ports provide a flexible programming environment for applications with varied memory and I O requirements Timer counters with selectable operating modes are included to support real time operations 3C9484 C9488 F9488 MICROCONTROLLER The 53 9484 9488 9488 single chip CMOS microcontrollers are fabricated using the highly advanced CMOS process technology based on Samsung s latest CPU architecture The S3C9484 is a microcontroller with a 4K byte mask programmable ROM embedded The S3C9488 is a microcontroller with a 8K byte mask programmable ROM embedded The S3F9488 is a microcontroller with a 8K byte multi time programmable ROM embedded Using a proven modular design approach Samsung engineers have successfully developed the S3C9484 C9488 F 9488 by integrating the following peripheral modules with the powerful SAM88 RCRI core Five configurable I O ports 38 pins with 8 pin LED direct drive and LCD display Ten interrupt sources with one vector and one
65. 2SDIP 32SOP EPROM Programmability User Program multi time Programmed at the factory 21 4 ELECTRONICS 53 9484 9488 9488 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a host system any standard computer that employs Win95 98 2000 XP as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator SMDS2 or SK 1000 for the S3C7 S3C9 and S3C8 microcontroller families SMDS2 is a newly improved version of SMDS2 and 5 1000 is supported by a third party tool vendor Samsung also offers supporting software that includes debugger an assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be easily sized moved scrolled highlighted added or removed SASM The SASM takes a source file containing assembly language statements and translates them into a corresponding source code an object code and comments The SASM supports macros and condition
66. 34 Port 2 control Low register 235 Port 3 control High register 236 Port 3 control Low register 237 Port 3 interrupt control register 238 Port 3 interrupt pending register 239 Port 4 control High register 240 Port 4 control Low register 241 Timer A Timer B interrupt pending register 242 Timer A control register 243 Timer A counter register 244 Timer A data register 245 Timer B data register high byte 246 Timer B data register low byte 247 Timer B control register 248 Watch timer control register 249 250 251 252 253 254 255 A D converter data register high byte ADDATAH converter data register low byte ADDATAL A D converter control register UART control register UART data register FFH R W 4 2 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER Table 4 2 LCD display Register and Peripheral Registers page 1 Register Name LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM LCD Display RAM Location 13H is not mapped UART baud rate data register high byte 20 UART baud rate data register low byte BRDATAL 21 NOTE When you use the SK 1000 SK 8xx MDS the BRDATAH BRDATAL of mnemonic isn t showed on the system register window of MDS application program be
67. 3C9484 C9488 F9488 PORT 3 Port is an 7 bit I O Port that you can use two ways General purpose I O Alternative function Port 3 is accessed directly by writing or reading the port 3 data register P3 at location E3H Port 3 Control Interrupt Control Register P3CONL Port 3 pins are configured individually by bit pair settings in two control registers located P3CONL low byte EDH high byte When you select output mode a push pull circuit is configured In input mode many different selections are available Input mode Push pull output mode Alternative function Timer A signal in out mode TAOUT TAPWM TACAP TACK Alternative function External interrupt input INTO INT1 INT2 INT3 Alternative function LCD SEG signal output SEG15 SEG16 SEG17 SEG18 Alternative function UART module TXD RXD 9 12 ELECTRONICS 53 9484 9488 9488 PORTS Port 3 Control Register High Byte ECH R W Reset value 00H P3 6 P3 5 P3 4 P3 3 TACK TAOUT SEG18 INT3 INT2 INT1 INTO Input mode with pull up External interrupt input INT3 TACAP Input mode External interrupt input INT3 TACAP Push pull output Open drain output Input mode with pull up External interrupt input INT2 TACK Input mode External interrupt input INT2 TACK Push pull output Open drain output Input mode with pull up Ex
68. 488 F 9488 8 BIT TIMER B OVERVIEW The 53 9484 9488 9488 micro controller has an 8 bit counter called timer Timer which be used to generate the carrier frequency of a remote controller signal As a normal interval timer generating a timer B interrupt at programmed time intervals TBCON 6 7 2 0 Underflow TBUF TBCON 3 Pending Timer Data Low Byte Register TINTPND 2 Timer B Data High Byte Register Data Bus In case of setting TBCON 5 4 at 10 the value of the TBDATAL register is loaded into the 8 bit counter when the operation of the timer B starts And then if a underflow occurs in the counter the value of the TBDATAH register is loaded with the value of the 8 bit counter However if the next borrow occurs the value of the TBDATAL register is loaded with the value of the 8 bit counter Figure 11 5 Timer B Functional Block Diagram 11 6 ELECTRONICS 53 9484 9488 9488 8 Timer Control Register TBCON F8H R W Reset 00H wes 5 2 1 Timer B input clock selection bit Timer B output flip flop 00 fxx 1 control bit 01 fxx 2 0 is low 10 fxx 4 1 T FF is high 11 fxx 8 Timer B mode selection bit 0 One shot mode 1 Repeating mode Timer B interrupt time selection bit 00 Interrupt on TBDATAL underflow 01 Interrupt on TBDATAH underflow 10 Interrupt on TBDATAH and TBDATAL
69. 4H RESET Value 0 0 0 Read Write R W R W R W 7 Oscillator IRQ Wake up Function Enable Bit Enable IRQ for main system oscillator wake up function 1 Disable IRQ for main system oscillator wake up function 6 5 Not used for the 53C9484 C9488 F 9488 4 3 CPU Clock System Clock Selection Bits note cops fee SSS 2 0 Not used for the 53 9484 9488 9488 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 ELECTRONICS 4 7 CONTROL REGISTERS 3C9484 C9488 F9488 FLAGS System Flags Register D5H Bit Identifier 7 6 5s 4 3 2 a 9 RESET Value x x x x Read Write R W R W R W R W 7 Carry Flag E Operation does not generate a carry or borrow condition Operation generates a carry out or borrow into high order bit 7 6 Zero Flag Z Operation result is a non zero value Operation result is zero 5 Sign Flag S Operation generates a positive number MSB 0 Operation generates a negative number MSB 1 4 Overflow Flag V 0 Operation result is lt 127 or 128 Operation result is gt 127 or lt 128 3 0 Not used for the S3C9484 C9488 F9488 4 8 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER LCDCON cb Control Register DOH RESET Value 0 0 0 0 0 0 0 Read
70. 8 F9488 PORT 2 Port 2 is an 8 bit I O port that you can use two ways General purpose I O Alternative function Port 2 is accessed directly by writing or reading the port 2 data register P2 at location E2H Port 2 Control Register 2 P2CONL Port 2 pins are configured individually by bit pair settings in two control registers located P2CONL low byte EBH and P2CONH high byte EAH When you select output mode a push pull circuit is configured In input mode many different selections are available input mode Push pull output mode Alternative function LCD SEG signal output SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 Port 2 Control Register Low Byte P2CONL EBH R W Reset value 00H HM 0 SEG3 an 1 SEG4 P2 2 SEG5 P2 3 SEG6 P2CONL Pin Configuration Settings Input mode with pull up Input mode Push pull output Alternative function LCD SEG 6 3 signal output Figure 9 7 Port 2 High Byte Control Register 2 9 10 ELECTRONICS 53 9484 9488 9488 PORTS Port 2 Control Register Low Byte P2CONL EBH R W Reset value 00H ve 5 4 T2 7 o v TLL P2 1 SEG4 P2 2 SEG5 P2 3 SEG6 P2CONL Pin Configuration Settings Input mode with pull up Input mode Push pull output Alternative function LCD SEG 6 3 signal output Figure 9 8 Port 2 Low Byte Control Register P2CONL ELECTRONICS 9 11 PORTS
71. AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in 1 bit being stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected C Unaffected Z Setifthe result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 Bytes Cycles Opcode Addr Mode Hex dst src 6 53 r Ir opc src dst 3 6 54 R R 55 R IR opc dst src 3 6 56 R IM Given R1 12H R2 register 01H 21H register 02H register OAH AND R1 R2 R1 02H R2 03H AND R1 R2 R1 02H R2 03H AND 01H 02H Register 01H 01H register 02H 03H AND 01H 02H Register 01H OOH register 02H AND 01 25 Register 01H 21H In the first example destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 ELECTRONICS 6 13 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 CALL call Procedure CALL Operation Flags Format Examples dst SP 5 1 SP lt PCL SP SP 1 SP lt PCH PC lt dst The current contents of the program counter are pushed onto the top of the stack The
72. AP pin PWM mode TAOUT Timer A has the following functional components Clock frequency divider fxx divided by 1024 256 or 64 with multiplexer External clock input pin TACK 8 bit counter TACNT 8 bit comparator and 8 bit reference data register TADATA I O pins for capture input TACAP or PWM or match output Timer overflow interrupt and match capture interrupt generation Timer A control register TACON F3H read write ELECTRONICS 11 1 8 BIT TIMER A B 3C9484 C9488 F9488 FUNCTION DESCRIPTION Timer A Interrupts The timer A module can generate two interrupts the timer A overflow interrupt TAOVF and the timer A match capture interrupt TAINT Timer A overflow interrupt pending condition must be cleared by software when it has been serviced Timer A match capture interrupt TAINT pending condition is also cleared by software when it has been serviced Interval Timer Function The timer A module can generate an interrupt the timer A match interrupt TAINT When timer A interrupt occurs and is serviced by the CPU the pending condition have to be cleared by software In interval timer mode a match signal is generated and TAOUT is toggled when the counter value is identical to the value written to the TA reference data register TADATA The match signal generates a timer A match interrupt and clears the counter If for example you write the value 10H to TADATA and
73. BUZ ADC2 P1 1 ADC1 P1 2 ADCO P1 3 1 4 2 1 5 COM1 P1 6 COMO P1 7 Q N O S3F9488 Top View 32 SOP 32 SDIP Q VDD P3 6 INT3 TACAP SCLK P3 5 INT2 TACK SDAT P3 4 INT1 TAOUT P3 3 INTO SEG 18 P3 2 TXD SEG17 P3 1 RXD SEG16 P3 0 SEG15 P2 7 SEG10 P2 6 SEG9 P2 5 SEG8 P2 4 SEG7 P2 3 SEG6 P2 2 SEG5 2 1 5 4 P2 0 SEG3 Figure 21 3 Pin Assignment Diagram 32 Pin Package ELECTRONICS MTP MTP 53 9484 9488 9 488 Table 21 1 Descriptions of Pins Used to Read Write the Flash ROM Main Chip During Programming 44 pin Serial data pin output when reading Input 9 42 pin when writing Input and push pull output port 30 32 pin can be assigned 4 44 pin Serial clock pin input only pin 10 42 pin 31 32 pin 9 44 pin Power supply pin for flash ROM cell writing 15 42 pin indicates that MTP enters into the writing mode When 12 5 V is applied MTP is in writing mode and when 5 V is applied MTP is in reading mode Option RESETB 12 44 pin 18 42 pin 7 32 pin 5 6 44 pin Logic power supply pin 11 12 42 pin 32 1 32 pin Table 21 2 Comparison of S3F9488 and 53 9484 9488 Features Characteristic S3F9488 53 9484 9488 Program Memory 8 Kbyte Flash ROM 4K 8K byte mask ROM Operating Voltage V pp 2 2 2 7 V to 5 5 V 2 2 2 7 V to 5 5 V MTP Programming Mode VDD 5 V VPP 12 5 V Pin Configuration 44QFP 42SDIP 3
74. Before running system you must select Smart Option 3FH 1 for WDT counter source If you select internal RC oscillator normally you must set Watchdog Timer to be disable before entering to STOP mode Because If WDT is not disabled reset operation will occur by WDT counter overflow If you want to use WDT in STOP IDLE mode for noise problem current may drain too much by internal RC oscillation So if noise issue is not important you had better select basic timer overflow signal for WDT counter clock source Watchdog Timer Counter Overflow Time for Reset 1 If the basic timer overflow signal is selected for the WDT counter clock source and main clock Fxx is 8MHz Basic Timer Clock Fxx 128 Fxx 1024 Fxx 4096 2 If internal RC ring oscillator is selected for the WDT counter clock source Timer for WDT overflow 1 3 47 u sec X 216 18 89msec 16 2 ELECTRONICS 53 9484 9488 9488 WATCHDOG TIMER Smart Option 3FH 1 RC 3 47MHz WDTCON Ring OSC 16bit Watchdog Timer Basic Timer Up Counter OVF WDTCON 7 4 Figure 16 2 Watchdog Timer Block Diagram ELECTRONICS 16 3 WATCHDOG TIMER 53 9484 9488 9488 NOTES 16 4 ELECTRONICS 53 9484 9488 9488 VOLTAGE LEVEL DETECTOR 1 VOLTAGE LEVEL DETECTOR OVERVIEW The 53 9484 9488 9488 micro controller has a built in VLD Voltage Level Detector circuit which allows detection of power voltage drop through software Turning the VLD operation on and
75. C IR1 r1 Irr2 r1 Ir2 D SRA SRA LDC LD IR1 r2 lrr1 IR1 IM Ir1 r2 RR LDCD LDCI LD LD LD LDC IR1 r1 Irr2 r1 Irr2 R2 R1 R2 IR1 r1 Irr2 xs CALL LD CALL LDC IRR1 IR2 R1 DA1 r2 Irr1 xs i 2 2 ELECTRONICS 6 N SAM88RCRI INSTRUCTION SET 53 9484 9488 9488 Table 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX 6 8 ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes m Always false Always true Carry I x Zero Not zero Plus I Minus II Overflow II No overflow 2 2 S 5 V V Z II Equal Not equal Z 0 Greater than or equal S XOR V 0 Less than S XOR V 1 Greater than 2 OR S V 0 Less than or equal 2 OR S V 1 Unsigned greater than or equal C 0 Unsigned less than C 1
76. D LD LD LD LD LD LD LD LD LD 3C9484 C9488 F9488 RO 01H R1 OAH register OOH 01H register 01H 20H register 02H 02H LOOP and register RO 10H R0 01H 01H RO R1 GRO RO R1 00H 01H 02H 00H 00H 0AH 00H 10H 00H 02H RO LOOP R1 SI OOP RO R1 600000000 00 RO 10H RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H RO 01H RO 01H R1 OAH register 01H OAH Register OOH 20H register 01H 20H Register 02H 20H register OOH 01H Register OOH OAH Register 01H register 01H 10H Register OOH 01H register 01H 02 register 02H 02H RO OFFH R1 OAH Register 31H OAH RO 01H R1 OAH ELECTRONICS 53 9484 9488 9488 LDC LDE Load Memory LDC LDE Operation Flags Format dst src dst _ src SAM88RCRI INSTRUCTION SET This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes or rr values an even number for program memory and odd an odd number for data memory No flags are affected opc 2 opc 3 opc 4 opc 5 opc 6 opc 10 opc NOTES dst src dst src src dst dst src src dst dst 0000 src 0000 dst 0001 src 0001 X XS DA DA DA DA DA DA DA
77. Description Baud Rate Shift register fxx 16 x 16bit BRDATA 1 8 bit UART 16 x 16bit BRDATA 1 9 bit UART 16 x 16bit BRDATA 1 NOTES 1 In mode 2 if the UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit is 0 In mode 1 if UARTCON 5 1 then the receive interrut will not be activated if a valid stop bit was not received The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits of serial data for receiving and transmitting Parity enable bits PEN is located in the UARTPND register at address FEH Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only Figure 12 1 UART Control Register UARTCON ELECTRONICS 12 3 UART 53 9484 9488 9488 UART INTERRUPT PENDING REGISTER UARTPND The UART interrupt pending register UARTPND is located at address FEH It contains the UART data transmit interrupt pending bit UARTPND 0 and the receive interrupt pending bit UARTPND 1 In mode 0 of the UART module the receive interrupt pending flag UARTPND 1 is set to 1 when the 8th receive data bit has been shifted In mode 1 or 2 the UARTPND 1 bit is set to 1 at the halfway point of the stop bit s shift time When the CPU has acknowledged the receive interrupt pending condition the UARTPND 1 flag must be cleared by software in the interrupt service routine In mode 0 of the UART mo
78. H RO R2 01H R3 04H RO _ contents of external data memory location 0104H RO 2AH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0104H RR2 working registers RO R2 _ no change 11H contents of RO is loaded into external data memory location 0104H RR2 working registers RO R2 R3 _ no change RO contents of program memory location 0061H 01H RO AAH R2 00H R3 60H RO contents of external data memory location 0061H 01H RR4 RO BBH R4 00H R5 60H 11H contents of RO is loaded into program memory location 0061H 01H 0060H 11H contents of RO is loaded into external data memory location 0061H 01H 0060H RO _ contents of program memory location 1104H 1000H 0104H RO 88H R2 01H R3 04H RO _ contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H R3 04H RO _ contents of program memory location 1104H RO 88H RO _ contents of external data memory location 1104H RO 98H 11H contents of RO is loaded into program memory location 1105H 1105H _ 11H 11H contents of RO is loaded into external data memory location 1105H 1105H _ 11H NOTE These instructions are not supported by masked ROM type devices ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET LDCD LDED Load Memory and Decrement LDCD LDED Operation Flags Format Examples dst src dst src
79. Measurement Using a Main System or Subsystem Clock Source Clock Source Generation for LCD Controller Buzzer Output Frequency Generator Timing Tests in High Speed Mode ELECTROUNICS 13 1 WATCH TIMER WATCH TIMER CONTROL REGISTER WTCON 13 2 3C9484 C9488 F9488 Watch Timer Control Register WTCON F9H R W Reset 00H Watch Timer control selection bit 0 main system clock fxx 128 1 sub system clock Watch Timer interrupt enable bit 0 Disable watch timer interrupt 1 enable watch timer interrupt Buzzer Signal Selection bits 00 0 5 kHz buzzer BUZ signal output 01 1 kHz buzzer BUZ signal output 10 2 kHz buzzer BUZ signal output 11 4 kHz buzzer BUZ signal output Watch Timer interrupt pending bit 0 interrupt is not pending When write pending bit cleared 1 interrupt is pending Watch Timer enable bit 0 Disable Watch Timer 1 Enable Watch Timer Watch Timer Speed Selection Bits 00 Set watch timer interrupt to 1 05 01 Set watch timer interrupt to 0 5S 10 Set watch timer interrupt to 0 25S 11 Set watch timer interrupt to 3 91mS NOTE Fxx is assumed to be 4 195 MHz Figure 13 1 Watch Timer Control Register WTCON ELEGTRONIGS 53 9484 9488 9488 WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM WTCON 5 WTCON 4 WTCON 3 WTCON 2 Enable Disable WTCON 1 WTCON 7 ELEGTRONEGS BUZZER Output WTCON 6 fw 64 0 5 kHz fw 32 1 kHz
80. ONTROL REGISTER VLDCON The bit 0 of VLDCON controls to run or disable the operation of Voltage level detector Basically this Vvip is set as 2 4 V by system reset and it can be changed in 4 kinds voltages by selecting Voltage Level Detector Control register VLDCON When you write 5 bit data value to VLDCON an established resistor string is selected and the VVLD is fixed in accordance with this resistor Table 17 1 shows specific of levels Voltage Level Detector Control Register VLDCON D8H R W Bit6 read only Reset value 2CH omparator Figure 17 2 Voltage Level Detect Circuit and Control Register Table 17 1 VLDCON Value and Detection Level NOTE VLDCON reset value is 2CH ELECTRONICS 17 3 VOLTAGE LEVEL DETECTOR 53 9484 9488 9 488 VOLTAGE VDD LEVEL DETECTION SEQUENCE VLD USAGE STEP 0 Don t make VLD on in normal conditions for small current consumption STEP 1 For initializing analog comparator write 3Fh to VLDCON Comparator initialization VLD enable STEP 2 Write value to reference voltage setting bits in VLDCON Voltage setting VLD enable STEP 3 Wait 10 20usec for comparator operation time Wait compare time STEP 4 Check result by loading voltage level set bit in VLDCON Check result STEP 5 For another measurement repeat above steps PROGRAMING TIP LD VLDCON 3FH Comparator initialization VLD enable STEP 1 LD VLDCON 00011101B 3 3V detection voltage setting VLD ena
81. SEG7 SEG8 P2 5 P2 6 SEG9 SEG10 P2 7 P4 3 SEG11 SEG12 P4 4 P4 5 SEG13 SEG14 P4 6 P3 0 SEG15 SEG16 RXD P3 1 P3 2 TXD SEG17 N C N C N C N C N C N C 144905 did Nid 0S Figure 22 4 44 Pin Connector for TB9484 88 Target Board Target System J101 Target Cable for Connector Part Name AS20D Order Code SM6304 06 gt 5 23 2 Figure 22 5 S3C9484 C9488 F9488 Probe Adapter for 44 pin Connector Package 27 22 6 ELECTRONICS
82. SET 3C9484 C9488 F9488 RLC Rotate Left Through Carry RLC Operation Flags Format Examples 6 40 dst dst 0 _ C C _ dst 7 dst n 1 _ dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of the carry flag replaces bit zero Set if the bit rotated from the most significant bit position bit 7 was 1 Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 10 R 4 11 IR Given Register 00H OAAH register 01H 02H and register 02H 17H C 0 RLC 00H Register OOH 54H C 1 RLC 01H Register 01H 02H register 02H 2 0 In the first example if general register OOH has the value OAAH 10101010B the statement RLC rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register OOH leaving the value 55H 01010101B The MSB of register resets the carry flag to 1 and sets the overflow flag ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET RR Rotate Right RR Operation Flags
83. SK 1000 Target EPROM Writer Unit Application RAM Break Display Unit System Probe Adapter Trace Timer Unit TB9484 88 SAM9 Base Unit Target Board EVA Power Supply Unit Chip Figure 22 1 SMDS or SK 1000 Product Configuration 22 2 ELECTRONICS 53 9484 9488 9488 DEVELOPMENT TOOLS TB9484 9488 TARGET BOARD The TB9484 9488 target board is used for the S3C9484 C9488 F9488 microcontrollers It is supported by the SK 1000 SMDS2 development systems TB9484 88 lt lt OFF ON IDLE STOP RESET O 74HC11 5 1 N 0 USE PORT X tal O 32KHz 144 QFP S3E9480 EVA Chip E REVO REV1 gt 3EH 7 3FH 2 3EH 0 3FH 1 3EH 1 3FH 0 O 3EH 2 3FH 7 50 Pin Connector 1 SMDS2 SMDS2 SMxxxx Figure 22 2 TB9484 88 Target Board Configuration ELECTRONICS 22 3 DEVELOPMENT TOOLS 3C9484 C9488 F9488 Table 22 1 Power Selection Settings for TB9484 88 To User Vcc Settings Operating Mode To user Vcc The SK 1000 SMDS2 main TB9484 88 External board supplies Vcc to the Vcc target board evaluation chip and the target system Vcc I SK 1000 SMDS2 To user_Vcc The SK 1000 SMDS2 main board supplies Vcc only to the target board evaluation chip The target system must have its own power supply External Vcc SK 1000 SMDS2 NOTE following symbol in the To User Vcc
84. UPT SERVICE ROUTINES Before an interrupt request can be serviced the following conditions must be met Interrupt processing must be enabled El SYM 3 1 Interrupt must be enabled at the interrupt s source peripheral control register If all of the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt machine cycle that completes the following processing sequence 1 Reset clear to 0 the global interrupt enable bit in the SYM register DI SYM 3 0 to disable all subsequent interrupts Save the program counter and status flags to stack Branch to the interrupt vector to fetch the service routine s address Pass control to the interrupt service routine When the interrupt service routine is completed an Interrupt Return instruction IRET occurs The IRET restores the PC and status flags and sets SYM 3 to 1 El allowing the CPU to process the next interrupt request GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM contains the address of the interrupt service routine Vectored interrupt processing follows this sequence Push the program counter s low byte value to stack Push the program counter s high byte value to stack Push the FLAGS register values to stack Fetch the service routine s high byte address from the vector address 0000H Fetch the service routine s low byte address from the vector a
85. Write R W R W R W R W R W R W R W 7 LCD Module enable disable Bit Disable LCD Module 1 Enable LCD Module 6 Not used for the S3C9484 C9488 F9488 5 4 LCD Duty Selection Bit o o 1 8 duty 1 4 bias ajay be SSCS 3 2 LCD Dot On Off Control Bits o ojotsme Pos os 1 0 LCD Clock Signal Selection Bits ELECTRONICS 4 9 CONTROL REGISTERS 53 9484 9488 9488 LCDVOL Control Register D1H RESET Value 0 0 0 0 0 Read Write R W R W R W R W R W 7 LCD Contrast Control Enable Disable Bit Disable LCD Contrast Module 1 Enable LCD Contrast Module Not used for the 53 9484 9488 9488 e gt 3 0 LCD Segment Port Output Selection Bits o 0 o 4 6 step The dimmest level oses o Fe pipe sum opii o mes opii o es wa as J pre onesee 3 ope peo paese 3 i ro ness oppo 1 1 4 10 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER OSCCON oscillator Control Register D6H RESET Value 0 0 0 Read Write R W R W R W 7 4 Not used for the S3C9484 C9488 F9488 3 Main System Oscillator Control Bit Main System O
86. al assembly It runs on the MS DOS operating system As it produces the re locatable object codes only the user should link object files Object files can be linked with other object files and loaded into memory SASM requires a source file and an auxiliary register file device_name reg with device specific information SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generating an object code in the standard hexadecimal format Assembled program codes include the object code used for ROM data and required In circuit emulators program control data To assemble programs SAMA requires a source file and an auxiliary definition device_name def file with device specific information HEX2ROM HEX2ROM file generates ROM code from a HEX file which is produced by the assembler A ROM code is needed to fabricate a microcontroller which has a mask ROM When generating a ROM code OBJ file by HEX2ROM the value FF is automatically filled into the unused ROM area up to the maximum ROM size of the target device ELECTRONICS 22 1 DEVELOPMENT TOOLS 3C9484 C9488 F9488 TARGET BOARDS Target boards are available for all the S3C9 series microcontrollers All the required target system cables and adapters are included with the device specific target board TB9484 88 is a specific target board for the 53 9484 9488 9488 development IBM PC AT or Compatible RS 232C Emulator SMDS2 or
87. all operating modes transmission is started when any instruction usually a write operation uses the UDATA register as its destination address In mode 0 serial data reception starts when the receive interrupt pending bit UARTPND 1 is 0 and the receive enable bit UARTCON 4 is 1 In mode 1 and 2 reception starts whenever an incoming start bit is received and the receive enable bit UARTCON 4 is set to 1 PROGRAMMING PROCEDURE To program the UART modules follow these basic steps 1 Configure P3 1 and P3 2 to alternative function RXD P3 1 TXD P3 2 for UART module by setting the P3CONL register to appropriate value Load an 8 bit value to the UARTCON control register to properly configure the UART I O module For parity generation and check in UART mode 2 set parity enable bit UARTPND 5 to 1 For interrupt generation set the UART interrupt enable bit UARTCON 1 or UARTCON O to 1 When you transmit data to the UART buffer write transmit data to UDATA the shift operation starts When the shift operation transmit receive is completed UART pending bit UARTPND 1 or UARTPND 0O is set to 1 and an UART interrupt request is generated oa fF WN ELECTRONICS 12 1 UART UART CONTROL REGISTER UARTCON 3C9484 C9488 F9488 The control register for the UART is called UARTCON at address FDH It has the following control functions Operating mode and baud rate selection Multiprocessor communication an
88. an be accessed 208 are available for general purpose use And 19 are available for LCD display register But if LCD driver not used available for general purpose use For many SAM88RCRI microcontrollers the addressable area of the internal register file is further expanded by additional register pages at space of the general purpose register QOH BFH This register file expansion is not implemented in the S3C9484 C9488 F9488 however The specific register types and the area in bytes that they occupy in the internal register file are summarized in Table 2 1 Table 2 1 Register Type Summary Register Type Number of Bytes 47 System and peripheral registers pageO amp page1 General purpose registers including the 16 bit 208 common working register area LCD display Registers page1 19 Total Addressable Bytes 2 4 ELECTRONICS 53 9484 9488 9488 ADDRESS SPACES Peripheral Control Registers 64 Bytes of Common Area System Control Registers Working Registers General Purpose 192 Bytes Register File and Stack Area 15H 1 LCD Display Registers amp 22 Bytes Peripheral Register 00H Figure 2 3 Internal Register File Organization ELECTRONICS 2 5 ADDRESS SPACES 3C9484 C9488 F9488 COMMON WORKING REGISTER AREA COH CFH The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce e
89. at Examples dst dst _ SP SP _ SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one No flags affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 50 R 51 IR Given Register 00H 01H register 01H 1BH SP OD9H OBBH and stack register OBBH 55H POP 00H amp Register OOH 55H SP OBCH POP 00H Register OOH 01H register 01H 55H SP OBCH In the first example general register contains the value 01H The statement POP 00H loads the contents of location OBBH 55H into destination register and then increments the stack pointer by one Register then contains the value 55H and the SP points to location OBCH ELECTRONICS 6 35 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 PUSH Push To Stack PUSH Operation Flags Format Examples src SP _ SP 1 SP _ src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc src 2 8 70 R 71 IR Given Register 40H 4FH register 4FH OAAH SP PUSH 40H Register 40H 4FH stack register OBFH 4FH SP OBFH PUSH 40H Register 40H 4FH register OAAH stac
90. ble STEP 2 NOP NOP NOP Wait 10 20usec STEP 3 LD RO VLDCON Load VLDCON to RO STEP 4 RO 01000000B Check bit6 of RO If bit6 is VDD is lower than 3 3V JP NZ LOW VDD If not zero bit 6 is jump to LOW routine Table 17 2 Characteristics of Voltage Level Detect Circuit TA 25 C Detection Voltage VLDCON 5 1 10110b VLDCON 5 1 011105 VLDCON 5 1 010115 Current consumption VLD VLD on Vpp 5 5 V uA 17 4 ELECTRONICS 53 9484 9488 9488 VOLTAGE LEVEL DETECTOR ELECTRONICS 17 5 53 9484 9488 9488 LOW VOLTAGE RESET 1 8 LOW VOLTAGE RESET OVERVIEW The 53 9484 9488 9488 be reset in four ways by external power on reset by the external reset input pin pulled low the digital watchdog timing out by the Low Voltage reset circuit LVR During an external power on reset the voltage VDD is High level and the RESETB pin is forced Low level The RESETB signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This brings the S3C9484 C9488 F 9488 into a known operating status To ensure correct start up the user should take that reset signal is not released before the VDD level is sufficient to allow MCU operation at the chosen frequency The RESETB pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal
91. cal OR OR Operation Flags Format Examples dst src dst _ dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Set if the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 Bytes Cycles Opcode Addr Mode Hex dst src 6 43 r Ir opc src dst 3 6 44 R R 45 R IR opc dst src 3 6 46 R IM Given RO 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H OR RO R1 RO 3FH R1 2AH OR RO R2 RO R2 01H register 01H 37H OR 00H 01H Register OOH register 01H 37H OR 01H Q00H Register O8H register 01H OR 00H 02H Register 00H OAH In the first example if working register RO contains the value 15H and register R1 the value 2AH the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result in destination register RO The other examples show the use of the logical OR instruction with the various addressing modes and formats ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET POP Pop From Stack POP Operation Flags Form
92. cause BRDATAH BRDATAL is located on the general register page ELECTRONICS 4 3 CONTROL REGISTERS Bit number s that is are appended to the register name for bit addressing 4 4 Register ID Re FLAGS System Flags Register Bit Identifier RESET Value Read Write R Read on W Write only R W Read Not used 3C9484 C9488 F9488 Name of individual bit or related bits Register address gister name hexadecimal D5H x x x x v R W R W R W R W I Carry Flag C Operation does generate a carry or borrow conditio Operation generates carry out or borrow into high order bit 7 Zero Flag Z EN Operation result is a non zero value Operation result is zero Sign Flag 5 EE Operation generates positive number MSB 0 Operation generates negative number MSB 1 ly Description of the effect of specific bit settings RESET value notation Not used x Undetermined value 0 Logic zero 4 Logic one write Bit number MSB Bit 7 LSB Bit 0 Figure 4 1 Register Description Format ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER ADCON A D Converter Control Register FCH RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 4 A D Input Pin Selection Bits O ojo ojo 919019 tja j O oj t ojo j 910111495 j j
93. ce voltage When you calculate power consumption please remember that a static current of LVR circuit should be added a CPU operating current in any operating modes such as Stop Idle and normal RUN mode ELECTRONICS 18 1 LOW VOLTAGE RESET 3C9484 C9488 F9488 Smart Option 0 Watchdog RESET RESET Internal System RESETB Smart Option 3EH 7 Comparator When the Voo level is lower than 2 7V Smart Option 3EH 7 I NOTES 1 The target of voltage detection level is that you did select at smart option 3EH 2 BGR is Band Gap voltage Reference Figure 18 1 Low Voltage Reset Circuit NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the watchdog function which causes a system reset if a watchdog timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of WDTCON 18 2 ELECTRONICS 53 9484 9488 9488 1 0 ELECTRICAL DATA OVERVIEW ELECTRICAL DATA In this chapter S3C9484 C9488 F9488 electrical characteristics are presented in tables and graphs The information is arranged in the following order Absolute maximum ratings Input output capacitance D C electrical characteristics A C electrical characteristics Oscillation characteristics Oscillation stabilization time Data retention supply voltage in st
94. d 9 bit UART mode don t include start and stop bits for serial data receive and transmit Parity enable bits PEN are located in the UARTPND register at address FEH 4 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only d 4 32 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER UARTPND UART Pending and parity control FEH RESET Value 0 0 0 0 Read Write R W R W R W R W 7 6 Not used for the 53 9484 9488 9488 5 UART parity enable disable PEN O 771 4 UART receive parity error RPE E No error 3 2 Not used for the 53 9484 9488 9488 1 UART receive interrupt pending flag Not pending EN Clear pending bit when write Interrupt pending 0 UART transmit interrupt pending flag Not pending EJ Clear pending bit when write Interrupt pending NOTES 1 Inorderto clear a data transmit or receive interrupt pending flag you must write a 0 to the appropriate pending bit 2 To avoid programming errors we recommend using load instruction except for when manipulating UARTPND values Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only 4 Parity error bit RPE will be refreshed whenever 8th receive data bit has been shifted ELECTRONICS 4 33 CONTROL REGISTERS 3C9484 C9488 F9488 VLDCON Voltage Level Detector Control Register D8H RESET Value 0 1 0 1 1 0 0 Read Write R R W
95. d interrupt control Serial receive enable disable control 9th data bit location for transmit and receive operations mode 2 Parity generation and check for transmit and receive operations mode 2 UART transmit and receive interrupt control A reset clears the UARTCON value to 00H So if you want to use UART module you must write appropriate value to UARTCON ELECTRONI S 53 9484 9488 9488 UART UART Control Register UARTCON FDH R W Reset Value 00H vso si so woe ve ve sn Operating mode and baud rate selection bits see table below Transmit interrupt enable bit 0 Disable 1 Enable Multiprocessor communication Received interrupt enable bit enable bit mode 2 only 0 Disable 0 Disable 1 Enable 1 Enable If parity disable mode PEN 0 Serial data receive enable bit location of the 9th data bit that was received 0 Disable UART mode 2 0 1 1 Enable If parity enable mode PEN 1 If parity disable mode PEN 0 Even odd parity selection bit for receive data location of the 9th data bit to be transmitted in UART mode 2 in UART mode 2 0 or 1 0 Even parity check for the received data 1 Odd parity check for the received data If parity enable mode PEN 1 Even odd parity selection bit for transmit data in UART mode 2 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data MS1 MSO Mode
96. d output pins Test signal input pin for factory use only must be connected to Vas Power supply input pin ELECTRONI S Circuit 44 Pin Shared Type No Functions XTIN XTOUT RESETB ADC8 COM7 ADC7 COM6 ADC6 COMB ADC5 COM4 ADC4 19 26 ADC3 TBPWM ADC2 BUZ ADC1 ADCO COM3 COMO n 30 37 SEG3 SEG10 SEG15 1 A SEG16 RXD SEG17 TXD SEG18 INTO TAOUT INT1 TACK INT2 TACAP INT3 27 29 31 33 5 0 2 38 41 42 1 3 SEG11 14 Se 1 7 PRODUCT OVERVIEW 3C9484 C9488 F9488 Table 1 1 Pin Descriptions of 44 QFP and 42 SDIP Continued Pin Pin Description Circuit 44 Pin Shared Type Type No Functions 5 0 18 LCD segment display signal output pins 14 31 42 4 0 4 2 15 1 7 2 0 2 7 17 4 3 4 6 P3 0 P3 1 RXD P3 2 TXD P3 3 INTO COMO 7 ADCO 8 LCD common signal output pins 1 7 1 4 0 4 0 7 A D converter analog input channels 1 3 1 2 P1 1 BUZ P1 0 TBPWM P0 7 COMA P0 6 COM5 P0 5 COM6 P0 4 COM7 I P0 3 A D converter reference voltage Po Serial data RXD pin for receive input and H 17 P3 1 SEG16 transmit output mode 0 Serial data TXD pin for transmit output and H 17 44 P3 2 SEG17 shift clock output mode 0 External interrupts P3 3 SEG18 P3 4 TAOUT P3 5 TACK P3 6 TACAP TAOUT Timer counter A overflow output or Timer counter A PWM output TBPWM XTn XT Out D4 i E Clock input and output pins for subsystem P0 0 clock P0
97. ddress 0001H WON gt Branch to the service routine specified by the 16 bit vector address ELECTRONICS 5 3 INTERRUPT STRUCTURE 3C9484 C9488 F9488 53 9484 9488 9488 INTERRUPT STRUCTURE The S3C9484 C9488 F9488 microcontroller has four peripheral interrupt sources Timer A match overflow Timer B underflow P3 3 P3 4 P3 5 P3 6 external interrupt Watch Timer interrupt UART transmit interrupt receive interrupt Vector Pending Bits Enable Disable Source TINTPND O Timer A match TACON 1 TINTPND 1 Timer A Overflow TACON 2 TINTPND 2 Timer B underflow TBCON 3 P3 3 External Interrupt P3PND 0 INTO P3INT O 1 P3 4 External Interrupt P3PND 1 1 2 3 P3 5 External Interrupt P3PND 2 INT2 P3INT 4 5 P3 6 External Interrupt P3PND 3 INT3 P3INT 6 7 Watch Timer interrupt WTCON O WTCON 1 UART transmit UARTPND O UARTCON O UART receive UARTPND 1 UARTCON 1 Figure 5 3 S3C9484 C9488 F9488 Interrupt Structure 5 4 ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET SAM88RCRI INSTRUCTION SET OVERVIEW The SAM88RCRI instruction set is designed to support the large register file It includes a full complement of 8 bit arithmetic and logic operations There are 41 instructions No special I O instructions are necessary because I O control and data registers are mapped directly into the register file Flexible instruct
98. dule the transmit interrupt pending flag UARTPND O is set to 1 when the 8th transmit data bit has been shifted In mode 1 or 2 the UARTPND O bit is set at the start of the stop bit When the CPU has acknowledged the transmit interrupt pending condition the UARTPND 0 flag must be cleared by software in the interrupt service routine UART Pending Register UARTPND FEH R W Reset Value 00H we 7 s ren mre gt e o Not used Not used UART transmit interrupt pending flag 0 Not pending 0 Clear pending bit when write UART parity enable disable 1 Interrupt pending 0 Disable 1 Enable UART receive interrupt pending flag 0 Not pending UART receive parity error 0 Clear pending bit when write 0 No error 1 Interrupt pending 1 Parity error NOTES 1 In order to clear a data transmit or receive interrupt pending flag you must write a 0 to the appropriate pending bit A 0 has no effect 2 To avoid errors we recommended using load instruction when manipulating UARTPND value 3 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only Parity error bit RPE will be refreshed whenever 8th receive data bit has been shifted Figure 12 2 UART Interrupt Pending Register UARTPND 12 4 ELECTRONICS 53 9484 9488 9488 UART In mode 2 9 bit UART data by setting the parity enable bit PEN of UARTPND register to 1 the 9 data bit of transmit data will b
99. e an automatically generated parity bit Also the 9 data bit of the received data will be treated as a parity bit for checking the received data In parity enable mode PEN 1 UARTCON 3 TB8 and UARTCON 2 RB8 will be a parity selection bit for transmit and receive data respectively The UARTCON 3 8 is for settings of the even parity generation TB8 0 or the odd parity generation TB8 0 in the transmit mode The UARTCON 2 RB8 is also for settings of the even parity checking RB8 0 or the odd parity checking RB8 1 in the receive mode The parity enable generation checking functions are not available in UART mode 0 and 1 If you don t want to use a parity mode UARTCON 2 RB8 and UARTCON 3 8 a normal control bit as the 9 data bit in this case PEN must be disable 0 in mode 2 Also it is needed to select the 9th data bit to be transmitted by writing TB8 to 0 or 1 The receive parity error flag RPE will be set to 0 or 1 depending on parity error whenever the 8 data bit of the receive data has been shifted UART DATA REGISTER UDATA UART Data Register UDATA FFH R W Reset Value Undefined Transmit or Receive data Figure 12 3 UART Data Register UDATA ELECTRONICS 12 5 UART 3C9484 C9488 F9488 UART BAUD RATE DATA REGISTER BRDATAH BRDATAL The value stored in the UART baud rate register BRDATAH BRDATAL lets you determine the UART clock rate baud rate
100. e page1 is mapped for LCD display data area ELECTRONICS 2 1 ADDRESS SPACES 3C9484 C9488 F9488 PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The S3C9484 C9488 has 4K and 8Kbytes of internal mask programmable program memory The program memory address range is therefore OH OFFFH and OH 1FFFH S3F9488 have 8Kbytes locations OH 1FFFH of internal multi time programmable MTP program memory see Figure 2 1 The first 2 bytes of the ROM 0000 0001 are interrupt vector address Unused locations 0002H 00FFH except 3CH can be used as normal program memory The location 3CH 3DH 3EH and 3FH is used as smart option ROM cell The program reset address in the ROM is 0100H Decimal HEX 8 191 1FFFH 8Kbyte 53 9488 9488 Program Memory 1000H OFFFH 53 9484 Program Memory Program Start Smart option ROM cell Interrupt Vector Area Figure 2 1 Program Memory Address Space 2 2 ELECTRONICS 53 9484 9488 9488 ADDRESS SPACES Smart Option Smart option is the ROM option for starting condition of the chip The ROM addresses used by smart option are from 003CH to 003FH The default value of ROM is FFH ROM Address 003CH P3CONH 7 0 The reset value of PSCONH Port 3 Control Register High byte register is determined by 3DH 7 3DH 0 bits when CPU is reset ROM Address 003EH LVR enable LVR level selection bits Not used or
101. ecuting a DI instruction it will be serviced when you execute the instruction No flags are affected Bytes Cycles Opcode Hex opc 1 4 9F Given SYM OOH EI If the SYM register contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 08H enabling all interrupts SYM 3 is the enable bit for global interrupt processing ELECTRONICS 6 21 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 IDLE idie Operation IDLE Operation The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6F Example The instruction IDLE NOP NOP NOP stops the CPU clock but not the system clock 6 22 ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET INC Increment INC dst Operation dst _ dst 1 The contents of the destination operand are incremented by one Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is dst value is 127 7FH and result is 128 80H cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst dst opc 1 4 rE r r 0 to F opc dst 2 4 20 R 21 IR Examples Given RO 1BH register
102. ed Stop mode is executed Using an internal Interrupt to Release Stop Mode If you use Watch Timer with sub oscillator STOP mode is released by WATCH TIMER interrupt How to enter into stop mode Handling STPCON register then writing STOP instruction Keep the order 8 4 ELECTRONI S 53 9484 9488 9488 RESET and POWER DOWN Attentions of Using Stop Mode If you use 42 pin Package you must set P0 3 0 4 for output mode and must set out value on low And If you use 32 pin Package you must set P4 0 P4 6 P0 3 P0 7 for output mode and must set out value to low to prevent the leaky current in stop mode IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU but all peripherals timers remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to 00B If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON
103. elected block RP points Program Memory to Ven of working OFFSET register sevens d dst src src Register REDE OPCODE i ee 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in Instruction Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES 3C9484 C9488 F9488 DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte or 1 LSB Selects Program OPCODE Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded i
104. enable disable are at your hardwired option e Port P0 0 P0 2 P3 3 P3 6 mode selection at Reset e Watchdog Timer oscillator selection ELECTRONICS 53 9484 9488 9488 PRODUCT OVERVIEW BLOCK DIAGRAM 0 7 1 0 1 7 ADC4 8 COM4 7 AVREF ADCO 3 COMO 3 5522222 Y 2222252 XIN XTIN XOUT XTOUT OSC RESET RESET P0 2 Port and Interrupt Control 8 Bit Basic Timer TAOUT P3 4 lt 8 Bit TACK P3 5 gt Timer TACAP P3 6 gt Counter P2 0 P2 7 SEG3 10 P3 0 P3 6 SEG15 18 INTO 3 SAM88RCRI CPU P4 0 P4 6 SEGO 2 SEG11 14 Watchdog Timer with RC oscillator i 8 Bit TBPWM P1 0 Timer 7 Counter SEGO 18 BUZ P1 1 Watch Timer TXD P3 2 RXD P3 1 Figure 1 1 S3C9484 C9488 F9488 Block Diagram ELECTRONICS 1 3 PRODUCT OVERVIEW 3C9484 C9488 F9488 PIN ASSIGNMENT 33 L3 P2 3 SEG6 32 1 P22 SEG5 31 P2 1 SEG4 30 P2 0 SEG3 29 P4 2 SEG2 28 m P4 1 SEG1 27 P4 0 SEGO 26 1 P1 7 COMO 25 P1 6 COM1 24 M P1 5 COM2 23 P1 4 COM3 SEG7 P2 4 P1 3 ADCO SEG8 P2 5 53 9484 P1 2 ADC1 SEGO9 P2 6 P1 1 ADC2 BUZ SEG10 P2 7 53 9488 P1 0 ADC3 TBPWM SEG11 P4 3 S3F9488 P0 7 COM4 ADC4 SEG12 P4 4 P0 6 COM5 ADC5 SEG13 P4 5 Top View P0 5 COM6 ADC6 SEG14 P4 6 AVREF SEG15 P3 0 44 QFP P0 4 COM7 ADC7 SEG16 RXD P3 1 P0 3 ADC8 SEG17 TXD P3 2 PO 2 RESETB TACK INT2 P3 5 3 TACAP INT3 P3 6 4 XTin PO 0
105. ent Output low leakage current Pull up resistor m COM output Vpp 5 V voltage deviation Vi c4 COMI IO 15 p pA i 0 7 Vpp Vig 5 V Vi c4 SEGi IO 15 p pA i 0 18 lt g SEG output voltage deviation lt ELECTRONICS 19 3 ELECTRICAL DATA 3C9484 C9488 F9488 Table 19 2 D C Electrical Characteristics Concluded TA 25 C to 85 C Vpp 2 2V to 5 5 V LCD Voltage Dividing Ricp 40 1 kQ Resister Vic3 OUTPUT VOLTAGE Vica Vpp71 8V to 5 5V 1 4 bias 0 75Vpp 0 2 0 75Vpp 0 75 02 V LCD clock 0Hz Vica Vpp OUTPUT VOLTAGE 0 5Vpp 0 2 0 5Vpp 0 2 OUTPUT VOLTAGE 0 25Vpp 0 2 0 25V5p_ 0 25Vpp 0 2 Supply current 1 2 2 8 MHz crystal oscillator Vpp 3 V 10 8 MHz crystal oscillator Ipp2 lIdle mode Vpp 5 V 10 8 MHz crystal oscillator Idle mode Vpp 3 V 10 8 MHz crystal oscillator T 1 2 1 Supply current does not include current drawn through internal pull up resistors or external output current loads 2 lpp4 and include a power consumption of subsystem oscillator Sub operating main osc stop Vpp 3V 10 32768 Hz crystal oscillator Sub idle mode main osc stop 32768 Hz crystal oscillator Main stop mode sub osc stop 00 5 0 5 10 3 0 4 3 Vpp 5 V 10 Ta 25 yp 75 12 4 3 1 3 1 5 4 1 2 1 0 40 7 1 0 5 V
106. er Ae Value used in Instruction Execution 8 bit Register File Address One Operand Instruction Example Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Point to RPO ot RP1 RPO or RP1 Selected RP points Program Memory 4 bit Working Register OPCODE B d OPERAND Working Register TwoOperand 7 Instruction Example 1 of 8 Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing 3 2 to start of working register block ELECTRONICS 53 9484 9488 9488 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Program Memory Register File Regier _ PE f ADDRESS OPCODE Register in One Operand 4 File Instruction Example Address of Operand used by Instruct
107. erand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of the carry flag replaces bit 7 MSB 7 0 Set if the bit rotated from the least significant bit position bit zero was 1 Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 CO R C1 IR Given Register 55H register 01H 02H register 02H 17H and C 0 RRC 00H amp Register OOH 2AH C 1 RRC 01H Register 01H 02H register 02H OBH C 1 In the first example if general register 00H contains the value 55H 01010101B the statement RRC rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in destination register 00H The sign flag and overflow flag are both cleared to O ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET SBC subtract With Carry SBC dst src Operation dst dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the s
108. flag is set to 1 so that a check can be made to verify that the conversion was successful 5 The converted digital value is loaded to the output register ADDATAH 8 bit and ADDATAL 2 bit then the ADC module enters an idle state 6 The digital conversion result can now be read from the ADDATAH and ADDATAL register Reference Voltage Input Analog Input Pin ADCO ADC8 53 9484 9488 F9488 NOTE symbol R signifies an offset resistor with a value of from 50 to 100 If this resistor is omitted the absolute accuracy will be maximum of 3 LSBs Figure 15 4 Recommended A D Converter Circuit for Highest Absolute Accuracy ELECTRONICS 15 5 A D CONVERTER 53 9484 9488 9488 NOTES 15 6 ELECTRONICS 53 9484 9488 9488 WATCHDOG TIMER 1 6 WATCHDOG TIMER OVERVIEW WHATCHDOG TIMER You can use the watchdog timer Watchdog timer provides an automatic reset mechanism with counter clock source of internal RC ring oscillation or basic timer overflow signal Watchdog timer can run in unintentional STOP IDLE mode with internal RC ring oscillator This prevents MCU from remaining in the abnormal STOP IDLE mode The functional components of the watchdog timer block are Internal RC oscillation or basic timer overflow signal Smart Option 3FH 1 selects counter clock source 16bit watchdog timer overflow condition bit15 OVF with internal ring oscillator or bit3 OVF with basic timer overfl
109. fw 16 2 kHz fw 8 4 kHz Selector Circuit Clock Frequency Selector Dividing 32 768 kHz Circuit fLcp 2 kHZ fxx 128 fxx Selected clock between fx and fxt 4 195 MHz Subsystem Clock 32 768 Hz fw Watch timer Figure 13 1 Watch Timer Circuit Diagram 13 3 WATCH TIMER 3C9484 C9488 F9488 PROGRAMMING Using The WATCH TIMER Display 3 91ms 4kHz buzzer out INCLUDE VECTOR F9488_INT IRET WATCH_T_INT AND XOR NOP NOP IRET END C SKSTUDIO INCLUDE REG S3C9488 REG 00 9488 003CH OFFH OFFH 01100000B DISABLE LVR 00000011B SUB OSCILLATOR BT OVERFLOW RESET PIN ENALBE 100H WDTCON 10101010B BTCON 0001011B CLKCON 00011000B SP 0COH SYM 00H OSCCON 00000000B P1CONL 10100110B BUZZER OUTPUT WTCON 11111110B SUB SYSTEM CLOCK 4KHz 3 91ms interval WTCON 01H CHECK WHAT INTERRUPT PENDING BIT IS SET NZ WATCH_T_INT WTCON 0FEH P1 01H PORT TOGGLE WHENEVER INTERRUPT SERVICE ROUTINE IS EXECUTED ELEGTRONIGS 53 9484 9488 9488 LCD CONTROLLER DRIVER LCD CONTROLLER DRIVER OVERVIEW 53 9484 9488 9488 micro controller can directly drive an up to 19 digit 19 segment LCD panel The LCD module has the following components LCD controller driver Display RAM 00H 12H for storing display data in page 1 19 segment output pins SEGO SEG18 8 common output pins COMO COM7 Bit setting
110. gister P3PND EFH R W Reset value 00H Not used INT2 INT1 INTO Pending Bit 0 No interrupt pending When write pending clear 1 Interrupt is pending Figure 9 13 Port 3 Interrupt Pending Register P3PND PORTS 9 15 PORTS 3C9484 C9488 F9488 PORT 4 Port 4 is an 7 bit I O port with individually configurable pins Port 4 pins are accessed directly by writing or reading the port 4 data register P4 at location E4H P4 0 P4 6 can serve as inputs with or without pull up and push pull output And they can serve as segment pins for LCD Port 4 Control Register PACONH PACONL Port 4 pins are configured individually by bit pair settings in two control registers located P4CONL low byte F1H PACONH high byte FOH When you select output mode a push pull circuit is configured In input mode many different selections are available Input mode Push pull output mode Alternative function LCD SEG signal output SEGO SEG1 SEG2 SEG11 SEG12 SEG13 SEG14 Port 4 Control Register High Byte FOH R W Reset value 00H ws 5 4 T2 a 5 v P4 4 SEG12 P4 5 SEG13 P4 6 SEG14 Not used Input mode with pull up Input mode Push pull output Alternative mode LCD SEG14 signal output Input mode with pull up Input mode Push pull output Alternative mode LCD SEG13 signal output Input mode with pull up Input mode Push pull output Al
111. has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when stop mode is released 1 During stop mode a power on reset or an interrupt occurs to trigger the Stop mode release and oscillation starts 2 If a power on reset occurred the basic timer counter will increase at the rate of fxx 4096 If an interrupt is used to release stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows When a BTCNT 4 overflow occurs normal CPU operation resumes RESET or STOP Bits 3 2 y Data Bus fxx 4096 8 Up Counter BTCNT Read Only Start the CPU note R NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Figure 10 2 Basic Timer Block Diagram ELECTRONICS 10 3 BASIC TIMER 53 9484 9488 9488 NOTES 10 4 ELECTRONICS 53 9484 9488 9488 8 8 BIT TIMER A B 8 BIT TIMERA OVERVIEW The 8 bit timer is an 8 bit general purpose timer counter Timer A has three operating modes you can select one of them using the appropriate TACON setting Interval timer mode Toggle output at TAOUT pin Capture input mode with a rising or falling edge trigger at the TAC
112. he program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode note Hex dst cc 0 to F NOTE first byte of the two byte instruction format the condition code and the op code are each four bits Given The carry flag 1 and LABEL X 1FF7H JR C LABEL X amp 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET LD Load LD dst src Operation dst _ src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src dst opc src 2 4 r IM 4 r8 r R r OtoF 4 D7 Ir r opc src dst 3 6 E4 R R 6 E5 R IR opc dst src 3 6 E6 R IM 6 D6 IR IM src dst R R ELECTRONICS 6 27 SAM88RCRI INSTRUCTION SET LD Load LD Continued Examples Given LD LD L
113. her Register Pair Program Memory or 1 of 4 Data Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in OPERAND Instruction Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS 53 9484 9488 9488 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC
114. imer Oscillator Oscillator Circuit Circuit OSCCON 3 OSCCON 0 d OSCCON 2 ik Basic Timer OSC inst 1 8 1 4096 Timer Counter Frequency STPCON Dividing Watch Timer fxx 128 Circuit LCD Controller 11 1 22 1 8 1 16 A D Converter cLkcon 4 3 Selector 2 Figure 7 3 System Clock Circuit Diagram 7 2 ELECTRONICS 53 9484 9488 9488 CLOCK CIRCUIT SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located at address D4H It is read write addressable and has the following functions Oscillator frequency divide by value After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to 8 2 or od1 System Clock Control Register CLKCON D4H R W ve 7 TST T4 T T2 T2 T5 Not used Not used Oscillator IRQ Wake up Divide by selection bits for Function Enable Bit CPU clock frequency 0 Enable IRQ for main system 00 fxx 16 oscillator wake up function 01 fxx 8 1 Disable IRQ for main system 10 fxx 2 oscillator wake up function 11 fxx 1 non divided Figure 7 4 System Clock Control Register CLKCON MAIN SUBSYSTEM OSCILLATOR SELECTION OSCCON When a main oscillator is selected users cannot stop operating of a main oscillator by handling the OSCCON register but sub oscillator can be stopped If users intend to stop operating of a main oscillato
115. interrupt level One watchdog timer function with two source clock Basic Timer overflow and internal RC oscillator One 8 bit basic timer for oscillation stabilization Watch timer for real time clock Two 8 bit timer counter with time interval PWM and Capture mode Analog to digital converter with 9 input channels and 10 bit resolution One asynchronous UART The S3C9484 C9488 F9488 microcontroller is ideal for use in a wide range of home applications requiring simple timer counter ADC LED or LCD display with ADC application etc They are currently available in 32 pin SOP SDIP 42 pin SDIP and 44 pin QFP package MTP S3F9488 has on chip 8 Kbyte multi time programmable MTP ROM instead of masked ROM The S3F 9488 is fully compatible to the S3C9488 in function in D C electrical characteristics and in pin configuration ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU e SAM88RCRI CPU core Memory e 208 byte general purpose register RAM e 4 8 Kbyte internal mask program memory e 8 Kbyte internal multi time program memory S3F9488 Oscillation Sources e Crystal Ceramic e clock divider 1 1 1 2 1 8 1 16 Instruction Set e 41 instructions e IDLE and STOP instructions added for power down modes Instruction Execution Time e 500 ns at 8 MHz fosc minimum Interrupts e 10 interrupt sources with one vector one level Ports e Total 38 bit programmable pins
116. ion Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES 3C9484 C9488 F9488 INDIRECT REGISTER ADDRESSING MODE Continued Register File REGISTER Example Instruction References OPCODE Points to Progam Resserner 16 Bit Memory Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND CALL RR2 Instruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS 53 9484 9488 9488 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPO or RP1 RPO or RP1 Selected RP points Program Memory to start fo m working register block i F C Working Register Point to the ADDRESS Address Working Register G C quK Value used in OPERAND j C T Sample Instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES 3C9484 C9488 F9488 INDIRECT REGISTER ADDRESSING MODE Concluded Register File MSB Points to RPO or RP1 RPO or RP1 Selected RP points to start of working register block Program Memory 4 bit Working Register Address y Register Next 2 bit Point Pair Example Instruction REN to Working References eit
117. ions for bit addressing rotate and shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 13 bit program memory or data memory addresses For detailed information about register addressing please refer to Chapter 2 Address Spaces ADDRESSING MODES There are six addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA and Immediate IM For detailed descriptions of these addressing modes please refer to Chapter 3 Addressing Modes ELECTRONICS 6 1 SAM88RCRI INSTRUCTION SET Mnemonic Operands Load Instructions CLR dst LD dst src LDC dst src LDE dst src LDCD dst src LDED dst src LDCI dst src LDEI dst src POP dst PUSH src Arithmetic Instructions ADC dst src ADD dst src CP dst src DEC dst INC dst SBC dst src SUB dst src Logic Instructions AND dst src COM dst OR dst src XOR dst src 6 2 3C9484 C9488 F9488 Table 6 1 Instruction Group Summary Instruction Clear Load Load program memory Load external data memory Load program memory and decrement Load external data memory and decrement Load program memory and increment Load external data memory and increment Pop from stack Push to stack Add with carry Add
118. it Disable watch timer Clear frequency dividing circuits Enable watch timer 0 Watch Timer Interrupt Pending Bit K Interrupt is not pending Clear pending bit when write 1 Interrupt is pending 4 36 ELECTRONICS 53 9484 9488 9488 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW SAM88RCRI interrupt structure has two basic components a vector and sources The number of interrupt sources be serviced through an interrupt vector which is assigned in ROM address 0000 VECTOR SOURCES 51 52 NOTES 1 The SAM88RCRI interrupt has only one vector address 0000 0001 2 The numbern of Sn value is expandable Figure 5 1 S3C9 Series Interrupt Type INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can be controlled in two ways either globally or specific interrupt level and source The system level control points in the interrupt structure are therefore Global interrupt enable and disable by El and DI instructions Interrupt source enable and disable settings in the corresponding peripheral control register s ELECTRONICS 5 1 INTERRUPT STRUCTURE 3C9484 C9488 F9488 ENABLE DISABLE INTERRUPT INSTRUCTIONS El The system mode register SYM DFH is used to enable and disable interrupt processing SYM 3 is the enable and disable bit for global interrupt processing respectively by modifying SYM 3 An Enable Interrupt El instruction must be included in the ini
119. its 7 and 6 to 01 3 Write transmission data to the shift register UDATA FFH The start and stop bits are generated automatically by hardware Mode 1 Receive Procedure 1 Select the baud rate to be generated by 16bit BRDATA 2 Select mode 1 and set the RE Receive Enable bit in the UARTCON register to 1 3 The start bit low 0 condition at the RxD P3 1 pin will cause the UART module to start the serial data receive operation Tx ej R R n n n R n Tr H Write to Shift Register UDATA e _ _ __ JL H Transmit TIP d Seng DO X X D2 X X X ps X po X vr StopBit subesse tne TTL TTL T L LIL l L IL JL L RIP Receive Figure 12 7 Timing Diagram for UART Mode 1 Operation 12 10 ELECTRONICS 53 9484 9488 9488 UART UART MODE 2 FUNCTION DESCRIPTION In mode 2 11 bits are transmitted through the TxD pin or received through the RxD pin Each data frame has four components Start bit 0 8 data bits LSB first Programmable 9th data bit or parity bit Stop bit 1 lt In parity disable mode PEN 0 gt The 9th data bit to be transmitted can be assigned a value of 0 or 1 by writing the TB8 bit UARTCON 3 When receiving the 9th data bit that is received is written to the RB8 bit UARTCON 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 x 16bit BRDATA 1 clock frequency lt In par
120. ity enable mode PEN 1 gt The 9th data bit to be transmitted can be an automatically generated parity of 0 or 1 depending on a parity generation by means of TB8 bit UARTCON 3 When receiving the received 9th data bit is treated as a parity for checking receive data by means of the RB8 bit UARTCON 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 x 16bit BRDATA 1 clock frequency Mode 2 Transmit Procedure 1 Select the baud rate generated by 16bit BRDATA 2 Select mode 2 9 bit UART by setting UARTCON bits 6 and 7 to 10B Also select the 9th data bit to be transmitted by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 0 if you don t use a parity mode If you want to use the parity enable mode select the parity bit to be transmitted by writing TB8 to O or 1 and set PEN bit of UARTPND register to 1 3 Write transmission data to the shift register UDATA FFH to start the transmit operation Mode 2 Receive Procedure 1 Select the baud rate to be generated by 16bit BRDATA Select mode 2 and set the receive enable bit RE in the UARTCON register to 1 If you don t use a parity mode set PEN bit of UARTPND register to 0 to disable parity mode If you want to use the parity enable mode select the parity type to be check by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 1 Only 8 bits BitO to Bit7 of received data are available for data value 4
121. k register OBFH OAAH SP OBFH In the first example if the stack pointer contains the value OCOH and general register 40H the value the statement PUSH 40H decrements the stack pointer from to It then loads the contents of register 40H into location OBFH Register OBFH then contains the value 4FH and SP points to location OBFH ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET RCF Reset Carry Flag RCF RCF Operation _0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to 0 No other flags are affected Format Bytes Cycles Opcode Hex 1 4 Example Given 1 or 0 The instruction RCF clears the carry flag to logic zero ELECTRONICS 6 37 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 RET Return RET Operation Flags Format Example PC SP SP _ SP 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex opc 1 8 AF 10 Given SP OBCH SP 101AH and PC 1234 RET PC 101AH SP OBEH The statement RET pops the contents of stack p
122. l output Alternative function LCD COM1 signal output 3 2 P1 5 COM2 Input mode KEE Push pull output Alternative function LCD COM2 signal output 1 0 P1 4 COM3 o x mamm EES Push pull output Alternative function LCD COMS signal output NOTE When users use Port 1 users must be care of the pull up resistance status ELECTRONICS 4 15 CONTROL REGISTERS 3C9484 C9488 F9488 P1CONL Port 1 Control Register Low Byte E9H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P1 3 ADCO Input mode Push pull output Alternative function ADCO input 5 4 P1 2 ADC1 Input mode Push pull output Alternative function ADC1 input 3 2 P1 1 ADC2 BUZ o o mamm a olee oO 1 0 P1 0 ADC3 TBPWM olo Input mode L6 3 Alternative function TBPWM output 3 9 Push pull output Alternative function ADC3 input NOTE When users use Port 1 users must be care of the pull up resistance status 4 16 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER P1PUR Port 1 Pull up Resistor Control Register D3H RESET Value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W 7 P1 7 Pull up Resistor Enable Disable 0 Pull up resistor disable Pull up resistor enable 6 P1 6 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable 5 P1 5 P
123. laces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC Flags No flags are affected Format 1 Bytes Cycles Opcode Addr Mode 2 Hex dst dst 3 8 ccD DA cc 0 to F opc dst 2 8 30 IRR NOTES 1 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the op code are both four bits Examples Given The carry flag 1 register 00 01H and register 01 20H JP CLABELW LABEL W 1000H PC 1000H JP 00H amp PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement JP C LABEL_W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair and 01H leaving the value 0120H ELECTRONICS 6 25 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 JR Jump Relative JR Operation Flags Format Example cc dst If cc is true PC _ PC dst If the condition specified by the condition code cc is true the relative address is added to t
124. nto register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS 53 9484 9488 9488 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Address Used Memory Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES 3C9484 C9488 F9488 INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory lt Next Instruction LSB Must be Zero dst Current Instruction OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 4
125. o be assigned individually as alternative function pins I O port with bit programmable pins Configurable to input mode push pull output mode Pins can also be assigned individually as alternative function pins port with bit programmable pins Configurable to input mode push pull output mode Pins can also be assigned individually as alternative function pins ELECTRONICS 9 1 PORTS 3C9484 C9488 F9488 PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all five S3C9484 C9488 F9488 I O port data registers Data registers for ports 0 1 2 3 and 4 have the general format shown in Figure 9 1 Table 9 2 Port Data Register Summary 9 2 ELECTRONICS 53 9484 9488 9488 PORTS 0 Port 0 is an 8 bit I O Port that you can use two ways General purpose I O Alternative function Port 0 is accessed directly by writing or reading the port 0 data register PO at location EOH Port 0 Control Register POCONH POCONL POPUR Port 0 pins are configured individually by bit pair settings in three control registers located POCONL low byte E7H POCONH high byte E6H and POPUR D2H When you select output mode a push pull circuit is configured In input mode many different selections are available Input mode Push pull output mode Alternative function LCD COM signal output COM5 COM6 COM7 Alternative function ADC input
126. off can be controlled by software Because the IC consumes a large amount of current during VLD operation It is recommended that the VLD operation should be kept OFF unless it is necessary Also the VLD criteria voltage can be set by the software The criteria voltage can be set by matching to one of the 3 kinds of voltage 2 4V 2 7V 3 3V or 3 9V VDD reference voltage VLD block works only when VLDCON O is set If VDD level is lower than the reference voltage selected with VLDCON 5 1 VLDCON 6 will be set If VDD level is higher VLDCON 6 will be cleared Please do not operate the VLD block for minimize power current consumption Voltage Level Detector Control Register VLDCON D8H R W Bit6 read only Reset value 2CH ve Ts Not used Reference voltage selection bit 10110 2 4 10011 2 7 V 011102 3 3 V 01011 3 9 V VLD operation enable bit 0 Operation off 1 Operation on Voltage level set bit read only 0 is higher than reference voltage 1 VoD is lower than reference voltage Figure 17 1 VLD Control Register VLDCON ELECTRONICS 17 1 VOLTAGE LEVEL DETECTOR Vpp Pin Voltage Level Detector Voltage Level Setting 3C9484 C9488 F9 488 VLDCON 6 VLD out VLDCON O VLD run VLDCON 5 VLDCON 1 Set the level Figure 17 2 Block Diagram for Voltage Level Detect 17 2 ELECTRONICS 53 9484 9488 9488 VOLTAGE LEVEL DETECTOR VOLTAGE LEVEL DETECTOR C
127. og input voltage level is compared to the reference voltage The analog input level must remain within the range Vas to AVggr usually AVper Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first conversion bit is always 1 2 AVper ELECTRONICS 15 3 A D CONVERTER 3C9484 C9488 F9488 BLOCK DIAGRAM A D Converter Control Register ADCON FCH ADCON 0 ADC Start Control Clock ADCON 3 Circuit Selector EOC Flag ADCON 7 4 ADCO P1 3 ADC1 P1 2 ADC2 P1 1 Successive Approximation Circuit Analog Comparator ADC7 P0 4 ADC8 P0 3 Amxmreuvu Arce VDD Conversion Result D A Converter ADDATAH ADDATAL FAH FBH To data bus Figure 15 3 A D Converter Functional Block Diagram 15 4 ELECTRONICS 53 9484 9488 9488 A D CONVERTER INTERNAL A D CONVERSION PROCEDURE 1 Analog input must remain between the voltage range of VSS AVREF 2 Configure 0 3 0 7 and 1 0 1 3 for analog input before A D conversions To do this you have to load the appropriate value to the POCONH POCONL and P1CONL for ADCO ADCS registers 3 Before the conversion operation starts you must first select one of the eight input pins ADCO ADC8 by writing the appropriate value to the ADCON register 4 When conversion has been completed 50 clocks have elapsed the EOC ADCON 3
128. ointer location OBCH 10H into the high byte of the program counter The stack pointer then pops the value in location OBDH 1AH into the PC s low byte and the instruction at location 101AH is executed The stack pointer now points to memory location OBEH ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET RL Rotate Left RL dst Operation C _ dst 7 Flags Format Examples dst 0 _ dst 7 dst n 1 _ dst n n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag 7 0 gel Set if the bit rotated from the most significant bit position bit 7 was 1 Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 90 R 91 IR Given Register OOH OAAH register 01H 02H and register 02H 17H RL 00H amp Register OOH 55H C 1 RL 01H Register 01H 02H register 02H 2EH C 0 In the first example if general register OOH contains the value OAAH 10101010B the statement RL 00H rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONICS 6 39 SAM88RCRI INSTRUCTION
129. op mode A D converter electrical characteristics ELEGTRONIGS ELECTRICAL DATA 3C9484 C9488 F9488 Table 19 1 Absolute Maximum Ratings Ta 25 Parameter Symbot Cono Una Bere e maa WS 65 Mena Output current low loL One pin active Total pin current for port Table 19 2 D C Electrical Characteristics TA 25 C to 85 Vpp 2 2 V to 5 5 V Input high voltage All input pins except Viri Input low voltage All input pins except Vi BE 19 2 ELECTRONICS 53 9484 9488 9488 ELECTRICAL DATA Table 19 2 D C Electrical Characteristics Continued TA 25 C to 85 Vpp 2 2 V to 5 5 V Output high voltage Vpp 2 4 V 4mA Vpp 0 7 Vpp 0 3 P1 0 P1 1 and P3 4 P3 6 Port 2 Vous Vpp 5 V 1mA Normal output pins Output low voltage Vout Vpp 2 4 V Io 12 P1 0 P1 1 and P3 4 P3 6 Port 2 Vpp 5 V loL 4 mA Normal output pins Input high leakage current Vin All input pins except l yo lug Vi Vpp Xin XTN Input low leakage current Vin OV All input pins except 2 li2 VnF OV Xy XTN Vour All I O pins and Output pins lo Vour 9V All I O pins and Output pins Oscillator feed back Rosci Vpp 5 0 V Ta 25 C resistors XN Vpp Xour 0 V Port 0 1 2 3 4 Ty 25 C Output high leakage curr
130. or 53 9484 9488 9488 1 Page 5 Not used for 3C9484 C9488 F9488 EZENES Page 6 Not used for 3C9484 C9488 F9488 Page 7 Not used for 3C9484 C9488 F9488 NOTE Following a reset you must enable global interrupt processing by executing an El instruction not by writing a 1 to SYM 3 ELECTRONICS 4 27 CONTROL REGISTERS 3C9484 C9488 F9488 TACON Timer A Control Register F3H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 Timer A Input Clock Selection Bits Polo rune 771 Fo res SSCS 5 4 Timer A Operating Mode Selection Bits Internal mode TAOUT mode fo Capture mode capture on rising edge counter running OVF can occur 1 Capture mode capture on falling edge counter running OVF can occur 1 PWM mode OVF interrupt can occur 13 Timer Counter Clear Bit 3 No effect 1 Clear the timer A counter After clearing return to zero 2 Ti 3 er A Overflow Interrupt Enable Bit Disable interrupt 1 Enable interrupt 1 Timer A Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer Start Stop Bit Stop Timer A Start Timer A 1 4 28 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER TBCON Timer B Control Register F8H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 Timer B Input Clock Selection Bits Invalid setting 3 Timer B Underflow Interrup
131. ormal I O function at Smart option the reset value of POCONL 3 0 bits are 0000 2 When users use Port 0 users must be care of the pull up resistance status ELECTRONICS 4 13 CONTROL REGISTERS 53 9484 9488 9488 POPUR Porto Pull up Resistor Control Register D2H RESET Value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W 7 0 7 Pull up Resistor Enable Disable EN Pull up resistor disable Pull up resistor enable 6 0 6 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable 5 0 5 Pull up Resistor Enable Disable EN Pull up resistor disable Pull up resistor enable 4 0 4 Pull up Resistor Enable Disable Es Pull up resistor disable Pull up resistor enable 3 P0 3 Pull up Resistor Enable Disable ES Pull up resistor disable Pull up resistor enable 2 0 2 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable 1 0 1 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable 0 0 0 Pull up Resistor Enable Disable Pull up resistor disable 1 Pull up resistor enable 4 14 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER P1CONH Port 1 Control Register High Byte E8H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P1 7 COMO DE 1 Push pull output Alternative function LCD COMO signal output 5 4 P1 6 COM1 fo x Input mode Push pul
132. ource are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands Flags C Set if a borrow occurred src gt dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src 6 33 r Ir opc src dst 3 6 34 R R 35 R IR opc dst src 3 6 36 R IM Examples Given R1 10H R2 1 register 01H 20H register 02H and register 03H OAH SBC R1 R2 R1 OCH R2 03H SBC R1 R2 R1 05H R2 register OAH SBC 01H 02H Register 01H 1CH register 02H SBC 01H 02H Register 01H 15H register 02H 03H register 03H OAH SBC 01H Z8AH Register 01H 95H C S and V 1 In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 ELECTRONICS 6 43 SAM88RCRI
133. ow Also on STOP and IDLE mode with internal RC ring oscillator watchdog timer counter is not cleared by smart option Watchdog timer control register WDTCON E5H read write 16bit Watchdog Timer Counter WATCHDOG TIMER CONTROL REGISTER WDTCON Watchdog Timer Control Register WDTCON E5H R W Reset 00H Watchdog timer enable bits Watchdog timer counter clear bits 1010B Disable watchdog function 1010B Clear watchdog timer counter Other value Enable watchdogfunction Other value don t care Figure 16 1 Watchdog Timer Control Register WDTCON ELECTRONICS 16 1 WATCHDOG TIMER 3C9484 C9488 F9488 WATCHDOG TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the watchdog timer overflow signal WDTOVF to generate a reset by setting WDTCON 7 4 to any value other than 1010B The 1010B value disables the watchdog function A reset clears WDTCON to 00H automatically enabling the watchdog timer function The MCU is reset whenever a watchdog timer counter overflow occurs During normal operation the application program must prevent from the overflow To do this the WDTCNT value must be cleared by writing a 1010j to WDTCON 0 3 at regular intervals If a malfunction occurs due to noise or some other error conditions the watchdog counter clear operation will not be executed by chip malfunction So before long a watchdog timer overflow reset will occur After this reset chip will carr
134. pc dst 2 4 00 R 01 IR Given R1 03H and register O3H 10H DEC R1 R1 02H DEC R1 Register 03H OFH In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained the destination register by one leaving the value OFH ELECTRONICS 6 19 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 DI Disable Interrupts DI Operation Flags Format Example SYM 3 _ 0 Bit zero of the system mode register SYM 3 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex opc 1 4 8F Given SYM O8H DI If the value of the SYM register is 08H the statement DI leaves the new value 00H in the register and clears SYM 3 to 0 disabling interrupt processing ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET El Enable Interrupts El Operation Flags Format Example SYM 3 _ 1 An EI instruction sets bit 3 of the system mode register SYM 3 to 1 This allows interrupts to be serviced as they occur If an interrupt s pending bit was set while interrupt processing was disabled by ex
135. perand to the destination operand C Setif a borrow occurred cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst src 6 23 r Ir opc src dst 3 6 24 R R 25 R IR opc dst src 3 6 26 R IM Given R1 12H R2 register 01H 21H register 02H register OAH SUB R1 R2 R1 OFH R2 SUB R1 R2 R1 08H R2 03H SUB 01H 02H Register 01H register 02H SUB 01H 02H Register 01H 17H register 02H SUB 01H 90H Register 01H 91H S and V 1 SUB 01H 265H Register 01H OBCH 1 V 0 In the first example if working register R1 contains the value 12H and if register R2 contains the value 03H the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in destination register R1 6 47 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 TCM rest Complement Under Mask TCM Operation Flags Format Examples 6 48 dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by
136. pp 3 Va 10 TA 25 NOTES 3 Ipp3andlppaare the current when the main system clock oscillation stop and the subsystem clock is used And they does not include the LCD and Voltage booster and voltage level detector current Ipps is the current when the main and subsystem clock oscillation stop 5 Voltage booster s operating voltage rage is 2 0V to 5 5V 6 If you use LVR module supply current increase refer to Table 19 12 19 4 ELECTRONICS 53 9484 9488 9488 ELECTRICAL DATA Table 19 3 A C Electrical Characteristics TA 25 C to 85 Vpp 2 2 V to 5 5 V Interrupt input high low width P3 3 P3 6 RESET input low width NOTE User must keep more large value then min value tNTL tINTH r Figure 19 1 Input Timing for External Interrupts P3 3 P3 6 Figure 19 2 Input Timing for RESET ELECTRONICS 19 5 ELECTRICAL DATA 3C9484 C9488 F 9488 Table 19 4 Input Output Capacitance 25 C to 85 0 Input f 1 MHz unmeasured pins capacitance are returned to Vss capacitance I O capacitance Table 19 5 Data Retention Supply Voltage in Stop Mode TA 25 to 85 C Data retention VpppR supply voltage Data retention IDDDR w 2V supply current RESET Occurs Oscillation 4 Stabilization 31 Stop Mode p Time Y Normal 4 Data Retention Mode 4 Operating Mode
137. program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR Given RO 15H R1 21H PC 1A47H and SP 2 CALL 1521H SP OBOH Memory locations OOH 01H where 4AH is the address that follows the instruction CALL RRO SP OBOH 00H 01H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value OB2H the statement CALL 1521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location The PC is then loaded with the value 1521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL QRRO produces the same result except that the 49H is stored in stack location 01H because the two byte instruction format was used The PC is then loaded with the value 1521H the address of the first instruction in the program sequence to be execu
138. r control register BTCON 220 Basic timer counter register BTCNT 221 Location DEH is not map Register Name Address Bit Values After RESET D g ZE 2 2 2 U I g 0 0 1 1 2 2 2 g T g I D7 I 8 9 10 2 13 4 16 Og ed g System mode register Port 0 Data Register m m Port 1 Data Register Port 2 Data Register m rm N L IT Port 3 Data Register Port 4 Data Register m Watchdog timer control register WDTCON Port 0 control High register Port 0 control Low register Port 1 control High register Port 1 control Low register m m N IT 2 2 2 2 2 2 2 m co H 223 24 25 26 27 28 229 30 231 32 233 CARJA m e 53 9484 9488 9488 RESET and POWER DOWN Table 8 1 S3C9484 C9488 F9488 Registers Values after RESET continued Register Name Mnemonic Address Port 2 control High register P2CONH 234 EAH Port 2 control Low register P2CONL B Port 3 control High register P3CONH E Port 3 control Low register P3CONL E 3 3 2 2 I RICO BH U oO H m T Port 3 interrupt control register E Port 3 interrupt pending register Port 4 control High register Port 4 control Low register Timer A B interrupt pending register Timer A control register Timer A counter register Timer A data regi
139. r users must use STOP instruction When a sub oscillator is selected users must do the contrary of the above case NOTE Ifa sub oscillator is not used users must connect it to Vss ELECTRONICS 7 3 CLOCK CIRCUIT 3C9484 C9488 F9488 Oscillator Control Register OSCCON D6H R W ve 7 Tes 4 s 2 ao System clock selection bit 0 Mainsystem oscillator select 1 Subsystem oscillator select Not used Subsystem oscillator control bit 0 Subsystem oscillator RUN 1 Subsystem oscillator STOP Mainsystem oscillator control bit 0 Mainsystem oscillator RUN 1 Mainsystem oscillator STOP When the CPU is operated with fxt sub oscillation clock it is possible to use the stop instruction but in this case before using stop instructionyou must select fxx 128 for basic timer counter input clock Then the oscillation stabilization time is 62 5 1 32768 x 128 x 16 ms Here the warm up time is from the stop release signal activates until the basic timer counter counting start So the totaly needed oscillation stabilization time will be less than 162 5 ms Figure 7 5 Oscillator Control Register OSCCON STOP Control Register STPCON STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction Figure 7 6 STOP Control Register STPCON 7 4 ELECTRONICS 53 9484 9488 9488 RESET and POWER DOWN RESET and POWER DOWN SYSTEM RESET OVERVIEW During a power on reset
140. rce operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands Flags C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src 6 13 r Ir opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Examples Given R1 10H R2 C flag 1 register 01H 20H register 02H register OAH ADC R1 R2 R1 14H R2 03H ADC R1 R2 R1 1BH R2 03H ADC 01H 02H Register 01H 24H register 02H ADC 01H 02H Register 01H 2BH register 02H 03H ADC O1H 11H Register 01H 32H In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value 03H The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in regi
141. rements after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 5 High Address Stack contents Stack contents after a call Low Address after an instruction interrupt Figure 2 5 Stack Operations Stack Pointer SP Register location D9H contains the 8 bit stack pointer SP that is used for system stack operations After a reset the SP value is undetermined Because only internal memory space is implemented in the S3C9484 C9488 F9488 the SP must be initialized to an 8 bit value in the range OOH OCOH NOTE In case a Stack Pointer is initialized to OOH it is decreased to FFH when stack operation starts This means that a Stack Pointer access invalid stack area We recommend that a stack pointer is initialized to COH to set upper address of stack to BFH ELECTRONICS 2 7 ADDRESS SPACES 3C9484 C9488 F9488 PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD PUSH PUSH PUSH PUSH POP POP POP POP 2 8 SP 0COH SYM R15 20H R3 R3 20H R15 SYM SP lt COH Normally the SP is set to COH by the initialization routine Stack address SYM Stack address lt R15 Stack address OBDH lt 20H Stack address OBCH lt Stack address OBCH 20H lt S
142. s in the LCD control register LCDCON determine the LCD frame frequency duty and bias and the segment pins used for display output When a subsystem clock is selected as the LCD clock source the LCD display is enabled even during stop and idle modes The LCD Voltage control register LCDVOL switches contrast output to segment port LCD data stored in the display RAM locations are transferred to the segment signal pins automatically without program control Q COM0 COM7 LCD Controller EUR SEG0 SEG18 99 UJ m UJ c Figure 14 1 LCD Function Diagram ELECTRONICS 14 1 LCD CONTROLLER DRIVER 3C9484 C9488 F9488 LCD CIRCUIT DIAGRAM Segment Driver Timing Controller LCD Voltage Control NOTE ficp fw 2 fw 25 tw 28 tw 2 Figure 14 2 LCD Circuit Diagram 14 2 ELECTRONICS 53 9484 9488 9488 LCD CONTROLLER DRIVER LCD RAM ADDRESS AREA RAM addresses 00H 12H of page 1 are used as LCD data memory When the bit value of a display segment is 1 the LCD display is turned on when the bit value is 0 the display is turned off Display RAM data are sent out through segment pins SEGO SEG18 using a direct memory access DMA method that is synchronized with the f c signal If these RAM addresses not used for LCD display you can be allocated to general purpose use BIT7 BIT6 BIT1 BITO COM7 COM6 COM1 COMO Figure 14 3 LCD Display Data RAM Organization NOTE In MDS such as SK 1
143. scillator RUN Main System Oscillator STOP 2 Sub System Oscillator Control Bit Sub system oscillator RUN 1 Sub system oscillator STOP Not used for the 53 9484 9488 9488 0 System Clock Selection Bit Main oscillator select 1 Subsystem oscillator select ELECTRONICS 4 1 CONTROL REGISTERS 3C9484 C9488 F9488 POCONH Port 0 Control Register High Byte E6H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P0 7 COM4 ADC4 Input mode Alternative function ADC4 input Ea Push pull output 1 Alternative function LCD COM4 signal output 3 2 P0 5 COM6 ADC6 1 traion aos m 1 0 P0 4 COM7 ADC7 o Input mode fo 1 Alternative function ADC7 input ENEJ Push pull output Alternative function LCD COM7 signal output NOTE When users use Port 0 users must be care of the pull up resistance status 4 12 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER POCONL Port 0 Control Register Low Byte E7H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P0 3 ADC8 fo x Input mode 1 Push pull output Alternative function ADC8 input Push pull output 3 2 PO 1 o x mamm SSCS 1 0 0 0 o mama _ NOTES 1 Ifyou selected the Xtin Xtout function at Smart option no relations to POCONL 3 0 bit value But if you selected the n
144. setting UARTCON 6 and 7 to Write transmission data to the shift register UDATA FFH to start the transmission operation Mode 0 Receive Procedure 1 2 3 4 Select mode 0 by setting UATCON 6 and 7 to 00B Clear the receive interrupt pending bit UARTPND 1 by writing a 0 to UARTPND 1 Set the UART receive enable bit UARTCON 4 to 1 The shift clock will now be output to the TxD P3 2 pin and will read the data at the RxD P3 1 pin A UART receive interrupt vector 00H 01H occurs when UARTCON 1 is set to 1 to Shift Register UDATA Shift X X m X 5 X 5 X 5 X 5 X 7 TxD Shift Clock TIP Write to UARTPND Clear RIP and set RE Transmit Shift DO D1 D2 D3 D4 05 06 07 x RxD Data In TxD Shift Clock 1 2 3 4 5 6 7 8 Figure 12 6 Timing Diagram for UART Mode 0 Operation ELECTRONICS 12 9 UART 3C9484 C9488 F9488 UART MODE 1 FUNCTION DESCRIPTION In mode 1 10 bits are transmitted through the TxD P3 2 pin or received through the RxD P3 1 pin Each data frame has three components Start bit 0 8 data bits LSB first Stop bit 1 When receiving the stop bit is written to the RB8 bit in the UARTCON register The baud rate for mode 1 is variable Mode 1 Transmit Procedure 1 Select the baud rate generated by 16bit BRDATA 2 Select mode 1 8 bit UART by setting UARTCON b
145. ster R1 ELECTRONICS 6 11 SAM88RCRI INSTRUCTION SET 3C9484 C9488 F9488 ADD ADD dst src Operation dst _ dst src Flags Format Examples The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed C Setif there is a carry from the most significant bit of the result cleared otherwise Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst src 6 03 r Ir opc src dst 3 6 04 R R 6 05 R IR opc dst src 3 6 06 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H OAH ADD R1 R2 R1 15H R2 03H ADD R1 R2 R1 1CH R2 03H ADD 01H 02H Register 01H 24H register 02H ADD 01H 02H Register 01H 2BH register 02H ADD O1H 25H 6 Register 01H 46H In the first example destination working register R1 contains 12H and the source working register R2 contains The statement ADD R1 R2 adds to 12H leaving the value 15H in register R1 ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET AND Logical AND AND Operation Flags Format Examples dst src dst _ dst
146. ster TADATA Timer B data register high byte Timer B data register low byte Timer B control register Watch timer control register converter data register high byte 250 A D converter data register low byte A D converter control register F mm gt L T 2 T I 1 19 oj o d T Z Z NOTE Not mapped or not used x Undefined S be set by Smart option ELECTRONICS 8 3 RESET and POWER DOWN 3C9484 C9488 F9488 POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than 3 pA All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by interrupts NOTE Do not use stop mode if you are using an external clock source because Xy input must be restricted internally to Vgg to reduce current leakage Using RESET to Release Stop Mode Stop mode is released when the RESET signal is released and returns to high level all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock 1 16 because CLKCON 3
147. t Enable Bit Disable Interrupt 1 Enable Interrupt 2 Ti 3 er B Start Stop Bit Stop timer B 1 Start timer B 1 Timer B Mode Selection Bit One shot mode 3 1 Repeating mode 0 Timer Output flip flop Control Bit 0 T FF is low 1 T FF is high NOTE fxxis selected clock for system ELECTRONICS 4 2 CONTROL REGISTERS 3C9484 C9488 F9488 TINTPND Timer Interrupt Pending Register F2H RESET Value 0 0 0 Read Write R W R W R W 7 3 Not used for the 53 9484 9488 9488 2 Timer B Underflow Interrupt Pending Bit No interrupt pending Clear pending bit when write Interrupt pending 1 Timer A Overflow Interrupt Pending Bit EN No interrupt pending Clear pending bit when write Interrupt pending 0 Timer Match Capture Interrupt Pending Bit No interrupt pending ES Clear pending bit when write Interrupt pending 4 30 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER UARTCON UART Control Register FDH RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 Operating mode and baud rate selection bits o 0 Mode 0 Shift Register fxx 16 16bit BRDATA 1 0 1 Mode 1 8 bit UART fxx 16 16bit BRDATA 1 1 x Mode 2 9 bit UART fxx 16 x 16bit BRDATA 1 5 Multiprocessor 1 enable bit for modes 2 only Disable 1 Enable 4 Serial data receive enable bit
148. tack address OBDH R15 lt Stack address OBEH SYM lt Stack address ELECTRONI S 53 9484 9488 9488 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Register R Indirect Register IR Indexed X Direct Address DA Indirect Address 1 Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES 3C9484 C9488 F9488 REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Register File OPERAND oint to One PA OPCODE Register in Regist
149. te control register When P3CONH 5 4 is 00 and 01 the TACAP input or normal input is selected When P3CONH 5 4 is set to 10 and 11 output is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflow occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the TADATA register By reading the captured data value in TADATA and assuming a specific value for the timer A clock frequency you can calculate the pulse width duration of the signal that is being input at the TACAP pin 11 2 ELECTRONICS 53 9484 9488 9488 8 TIMER A CONTROL REGISTER You use the timer A control register TACON Select the timer A operating mode interval timer capture mode and PWM mode Select the timer A input clock frequency Clear the timer A counter TACNT Enable the timer A overflow interrupt or timer A match capture interrupt Timer A start stop Clear timer A match capture interrupt pending conditions TACON is located at address F3H and is read write addressable using Register addressing mode A reset clears TACON to This sets timer A to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer A interrupts You can clear the timer A counter at any time during normal operation by writing a 1
150. ted ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET CCF Complement Carry Flag CCF Operation The carry flag is complemented If C 1 the value of the carry flag is changed to logic zero if C 0 the value of the carry flag is changed to logic one Flags C Complemented No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 EF Example Given carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one ELECTRONICS 6 15 SAM88RCRI INSTRUCTION SET CLR clear CLR dst Operation dst _ 0 The destination location is cleared to 0 Flags No flags are affected Format opc dst Examples Given Register 00H 4FH register 01H CLR 00H Register 00H CLR 01H Register 01H 53 9484 9488 9488 Bytes Cycles Opcode Addr Mode Hex dst 2 4 BO R B1 IR 02H and register 02H 00H 02H register 02H OOH In Register R addressing mode the statement CLR OOH clears the destination register OOH value to OOH In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to 00H ELECTRONICS 53 9484 9488 9488 SAM88RCRI INSTRUCTION SET COM Complement COM dst Operation dst _ NOT dst The contents of the destination location are complemented
151. ter clear bit 3 is set the 8 bit counter is cleared and it also is cleared automatically Figure 11 1 Timer A Control Register TACON ELECTRONICS 11 3 8 BIT TIMER A B 3C9484 C9488 F 9488 Timer Interrupt Pending Register TINTPND F2H Reset 00H RW Not Used Timer A macth capture interrupt pending flag Timer B underflow 0 Not pending interrupt pending flag 0 Clear pending bit 0 Not pending When write 0 Clear pending bit 1 Interrupt pending When write 1 Interrupt pending Timer A overflow interrupt pending flag 0 Not pending 0 Clear pending bit When write 1 Interrupt pending Figure 11 2 Timer interrupts Pending Register TINTPND Timer A Data Register TADATA F5H R W Reset Value FFh Figure 11 3 Timer A DATA Register TADATA 11 4 ELECTRONICS 53 9484 9488 9488 8 BLOCK DIAGRAM TACON 2 TACON 7 6 TACON O TINTPND 1 fxx 1024 fxx 256 CI 8 bit Up Counter gar lt TACON 3 fxx 64 _ Read Only TACK TACON 1 Match TAINT 8 bit Comparator M ER NE x Pending x M 4 U Ey TINTPND O X Timer A Buffer Reg M U X 5 4 Timer Data Register Read Write TACON 5 4 Data Bus NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 11 4 Timer A Functional Block Diagram ELECTRONICS 11 5 8 BIT TIMER A B 3C9484 C9
152. ternal interrupt input INT 1 Input mode External interrupt input INT1 Push pull output Alternative mode TAOUT TAPWM output 00 Input mode with pull up External interrupt input INTO 01 Input mode External interrupt input INTO 10 Push pull output 11 Alternative mode LCD SEG18 signal output NOTE Reset value of P3CONH is determined by Smart Option Figure 9 9 Port 3 High Byte Control Register P3CONH ELECTRONICS 9 13 PORTS Port 3 Control Register Low Byte P3CONL EDH R W Reset value 00H ESET NEN 0 SEG15 P3 1 SEG16 RXD P3 2 SEG17 TXD Input mode with pull up Input mode Push pull output Alternative mode TXD output Alternative mode LCD SEG17 signal output Input mode with pull up RXD input Input mode RXD input Push pull output Alternative mode RXD output Alternative mode LCD SEG16 signal output Input mode with pull up Input mode Push pull output Alternative mode LCD SEG15 signal output Figure 9 10 Port 3 Low Byte Control Register P3CONL 3C9484 C9488 F9488 ELECTRONICS 53 9484 9488 9488 ELECTRONICS Port 3 Interrupt Control Register P3INT EEH R W Reset value 00H 5 4 T2 2 eo 2 INT1 INTO Interrupt Enable Disable Selection Interrupt disable Interrupt enable falling edge Interrupt enable rising edge Figure 9 12 Port 3 Interrupt Control Register P3INT Port 3 Interrupt Pending Re
153. ternative mode LCD SEG12 signal output Figure 9 14 Port 4 High Byte Control Register 9 16 ELECTRONICS 53 9484 9488 9488 PORTS Port 4 Control Register Low Byte PACONL F1H R W Reset value 00H e 5 4 2 a 5 v d P4 1 SEG1 P4 2 SEG2 P4 3 SEG11 Input mode with pull up Input mode Push pull output Alternative mode LCD SEG11 signal output Input mode with pull up Input mode Push pull output Alternative mode LCD SEG2 signal output Input mode with pull up Input mode Push pull output Alternative mode LCD SEG1 signal output Input mode with pull up Input mode Push pull output Alternative mode LCD SEGO signal output Figure 9 15 Port 4 Low Byte Control Register PACONL ELECTRONICS 9 17 PORTS NOTES 53 9484 9488 9488 ELECTRONICS 53 9484 9488 9488 BASIC TIMER 1 0 BASIC TIMER OVERVIEW BASIC TIMER BT You can use the basic timer BT To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are Clock frequency divider fxx divided by 4096 1024 or 128 with multiplexer 8 bit basic timer counter DDH read only Basic timer control register DCH read write BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency
154. th data bit is 1 The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data The other slaves continue operating normally Full Duplex Multi S3C9484 C9488 F9488 Interconnect TxD RxD TxD RxD TxD RxD TxD RxD Master 53 9484 C9488 F9488 Slave 1 53 9484 9488 9488 Slave 2 53 9484 C9488 F9488 Slave n 53 9484 9488 F9488 Figure 12 9 Connection Example for Multiprocessor Serial Data Communications 53 9484 9488 9488 WATCH TIMER 1 3 WATCH TIMER OVERVIEW Watch timer functions include real time and watch time measurement and interval timing for the system clock To start watch timer operation set bit 1 and bit 6 of the watch timer mode register WTCON 1 and 6 to 1 After the watch timer starts and elapses a time the watch timer interrupt is automatically set to 1 and interrupt requests commence in 3 9ms 0 25 s 0 5s or 1 0s intervals The watch timer can generate a steady 0 5kHz 1kHz 2 kHz or 4 kHz signal to the BUZZER output By setting WTCON 3 and WTCON 2 to 11b the watch timer will function in high speed mode generating an interrupt every 3 91 ms High speed mode is useful for timing events for program debugging sequences The watch timer supplies the clock frequency for the LCD controller f cp Therefore if the watch timer is disabled the LCD controller does not operate Real Time and Watch Time
155. tialization routine that follows a reset operation in order to enable interrupt processing Although you can manipulate SYM 3 directly to enable and disable interrupts during normal operation we recommend that you use the El and DI instructions for this purpose INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed the application program s service routine must clear the appropriate ending bit before the return from interrupt subroutine IRET occurs INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM88RCRI the order of service is determined by a sequence of source which is executed in interrupt service routine El Instruction Execution Interrupt Pending Register RESET Interrpt priority is determind by Source Interrupts software polling Vector Interrupt Source Interrupt method Enable Cycle Global Interrupt Control El DI instruction Figure 5 2 Interrupt Function Diagram 5 2 ELECTRONICS 53 9484 9488 9488 INTERRUPT STRUCTURE INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows 1 A source generates an interrupt request by setting the interrupt request pending bit to 1 2 The CPU generates an interrupt acknowledge signal 3 The service routine starts and the source s pending flag is cleared to 0 by software 4 Interrupt priority must be determined by software polling method INTERR
156. tions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual The locations and read write characteristics of all mapped registers in the S3C9484 C9488 F9488 register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 System and Peripheral Registers Register Name LCD control register LCDCON LCD drive voltage control register Port 0 pull up resistor control register Port 1 pull up resistor control register System Clock control register System flags register Oscillator control register STOP control register Voltage Level Detector control register Stack pointer register Location DAH DBH are not mapped Basic timer control register 220 Basic timer counter register 221 Location DEH is not mapped ELECTRONICS 4 1 CONTROL REGISTERS 3C9484 C9488 F9488 Table 4 1 System and Peripheral Registers continued Register Name Mnemonic Port 0 Data Register PO Port 1 Data Register Port 2 Data Register Port 3 Data Register P4 224 225 226 227 Port 4 Data Register PA 228 Watchdog timer control register 229 Port 0 control High register 230 Port 0 control Low register 231 Port 1 control High register 232 Port 1 control Low register 233 Port 2 control High register 2
157. ull up Resistor Enable Disable resistor disable Pull up resistor enable 4 P1 4 Pull up Resistor Enable Disable 0 Pull up resistor disable Pull up resistor enable 3 P1 3 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable 2 P1 2 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable 1 P1 1 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable 0 P1 0 Pull up Resistor Enable Disable Pull up resistor disable 1 Pull up resistor enable ELECTRONICS 4 1 CONTROL REGISTERS 53 9484 9488 9488 P2CONH Port 2 Control Register High Byte EAH RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 2 7 5 10 Input mode with pull up Input mode 1 387 Push pull output 1 1 Alternative function LCD SEG10 signal output nput mode with pull up Input mode Push pull output Alternative function LCD SEG9 signal output 3 2 1 0 P2 4 SEG7 0 0 Input mode with putue O 011 Inputmode 00000 ENEJ Push pull output Alternative function LCD SEG7 signal output 4 18 ELECTRONICS 53 9484 9488 9488 CONTROL REGISTER P2CONL Port 2 Control Register Low Byte EBH RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P2 3 SEG6 lo Input mode with pull up Input mode 1 Push pull
158. valent 10 bit digital values The analog input level must lie between the AVper and Vss values The A D converter has the following components Analog comparator with successive approximation logic D A converter logic resistor string type ADC control register ADCON Nine multiplexed analog data input pins ADO 08 alternately digital data I O port 10 bit A D conversion data output register ADDATAH L pins is internally connected to Vas FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at the first you must set port control register POCONH POCONL P1CONL for AD analog input And you write the channel selection data in the A D converter control register ADCON 4 6 to select one of the eight analog input pins ADO 8 and set the conversion start bit The read write ADCON register is located at address FCH The unused pin can be used for normal I O During a normal conversion ADC logic initially set the successive approximation register to 200H the approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 7 4 in the ADCON register To start the A D conversion you should set the enable bit ADCON O
159. value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 a no select signal is sent to the corresponding segment pin Each bias has select and no select signals 8 54 Non Select Figure 14 8 Select No Select Bias Signals in Static Display Mode 4 Select Frame Figure 14 9 Select No Select Bias Signals in 1 4 Duty 1 3 Bias Display Mode ELECTRONICS 14 9 LCD CONTROLLER DRIVER 53 9484 9488 9488 14 Select 4 1 Frame COM SEG Figure 14 10 Select No Select Bias Signals in 1 8 Duty 1 4 Bias Display Mode 14 10 ELECTRONICS 53 9484 9488 9488 LCD CONTROLLER DRIVER 0 1 2 3 4 5 6 7 0 11 2 3 4 5 6 7 lt 1 Frame 0 1 2 3 4 5 6 7 Data Register page1 Data Register page 1 Address 00H LD OOH 5Dh Address 01H LD 01H 2Eh Figure 14 11 LCD Signal and Wave Forms Example in 1 8 Duty 1 4 Bias Display Mode ELECTRONICS 14 11 LCD CONTROLLER DRIVER 53 9484 9488 9488 011 2 3 011213 Framl T FR Frame Q o 1 t o x x x x 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Data Register page12 Data Register page 1 Address 03H Data Register page 1 Address 02H Address 00H LD 02H 03h LD 03H 06h LD 00H 0Eh Data Register page 1 Address 01H LD 01H 03h Figure 14 12 LCD Signals and Wave Forms Example in
160. xecution time This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Registers are addressed either as a single 8 bit register or as a paired 16 bit register In 16 bit register pairs the address of the first 8 bit register is always an even number and the address of the next register is an odd number The most significant byte of the 16 bit data is always stored in the even numbered register the least significant byte is always stored in the next 1 odd numbered register Even address Figure 2 4 16 Bit Register Pairs 2 6 ELECTRONICS 53 9484 9488 9488 ADDRESS SPACES SYSTEM STACK S3F9 series microcontrollers use the system stack for subroutine calls and returns and to store data The PUSH and POP instructions are used to control system stack operations The S3C9484 C9488 F9488 architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls and interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS registers are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address always decrements before a push operation and inc
161. ximum CPU clock frequency is 8 MHz The Xy and Xour pins connect the external oscillator or clock source to the on chip clock circuit SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON Oscillator control register OSCCON and STOP control register STPCON 53 9484 53 9484 9488 9488 9488 9488 Figure 7 1 Main Oscillator Circuit Figure 7 2 Main Oscillator Circuit Crystal or Ceramic Oscillator RC Oscillator ELECTRONICS 7 1 CLOCK CIRCUIT 3C9484 C9488 F9488 CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows In Stop mode the main oscillator is halted Stop mode is released and the oscillator started by a reset operation or an external interrupt with RC delay noise filter and can be released by internal interrupt too when the sub system oscillator is running and watch timer is operating with sub system clock In Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt Stop Release Main System Sub system Watch T
162. y out normal operation again In other words during the normal operation the watchdog timer overflow bit 3 overflow or bit 15 overflow of the 16 bit watchdog timer counter WDTCNT does not occur by a 16bit Watchdog timer counter clear operation Watchdog Timer Counter Clock Sources Selection You can select counter clock source between basic timer overflow signal and internal RC ring oscillator If you use basic timer overflow clock source WDT overflow will occur at the time when counter bit 3 is set If you use internal RC ring oscillator clock source WDT overflow will occur at the time when counter bit 15 is set Watchdog Timer in STOP IDLE mode 1 If the basic timer overflow signal is selected for the WDT counter clock source WDT will be disabled automatically by hardware So system reset can not occur by WDT WDT counter is cleared automatically in STOP IDLE mode In this case current consumption is very small 2 If internal RC ring oscillator is selected for the WDT counter clock source WDT can be enabled in unintentional STOP IDLE mode So system reset can occur by WDT WDT counter is not cleared in STOP IDLE mode So when abnormal STOP or IDLE mode occurs by noise MCU can be returned to normal operation by WDT overflow reset But at this case STOP IDLE mode current consumption becomes larger If noise problem like chip entering to unintentional STOP IDLE mode is more important you had better use internal RC ring oscillator

USER`S MANUAL - Dataman Programmers Ltd.

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