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Configuration and programming software (CAPS)

1. define DEBUG always Jy Direct memory access Tf KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KK KK KKK KKKKKKKKKKKKKKKAKKAK KK KK define _DMA always define _DMA_ChannelO always define _DMA_Channell always define _DMA Channel2 always 48 56 3 Designing with CAPS UM0225 49 56 define _DMA Channel3 always define _DMA_Channel4 always define _DMA_Channel5 always define _DMA_Channel6 always define _DMA_Channel7 always Jy Clock source
2. define _RTC always Tf System Control unit Jy KKK KKK KEK K KKK kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkk kkk define _SCU always Watch dog A define _WDG always DEBUG
3. GPIO type register setting Ek define GPIOTYPEO 0x0 define GPIOTYPE1 0x0 define GPIOTYPE2 0x0 define GPIOTYPE3 0x0 define GPIOTYPE4 0x0 define GPIOTYPE5 0x0 define GPIOTYPE6 0x0 define GPIOTYPE7 0x0 define GPIOTYPE8 0x0 define GPIOTYPE9 0x0 id GPIO direction register setting KKK KKK KKK KKK KKK KKK KKK KKK KK KK KKK KKK KKK KK KKK KK KKK KKK define GPIO_DIRO 0x0 define GPIO_DIR1 0x0 UM0225 3 Designing with CAPS de de de de de de de de de de de de de de de de de de Bk fine GPIO_DIR2 0x0 fine GPIO_DIR3 0x0 fine GPIO_DIR4 0x0 fine GPIO_DIR5 0x
4. Flash memory interface AF define _FMI always Wakeup interrupt unit define _WIU always i Real time clock
5. define _SSP Synchronous Serial Port define _SSPO Synchronous Serial Port 0 define _SSP1 Synchronous Serial Port 1 Timer fine _TMR Timer gt At least one of the timers is enabled define _TMRO Timer 0 fine _TMR1 Timer 1 enabled 50 56 3 Designing with CAPS UM0225 51 56 define _TMR2 Timer 2 define _TMR3 Timer 3 J UART
6. define _ENET Ethernet I2C KKK KKK KKK KK KKK KEK KK KEK KKK KKK KK KKK KKK KKK KKK KK KK KKK KKK 91 91 KKK define _12C I2C define _12CO I2C0 serial interface define _I2C1 I2C1 serial interface KKEKKKKKKKKKKKKKKKKKKKKKKKKK KK KKK KKK KK KKK KKK KKK KKK MC Motor Control define _MC Induction Motor Control SSP Synchronous Serial Port
7. CAN define _CAN CAN KKKKKKKKKKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK EMI External Memory Interface define _EMI EMI define SCU_EMI 0x0 Port8 and Port 9 is not connected to EMI block if de de ENET Ethernet
8. define _Device_Type STR912FW44X6 Tf System AHB and peripheral APB Buses define _AHBAPB always define _AHBAPBO always define _AHBAPB1 always Vectored interrupt controller Ey define _VIC always define _VICO always define _VIC1 always Jy
9. define _UART UART gt At least of the UARTs is enabled define _UARTO UART 0 enabled define _UART1 UART 1 define _UART2 UART 2 USB define _USB USB enabled define _USBCLK SCU_USBCLK_EXT Use external clock void Device_Init void endif _ new912_128 h EREREREEEREEE Copyright C 2005 2006 STMicroelectronics Inc eeeeeeeeeee 3 UM0225 3 Designing with CAPS Appendix D FlashLINK Cable Install fast JTAG driver Warning Dual Processor System or HyperThreading Enabled System Please do NOT install the D 1 Note D 2 D 2 1 D 2 2 3 fast JTAG driver JTD for FlashLINK cable The reason is that the JTD driver is not designed to handle code reentrancy as such it cannot support two processes at the same time Refer to the workaround solution described below Driver installation To install the FlashL
10. define _MCLK_Source SCU_MCLK_PLL define _Main_Crystal 25000 00 In KHz Lif Phase Lock Loop PLL setting Jy KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KK kkk kkk kkk kkk kkk k k define _PLL_M 25 M 1 lt M lt 255 value for phase lock loop define _PLL_N 192 N 1 lt N lt 255 value for phase lock loop define _PLL_P 2 P 1 lt P lt 5 value for phase lock loop clocks divisor setting define _RCLK_Divisor SCU_RCLK_Divl Reference clock divisor define _HCLK_Divisor SCU_HCLK_Divl1l ARM high speed bus divisor define _PCLK_Divisor SCU_PCLK_Div2 ARM Perip
11. The dialog guides you through the following programming steps 1 Select programming file and target device By default the programming data file for the currently active session is displayed Use the Browse button to open another previously saved programming data file The type of target device associated with the programming data file is shown in the Select device box Use the drop down menu to change the device type Note All other file related operations within this dialog window operate on the current programming data file 2 Specify JTAG ISP operation and conditions Choose one of the available JTAG ISP operations using the Select operation drop down menu Refer to 3 7 1 JTAG ISP operations for a more detailed discussion of the programming options Note These operations should only be performed on a target device in a known operational state The JTAG ISP operation may be applied to the following device memory regions Main Flash e Secondary Flash e User Code e Configuration e OTP One or more regions may be selected simultaneously by clicking the desired checkbox es As a convenience click the All checkbox to select all regions for the JTAG ISP operation To automatically merge the MCU firmware click the Merge MCU firmware checkbox 35 56 Ky UM0225 3 Designing with CAPS Click the Properties button to view the JTAG ISP attributes This displays the configuration dialog shown in Figure 33
12. D 2 3 D 2 4 53 56 1 To uninstall the JTD go to the command line prompt and type gt gt JTDCFGW uninstall This command uninstalls the fast JTAG driver from your system If you are unable to boot into Windows a press and hold F8 immediately during boot up b Select Safe Mode to skip loading the JTD driver On systems that continue loading JTD driver boot into Safe Mode with command prompt Rename JTD sys and JTDMSG dll in the WINDOWS system32 drivers folder to prevent loading the JTD driver upon bootup c Reboot into Normal mode and restore the above two file names before executing JTDCFGW uninstall 2 Ifyou have not already installed PEP driver go to CAPS subfolder Drivers Needhams and invoke INSTALL BAT lf INSTALL BAT does not exist then go to your prompt command line prompt and follow the steps below gt gt Run regpep gt gt Copy pepnt sys windir system32 drivers 3 Goto the CAPS folder and update uPSDsoft IN as follows JTAG Driver PEP indicates the PEP driver is used OD indicates the JTD driver is used 4 Reboot your system Hyper thread enabled system using solution 1 Use the following steps to disable hyper thread and use the fast JTD driver 1 During power on Press F2 to enter CMOS setup 2 Move to CPU Information 3 Choose hyper thread and toggle to disabled 4 Save the configuration and continue with the boot process Follow the steps below to instal
13. 27 UM0225 Yy User manual Configuration and programming software CAPS tool for STR9 families Introduction Configuration and Programming Software CAPS is the configuration software for the STR9 family microcontroller The CAPS configuration tool allows you to easily configure the STR9 using simple drag and drop and point and click operations CAPS also supports In System Programming through an external JTAG adapter allowing fast In System Programming of the STR9 in both development and production environments This is the CAPS user manual describing CAPS software functionality When working with the CAPS tool you are also encouraged to download the datasheet associated with your particular device the datasheet may provide the only source of important configuration information needed for your design Getting started gives an introduction to CAPS installation procedures and hardware requirements Although installation may seem trivial it is highly recommended that you carefully follow ne instructions because many problems are often caused by incorrectly installing CAPS This is followed by ntroduction to the CAPS user interface which describes g2naral CAPS usability and the design process The Designing with CAPS section gives detailed information about eacu SAPS feature The appendices provide reference material useful for design anc cralysis August 2006 Rev 2 1 56 www st com UM0169 1 56 Gettingl star
14. 1 CAPS user interface shows the basic CAPS user interface components followed by a brief description of each component Following sections describes the menu bar in more detail Specific functionality is described in Designing with CAPS The CAPS software is a Windows based program As such the user interface implements basic interface conventions commonly found in Windows programs 6 56 2 Introduction to the CAPS user interface UM0225 Figure 1 CAPS user interface Title Bar CAPS new upj LVD Voltage Menu Bar Project Tools View Help Toolbar 2 25 e gx LYD Voltage Clocks Peripheral Pin Assignment Pin Summary Manage m Step 1 Specify Voltage Project The 5TR91xF requires two separate operating voltage supplies The CPU and memories operate from a 1 65 to 2 0V on the VDD pins and the 1 0 ting operates at 2 7V to 3 6 on the VDDQ pins oy Specify the VDDQ LYD threshold voltage Design C27 Entry F Recommendations Choose 2 4 LVD threshold voltage ta go with VDDQ of 2 7V to 3 3V 2 Choose 2 7 LYD threshold voltage to go with VDDG of 3 0 to 3 6V Additional Note If you intend to use USB VDDQ of 3 3 is required in order to meet USB specifications Settings You should select 2 7 LVD threshold voltage 4 Apply Program Device 6 Open project C CAPS Projects new new upj Status Bar For Help press F1 Project new D
15. 2 channels for SPI SSI or Microwire 8 16 bit External Memory Interface EMI 4 standard 16 bit Standard Timers TIM 3 Phase Induction Motor Controller IMC JTAG Interface with Boundary Scan Embedded Trace Module ETM Real Time Clock Flexible Power Management For Help press Fl Project N A Device N A 03 24 2006 23 06 27 Project names must be unique Otherwise CAPS displays the error message shown in Figure 9 Create project dialog error Figure 9 Create project dialog error xl A project name entered already exists Please enter a different Project name 3 15 56 UM0225 3 Designing with CAPS Click OK and enter a different project name to continue 3 1 Design flow The CAPS design flow interface models the typical steps used in the design process These steps have corresponding navigation buttons shown in the left frame of the main window as shown in Figure 10 Design flow interface buttons Figure 10 Design flow interface buttons Manage Project Additional Settings Program Device The red arrow indicates the next action to be performed in the design process Click the button corresponding to the desired design and programming operation e Manage Project Design Entry Additional Settings e Program Device 3 1 1 Manage Project dialog Click the Manage Project button to access the project management functions listed below Invoke the function by clicking the r
16. 56 3 Designing with CAPS UM0225 Note 27 56 Click the desired radio buttons to assign the pins to the respective function Click the Apply button to save the assignment and to automatically lock the pin to the function When the dialog shown in Figure 20 is displayed click OK to accept the configuration and continue The Timer1 peripheral is selected and displayed in the List of assigned peripheral s as shown in Figure 22 Figure 22 Example selected Timer1 peripheral Step 1 Select the peripheral from the List of available peripheral s box for GPIO pins assignment List of available peripherals List of assigned peripheralfs Embedded Trace Interface Ethernet MII Interface External DMA Request External Interrupt Request External Memory Interface lt lt Unassign Legend Legend Assignable Unassignadic Mouse over the Timer peripheral in the List of assigned peripheral s to view pin resource utilization as shown in Figure 23 The example shows the functions dynamically assigned to pins 1 P4_2 and 50 P3_1 As an alternative you may also view resource utilization using the Tools Generate Project Report menu or use Pin Summary for a graphic display of pin utilization Figure 23 Example Timer1 pin assignment display List of assigned peripheral s Pin Name Pin Number Pin Function p3_1 59 Timer 1 Compare PWM A p4 2 1 Timer 1 Captur
17. Connect the red wire VCC to a DC voltage source 2 7 to 5 5V 5 Turn on the DC source When you are ready click OK to continue If the test passes a success message is displayed Click OK to continue 3 40 56 3 Designing with CAPS UM0225 If the test fails the dialog shown in Figure 38 Link connect test error dialog displays A similar dialog displays for the RLink option Figure 38 Link connect test error dialog FlashLINK Connect Test Status FlashLINK connect test failed Invalid port selected Check also FlashLINK connection and parallel port operability E Press OK to continue and check the physical connections between your PC and target board by performing a loopback test 4 Click the Target Connect Test button to test communication from your PC through the JTAG chain on the target board Note It is recommended that link and connectivity tests be run before attempting any JTAG operations The dialog shown in Figure 39 Target connectivity test dialog displays showing the preliminary steps required for a successful test Figure 39 Target connectivity test dialog Target Connect Test x 1 Ensure the FlashLINK cable is installed on your parallel port 2 Connect a system board to the FlashLINK unit 3 Turn on the DC source If the JTAG chain on the target board successfully responded a message displays indicating the test passed Press OK to continue If the t
18. I 1 APBDI Y 1 2438 RCLKDIV Typical 2 1 2 4 8 16 1024 RTC Crystal 3 Typical 1 FRIIDIW FMICLK 12 Typical 1 M CPUCLK Typical OSC 25 MHz MSTR 96 MHz RCLK 96 MHz HCLK 96 MHz USBCLK PCLK 48 MHz RCLK Divider RCLK 96 0000 MHz HCLK Divider HCLK 96 0000 MHz 1 v fi Y PCLK Divider 2 PCLK 48 0000MHz fi v FMICLK Divider FMICLK 96 0000 MHz From the drop down menu for each clock signal select the desired divider value Saving the clock settings It is recommended that you continue to step 3 of this dialog to create a C header file The header file 91x_conf H is automatically created for your project along with Project H file The header file 91x_conf H is used by the STR9 HAL library to initialize clock source and peripheral usage See Figure 16 Clock C header create step 3 Figure 16 Clock C header create step 3 Step 3 Save C header File Specify folder and filename to save the entries in this session to a C header file Select folder and fle Save Click the Save button to save the C header file 4 UM0225 3 Designing with CAPS 3 4 Specifying peripheral and GPIO pin assignment Click the Peripheral Pin Assignment tab to select the peripherals for your design Pin resources are dynamically allocated and de allocated based on peripheral selection Therefore the peripheral selection sequence directly affects pin resource a
19. JTAG ISP attributes dialog Figure 33 JTAG ISP attributes dialog x JTAG SP Attributes FJTAG ISP Attributes Device Name STR912Fw44x6 Instruction Register Length 17 r Description Name of the device 3 Save or retrieve JTAG ISP setup To save the JTAG ISP settings entered in the preceding steps click the Save button Use the browser dialog to enter the file name and directory location This saves a JTAG Chain File with extension jcf Later you may use the Browse button to open the file to restore your current settings 4 Additional functions If this is the first time programming the device click the HW Setup button to set the target device to a known state by select and validate the communication link This operation is discussed in detail in section 3 7 4 Target hardware verification Click the Checksum button to generate NVM checksums This operation is discussed in detail in section 3 7 2 Checksum the programming file Click the ATE file button to generate ATE files This operation is discussed in detail in section 3 7 3 Generate ATE file Click Reset Target to reset the target device Click Assert Reset to hold the reset signal low This toggle option provides a way to hold the reset signal low at the user s discretion When the option is selected the reset signal is continuously asserted Click De Assert Reset to release the reset signal 3 7 1 JTAG ISP operations The
20. Out Master Master Master Master UARTO TxD UARTO RxD 9 1200 bus 4 1200 bus 9 1200 bus 4 1200 bus Clock In Data Out Clock Out Data In Timer 0 Compare PWM A Timer 0 Capture B 3 UM0225 3 Designing with CAPS Appendix C HAL library C header file example This is an example of the HAL library C header file 91x_conf h ERM Copyright C 2005 2006 STMicro lectronics Ina 3133311 Header file generated by CAPS Version x xx Alpha 4 20 2006 11 52 28 Project Name new912_128 Project Folder C CAPS Projects new912_128 Project Description This is an example Target Device STR912FW44X6 A I A AA IIA I k kkk k k k k k k k A k Fe IR k ifndef _ new912_128_h define __new912_128_h id Device name
21. Project Name or enter a new name for your project After a new directory and project name are entered click Open Note A project is saved to disk only after choosing one of the Save project menu options A valid project name Can have a maximum number of 45 characters Must begin with an alphanumeric character an underscore _ or a tilde Names are not case sensitive Cannot include symbols or punctuation marks 5 For new projects a target device must also be specified Using the device list tree in the Target Devices dialog expand the tree until your target device appears then click on the device icon A description of the device appears in the Device Overview window to the right and the name of the datasheet associated with the device appears in the Target Devices line above the device selection tree Available devices include all devices currently supported by CAPS software Figure 6 Target device selection example shows an example in which the 128 pin STR912FW44 device is selected Figure 6 Target device selection example Target Devices Datasheet STR512FW44X6 E 51859 Family Device Overview H STRSIXF gt 96MHz ARN9E Microcontroller les 5TR910FM32 Dual Burst Flash Memories 512 KB Main Flash Memory and 32 KB Secondary Flash Memory H E STR310Fw32 KE SRAM 52 32 Bytes OTP Memory 9 Programmable DMA channels 5TR911FM44 Clock Reset and Supply Managem
22. Settin Ashes Note If you want 5 1891 to provide clock to the external Ethernet PHY interface device OSC frequency should be 25 MHz Otherwise a separate clock is needed for the PHY PLL carn be 6 et ock frequency used bv the CPU and various penpherals m Program Device E E Enter the desired PLL clock frequency na MHZ Note 1 you plan to us B 1 clack should be either 46 MHz or 96 MHz unless yau provide an external U Click here to validate and refresh clock calculation gt Refresh For Help press F1 Project new Device STR912FW44 03 24 200 7 The frequency must be in the range from 4 to 25 MHZ Note If the STR91x provides clock to the external Ethernet PHY interface device the frequency must be 25 MHz Otherwise a separate clock is needed for the PHY The PLL can be used to generate the desired master clock frequency used by the CPU and various peripherals Note 1 The maximum master clock output is 96 MHz 2 When using USB the master clock frequency should be either 48 MHz or 96 MHz unless an external USB clock is provided Selecting the PLL clock requires you to enter the external crystal frequency and the PLL frequency as shown in Figure 13 PLL clocks selection step 1 3 20 56 3 Designing with CAPS UM0225 21 56 Figure 13 PLL clocks selection step 1 LYD Voltage Clocks Peripheral Pin Assignment Pin Summary Step 1 Specify Clock Source an
23. and Software FAQs Forums Web Sites Displays links to obtain technical information about ST Microelectronics microcontroller products and to report questions or issues regarding CAPS A link to Frequently Asked Questions FAQs is also provided See Figure 5 Help menu for a list of the links provided About CAPS Displays CAPS software version copyright contact and licensing information 2 3 Starting a project Every CAPS session begins by opening a project You may either create a new project or open an existing project This section describes the basic steps common to all projects 2 3 1 Creating a new project Follow these steps to create a new project 1 Use either the New icon in the toolbar or the Project New Project menu item Figure 2 Project menu to create a new project 2 Enter an optional project description in the Description text box 3 Inthe Create Project dialog use the Browse button to specify the name of your project and directory where the project files are to be created The default project name is new upj and the default directory is c CAPS Projects new The project name is the same as the directory name 4 To accept the default project name and directory click Open in the file browser dialog To choose another directory use the file browser to navigate to the desired directory Then 3 12 56 2 Introduction to the CAPS user interface UM0225 either use the default
24. error messages e Explicit design flow sequencing that models the actual design process e Detailed directions on most forms that describe input field formats and how to use the form 2 2 1 The project menu The project menu allows users to manage the project life cycle set project preferences and exit the CAPS program This section describes the operations available in the project menu 3 8 56 2 Introduction to the CAPS user interface UM0225 Figure 2 Project menu fal CAPS new upj Pin Summary Project Tools View Help New Project Open Project Close Project Save Project Save As Project Ghange Target Device Delete Project Import PSDsoft Project Recent Projects Preference About Exit CAPS New Project Creates a new project Open Project Opens an existing project Close Project Closes the currently active project Other projects previously opened within the same CAPS session remain open Save Project Saves the currently active project Save as Project Saves the currently active project to a different file name Follow these steps in the displayed dialog box 1 Enter the new project name see 2 3 1 Creating a new project for project name constraints 2 Optionally enter or modify the project description 3 Click the Save button Change Target Device Selects another target device ONLY within the same product fam
25. following steps provide complete JTAG ISP programming functionality 3 36 56 3 Designing with CAPS UM0225 37 56 Blank Test Erase Program Verify Program Only Verify Upload ByPass All Main Flash 2nd Flash User Code Configuration Use the Select operation drop down menu to choose from the following programming Determine if any region of the device has been programmed Erase one or more regions of the device Write code configuration or data to the device based on the contents of the programming data obj file Following programming compare the actual contents of the device with the contents of the current programming data ob file Write code configuration or data to the device based on the contents of the programming data obj file Compare the actual contents of the device with the contents of the current programming data obj file Read the contents of the device and save the contents to a programming data obj file Place the device in bypass mode This option has limited use in single device view mode other than to verify that the JTAG interface works correctly Use the Select region checkbox to select the device memory region for the programming The entire device The main flash region only The secondary flash region only The user code region only Configuration data region only UM0225 3 Designing with CAPS OTP One time progr
26. is provided to produce a C header file to be included in your source code The following subsections discuss the clock configuration options in more detail Selecting the clock source and frequency There are three clock source options available e Main oscillator input clock OSC e PLL clock e RTC clock Which clock source is selected affects which other clock configuration options are available Clicking the radio button associated with the desired clock source automatically displays the configurable parameters as describe below Typical system values are displayed as default values in the following dialogs ky UM0225 3 Designing with CAPS Selecting the Main Oscillator input clock 4 to 25 MHz external crystal requires you to enter the external crystal frequency as shown in Figure 12 Main oscillator clocks selection step 1 Figure 12 Main oscillator clocks selection step 1 CAPS new upj Clocks Project Tools View Help 5 819 5 2811 5 olx LVD Yoltage Clocks Peripheral Pin Assignment Pin Summary Manage Step 1 Specify Clock Source and Master Clock Frequency Project The master clack MSTR in the Clock Control Unit CCU is derived from one of three clock input sources Select clock source to the CCU C PLL clock C RTC clock 32 768 KHz extemal crystal The source for the OSC is a 4 to 25 MHz extemal crystal connected to STRSTsF Additional Enter your OSC frequency 25 MHz
27. type CAPS Files upi Cancel L 7 Note You may edit the project description however notice that the target device may not be changed 3 14 56 3 Designing with CAPS UM0225 3 Designing with CAPS This section provides a detailed description of how to use CAPS features including e The design flow model that guides you through the design process Firmware placement e Specifying peripheral and GPIO pin function assignment e Setting security Setting JTAG ISP parameters e Setting sector protection e Validating and programming the target device From the window used to create a new project click the Create button to begin designing a project as shown in Figure 8 Create a project dialog Figure 8 Create a project dialog Target Devices Datasheet STR912FW44X6 E 5TR3Famy Device Overview Eh 2 STRSIXF 96MHz ARM9E Microcontroller f 5TR910FM32 Dual Burst Flash Memories 512 KB Main Flash Memory and 32 KB Secondary Flash Memory H E 5TR310Fw32 2 96 KBSRAM E STR911FM42 32 Bytes OTP Memory 9 Programmable DMA channels STRSTIFM44 Clock Reset and Supply Management fo STR912Fw42 Vector Interrupt Controller VIC A D Converter 8 Channets 10 bit resolution 22 STR312Fw44 Communication Interfaces 10 100 Ethernet MAC with DMA and MII port lt 4 USB 2 0 Full Speed 12 Mbps SVEST CAN interface 2 08 Active 3UARTs 2 fast 12C Master Slave bus controller
28. 0 fine GPIO_DIR6 0x0 fine GPIO_DIR7 0x0 fine GPIO_DIR8 0x0 fine GPIO_DIR9 0x0 GPIO fine _GPIO fine _GPIOO fine _GPIO1 fine _GPIO2 fine _GPIO3 fine _GPIO4 define _GPIO5 fine _GPIO6 define _GPIO7 define _GPIO8 define _GPIO9 ADC KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK 3 3 3 KKK fine _ADC ADC enabled At least one of ADC channels is used fine GPIO_ANAChannel4 0x10 ADC Channel 4 is selected fine GPIO_ANAChannel5 0x20 ADC Channel 5 is selected
29. 626606 66 Revision history 4 ky 2 56 1 Getting started UM0225 1 1 Note Caution 3 56 Getting started Before using CAPS install the software on your PC Connect your target device if you plan to program the device This section discusses the following topics needed to begin using the CAPS software e CAPS software installation Setting up the target hardware e The recommended approach to using this manual Complementary documentation considered to be useful when using the CAPS software Installation This section describes the requirements and procedures needed to install the CAPS software System requirements The CAPS PC configuration minimally requires e PC with an Intel Pentium processor running a 32 bit Microsoft operating system Microsoft Windows XP Windows 2000 Windows 8 Windows ME Windows NT with Service Pack 6 e 32 MB RAM 25 MB hard disk space available To use RLINK ST a USB port is required with a USB supporting Windows operating system e g Win98SE Win2000 Me and XP Note that Win95 Win98 First Edition and NT4 0 do NOT support USB FlashLINK Cable JTD driver OD is NOT supported on dual processor systems or hyper threading enabled systems Refer to Appendix D FlashLINK Cable Install fast JTAG driver for workaround options for both dual processor and hyperthreading systems Installing CAPS Follow these procedures and the on screen instru
30. Failed to detect all IDCODEs Invalid port selected Check also FlashLINK connection and parallel port operability 3 7 5 Chaining multiple devices This section describes procedures for specifying chained devices and their order Refer to the other subsections of 3 7 Validating and programming the target device for operations common to both single and multiple devices If Multiple device view is selected the program displays Figure 43 Programming dialog for multiple devices when the Program Device button is clicked The multiple device view adds dialog for chaining devices to the single device dialog 3 42 56 3 Designing with CAPS UM0225 Click the Library button to add non ST devices to the chain Figure 43 Programming dialog for multiple devices fal CAPS new upj JTAG Project Tools View Help 05 2 5 1 7 x Step 1 Define each device in JTAG ISP chain Select folder and programming file Select device C ACAPS Projects new new obj f 7 STR912FW44X6 Select region Select operation All Program Only X IV Main Flash IV 2nd Flash IV User Code Properties IV Configuration 5 oTP Library Additional Settings Step 2 Build JTAG ISP chain Add devices from step 1 to the JTAG ISP chain Update highlighted device from step 1 Or you can also delete and move devices Devce Operation Region Usercode 1 STR912F new 0bj H Program Only Main Fla
31. INK Cable fast JTAG driver JTD 1 Locate the Drivers FLink folder under your CAPS folder 2 At command prompt a To install the JTD driver gt gt JTDINSTALL b To uninstall the JTD driver gt gt JTDCFGW uninstall 3 You must reboot the system after installing or uninstalling the driver To achieve better programming performance in conjunction with the JTD driver we recommend that you use the PCI parallel port card from SIIG Cyber Parallel PCI Single Parallel Port Workaround solutions There are two workaround options for dual processor systems which are described below 1 Boot into single processor mode and use the fast JTD driver 2 Use the standard Parallel Port driver PEP There are two workaround options for systems with hyper thread enabled which are described below 1 Disable hyper thread and use the fast JTD driver 2 Leave hyper thread as enabled and use the standard parallel port driver PEP From JTAG ISP standpoint the tradeoff between the two solutions is the programming performance Dual processor System using solution 1 1 Boot your system in single processor mode and install JTD driver If you have not already installed the JTD driver go to the CAPS subfolder Drivers Flink and invoke JTDINSTALL BAT 2 Reboot your system Dual processor System using solution 2 Follow the steps below to uninstall the JTD driver and install the PEP driver 52 56 3 Designing with CAPS UM0225
32. Reset Signal _ r Description C Generate SVF File Generates JAM STAPL language file with all JTAG 6 Generate JAM STAPL File sna Hos ada erase program verify rates EI This option generates adaptive algorithm using the four M Assert Reset standard JTAG pins TCK TMS TDI TDO Reset Name RESET Reset Active State 1 Programming Options IV Blank Check IV Erase The description frame on the right of the dialog provides a context sensitive help for the various selection options 1 Click the OK button to accept the specified file format A browser dialog window appears allowing you to enter the file name and directory location to save the file 2 Click the Save button The file is saved to disk and Successful ATE file creation displays in the output log 3 7 4 Target hardware verification Use the programming dialog to perform the following functions Set the target hardware to an initial state Specify the type of communication link e Perform loopback tests on the link and validate target board connectivity e List the IDCODEs of all devices in the JTAG chain Click the HW Setup button to display the hardware setup dialog shown in Figure 36 Hardware setup dialog Note 1 The target device and communication links must first be connected and powered as described in 1 2 Setting up the target hardware 2 It is recommended that you reset the target device before pe
33. adio button associated with the function then click OK Create a new project Select this option to create a new project for your design Open an existing project Select this option to open a project that you have previously created 3 16 56 3 Designing with CAPS UM0225 17 56 Save current opened project to a different name Delete an existing project Close current opened project Design entry forms Select this option to rename the current project The project with the new name becomes the currently active project Select this option to delete a project and all of its associated files Select this option to close the currently active project Use one or more of the design entry forms for CAPS design These forms are accessed by clicking the Design Entry button then selecting the appropriate tab LVD Voltage Clocks Peripheral Pin Assignment Pin Summary Additional settings form Use this form to choose the desired voltage specification option See Specifying the LVD voltage for a detailed discussion on using this feature Use this form to choose the desired clock source option See Specifying the clock source and frequency for a detailed discussion on using this feature Use this form to select the desired peripheral for your design and its pin function assignment See Specifying peripheral and GPIO pin assignment for a detailed discussion on using this feature Use this form to graphica
34. ammable region only Click the Properties button to view the JTAG ISP Attributes This shows the device name and its instruction register length This information may be useful to setup the JTAG chain for 3 party programming tools that do not have an auto detect function Click the Execute button to perform the programming operation selected above If you attempt to program a device that is not blank a warning message verifies that you want to do the full chip erase before continuing Click Yes to continue 3 7 2 Checksum the programming file Click the File Checksum button to generate checksums for the current programming file The following checksums are generated Main flash Secondary flash User code Configuration data area including OTP memory The entire file The output log if enabled shows the results of the operation as shown in Figure 34 Checksum file output log Figure 34 Checksum file output log Start generating checksum Device 1 STR912FW44X6 Filename new4 obj Main Flash 7F80000 2nd Flash 7F8000 User Code 3FC Configuration Cc Total 8778408 successful checksum generation 3 7 3 Generate ATE file For STR9 devices the Serial Vector Format SVF or JEDEC Standard Programming Language STAPL format file is not supported The ATE Files feature should not be used 3 38 56 3 Designing with CAPS UM0225 Figure 35 Create ATE File dialog r Language and
35. ble peripheral s Embedded Trace Interface External DMA Request External Interrupt Request External Memory Interface GPIO 2110 201 Assignable Unassignabie Step 2 Save C header file Step 1 Select the peripheral from the List of available peripheral s box for GPIO pins assignment of assigned peripherals Ethernet MII Interface Peripheral Assignment Timer x Select the desired timer counter clock Internal timer clock External timer clock Select the desired timer counter mode as IV Input Capture A Input Capture B IV Pulse Width Modulation I Output Compare A F Output Compare B Specify folder and filename to save t Select folder and file PinAssionment Cancel This example specifies the nternal timer clock default as the clock source and nput Capture A and Pulse Width Modulation as the desired counter timer modes Click Pin Assignment to select the pin assignments for the peripheral function The program displays the dialog shown in Figure 21 Figure 21 Peripheral pin assignment Pin Assignment Timer1 x Assign the desired pin for its respective function Note The Apply button assigns the pin to its function and locks all pin assignment Timer 1 Capture A p42 C p62 automatically r Timer 1 Compare PWM A p31 amp o C p42 C p62 3 26
36. cation if any one bit of the byte location was previously written Check the OTP Bit Lock checkbox to disable writes to OTP memory Validating and programming the target device After completing the design of your project you are ready to program the firmware into your target device Before programming the device perform the following steps 1 Set your default programming to use either Single device view or Multiple device view using the Project Preferences menu selection shown in Figure 30 Project preferences dialog Figure 30 Project preferences dialog xi JTAGAISP Single device view C Multiple device view Use single device view if there is only one device on your board Use multiple device view if multiple devices are daisy chained Click the radio button corresponding to the desired view A JTAG chain is defined to be two or more JTAG compliant IEEE 1149 1 standard devices connected together in a chain Each device in the chain must support the four basic JTAG signals TDI TDO TCK and TMS The following JTAG chaining rules apply Different brands of chips must be set in ByPass operation and will require different programming software ky UM0225 3 Designing with CAPS Only one device in a chain will be programmed at a time not concurrently Before any JTAG operation can begin the chain order must be defined and the instruction register length for each device must be known by t
37. click the Select region checkbox for the desired region Multiple regions including All may be checked Click the Update button to apply the change Note Different regions can be specified for each device 5 Once the JTAG chain and device properties are defined click the Execute button to perform the selected programming operation 43 56 Ky UM0225 3 Designing with CAPS Appendix A Intel hex 32 record format A 1 The Intel 32 bit hexadecimal file record format has a 9 character 4 field prefix that defines the start of the record byte count load address record type and a 2 character checksum suffix The hex file Figure 44 illustrates the sample records of this format Figure 44 Intel 32 bit hexadecimal file format Start Character Add eS Offset Address i 20000020000FC 1 Extended Segment Address Record 222101 At Extended Linear Address Record 10000000FFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFO00C 10001000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0 AN 10002000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEO Records 10003000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD0 10004000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCO 00000001FF End of File Record L Checksum Checksum LEGEND Record Type B Nonprinting Carriage Return with optional line Byte Count feed and nulls determined by null count Four record types are defined e Data record e End record e Extended se
38. ctions to install CAPS 1 Download the compressed CAPS software from the website 2 Extract the contents of the zip file into a temporary directory 3 Double click the extracted executable setup exe to initiate the installation and follow the on screen prompts to install CAPS in the development environment This executable installs all the necessary files and configures the PC environment for running CAPS You may be prompted to restart your PC before running CAPS for the first time following the installation CAPS installation includes a number of utilities Documentation for the utilities is located in the subdirectory Docs where CAPS is installed ky UM0225 1 Getting started Table 1 CAPS utility programs Utility Executable Description ObjFileEditor exe Programming data file OBJ editor uFLink exe Standalone JTAG ISP programming utility uMerge exe Merge firmware utility uObjOsf exe Program data file conversion utility Convert obj to osf and osf to obj files Subdirectory Projects is also created and is the default location for storing your CAPS project files For example if CAPS is installed in base directory C CAPS the Projects directory is located at C CAPS Projects 1 1 3 Uninstalling CAPS To uninstall CAPS select Start Programs STMicroelectronics CAPS Uninstall CAPS This removes all CAPS executable software and desktop references Note Any project files and environment
39. d Master Clock Frequency The master clock MSTA in the Clock Control Unit CCU is derived from one of three clock input sources Select clock source to the CCU Main Oscillator input clock OSC 4 to 25 MHz external crystal PLL clock RTC clock 32 768 KHz extemal crystal The source for the OSC is a 4 to 25 MHz external crystal connected to STR91xF Enter your OSC frequency 25 MHz Note If you want 51 891 to provide clock to the external Ethernet PHY interface device OSC frequency should be 25 MHz Otherwise a separate clock is needed for the PHY PLL can be used to generate the desired master clock frequency used by the CPU and various peripherals Maximum master clock output is 96 MHz Enter the desired PLL clock frequency as MHz Note If you plan to use USB master clock should be either 48 MHz or 96 MHz unless you provide an external USB clock Click here to validate and refresh clock calculation gt gt Enter the external crystal frequency between 4 and 25 MHz and with the same constraints as described above Enter the PLL frequency Selecting the RTC clock 32 768 KHz external crystal requires you to enter the external crystal frequency as shown in Figure 14 RTC clocks selection step 1 3 UM0225 3 Designing with CAPS Figure 14 RTC clocks selection step 1 LVD Voltage Clocks Peripheral Pin Assignment Pin Summary Step 1 Specify Clock Source and Master Clock Freq
40. displays useful information corresponding to the current cursor location in any data entry window on the form Click the cursor in a data entry window to see the description for that window After completing all desired Configuration form entries click the Apply button at the bottom of the form to regenerate a new programming data file for the design 3 6 1 Setting security Setting the security bit blocks all access to the content of the device by means of JTAG or a conventional programmer Once the security bit is set reading or copying the configuration or memory contents of the device is disabled In the Security dialog click the Enable security bit checkbox to enable security Uncheck the box do disable security Note The only way to override the security bit is to erase the entire device 3 6 2 Power up boot flash selection This option in the Boot Flash dialog allows you to select the flash from which the CPU boots at power up Click the desired radio button to select either main flash or secondary flash 3 6 3 Setting a JTAG ISP user code This option in the JTAG ISP dialog allows you to enter a 32 bit code which can be used for various functions such as programming contents and revision level identification Enter the JTAG ISP User Code on the Configuration form entering any 32 bit hexadecimal value The default value is FFFFFFFF 3 6 4 Setting sector protection Individual NVM segments within the device may be staticall
41. e to write the current project settings to the saved file If Single device view is selected in the Project Preferences menu the program displays Figure 32 Programming dialog for single device All discussion for the single device dialog also applies to the multiple device dialog The multiple device dialog provides additional chaining options which are discussed in 3 7 5 Chaining multiple devices 3 34 56 3 Designing with CAPS UM0225 Figure 32 Programming dialog for single device al CAPS new up JTAG Project gt Thols View Help 0 2 s Be 5 Step 1 Select programming file and target device Select folder and programming file Select device Manage Project C CAPS Projects new new obj Browse STRO12FW44X6 Step 2 Specify JTAG ISP operation and conditions Select region Select operation All Program Only JV Main Flash lv 2nd Flash JV Merge MCU firmware IV User Code JV Configuration Properties Additional omP Settings Click here to perform specified JTAG ISP operation gt gt Step 3 Save or retrieve JTAG ISP setup Specify folder and filename to save this JTAG ISP session setup or to retrieve a previous session setup Save Program fect Select folder and file Browse File Checksum ATE Files HW Setup Reset Target Assert Reset For Help press F1 Project new Device STR912FW44 06 20 2006 11 48 25
42. e A UM0225 3 Designing with CAPS Note 3 Because of STR91x pin dependencies some peripherals may become unavailable for assignment as pins are assigned CAPS dynamically makes the necessary pin assignments and reassignments Peripherals no longer available for assignment due to GPIO resource limitations are highlighted in red As a design aid during pin assignment you may always choose the Pin Summary tab to graphically show the current pin assignments See Figure 26 Pin Summary tab The header file 91x_conf H is automatically created for your project This default header file is used by the STR9 HAL library to initialize clock source and peripheral usage You may optionally continue to step 2 of the dialog to create a C header file It is recommended that you create the separate C header file to be included in your source code to reference the pins and their respective functions See Figure 24 C header file create dialog Figure 24 C header file create dialog Step 2 Save C header file Specify folder and filename to save the entries in this session to a C header file Select folder and file Save Click the Save button to save the C header file To address incremental design and PCB constraints there are two options for fixing pin assignment e Lock pin feature e Selective pin function assignment The lock pin feature gives the user the option to fix a set of assi
43. ed 54 56 4 Revision history UM0225 4 55 56 Revision history Date 22 May 2006 9 Aug 2006 Revision 1 Changes Initial release New note added Section 1 2 on page 4 Notes modified Section 1 2 Setting up the target hardware New text added Section 3 7 3 on page 38 UM0169 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intel
44. ended linear address offset for the data record 0010 in the example 2 Find the extended segment address offset for the data record 1230 in the example 3 Find the address offset for the data from the data record 0045 in the example 4 Calculate the absolute address for the first byte of the data record as follows 00100000 Linear address offset shifted left 16 bits 12300 Segment address offset shifted left 4 bits 0045 Address offset from data record 00112345 32 bit address for first data byte The address for the first data byte is 112345 Always specify the address offset when using this format even when the offset is zero During output translation the firmware forces the record size to 16 decimal if the record size is specified greater than 16 There is no such limitation for record sizes specified less than 16 Extended linear address record This record specifies bits 16 31 of the destination address for the data records that follow This address is added to the offset to determine the absolute destination address and can appear anywhere within the file The address field for this record must contain ASCII zeros hexadecimal 30s UM0225 3 Designing with CAPS Appendix B Project Report 3 This is an example of a project report The report includes e CAPS version project name location description and target device Design entry settings and configuration specifications Peripheral pin assig
45. ent El STR912Fw42 Vector interrupt Controler VIC h A D Converter 8 Channels 10 bit resolution STR912PW44 Communication Interfaces H 128 Pin TQFP 10 100 Ethernet MAC with DMA and MII port USB 2 0 Full Speed 12 Mbps EE E UPSD Family CAN interface 2 08 Active 3UARTs 2 fast 12C Master Slave bus controller 2 channels for SPI SSI or Microwire 8 16 bit External Memory Interface EMI 4 standard 16 bit Standard Timers TIM 3 Phase Induction Motor Controller IMC JTAG Interface with Boundary Scan Embedded Trace Module ETM Reat Time Clock Flexible Power Management Create Cancel For Help press F1 Project N A Device N A 03 24 2006 23 06 27 2 3 2 Opening an existing project Follow these steps to open an existing project 1 Use either the Open icon in the toolbar or the Project Open Project menu item Figure 2 Project menu to open an existing project 2 Inthe Open Project dialog use the Browse button to use the file browser to locate the directory where your existing project file resides The dialog displays the project file names with extension upj as shown in Figure 7 Open an existing project example Click on the desired file name then click Open to open the file to display your previously saved project 13 56 54 UM0225 2 Introduction to the CAPS user interface Figure 7 Open an existing project example File name fhew upj Files of
46. est fails the error message shown in Figure 39 Target connectivity test dialog displays Figure 40 Target connect test error dialog Target Connect Test Status xi Target connect test failed Invalid port selected Check also FlashLINK connection and parallel port operability 3 41 56 UM0225 3 Designing with CAPS Check the JTAG chain connectivity on the target board and that the target board is powered on Click OK to continue 5 Click Determine TCK Speed button to determine the maximum attainable TCK rate in KHz 6 Click Detect IDCODEs to display the IDCODEs of CAPS supported devices in the JTAG chain For unsupported devices the string Non ST device is displayed If the detection passes the detected IDCODEs are listed in the dialog shown in Figure 41 Detected JTAG IDCODEs dialog Figure 41 Detected JTAG IDCODEs dialog Hardware Setting Hardware Selection FlashLINK FlashLINK Connect Test Parallel Port Auto Select v Target Connect Test Determine TCK Speed Detect IDCODEs F Always monitor RTCK IDCODE of ST devices in the chain 1 STRS12PW446 1457F041 25966041 04570041 Cancel OK If the detection fails the dialog shown in Figure 42 JIAG IDCODEs detection error dialog displays Check the JTAG chain connectivity on the target board and that the target board is powered on Click OK to continue Figure 42 JTAG IDCODEs detection error dialog Detect All IDCODEs x
47. evice STR912FW44 7 Menu bar Use the menu bar to access these CAPS design functions The project menu The tools menu The view menu and The help menu These functions are described in more detail beginning with 2 2 1 The project menu Toolbar The toolbar provides quick access to common menu bar functions including e Create a new project e Open an existing project e Save a project File editing functions cut copy and paste Help using CAPS 7 56 UM0225 2 Introduction to the CAPS user interface Main window Output log window Note Status bar The main window displays the CAPS design entry forms The window may consist of multiple panes depending on the current design function Figure 1 CAPS user interface shows an example of a typical design window with two panes 1 A navigation pane appears on the left 2 A current work pane appears on the right Some modes of operation may also have function tabs across the top of the work window as shown in Figure 1 The output log window echoes all commands executed by CAPS along with informational and progress messages This window is made visible by checking the Output Log option in the View menu The status bar displays e Current project name e Target device Today s date MM DD YYYY e Current time HH MM SS The CAPS user interface provides the following additional aids to using the software Descriptive pop up
48. files are preserved so they are available following a CAPS software upgrade However it is a safe practice to backup your project files before uninstalling and reinstalling the software 1 2 Setting up the target hardware If you are using CAPS features that interact with the target hardware such as programming the flash configure and power the target hardware before starting a CAPS session Refer to the the User Guide for your particular target hardware found at http www st com mcu Note 1 When using FlashLINk the 20 pin to 14 pin adapter provided with the EVAL Kit or a customer board is required 2 The device under test must be the same as the target device you select when you created your project 3 Follow the instructions below referring to the device specific quick start guide or design guide as needed 1 Connect either the RLINK ST USB cable or the FlashLINK parallel cable to your PC and connect the other end of the JTAG interface to the target board 2 Configure jumpers according to the quick start or design guide documentation for the target board 3 Attach the power plug to the power jack of the target board 4 Switch ON the target board 3 4 56 1 Getting started UM0225 1 3 1 4 5 56 How to use this manual Use these recommendations as a guide to learning the CAPS software Read Getting started to learn what CAPS is and to install the software for the first time Read ntroduc
49. gment address record e Extended linear address record Data record This record begins with the colon start character which is followed by the byte count in hexadecimal notation the address of the first data byte and the record type equal to 00 Following these are the data bytes The checksum follows the data bytes and is the two s complement in binary of the preceding bytes in the record including the byte count address record type and data bytes 44 56 3 Designing with CAPS UM0225 A 2 A 3 Note A 4 45 56 End record This end of file record also begins with the colon start character and is followed by the byte count equal to 00 the address equal to 0000 the record type equal to 01 and the checksum FF Extended segment address record This is added to the offset to determine the absolute destination address The address field for this record must contain ASCII zeros hexadecimal 30s This record type defines Bits 4 to 19 of the segment base address it can appear randomly anywhere within the file and affects the absolute memory address of subsequent data records in the file The following example illustrates how the extended segment address is used to determine a byte address Problem Find the address for the first data byte for the following file 02 0000 04 0010 EA 202 0000 02 1230 BA 10 0045 00 55AA FF BC Solution 1 Find the ext
50. gned pin s for the selected peripheral by preventing CAPS from de allocating those pins during subsequent peripheral selection The benefit of the lock pin feature a toggle feature is to allow the user to lock the optimal pin grouping assigned by CAPS To lock the pin preventing CAPS pin reassignment right click on the desired peripheral in the assigned list and click the Lock Pin pop up button as shown in Figure 25 Figure 25 Lock and unlock pin toggle dialog List of assigned peripheral s Lock Pin The peripheral mnemonic is grayed when the pin is locked This is a toggle operation so use the same mechanism right click and click the Unlock Pin pop up button to unlock the pin The selective pin function assignment option allows advanced users to have full control in selectively assigning the pin functions of the selected peripheral This option prevents the pin function from being re routed fixing the pin for PCB layout 28 56 3 Designing with CAPS UM0225 3 5 View the GPIO pin assignment summary The pin assignment summary dialog displays the current pin assignments as the assignments are made following the steps in Section 3 4 Specifying peripheral and GPIO pin assignment The dialog shows the default and user defined pin assignments which were assigned according to resource availability Click the Pin Summary tab to graphically view the current pin assignments Figure 26 Pin Summary tab shows the Pi
51. guration choices Project m Security Enable security bit Boot Flash Des At power up CPU boot from Main Flash C Secondary Flash Entry FJIAGNSP User Code FFFFFFF Additional Settings Sector Protection Main Flash Secondary Flash Sector0 Sector 4 Sector 0 ogee Sector 1 Sectors Sector 1 Sector2 Sector Sector 2 Sector3 Sector7 Sector 3 r Firmware Placement File Start File End 8 Address HEX Address HEX File Name Main Flash I Browse OTP Setting Note It is recommended that bytes 24 29 be assigned to store Ethernet MAC address OTP Content Byte gt gt 14 13 12 11 10 J 8 amp amp FF Byte gt gt 29 28 27 26 24 23 2 20 FFP i OTP Lock Bit Description Use this field to facilitate your programming contents and revision level identification The setting of the security options will not affect the reading of this information Default FFFFFFFF Project Inew Device STR912FW44 01 29 2006 13 56 32 7 The form provides the interface for the following configuration options e Security Boot Flash e JIAG ISP Sector Protection 31 56 UM0225 3 Designing with CAPS Firmware Placement e OTP Setting These are discussed in detail in the following subsections At the bottom of the form is a Description window This window
52. he software Note The order of the chain is important when programming the devices You must set up the chain in your programming software such that it matches physical ordering of the devices on your board The multiple device view in Project Preferences allows you to build the JTAG ISP chain Next setup and power your target device as described in 1 2 Setting up the target hardware 2 Setup and power your target device as described in 1 2 Setting up the target hardware CAPS setup and the hardware are now ready for programming the device Click the Program Device design flow button to access the device verification and programming dialog CAPS verifies the changes made in the previous design steps were applied by clicking the Apply button before continuing with device programming If the current open project settings differ from the saved data file for the project the dialog shown in Figure 31 Project file synchronization dialog gives the option to synchronize with the saved project file Figure 31 Project file synchronization dialog APS gt Your project settings are more current than the most recent programming data file To update your programming data file click Update button To proceed without updating programming data file click Continue button To cancel the current process click Cancel button Continue Cancel Click Continue or Cancel to proceed without updating the programming data file Click Updat
53. heral bus divisor define _FMICLK_Divisor SCU_FMICLK_Divl FMI divisor GPIO input register setting define GPIOINO 0x0 define GPIOIN1 1 define GPIOIN2 0x0 define GPIOIN3 1 define GPIOIN4 0x4 define 621015 0x0 define GPIOIN6 0x8 define GPIOIN7 0x0 Tf GPIO output register settind KKK KKK KKK KK KKK KKK KKK KKKK KKK KKK KKK KE KK KE KKK KK KKK 9 KKK define GPIOOUTO OxFFFF define 650011 0 define GPIOOUT2 0x0 define GPIOOUT3 0x30C define GPIOOUT4 0x80 define 62100015 0 define GPIOOUT6 0x0 define GPIOOUT7 0x0 J
54. ifying peripheral and GPIO pin assignment 24 3 5 View the GPIO pin assignment summary i 29 3 6 Configuring optional device parameters 0 31 3 6 1 Setting security 0 0 a E a 32 3 6 2 Power up boot flash selection i 32 UM0169 3 6 3 Setting a JTAG ISP user code 0 32 3 6 4 Setting sector protection 9 32 3 6 5 Firmware placement 00 eee eee ae 32 3 6 6 Setting OTP programmable memory bytes 0 000 cence eee 32 3 7 Validating and programming the target device 00005 33 3 7 1 JTAG ISP operations os serada deaud tee eee 36 3 7 2 Checksum the programming file i 38 3 7 3 Generate ATE file i 38 3 7 4 Target hardware verification i 39 3 7 5 Chaining multiple devices i 42 Appendix A Intel hex 32 record format 44 A 1 Data reCOrd AR 44 A 2 End TOCOIG ye tos dich s e Ee ea Hae ete Ce Ge 45 A 3 Extended segment address record i 45 A 4 Extended linear address record 00000 Ra 45 Appendix B Project Report 000 cece ce Gee dace eens 46 Appendix C HAL library C header file example 48 Appendix D FlashLINK Cable Install fast JTAG driver 52 D 1 Driver installation 2 52 D 2 Workaround solutioNnS 52 55 666626262
55. ily from the expandable device tree list Changing the package type may invalidate the pin function re assignment done in the Peripheral Pin Assignment window Delete Project Deletes a project and all files associated with the project 9 56 54 UM0225 2 Introduction to the CAPS user interface Import PSDsoft Project Imports an existing project created using the PSDsoft tool Note This option is only applicable to uPSD projects Recent Projects Lists the most recently opened projects A project may be opened by double clicking on a list entry Preference Sets the CAPS design environment Select either Single device view or Multiple Device view for the JTAG ISP property Single and multiple device operations are discussed in 3 7 Validating and programming the target device About Displays details about a project e Project name e Project folder e Device family Part number e Voltage e Project description Note The project must already be open Exit CAPS Exit the CAPS program 2 2 2 The tools menu The tools menu provides the ability to produce a project report Figure 3 Tools menu he CAPS new upj Pin Summary Project Tools View Help D E Generate Project Report i oxi LYD Voltage Project Generate Project Report Produces a text file report of your design The result shows detailed peripheral and pin function assignments See P
56. l JTD driver 1 If you have not already intalled JTD driver go to CAPS subfolder Drivers Flink and invoke JTDINSTALL BAT 2 Reboot your system Hyper thread enabled system using solution 2 Use the following steps to leave hyper thread enabled and use the standard parallel port driver PEP Uninstall the JTD driver and install the PEP driver 1 To uninstall the JTD enter the following at the command line prompt gt gt JTDCFGW uninstall If you are unable to boot into Windows a press and hold F8 immediately during boot up b Select Safe Mode to skip loading the JTD driver On systems that continue loading JTD driver boot into Safe Mode with command prompt Rename JTD sys and JTDMSG dll in the WINDOWS system32 drivers folder to prevent loading the JTD driver upon bootup ky UM0225 3 Designing with CAPS 3 c Reboot into Normal mode and restore the above two file names before executing JTDCFGW uninstall If you have not already installed the PEP driver go to the CAPS subfolder Drivers Needhams and invoke INSTALL BAT lf INSTALL BAT does not exist then enter the following commands at the command prompt gt gt Run regpep gt gt Copy pepnt sys windir S system32 drivers Go to the CAPS folder and update uPSDsoft NI as follows JTAG Driver PEP lt lt lt this is to indicate PEP driver is used OD indicates JTD driver is used Reboot your system with hyper thread enabl
57. lectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the p
58. lly display the results of your Peripheral Pin Assignment operations Optional configuration choices are available by clicking on the design flow Additional Settings button then clicking the Configuration tab UM0225 3 Designing with CAPS 3 2 Note 1 3 Configuration Use this form for additional design settings including setting security selecting the power up boot flash specifying a user code setting the internal memory sector protection specifying OTP memory programming and your firmware placement information Program device form Click the Program Device design flow button to program your design into the target device Options are also available to calculate the file checksum generate an SVF or JAM file and validate the target device See Validating and programming the target device for a detailed description on using this feature Specifying the LVD voltage Click the LVD Voltage tab to select the LVD threshold voltage The STR91x requires separate operating voltage supplies The CPU and memory operate from at 1 65 to 2 0 volts on the VDD pins and the I O ring operates at 2 7 to 3 6 volts on the VDDQ pins Choose 2 4 volts LVD threshold voltage to go with a VDDQ of 2 7 to 3 3 volts Choose 2 7 volts LVD threshold voltage to go with a VDDQ of 3 0 to 3 6 volts If you to use USB VDDQ of 3 3 volts is required to meet USB specifications Select the 2 7 volt LVD threshold voltage The dialog shown i
59. n 2 OEE Sector Protection Main Flash Protection Status Sector 0 protected Sector 1 unprotected Sector 2 unprotected Sector 3 unprotected Sector 4 unprotected Sector 5 unprotected 46 56 3 Designing with CAPS UM0225 47 56 Sector 6 Sector 7 2nd Flash Sector 0 Sector 1 Sector 2 Sector 3 Firmware Setting Main Flash start addre Main Flash end address File path for Main Flash OTP Setting OTP Content Byte gt gt 14 13 12 Data gt gt FF FF FF Byte gt gt 29 28 27 Data gt gt FF FF FF OTP lock bit oft ss protected protected Protection Status protected protected unprotected unprotected 0 SFFF C uPSDsoft Projects Example MyCode hex TL 10 8 8 7 6 5 FF FF FF FF FF FF FF 26 25 24 23 22 21 20 FF FF FF FF FF FF FF FF 19 FF FF 18 FF FF 17 FF FF 16 FF FF 15 FF Peripheral Pin Pi Name Name Nu GPIO pet 47 External DMA Request p3_0 55 Embedded Trace Interface poe 67 01 69 p0_2 71 03 76 po_4 78 p0_5 85 206 88 OR 90 plo 98 pis 11 SSP0 p2_4 37 p2_5 45 p2_6 53 p2_7 54 UARTO p5_0 12 p5_1 18 I2C0 pl_4 10 pl_6 Ti 14 10 21 6 1i Timer0 p4_0 3 p4_1 2 n Pin mber Function GP I O mode Output Push Pull External DMA Request 0 Packet Packet Packet Packet 3 Pipe Stat 0 Pipe Stat 1 Pipe Stat 2 Trace Sync By External Trigger 0 ETM Trace Clock Clock Out Data Out Data In Select
60. n Figure 11 LVD Voltage tab is used to select the desired LVD threshold voltage 18 56 3 Designing with CAPS UM0225 3 3 Note 3 3 1 Note 19 56 Figure 11 LVD Voltage tab CAPS new upj LVD Voltage Project Tools View Help 5 s alee aixi LYD Voltage Clocks Peripheral Pin Assignment Pin Summary Manage Step 1 Specify Voltage Project The 518912 requires two separate operating voltage supplies The CPU and memories operate from a 1 65 to 2 0 on the YDD pins and the 1 0 ting operates at 2 7 to 3 6 on the VDDQ pins Specify the YDDQ LYD threshold voltage Ci Recommendations Choose 2 LYD threshold voltage to go with VDDD of 2 7 to 3 3 Choose 2 7 LYD threshold voltage to go with YDDA of 3 0 to 3 6V Additional Note If you intend to use USB VDDQ of 3 3 is required in order to meet USB specifications Settings You should select 2 7 LVD threshold voltage Apply Program Device For Help press F1 Project jnew Device ISTRO12FW44 a Click either the 2 4V or 2 7V LVD threshold radio button as applicable Specifying the clock source and frequency Click the Clocks tab for the following clocking options e Specify the clock source and master clock frequency Specify the clock divisors e Save clock settings in a C header file The clock settings affect the Hardware Abstraction Layer HAL library so the capability
61. n Summary dialog Figure 26 Pin Summary tab CAPS new upj Pin Summary Project Tools View Help se 2 olxl LYD Voltage Clocks Peripheral Pin Assignment Pin Summary Manage Project Additional Settings 4 Program Device sieve pn For Help press F1 Project jnew Device STRO12FW44 03 27 2006 17 04 45 7 Use the horizontal and vertical scroll bars to view pins outside the display window Mnemonic pin names are shown for pins assigned in the Peripheral Pin Assignment step Pins are color coded according to the following legend Color Description Red Voltage VCC VDD Dark blue Ground GND Light blue Reserved should not be used Light brown Locked cannot be assigned or unassigned Light cyan Available pin pin is available for assignment Dark cyan Assigned pin pin is used but can be unassigned 29 56 UM0225 3 Designing with CAPS Figure 27 Pin summary with unassigned pins voda p05 p65 p64 lt a a E 3 BERERERSQREEEEEES 30 56 3 Designing with CAPS UM0225 3 6 Configuring optional device parameters Click the Additional Settings button to use the Configuration form See Figure 29 Additional Settings button Figure 29 Additional Settings button CAPS new upj Configuration Project Tools View Help 85 2 0 Dixi Configuration Manage Optional confi
62. nfigurable peripheral parameters Enter the desired information and values to configure the peripheral For peripherals that have predefined pin assignments the following prompt is displayed to either accept the default assignment or enter a different pin assignment Figure 18 Accept default pin assignment prompt I2C0 9 Doyou wish to assign the pin function of your selected peripheral We J Default Pin assignment is dynamically allocated based on pin resource availability Yes No 3 24 56 3 Designing with CAPS UM0225 Click Yes to define new pin assignments Click No to accept the default pin assignments for the peripheral The following is a peripheral configuration example using the Timer1 peripheral Figure 19 Example assign Timer1 peripheral m Step 1 Select the peripheral from the List of available peripheral s box for GPIO pins assignment List of available peripheralts List of assigned peripheral s External Interrupt Request External Memory Interface Assignable Unassignable To select the Timer peripheral left click Timer1 in the list of available peripherals then click the Assign gt gt button For configurable peripherals such as Timer1 a dialog window appears with the configuration options as shown in Figure 20 3 25 56 UM0225 3 Designing with CAPS Figure 20 Example configure Timer1 peripheral List of availa
63. nment Sample report Project file generated by CAPS Version x xx 3 20 2006 15 32 08 Project Name Example Project Folder C uPSDsoft Projects Example Project Description This is an example Target Device STR912FW44X6 VDDQ LVD threshold voltage 2 7 7 LVD reset option VDD or VDDQ LVD warning option VDD or VDDQ Clocks Master clock source PLL Main crystal frequency 25000000 00 Hz Master clock frequency 96000000 00 Hz M value of PLL 3425 N value of PLL 192 P value of PLL 2 RCIK divisor value 4 5011 frequency gt 24000000 00 Hz HClk divisor value 76 HClk frequency amp 24000000 00 Hz PClk divisor value 2 PClk frequency 12000000 00 Hz FMI divisor value ged FMI CLK frequency 24000000 00 Hz At power up CPU boot from Main Flash JTAG user code 24689ADC Device Security Protectio
64. rforming these operations by clicking the Reset Target button 4 39 56 UM0225 3 Designing with CAPS Figure 36 Hardware setup dialog Hardware Setting S x Hardware Selection FashuNK FlashLINK Connect Test Parallel Port Auto Select Target Connect Test Determine TCK Speed Detect IDCODEs Always monitor RTCK LPT1 TCK rate 236 KHz Cancel 1 Use the drop down menu to choose the type of communication link RLink or FlashLINK connected between the PC and target board RLink Communication using a USB port FlashLINK Communication using a parallel port If FlashLINK is selected also click Parallel Port and choose Auto Select or the LPT port from the drop down menu 2 Check the Always monitor RTCK checkbox to use the RTCK to pace the TCK clock frequency from the external JTAG test equipment Note Using RTCK requires another connector pin 3 Click the FlashLINK Connect Test button or the RLink Connect Test button as applicable to confirm connectivity between your PC and the target board The dialog shown in Figure 37 Link connectivity test dialog appears showing the preliminary steps required before continuing Figure 37 Link connectivity test dialog FlashLINK Connect Test xj 1 Ensure the FlashLINK cable is installed on your parallel port 2 Connect the loop back cable provided to the FlashLINK unit 3 Connect the black wire GND to a ground source 4
65. roject Report for an example 3 106 2 Introduction to the CAPS user interface UM0225 2 2 3 2 2 4 11 56 The view menu The view menu selection allows the user to toggle the user interface panes to be displayed while working on a project Check the menu item to enable the display This section describes the operations available in the view menu Figure 4 View menu Design Flow Output Log Full Screen Toolbar Status Bar The help menu Ral CAPS new upj Pin Summary Project Tools View Help Design Flow 2 v Output Log Full Screen Toolbar Manage Project w Status Bar Display the CAPS design flow pane Display the output log pane that shows commands executed by CAPS and informational and status messages See Figure 1 CAPS user interface Maximize the CAPS display interface on the screen Display the toolbar See Figure 1 CAPS user interface Display the status bar See Figure 1 CAPS user interface The help menu provides access to various links to obtain technical information about ST Microelectronics microcontroller products and to report questions or issues related to CAPS This section describes the operations available in the help menu 4 UM0225 2 Introduction to the CAPS user interface Figure 5 Help menu CAPS Project View s s D 2 MEE ome Page About CAPS CAPS Update Related Documentation
66. roperty of their respective owners 2006 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 3 56 56
67. sh FFFFFFFF Step 3 Execute JTAG ISP Operations JV Merge MCU firmware Click here to perform specified JITAG ISP operations gt gt Step 4 Save or retrieve JTAG ISP setup Specify folder and filename to save this JTAG ISP session setup or to retrieve a previous session Save Select folder and file Browse File Checksum ATE File HW Setup Reset Target Assert Reset For Help press F1 Project new Device STR912FW44 06 20 2006 12 30 17 7 The edit windows contain default values for the current project Follow these steps for each device in the device programming chain 1 Click the Browse button to use the file browser to load a saved programming data ob file 2 After opening the programming data file click the Add button to add the file to the JTAG chain list window Highlight a file in the list and click Delete to remove the file from the listed Highlight the device and click the Move scroll buttons to reorder the chain list Note 1 The list device order must match the physically device order 2 Device 1 should be the first device on the board that has its TDI pin connected to the JTAG ISP programmer 3 To change the device type highlight the device in the device list then select the desired device type from the Select device drop down menu Click the Update button to apply the change 4 Tochange the memory region of a device highlight the device in the device list then
68. ssignment Note The selected peripherals affect the initialization module in the HAL library A default C header file 91x_conf H is automatically generated to be included with the HAL library source code It is recommended to generate a C header file to be included in your source code as described in Section 3 3 3 to facilitate integration of the CAPS design and initialization Figure 17 Peripheral Pin Assignment tab shows a list of peripherals available for the target device Figure 17 Peripheral Pin Assignment tab CAPS new upj Peripheral Pin Assignment Project Tools View Help Da 3 9 LYD Voltage Clocks Peripheral Pin Assignment Pin Summary Manage Step 1 Select the peripheral from the List of available peripheral s box for GPIO pins assignment Project List of available peripheral s List of assigned peripherals CAN Embedded Trace Interface Ethernet MII Interface External DMA Request External Interrupt Request External Memory Interface Assign gt gt Additional Settings lt lt Unassign Program Device Legend Assignable Unassignabie For Help press F1 Project Inew Device STR912FW44 03 24 2006 23 5 7 Select a peripheral from the list and click the Assign gt gt button to assign the pin moving it to the list in the right window As peripherals are assigned a dialog window displays co
69. ted iin a sip a a ta mn mh 3 1 1 INS tANAUOM spenen eee eee Mae ee Mek ee eRe RK Ae Rae es eee ee tee 3 1 1 1 System requirements i 3 1 1 2 Installing CAPS kad ken 3 1 13 Uninstalling CAPS sa na No 4 12 Setting up the target hardware i 4 13 INOW TO USE TiS manvals s send ced hoes tanpi uaa RA ees 5 1 4 Recommended reading i 5 Introduction to the CAPS user interface 6 2 1 Project development 0000 eee ee 6 2 2 The user interface view ee 6 2 2 1 The project menu AN 8 2 2 2 The tools menu NN 10 2 2 3 The view MenU AN 11 2 2 4 The help menu 11 2 3 Starting a project 12 2 3 1 Creating a new project u sasaaa e 060 6000 12 2 3 2 Opening an existing project ses teea tee 13 Designing with CAPS i 15 3 1 Design IOW sssri wees Aaaa Ee EEA EEE RE EA 16 3 1 1 Manage Projectdialog i 16 3 1 2 Designentry forms 0 17 3 1 3 Additional settings form 0 17 3 1 4 4 Program device form 0 18 3 2 Specifying the LVD voltage i 18 3 3 Specifying the clock source and frequency i 19 3 3 1 Selecting the clock source and frequency i 19 3 3 2 Specifying the clock divisor 9 22 3 3 3 Saving the clock settings i 23 3 4 Spec
70. tion to the CAPS user interface for a basic understanding of the CAPS user interface More advanced users may skip this section e For a detailed discussion of how to use CAPS features read Designing with CAPS Recommended reading You are encouraged to download the datasheet associated with a particular device The datasheet may be the only source of important configuration information needed for your design 3 UM0225 2 Introduction to the CAPS user interface 2 2 1 2 2 3 Introduction to the CAPS user interface This section introduces you to the following CAPS topics e Project development steps and considerations e A reference for the CAPS user interface e Beginning steps needed to start a project Project development The CAPS software guides the designer through the process of configuring a target device for a particular application using the following project development steps 1 Create a unique project for each device under test application combination 2 Configure voltage clock source peripheral and GPIO pins and hardware and firmware parameters 3 Merge the design with your Intel hex format firmware file 4 Program the resulting programming data file into your device 5 Save your project to a file for later use The user interface This section is a reference for the CAPS user interface To learn how to begin using the interface to work with a project see Starting a project Figure
71. uency The master clock MSTR in the Clock Control Unit CCU is derived from one of three clack input sources Select clock source to the CCU Main Oscillator input clock OSC 4 to 25 MHz external crystal PLL clock The source for the OSC is a 4 to 25 MHz external crystal connected to 5TR91xF Enter your OSC frequency 25 MHz Note If you want STR91xF to provide clock to the external Ethernet PHY interface device OSC frequency should be 25 MHz Otherwise a separate clock is needed for the PHY Click here to validate and refresh clock calculation gt gt Refresh Enter the external crystal frequency between 4 and 25 MHz and with the same constraints as described above After selecting the clock source and specifying the frequencies click Refresh to validate he input and refresh the clock calculation 3 3 2 Specifying the clock divisor CAPS provides the facility for dividing the master clock to the CPU and peripherals to meet particular system requirements Step 2 Specify Clock Divisors provides the following divider options e RCLK Divider e HCLK Divider e PCLK Divider e FMICLK Divider 3 22 56 3 Designing with CAPS UM0225 3 3 3 23 56 Figure 15 Clock divisor specification step 2 Step 2 Specify Clock Divisors You have the option of dividing the master clock to the CPU and peripherals in order to meet your system requirements AHB Bus Mil_PHYCLK AHBDI 1 24 Typica
72. y write protected to prevent accidental data loss Click the checkbox for the sector you wish to write protect Uncheck the box to disable protection Protection granularity is eight sectors in Main Flash and four sectors in Secondary Flash 3 6 5 Firmware placement The firmware file may be located in main or secondary flash memory In the Firmware Placement dialog enter the start and end hexadecimal addresses and the firmware filename for the desired flash area 3 6 6 Setting OTP programmable memory bytes The OTP Settings dialog allows you to write values to and lock programmable memory 3 32 56 3 Designing with CAPS UM0225 Note 3 7 33 56 Thirty two bytes of OTP memory can be programmed one time only through either the JTAG programmer or by the CPU These bytes can never be altered once they are programmed Enter the hexadecimal value in the numbered byte location Table 2 Reserved OTP memory bytes shows the reserved and recommended OTP memory usage Table 2 Reserved OTP memory bytes Byte Number Reserved Recommended Usage 24 29 Ethernet MAC address 31 Mask identifier 32 Family identifier Setting the OTP lock bit disables any further writing to OTP memory The lock bit itself is also one time programmable If the OTP array is unlocked it is always possible to write to an OTP byte location that has not been written It is never possible to change the value of an OTP byte lo

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