µPD78F9842
Contents
1. A saddr A CY A saddr CY A laddr16 CY A addr16 CY A HL A CY HL A HL byte A CY lt HL byte A byte A CY A byte saddr byte saddr CY saddr byte A CY A r A saddr A CY lt A saddr A laddr16 A CY lt A addr16 A HL A CY A HL A HL byte A CY lt A HL byte A byte A CY A byte CY saddr byte saddr lt byte CY A r A CY A r CY A saddr A CY lt A saddr C A laddr16 A CY lt addr16 CY A HL A CY A HL CY A HL byte A CY lt A HL byte CY A byte lt A byte byte lt saddr byte saddr A laddr16 lt A addr16 A HL A HL A HL byte 3 5 34 09 0 3 0 3 014 3 0 5 0 9 RIL 0 0 0 8 05 SA lt A HL byte Remark instruction clock is based on the CPU clock fceu specified in the processor clock controller register PCC 20 Preliminary Product Information Clock2. Operation AC CY Remark OR A byte 2 4 lt byte saddr byte 3 6 saddr lt saddr v byte A r 2 4 AcAvr A saddr 2 4 A lt A v laddr16 3 8 lt v addr16 HL 1 6 lt v HL A HL byte 2 6 A lt A v HL byte XOR A byte 2 4 lt A saddr byte 3 6 saddr lt saddr byte A r 2 4 2 4 A lt laddr16 3 8 lt v addr16 A HL 1 6 A A x HL A HL byte 2 6 lt A v HL byte CMP A byte 2 4 A byte x X saddr byte 3 6 saddr byte x 2 4 A r x x A saddr 2 4 A saddr laddr16 3 8 A addr16 X A HL 1 6 HL x HL byte 2 6 A HL byte ADDW AX word 3 6 AX CY lt AX word SUBW AX word 3 6 AX CY lt AX word x X CMPW AX word 3 6 AX word x x INC r 2 4 rer 1 x saddr 2 4 saddr saddr 1 x DEC r 2 4 rer 1 x saddr 2 4 saddr saddr 1 x INCW rp 1 4 rp lt rp 1 DECW rp 1 4 rp lt rp 1 ROR A 1 1 2 CY Az lt Ao lt Am x 1 x ROL A 1 1 2 CY Ao lt Az lt Am x 1 x RORC 1 1 2 CY lt lt Am1 lt x 1 ROLC A 1 1 2 CY lt Az Ao lt CY Ama lt Am x 1 x Preliminary Product Information The instruction clock is based on
3. Flash Memory Version Mask ROM Version 78 9842 789841 789842 16 Kbytes 8 Kbytes 16 Kbytes Item High speed RAM 256 bytes Electrical specifications May differ between the flash memory and mask ROM versions Caution There are differences in the amount of noise tolerance and noise radiation between flash memory versions and mask ROM versions When considering changing from a flash memory product to a mask ROM version during process from experimental manufacturing to mass production make sure to sufficiently evaluate the flash memory versions using commercial samples CS not engineering samples ES of the mask ROM versions Preliminary Product Information 35 78 9842 APPENDIX DEVELOPMENT TOOLS The following development tools are available for developing systems that use the uPD78F9842 LANGUAGE PROCESSING SOFTWARE RA78KO0S 2 Assembler package common to the 78K 0S Series CC78K0S 23 C compiler package common to the 78K 0S Series DF789842 5535 Device file for the 789842 Subseries FLASH MEMORY WRITE TOOLS Flashpro III Model number FL Dedicated flash programmer for on chip flash memory PG FP3 FA 44GB 494 Flash memory write adapter for 44 pin plastic QFP Connection is required according to the target product Flashpro controller A program controlled by a PC is included in the Flashpro III Can be operated in Windows 95
4. Circuit Type Recommended Connection of Unused Pins POO to P07 When used as inputs individually connect these pins to the or Vss pin via resistors P10 to P17 When used as outputs leave these pins open P20 TOFF7 P21 TxD P22 RxD P23 TO82 25 1 1 1 P60 ANIO to Input Connect these pins directly to the or Vss pin P67 ANI7 TO70 to TO75 7 1075 4 Output Individually connect these pins to the Von or Vss pin via resistors connect these pins to the or Vss pin via resistors RESET PS Preliminary Product Information 11 78 9842 Figure 3 1 Pin Input Output Circuits Type 2 Type 8 A 2 Pull up enable IN Data pH H P ch IN OUT Output H N ch Schmitt trigger input with a hysteresis characteristics disable Vss Type 4 Type 9 C Comparator Vpop P ch INO N ch 1 Data i VREF IN OUT Threshold voltage Output N ch disable V 55 77 Input enable Type 5 A e Pull up gt enable Output disable Input Voo Vss 77 enable 12 Preliminary Product Information 78 9842 4 MEMORY SPACE The uPD78F9842 can access up to 64 Kbytes of memory space Figure 4 1 shows the memory Figure 4 1 Memory Map FFFFH Special function registe
5. DEBUGGING TOOLS IE 78K0S NS This in circuit emulator is used to debug hardware or software when application systems In circuit emulator that use the 78K 0S Series are developed The IE 78K0S NS supports the integrated debugger ID78KOS NS The IE 78KOS NS is used in combination with an interface adapter for connection to an AC adapter emulation probe or host machine IE 70000 MC PS B This adapter is used to supply power from a 100 to 240 V AC outlet AC adapter IE 70000 98 IF C This adapter is required when a PC 9800 series computer other than a notebook type is Interface adapter used as the host machine for the IE 78KOS NS C bus supported IE 70000 CD IF A This PC card and interface cable are required when a PC 9800 series computer is used as PC card interface the host machine for the IE 78KOS NS PCMCIA socket supported IE 70000 PC IF C This adapter is required when IBM PC AT or compatibles are used as the host machine for Interface adapter the IE 78K0S NS ISA bus supported IE 70000 PCI IF This adapter is required when a PCI bus embedded computer is used as the host machine Interface adapter for the IE 78KOS NS IE 789842 NS EM1 This board is used to emulate the peripheral hardware specific to the device The IE Emulation board 789842 NS EM1 is used in combination with the in circuit emulator NP 44GB This board is used to connect the in circuit emulator to the target system The NP 44GB is for the 44 pin
6. 0 0 039 G 1 0 0 039 0 08 0 003 H 0 37 19 08 0 01578 003 1 0 16 0 007 J 0 8 T P 0 031 T P K 1 6 0 2 0 063 0 008 0 009 L 0 8 0 2 0 031 8 888 0 06 0 002 0 17 76 08 0 007 20 003 0 10 0 004 0 005 2 7 0 1 0 106 0 003 0 125 0 075 0 005 0 003 7 7 R ges 34 5 3 0 0 119 S44GB 80 3BS 1 Preliminary Product Information 33 78 9842 44 PIN PLASTIC 10 x 10 mm PACKAGE DRAWING detail of lead end 5 e R C ITEM MILLIMETERS Each lead centerline is located within 0 16 mm of A 12 0 0 2 its true position T P at maximum material condition 10 0 0 2 10 0 0 2 12 0 0 2 1 0 1 0 0 08 0 37 79 07 O miojou 0 2 0 8 1 0 0 2 0 5 0 03 0 17 79 06 0 10 1 4 0 05 0 140 05 Lee 1 6 MAX 0 6 0 15 5446 80 8 5 1 34 Preliminary Product Information 78 9842 APPENDIX DIFFERENCES BETWEEN THE 78 9842 AND MASK ROM VERSIONS The uPD78F9842 is produced by replacing the internal ROM of a mask ROM version with flash memory Table A 1 lists the differences between the uPD78F9842 and mask ROM versions Table A 1 Differences between the 78 9842 and Mask ROM Versions
7. A D function of the 789167 44 pin 4uPD789167 n Device developed by enhancing the timers of the 789104 30 pin 789156 Device developed by enhancing the A D function of the 789146 78 0 08 30 pin 7 uPD7891 477 Device developed by adding EEPROM to the 789104 Series a eee eee 28 30 789134 Device developed by enhancing the A D function of the 789124 28 30 pin 789124 RC oscillator version of the 789104 28 30 pin 4PD789114A Device developed by enhancing the A D function of the 789104 28 30 pin 72 uPD789104A Device developed by adding an A D function and multiplier to the 789026 44 pin 4PD789842 2 Inverter control circuit with built in UART For LCD driving 80 pin HPD789417A Device developed by enhancing the A D function of the PD789407A 80 pin 789407 Device developed by adding an A D function and enhancing the timers of the 789026 88 pin 7 789830 With built in UART bus dot LCD 44 pin 789840 Device for key pad with a built in 5 pin 0789810 Device for card with built in security circuit 42 44 pin 789800 Device for a PC keyboard with a built in USB function Preliminary Product Information 3 78 9842 The following table lists the major differences in functions between
8. NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices is Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact an NEC sales representative in advance Anti radioactive design is not implemented in this product M4 96 5
9. required for oscillation to stabilize once a reset sequence ends or STOP mode is released Use a resonator that will become stable within the oscillation wait time Caution When using the system clock oscillation circuit observe the following conditions for the wiring of the sections enclosed in dotted lines in the above diagrams so as to avoid the effects of wiring capacitance etc Keep the wiring as short as possible Do not allow signal wires to cross one another Keep the wiring away from wires that carry a high non stable current Keep the grounding point of the capacitors at the same level as the Vss Do not connect the grounding point to a grounding wire that carries a high current Do not extract a signal from the oscillation circuit Preliminary Product Information 25 78 9842 DC CHARACTERISTICS 40 to 85 C 4 0 to 5 5 V meme um ne Dec o High level output current LT Low level output current lo ___________ ___ CN E we we qmm 0 0 of EN lem ST e High level input leakage current Vin Low level input leakage current 0 Pins otherthanxtandx2 o Power supply current 9 A 8 38 MHz crystal osc
10. the ports using software Caution To select a transmission method always use the corresponding number of pulses listed Table 5 1 Figure 5 1 Format of Transmission Method Selection 10V Voo RESET Vss 14 Preliminary Product Information 78 9842 5 2 Flash Memory Programming Function Flash memory writing and other operations can be performed by transmitting receiving commands and data according to the selected transmission method Table 5 2 lists the main flash memory programming functions Table 5 2 Main Flash Memory Programming Functions Erases the entire memory contents Batch blank check Checks that the entire memory contents have been erased Data write Writes to the flash memory according to the specified write start address and number of bytes of to be written Batch Batoh verity Compares the entire memory contents with the input data the entire memory contents with the input data 5 3 Connecting Flashpro Ill The connection between the Flashpro and the uPD78F9842 varies with the transmission method UART or pseudo 3 wire Figures 5 2 and 5 3 show the connection for each transmission method Figure 5 2 Flashpro Ill Connection in UART Mode Flashpro III PD78F9842 VppnNote Voo RESET RxD TxD Vss AVss Note 1 Figure 5 3 Flashpro Connection in Pseudo 3 W
11. the subseries Timer 8 bit Serial Interface Remarks ao I IEE Small scale 789046 ich 1ch toh 1ch 1ch UART 1ch 34 pins general uPD789026 4Kto16K purpose applications HPD789014 2K to 4K EM Small scale uPD789217AY 16 24K 3ch 1 i RC oscillator general M 1ch version with on purpose SMB ich chip EEPROM 789197 With on chip function 77 1ch UART 1ch uPD789167 67 4K to 16K uPD789146 46 E E 24A ET 14A uPD789104A 04A pou control 789417 12Kto24K 3ch ich 1ch ich 7ch UART 1ch 43 pins Pam 2 ASSP uPD789840 1ch ach _____ 29 pins EN EEPROM jx me Note 10 bit timer 1 channel With on chip EEPROM RC oscillator version 4 Preliminary Product Information 78 9842 FUNCTIONS Instruction set 16 bit operations Bit manipulations such as set reset and test ports Total 30 CMOS input output pins 22 CMOS input pins 8 Timers 10 bit inverter control timer 1 channel 8 bit timer event counter 2 channels 8 bit timer counter 1 channel Watch timer 1 channel Watchdog timer 1 channel A D converters 8 bit resolution x 8 channels Serial interface UART 1 channel Multiplier 10 bits x 10 bits 20 bits SWAP Contents of the high order 4 bits and th
12. 16J U11816E 5 78 05 5 78 05 System Simulator Windows Simulator Windows Base Reference 1148 1489J U1 SM78K Series System Simulator External Parts User Open U10092J U10092E Interface C EN ID78KOS NS ID78KOS NS Integrated Debugger Windows Debugger Windows Base Reference 912909 uotE IE 78KOS NS In circuit Emulator U13549J U13549E IE 789742 NS EM1 Emulation Board To be prepared To be prepared DOCUMENTS RELATED TO SOFTWARE TO BE INCORPORATED INTO THE PRODUCT USER S MANUALS Document No OS for 78 05 Series 78 05 U12938J U12938E OTHER DOCUMENTS Document No IC Package Manual CD ROM 22 11 13388 Semiconductor Device Mounting Technology Manual C10535J C10535E aint Gy Caution The related documents listed above are subject to change without notice Be sure to use the latest documents when designing application systems 38 Preliminary Product Information 78 9842 Preliminary Product Information 39 78 9842 40 Preliminary Product Information 78 9842 Preliminary Product Information 41 78 9842 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade
13. A sfr 2 4 A lt sfr sfr A 2 4 sfr A A laddr16 3 8 A lt addr16 laddr16 3 8 addr16 lt A PSW byte 3 6 PSW lt byte x X x A PSW 2 4 lt PSW PSW A 2 4 PSW A x X A DE 1 6 lt DE DE 1 6 DE A HL 1 6 A lt HL HL A 1 6 HL HL byte 2 6 A lt HL byte HL byte 2 6 HL byte A XCH 1 4 Ar 2 6 Aor A saddr 2 6 A saddr A sfr 2 6 A lt gt str A DE 1 8 A DE A HL 1 8 A lt gt HL A HL byte 2 8 A HL byte MOVW rp word 3 6 lt word saddrp 2 6 lt saddrp saddrp AX 2 8 saddrp lt AX AX rp 1 4 AX lt rp rp AX 1 4 rp AX XCHW rp 1 8 AX Notes 1 Except when r 2 Except when r Aor X 3 Only when rp BC DE or HL Remark The instruction clock cycle is based on the CPU clock fceu specified in the processor clock controller register PCC Preliminary Product Information 19 byte 78 9842 Operation A CY byte saddr byte saddr CY saddr byte A r saddr A saddr A laddr16 A CY lt addr16 A HL A CY A HL A HL byte A CY lt HL byte A byte A lt byte CY saddr byte saddr CY saddr byte CY A r CY A r4 CY
14. AL 5 24 8 PACKAGE DRAWINGS 2 2 33 APPENDIX DIFFERENCES BETWEEN THE uPD78F9842 AND MASK VERSIONG 35 APPENDIX DEVELOPMENT TOOLS 36 APPENDIX RELATED 65 2 2 38 6 Preliminary Product Information 78 9842 1 PIN CONFIGURATION TOP VIEW 44 pin plastic LuPD78F9842GB 3BS MTX 10 10 mm 2 7 mm resin thickness LuPD78F9842GB 8ES 10 10 mm 1 4 mm resin thickness fe x 2 2 lt zs QN a 0 P60 ANIO RESET o TO75 98 gt gt P63 ANI3 o TO74 P64 ANI4 o 2 o TO73 P65 ANI5 o 3 72 P66 ANI6 o 4 o TO71 P67 ANI7 o 5 o TO70 AVss O 6 o P25 INTP1 TI81 o 7 o P24 INTPO TI80 1 8 P23 TO82 2 9 P22 RxD 10 o P21 TxD 4 o P20 TOFF7 O O O Cautions 1 Connect the Vr pin directly the Vss pin 2 Connect the pin to the pin 3 Connect the AVss pin to the Vss pin ANIO to ANI7 Analog Input RxD Receive Data Analog Power Supply TI80 TI81 Timer Input AVss Analog Ground TI70 to TO75 TO82 T
15. H MEMORY PROGRAMMING CHARACTERISTICS 1 Basic characteristics Ta 20 to 60 C 4 0 to 5 5 V 88 e e be LE 2 AC CHARACTERISTICS 20 to 60 Voo 4 0 to 5 5 V Flash memory write mode RESET count start time a Count execution time Undefined Ver pulse high level width and low level width Vp pulse rising time and falling tr time Preliminary Product Information 31 N EC FLASH MEMORY WRITE MODE 10V OV RESET 32 5 1 D78F9842 Preliminary Product Information 78 9842 8 PACKAGE DRAWINGS 44 PIN PLASTIC QFP 10 x 10 mm PACKAGE DRAWING detail of lead end ITEM MILLIMETERS INCHES 0 008 A 13 2 0 2 0 520 0 008 0 008 B 10 0 0 2 0 394 0 008 NOTE 0 008 9 1 Controlling dimension millimeter e 2 0 3942 0 009 13 2 0 2 0 520 0 008 2 Each lead centerline is located within 0 16 mm 0 007 inch of 70 009 its true position T P at maximum material condition F 1
16. NVERTER CHARACTERISTICS 40 to 85 C 4 0 to 5 5 V mew _____ ___ ____ 19191 2 2 se 1251 1121 Note No quantization error 1 2 LSB is included DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA HOLD CHARACTERISTICS 40 to 85 C Oscillation stabilization wait Cleared RESET 2 Note 1 Notes 1 The oscillation stabilization time is a period which the operation of the CPU is stopped in order to avoid unstable operation at the start of oscillation 2 The typical TYP value can be selected from 2 fx 2 fx or 2 fx by bits 0 to 2 OSTSO to OSTS2 of the oscillation stabilization time select register Remark fx system clock oscillation frequency Preliminary Product Information 29 78 9842 DATA HOLD TIMING STOP mode release by RESET Internal reset operation HALT mode STOP mode lt Operation mode Data hold mode Stop instruction execution RESET DATA HOLD TIMING Standby release signal STOP mode release by interrupt signal HALT mode M STOP mode gt 5 Operation mode Data hold mode Stop instruction execution Standby release signal interrupt request 30 Preliminary Product Information 78 9842 FLAS
17. O ANI7 8 bit input only port y o Port 2 TOFF7 6 bit input output port Im Input output can be specified in 1 bit units On chip pull up resistor connection can be specified by means of ID Preliminary Product Information 9 78 9842 3 2 Non Port Pins Input External interrupt inputs for which effective edges rising and or falling Input P24 T180 edges can be specified 25 181 Timer ouput External count clock input of TM80 Input TI81 External count clock input of TM81 P25 INTP1 TO82 Output Timer output of TM82 A D converter ground potential px qp A D converter analog power supply Po Crystal resonator connection for system clock oscillation Low _ x T wesemmema vn 1400 This pin is used to set the flash memory programming mode and applies a high voltage when a program is written or verified In normal operation mode connect this pin directly to the Vss pin 10 Preliminary Product Information 78 9842 3 3 Pin Input Output Circuits and Connection of Unused Pins Table 3 1 lists the input output circuit type for each pin and explains how unused pins are handled Figure 3 1 shows the configuration of each type of input output circuit Table 3 1 Type of Input Output Circuit for Each Pin and Connection of Unused Pins
18. PRELIMINARY PRODUCT INFORMATION NEC MOS INTEGRATED CIRCUITS p 8 BIT SINGLE CHIP MICROCONTROLLER The uPD78F9842 is a member of uPD789842 Subseries of the 78K 0S Series product The uPD78F9842 is a product that has expanded the internal ROM of the uPD789841 789842 and replaced it with flash memory Flash memory can be written or erased electrically on board making the uPD78F9842 best suited for prototypes in system development small scale production or systems likely to be upgraded frequently The details of functions are described in the following user s manuals Be sure to read them before designing 789842 Subseries User s Manual U13776E 78K 0S Series User s Manual Instructions U11047E FEATURES Pin compatible with mask ROM versions other than the Ver Flash memory 16 Kbytes Internal high speed RAM 256 bytes Selectable minimum instruction execution time High speed 0 24 us and low speed 0 96 us with the system clock operating at 8 38 MHz I O ports 30 O Timer 6 channels 10 bit inverter control timer 1 channel 8 bit timer event counter 2 channels 8 bit timer counter 1 channel Watch timer 1 channel Watchdog timer 1 channel O A D converter with 8 bit resolution 8 channels Serial interface UARTOO 1 channel Multiplier 10 bits x 10 bits 20 bits O SWAP contents of the high order 4 bits and the low order 4 bits of the 8 bit register a
19. cumulator X X register B B register C C register D D register E E register H H register L L register AX AX register pair 16 bit accumulator BC BC register pair DE DE register pair HL HL register pair PC Program counter SP Stack pointer PSW Program status word CY Carry flag AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag NMIS Flag to indicate that a nonmaskable interrupt is being processed Contents of a memory location indicated by a parenthesized address or register name XL High order and low order 8 bits of a 16 bit register Logical product AND v Logical sum OR Exclusive OR Inverted data addri6 16 bit immediate data or label jdisp8 Signed 8 bit data displacement value 6 1 3 Description of the flag operation field Blank No change Cleared to 0 Set 1 Set or cleared according to the result Restored to the previous value 18 Preliminary Product Information 6 2 Operations 78 9842 Clock Operation J Z AC CY MOV r byte 3 6 r lt byte sadar byte 3 6 saddr byte sfr byte 3 6 sfr lt byte 2 4 Acr pA 2 4 lt saddr 2 4 lt saddr 2 4 lt A
20. e low order 4 bits of the 8 bit register are Switchable Preliminary Product Information 5 78 9842 CONTENTS 1 PIN CONFIGURATION TOP 2 4 7 2 BLOCK 8 PIN 25445 520414 9 EE Dudum 9 32 m nanne nanna 10 3 3 Input Output Circuits and Connection of Unused 11 4 MEMORY SPACE o EI eos 13 5 FLASH MEMORY PROGRAMMING 4 0 000 0 0 14 51 Selecting Transmission Method 14 5 2 Flash Memory Programming senes nnne nnns nitens ananas nnne nasse nnns 15 5 3 Connecting 55 5 4 M 15 5 4 Settings for Flashpro lll eere tenore uo aint nnus ntes uan Dna pP rase Rn 16 6 INSTRUCTION SET OVERVIEW 17 MEE CODICE 17 6 2 OPO ratiONS 19 7 ELECTRIC
21. e processor clock controller register PCC Preliminary Product Information 23 78 9842 7 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Ta 25 C 5 5 5 Dmm orra arnon m Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remark Unless otherwise specified the characteristics of alternate function pins are the same as those of port pins 24 Preliminary Product Information 78 9842 CHARACTERISTICS OF THE SYSTEM CLOCK OSCILLATION CIRCUIT 40 to 85 C 4 0 to 5 5 V Ceramic Oscillator frequency oscillation resonator voltage range Oscillation Time after the stabilization time has reached the minimum value in the oscillation voltage Crystal oscillator Oscillator frequency fx Note 1 Oscillation stabilization time Note 2 Notes 1 Only the characteristics of the oscillation circuit are indicated See the description of the AC characteristics for the instruction execution time 2 Time
22. illation operating Undefined Undefined mode Note 2 1502 8 38 MHz crystal oscillation HALT Undefined Undefined TE STOP mode mode undefined Undefed Ipp4 8 38 MHz crystal oscillation A D Undefined Undefined operating mode Notes 1 The power supply current does not include the current flowing through the on chip pull up resistor 2 During high speed mode operation when the processor clock control register PCC is cleared to OOH Remark Unless otherwise specified the characteristics of alternate function pins are the same as those of port pins 26 Preliminary Product Information 78 9842 AC CHARACTERISTICS 1 Basic operations Ta 40 to 85 C 4 0 to 5 5 V Cycle time minimum instruction When the PCC is set to 00 2 2 execution time ro meme masses P m Si 2 Serial interface UART 40 to 85 C Vp 4 0 to 5 5 V Preliminary Product Information 27 78 9842 AC TIMING MEASUREMENT POINTS except the X1 input 0 8 0 8 Measurement points 0 2Vop 0 2Vop CLOCK TIMING MIN Vita MAX X1 input TI TIMING 80 TI81 INTERRUPT INPUT TIMING INTPO INTP1 RESET INPUT TIMING ni 28 Preliminary Product Information 78 9842 A D CO
23. imer Output INTPO 1 Interrupt from Peripherals TOFF7 Timer Output Off POO to P07 Porto TxD Transmit Data P10 to P17 Porti Power Supply P20 to P25 Port2 Programming Power Supply P60 to P67 Port6 Vss Ground RESET Reset X1 X2 Crystal Preliminary Product Information 7 2 BLOCK DIAGRAM TI80 P24 INTPO TI81 P25 INTP1 TO82 P23 TO70 TO75 lt 10 bit INVERTER TOFF7 P20 CONTROL TIMER 11 8 bit TIMER EVENT COUNTER80 8 bit TIMER EVENT 81 WATCHDOG TIMER RxD P22 INTPO P24 pir Vss VPP INTP1 P25 L H 181 Preliminary Product Information lt PD78F9842 PORTO gt P00 P07 PORT1 gt 1 17 7 gt P20 P25 P60 P67 ANIO P60 ANI7 P67 AVss RESET X1 2 MULTIPLIER 78 9842 3 PIN FUNCTIONS 3 1 Port Pins POO to P07 y o Port 0 8 bit input output port Input output can be specified in 1 bit units When used as an input port on chip pull up resistor connection can be specified by means of software P10 to P17 Port 1 8 bit input output port Input output can be specified in 1 bit units When used as an input port on chip pull up resistor connection can be TxD RxD specified by means of software P20 P21 P22 P23 P24 P25 software TO82 INTPO TI80 INTP1 TI81 P60 to P67 Input Port6 ANI
24. ire Mode Flashpro Ill u PD78F9842 RESET POO serial clock P02 serial input P01 serial output Vss AVss Note n Oor 1 Preliminary Product Information 15 78 9842 5 4 Settings for Flashpro Ill When using the Flashpro III to write to flash memory set the Flashpro Ill as listed in Table 5 3 Table 5 3 Settings for the Flashpro Ill Transmission Method Settings for the Flashpro III Number of Pulses UART 4 1943 2 UART BPS 9600 bps p CPU CLK On Target Board On Target Board 4 1943 MHz SIO CLK In Flashpro SIO CLK 1 00 MHz Notes 1 The number of pulses supplied from the Flashpro during the initialization of serial transmission Pins to be used in transmission depend on this number 2 Select one of the following 9 600 19 200 38 400 or 76 800 bps Remark COMM PORT Selection of the serial port SIO CLK Selection of the serial clock frequency CPU CLK Selection of the input CPU clock source 16 Preliminary Product Information 78 9842 6 INSTRUCTION SET OVERVIEW The instruction set for the wPD78F9842 is listed later 6 1 Conventions 6 1 1 formats and descriptions The description made in the operand field of each instruction conforms to the operand format for the instructions listed below the details conform to assembl
25. nternational Business Machines Corporation HP9000 series 700 and HP UX are trademarks of Hewlett Packard Company SPARCsiation is a trademark of SPARC International Inc Solaris and SunOS are trademarks of Sun Microsystems Inc NEWS and NEWS OS are trademarks of SONY Corporation The related documents in this publication may include preliminary versions However preliminary versions are not marked as such No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features
26. oller register PCC 22 Preliminary Product Information 78 9842 Operation Z AC CY BC addr16 2 6 PC PC 2 jdisp8 if CY 1 BNC addr16 2 6 PC 2 jdisp8 if CY 0 BZ addr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ 16 2 6 2 jdisp8 2 0 BT saddr bit addr16 4 10 PC c 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC lt 4 jdisp8 if sfr bit 1 A bit addr16 3 8 amp PC 3 jdisp8 if A bit 1 PSW bit addr16 4 10 PC 4 jdisp8 if PSW bit 1 BF saddr bit addr16 4 10 PC lt 4 jdisp8 if bit 0 sfr bit addr16 4 10 PC lt 4 jdisp8 if sfr bit 0 A bit addr16 3 8 PC PC 3 jdisp8 if A bit 0 PSW bit addr16 4 10 PC 4 jdisp8 if PSW bit 0 DBNZ B addr16 2 6 B lt B 1 then PC lt PC 2 jdisp8 if B 0 addr16 C C 1 then PC PC 2 jdisp8 if C 0 saddr addr16 saddr saddr 1 then PC PC 3 jdisp8 if 0 NOP No operation EI IE lt 1 Enable Interrupt DI IE 0 Disable Interrupt HALT Set HALT Mode STOP Set STOP Mode Remark The instruction clock is based on the CPU clock fceu specified in th
27. ower on does not necessarily define initial status of MOS device Produc tion process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed imme diately after power on for devices having reset function 42 Preliminary Product Information 78 9842 Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Germany GmbH Due
28. plastic QFP SM78K0S System simulator common to all 78K OS series units ID78K0S NS 25 Integrated debugger common to all 78K 0S series units DF789842 25 Device file for the 789842 Subseries REAL TIME OS 78 5 OS for the 78 05 Series 36 Preliminary Product Information 78 9842 Notes 1 Based on the PC 9800 series MS DOS Windows 2 Based on IBM PC AT and compatibles Japanese English Windows 3 Based on the HP9000 series 700 HP UX SPARCstation SunOS and Solaris and NEWS NEWS OS 4 Product manufactured by Naito Densei Machidaseisakusho 81 44 822 3813 Consult an NEC sales representative regarding purchase 5 Under development Remark 78 05 78 05 and 5 78 05 be used in combination with the DF789842 Preliminary Product Information 37 78 9842 APPENDIX RELATED DOCUMENTS DOCUMENTS RELATED TO DEVICES Document No 789841 789842 Preliminary Product Information U13790J U13790E UPD78F9842 Preliminary Product Information U13901J 789842 Subseries User s Manual U13776J To be prepared 78 05 Series User s Manual Instruction U11047J U11047E DOCUMENTS RELATED TO DEVELOPMENT TOOLS USER S MANUALS Document No RA78KOS Assembler Package U11622J U11622E Assembly Language U11599J U11599E Structured Assembly U11623J U11623E CC78KOS C Compiler Operation U118
29. r 256 x 8 bits FFOOH FEFFH Internal high speed RAM 256 x 8 bits FEOOH FDFFH Reserved Data memory Space 3FFFH 4000H 3FFFH Program area 0080H Internal flash memory 007FH 16384 x 8 bits CALLT table area 0040H 003FH Program memory space Program area 001EH 001DH 0000H 0000H Vector table area Preliminary Product Information 13 78 9842 5 FLASH MEMORY PROGRAMMING The internal program memory of the uPD78F9842 is flash memory Flash memory can be written to even while the device is mounted in the target system on board write To write a program to flash memory connect the dedicated flash programmer Flashpro Model number FL PR3 and PG FP3 to both the host machine and target system Remark The FL PR3 is manufactured by Naito Densei Machidaseisakusho 5 1 Selecting Transmission Method The Flashpro Ill writes to flash memory by means of serial transmission The transmission method to be used for writing is selected from those listed in Table 5 1 To select a transmission method use the format shown in Figure 5 1 according to the number of Ver pulses listed in Table 5 1 Table 5 1 Transmission Methods Transmission Method Number of Ver pulses UART TxD P21 RxD P22 Note Pseudo three wire mode serial clock input P01 serial data output 2 serial data input Note Serial transfer is performed by controlling
30. re switchable O Vectored interrupt sources 14 Power supply voltage 4 0 V to 5 5 V APPLICATIONS Inverter air conditioners etc The information contained in this document is being issued in advance of the production cycle for the device The parameters for the device may change before final production or NEC Corporation at its own discretion may withdraw the device prior to its production Document No U13901EJ1VOPMO0 1st edition Date Published December 1998 N CP K Printed Japan NEC Corporation 1998 78 9842 ORDERING INFORMATION Part number Package PD78F9842GB 3BS MTX 44 pin plastic QFP 10 x 10 mm 2 7 mm resin thickness PD78F9842GB 8ES 44 pin plastic QFP 10 x 10 mm 1 4 mm resin thickness 2 Preliminary Product Information uPD78F9842 78K 0S SERIES DEVELOPMENT The products of the 78K 0S Series are shown below The subseries names are indicated in the frames ESSERE In production Under development 44 pin With a built in subsystem clock in the 789026 42 44 pin Device developed by enhancing the timer function of the 789014 and expanding ROM and RAM 28 pin With a built in UART bus and capable of low voltage 1 8 V operation 44 48 pin uPD789217AY RC oscillator version of the 789197 44 48 pin s uPD789197AY 7 With built in EEPROM and SMB in the 789177 44 pin 2 789177 Device developed by enhancing the
31. sseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Preliminary Product Information NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd United Square Singapore 1130 Tel 65 253 8311 Fax 65 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Rodovia Presidente Dutra Km 214 07210 902 Guarulhos SP Brasil Tel 55 11 6465 6810 Fax 55 11 6465 6829 J98 11 43 uPD78F9842 EEPROM is a trademark of NEC Corporation MS DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries PC AT is a trademark of I
32. the CPU clock specified in the processor clock controller register PCC NEC uPD78F9842 21 78 9842 Operation bit saddr bit lt 1 sfr bit sfr bit 1 A bit A bit lt 1 PSW bit PSW bit lt 1 HL bit HL bit 1 bit saddr bit lt 0 sfr bit sfr bit 0 A bit PSW bit A bit lt 0 PSW bit lt 0 62 HL bit HL bit lt 0 CY 1 CY 0 CY lt laddr16 SP 1 lt PC SP 2 lt PC 3 lt 16 SP lt SP 2 addr5 SP 1 lt 1 SP 2 lt 1 lt 00000000 addr5 1 PC lt 00000000 addr5 SP 5 2 PCH lt SP 1 PC lt SP SP lt SP 2 PCH lt SP 1 PC lt SP PSW lt SP 2 SP lt SP 3 NMIS lt 0 SP 1 lt PSW lt SP 1 SP 1 lt SP 2 SP lt 2 PSW lt SP SP SP 1 lt SP 1 lt lt SP SP lt 2 SP AX SP AX AX SP AX SP laddr16 PC lt addr16 PC PC 2 jdisp8 AX PCH lt PCL lt X Remark instruction clock is based on the CPU clock fceu specified in the processor clock contr
33. the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS device behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to or GND with resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note P
34. y specifications more than one operand format is listed for an instruction one is selected Uppercase letters and square parentheses are used to specify keywords which must be written exactly as they appear The meanings of these special characters are as follows Immediate data specification Relative address specification Absolute address specification Indirect address specification Immediate data should be described using appropriate values or labels The specification of values and labels must be accompanied by or Operand registers expressed as r or rp in the formats can be described using both functional names X A C etc and absolute names RO R1 R2 and other names listed in Table 6 1 Table 6 1 Operand Formats and Descriptions X RO A R1 C R2 B E D R5 L R6 H R7 AX RPO BC RP1 DE RP2 HL RP3 Special function register symbol saddr FE20H FF1FH Immediate data or label saddrp FE20H FF1FH Immediate data or label even addresses only addr16 0000H FFFFH Immediate data or label only even addresses for 16 bit data transfer instructions adar5 0040H 007FH Immediate data or label even addresses only word 16 bit immediate data or label byte 8 bit immediate data or label bit 3 bit immediate data or label Preliminary Product Information 17 78 9842 6 1 2 Descriptions of the operation field A A register 8 bit ac
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