Tips on Using Test Vectors for Atmel PLDs
Contents
1. Inputs Pin 1 clk Pin 2 reset Outputs Pin 14 17 q0 3 Logic Equations 4 Bit Binary Counter equations using D type registers q0 d q0 ql d ql amp q0 ql amp q0 q2 d q2 amp ql amp q0 tf q2 amp ql q2 amp q0 q3 d q3 amp q2 amp ql amp qO q3 amp q2 q3 amp ql q3 amp q0 q3 0 ar reset resets the counter q3 0 ck clk clocks the counter COUNTA SI Name COUNT4 Partno XXXXX Date 3 27 95 Designer Atmel Device V750 BORK KK KKK I KK IK KKK I KR A KR IRR IRR k k k k IR k k k k k k k I ke ke ke X ek fe Simulation Input File for Register Example i4 BORK KK KKK I KK IK KK Kk Ck IK KA CK k kk Kk k kk A kk k ke k k ke kk I ke ke X ek S ORDER VECTORS 000000404040 C X4 Cr 0X 9 0 E L od d d D 10 clk 1 reset 1 q3 q2 Inputs ql q0 Outputs resets the counter Example 4 Using Sets for a group of signals in Test Vectors When using the ABEL or CUPL design language you can simplify the logic description for groups of signals such as Address and Data Lines by grouping the signals in a set This grouping of signals in sets also simplifies your test vectors and hence makes them easier to understand The 4 bit Binary Counter design from Example 3 was modified to show that the test vector implementation was simplified by grouping the counter outputs q3 q2 q1 and q2. Din EQUATIONS Qnodes cl Qnodes ar Qnodes d DECLARATI OPREG radix 2 used the ATV750 buried nodes out node 26 27 28 istype buffer reg_d 03 02 01 00 Q nodes 0 03 02 01 Shifting input always shift 0 into Q3 D3 D2 D1 D0 Data input k CLK Clock for the Shift Register RES Reset for the Shift Register Load amp Din Load in the data Load amp Qshift Shifts the data ONS rap Gear set to Binary numbering system TEST_VECTORS CLK RE 0 K G r C C a C r C L A 0 end S Load Din Qnodes Ser out Ser out QO 0 0 p IX 0000 0 f 0 7 Te 4 LELOT aa 1110 0 R Loads Data Din 0 f 0 X qt DITI X d H 0 Oo X MEL OTI HL 0 i 0 op X iL 0001 2 p 0 D X 0000 0 0 l 450 E Qs B 0101 1 z Loads Data Din 1 A OU wc X T 0000 0 E Resets Registers AIMEL 15 AIMEL CUPL Files SHIFT4 PLD Name SHIFT4 Partno XXXXX Date 3 27 95 Designer PLD Expert Company Atmel Assembly None Location None Device V750 Block Diagram ag Load eee gt Ser_out DO D3 gt When Load is TRUE D0 D3 data is loaded into the shift register Once Load is FALSE the data is shifted to the right D3 D0 A 0 is loaded into the D3 during the shifting process The last bit of the shift register Ser_out shifts the data out n Pin 1 CLK Pin 2 Load Pin 3
3. Low Fast Transition D Not Used X Output Not Tested Input Defined Default Level X X F Float Input or Output F Not Used L Test Output Low 0 L H Test Output High 1 H Z Test Input or Output for High Impedance AZ Z Note 1 In ABEL you can assign the test vector values to identifiers in the ABEL DECLARATIONS section and then use these identifiers in the TEST_VECTORS section The following is an example of the ABEL test vector value assignments H L X Z D U C K F 1 0 X Z D U C K F Figure 1 Typical Waveforms of Input Vectors Applied by a PLD Programmer JEDEC 4 Glock period gt vector Slow transition rate AIMEL Input signals set up before clock signals Fast transition rate Clock signals AIMEL Recommended Vector Usage The following recommendations will ensure 1 That your test vectors simulations results from ABEL or CUPL are consistent with the verification or testing results by the programming hardware 2 That the test vectors applied by the programmer are not hardware dependent t Recommendation 1 Always use the D U C or K vector value for clock pins or clock product terms Do not use 0 and 1 values to clock registers See Example 1 in the Appendix Section For registered functions it is very important to always use the value D U C or K to clock registers If you
4. Vectors Example 5 Repeating Vectors with the ABEL REPEAT or CUPL REPEAT syntax Example 6 Simulating Buried Nodes Example 7 Testing Bi Directional I O pins In this application note please pay spe cial attention to the key notes that are indicated by the symbol Simulating in ABEL ABEL allows the designer to enter test vectors within the ABEL source file by using the TEST_VECTORS statement ABEL provides two functional simulators PLASIM PLASIM EXE and JEDSIM JEDSIM EXE to simulate a PLD design The PLASIM simulator which simulates the ABEL logic equations is executed from the Simulate Equations Simulate Optimized or Simulate Fitted Design command in the ABEL design environment The first two commands simulate the pre fitted device indepen dent equations If you have the Atmel PLD fitters you can simulate fitted equa tions with the Simulate Fitted Design command The second simulator avail able in the ABEL development tool is the JEDSIM This simulator which is executed via the Simulate JEDEC command in the ABEL design environ ment verifies your test vectors with the logic data extracted from the device JEDEC file AIMEL T A Erasable Programmable Logic Device Application Note Rev 0479C 09 99 AIMEL Simulation Trace Options With the ABEL functional simulators PLASIM and JED SIM you can select the following trace options for producing si
5. k ORDER d0 1 dl 1 Inputs outl out2 1 0ut3 out4 Outputs VECTORS 0 1 HL HH 0 1 Input values 1 0 HL HL L H Output values HL HH HH LL LL LH HL HL HL HH HH LL rororo FPRPOORER Example 3 Testing Registered Functions A simple 4 bit Binary Counter with reset function is used to illustrate the test vector implementation for a registered function ABEL File COUNT4 ABL module COUNT4 inputs clk pin 1 reset pin 2 outputs q0 g1 g2 q3 pin 14 15 16 17 ISTYPE REG Constant Declarations to be used in the TEST VECTORS section Cre SG 1 0 C Low High Low Clock pulse Equations 4 Bit Binary Counter equations using D type registers q0 d q0 ql d ql amp q0 ql amp q0 q2 d q2 amp ql amp q0 tf q2 amp ql f q2 amp q0 q3 d q3 amp q2 amp qgl1 amp q0 q3 amp q2 q3 amp ql q3 amp q0 q3 q2 ql q0 ar reset resets the counter q3 q2 q1 q0 clk clk clocks the counter Test vectors 4 Bit Counter clk reset q3 q2 q1 q0 Cy 1 L L L Lj resets the counter C 0 ud L L L H 1 C 0 E L L H Lj 2 Cy 0 Lp A Hee ONS C 0 id hop Hey Rho dog 4 Coy 0 L5 Hry Gage ie SS Cra 0 Lt egal Hope Hope ele RONG Gu 0 H H H 7 C 0 E iL L Ly 8 end AIMEL CUPL Files AIMEL COUNT4 PLD Name COUNT4 Partno XXXXX Date 3 27 95 Designer Atmel Device V750
6. use U and D on the clock pins whenever possible If you use a 1 then a 0 or a 0 then a 1 to clock your registers then expect trouble Different programmers treat test vectors differently Some go from pin to pin and assert 0 s and 1 s in a sequential manner then look for C s K s U s and D s and assert them from pin to pin If O s and 1 s are used your registers can be clocked before the inputs to the registers even have a chance to change and therefore the programmers report a failure to pass vector message Other programmers assert 0 s and 1 s almost simultaneously and then go through the test vector and look for C s K s U s and D s and then assert them almost simultaneously This could also give you a failure if you use 0 s and 1 s to clock clock and data will be asserted almost simultaneously still no guarantee which will come first the set up time is not Since your satisfied thus the programmers report a test vector failure Keep in mind that the programmers do functional tests not timing tests It won t catch your timing errors in your design for you The test vectors simply verify your design s functionality but that alone should reduce the time spent on the test bench Equations O23 ck 13 O23 re I6 023 00 1 B23 ck 13 B23 re I6 6 CMOS PLD _ r in O21 combinatorial function 023 D Il I2 B23 D I4 amp 023 0 I5 amp 023 0 022 D I7 O22 ck
7. 0 in a set called count The bold words indicate either additions or changes to the original counter design ABEL File COUNT4A ABL module COUNT4A Pin declarations same as COUNT4 ABL count q3 q2 ql q0 Used in the TEST VECTORS section Equations Design equations same as COUNT4 ABL RADIX n where n is 2 binary 8 octal 10 decimal default or 16 hexadecimal The RADIX compiler directive allows the base numbering system to be changed The default numbering system is 10 Test vectors 4 Bit Counter clk reset count Cuz 1 0 reset the counter C 5 54 l y 0 ES 2 3 C7 0 3 x CG 0 4 Cy 0 Di cf C y 0 6 3 Gy 0 E ES Cx 0 8 end CUPL Files COUNTAA PLD Name COUNT4A Design desciptions and equations same as COUNT4 PLD x field count q3 0 AIMEL i AIMEL COUNTAA SI Name COUNT4A Partno XXXXX Date 3 27 95 Designer Atmel Device V750 BORK KK KKK Ck kk IK KK Kk RR AK kk kk Kk k k k k ke kk k ke kk k k k k I koe ke X ek UA Simulation Input File for Register Example RR KKK KKK IK KK KK IK RK AR Kk kk Kk k kk k kk k k k k ke k k k kk k kk ke ke ek Base decimal Selection octal decimal and hexadecimal This syntax sets the base numbering system Use single quotes for inputs and double quotes for outputs Eg Inputs 9 Outputs 9 If the quotes single or double are not used the default numbering system is bi
8. 4A PLD 2 COUNT4B SI Name COUNT4B Partno XXXXX Date 3 27 95 Designer Atmel Device V750 RR KKK KKK I KKK IK IKK A AA k k k k k k k k k k k A k k k k k k k k k k I ke ke ke ek Simulation Input File for Register Example BORK IKK KK I KK IK I Kk Ck I KKK AA IKK AR k k k ke kk k k k k k kk k I ke ke ek Base decimal Selection octal decimal and hexadecimal This syntax sets the base numbering system Use single quotes for inputs and double quotes for outputs Eg Inputs 9 Outputs 9 r If the quotes single or double are not used the default numbering system is binary i e 0 or 1 Ef ORDER clk 1 reset 1 Inputs count Outputs VECTORS pd SON c 0 1 SREPEAT 13 Repeat 13 times C D muet G0 NS Last count C0 NO Count roll back to zero AIMEL AIMEL Example 6 Simulating Buried Nodes In addition to output pins ABEL and CUPL allow buried nodes combinatorial or registered to be simulated Simulating the buried logic allows the designers to debug the complex logic and state machines in their PLD designs There are no special requirements for simulating the buried nodes except that it is important to note that the buried node vectors cannot be functionally verified on a programmer This means that the expected output for the buried nodes will not appear on the JEDEC file If verifying the functionality of the buried nodes on the programmer is important
9. I8 amp I9 O21 I9 amp I10 test vectors I1 12 13 14 15 1I Qu Uy Oy Op 707 r r C 1 U r K D r U 6 1 0 0 0 0 0 0 Q2 AE 49 0E op jp TOL E REX HH OLOO os test vectors I7 I18 19 110 022 021 Dep Og 7420 7 E 1 0 D 0 0 0 l2 alps UG pale Se ble St ub 0 Le Dy Ae Pe ee 0 Ol lye Oy d emot al end FPRPOrRRON reset clock clock clock clock clock 023 023 B23 B23 023 first then B23 Recommendation first then O23 Recommendation Recommendation I9 is clock pin used in product term and Recommendation 1 2 Recommendation 1 2 2 Example 2 Testing Combinatorial Functions The following GATES example shows how the test vectors are implemented for simple combinatorial functions such as OR AND XOR and INVERT logic gates ABEL File GATES ABL module GATES title Simple examples Inputs d0 dl pin 1 2 Outputs Outl pin 14 ISTYPE Out2 pin 15 ISTYPE Out3 pin 16 ISTYPE Out4 pin 17 ISTYPE Constant Declarations to X Don t Care state 1 Logic High 0 Logic Low EQUATIONS Outl dO dl Out2 d0 amp dl Out3 d0 dl Out4 d0 COM COM COM COM be used in the TEST VECTORS that can be used for inputs OR function AND function XOR function INVERT function AIMEL U and D send logic 1 and 0 respecti
10. RES Pin 4 7 DO 3 Outputs Pin 23 Ser_out This output is the Q0 bit Q Nodes used the ATV750 buried nodes Q0 Ser out Pinnode 26 28 Q1 3 field Qnodes Q3 0 Q nodes field Qshift b 0 03 1 Shifting input always shift 0 into Q3 field Din BS Data input Qnodes ck CLK Clock for the Shift Register Qnodes ar RES Reset for the Shift Register Qnodes d Load amp Din Load in the data Load amp Qshift Shifts the data SHIFT4 SI Name SHIFT4 Partno XXXXX Date 3 27 95 Designer PLD Expert Company Atmel Assembly None Location None Device V750 BRK KK KKK I KK IK IR IK RR KR k k k RAR k k k k IR k k k k k k k I ke ke ke ek ke Simulation Input File for Buried Node Example RR KKK KKK I KK IK IK Kk KC IK AR kk kk Kk k k k k ke kk k ke kk k k k k I ke ke ke ek ORDER CLK 1 RES 1 Load 1 Din 22 Inputs Qnodes 2 Buried Nodes Ser out QO0 Ser out Output VECTORS 000 XXXX LLLL L C 0 1 1110 HHHL L Loads Data Din C00 XXXX LHHH H C 0 0 XXXX LLHH H COO XXXX LLLH H C 0 0 XXXX LLLL L C01 0101 LHLH H Loads Data Din 010 XXXX LLLL L Resets Registers Example 7 Testing Bi Directional I O pins The following example illustrates the use of test vectors to verify bi directional I O pins It is important to specify your bi directional I O vectors in the follo
11. SI For instance if you have a CUPL source file called GATES PLD then your test vector specification file will be called GATES SI Simulation Trace Options Like the ABEL simulators the CUPL simulator CSIM has several simulation trace options that you can select to control the simulation outputs The CSIM trace options is set by the TRACE directive in the SI file and it ranges from Trace Levels 0 to 4 The default option is Level 0 that prints only the resulting simulation results The Trace Lev els 1 through 4 turns on the intermediate simulation results for each vector These levels are specifically used for debugging your design For example Trace Level 1 prints the intermediate results for any vector that requires more than one evaluation pass to become stable and Level 2 shows register values when the clock is 0 1 and 0 again for each vector Please refer to your CUPL manual for more detailed infor mation on the CUPL CSIM simulator and its trace options Types of Test Vector Signals In accordance with the standards defined by the JEDEC STANDARD No 3 C Table 1 shows some of the most commonly used JEDEC test vector values when testing a PLD device The table also shows the ABEL and CUPL test vector values that correspond to each JEDEC vector Test Vector Issues on the Programming Hardware When entering test vectors in your design it is very impor tant to use the proper vector values If incorrect v
12. Tips on Using Test Vectors for Atmel PLDs Test vectors are a useful method for ver ifying designs implemented in Programmable Logic Devices PLDs Test vectors allow the designer to verify test and debug a PLD design for proper functionality before it is used in the sys tem Most PLD development software tools and programmers offer test vector capabilities so that PLDs can be func tionally simulated via software and tested during the programming process This application note describes the use of test vectors in the ABEL and CUPL HDLs Hardware Description Lan guages In addition some pitfalls and precautions on the usage of test vectors will be discussed When simulating your design using test vectors in the Atmel ABEL or Atmel CUPL development tool it is important to note that the test vec tors may not simulate the actual timing requirements of your design The ABEL or CUPL test vectors are only used to simulate and test the logic of your PLD design Note 1 Atmel ABEL or Data l O ABEL Version 4 x or above and Atmel CUPL or Logical Devices CUPL Version 4 4c or above To illustrate the usage of the test vectors in ABEL and CUPL HDLs the following examples are included in this application note Example 1 Example using the D U C and K vector values Example 2 Testing Combinatorial Functions Example 3 Testing Registered Functions Example 4 Using Sets for a group of signals in Test
13. als with fast edge rate These drivers are usually dedicated for driv ing pins with the D U C or K clock values For the 0 and 1 values normal input drivers with slow edge rate are used see Figure 1 Note 1 The JEDEC standard specifies that the 0 and 1 vectors must use a fine current drive since the pro grammer must allow the applied input conditions to be overridden by bidirectional I O pins Note that there are some PLD programmers that have clock or high speed drivers which are hard wired to some dedicated pins only usually pin 1 of each pack age type So even when the clock values such as D U C and K are used test vectors may still fail because slow drivers are used This is especially important for the Atmel V Series CPLDs because the architectures allow any input or I O pin or an AND function to be configured as clock for the registers Many of today s PLD programmers either have a clock or high speed driver dedicated to each pin or allow limited number of high speed drivers to be routed to any pin For driving clocks that are gated in a clock product term the C or K value can still be used as long as the clock pin is not used in other combinatorial functions see Rec ommendation 8 t Recommendation 2 Use the D or U value if your design uses the rising and falling edges of the same clock pin See Example 1 in the Ap
14. ector values are used the vectors may fail on the PLD program mer even though they passed the ABEL or CUPL functional simulation For instance if you use 0 and 1 vector val ues to drive the clock pin of your design the vectors will probably fail on the programmer even though they passed the ABEL or CUPL simulation see Recommendation 1 In addition to improper test vector usage test vector fail ures on PLD programmers may also be a result of the programmer s hardware characteristics The programming hardware dictates the sequence in which inputs in a given vector are applied to the device For example the program mer may assert 0 and 1 input vectors in a sequential manner from the first pin to the last pin or asserts the input vectors almost simultaneously In addition the programmer also sets the transition or edge rate of the input signals Most of today s PLD programmers can drive both slow and fast edge signals because they contain both normal and high speed or clock input drivers Figure 1 shows the typical waveforms of the input signals applied by a programmer Table 1 ABEL and CUPL Test Vector Values Vector In ABEL Test CUPL Test JEDEC File Description Vector Value Vector Value 0 Drive Pin Low 0 0 1 Drive Pin Low 1 1 C Drive Pin Low High Low C C K Drive Pin High Low High Fast Transition K K U Drive Pin High Fast Transition U Not Used D Drive Pin
15. g 3 Setthe I O pins with values L and H 0 and 1 for ABEL to verify the output signals AIMEL AIMEL Appendix Section Examples on using Test Vectors in Atmel PLDs The following examples discuss the use of test vectors in several different logic functions If applicable the test vector examples for each logic function are illustrated in both ABEL and CUPL HDL formats Example 1 Example using the D U C and K vector values The following ABEL example illustrates the usage of the D U C and K clock values Note that since the D and U values are not supported by CUPL the corresponding CUPL example is not shown For illustration on the C and K clock vectors usage in CUPL please refer to Example 3 DUCK ABL module duck title When to use D U C and K ATMEL Corporation DUCK device P750 I1 12 13 14 15 pin 1 2 3 4 5 I6 17 18 19 110 1I11 113 pin 6 7 8 9 10 11 13 o 19 020 021 022 023 14 015 016 017 018 pin pin 19 20 21 22 23 14 15 16 17 18 o B14 B15 B16 B17 B1 B19 B20 B21 B22 B23 node 26 27 28 29 30 node 31 32 33 34 35 BUFFER REG 023 IsType 022 IsType BUFFER REG X 2 D U C K dS vie pie Digne Ug e esl y Writing Test Vectors for a Asynchronous Device If you want a complete clock cycle use C and K on your clock pins whenever possible If you want to see what happens after one clock edge
16. injected into the device do not use the F value because some programmers may actually float the pins We recommend that all unused device s inputs and l O s to be terminated Us Recommendation 5 Use 2 to 3 vector cycles for testing bi directional I O s See Example 7 in Appendix When testing bi directional I O pins it is important to spec ify the vectors in a proper manner For instance if you are testing an I O pin as an input in which the I O pin was orig inally configured as an output always ensure that the I O pins are in high impedance state before driving them as inputs When testing the I O pin as an input from an output mode 1 First set the I O pin to high impedance by disabling the output enable Use the Z value for the I O pin 2 Then drive the I O pin as an input If a single vector is used to disable and drive the I O pins at the same time these I O pins may experience signal or bus contention conditions i e the programmer is driving sig nals into the device s pins and at the same time the device s output pins are driving when the vector is being exercised on the programmer This signal contention condi tion can sometimes cause your vectors to fail on the programmer and may possibly cause damage to the I O pins When testing the I O pin as an output from an input mode 1 Setthe I O pin to the X don t care value 2 Enable the output enable so that the I O pin is drivin
17. most all programmers do not drive the pins with vector X Even if ENA 0 IOl output disabled it is recommended to always use vector X on the input side of all bi directional I Os for the first vector because the programmer may enable the output while setting up for the vector testing 1 des X Alves ip deste cb io IO2 output follows the IOl because of the combinatorial feedback 0 0 X eae SEE Disable the IOl output but keep the vector X on input IOl1 to ensure that it is not driven as input 0 5 0 Tee a ita Za age us It is safe to drive IOl as an input now 0 0 Jis dens li end CUPL Files BIDIR PLD Name BIDIR Partno XXXXX Date 3 1 955 Designer Atmel Device V750 RRR IKK KK I kk kk kk Kk Ck CK Ck KC Kk Ck Kk Ck CK k kk Kk Ck kk ck k k A IR ko kk ke k k k ke ke This example shows how to define and use a x a bi directional I O pin in CUPL f RRR KK KKK IK KK KA CK kk Kk k k Kk k Kk k k k k k IRA kk kk kk oko ko kk ke kk ke ke ke Inputs Pin 2 ENA Pin 3 Dl Outputs Pin 22 I01 Pin 21 102 Logic Equations IOl D1 IOl oe ENA IOl output is enabled when ENA 1 IO2 I01 10 IOl is used as in input here BIDIR SI Name BIDIR Partno XXXXX Date 3 37955 Designer Atmel Device V750 RRR KK KKK Ck CkCk Kk Ck I KK KR CK Ck k Ck k kk kk ke k k ko ke kk ke ke ke ke ke k k Simulation Input file for Bi directional I O ui i Exam
18. mulation outputs Trace Formats The simulation output formats available in ABEL include the Pins Waveform Table and Macrocell for mats Note that this display option is detailed and should be used in conjunction with the Signal option to reduce the size of the output report The default option is Table format Trace Outputs This option selects the simulation trace level desired such as Brief Detailed or Clock option The default is the Brief option The Detailed and Clock options are useful for debugging complex logic circuits For instance the Clock option generates a simulation report that shows register values when the clock is 0 1 and 0 again for each vector This option is useful with the Macrocell trace format for debugging asynchronous circuits Other trace options available in ABEL include Trace Signal Trace Last Vector Trace First Vector Trace Powerup Trace X Value Trace Z Value and Trace tmv options For more information on the ABEL simulators and the trace options please refer to your ABEL User manual Simulating In CUPL With CUPL a PLD design is simulated via the CSIM CSIM EXE functional simulator This simulator simulates the logic equations of your design before the logic is mapped into your selected target PLD Unlike ABEL the test vectors for the CUPL are not specified within the source file All CUPL test vectors must be specified in a test specification source file with file extension
19. nary i e 0 or 1 ORDER clk 1 reset 1 I inputs 7 count Outputs VECTORS Go vo p ONUS pep Gp win c o vg q ges goce gogo c 0 wes Example 5 Repeating Vectors with the ABEL REPEAT or CUPL REPEAT syntax Both the ABEL and CUPL HDLs have a compiler directive that causes a vector to be repeated a specified number of times This REPEAT directive is particularly useful for generating sets of test vectors especially vectors for testing counters For more detailed information on the syntax of the REPEAT compiler directive please refer to your ABEL or CUPL manual The 4 bit Binary Counter design from Example 4 was modified further to use the REPEAT syntax The REPEAT syntax reduces the effort of generating the vectors for the counter design Note that the modifications to Example 4 are indicated by the bold words ABEL File COUNT4B ABL module COUNT4B Design descriptions and equations same as COUNT4A ABL v v CONST CNT 1 Initialize the Constant CNT Test vectors 4 Bit Counter clk reset count C E eem 0 reset the counter C D epe l1 REAPEAT 13 Repeat vector for 13 times CONST CNT CNT 1 Increment CNT LL Qa des CNT The compiler automatically inserts the CNT value into the vector m s Ov np T5 ap Last count t p Q 3 Count roll back to zero end CUPL Files COUNTAB PLD Name COUNT4B Design desciptions and equations same as COUNT
20. pendix Section In some designs you may be required to use the rising and falling clock edges to completely test the logic With these designs use the D or U values on the clock pins when ever possible t Recommendation 3 Use the D or U value for generated clocks that are implemented in product term clock functions and are used in separate combinatorial functions See Example 1 in the Appendix Section If a clock pin is used to drive both a product term clock function and a separate combinatorial function then it is recommended to use D or U value on the clock pin As mentioned in Recommendation 1 the PLD programmer applies the D and U values after all the 0 and 1 val ues are implemented If the clock pin is used in a separate combinatorial function the logic values 0 and 1 are also asserted by the D and U values respectively Even though these logic values are applied a little later than the signals implemented via the 0 and 1 values there is still sufficient time typically in ms for most programmers for the combinatorial logic to settle out before the programmer senses the output signal For this type of design the C or K clock vector is not suitable because the clock pulse may return to the inactive level LOW or HIGH before the programmer senses the output C Recommendation 4 Do not use the F vector on unused inputs and I O s To reduce noise being
21. ple BORK KK KKK Ck CkCk Kk e Kk KC KK A Kk Ck Kk Ck kk kk ke k k ko ke ke ke ke ke ke ke e ke x x f ORDER ENA 1 D1 22 Inputs IO1 2 1 102 Outputs VECTORS 00 ZX Disable the I O output pin on the first vector to ensure no signal contentions on the programmer during test vector setup TLO iB IOl output is enabled and can be tested now l l 2HzH IO2 follows the IOl because of combinatorial feedback 00 ZX IOl output is disabled Always use a separate vector to disable the I O pin first 00 1H IOl is now used as an input 0 0 0L IOl is now used as an input Summary The ABEL and CUPL test vectors are useful for checking the logic of your complex PLD designs through software simula tion To further verify your designs the test vectors can be used on the PLD programming hardware to test the actual device operation To achieve consistent results between the software simulations and vector testing implemented on the programmers it is recommended that you use appropriate input and output vector values Remember that both software simulation and programmer vector testing provide only functional testing of your design They are not intended to verify tim ing requirements of your designs AIMEL B AMEL T A Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose CA 95131 TEL 408 441 0311 FAX 408 487 2600 Europe Atmel U K Ltd Coliseum Business Centre River
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24. then these nodes can be buff ered to the unused I O pins of the device t f a fitter is used for the Atmel ABEL or Data l O s ABEL tool the fitter will optimize the design by choosing the reversed polarity of the combinatorial nodes indicated by the Polarity is INVERT message in the fitter output file FIT To com pensate for the reversed polarity the fitter inverts all the references to the combinatorial nodes Hence the resulting logic at the output pins is equivalent to the original equations If these buried combinatorial nodes are simulated via the Simu late Fitted Design or Simulate JEDEC command only the vectors for these nodes will need to be inverted to reflect the change in polarity of the buried nodes A 4 Bit Loadable Shift Register design is used to illustrate the buried node simulation ABEL File SHIFT4 ABL MODULE shift4 TITLE 4 Bit Loadable Shift Register Block Diagram Load ure i i gt Ser out DO D3 eee When Load is TRUE D0 D3 data is loaded into the shift register Once Load is FALSE the data is shifted to the right D3 DO A O is loaded into the D3 during the shifting process The last bit of the shift register Ser out shifts the data out shift4 device p750 Inputs CLK pin 1 Load pin 2 RES pin 3 DO D1 D2 D3 pin 4 5 6 7 Outputs Ser out pin 23 istype buffer reg d This output is the Q0 bit Q Nodes Q0 Ser 01 02 03 Onodes Qshift
25. use 0 and 1 input vectors to drive the clock pin of your design the vectors may pass the ABEL or CUPL functional simulation but these same vectors may fail when they are applied on the programmer The two problems associated with using 0 and 1 input values for clocking the registers are 1 The input data to the register may not set up prior to the clock signal With all PLD programmers the 0 and 1 input values are applied to the device s pin before the D U C or K input This implemen tation ensures that the input data to the registers are set up prior to the registers receiving the clock signal If 0 and 1 input values are used for clock ing then the registers could get the clock signal before the input data is set up This would cause incorrect input signals to be set up and clocked into the register resulting in a test vector failure on the programmer Note that you can eliminate the input data set up prob lem by adding a wait state vector prior to each 0 and 1 edge transition However using 0 and 1 input vectors to drive the clock for the registers is still not rec ommended due the possibility of the slow edge rate input drivers being used by the programmer 2 The slow transitions of the clock signals that may cause the input data to the register to be double clocked In most PLD programmers there are clock or high speed drivers that can drive input sign
26. vely to O21 combinatorial function O21 passed Recommendation 43 Showing how test vectors are used for combinatorial outputs section X H L or outputs AIMEL TEST VECTORS Test AND OR Functions d0 d1 Outl Out2 Pe Oey SOP el L P hd 0 is substituted for L Len zd H A L J 1 is substituted for H E 0 E NT os el H p 4 mr H H L TEST VECTORS Test XOR INVERT Functions CL od0 di Outs Oaks 4 0 0 384m L H 0p 1 0 Lib H X L0 voc Te H X eg su pecu L li L ABEL allows several test vector statements to be used in a module Each test vector group is compiled individually The compiler will combine vectors from all groups to create a composite test vector set when it creates the JEDEC file end CUPL Files GATES PLD Name GATES Partno XXXXX Date 3 27 95 Designer Atmel Device V750 Inputs Pin 1 d0 Pin 2 dl Outputs Pin 14 17 out1 4 Logic Equations outl dO dl OR Function out2 d0 amp dl AND Function out3 d0 dl XOR Function out4 d0 INVERT Function GATES SI Name GATES Partno XXXXX Date 3 27 95 Designer Atmel Device V750 BRK RK KKK I KK IK IK IK RK KA IK RA KR k k k k IR k k k k k k k I ke ke ke IK Simulation Input File for Gates Example aA RR KKK KKK e KK e e e KK IK KR IK IKK k A k k k k k IR k k k k k k k I k k k k kk
27. wing manner When testing the I O pin as an input from an output mode 1 First set the I O pin to high impedance by disabling the output enable Use the Z value for the I O pin 2 Then drive the I O pin as an input When testing the I O pin as an output from an input mode 1 Setthe I O pin to the X don t care value 2 Enable the output enable so that the I O pin is driving 3 Setthe I O pins with values L and H 0 and 1 for ABEL to verify the output signals ABEL File BIDIR ABL module BIDIR Title This example shows how to test a bi directional I O pin in ABEL Inputs ENA pin 2 Output enable D1 pin 3 AIMEL v AIMEL Outputs IOl pin 22 istype com This pin is being used bi directionally IO2 pin 21 istype com This pin is defined as an output TO1l and IO2 pins could also be defined as registered outputs Declarations X Z H L X 2 1 0 Z High Impedance or Tri state Equations IOl Dl I O pin IOl as an output IOl oe ENA When ENA 1 output IOl is enabled When ENA 0 output IOl is tristated and can be used as input IO2 IOL IOl is used as an input for this output test vectors Bi directional I O test ENA D1 IO1 101 102 IO1 must be specified on both the input and output sides EU y 0 Ke eT Wae Os IOl output is enabled it is important to use X don t care for IOl on the input side when IO1 output is enabled Al
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