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1. Multi touch LCD Module User Manual 01010101010101010010101011101010010101001001010101010100101010101010101010101001011010101101100010111101001 1010 101010101000101010101010101010100101010111010100101010010010101010101001010101010101010101010010110101011011000101111010011010 1010101010001010101010101010101001010101110101001010100100101010101010010101010101010101010100101101010110 1010101010001010101010101010101001010101110101001010100100101010101010010101010101010101016 101010101000101010101010101010100101010111010100101010010010101010101001010101010101010101010010110101011011000101111010011010 101010101000101010101010101010100101010111010100101010010010101010101001010101010101010101010010110101011011000101111010011010 101010101000101010101010101010100101010111010100101010010010101010101001010101010101010101010010110101011011000101111010011010 www terasic com Copyright 2003 2011 Terasic Technologies Inc All Rights Reserved CONTENTS cato ccnl CHAPTER 1 INTO 3 LEADON Waid bom ore DIURNO et 3 KU T E EEOC aea 4 1 3 Setup License for Multi touch 5 IN e doll e 6 T T mm 7 riu RR m 7 CHAPTER 2 ARCHITECTURE OF MTL oisein ier 8 PEE Kc
2. Wh Figure 1 2 MTL Power Adapter MTL User Manual 4 www terasic com www terasic com 1 3 Setup License for Terasic Multi touch IP To utilize multi touch panel a Quartus II project a Terasic Multi Touch is required After license file for Quartus II 15 installed there 15 one more license file needed to implement Terasic s Multi touch IP Error messages will be displayed if the license file is not added before compiling projects using Terasic Multi touch IP The license file is located at MTL System multi touch dat There are two ways to install the License The first one is to add the license file license multi touch dat to the licensed file listed Quartus II as shown in Figure 1 3 Options Category i General License Setup Tool Options Fonts Internet Connectivity License File 180089192 168 1 56 Libraries Use LM LICEMSE FILE variable License Setup T Preferred Text Editor Current license Processing Web License Update Tooltip Settings License Type Full version G E Messages Suppression cep De Begin 30 day Grace Period Colors Host ID Type ID Host ID Value 0018 3 326 Wait for Floating licenses Figure 1 3 License Setup The second way 15 to add license content to the existing license f
3. 0 Output 3 3 V LVTTL 24 MTL_G 7 Output 3 3 V LVTTL 25 MIL B 1 Output 3 3 V LVTTL 26 MTL 2 Output 3 3 V LVTTL 21 3 3 3 V LVTTL 28 MTL 4 Output 3 3 V LVTTL 29 30 5 31 MTL_B 5 Output 3 3 V LVTTL 32 MTL_B 6 Output 3 3 V LVTTL 33 MIL B 7 Output 3 3 V LVTTL 34 35 MTL HSD Output 3 3 V LVTTL 36 MTL VSD Output 3 3 V LVTTL 37 MTL TOUCH I2C SCL Output 3 3 V LVTTL 38 MTL TOUCH SDA Inout 3 3 V LVTTL 39 MTL TOUCH INT n Input 3 3 V LVTTL 40 MTL User Manual 14 www terasic com www terasic com 3 2 Using LCD The LCD features 800x480 pixel resolution and runs a 33 MHz pixel rate No configuration is required to drive the LCD The timing specification 1s defined as in the Table 3 2 Table 3 2 LCD Timing Item Typical Value Unit Pixel Rate 33 MHz Horizontal Period 1056 Pixel Horizontal Pulse Width 30 Pixel Horizontal Back Porch 16 Pixel Horizontal Front Porch 210 Pixel Horizontal Valid 800 Pixel Vertical Period 525 Line Vertical Pulse Width 13 Line Vertical Back Porch 10 Line Vertical Front Porch 22 Line Vertical Valid 480 Line 3 3 Using Terasic Multi touch IP Terasic Multi touch IP is provided for developers to retrieve user inputs including multi touch gestures and single touch The file name of this IP is 12 touch config and it is encrypted To compile projects with the IP users need to install the IP license first For license installation please re
4. 5 1 shows the Graphical User Interface GUI of the Painter Demo The GUI is classified into four separate areas Painting Area Gesture Indicator Clear Button and Color Palette Users can select a pen color from the color palette and start painting in the paint area If a gesture 15 detected the associated gesture symbol 16 shown in the gesture area To clear the painting area click the Clear button Painting Area Gesture Clear Color Palette Indicator Figure 5 1 GUI of Painter Demo Terasic MTL User Manual 24 www terasic com www terasic com m efejelek 2 Figure 5 2 Single finger Painting Figure 5 3 displays the counter clockwise rotation gesture Figure 5 3 Counter clockwise Rotation Gesture Figure 5 4 shows the zoom in gesture Figure 5 4 Zoom in Gesture 5 2 System Description For LCD display processing the reference design 15 developed based on 5 Video and Image Processing Suite VIP The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content 15 drawn by the NIOS II processor according to user input Terasic MTL User Manual 25 www terasic com www terasic com For multi touch processing Terasic Memory Mapped IP is used to retrieve the user input including multi touch gestures and single touch coordinates For IP usage details please refer to the Chapter Three in this
5. 8 or 8 2 Multi touch LCD Mod le MTL 9 P2 BIST 62 EET 11 TU 11 3 E E E A 13 Definiton Of 2x20 GPIO C On 13 15 3 3 Using Terasic D RT 15 4 EPHOTO 18 AA Operation Descrip Oi 18 4 2 Block Diagram of the ePhoto 19 4 3 Loading Photos into FLASH PPP 20 4 4 Demonstration for Terasic DE2 115 FPGA Board 21 43 Caston Display 23 MTL User Manual 1 www terasic com www terasic com 5 PAINTER 5 24 S T OBOEHUON 24 Dec 25 5 3 Demonstration for Terasic DE2 115 FPGA 26 5 4 Demons tration Source Code P HH 2 CHAPTER 6 Pug dL X 7 X 28 MTR 1S ete m 28 UAE 28 Terasic MTL User Manual 2 www terasic com www teresic com Chapter 1 Introduction The Terasic Multi
6. document Note the IP is encrypted so the license should be installed before compiling the Quartus II project Figure 5 5 shows the system generic block diagram of demonstration reference design FPGA SOPC Avalon Interconnect Fabric Avalon Memory Mapped Bus Avalon Streaming Bus Figure 5 5 System Block Diagram 5 3 Demonstration for Terasic DE2 115 FPGA Board This section shows how to setup the painter demo the Terasic DE2 115 FPGA Board For other Terasic FPGA boards the setup procedures are similar Hardware Setup Terasic MTL User Manual 26 www terasic com www terasic co m Hees A RANA Aah Figure 5 6 Hardware Setup with DE2 115 Execute Demonstration Please follow the procedures below to setup the demonstration Make sure the DE2 115 is powered off Mount the ITG adapter onto the 2x20 GPIO 0 expansion header of the DE2 115 Connect the DE2 115 USB Blaster USB B port to the PC USB Port with a USB Cable Power on the DE2 115 FPGA Development Board Make sure Quartus II 10 1 and NIOS II 10 1 are installed on your system Copy the folder Demonstrations SOPC DE2 115 SOPC PAINTER demo batch in the MTL System CD onto your system and execute test bat 7 Now you should see the painter GUI on the LCD p a Ue Note Please attach the 5V USB power adapter when using the DE2 FPGA Development Board 5 4 Demonstration Source Code The source code location
7. touch LCD Module MTL is an all purpose capacitive touch screen for FPGA applications and provides multi touch gesture and single touch support An IDE cable with an IDE to GPIO ITG adapter is used to interface with various Terasic FPGA development boards through a 2x20 GPIO interface on the MTL The kit contains complete reference designs and source code for an ePhoto demonstration and Painter application This chapter provides the key information about the kit 1 1 About the Package The MTL kit comes with the following contents e Multi touch LCD Module IDE Cable with Adapter MTL System CD ROM 5V Power Supply e Four Silicon Footstands The system CD contains technical documents of the MTL kit which includes component datasheets demonstrations schematic cable and user manual Figure 1 1 shows the contents of MTL kit MTL User Manual 3 www terasic com rasic com Multi touch LCD Module IDE Cable with ITG Adapter MTL System CD ROM 6 5V Power Supply G Four Silicon Footstands Figure 1 1 Contents of MTL Kit 1 2 Power Adapter for MTL Figure 1 2 shows the power adapter for the MTL Due to the fact that the LCD panel in the MTL consumes more power than some boards can provide a dedicated power adapter for MTL 15 required Note the power adapter 1s not necessary for the DE2 115 FPGA board amp IE pRO 2 4 gt F Ta M5 TE 14110
8. DE cable Plug the adapter into the 1 0 header of the FPGA development kit from MTL before turning on Important Plug the MTL power adaptor into the power connector of MTL unless the DE2 115 FPGA board is used Figure 4 4 ePhoto Configuration Setup Terasic MTL User Manual 21 www terasic com www teresic com Execute Demonstration Procedure to execute demonstration Make sure the DE2 115 is powered off Mount the ITG adapter onto the 2x20 GPIO 0 expansion header of the DE2 115 Connect the DE2 115 USB Blaster USB port to the PC USB Port with a USB Cable Power on the DE2 115 FPGA Development Board Make sure Quartus II 10 1 and NIOS II 10 1 are installed in your system If you haven t already store pictures into the flash memory For more detailed instructions please refer to section 4 5 Loading Photos into FLASH 7 Copy the folder Demonstrations RTL DE2_115_EPHOTO demo_batch in the MTL System CD onto your system and execute test bat 8 A photo should be displayed in the LCD as shown in Figure 4 5 9 Slide left or right with one finger on the touch panel to display the previous and next photos respectively 10 Slide with two fingers in the opposite direction to zoom in on the picture and pinch two fingers together to zoom the picture out Note Please attach the 5V USB power adapter when using the DE2 FPGA Development Board Figure 4 5 Photo Display Table 4 2 lists the demons
9. control signals 3 1 Pin Definition of 2x20 GPIO Connector The 2x20 GPIO female connector 1s designed to directly connect to the 2x20 GPIO male connector on the Terasic FPGA development boards Figure 3 1 shows the signal names of the 2x20 GPIO from the ITG adapter J1 2x20 header female 6 DCLK eo RO R1 R2 R3 7 R4 R5 D R6 VCC5 1180812 GND R7 GO G1 G2 G3 G4 19 20 G5 Z A G6 BO G7 B1 B f B2 B3 9 4 2930 GND B5 518832 B6 BL HSD VSD I2CSCL os I2CSDA INT M Figure 3 1 2x20 GPIO Table 3 1 shows the recommended pin assignments for the 2x20 GPIO pins in Quartus II MTL User Manual 13 www terasic com www terasic com Table 3 1 Recommended Pin Assignments of 2x20 GPIO in Quartus II Pin Numbers Pin Name Direction IO Standard 1 2 MTL DCLK Output 3 3 V LVTTL 3 4 MTL RI 06 Output 3 3 V LVTTL 5 MIL R 1 Output 3 3 V LVTTL 6 MTL R 2 Output 3 3 V LVTTL MTL_R 3 Output 3 3 V LVTTL 8 MTL_R 4 Output 3 3 V LVTTL 9 MTL 5 Output 3 3 V LVTTL 10 MTL_R 6 Output 3 3 V LVTTL 11 s _ 12 _ 13 _ 3 3 V LVTTL 14 MTL G 0 Output 3 3 V LVTTL 15 MTL_G 1 Output 3 3 V LVTTL 16 MTL_G 2 Output 3 3 V LVTTL 17 MTL_G 3 Output 3 3 V LVTTL 18 MTL_G 4 Output 3 3 V LVTTL 19 20 21 G 5 3 3 V LVTTL 22 MTL G 6 Output 3 3 V LVTTL 23 MTL_B
10. e LCD display When users touch MTL screen 12 Touch Config will receive an interrupt signal from the touch screen When an interrupt is detected 2 Touch Config will read touch information from the touch panel and assert the oREADY signal When Touch Controller detects a rising signal of oREADY it will read touch information and determine the input which may be a gesture or a single point touch If a west or east gesture is detected it will change the reading port address of the desired active photo in the SDRAM Controller If a zoom in or zoom out gesture is detected it will change the zooming factor in Zoom For multi touch gesture processing a Terasic Memory Mapped IP 12 Touch Config is used to retrieve the touch information For IP usage details please refer to the Chapter 3 1n this document Note the IP 15 encrypted so the license should be installed before compiling the Quartus II project MTL User Manual 19 www terasic com resic com SDRAM LCD Display Figure 4 3 The Block Diagram of the ePhoto Demonstration 4 3 Loading Photos into FLASH Before executing the demonstration users have to utilize the Control Panel software to load photos into the FLASH of the FPGA board first The Control Panel software is available in the CD of the FPGA development kit Table 4 1 shows the respective Control Panel names and bitstreams for various FPGA development boards Table 4 1 C
11. erasic FPGA boards TilasiC Terasic MTL User Manual 10 www terasic com www Ceresio EEE 2 4 IDE Cable The connection cable included is a standard IDE cable However to achieve the best performance we strongly recommend users use the bundled IDE cable only Third party IDE cables may cause the MTL to malfunction or even damage the module The IDE cable is shown in Figure 2 5 Figure 2 5 IDE cable 2 5 ITG Adapter The IDE to GPIO adapter is designed to remap IDE pins to GPIO pins Component and Layout Figure 2 6 and Figure 2 7 show the top view and bottom view of ITG adapter respectively The J1 connector 15 used to connect the FPGA board The J2 connector 1s used to interface with the IDE cable Terasic MTL User Manual www terasic com www terasic com J1 2x20 GPIO Header J2 IDE Connector 4444 amp 5 Figure 2 6 ITG Adapter Top View A r E J2 J1 IDE Connector 2x20 GPIO Header Figure 2 7 Adapter Bottom View Terasic MTL User Manual 12 www terasic com www terasic com Chapter 3 Using the MTL This chapter provides information on how to control the Multi touch LCD Module MTL hardware including definition of 2x20 GPIO interface LCD control and multi touch
12. eset signal Input Connect to Interrupt Pin of Touch IC oREADY Output Rising Trigger when following six output data 1s valid oREG XI Output 10 bits X coordinate of first touch point oREG YI Output 9 bits Y coordinate of first touch point oREG X2 Output 10 bits X coordinate of second touch point oREG Y2 Output 9 bits Y coordinate of second touch point oREG TOUCH COUNT Output 2 bits touch count Valid value is 1 or 2 oREG GESTURE Output 8 bits gesture ID See Table 3 4 SCLK Output Connect to I2C Clock Pin of Touch IC 2 SDAT Inout Connect to I2C Data Pin of Touch IC The supported gestures and IDs are shown in Table 3 4 Table 3 4 Gestures Gesture ID hex One Point Gesture North 0x10 North East 0x12 East 0x14 South East 0x16 South 0x18 South West OxlA West Ox1C North West 1 Rotate Clockwise 0x28 Rotate Anti clockwise 0x29 Click 0x20 Double Click 0x22 Terasic MTL User Manual resic com www terasic com Note The Terasic IP Multi touch IP can also found under MP folder in system CD well as the MP folder in the reference designs MTL User Manual 17 www terasic com www terasic com Chapter 4 ePhoto Demonstration This chapter describes how to use MTL to design a simple photo viewer The demonstration can support the following Terasic FPGA boards e DE2 115 e DE2 4 1 Operation Description This demonstration implements a
13. fer to Chapter 1 in this document The license file 1s located at MTL System multi touch dat The IP decodes I2C information and outputs coordinate and gesture information The IP interface 1s shown below module ize touch config Host Side iCLK LRSTH iTRIG OREG TOUCH COUNT GESTURE I2C Side I2C I2C SD T MTL User Manual 15 www terasic com resic com The signal purpose of IP is described in Table 3 3 The IP requires 50 MHz signal as a reference clock to the pin and system reset signal to IRSTN SCLK and IC2 SDAT pins should be connected of MTL TOUCH INT n TOUCH SCL and TOUCH signals in the 2x20 GPIO header respectively When oREADY rises it means there is touch activity and associated information is given in oREG oREG X2 Y2 oREG TOUCH COUNT oREG GESTURE pins For the control application when touch activity occurs it should check whether the value of oREG GESTURE matched a pre defined gesture ID defined in Table 3 3 If it is not a gesture it means a single touch has occurred and the relative X Y coordinates can be derived from oREG and Table 3 3 Interface Definitions of Terasic Multi touch Pin Name Direction Description iCLK Input Connect to 50M Hz Clock iRSTN Input Connect to system r
14. ile The procedures are listed below Use Notepad or other text editing software to open the file license multi touch dat 1 The license contains the FEATURE lines required to license the IP Cores as shown in Figure 1 4 lieense multi Eouch dat 10 20 30 40 5L 6 0 20 1 FEATURE 5356 0018 alterad 9999 12 12 3 9999 uncounted 3 15028 111 4 2 VENDOR STRIHG I14Zzczkz9 gj hoTVOotLcnyvSBri hPsnSaeyvATvocoVv50sL3wvQOdqoclDdcIz 3 HOSTID ANY TS SIGN 1177 518556 SDAS 4068 5C33 BEST 9139 4 855 3545 6582 7215 9862 CD64 4358 0519 4 2 15 8 B6C8 CASE 5 E549 C994 C296 DGFD 93 SADE 3093 9952 EDCF 0843 Figure 1 4 Content of license multi touch dat 2 Open your Quartus II license dat file in a text editor Copy everything under license multi touch dat and paste it at the end of your Quartus II license file Note Do not delete any FEATURE lines from the Quartus II license file Doing so will result in an unusable license file 4 Save the Quartus II license file p Terasic MTL User Manual www terasic com www teresic com Note The Terasic IP Multi touch IP can also found under MP folder in system CD well as the MP folder in the reference designs 1 4 Assembly Here are the procedures to assemble the MTL kit 1 Connect the IDE cable to the IDE connector on the back of the MTL as shown in the Figure 1 5 Figure 1 5 MTL connection for the IDE cable 2 Place f
15. le MTL Component and Layout The top view of MTL 15 shown in Figure 2 1 MTL User Manual 8 www terasic com rasic com Figure 2 1 Multi touch LCD Module Top View The bottom view of Multi touch LCD Module is shown in Figure 2 2 It depicts the layout and indicates the locations of connectors and key components Connector for LCD Panel Multi touch Controller USB Interfaced Power Jack IDE Connector 5 2 774 l 1 0107 9 P neq 2498014 10 X21N 02 4S0 1 Connector for Multi touch Panel Figure 2 2 Multi touch LCD Module Bottom View MTL User Manual 9 www terasic com www terasic com ANOTE RYAN a Block Diagram Figure 2 3 shows the block diagram of MTL The IDE connector houses all the wires from peripheral interfaces connecting to the FPGA of a development kit through the IDE cable and ITG adapter I2CSCL I2CSDA Analog Signal INT n 4 m O D o DCLK ly VSD 6 a S gt e Video Data 24 Figure 2 3 Block Diagram of MTL Figure 2 4 illustrates the connection for MTL to the Terasic FPGA boards Terasic IDE to GPIO IDE IDE Multi touch ITG Connector Connector LCD Module Adapter FPGA Board Old9 sews Old9 Figure 2 4 Connection Diagram of MTL Kit with T
16. ontrol Panel Names and Bitstreams for Various FPGA Boards FPGA Board Control Panel Name _ FPGA Bitstream DE2 115 DE2 115 Control Panel DE2 115 ControlPanel sof DE2 DE2 Control Panel 1 04 DE2 USB API sof IijasiC MTL User Manual www terasic com www Procedure for loading photos to FLASH 1 Make sure the USB Blaster download cable is connected to the host 2 Power on the FPGA Development Board 3 Execute the Control Panel application software Please refer to the user manual of the FPGA development kit for more information for the Control Panel software 4 Switch to the FLASH page and click on the Chip Erase xx Sec button to erase FLASH data 5 Click on the File Length checkbox to indicate that you want to load the entire file 6 Click on the Write a File to FLASH button When the Control Panel responds with the standard Windows dialog box and asks for the source file select the DEMO raw file in the Demonstrations RTL Photo directory 7 When loading is completed a prompt will appear indicating success 4 4 Demonstration for Terasic DE2 115 FPGA Board This section shows how to setup the painter demo on the Terasic DE2 115 FPGA Board For other Terasic FPGA boards the setup procedures are similar Hardware Setup The demonstration configuration is as shown in Figure 4 4 Make sure ITG adapter is connected firmly to the I
17. our silicon footstands to foot pegs of the MTL as shown in Figure 1 6 Figure 1 6 MTL Footstand Setup TTlasiC Terasic MTL User Manual 6 www terasic com www rasic com 1 5 Connectivity The following figures show the connectivity for MTL to DE2 115 and DE2 FPGA Development Boards Note The 5V power supply is required to connect to the DE2 ai Tue Lm ODDO Figure 1 8 MTL with DE2 1 6 Getting Help is information of how to get help if you encounter any problem Office Hours 9 00 a m to 6 00 p m GMT 8 Telephone 886 3 550 8800 Email support terasic com MTL User Manual 7 www terasic com www t Chapter 2 Architecture of MTL This chapter provides information regarding features and architecture of the Multi touch LCD Module MTL 2 1 Features The key features of this module are listed below e 800x480 pixel resolution LCD with 24 bit color depth e Two point multi gesture support e Single touch support IDE interface 2x20 GPIO interface with ITG adapter 2 2 MTL Kit The MTL kit is assembled via three components Multi touch LCD Module e IDE Cable IDE to GPIO adapter The IDE cable is used to provide a high speed signal transmission for 33 MHz video signals The ITG adapter 1s designed to map the standard IDE pin assignment to the 2x20 GPIO interface on the FPGA boards 2 3 Multi touch LCD Modu
18. s of this demonstration for the various Terasic FPGA boards are shown in Table 5 1 Note The project is built under Quartus II 10 1 and both Altera VIP license and Terasic Multi Touch IP license are required for rebuilding the project Table 5 1 Source Code Locations of Painter Demonstration FPGA Board Location DE2 DemonstrationsSOPCWDE2 MTL PAINTER DE2 115 DemonstrationsSOPCWDE2 115 MTL PAINTER Terasic MTL User Manual 27 www terasic com www terasic com Chapter 6 Appendix 6 1 Revision History Version Change Log V1 0 Initial Version Preliminary 6 2 Copyright Statement Copyright 2011 Terasic Technologies All rights reserved We will continue to provide interesting examples and labs on our MTL webpage Please visit mtl terasic com for more information Terasic MTL User Manual 28 www terasic com www terasic com
19. simple photo viewer Before running this demonstration three 800x480 photos should be vertically merged into one 800x1440 photo and be stored in FLASH of the FPGA board in advance In this demonstration users can browse each photo by using single touch west or east gesture to select the previous or next photo as shown in Figure 4 1 Figure 4 1 Select Next Photo by East Gesture Also users can use two point zoom in and zoom out gestures to zoom the photo displayed as shown in Figure 4 2 www terasic com 4 2 Block Diagram of the ePhoto Design This section describes the block diagram of the ePhoto demonstration to give users a better understanding of the code provided Figure 4 3 shows the block diagram of the ePhoto demonstration When the demonstration starts up the system will control the Flash Controller to read the RGB data of three photos stored in the FLASH and write the data into SDRAM by using the writing port of the SDRAM The SDRAM Controller provides two reading ports and two writing ports In this demonstration only one reading port and one write porting are used To display the selected photo on the 800x480 LCD the VGA Controller will retrieve the photo data via reading the port of the SDRAM and drive the LCD display with the retrieved photo data The VGA Controller retrieves the photo data at a rate of 60 photos per second Zoom handles the photo zooming process The displayed photo is zoomed before being sent to th
20. tration bitstream files for various Terasic FPGA boards Table 4 2 Bitstream Files for Various FPGA Boards FPGA Board Quartus Project Directory FPGA Bitstream Used DE2 115 DemonstrationsRTIADE2 115 MTL MTL DEMO sof DE2 Demonstrations RTL DE2 _ MTL EPHOTO DE2 MTL sof MTL User Manual 22 www terasic com www terasic com NOTES RYA 4 5 Custom Display Photo Procedure for creating custom photos for ePhoto 1 Prepare three 24 bit bitmap format photos with 1mage resolutions of 800 width x 480 height pixels for each as shown in Figure 4 6 Figure 4 6 Original Photo Resolution 2 Use image processing software to vertically merge the three photos into a new photo image with 24 bits color bitmap format The merged photo resolution should be 800 width x 1440 height pixels as shown in Figure 4 7 3 Use tool to raw exe the Demonstrations RTL Photo directory to convert picture to raw file Terasic MTL User Manual 23 www terasic com Chapter 5 Painter Demonstration UD This chapter shows how to implement a painter demo on the Multi Touch LCD Module based on SOPC Builder and the Altera s Video and Image Processing Suite VIP The design demonstrates how to use multi touch gestures and single touch The demonstration requires the following hardware Terasic Board e Multi touch LCD Module 5 1 Operation Description Figure

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