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AT-MIO-64F-5 User Manual

1. 0 to 70 C with Respect to 0 5 V to 7 0 V Supply Voltage Vcc 5 V 5 All Signal Voltages with Respect to 55 05 V to 7 0 V Industrial 1 Devices Power Dissipitation Package Limitation 15 Temperature Supply Voltage Vcc Stresses above those listed under ABSOLUTE MAXIMUM Military M Devices RATINGS may cause permanent device failure Functionality Temperature at or above those limits is not implied Exposure to absolute Supply Voltage Vcc i ratings for extended periods may affect device __ rating ranges define those limits between which the functionality of the device is guaranteed DC CHARACTERISTICS over operating ranges uniess otherwise specified aes e ee eee input High Volage a le 5 Xm _____ ___________ wc ___ Hysteresis SRC and GATE Inputs Ony 46 Output Low _________ _0 _ __ 0 ves Output High Voltage 24 Ves LX Load Curent XD _______ lt lt 1 o EN EMEN IIO NENNEN LI eo l 777646 VC Supply Current Steady State ____________________ 255 25 EN Capacitance bet ai tee sanc E ERN cour Ou
2. ue RESLS witel Control PattGrs see AT MIO 64F 5 EEPROM Revision and Subrevision Configuration Memory Depth Field and DAC FIFO Depth Field uri tient ie ten pere aai Area Information A AT MIO 64F 5 Connector eee eene enne nnne nennen nennen 50 Pin MIO Optional eso Ce eret o PU Default Settings of National Instruments Products for the PC Switch Settings with Corresponding Base I O Address and Base I O Address Sade dudo Due fitus gs ew Available Input Configurations for the AT MIO 64F 5 eese Actual Range and Measurement Precision Versus Input Range Selection AMC GAIN MERE Recommended Input Configurations for Ground Referenced and Hloa ug Signal AT MIO 64F 5 Register sagen ete sane aT NES DMA Channel Selection die inerte e Pei pete pre DIMA and Hiterr pt avis tes qt ote vU oua Pieve Interrupt Level Selection eie te Board RTSI Clock Selection ics ien std ated
3. 5 15 Servicing the Data Acquisition 5 16 Resetting the Hardware after Data Acquisition 5 16 Resetting a Single Am9513A Counter Timer eese 5 16 Programming the Analog Output Circuitry eene 5 18 Cyclic Waveform Generation cad edo ein 5 18 Programmed Cycle Waveform 5 19 Pulsed Cyclic Waveform Generation a d oed eee 5 2 Waveform Generation Programming 5 23 Clearing the Analog Output Circuitry eee 5 23 Selecting the Internal Update Counter eese 5 23 Programming the Update Interval Counter eese 5 23 Programming the Waveform Cycle Counter esses 5 24 Programming the Waveform Cycle Interval Counter 5 25 Servicing Update orga uade 5 26 Programming Digital I O C CUllty oer Tete emda 5 26 Programming the Am9513A 4 1 5 27 RTSI Bus Trigger Line Programming Considerations 5 27 RTSI Switch Signal Connection Considerations eee 5 28 Programming the R ESI iie iio taie i eere einn sa iS 5 29 Programming DMA Operations eeseesese
4. Po 9 9 3 5 5 11 roo ce o Gate meam X6 LEVEL ooo iever Eoee ooo Leve EDGE coo LeveL Eoee count te TC once tendum XT XT x 7 1 1 LL twice wn dam to repeatedy dmg x Txt x yx ee NN gue ev X Start count on active gate edge and stop count on next TC second 7 07 e e siop count on E ERE tte pepe Fei cone ae bea ge TE CTS Sat Reload counter on each TC ia source between Load and Hold gate is LOW transfer Hold register into counter on each TC that gate is HIGH LLL register and then reload counter from Load RENI ee ewemume DII I tit _ counter Mode pats Special Gate CMD ______ ee Reload Source ______ oe Poe CMS oo Gate Contro CM15 CM13 000 EDGE 000 LEVEL EDGE 000 LEVEL EDGE 000 LEVEL EDGE Count to TC once ten ___ Count to TC twice then aisan 1 1 LLL Count to TC repeatedly without disarming ____ ex _______ ____ __ __ Count only during active gate level ___ x x
5. 64 5 User Manual Multifunction I O Board for the PC AT EISA July 1994 Edition Part Number 320487 01 Copyright 1992 1994 National Instruments Corporation Rights Reserved National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin TX 78730 5039 512 794 0100 Technical support fax 800 328 2203 512 794 5678 Branch Offices Australia 03 879 9422 Austria 0662 435986 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Italy 02 48301892 Japan 03 3788 1921 Netherlands 03480 33466 Norway 32 848400 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 27 00 20 U K 0635 523545 Limited Warranty The AT MIO 64F 5 is warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace softw
6. Ll sem Qus tore 948 ege sp cour on Sogo ea em LEER EE a L Ix Reload counter from Load register on EEESEE EE Reload counter on each TC alternating reload source between Load and Hold registers Transter Load register into counter on each TC that gate is LOW transfer Hold register into counter on each TC that gate is HIGH On active gate edge transfer counter into Hold register and then reload counter from Load register son bas ee Cece register but counting continues Notes 1 Courter modes M P T U and W are reserved and should not be used 2 Mode X is available for Am9513A only Figure 14 Counter Mode Operating Summary the ARM command is omitted The retriggering modes are shown with one retrigger operation Both a TC COUNTER MODE DESCRIPTIONS Counter Mode register bits CM15 CM13 and CM7 CMS select the operating mode for each counter see Figure 14 To simplify references to a particular mode each mode is assigned a letter from A through X Representative waveforms for the counter modes are illustrated in Figures 15a through 15v Because the letter suffix in the figure number is keyed to the mode Figures 15m 15 15t 15 and 15w do not exist The figures assume down counting on rising source edges Those modes which automatically disarm the counter CMS 0 are shown with the plus enter
7. 0 lt 2 0 gt DMACHAB lt 2 0 gt Register Map and Descriptions Description continued Bipolar DAC 1 This bit configures the range of DAC 1 in the analog output section If this bit is set DAC 1 is configured for bipolar operation of Vref to Vref In this mode data written to this DAC is interpreted in two s complement format If this bit is cleared DAC 1 is configured for unipolar operation of 0 V to Vref In this mode data written to DAC 1 is interpreted in straight binary format Bipolar DAC 0 This bit configures the range of DAC 0 in the analog output section If this bit is set then DAC 0 is configured for bipolar operation of Vref to In this mode data written to this DAC is interpreted in two s complement format If this bit is cleared then DAC 0 is configured for unipolar operation of 0 V to Vier In this mode data written to DAC 0 is interpreted in straight binary format External Reference for DAC 1 This bit controls the reference selection for DAC 1 in the analog output section If this bit is set the reference used for DAC 1 is the external reference voltage from the I O connector If this bit is cleared the internal 10 is used for the DAC 1 reference External Reference for DAC 0 This bit controls the reference selection for DAC 0 in the analog output section If this bit is set the reference used for DAC O is the external reference voltage from the
8. enirn 3 12 Analog Output and Timing Circuitry eese eese esee sienne eene enne nnne nenne 3 12 Analog Output Soci aee e RE Eee pide hace e 3 13 Analog Output Configuration essen nennen 3 14 Analog Output Calibration eite reete et eee viue 3 14 DAC Waveform Generation Timing and 02 4 00 0 3 14 DAC Waveform Circuitry 3 15 DAC Waveform Timing Circuitry s eeu eet teer sciet teens 3 16 FIFO Continuous Cyclic Waveform Generation 3 17 FIFO Programmed Cyclic Waveform 3 18 FIFO Pulsed Waveform Generation iss Assad 3 18 cosa Sacto it ei deo a qe dut eto A lun n EUR ds 3 19 Timing VO CAreuliry iu oun e RO UR SR DER Ton S Vox ea 3 20 RESI Buy Interface CATOHH e gea pts es obe tib ep AD Nes tui rub dev 3 23 Chapter 4 Register Map and Descriptions seen 4 1 a esas oe eee 4 1 Resister SIZES 4 2 AT MIO 64F 5 User Manual x National Instruments Corporation Contents Register Description Format use esten tte eoe rante ee reae tS Ue esa Pa 4 3 Configuration and Status Register Group seen
9. bte eie Analog Output Waveform Modes Straight Binary Mode A D Conversion Two s Complement Mode A D Conversion Values eee op t bs Meca eo Calibration caet omen oo aa pates op Extended Analog Input Connections Analog Output Voltage Versus Digital Code Unipolar Mode Analog Output Voltage Versus Digital Code Bipolar Mode Am9513A Counter Timer Allocations essen ETSI Switch Signal Conti CtlOns s dece bes lacer ea ve IEEE sd National Instruments Corporation AT MIO 64F 5 User Manual Contents Table 6 1 EEPROM Factory Area Information itae 6 2 cC dE ou DAG A A A 6 5 Table 6 3 Calibration 2 6 6 Table 1 Equivalent Offset Errors in 16 Bit Systems eee A 2 Table A 2 Equivalent Gain Errors in 16 Bit Systems esse 3 AT MIO 64F 5 User Manual xvi National Instruments Corporation 1 Introduction This chapter describes the AT MIO 64F 5 lists the conten
10. vam 8 0 3868 FPES SERE Rum i e SG 2898 08000004 00009001 ore pun p m n SBR PEDE He 00020 858 4 opis 76 ipe 55 pei es iR DAT A E y Segna peooocoocg gos lt lt 045 Bm pn us To a v212 VETE So 2 8 915458 00000 oaas 9000000 y A 1 N 8688 gm ee x B38 E Heetozi SPH L 8 SCC 838 go 000000000 0020000000 00000000 888 000000 mecum mni N 89355 ag Smet pond gel m 1 E ds D 0000000 0000091 00000 SG E SERES my 9 po wem 259 8 as 3 828 Sung Tm tas Oa SRW Ben B 4 di j 8 nn TELS ER f SY gt So sema amp R s s FSSSSSSsSUHSSSSsmUM 2 ig O 8 uix lt A of deh 398 EY Ete gt 58 1 4 5 pue E _ t S Jequiny quiessy 3 t S ouleN yONpoIg 3 2 D 1 E SE b 1 lt x Chapter 2 Configuration and Installation AT Bus Interface Operation of the AT MIO 64F 5 multifunction I O board is controlled through accesses to registers within the board register set Some of the registers in the register set retain data written to them to determine board operation Other registers in the register set contain important status information necessar
11. 2 122 AT MIO 64F 5 User Manual provides direct access to the Status and Command registers as well as allowing the user to update the Data Pointer register The Data port is used to communicate with all other addressable internal locations The Data Pointer register controls the Data port addressing Among the registers accessible through the Data port are the Master Mode register and five Counter Mode registers one for each counter The Master Mode register controis the program mable options that are not controlled by the Counter Mode fegisters Each of the five general purpose counters is 16 bits long and is independently controlled by its Counter Mode register Through this register a user can software select one of 16 Sources as the counter input a variety of gating and repetition modes up or down counting in binary or BCD and active high or active low input and output polarities Associated with each counter are a Load register and a Hold register both accessible through the Data port The Load register is used to automatically reload the counter to any predefined value thus controlling the effective count period The Hold register is used to save count values without disturbing the count process permitting the host processor to read intermediate counts in addition the Hold register may be used as second Load register to generate a number of complex output waveforms All five counters have the same basi
12. Element increment 11 Hold Register Hold increment 00 Alarm Register 1 01 Alarm Register 2 10 Master Mode Reg National Instruments Corporation Control increment 11 Status Register No increment Figure 7 Data Pointer Register Am9513A E 9 1 Least Significant Byte Transterred Next 001 x Counter Group 1 010 Counter Group 2 011 Counter Group 3 100 Counter Group 4 101 Counter Group 5 110 111 Control Group DF001890 2 123 AT MIO 64F 5 User Manual at 4 AMD Am9513A Data Sheet Register Register Register Figure 8 Load Data Pointer Commands Sequencing is enabled by clearing Master Mode bit 14 MM14 to zero As shown in Figure 9 several types of sequencing are available depending on the data bus width being used and the initial Data Pointer value entered by command When E1 0 or E2 0 and G4 G2 G1 points to a Counter Group the Data Pointer will proceed through the Element cycle The Element field will automatically sequence through the three values 00 01 and 10 starting with the value entered When the transition from 10 to 00 occurs the Group field will also be incremented by one Note that the Element field in this case does not sequence to a value of 11 The Group field circulates only within the five Counter Group codes If E2 1 11 and a Counter Group are selected then on
13. FF21 Arm Counter 1 FF22 Arm Counter 2 FF30 Arm Counter 5 After you complete this programming sequence Counter is configured to generate active low pulses as soon as the load arm counter command is written Programming the Waveform Cycle Counter Select the appropriate counter 1 2 or 5 from the Am9513A Counter Timer to be used for counting DAC buffer cycles To program the cycle counter complete the following programming sequence writes are 16 bit operations values given are hexadecimal 1 Write FF00 to the Am9513A Command Register to select the Counter n Mode Register 2 Write 0325 to the Am9513A Data Register to store the Counter mode value Am9513A counter mode information can be found in Appendix E AMD Am95134A Data Sheet 3 Write 08 n to the Am9513A Command Register to select the Counter n Load Register 4 Write the desired cycle count to the Am9513A Data Register to store the Counter load value 5 Write the following value to the Am9513A Command Register to load Counter n FF41 Load Counter 1 FF42 Load Counter 2 FF50 Load Counter 5 AT MIO 64F 5 User Manual 5 24 National Instruments Corporation Chapter 5 Programming 6 Write FFFO n to the Am9513A Command Register to decrement Counter 7 Write the following value to the Am9513A Command Register to arm Counter n FF21 Arm Counter 1 FF22 Arm Counter 2 FF30 Arm Counter 5 After you compl
14. 3DF 3FF c gt lt gt lt 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 _ _ RRP Rr _ OCR _ _ RFP Interrupt Channel Selection The base I O address selection is the only resource on the AT MIO 64F 5 board that must be set manually before the board is placed into the PC The interrupt level and DMA channels used by the AT MIO 64F 5 are selected via registers in the AT MIO 64F 5 register set The AT MIO 64F 5 powers up with all interrupt and DMA requests disabled To use the interrupt capability of the AT MIO 64F 5 an interrupt level must first be selected via register programming then the specific interrupt mode must be enabled The same method holds for DMA channel selection To use the DMA capability of the board one or two DMA channels must be selected through the appropriate register then the specific DMA mode must be enabled It is possible to have interrupt and DMA resources concurrently enabled The interrupt lines supported by the AT MIO 64F 5 hardware are IRQ3 IRQ4 IRQ5 IRQ7 IRQIO IRQ11 IRQ12 and IRQ15 The DMA channels supported are channels 0 through 3 and channels 5 through 7 If the AT MIO 64F 5 is used in an AT type computer only DMA channels 5 throug
15. e Multiplexer control is configured to control up to 32 input channels AI SENSE may be driven by the board analog input ground or left unconnected Considerations for using the DIFF input configuration are discussed in the Signal Connections section later in this chapter Figures 2 7 and 2 8 show schematic diagrams of this configuration RSE Input 64 Channels RSE input means that all input signals are referenced to a common ground point that is also tied to the analog input ground of the AT MIO 64F 5 board The negative input of the differential input amplifier is tied to the analog ground This configuration is useful when measuring floating signal sources See the Types of Signal Sources section later in this chapter for more information With this input configuration the AT MIO 64F 5 can monitor up to 64 different analog input signals This configuration is selected via software See the configuration memory register and Table 4 9 in Chapter 4 Register Map and Descriptions The results of this configuration are as follows e The negative input of the is tied to the PGIA signal ground e Multiplexer outputs are tied together into the positive input of the e Multiplexer control is configured to control up to 64 input channels AI SENSE may be driven by the board analog input ground or left unconnected Considerations for using the RSE configuration are discussed in the Signal Connections section la
16. lt 0 15 gt as channels 0 through 15 lt 0 15 gt represents the first eight channels in the differential configuration and the first 16 channels in the single ended configuration Analog Input Sense This pin serves as the reference node when the board is in NRSE configuration If desired this signal can be programmed to be driven by the board analog input ground in the DIFF and RSE analog input modes Analog Channel 0 Output This pin supplies the voltage output of analog output channel Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 External Reference This is the external reference input for the analog output circuitry Analog Output Ground The analog output voltages are referenced to this node Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply Digital I O port A signals National Instruments Corporation Chapter 2 Pin 26 28 30 32 34 35 36 37 38 39 40 41 42 43 Signal Name BDIO lt 0 3 gt 5 SCANCLK EXTSTROBE EXTTRIG EXTGATE EXTCONV SOURCEI GATEI OUTI National Instruments Corporation Reference DIG GND DIG GND DIG GND DIG GND DIG GND DIG GND DIG GND DIG GND DIG GND DIG GND 2 15 Configuration and Installation Description continued Digital I O port B signals 5 VD
17. output logic high voltage 2 4 V minimum Vj output logic low voltage 0 5 V maximum output source current logic high 2 6 mA maximum Io output sink current logic low 24 mA maximum With these specifications each digital output line can drive 11 standard TTL loads and over 50 LS TTL loads Figure 2 12 depicts signal connections for three typical digital I O applications Port A ADIO lt 3 0 gt Port B BDIO lt 3 0 gt Switch MIO Subconnector AT MIO 64F 5 Board Figure 2 12 Digital I O Connections In Figure 2 12 port A is configured for digital output and port B is configured for digital input Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 2 12 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 2 12 National Instruments Corporation 2 29 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 Power Connections Pins 34 and 35 of the MIO subconnector provide 5 V from the PC power supply These pins are referenced to DIG GND and can be used to power external digital circuitry Power rating 1 0 A at 5 V 10 fused Warning Under no circumstances should these 5 V power pins be directly connected to analog or digital ground or to any other voltage source on the AT MIO 64F 5 or any other device Doing so can damage the AT MIO 64F 5 and
18. National Instruments Corporation 4 35 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 CONFIGMEMCLR Register Accessing the CONFIGMEMCLR Register clears all information in the channel configuration memory and resets the write pointer to the first location in the memory Address Base address 1B hex Type Read only Word Size 8 bit Bit map Not applicable no bits used Strobe Effect Clears the channel configuration memory Before the channel configuration memory is written to it must be cleared of its existing information and reset to an initialized state This process is accomplished by accessing the CONFIGMEMCLR Register Once the existing channel configuration values are cleared they are not recoverable At this point the channel configuration memory is ready to be filled with valid information AT MIO 64F 5 User Manual 4 36 National Instruments Corporation Chapter 4 Register Map and Descriptions CONFIGMEMLD Register Accessing the CONFIGMEMLD Register loads and sequences through the channel configuration memory Address Base address 1B hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Read and apply a channel configuration value to the analog input section Accessing the CONFIGMEMLD Register loads the channel configuration memory values and applies the first channel configuration value to the analog input circuitry After the final writ
19. il Figure 1 1 AT MIO 64F 5 Board You can use the AT MIO 64F 5 with its multifunction analog digital and timing I O in many applications including machine and process control automation level monitoring and control instrumentation electronic testing and many others You can use the multichannel analog input for signal and transient analysis data logging and chromatography The two analog output channels are useful for machine and process control analog function generation 12 bit resolution voltage source and programmable signal attenuation You can use the eight TTL compatible digital I O lines for machine and process control intermachine communication and relay switching control The three 16 bit counter timers are useful for such functions as pulse and clock generation timed control of laboratory equipment and frequency event and pulse width measurement With all these functions on one board you can automatically monitor and control laboratory processes The AT MIO 64F 5 is interfaced to the National Instruments RTSI bus With this bus National Instruments AT Series boards can send timing signals to each other The AT MIO 64F 5 can send signals from the onboard counter timer to another board or another board can control single and multiple A D conversions on the AT MIO 64F 5 Detailed specifications for the AT MIO 64F 5 are listed in Appendix A Specifications AT MIO 64F 5 User Manual 1 2 National Instruments Corpo
20. Register and Descriptions Chapter 4 Table 4 1 AT MIO 64F 5 Register Map Continued Register Name Offset Address Type Size Hex ADC Event Strobe Register Group CONFIGMEMCLR Register 1B Read only CONFIGMEMLD Register 1B Write only DAQ Clear Register 19 Read only DAQ Start Register 1D Read only 1D Single Conversion Register Write only DAC Event Strobe Register Group TMRREQ Clear Register Read only DAC Update Register Write only DAC Clear Register Read only General Event Strobe Register Group DMA Channel Clear Register Read only DMATCA Clear Register Write only DMATCB Clear Register Read only External Strobe Register Write only Calibration DAC 0 Load Register Write only Am9513A Counter Timer Register Group Am9513A Data Register Read and write Am9513A Command Register Write only Am9513A Status Register Read only Digital I O Register Group Digital Input Register Read only Digital Output Register Write only RTSI Switch Register Group RTSI Switch Shift Register Write only RTSI Switch Strobe Register Write only Register Sizes Two different transfer sizes for read and write operations are available on the PC byte 8 bit and word 16 bit Table 4 1 shows the size of each AT MIO 64F 5 register For example reading the ADC FIFO Register requires a 16 bit word read operation at the selected address whereas writing to the RTSI Strobe Register requires an 8 bit byte write operation at the selected a
21. c Setthe OUTEN bit for all output pins 2 Fori to 55 follow these steps a Copy bit i of the 56 bit pattern to bit O of an 8 bit temporary variable b Write the temporary variable to the RTSI Switch Shift Register 8 bit write 3 Write 0 to the RTSI Switch Strobe Register 8 bit write This operation loads the 56 bit pattern into the RTSI switch At this point the new signal routing goes into effect Step 2 can be completed by simply writing the low order 8 bits of the 56 bit pattern to the RTSI Switch Shift Register then shifting the 56 bit pattern right once and repeating this two step operation a total of 56 times Only bit 0 of the word written to the RTSI Switch Shift Register is used The higher order bits are ignored Programming DMA Operations The AT MIO 64F 5 can be programmed so that the ADCFIFOEF generates DMA requests every time one or more A D conversion values are stored in the ADC FIFO when the ADCFIFOHF 15 low and the FIFO is half full and when the DACFIFO requires at least one data value DACFIFOFF is set and when the DACFIFO is less than half full DACFIFOHF is set There are two DMA modes single channel transfer and dual channel transfer Single channel DMA uses only Channel A DMA signals while dual channel DMA uses signals for both Channel A and Channel B The DMA channels are selected through Command Register 2 To program the DMA operation perform the following steps after the circuitry on the AT M
22. line because it is connected to ground National Instruments Corporation 2 23 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 Hence this noise appears as a differential mode signal instead of a common mode signal and so the PGIA does not reject it In this case instead of directly connecting the negative line to AI GND connect it to AI GND through a resistor that is about 100 times the equivalent source impedance This puts the signal path nearly in balance so about the same noise couples onto both and connections yielding better rejection of electrostatically coupled noise Also this configuration does not load down the source other than the 100 GQ input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive input and AI GND This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for instance the source impedance is 2 and the two resistors are each 100 kQ the resistors load down the source with 200 kQ and produce a 196 gain error Both inputs of the PGIA require a DC path to ground in order for the PGIA to work If the source is AC coupled capacitively coupled then the PGIA needs a resistor between the positive input and AI GND If the source has low impedance choose a resistor that
23. 1 to MSB LSB Figure 6 5 Area Information Field If the Area Information Field contains the binary value XXXXX10X where X indicates don t care bits then the area described by this area information value contains bipolar DAC 1 calibration constants and unipolar DAC 0 calibration constants thus a 1 indicates bipolar and a 0 indicates unipolar The area information value for the factory bipolar area will always be XXXXX11X and for the factory unipolar area it will always be If the analog output section is calibrated using the library functions and the constants are saved to an EEPROM area then the area information bits will be set according to the mode in which the analog output section was calibrated The analog input section is calibrated in both unipolar and bipolar modes so you do not need to recalibrate this section when the mode changes AT MIO 64F 5 User Manual 6 4 National Instruments Corporation Chapter 6 Calibration Procedures Calibration Equipment Requirements Normal self calibration requires no external calibration equipment However because the internal voltage reference drifts slightly with time and temperature it may be necessary to redetermine its value every year or whenever operating the board at an ambient temperature that is more than 20 C from the temperature at which the reference value was last determined The value of the reference is initially determined at the factory at a room temperat
24. 4 20 5 23 5 31 DMATCA Clear Register 4 47 5 23 5 30 5 31 DMATCB bit 4 20 5 23 5 31 DMATCB Clear Register 4 48 5 23 5 30 5 31 DMATCINT bit 4 12 documentation abbreviations used in the manual vi acronyms used in the manual vii organization of manual v related documentation vii DRVAIS bit 4 14 E EEPROM ADC and DAC FIFO Depth field 6 4 Area Information field 6 4 Configuration Memory Depth Field 6 3 EEPROM map 6 1 factory area information 6 2 Revision and Subrevision field 6 3 storage area 6 3 bit 4 21 EEPROMCS bit 4 5 EEPROMDATA bit 4 21 AT MIO 64F 5 User Manual Index 12 National Instruments Corporation Index bit 4 9 equipment optional 1 4 to 1 5 event counting event counting application with external switch gating 2 34 programming 2 33 to 2 34 EXTCONV signal definition 2 15 C 3 generating single conversions 5 5 programming sample interval counter 5 11 RTSI switch 3 24 single channel data acquisition timing 3 9 timing applications 3 22 timing connections 2 31 updating DACs 5 23 extended analog input subconnector mapping in different input configurations table 4 28 4 30 pin assignments 2 17 D 1 signal connection guidelines 2 18 to 2 20 signal descriptions 2 18 D 2 External Strobe Register 4 49 EXTGATE signal data acquisition timing connections 2 32 definition 2 15 C 3 EXTREF signal analog output signal connection
25. A 2 to A 3 postgain offset error A 2 pregain offset error A 2 AT MIO 64F 5 User Manual Index 16 National Instruments Corporation Index M MIO subconnector pin assignments 2 13 C 1 signal connection descriptions 2 14 to 2 16 C 2 to C 3 signal connections 2 18 multiple analog input channel programming 5 11 multiple channel scanned data acquisition timing 3 10 to 3 12 continuous scanning 3 11 data acquisition rates 3 12 interval scanning 3 12 posttrigger data acquisition timing continuous scanning 3 11 interval scanning 3 12 multiple channel scanning acquisition rates A 5 multiplexers input See input multiplexers N NI DAQ software 1 3 noise minimizing environmental noise 2 37 to 2 38 system noise A 4 nonlinear errors differential nonlinearity A 4 integral nonlinearity A 3 relative accuracy A 3 nonreferenced single ended NRSE input configuration 2 7 definition 2 7 differential connections 2 22 to 2 23 single ended connections for grounded signal sources 2 26 NRSE See nonreferenced single ended NRSE input offset error analog output circuitry 6 operating environment specifications A 7 operation of AT MIO 64F 5 See theory of operation optional equipment 1 4 to 1 5 optional software 1 3 OUT GATE and SOURCE timing signals 2 33 to 2 37 3 21 to 3 22 3 24 OUT 5 1 bit 4 54 OUTI signal 2 15 5 23 C 3 OUT 2 signal 2 16 5 23 C 3 signal 5 23 OUTS
26. By enabling DITHER and using averaging input resolution greater than 12 bits is obtainable National Instruments Corporation 4 5 AT MIO 64F 5 User Manual Register and Descriptions Bit Name 10 INTGATE 9 RETRIG DIS 8 DAQEN 7 SCANEN 6 SCN2 5 CNT32 16 AT MIO 64F 5 User Manual Chapter 4 Description continued Internal Gate This bit controls internal and external A D conversions When INTGATE is set no A D conversions take place When INTGATE is cleared A D conversions take place normally INTGATE can be used as a software gating tool or to inhibit random conversions during setup operations Retrigger Disable This bit controls retriggering of the AT MIO 64F 5 data acquisition circuitry When RETRIG DIS is set retriggering of the data acquisition circuitry is inhibited until the end of the previous operation is acknowledged by clearing the DAQPROOG bit in Status Register 0 When RETRIG DIS is cleared the data acquisition circuitry may be retriggered any time following the end of the previous acquisition sequence Data Acquisition Enable This bit enables and disables a data acquisition operation that is controlled by the onboard sample interval and sample counters If DAQEN is set a software DAQ Start or hardware EXTTRIG trigger starts the programmed counters thereby initiating a data acquisition operation If DAQEN is cleared software and hardware triggers have no effect Scan Enable
27. Enabled 5 input 10 TOD Enabled 6 input 11 TOO Enabled 10 input 0 001913 Figure 11 Master Mode Register Bit Assignments Time of Day Bits MMO and 1 of the Master Mode register specity the Time of Day TOD options When 0 and 1 0 the special logic used to implement TOD is disabled and Count ers 1 and 2 will operate in exactly the same way as Counters 3 4 and 5 When MMO 1 or MM1 1 additional counter decoding and contro logic is enabled on Counters 1 and 2 which causes their decades to turn over at the counts that generate appropriate 24 hour TOD accumulations For addi tional information see the Time of Day chapter in the 9513A System timing controller technica manual Comparator Enabie Bits MM2 and control the Comparators associated with Counters 1 and 2 When a Comparator is enabled its output is substituted for the normal counter output on the associated OUT1 or OUT2 pin The comparator output will be active high if the output contro field of the Counter Mode register is 001 or 010 and active low for a code of 101 Once the compare output is true it will remain so until the count changes and the comparison therefore goes faise The two Comparators can always be used individually in any operating mode One special case occurs when the Time of Day option is revoked and both Comparators are enabled The operation of Comparator 2 will then be conditioned by Comparator 1 so tha
28. The RTSI switch is a National Instruments custom integrated circuit that acts as a 7x7 crossbar switch Pins B 6 0 are connected to the seven RTSI bus trigger lines Pins A 6 0 are connected to seven signals on the board The RTSI switch can drive any of the signals at pins A 6 0 onto any one or more of the seven RTSI bus trigger lines and can drive any of the seven trigger line signals onto any one or more of the pins A lt 6 0 gt This capability provides a completely flexible signal interconnection scheme for any AT Series board sharing the RTSI bus The RTSI switch is programmed via its chip select and data inputs On the AT MIO 64F 5 board nine signals are connected to pins A lt 6 0 gt of the RTSI switch with the aid of additional drivers The signals OUT1 OUT2 SOURCES OUTS and FOUT are shared with the AT MIO 64F 5 I O connector and Am9513A Counter Timer The EXTCONV and EXTTRIG signals are shared with the I O connector and the data acquisition timing circuitry The TMRTRIG signal is used to update the two DACs on the AT MIO 64F 5 These onboard interconnections allow AT MIO 64F 5 general purpose and data acquisition timing to be controlled over the RTSI bus as well as externally and allow the AT MIO 64F 5 and the I O connector to send timing signals to other AT boards connected to the RTSI bus AT MIO 64F 5 User Manual 3 24 National Instruments Corporation Chapter 4 Register Map and Descriptions This
29. differential connections general considerations 2 21 ground referenced signal sources 2 22 nonreferenced or floating signal sources 2 23 to 2 24 differential input configuration 2 8 differential nonlinearity errors analog input A 4 analog output A 6 DIG GND signal 2 14 2 28 to 2 29 C 2 Digital Input Register 3 19 to 3 20 5 26 digital I O configuration 2 10 specifications A 7 digital I O circuitry block diagram 3 19 programming 5 26 theory of operation 3 19 to 3 20 Digital I O Register Group 4 55 to 4 57 National Instruments Corporation Index 11 AT MIO 64F 5 User Manual Index Digital Input Register 3 19 to 3 20 4 56 Digital Output Register 3 19 4 57 register map 4 2 Digital Output Register 3 19 5 26 DIOPAEN bit 4 11 5 26 DIOPBEN bit 4 11 5 26 DITHER bit 4 5 dither circuitry analog input circuitry 3 7 DMA channel bits for selecting 4 9 to 4 10 configuration 2 5 controlled by ADCREQ bit 4 13 to 4 14 default settings for National Instrument products 2 4 PC I O channel interface 3 4 DMA Channel Clear Register 4 46 DMA operations programming 5 30 to 5 31 dual channel interleaved mode 5 31 procedure 5 30 to 5 31 servicing update requests 5 26 single channel interleaved mode 5 31 DMA request generation bits for controlling 4 12 to 4 14 programming 5 30 to 5 31 DMACHA bit 4 12 DMACHAB lt 2 0 gt bit 4 9 DMACHB bit 4 12 lt 2 0 gt bit 4 9 DMATCA bit
30. may help e For the analog input signals shielded twisted pair wires for each analog input pair yield the best results assuming that differential inputs are used Tie the shield for each signal pair to the ground reference at the source The analog lines pins 1 through 23 of the MIO subconnector should be routed separately from the digital lines pins 24 through 50 e When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise from switching digital signals coupling into the analog signals AT MIO 64F 5 User Manual 2 38 National Instruments Corporation Chapter 3 Theory of Operation This chapter contains a functional overview of the AT MIO 64F 5 and explains the operation of each functional unit making up the AT MIO 64F 5 Functional Overview The block diagram in Figure 3 1 is a functional overview of the AT MIO 64F 5 board ADC Interrupt Mux Mode Selection A D Switches Interface 5 Data ER E ER Control PC I O Channel E o e Data Control Input DAC RTSI Bus DACO Interface Serial ADC Data DACI HERO Serial DAC Data ecu Figure 3 1 AT MIO 64F 5 Block Diagram National Instruments Corporation 3 1 AT MIO 64F 5User Manual Theory of Operation Chapter 3 The following major components make up the AT MIO 64F 5 board PC I O channel interface ci
31. the channel configuration memory is empty and can be written to If CFGMEMEF is set the channel configuration memory is not empty AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 Status Register 2 Status Register 2 contains 1 bit of AT MIO 64F 5 hardware status information for monitoring the status of the A D conversion Address Base address 1A hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 MSB 7 6 5 4 3 2 1 0 LSB Bit Name Description 15 1 X Don t care bits 0 BUSY This bit indicates the status of the A D converter on the AT MIO 64F 5 during a conversion If is clear an ADC conversion operation is currently in progress Initiating a conversion when ADC is clear will result in an OVERRUN error If BUSY is set no ADC conversion operation is in progress AT MIO 64F 5 User Manual 4 22 National Instruments Corporation Chapter 4 Register and Descriptions Analog Input Register Group The two registers making up the Analog Input Register Group control the analog input circuitry and can be used to read the ADC FIFO Reading from the ADC FIFO Register location transfers data from the AT MIO 64F 5 ADC FIFO buffer to the PC Writing to the CONFIGMEM Register location sets up channel configuration information for the analog input section This information is necessary for single conversions as well as
32. the first clock edge will cause the new load register contents to transfer into the counter and the next clock edge will decrement the counter and make it go out of TC 15 Glitches on CS just before the RD or WA puise may cause the part to behave incorrectly 16 Timing parameters TGVEH amp TEHGV must not be vio lated Figure A4 shows a method 1 Registers not being programmed correctly Check READ or WRITE recovery time 2 Setup and hold problems observed in synchronous systems Try switching from positive edge to negative edge triggering 004080 R1 6 8 210 R2 is a function of Driver Circuitry to meet X2 VIH 3 8 V X2 ViL 0 8 V Figure A1 Crystal input Configuration Am9513A National Instruments Corporation E 39 2 153 AT MIO 64F 5 User Manual AMD Am9513A Data Sheet Appendix E Lt Figure A2 Crystal input Configuration 002000 WF023981 TC004100 Figure A4 GATE SRC Configuration Suggestion 2 154 Am9513A__ AT MIO 4F 5 User Manual E 40 National Instruments Corporation Appendix Customer Communication For your convenience this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation Filling out a copy of the Technical Support Form before contacting National Instruments helps us help you better and faster National Instruments
33. 000 V 42 5 mV Temperature coefficient 5 ppm C maximum 25 wV C maximum Long term stability 15 ppm 4 1 000 hours 75 41 000 hours Explanation of Analog Input Specifications Linear Errors The offset and gain errors on the AT MIO 64F 5 are nulled with calibration DACs These DACs have ranges that are equal to or slightly larger than the ranges of error for which they must compensate If a calibration DAC is adjusted to center scale then the accuracy of the offset or gain that the DAC adjusts is the combined accuracy of the associated analog components and the calibration circuitry does not contribute to inaccuracy However if the setting of a calibration DAC is unknown then the DAC itself must be considered a source of error and its adjustment range is the amount of possible additional error Because of this possible contribution to error by the calibration DACs all gain and offset errors on the AT MIO 64F 5 are specified including the contributions of the calibration DACs The typical temperature coefficients are also given Pregain offset error is the amount of possible voltage offset error in the circuitry before the gain stage Its contribution to total offset error is multiplied by the gain Postgain offset error is the amount of possible voltage offset error in the circuitry following the gain stage Its contribution to total offset error is not multiplied by the gain The total offset error is the postgain offset error plus
34. 2 151 AT MIO 64F 5 User Manual AMD Am9513A Data Sheet Appendix E SWITCHING WAVEFORMS mores aest mores PK Cr 5 E E z 46 79 e Twv NOTE 8 our WF004792 Figure 21 Bus Transter Switching Waveforms Figure 22 Counter Switching Waveforms 2 152 Am9513A AT MIO 64F 5 User Manual E 38 National Instruments Corporation Appendix E AMD Am9513A Data Sheet APPENDIX A Design Hints 1 When a crystal is not being used X1 and X2 should be connected as shown for TTL input Figure A1 and no input Figure A2 2 Recommended oscillator capacitor values are 18 pF on X1 and X2 3 Unused inputs shouid be tied to VCC 4 The TC output can glitch when the counter is loaded For this reason this output should not be connected to edge sensitive interrupts The counter output should be set or cleared after the LOAD command 5 The two most significant bits of the status register are not specified They may be zero or one 6 The mode register should not be modified when the counter is armed 7 The LOAD and HOLD registers should not be changed during TC 8 When using the different clocks for different counters be aware that there is a 75 ns skew between F1 F2 F3 F4 and F5 9 The TC output will remain inactive if programmed to be in the TC TOGGLE mode and the step command is used to increment or decrement the counter The out
35. 2 28 cabling considerations 2 38 digital I O signal connections 2 28 to 2 29 extended analog input signal connections AT MIO 64F 5 PGIA 2 18 mapping channels in different input configurations table 4 28 4 30 signal connection guidelines 2 18 to 2 19 signal descriptions 2 16 D 2 warning against exceeding input ranges 2 19 field wiring considerations 2 37 to 2 38 input configurations common mode signal rejection 2 26 to 2 27 differential connections floating signal sources 2 23 to 2 24 general considerations 2 21 ground referenced signal sources 2 22 recommended configurations for ground referenced and floating signal sources 2 21 single ended connections floating signal RSE sources 2 25 general considerations 2 24 to 2 25 grounded signal NRSE sources 2 26 MIO subconnector 2 13 C 1 signal descriptions 2 14 to 2 16 C 2 to C 3 power connections I O connector 2 30 RTSI switch 5 27 to 5 28 timing connections 2 30 to 2 37 data acquisition timing connections 2 30 to 2 33 general purpose connections 2 33 to 2 37 pins for 2 30 types of signal sources floating signal sources 2 20 ground referenced signal sources 2 20 warning against exceeding ratings 2 11 single analog input channel programming 5 10 single channel data acquisition sequence programming 5 5 to 5 6 single channel data acquisition timing 3 8 to 3 10 See also data acquisition programming posttrigger data acquisition timing 3 9 pretrigger data
36. 4 4 Command Register eee eo neon Ve CERIS EU 4 5 Comiriand Nt dude e dba 4 8 Command Resister 3 edes 4 11 Command Register i 4 16 Status Register Tite curo etes sopa di ica ess 4 19 Status ebd ouis 4 22 Analog Input Register GITOUD 4 23 ADC FIFO Register 4 24 e e ep PUR gies 4 26 Analog Output Register Group setti 4 31 DACO odd a 4 33 DAGI 4 34 ADC Event Strobe Register 0211 111 4 35 CONFIGMEMCLR 4 36 CONFIGMEMLD 4 37 DAO Clear ReBISIGE oed ate a de sped seus 4 38 DAO Start Resister ose ost eto stes 4 39 Single Conversion Reglsletz Meade peus 4 40 DAC Event Strobe Register CIFOUD o oops pp RR SH eu eue guae 4 4 TMRBEQ Clear Reglslet saei e teo a Hitt 4 42 DAG Update Regist r T 4 43 DAC Clear
37. 4 54 Am9513A Command Register 4 53 Am9513A Data Register 4 51 to 4 54 Am9513A Status Register 4 54 programming 5 27 general considerations 5 27 resource allocation considerations 5 1 sample counters 5 12 to 5 14 sample interval counter 5 11 to 5 12 scan interval counter 5 14 to 5 15 update interval counter 5 23 to 5 24 waveform cycle counter 5 24 to 5 25 waveform cycle interval counter 5 25 register map 4 2 resetting after data acquisition operation 5 16 to 5 17 Am9513A System Timing Controller alarm registers and comparators E 11 block diagram E 2 bus transfer switching waveforms E 38 characteristics E 2 command descriptions E 29 to E 32 command summary E 30 connection diagram E 3 count control E 28 count source selection E 29 counter logic groups E 8 counter mode control options E 26 to E 29 counter mode descriptions E 14 to E 26 counter mode operating summary E 14 counter mode register E 11 counter mode register bit assignments E 27 counter output waveforms E 28 counter switching waveforms E 38 crystal input configuration E 40 data bus assignments E 7 data pointer register E 9 data pointer sequencing E 10 data port registers E 11 design hints E 39 detailed description E 8 to E 11 frequency scaler ratios E 13 AT MIO 64F 5 User Manual Index 2 National Instruments Corporation Index GATE SRC configuration suggestion E 40 gating control E 13 general description E 2 hardware retrigg
38. 6 6_ _ 15 ns TGVWH ___ Gate Vaid to Write High Notes 3 10 100 4 _ ___ Reed HgntoC DDontCme TRMEH _____ Read High to Count Source High Notes 4 D ___ 0 _ Read High to Data o Data Bus Release Time TRHRL Read High to Read Low Read Recovery ____________________ _TRHSH Read High to CS High Note 12 es _ Read High to Write Low Read Recovery ___________________ TRLOv Read Low to Data Ou Vid tts TRLOX _____ Read Low to Data Bus Driven Data Bus Drive Time 7 os Read Low to Read High Read Pulse Duraton Note 12 1 ___ TSLAL CS Low to Read Low Note 39 _ __ CS Low to Wate High Note 12 TWHAX Write High to C D Don t Gare dl _TWHOX ___ Write High to Data in Don t Care ts TWHEH Write High to Count Source High Notes 5 7 14 15 __ _ 50 ___ TWHGV Write High to Gate Valid Notes 5 10 34 Write High to Read Low Write Recovery Time Note 16 co fs TWHSH Write High to CS High Note 12 00000 ts TWHWL ___ Write High to Wate Low Write Recovery Time 06646 150 ___ ns ____ Write High to Out Vaid Notes 61000000 2 Write Low to Write High Write Duration Note 12 0 _ 10 _ ___
39. 64F 5 board has gains of 0 5 1 2 5 10 20 50 and 100 and is suited for a wide variety of signal levels With the proper gain setting the full resolution of the ADC can be used to measure the input signal Table 2 4 shows the overall input range and precision according to the input range configuration and gain used AT MIO 64F 5 User Manual 2 6 National Instruments Corporation Chapter 2 Configuration and Installation Table 2 4 Actual Range and Measurement Precision Versus Input Range Selection and Gain Range Configuration Actual Input Range 10 V 0 to 10 0 V 0 to 45 0 V 0 to 2 0 V 0 to 1 0 V 2 44 mV 1 22 mV 488 28 244 14 0 to 0 5 V 122 07 uV 0 to 0 2 V 48 83 0 to 100 0 mV 24 41 5 to 45 V i 10 0 to 10 0 V 4 88 mV 5 0 to 5 0 V 2 44 mV 2 5 to 2 5 V 1 22 mV 1 0 to 1 0 V 488 28 uV 0 5 to 0 5 V 244 14 uV 0 25 to 0 25 V 122 07 100 0 to 100 0 mV 48 83 uV 50 0 to 50 0 mV 24 41 uV The value of 1 LSB of the 12 bit ADC that is the voltage increment corresponding to a change of 1 count in the ADC 12 bit count Note See Appendix A Specifications for absolute maximum ratings Analog Output Configuration The AT MIO 64F 5 supplies two channels of analog output voltage at the I O connector The analog output circuitry is configurable through programming of a register in the board register set The reference and range for the analog output circuitry can be sele
40. 65 537 A 32 bit count mode should be used if the number of A D sample conversions to be performed is greater than or equal to 65 537 4 6 National Instruments Corporation Chapter 4 Register and Descriptions Bit Name Description continued 4 RTSITRIG RTSI Trigger This bit controls multiple board synchronization through RTSI Bus triggering If RTSITRIG is set then triggering of the data acquisition sequence by another National Instruments board over the RTSI bus is enabled Otherwise if RTSITRIG is cleared the data acquisition sequence is triggered by the onboard Start DAQ Register or a high to low transition on the EXTTRIG signal at the I O Connector When this bit is set the local DAQ Start Register and the EXTTRIG signal have no effect 3 0 0 Reserved These bits must always be set to zero National Instruments Corporation 4 7 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 Command Register 2 Command Register 2 contains 15 bits that control AT MIO 64F 5 RTSI bus transceivers analog output configuration and DMA channels A and B selection Bits 8 15 of this register are cleared upon power up and after a reset condition Bits 0 7 of this register are undefined upon power up and are not cleared after a reset condition These bits should be initialized through software Address Base address 02 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 1 0 MSB 7
41. AT MIO 64F 5 Use 760 nnn 1 AMD Am9513A Data Sheet IN N _ EO TC OUTPUT TC TOGGLED OUTPUT MODE Hardware Save avaliabie in Am9513A only cuis cuna curs 2 cura ono cus cma cma cma cw _ Mode X as shown in Figure 15x provides a hardware sampling of the counter contents without interrupting the count A LOAD AND ARM command or a LOAD command followed by an ARM command is required to initialize the counter Once armed a Gate edge starts the counting operation Gate edges applied to a disarmed counter are disregarded After application of the Triggering Gate edge the Counter will count all qualified source edges until the first TC irrespective of the gate level All gate edges applied during the Counting sequence will store the current count in the Hold register but they will not interrupt the counting sequence On each TC the counter will be reloaded from the Load register and stopped Subsequent counting requires a new triggering Gate edge counting resumes on the first source edge following the triggering Gate edge Note Mode X is only available in the Am9513A devices COUNTER MODE CONTROL OPTIONS Each Counter Logic Group includ
42. DIG GND DIG GND 2 16 Chapter 2 Description continued External Timer Trigger If selected a high to low edge on EXTTMRTRIG results in the output DACs being updated with the value written to them in the posted update mode EXTTMRTRIG will also generate a timed interrupt if enabled GATE2 This pin is from the Am9513A Counter 2 signal OUTPUT This pin is from the Am9513A Counter 2 signal SOURCES This pin is from the Am9513A Counter 5 signal GATES This pin is from the Am9513A Counter 5 signal OUTS This is from the Am9513A Counter 5 signal Frequency Output This pin is from the Am9513A FOUT signal National Instruments Corporation Chapter 2 Configuration and Installation Extended Analog Input Subconnector Pin Assignment Figure 2 5 shows the pin assignment for the 50 pin extended analog subconnector 16 17 18 19 20 21 22 23 24 25 26 27 AI SENSE ACH28 ACH29 ACH30 ACH31 ACH32 ACH33 ACH34 ACH35 ACH36 ACH37 ACH38 ACH39 Figure 2 5 Extended Analog Input Subconnector Pin Assignment National Instruments Corporation 2 17 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 Extended Analog Input Subconnector Signal Descriptions Pin Signal Name Reference Description 1 24 lt 16 27 gt AI GND Analog Input Channels 16 through 27 and lt 40 51 gt 51 AI GN
43. DIG GND DIG GND DIG GND C 2 Description Analog Input Ground These pins are the reference point for single ended measurements and the bias current return point for differential measurements Analog Input Channels 0 through 15 In differential mode the input is configured for up to eight channels In single ended mode the input is configured for up to 16 channels Analog Input Sense This pin serves as the reference node when the board is in NRSE configuration If desired this signal can be programmed to be driven by the board analog input ground in the DIFF and RSE analog input modes Analog Channel 0 Output This pin supplies the voltage output of analog output channel 0 Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 External Reference This is the external reference input for the analog output circuitry Analog Output Ground The analog output voltages are referenced to this node Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply Digital I O port A signals Digital I O port B signals 5 VDC Source These pins are fused for up to 1 A of 5 V supply National Instruments Corporation Appendix Pin 36 37 38 39 40 41 42 43 44 Signal Name SCANCLK EXTSTROBE EXTTRIG EXTGATE EXTCONV SOURCEI GATEI OUTI EXTTM
44. I O connector If this bit is cleared the internal 10 Vref is used for the DAC 0 reference EISA Computer DMA This bit controls the type of DMA transfer from the ADC FIFO on an EISA computer If EISA DMA is clear single transfer DMA mode is used If EISA_DMA is set demand mode DMA is used This bit should only be set if the AT MIO 64F 5 is installed in an EISA type computer Reserved This bit must always be set to zero DMA Channel B Select These bits select the secondary DMA channel for use by the AT MIO 64F 5 See Table 4 2 DMA Channel A Select These bits select the primary DMA channel for use by the AT MIO 64F 5 See Table 4 2 National Instruments Corporation 4 9 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 Table 4 2 DMA Channel Selection Bit Pattern Effect Bit Pattern Effect Secondary DMA Channel Selected B Primary DMA Channel Selected A BRIA DWAChmedl BNA DWA Cm oeie L DMA Channels DWA Chanel BRIA MA Channel 0 MA Channel 1 MA Channel 2 MA Channel 3 No effect MA Channel 5 MA Channel 6 MA Channel 7 a EEDEEEDEETSTS EHE DUE EEDEEEDEETSTSS 2 2 2 2 AT MIO 64F 5 User Manual 4 10 National Instruments Corporation Chapter 4 Register and Descriptions Command Register 3 Command Regi
45. MIO 64F 5 Board in the NRSE Input Configuration Figure 2 10 Single Ended Input Connections for Ground Referenced Signals Common Mode Signal Rejection Considerations Figures 2 7 and 2 10 located earlier in this chapter show connections for signal sources that are already referenced to some ground point with respect to the AT MIO 64F 5 In these cases the PGIA can reject any voltage caused by ground potential differences between the signal source and the AT MIO 64F 5 In addition with differential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the AT MIO 64F 5 AT MIO 64F 5 User Manual 2 26 National Instruments Corporation Chapter 2 Configuration and Installation The common mode input range of the AT MIO 64F 5 PGIA is defined as the magnitude of the greatest common mode signal that can be rejected The PGIA can reject common mode signals as long as and jn are both in the range 12 V Thus the common mode input range for the AT MIO 64F 5 depends on the size of the differential input signal V aiff The exact formula for the allowed common mode input range is as follows Voem max 12 V Vaitt 2 With a differential voltage of 10 V the maximum possible common mode voltage is x7 V The common mode voltage is measured with respect to the AT MIO 64F 5 ground and can be calculated by the following formula Vti V em actual 2
46. These bits must always be set to zero 7 4 BDIO lt 3 0 gt These four bits control the digital lines BDIO lt 3 0 gt The bit DIOPBEN in Command Register 3 must be set for BDIO lt 3 0 gt to be driven onto the digital lines BDIO lt 3 0 gt 3 0 ADIO lt 3 0 gt These four bits control the digital lines ADIO lt 3 0 gt The bit DIOPAEN in Command Register 3 must be set for ADIO lt 3 0 gt to be driven onto the digital lines ADIO lt 3 0 gt National Instruments Corporation 4 57 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 RTSI Switch Register Group The two registers making up the RTSI Switch Register Group allow the AT MIO 64F 5 RTSI switch to be programmed for routing of signals on the RTSI bus trigger lines to and from several AT MIO 64F 5 signal lines The RTSI switch is programmed by shifting a 56 bit routing pattern into the RTSI switch and then loading the internal RTSI Switch Control Register The routing pattern is shifted into the RTSI switch by writing one bit at a time to the RTSI Switch Shift Register The RTSI Switch Control Register is then loaded by writing to the RTSI Switch Strobe Register Bit descriptions of the two registers making up the RTSI Switch Register Group are given on the following pages AT MIO 64F 5 User Manual 4 58 National Instruments Corporation Chapter 4 Register and Descriptions RTSI Switch Shift Register The RTSI Switch Shift Register is written to in
47. This bit controls multiple channel scanning during data acquisition If SCANEN is set and DAQEN is also set alternate analog input channels are sampled during data acquisition under control of the channel configuration memory If SCANEN is cleared and DAQEN is set a single analog input channel is sampled during the entire data acquisition operation When SCANEN is set the SCANCLK signal at the I O connector is enabled Otherwise it is disabled Scan Mode 2 This bit selects the data acquisition scanning mode used when scanning multiple A D channels If SCN2 is set and SCANEN and DAQEN are set interval channel scanning is used In this mode scan sequences occur during a programmed time interval called a scan interval One cycle of the scan sequence occurs during each scan interval If SCN2 is cleared and SCANEN and DAQEN are set continuous channel scanning is used In this mode scan sequences are repeated with no delays between cycles 32 or 16 Bit Sample Count This bit selects the count resolution for the number of A D conversions to be performed in a data acquisition operation If CNT32 16 is cleared a 16 bit count mode is selected and Counter 4 of Am9513A Counter Timer controls conversion counting If CNT32 16 is set a 32 bit count mode is selected and Counter 4 is concatenated with Counter 5 to control conversion counting A 16 bit count mode can be used if the number of A D sample conversions to be performed is less than
48. access the recently saved Hoid register data Many systems will use the saving gate edge to interrupt the host CPU In systems such as this the interrupt service routine should issue a Load Data Pointer command prior to reading the saved data Status Register The 8 bit read only Status register indicates the state of the Byte Pointer bit in the Data Pointer register and the state of the Am9513A E 10 mand The following rules should be kept in mind regarding Appendix E National Instruments Corporation Appendix E OUT signal for each of the general counters See Figures 10 and 17 The OUT signals reported are those internal to the chip after the polarity select logic and just before the three state interface buffer circuitry Bits SR6 and SR7 may be 0 or t The Status register OUT bit reflects an active high or active low TC output or a TC Toggled output as programmed in the Output Control Field of the Counter Mode register That is it reflects the exact state of the OUT pin When the low impedance to Ground Output option CM2 CMO 000 is selected the Status register will reflect an active high TC Output When a high impedance Output option CM2 CMO 100 is selected the Status register will reflect an active low TC output For Counters 1 and 2 the OUT pin will reflect the comparator output if the comparators are enabled The Status register bit and OUT are active high if CM2 0 and active lo
49. acquisition timing 3 10 sample interval timer 3 8 to 3 9 specifications A 4 Single Conversion Register 4 40 single conversions programming flow chart 5 4 generating single conversions 5 5 reading single conversion result 5 5 National Instruments Corporation Index 21 AT MIO 64F 5 User Manual Index using SCONVERT or EXTCONV signal 5 4 single ended connections floating signal RSE sources 2 25 general considerations 2 24 to 2 25 grounded signal NRSE sources 2 26 single ended input configuration NRSE input 64 channels 2 7 RSE input 64 channels 2 7 single read timing 3 8 software optional 1 3 SOURCE OUT and GATE timing signals 2 33 to 2 37 3 21 to 3 22 3 24 SOURCE signal 2 15 C 3 SOURCES signal 2 16 C 3 specifications Am9513A System Timing Controller E 33 to E 37 analog data acquisition rates A 4 to A 5 analog input A 1 to A 4 analog output A 5 to A 6 digital I O A 7 operating environment A 7 physical characteristics A 7 power requirements A 7 storage environment A 7 timing I O A 7 square waves producing 2 33 SRC3SEL bit 4 18 SRC3SEL signal 5 23 Status Register 1 4 19 to 4 21 Status Register 2 4 22 5 26 storage environment specifications A 7 straight binary mode A D conversion values 4 24 to 4 25 switch settings See jumpers and switches system noise A 4 T technical support F 1 theory of operation analog input circuitry 3 6 to 3 7 A D converter 3 6 ADC FIFO buff
50. analog input channels are available Single ended input connections can be used when all input signals meet the following criteria Input signals are high level greater than 1 V e Leads connecting the signals to the AT MIO 64F 5 are less than 15 ft e All input signals share a common reference signal at the source or are floating DIFF input connections are recommended for greater signal integrity if any of the preceding criteria are not met AT MIO 64F 5 User Manual 2 24 National Instruments Corporation Chapter 2 Configuration and Installation The AT MIO 64F 5 can be software configured for two different types of single ended connections RSE configuration and configuration The RSE configuration is used for floating signal sources in this case the AT MIO 64F 5 provides the reference ground point for the external signal The NRSE input configuration is used for ground referenced signal sources in this case the external signal supplies its own reference ground point and the AT MIO 64F 5 should not supply one In single ended configurations more electrostatic and magnetic noise couples into the signal connections than in differential configurations Moreover the amount of coupling varies among channels especially if a ribbon cable is used The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of
51. be reloaded from the reload source selected by the Gate Following the second an ARM command is required to start a new counting cycle Mode S is shown in Figure 155 2 138 AT MIO 64F 5 User Manual MODE V Frequency Shift Keying Mode V shown in Figure 15v provides frequency shift keying modulation capability Gate operation in this mode is identical to that in Mode S TC induced reload will reload the counter from the Load register If the Gate is HIGH LOADs and reloads will occur from the Hold register The polarity of the Gate only selects the reload source it does not start or modulate counting Once armed the counter will count repetitively to TC On each TC the counter will reload itself trom the register determined by the polarity of the Gate Counting will continue in this manner until DISARM command is issued to the counter Frequency shift keying may be obtained by specifying a TC Toggled Output mode in the Counter Mode register The switching of frequencies is achieved by modulating the Gate Am9513A E 24 if the Gate is Low a LOAD command or a Appendix E National Instruments Corporation Appendix E AMD Am9513A Daia Sheet AVAVAVAVAVAVAVAYVAVAVAVAVAN AX TOOQLED oureut Figure 15s Mode S Waveforms XXX Figure 15v Mode Waveforms Am9513A National Instruments Corporation E 25
52. bit DACs CALDAC lt 0 7 gt on AT MIO 64F 5 that are used for calibration These DACs are described in Table 6 2 Table 6 2 Calibration DACs Analog DAC Function Adjustment Incremental Range Effect CALDACO Pregain offset trim CALDAC1 Postgain offset trim CALDAC2 Unipolar offset trim CALDAC3 Gain trim CALDAC4 DACO offset trim CALDACS DACO gain trim CALDAC6 DAC offset trim CALDAC7 DAC gain trim National Instruments Corporation 6 5 AT MIO 64F 5 User Manual Calibration Procedures Chapter 6 Calibration Channels Table 6 3 lists the calibration channels for the AT MIO 64F 5 showing what connects to each input of the PGIA when each channel is selected To measure these channels the board must be in Calibration mode See Chapter 4 Register Map and Descriptions for more information Table 6 3 Calibration Channels Effect PGIA 4 PGIA Reference Calibration The AT MIO 64F 5 has a stable voltage reference to which gain can be calibrated The value of this voltage reference is determined through the reference calibration routine which requires a known external voltage between 5 and 9 99 V to be connected differentially on any desired input channel The routine calibrates the circuitry to the external reference and then reads the internal reference This value is stored as a two s complement binary number in the onboard EEPROM for subsequent use by the analog input calibration routines Bec
53. channel with SC 205X cable Custom Cables The AT MIO 64F 5 I O connector is a 100 pin male ribbon cable header The manufacturer part number for this header is as follows e Robinson Nugent part number P50E 100P1 SR1 TG The mating connector for the AT MIO 64F 5 is a 100 position polarized ribbon socket connector This connector breaks out into two 50 pin female connectors with 50 conductor ribbon cables via a cable assembly National Instruments uses a keyed connector to prevent inadvertent upside down connection to the AT MIO 64F 5 The recommended manufacturer part number for this mating connector is as follows e Robinson Nugent part number P25E 100 5 TG Figure 1 2 shows the AT MIO 64F 5 cable assembly National Instruments Corporation 1 5 AT MIO 64F 5 User Manual Introduction Chapter 1 50 Pin MIO Subconnector Extended Analog Input 50 Pin Subconnector AT MIO 64F 5 Board n i AT MIO 64F 5 I O Connector 100 Pin Primary Figure 1 2 AT MIO 64F 5 Cable Assembly Recommended manufacturer part numbers for the standard ribbon cable 50 conductor 28 AWG stranded that can be used with these connectors are as follows e Electronic Products Division 3M part number 3365 50 T amp B Ansley Corporation part number 171 50 You can plug a polarizing key into these edge connectors to prevent inadvertent upside down connection to the I O module rack The location of this key varies from
54. configuration memory is set up the first value must be preloaded by accessing the CONFIGMEMLD Register Writing to the CONFIGMEM Register following a CONFIGMEMCLR automatically sequences into the memory list for multiple channel configuration values Writing can continue until the end of the channel configuration list is reached or the memory becomes full After the final write to the channel configuration memory the CONFIGMEMLD Register should be strobed to load the first channel configuration value At this point the channel configuration memory is primed and does not need to be accessed again until a new channel configuration sequence is desired Conversions either by EXTCONV or by Counter 3 of the Am9513A Counter Timer automatically sequence through the channel configuration memory as programmed When the end of the channel configuration memory is detected it is automatically reset to the first value in the list Strobing the DAQ Clear Register also resets the channel configuration memory to the first value in the list without destroying existing channel configuration values A strobe of the CONFIGMEMLD Register is still necessary to load the first value in the memory Continual strobing of the CONFIGMEMLD Register with only one value in the list serves only to reload this one value Continual strobing with more than one value in the memory sequences through the channel configuration list In the single channel data acquisition mode only
55. configured for up to 32 channels with ACH lt 16 27 gt and ACH lt 40 51 gt representing differential Channels 16 through 27 and 40 through 51 In the RSE and NRSE modes the input is configured for up to 64 channels with ACH lt 16 27 gt as Channels 16 through 27 and ACH lt 40 51 gt as Channels 40 through 51 25 AI SENSE AI GND Analog Input Sense This pin serves as the reference mode when the board is in NRSE configuration If desired this signal can be programmed to be driven by the board analog input ground 26 AI GND N A Analog Input Ground These pins are the reference point for single ended measurements and the bias current return point for differential measurements 27 50 lt 28 39 gt AI GND Analog Input Channels 28 through 39 and ACH 52 63 AI GND 52 through 63 In the DIFF mode ACH lt 28 39 gt ACH lt 52 63 gt represent differential Channels 28 through 39 In the RSE and NRSE modes ACH lt 28 39 gt represent Channels 28 through 39 and ACH lt 52 63 gt represent Channels 52 through 63 AT MIO 64F 5 User Manual D 2 National Instruments Corporation Appendix E AMD Am9513A Data Sheet This appendix contains the manufacturer data sheet for the AMD Am9513A System Timing Controller integrated circuit Advanced Micro Devices Inc This controller is used on the AT MIO 64F 5 Copyright O Advanced Micro Devices Inc 1989 Reprinted with permission of copyright owner All rights reser
56. count is 10000 65 536 decimal write 0 to the Am9513A Data Register Write 48 to the Am9513A Command Register to load Counter 4 Write FFF4 to the Am9513A Command Register to decrement Counter 4 clou I Write FF28 to the Am9513A Command Register to arm Counter 4 8 Clear the CNT32 16 bit in Command Register 1 to notify the hardware that only Counter 4 will be used as the sample counter After you complete this programming sequence Counter 4 is configured to count A D conversion pulses generated by Counter 3 and turns off the data acquisition operation when Counter 4 decrements to zero Sample Counts Greater than 65 536 To program the sample counter for sample counts greater than 65 536 use the following programming sequence to concatenate Counter 4 to Counter 5 The lower 16 bits of the sample count are stored in Counter 4 and the upper 16 bits of the sample count are stored in Counter 5 writes are 16 bit operations All values given are hexadecimal 1 Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register 2 Write 1025 to the Am9513A Data Register to store the Counter 4 mode value for posttrigger acquisition modes Write 9025 to the Am9513A Data Register to store the Counter 4 mode value for pretrigger acquisition modes 3 Write FFOC to the Am9513A Command Register to select the Counter 4 Load Register National Instruments Corporation 5 13 AT MIO 64F 5 User Manual Programming Chap
57. counter is needed Counter 4 of the Am9513A Counter Timer is used If more than 16 bits are needed Counter 4 is concatenated with Counter 5 of the Am9513A to form a 32 bit counter The sample counter decrements its count each time the sample interval counter generates an A D conversion pulse and the sample counter stops the data acquisition process when it counts down to zero The sample counter can also be used to count conversions generated by external conversion signals The configuration memory register is set up to select the analog input channel and configuration before data acquisition is initiated for a single channel data acquisition sequence These settings remain constant during the entire data acquisition process therefore all A D conversions are performed on a single channel Single channel acquisition is enabled through a register in the AT MIO 64F 5 register set The data acquisition process can be initiated via software or by applying an active low pulse to the EXTTRIG input on the AT MIO 64F 5 I O connector Figure 3 5 shows the timing of a typical single channel data acquisition sequence Trigger DAQPROG CONVERT qc SampleCTR 9 X8X7TX6XSX4X3X2KL XX 9 DAQCMPIT Interrupt __ LSS DAQCLEAR 55 13 55 Figure 3 5 Single Channel Posttrigger Data Acquisition Timing In this sequence the sample interval counter Counter 3 is programmed to generate conversion signals only under a certain ga
58. counter must be armed before it will function Application of a Gate edge to the armed counter will enable counting When the counter reaches it will reload itself from the Load register The counter will then stop counting awaiting a new Gate edge Note that unlike Mode a new ARM command is not needed after TC a new Gate edge After application of a triggering Gate edge the Gate input is disregarded until TC MODE G Sottware Triggered Delayed Puise One Shot eua cus cw cni ove in Mode G the Gate does not affect the counter s operation Once armed the counter will count to TC twice and then automatically disarm itself For most applications the counter will initially be loaded from the Load register either by a LOAD command or by the last TC of an earlier timing cycie Upon Counting to the first TC the counter will reload itself from the Hold register Counting will proceed until the second TC when the counter will reload itself from the Load register and automatically disarm itself inhibiting further counting Counting can be resumed by issuing a new ARM command A software triggered delayed pulse one shot may be generated by speci fying the TC Toggled output mode in the Counter Mode register The initial counter contents control the delay from the ARM command until the output pulse starts The Hold register contents control the puise duration
59. counter will cease all counting independent of other conditions The only exception to this is that a counter in the TC state will always count once in order to leave TC before DISARMing This count may be generated by a source edge by a LOAD or LOAD AND ARM command the LOAD AND ARM command will negate the DISARM command or by a STEP command A disarmed counter may be updated using the LOAD command and may be read using the SAVE command A count process may be resumed using an ARM command See the ARM command description for further details Save Counters Coding 1 S5 S4 53 S2 51 Description Any combination of counters as specified by S field will have their contents transferred into their associated Hold register The transfer takes place without interfering with any counting that may be underway This command will overwrite any previous Hold register contents The SAVE command is designed to aliow an accumulated count to be preserved so that it can be read by the host CPU at some later time Disarm and Save Counters Coding 07 C6 C5 C4 C3 Ci CO 1200 55 54 53 52 Sij AMD Am9513A Data Sheet Description Any combination of counters as specified by the field will be disarmed and the contents of the counter will be transferred into the associated Hold registers This com mand is identical to issuing a DISARM command followed by a SAVE command Set TC Toggle Output Coding C7 C6 C5 C4
60. edge trigger is applied to the EXTTRIG pin The acquisition then completes when the sample counter decrements to zero This mode acquires data both before and after a hardware trigger is received The minimum pulse width allowed is 50 nsec The first A D conversion starts within one sample interval from the high to low edge The sample interval is controlled by Counter 3 or EXTCONV There is no maximum pulse width limitation however EXTTRIG should be high for at least 50 nsec before going low The EXTTRIG signal is one HCT load and is pulled up to 5 V through a 10 resistor The EXTTRIG signal is logically ANDed with the internal DAQSTART signal If a data acquisition sequence is to be initiated with an internal trigger EXTTRIG must be high at both the I O connector and the RTSI switch If EXTTRIG is low the sequence will not be triggered In addition triggers from the EXTTRIG signal can be inhibited through programming of a register in the AT MIO 64F 5 register set Signal EXTGATE is an input signal used for hardware gating EXTGATE controls A D conversion pulses If EXTGATE is low no A D conversion pulses occur from EXTCONV or the sample interval counter If EXTGATE is high conversions take place if programmed and otherwise enabled EXTTMRTRIG Signal The analog output DACs on the AT MIO 64F 5 can be updated using either internal or external signals in posted update mode The DACS can be updated extern
61. enabled interrupts or DMA requests are generated until the DAC FIFO is full DAC FIFO Half Full Flag This bit reflects the state of the DAC FIFO If DACFIFOHF is clear the DAC FIFO is at least half full of data If DACFIFOHF is set the DAC FIFO is not half full of data If the appropriate DAC and I O modes are enabled interrupts or DMA requests are generated when the DAC FIFO is less than half full DAC FIFO Empty Flag This bit reflects the state of the DAC FIFO If DACFIFOEF is clear the DAC FIFO is empty If DACFIFOEF is clear before the last point has been transferred to the DACs and DACCOMP is set this 15 an error condition and should be handled appropriately If DACFIFOEF is set then the DAC FIFO has at least one remaining point to be transferred EEPROM Data This bit reflects the value of the data shifted out of the EEPROM using SCLK with EEPROMCS enabled EEPROM Chip Deselect This bit reflects the status of the EEPROM chip select pin Because protection circuitry surrounds the EEPROM having EEPROMCS enabled in Command Register 1 does not necessarily result in the EEPROM being enabled If EEPROMCD is low after a mode has been shifted into the EEPROM an error occurred in shifting in an unsupported mode To initialize EEPROMCD EEPROMCS must be brought low while SCLK is pulsed high Configuration Memory Empty Flag This bit indicates the status of the channel configuration memory If this bit is clear
62. full PC I O channel 16 bit DMA transfers DMA channels 5 6 and 7 of the PC I O channel are available for such transfers DMA channels 0 1 2 and 3 are available for 16 bit transfers on EISA computers only and not on PC AT and compatible computers With the DMA circuitry either single channel transfer mode or dual channel transfer mode can be selected for DMA transfer These DMA channels are selectable from one of the registers in the AT MIO 64F 5 register set Analog Input and Data Acquisition Circuitry The AT MIO 64F 5 handles 64 channels of analog input with software programmable configuration and 12 bit A D conversion In addition the AT MIO 64F 5 contains data acquisition configuration for automatic timing of multiple A D conversions and includes advanced options such as external triggering gating and clocking Figure 3 3 shows a block diagram of the analog input and data acquisition circuitry AT MIO 64F 5 User Manual 3 4 National Instruments Corporation Theory of Operation Chapter 3 puueyp 081 DOIHNOO eSAMINHINDIHNOO cl vied ANOO da quv UOISU9 Xd 916 OJIA OAY Surun uonismboy vq En m pC uonensrguo pouueyo mo 418 SOVG 8085002 298811 PUNXA AUO eUIO XA ANOOLXH XN IONVOS S9uo
63. gt bit for selecting waveform modes 4 17 FIFO continuous cyclic waveform generation 3 17 FIFO programmed cyclic waveform generation 3 18 FIFO pulsed waveform generation 3 18 to 3 19 immediate updating of DACs 3 14 to 3 15 posted DAC update timing illustration 3 16 posted update mode 3 14 to 3 15 selecting waveform modes with DACMB lt 3 0 gt bits 4 17 waveform circuitry illustration 3 15 waveform timing circuitry 3 16 to 3 17 DACO OUT signal 2 14 2 27 to 2 28 C 2 DACO Register 4 33 DACODSP bit 4 17 DACOREQ bit 4 14 OUT signal 2 14 2 27 to 2 28 C 2 DACI Register 4 34 DACIDSP bit 4 17 DACIREQ bit 4 14 DACCMPLINT bit 4 12 DACCOMP bit 4 21 5 23 5 26 DACFIFOEF bit 4 21 5 26 DACFIFOFF bit 4 21 5 30 DACFIFOHF bit 4 21 5 30 DACFIFORT signal 3 17 DACGATE bit 4 17 DACMB lt 3 0 gt bit 4 17 DACs analog output circuitry 3 13 immediate updating 3 14 to 3 15 output configuration 3 14 posted updating 3 15 DAQ Clear Register 4 38 5 10 5 30 5 31 DAQ Start Register 4 39 DAQCMPLINT bit 4 12 DAQCOMP bit 4 19 5 31 DAQEN bit 4 6 5 8 5 9 DAQPROG bit 4 19 data acquisition programming 5 10 to 5 26 analog input circuitry 5 4 to 5 10 analog output circuitry 5 18 applying a trigger 5 15 to 5 16 channel scanning 5 7 to 5 10 continuous channel scanning 5 7 to 5 8 interval channel scanning 5 8 to 5 10 clearing analog input circuitry 5 10 cyclic waveform ge
64. how much the electric field differs between the two conductors Referring to the MIO subconnector for example if AI GND is used as the signal reference Channels 0 and 8 are the quietest and Channels 7 and 15 are the noisiest AI GND is on pins 1 and 2 which are very close to pins 3 and 4 which are Channels 0 and 1 On the other hand Channels 7 and 15 are on pins 17 and 18 which are the farthest analog inputs from AI GND The sensitivities to noise of the other channels in the middle are between those of Channels 0 and 15 and vary according to their distance from AI GND If AI SENSE is used asa reference instead of AI GND the sensitivity to noise still varies among the channels but in this case according to their distance from AI SENSE pin 19 so Channel 15 is the least sensitive and Channel is the most sensitive Single Ended Connections for Floating Signal Sources RSE Configuration Figure 2 9 shows how to connect a floating signal source to an AT MIO 64F 5 board configured for single ended input The AT MIO 64F 5 analog input circuitry must be configured for RSE input to make these types of connections Configuration instructions are included in Chapter 4 Register Map and Descriptions Nonreferenced or Floating Signal Source Input Multiplexer AI SENSE Measured AI GND m Voltage AT MIO 64F 5 Board in the RSE Input Configuration Connector Figure 2 9 Single Ended Input Connections for Nonreferenced or Flo
65. in the last entry of the scan sequence loaded into the channel configuration memory More than one occurrence of the CHAN LAST bit is possible in the configuration memory list for the interval scanning mode For example there can be multiple scan sequences in one memory list AT MIO 64F 5 User Manual 4 28 National Instruments Corporation Chapter 4 Register and Descriptions Bit Name Description continued ICHAN GHOST Channel Ghost This bit is used to synchronize conversions for multiple rate channel scanning When this bit is set in any channel configuration value the conversion occurs on the selected channel but the value is not saved in the ADC FIFO In addition if the sample counter is programmed to count samples from Source 4 conversions with the CHAN GHOST bit set are not counted When the CHAN GHOST bit is clear conversions occur normally and are saved in the ADC FIFO OCHAN DSP Channel DSP This bit is used to flag channel data that is to be serially sent over the RTSI bus to the AT DSP2200 If the CHAN DSP bit is set the associated channel conversion data is sent over the RTSI bus If CHAN DSP is clear channel conversion data is not sent The CHAN bit has no bearing on whether or not the channel conversion data is stored in the ADC FIFO That is controlled by the CHAN_GHOST bit Writing to the channel configuration memory must be preceded with a strobe to the CONFIGMEMCLR Register After the channel
66. input 32 channels 2 6 to 2 7 input mode 2 6 to 2 7 input polarity and range 2 8 National Instruments Corporation Index 3 AT MIO 64F 5 User Manual Index NRSE input 64 channels 2 7 RSE input 64 channels 2 7 theory of operation 3 6 Analog Input Register Group 4 23 to 4 30 ADC FIFO Register 4 24 to 4 25 5 5 5 16 5 31 CONFIGMEM Register 4 26 to 4 30 5 10 5 11 register map 4 1 analog input signal connections See also signal connections extended analog input subconnector mapping channels in different input configurations table 4 28 4 30 signal connection guidelines 2 18 to 2 20 signal descriptions 2 18 D 2 MIO subconnector signal descriptions 2 14 to 2 16 pin assignments AT MIO 64F 5 I O connector 2 12 B 1 extended analog input subconnector 2 17 D 1 MIO subconnector 2 13 C 1 warning against exceeding input ranges 2 19 analog input specifications linear errors 2 to 3 equivalent gain and offset errors in 12 bit systems A 3 gain error A 2 to A 3 postgain offset error A 2 pregain offset error A 2 list of specifications A 1 to A 2 noise 4 nonlinear errors 3 to 4 differential nonlinearity A 4 integral nonlinearity A 3 relative accuracy A 3 overvoltage protection A 4 system noise A 4 analog output circuitry 3 12 to 3 14 block diagram 3 13 calibration 3 14 circuitry 3 13 clearing 5 23 configuration 3 14 programming 5 18 analog output configuration 2 9 polarity sel
67. is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 kQ to 1 If the source has high output impedance you should balance the signal path as described above using the same value resistor on both the positive and negative inputs and you should be aware that there is some gain error from loading down the source The PGIA obtains its input DC bias currents from the DC paths to ground These currents are typically less than 200 pA and do not contribute significantly to error in most applications If the source is DC coupled the resulting DC offset is less than 200 pA times the DC source resistance For instance a 1 kQ source will produce no more than 0 2 of input offset 0 01 LSB at a gain of 100 If the source is AC coupled then the resulting DC offset is less than 200 pA times the sum of the two bias resistors For example if two 100 bias resistors are used there could be as much as 40 of input offset voltage 1 6 LSB at a gain of 100 Single Ended Connection Considerations Single ended connections are those in which all AT MIO 64F 5 analog input signals are referenced to one common ground The input signals are tied to the positive input of the PGIA and their common ground point is tied to the negative input of the PGIA When the AT MIO 64F 5 is configured for single ended input up to 64
68. is referenced to the AT MIO 64F 5 ground The AT MIO 64F 5 ADC measures this output voltage when it performs A D conversions signals must be referenced to ground either at the source device or at the AT MIO 64F 5 If you have a floating source the AT MIO 64F 5 should reference the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors see the Differential Connections for Nonreferenced or Floating Signal Sources section later in this chapter If you have a grounded source the AT MIO 64F 5 should not reference the signal to AI GND The AT MIO 64F 5 board avoids this reference by using the DIFF or NRSE input configurations Types of Signal Sources When configuring the input mode of the AT MIO 64F 5 and making signal connections you must first determine whether the signal source is floating or ground referenced These two types of signals are described in the following sections Floating Signal Sources A floating signal source is one that is not connected in any way to the building ground system but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolator outputs and isolation amplifiers An instrument or device that provides an isolated output falls into the floating signal source category The ground reference of a floating signal must be tied to the AT MIO 64E5 analog input groun
69. nsec after the source signal rising or falling edge Field Wiring Considerations Accuracy of measurements made with the AT MIO 64F 5 can be seriously affected by environmental noise if proper considerations are not taken into account when running signal wires between signal sources and the AT MIO 64F 5 board The following recommendations apply mainly to analog input signal routing to the AT MIO 64F 5 board although they are applicable for signal routing in general You can minimize noise pickup and maximize measurement accuracy by doing the following Use differential analog input connections to reject common mode noise Use individually shielded twisted pair wires to connect analog input signals to the AT MIO 64F 5 With this type of wire the signals attached to the and CH inputs are twisted together and then covered with a shield This shield is then connected only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference e Route signals to the AT MIO 64F 5 carefully Keep cabling away from noise sources The most common noise source in a PC data acquisition system is the video monitor Separate the monitor from the analog signals as much as possible The following recommendations apply for all signal connections to the AT MIO 64F 5 Separate AT MIO 64F 5 signal lines from high current or high voltage
70. nsec minimum tout 300 nsec maximum Figure 2 19 General Purpose Timing Signals The GATE and OUT signal transitions in Figure 2 19 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram with the source signal inverted and referenced to the falling edge of the source signal applies to the case in which the counter is programmed to count falling edges The signal applied at a SOURCE input can be used as a clock source by any of the Am9513A counter timers and by the Am9513A frequency division output FOUT The signal applied to a SOURCE input must not exceed a frequency of 6 MHz for proper operation of Am9513A The Am9513A counters can be individually programmed to count rising or falling edges of signals applied at any of the Am9513A SOURCE or GATE input pins In addition to the signals applied to the SOURCE and GATE inputs the Am9513A generates five internal timebase clocks from the clock signal supplied by the AT MIO 64F 5 This clock signal is selected by a register in the AT MIO 64F 5 register set and then divided by 10 The default value is 1 MHz into the Am9513A 10 MHz clock signal on the AT MIO 64F 5 The five internal timebase clocks can be used as counting sources and these clocks have a maximum AT MIO 64F 5 User Manual 2 36 National Instruments Corporation Chapter 2 Configuration and Installation skew of 75
71. on the second channel and gain setting and so on The last entry written to the channel configuration memory must have the CHAN_LAST bit set This bit marks the end of the scan sequence After the last conversion is performed the scan sequence starts over If there are N entries in the channel configuration memory every Nth conversion in the data collected is performed on the same channel gain mode and range setting Multiple conversions can be performed on each entry in the channel configuration memory before incrementing to the next entry in the scan sequence If the SCANDIV bit in Command Register 1 is set the channel configuration memory increments to the next entry when an active low pulse is detected on the Am9513A Counter Timer OUTI signal If the SCANDIV bit is cleared the channel configuration memory is incremented to the next entry after every conversion The channel configuration memory must be loaded with the desired scan sequence before data acquisition begins To load the channel configuration memory perform the following write operations where N is the number of entries in the scan sequence Strobe the CONFIGMEMCLR Register e Fori 0 to N 1 use the following steps a Write the desired analog channel selection and gain setting to the CONFIGMEM Register this loads the configuration memory at location i b Ifi 2 N 1 also set the CHAN LAST bit when writing to the CONFIGMEM Register Strobe the CONFIGMEMLD Re
72. or execution of a STEP command In modes which alternate reload sources Modes G L the ARMing operation is used as a reset for the logic which 2 144 AT MIO 64F 5 User Manual Figure 19 Am9513A Command Summary Ser ants Ener bus Teepe bee p Gem Data Pomor Sequencing Gear mie Gate on FOU Lp eer Lit Lt Gear Emer Sat bes SETTLE eT 5 Eme Prisc for Ws operations determines which reload source to use on the upcoming TC Following each ARM or LOAD AND ARM command a counter in one of these modes will reload from the Hold register on the first TC and alternate reload sources thereafter reload from the Load register on the second TC the Hold register on the third etc Load Counters Coding C7 C6 C5 C4 C2 Ci CO Description Any combination of counters as specified in the S field will be loaded with previously entered values The source of inf tmation for each counter will be either the associated Load register or the associated Hold register as determined by the operating configuration in the Mode register The Load Hold contents are not changed This command will cause a transfer independent of any current operating configuration for the counter It will often be used as a software retrigger or as counter initialization prior to active hardware gating 1f a LOAD or LOAD AND AR
73. order to load the RTSI switch internal 56 bit Control Register with routing information for switching signals to and from the RTSI bus trigger lines The RTSI Switch Shift Register is a 1 bit register and must be written to 56 times to shift the 56 bits into the internal register Address Base address hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 pm ms MSB LSB Bit Name Description 7 1 0 Reserved These bits must always be set to zero ORSI RTSI Switch Serial Input This bit is the serial input to RTSI switch Each time the RTSI Switch Shift Register is written to the value of this bit is shifted into the RTSI switch See the Programming the RTSI Switch section later in this chapter for more information National Instruments Corporation 4 59 AT MIO 64F 5 User Manual Register Map and Descriptions Chapter 4 RTSI Switch Strobe Register The RTSI Switch Strobe Register is written to in order to load the contents of the RTSI Switch Shift Register into the RTSI Switch Control Register thereby updating the RTSI switch routing pattern The RTSI Switch Strobe Register is written to after shifting the 56 bit routing pattern into the RTSI Switch Shift Register Address Base address OE hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used AT MIO 64F 5 User Manual 4 60 National Instruments Corporatio
74. output bit 7 The enabled count source is one of F1 F5 TCN 1 SRC1 SRC5 GATE1 GATE 5 as selected in the applicable Counter Mode register The timing diagram assumes the counter counts on rising source edges The timing specifications are the same for falling edge counting B This parameter applies to edge gating CM15 CM13 110 or 111 and gating when both CM7 1 and 15 CM13 000 This parameter represents the minimum GATE pulse width needed to ensure that the pulse initiates counting or counter reloading 9 This parameter applies to both edge and level gating CM15 CM13 001 through 111 and CM7 0 This pa 2 148 AT MIO 64F 5 User Manual 5 Any input transition that occurs after this minimum hold time rameter represents the minimum setup or hold times to ensure that the Gate input is seen at the intended level on the active source edge and the counter may be off by one count 10 This parameter assumes that the GATENA input is unused 16 bit bus mode or is tied high in cases where the GATENA input is used this timing specification must be met by both the GATE and GATENA inputs 11 Signals F1 F5 cannot be directly monitored by the user The phase difference bet these signals will manifest itself by causing counters using two different F signals to count at different times on nominally simultaneous transi tions in the F signals F1 X2 12 This timing specification ass
75. provides comprehensive technical assistance around the world In the U S and Canada applications engineers are available Monday through Friday from 8 00 a m to 6 00 p m central time In other countries contact the nearest branch office You may fax questions to us at any time Corporate Headquarters 512 795 8248 Technical support fax 800 328 2203 512 794 5678 Branch Offices Phone Number Australia 03 879 9422 Austria 0662 435986 Belgium 02 757 00 20 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 00 Germany 089 741 31 30 Italy 02 48301892 Japan 03 3788 1921 Netherlands 03480 33466 Norway 32 848400 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 20 51 51 U K 0635 523545 National Instruments Corporation F 1 Fax Number 03 879 9179 0662 437010 19 02 757 03 11 45 76 71 11 90 502 2930 1 48 14 24 14 089 714 60 35 02 48301915 03 3788 1923 03480 30673 32 848600 91 640 0533 08 730 43 70 056 20 51 55 0635 523154 AT MIO 64F 5 User Manual Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software produc
76. relative accuracy specification indicates the worst deviation from the ideal that the ADC permits A relative accuracy specification of 1 LSB is roughly equivalent to but not the same as a 2 LSB nonlinearity or integral nonlinearity specification because relative accuracy encompasses both nonlinearity and variable quantization uncertainty a quantity often mistakenly assumed to be exactly 2 LSB Although quantization uncertainty is ideally 2 LSB it can be different for each possible digital code and is actually the analog width of each code Thus it is more specific to use relative accuracy as a measure of linearity than it is to use what is normally called nonlinearity because relative accuracy ensures that the sum of quantization uncertainty and A D conversion error does not exceed a given amount Integral nonlinearity INL in an ADC is an often ill defined specification that is supposed to indicate a converter s overall A D transfer linearity The manufacturer of the ADC chip used by National Instruments on the AT MIO 64F 5 specifies its integral nonlinearity by stating that the analog center of any code will not deviate from a straight line by more than 1 LSB This specification is misleading because although the center of a particularly wide code may be found within 1 LSB of the ideal one of its edges may be well beyond 1 5 LSB thus the ADC would have a relative accuracy of that amount National Instruments tests its boards to
77. sample does not occur until after the first falling edge of the Counter 2 output or one scan interval after the trigger Scanning stops at the end of the first scan sequence or at the end of the entire scan list The sequence restarts after a rising edge on Counter 2 is detected The interval scanning mode is useful for applications where a number of channels need to be monitored over a long period of time Interval scanning monitors the N channels every scan interval so the effective channel conversion interval is equal to the interval between scans Data Acquisition Rates The acquisition and channel selection hardware function so that in the channel scanning mode the next channel in the channel configuration register is selected immediately after the conversion process has begun on the previous channel With this method the input multiplexers and the PGIA begin to settle to the new value while the conversion of the last value is still taking place The circuitry on the AT MIO 64F 5 is designed and defined to settle to within 0 5 LSBs or 0 01 of full scale in 5 psec Analog Output and Timing Circuitry The AT MIO 64F 5 has two channels of 12 bit D A output Unipolar or bipolar output and internal or external reference voltage selection are available with each analog output channel through a register in the AT MIO 64F 5 register set Figure 3 9 shows a block diagram of the analog output circuitry AT MIO 64F 5 User Manual 3 12 National I
78. select a specific mode refer to Table 4 3 for available modes and associated bit patterns 4 12 National Instruments Corporation Chapter 4 Register and Descriptions Bit Name Description continued 6 ADCREQ ADC Request Enable This bit controls DMA requesting and interrupt generation from an A D conversion If this bit is set an interrupt or DMA request is generated when an A D conversion is available in the FIFO If this bit is cleared no DMA request or interrupt is generated following an A D conversion To select a specific mode refer to Table 4 3 for available modes and associated bit patterns Table 4 3 DMA and Interrupt Modes Interface Mode Mode Description Channel A to DACO hannel A to DACI hannel to DACO and interleaved hannel A from ADC hannel B to DACO hannel B to DACI hannel B DACO and interleaved hannel B from ADC sf o 11 Channel A and Channel B DACO and double buffered Channel A and Channel B to DACI double buffered 1 Channel A from ADC Channel B to and 1 interleaved pr 11191619111 pep op Ee i o acme continues Lo National Instruments C
79. signal 2 16 5 23 C 3 OUTEN bit 5 30 OVERFLOW bit 4 20 5 5 5 16 overvoltage protection A 4 OVERRUN bit 4 20 5 5 5 16 National Instruments Corporation Index 17 AT MIO 64F 5 User Manual Index P PC I O channel interface circuitry 3 2 to 3 4 PGIA See AT MIO 64F 5 PGIA physical specifications A 7 pin assignments Am9513A System Timing Controller E 6 AT MIO 64F 5 I O connector 2 12 B 1 extended analog input subconnector 2 17 D 1 MIO subconnector 2 13 C 1 polarity analog output polarity selection 2 9 configuring input polarity and range 2 8 posted update mode 3 14 to 3 16 postgain offset error A 2 power connections I O connector 2 30 power requirements A 7 pregain offset error A 2 programmed cycle waveform generation 5 19 to 5 21 programming See also registers Am9513A Counter Timer 5 27 analog input circuitry 5 4 to 5 10 data acquisition functions 5 10 to 5 26 analog output circuitry 5 18 applying a trigger 5 15 to 5 16 clearing analog input circuitry 5 10 cyclic waveform generation 5 18 to 5 19 multiple analog input channel configurations 5 11 programmed cycle waveform generation 5 19 to 5 21 pulsed cyclic waveform generation 5 21 to 5 23 resetting hardware 5 16 to 5 17 sample counter s 5 12 to 5 14 sample interval counter 5 11 to 5 12 scan interval counter 5 14 to 5 15 servicing data acquisition operations 5 16 single analog input channel configurations 5 10 waveform cycle cou
80. single and multiple channel data acquisition sequences Bit descriptions of the two registers making up the Analog Input Register Group are given on the following pages National Instruments Corporation 4 23 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 ADC FIFO Register Reading the ADC FIFO Register returns the oldest ADC conversion value stored in the ADC FIFO Whenever the ADC FIFO is read the value read is removed from the ADC FIFO thereby leaving space for another ADC conversion value to be stored Values are shifted into the ADC FIFO whenever an ADC conversion is complete The ADC FIFO is emptied when all values it contains are read Status Register 1 should be read to determine the FIFO state before the ADC FIFO Register is read If the ADC FIFO contains one or more ADC conversion values the ADCFIFOEF bit is set in Status Register 1 and the ADC FIFO Register can be read to retrieve a value If the ADCFIFOEF bit is cleared the ADC FIFO is empty in which case reading the ADC FIFO Register returns meaningless information If the ADCFIFOHF flag is clear in Status Register 1 the ADC FIFO is at least half full with conversion data and 256 FIFO values can be read without checking the ADCFIFOEF in Status Register 1 The values returned by reading the ADC FIFO Register are available in two different binary formats straight binary which generates only positive numbers or two s complement binary which gen
81. starts in Mode the count process will be retriggered on active going Gate edges including the first Gate edge used to start the counter On each retriggering Gate edge the counter contents will be transferred into the Hold register On the first Source edge after the retriggering Gate edge the Load register contents will be transferred into the counter Counting will resume on the second source edge after a retrigger Am9513A Appendix E National Instruments Corporation Appendix E NANIINININININININININININD 0000005 e XXXIX AMD Am9513A Data Sheet Figure 150 Mode O Waveforms MODE Q Rate Generator with Synchronization Event Counter with Auto Read Reset ons eua oun wna Guts omo cue eur ows ows cue ox DLL Mode Q shown in Figure 15q provides a rate generator with synchronization or an event counter with auto read reset The counter must first be issued an ARM command before counting can occur Once armed the counter will count ali source edges which occur while the Gate is active and disregard those edges which cccur while the Gate is inactive This permits the Gate to turn the count process on and off After the issuance of an ARM command and the application of an active Gate the counter will count to TC repetitively On each TC the counter will reload itself from
82. the source line of Counter 3 while Counter 2 is gated by the signal at its own gate pin Waveform Generation Programming Functions This section provides a detailed explanation of the programming functions necessary to generate synchronously timed analog output waveforms Clearing the Analog Output Circuitry This involves clearing the TMRREQ DACCOMP and DMATCA or DMATCB bits in the Status Register To do this access the TMRREQ Clear DAC Clear and if necessary the DMATCA or DMATCB Clear registers Selecting the Internal Update Counter Select the desired signal at the RTSI switch to be used for updating the DACs OUTI OUT2 OUTS3 available as EXTCONV OUTS are available for updating To route these update signals the A side pin of the RTSI switch must be internally routed to the B side or trigger side Select a trigger line that is not being used The signal must be routed from the selected B side trigger line to the A4 pin on the RTSI switch of this is done in one programming sequence by shifting a 56 bit value to the RTSI switch See the RTSI Bus Trigger Line Programming Considerations section later in this chapter Notice that if OUTS is to be used for updating it does not need to be routed across the RTSI switch In this case only is it sufficient to enable A4DRV to drive pin A4 of RTSI switch with OUTS Programming the Update Interval Counter Select the appropriate counter 1 2 3 or 5 from the Am9513
83. the AT MIO 64F 5 PGIA and signals connected to ACH lt 8 15 gt and ACH lt 40 63 gt are routed to the negative input of the AT MIO 64F 5 PGIA Warning Exceeding the differential and common mode input ranges results in distorted input signals Exceeding the maximum input voltage rating can result in damage to the AT MIO 64F 5 board and to the PC National Instruments is not liable for any damages resulting from such signal connections Connection of analog input signals to the AT MIO 64F 5 depends on the configuration of the AT MIO 64F 5 analog input circuitry and the type of input signal source With the different AT MIO 64F 5 configurations you can use the AT MIO 64F 5 PGIA in different ways Figure 2 6 shows a diagram of the AT MIO 64F 5 PGIA Programmable Gain V Measured Voltage Gain 0 5 1 2 5 10 20 50 100 Figure 2 6 AT MIO 64F 5 PGIA The AT MIO 64F 5 PGIA applies gain and common mode voltage rejection and presents high input impedance to the analog input signals connected to the AT MIO 64F 5 board Signals are routed to the positive and negative inputs of the PGIA through input multiplexers on the AT MIO 64F 5 The converts two input signals to a signal that is the difference between National Instruments Corporation 2 19 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 the two input signals multiplied by the gain setting of the amplifier The amplifier output voltage
84. the corresponding Element and Group fields of the Data Pointer register as shown in Figure 7 The Byte Pointer bit in the Data Pointer register is set Transfers into the Data Pointer only occur for G field values of 001 010 011 100 101 and 111 Values of 000 and 110 for G shouid not be used See the Setting the Data Pointer Register section of this document for additional details Disable Data Pointer Sequencing Coding C7 C6 C5 C4 C2 Ci 1 1 1 0 1 00 0 Description This command sets Master Mode bit 14 without affecting other bits in the Master Mode register MM14 controls the automatic sequencing of the Data Pointer regis ter Disabling the sequencing allows repetitive host processor access to a given internal location without repetitive updating of the Data Pointer MM14 may also be controlled by loading a full word into the Master Mode register Am9513A 2 145 National Instruments Corporation El AT MIO 64F 5 User Manual AMD Am9513A Data Sheet Enabie Data Pointer Sequencing Coding C7 C6 C5 C4 C3 C2 CO 1 1 1 00 Description This command clears Master bit 14 without affecting other bits in the Master Mode register MM14 controls the automatic sequencing of the Data Pointer regis ter Enabling the sequencing allows sequential host processor access to several internal locations without repetitive updating of the Data Pointer MM14 may also be controlled by loading a full word
85. the programmed cycle mode is the pulsed cyclic waveform generation mode in which a programmed number of cycles is generated between a programmed cycle interval The instructions in the blocks of the following flow chart are enumerated in the Waveform Generation Programming Functions section later in this chapter National Instruments Corporation 5 21 AT MIO 64F 5 User Manual Programming Clear the analog output circuitry including the DAC FIFO Internal update Set the A4RCV bit in Clear the A4RCV Command Register 2 bit in Command Register 2 Select the update counter via RTSI programming Program the update interval counter Program the cycle counter Program the cycle interval counter Set the waveform generation mode Enable updating Service update requests Figure 5 9 Pulsed Cyclic Waveform Programming Chapter 5 AT MIO 64F 5 User Manual 5 22 National Instruments Corporation Chapter 5 Programming In this mode Counter 1 counts the programmed number of cycles before terminating the sequence Counter 2 then begins counting the time between cycles the cycle interval then restarts the sequence This sequence of events continues ad infinitum and does not stop until the update signal is removed or the DAC circuitry is cleared This sequence requires that the GATE2SEL signal in addition to the SRC3SEL signal be set in Command Register 4 This allows Counter 1 to count the buffer retransmit signals from
86. to AM9SISA DC OCS 018 JC confirm availability of specific valid combinations to check on released combinations and to obtain additional data This device is also available in Military temperature AMD s standard military grade products range Am9513A 2 117 National Instruments Corporation AT MIO 64F 5 User Manuai AMD Am9513A Data Sheet _ Appendix E AMD products for ORDERING INFORMATION continued Standard Military Drawing SMD DESC Products and Defense applications are available in several packages and operating ranges Standard Military Drawing SMD DESC products are fully compliant with MIL STD 883C requirements The order number Valid Combination for SMD DESC products is formed by a combination of a Military Drawing Part Number b Device Type Case Outline d Lead Finish X 2 118 LEAD FINISH Any Lead Finish Acceptable CASE OUTUNE Q 40 Pin Ceramic DIP 040 X 44 Pin Ceramic LCC CL 044 b MILITARY DEVICE TYPE 01 7 MHz 85134 2 MILITARY DRAWING NO DESCRIPTION 5962 85523 System Timing Controller Valid Combinations Valid Combinations list configurations planned to be Supported volume for this device Consult the AMD sales office to confirm availability of specific valid combinations or to check for newly released valid Group A Tests Group A tests consist of Subgroups 1 2 3 7 8 9 10 11
87. write the software copy to the register Resource Allocation Considerations Counters 1 2 and 5 of the Am9513A Counter Timer are available at the I O connector for general purpose use These counters can only be used so long as this does not conflict with an internal operation in progress on the board that is already using the desired counter Table 5 1 lists the five counters in the Am9513A Counter Timer and enumerates what they are used for in each operation Table 5 1 Am9513A Counter Timer Allocations DAQ Operation Waveform Operation Scan division Updating cycle counting pulsed waveform Scan division Updating cycle counting pulsed waveform Sample interval Updating Sample count N A Sample count gt 65 536 Updating cycle counting Table 5 1 provides a general overview of the AT MIO 64F 5 resources to ensure there are no conflicts when using the counters timers As an example if an interval scanning data acquisition sequence that requires less than 65 537 samples is in operation Counters 2 3 and 4 of the Am9513A are reserved for this purpose This leaves Counters 1 and 5 available for general purpose or waveform generation use National Instruments Corporation 5 1 AT MIO 64F 5 User Manual Programming Chapter 5 Initializing the AT MIO 64F 5 The AT MIO 64F 5 hardware must be initialized for the AT MIO 64F 5 circuitry to operate properly To initialize the AT MIO 64F 5 hardware complete the following steps 1 Wri
88. 1 1 1 0 1 001 lt N amp 101 9 8 N2 1 Description The initial output level for TC Toggle mode is set HIGH for counter N selected by 4 N2 N1 001 Counter 1 thru 101 Counter 5 respectively This command conditions the TC Toggle flip flop see Figure 17 but does not appear at the counter output unless TC Toggle mode 2 CM1 010 is selected Clear TC Toggle Output Coding C7 CS C4 C2 Ci CO 001 lt N lt 101 Description The initial output level for TC Toggle mode is Cleared LOW for counter selected by 4 2 1 001 Counter 1 thru 101 Counter 5 respectively This command conditions the TC Toggle flip flop see Figure 17 but does not appear at the counter output unless TC Toggle mode CM2 CM1 CMO 010 is selected Step Counter Coding C6 C5 C4 C2 C1 CO 001 lt N lt 101 Description Counter N is incremented or decremented by one depending on its operating configuration If the Counter Mode register associated with the selected counter has its CM3 bit Cleared to zero this command will cause the counter to decrement by one if CM3 is set to a logic high this command will increment the counter by one The STEP command will take effect even on a disarmed counter Load Data Pointer Register Coding C7 C6 C5 C4 C2 CO 0 0 E2 G4 G2 GI G4 G2 G1 gt 000 110 Description Bits in the and G fields will be transferred into
89. 13A Command Register to select the Counter 2 Load Register Write 2 to the Am9513A Data Register to store the Counter 2 load value Write FF42 to the Am9513A Command Register to load Counter 2 Write FFF2 to the Am9513A Command Register to step Counter 2 down to 1 ME M Entries stored in the mux channel gain memory should be scanned once during a scan interval The following condition must be satisfied scan interval gt sample interval x where x is the number of entries in the scan sequence Write the desired scan interval to the Am9513A Data Register to store the Counter 2 load value e Ifthe scan interval is between 2 and FFFF 65 535 decimal write the scan interval to the Am9513A Data Register Ifthe scan interval is 10000 65 536 decimal write 0 to the Am9513A Data Register 8 Write FF22 to the Am9513A Command Register to arm Counter 2 After you complete this programming sequence Counter 2 is configured to assign a time interval to scan sequences once the trigger to enable A D conversions is detected Applying a Trigger Once a data acquisition operation has been configured and programmed the acquisition sequence is initiated when a trigger is received A trigger can be initiated through software or hardware To initiate the data acquisition operation through software strobe the Start DAQ Register Make sure EXTTRIG is not pulled low at the I O connector or RTSI switch To initiate the data acquisit
90. 3 shows the timing for the EXTSTROBE signal toy 2500 nsec Figure 2 13 EXTSTROBE Signal Timing AT MIO 64F 5 User Manual 2 30 National Instruments Corporation Chapter 2 Configuration and Installation The pulse width is defined as 500 nsec minimum The EXTSTROBE signal can be used by an external device to latch signals or trigger events The EXTSTROBE signal is an signal EXTCONV Signal A D conversions can be externally triggered with the EXTCONV pin Applying an active low pulse to the EXTCONV signal initiates an A D conversion Figure 2 14 shows the timing requirements for the EXTCONV signal tw 50 nsec minimum ADC switches to hold mode within 100 nsec from this point Figure 2 14 EXTCONV Signal Timing The minimum allowed pulse width is 50 nsec The ADC switches to hold mode within 100 nsec of the high to low edge This hold mode delay time is a function of temperature and does not vary from one conversion to the next There is no maximum pulse width limitation EXTCONV should be high for at least one conversion period before going low The EXTCONV signal is one HCT load and is pulled up to 5 V through a 10 resistor EXTCONV is also driven by the output of Counter 3 of the Am9513A Counter Timer This counter is also referred to as the sample interval counter The output of Counter 3 and the RTSI connection to EXTCONV must be disabled to a high impedance state if A D conversions are to be contr
91. 5 and specific programming requirements for the sample interval and sample counters are given earlier in this chapter For general programming details for Counters 1 2 and 5 and the programmable frequency output refer to Appendix E AMD Am95134A Data Sheet In programming the Master Mode Register keep the following considerations in mind The Am9513A must be used in 16 bit bus mode e scaler control should be set to BCD division for correct operation of the clocks as described in the Initializing the Am9513A section earlier in this chapter RTSI Bus Trigger Line Programming Considerations The RTSI switch connects signals on the AT MIO 64F 5 to the seven RTSI bus trigger lines The RTSI switch has seven pins labeled A lt 6 0 gt connected to AT MIO 64F 5 signals and seven pins labeled B lt 6 0 gt connected to the seven RTSI bus trigger lines Table 5 2 shows the signals connected to each pin National Instruments Corporation 5 27 AT MIO 64F 5 User Manual Programming Table 5 2 RTSI Switch Signal Connections RTSI Switch Pin Signal Name EXTCONV FOUT OUT2 GATEI SOURCES OUTS TMRTRIG OUTI EXTTRIG TRIGGERO 2 TRIGGER4 TRIGGER5 TRIGGER6 Signal Direction Bidirectional Output Output Input Bidirectional Output Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirection
92. 6 CFGMEMEF bit 4 21 CHAN_AIS bit 4 26 CHAN_BIP bit 4 27 CHAN_CAL bit 4 27 CHAN_DSP bit 4 29 CHAN_GHOST bit 4 29 CHAN_LAST bit 4 28 5 11 channel scanning See CONFIGMEM Register data acquisition programming CHAN_SE bit 4 26 CHANSEL S5 0 bit 4 27 to 4 28 CH_GAIN lt 2 0 gt bit 4 28 CLKMODEB lt 1 0 gt bit 4 16 CNT32 16 bit 4 6 5 13 5 14 Command Register 1 4 5 to 4 7 Command Register 2 4 8 to 4 10 5 31 Command Register 3 4 11 to 4 15 Command Register 4 4 16 to 4 18 common mode signal rejection considerations 2 26 to 2 27 CONFIGCLK signal 3 22 CONFIGMEM Register 4 26 to 4 30 5 10 5 11 CONFIGMEMCLR Register 4 29 4 36 5 10 5 11 CONFIGMEMLD Register 4 29 4 37 5 10 5 11 configuration See also installation signal connections analog input configuration 2 6 to 2 8 DIFF input 32 channels 2 6 to 2 7 input mode 2 6 AT MIO 64F 5 User Manual Index 8 National Instruments Corporation Index input polarity and range 2 8 NRSE input 64 channels 2 7 RSE input 64 channels 2 7 analog output configuration 2 9 polarity selection 2 9 reference selection 2 9 base I O address selection 2 3 to 2 5 board configuration 2 1 to 2 5 AT bus interface 2 3 cabling considerations 2 38 default settings for National Instrument products 2 4 digital I O configuration 2 10 DMA channel selection 2 5 field wiring 2 37 to 2 38 interrupt selection 2 5 parts locator diagram 2 2 RTSI bus clock configur
93. 6 5 4 3 2 1 0 EISA_DMA 0 DMACHBB2 DMACHBBI DMACHBBO DMACHAB2 DMACHABI DMACHABO LSB Bit Name Description 15 AARCV RTSI A4 Receive This bit controls the signal source for the TMRTRIG Timer Trigger signal The TMRTRIG signal updates DACs in delayed update mode If A4RCV is set pin A4 of the RTSI switch drives the TMRTRIG signal If A4RCV is cleared the TMRTRIG signal is driven by the EXTTMRTRG signal from the I O connector 14 A4DRV RTSI A4 Drive This bit controls the driver that allows the OUTS signal to drive pin A4 of the RTSI switch If A4DRV is set pin A4 of the RTSI switch is driven by OUTS If 4 is cleared pin A4 is not driven by OUTS and it can be driven by a signal on the RTSI bus 13 A2RCV RTSI A2 Receive This bit controls the driver that allows the GATEI signal to be driven from pin A2 of the RTSI switch If 2 is set pin A2 of the switch drives the GATEI signal In this case may not be driven by a signal at the I O connector 12 A2DRV RTSI A2 Drive This bit controls the driver that allows the OUT2 signal to drive pin A2 of the RTSI switch If A2DRV is set pin A2 of the RTSI switch is driven by OUT2 If A2DRV is cleared pin A2 is not driven by OUT2 and it can be driven by a signal on the RTSI bus AT MIO 64F 5 User Manual 4 6 National Instruments Corporation Chapter 4 Bit 11 10 Name BIPDACI BIPDACO EXTREFDACI EXTREFDACO
94. 9513A 4 bit programmable frequency output channel is located at the I O connector FOUT pin Any of the five internal timebases and any of the counter SOURCE or GATE inputs can be selected as the frequency output source The frequency output channel divides the selected source by its 4 bit programmed value and makes the divided down signal available at the FOUT pin RTSI Bus Interface Circuitry The AT MIO 64F 5 is interfaced to the National Instruments RTSI bus The RTSI bus has seven trigger lines and a system clock line All National Instruments AT Series boards with RTSI bus connectors can be wired together inside the PC and share these signals A block diagram of the RTSI bus interface circuitry is shown in Figure 3 19 MHz BRDCLK RTSICLK EXTCONV FOUT Drivers SOURCES OUTI TMRTRIG OUTS RTSI SEL Internal Data Bus DATA RTSI Switch Trigger 7 RTSI Bus Connector DAC_SDATA DAC_SYNC DAC_CLK ADC_CLK ADC_SYNC ADC_SDATA Figure 3 19 RTSI Bus Interface Circuitry Block Diagram The RTSICLK line can be used to source a 10 MHz signal across the RTSI bus or to receive another clock signal from another AT board connected to the RTSI bus BRDCLK is the system clock used by the AT MIO 64F 5 Bits in a command register in the AT MIO 64F 5 register set control how these clock signals are routed National Instruments Corporation 3 23 AT MIO 64F 5 User Manual Theory of Operation Chapter 3
95. A Counter Timer to be used for updating the DACs Active low pulsing and no gating should be part of the mode programmed To program the update interval counter complete the following programming sequence All writes are 16 bit operations All values given are hexadecimal 1 Write FF00 n to the Am9513A Command Register to select the Counter Mode Register 2 Write the mode value to the Am9513A Data Register to store the Counter n mode value Am9513A counter mode information can be found in Appendix E AMD Am9513A Data Sheet Use one of the following mode values 0225 Selects 5 MHz clock from SOURCE2 pin OB25 Selects 1 MHz clock 0C25 Selects 100 kHz clock 0025 Selects 10 kHz clock National Instruments Corporation 5 23 AT MIO 64F 5 User Manual Programming Chapter 5 OE25 Selects 1 kHz clock OF25 Selects 100 Hz clock 0525 Selects signal at SOURCES input as clock counts the rising edge of the signal 6 MHz maximum 3 Write 08 n to the Am9513A Command Register to select the Counter n Load Register 4 Write the desired update interval to the Am9513A Data Register to store the counter n load value 5 Wirite the following value to the Am9513A Command Register to load counter FF41 Load Counter 1 FF42 Load Counter 2 FF50 Load Counter 5 6 Write n to the Am9513A Command Register to decrement Counter 7 Write the following value to the Am9513A Command Register to arm Counter
96. AT MIO 64F 5 User Manual Configuration and Installation External Reference Signal Optional MIO Subconnector Chapter 2 EXTREF Channel 0 Channel 1 Analog Output Channels AT MIO 64F 5 Board Figure 2 11 Analog Output Connections The external reference signal can be either a DC or an AC signal This reference signal is multiplied by the DAC code to generate the output voltage Digital I O Signal Connections Pins 24 through 32 of the MIO subconnector are digital I O signal pins Pins 25 27 29 and 31 are connected to the digital lines ADIO lt 0 3 gt for digital I O port A Pins 26 28 30 and 32 are connected to the digital lines BDIO lt 0 3 gt for digital I O port B Pin 24 DIG GND is the digital ground pin for both digital I O ports Ports A and B can be programmed individually to be inputs or outputs The following specifications and ratings apply to the digital I O lines Absolute maximum voltage input rating 5 5 V with respect to DIG GND Digital input specifications referenced to DIG GND input logic high voltage input logic low voltage Ij input current load logic high input voltage Ij input current load logic low input voltage AT MIO 64F 5 User Manual 2 V minimum 0 8 V maximum 40 maximum 120 maximum 2 28 National Instruments Corporation Chapter 2 Configuration and Installation Digital output specifications referenced to DIG GND
97. Am9513A AT MIO 64F 5 User Manual 4 National Instruments Corporation Appendix E AMD Am9513A Data Sheet ORDERING INFORMATION continued APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges APL Approved Products List products are fully compliant with MIL STD 883C requirements The order number Valid Combination for APL products is formed by a combination of Device Number b Speed Option applicable c Device Class d Package Lead Finish 48 Hot Solder DIP d PACKAGE TYPE Q 40 Pin Ceramic DIP CD 040 U 44 Ceramic Leadiess Chip Carrier CL 044 c DEVICE CLASS 8 gt Class b SPEED OPTION Not Applicable Valid Combinations ER Valid Combinations list configurations planned to be C Supported in volume for this device Consult the local AMD Valid binations sales office to confirm availability of specific valid AM9513A ______ combinations or to check for newly released valid combinations Group A Tests Group A tests consist of Subgroups 1 2 3 7 8 9 10 11 Am9513A 2 119 National Instruments Corporation E 5 AT MIO 64F 5 User Manual AMD Am9513A Data Sheet Appendix E PIN DESCRIPTION Crystal X1 and X2 are the connections for an external crystal used to determine the frequency of the intemal oscillator The crystal should be a
98. C occurs Terminal Count is defined as that period of time when the counter contents would have been zero if an external value had not been transferred into the counter Thus the terminal count frequency can be the input frequency Am9513A National Instruments Corporation 11 AMD Am9513A Data Sheet divided by the value in the Load register in all operating modes either the Load or Hold register will be transferred into the counter when TC occurs cases where values are being accumulated in the counter the Load register action can become transparent by filling the Load register with all zeros Hold Register The 16 bit read write Hold register is dual purpose It can be used in the same way as the Load register thus offering an aiternate source for module definition for the counter The Hold register may also be used to store accumulated counter values for iater transfer to the host processor This allows the Count to be sampled while the counting process proceeds without interruption Transfer of the counter contents into the Hold register is accomplished by the hardware intertace in Some operating modes or by software commands at any time Counter Mode Register The 16 bit read write Counter Mode register controls the gating counting output and source select functions within each Counter Logic Group The Counter Mode Control Options section of this document describes the detailed control options availab
99. C Source These pins are fused for up to 1 A of 5 V supply Scan Clock This pin pulses once for each A D conversion in the scanning modes The low to high edge indicates when the input signal can be removed from the input or switched to another signal External Strobe Writing to the EXTSTROBE Register results in a minimum 500 nsec low pulse on this pin External Trigger In posttrigger data acquisition sequences a high to low edge on EXTTRIG initiates the sequence In pretrigger applications the first high to low edge of EXTTRIG initiates pretrigger conversions while the second high to low edge initiates the posttrigger sequence External Gate When is low A D conversions are inhibited When EXTGATE is high A D conversions are enabled External Convert A high to low edge on EXTCONV causes an A D conversion to occur Conversions initiated by the EXTCONV signal are inhibited outside of a data acquisition sequence and when gated off SOURCE This pin is from the Am9513A Counter 1 signal GATE This pin is from Am9513A Counter 1 signal OUTPUT This pin is from the Am9513A Counter 1 signal AT MIO 64F 5 User Manual Configuration and Installation Pin 44 45 46 47 48 49 50 Signal Name EXTTMRTRIG GATE2 OUT2 SOURCES GATES OUTS FOUT AT MIO 64F 5 User Manual Reference DIG GND DIG GND DIG GND DIG GND DIG GND
100. Counting will continue with the reload source alternating on each TC until a DISARM command is issued to the counter The third TC reloads the Hold register the fourth TC reloads from the Load register etc A variable duty cycle output can be generated by specifying the TC Toggled output in the Counter Mode register The Load and Hold values then directly control the Output duty cycle with high resolution available when relatively high count values are used 2 134 AT MIO 64F 5 User Manual ALARA RK KKK RR Figure 15i Mode Waveforms MODE K Variable Duty Cycle Rate Generator with Level Gating cis cura cue ue nar owe cus T cus cur Mode K shown in Figure 15k is identical to Mode J except that source edges are only counted when the Gate is active The counter must be armed for counting to occur Once armed the counter will count all source edges which occur while Gate is active and disregard those source edges which occur while the Gate is inactive This permits the Gate to tum the count process on and off As with Mode J the reload Source used will alternate on each TC starting with the Hold register on the first TC after any ARM command When the TC Toggled output is used this mode allows the Ga
101. D 40 through In the differential mode the input is configured for up to 32 channels with ACH lt 16 27 gt and ACH lt 40 51 gt representing differential Channels 16 through 27 and 40 through 51 In the RSE and NRSE modes the input is configured for up to 64 channels with ACH lt 16 27 gt as Channels 16 through 27 and ACH lt 40 51 gt as Channels 40 through 51 25 AI SENSE AI GND Analog Input Sense This pin serves as the reference mode when the board is in NRSE configuration If desired this signal can be programmed to be driven by the board analog input ground 26 AI GND N A Analog Input Ground These pins are the reference point for single ended measurements and the bias current return point for differential measurements 27 50 lt 28 39 gt AI GND Analog Input Channels 28 through 39 and lt 52 63 gt 63 AI GND 52 through In the DIFF mode ACH lt 28 39 gt and ACH lt 52 63 gt represent differential Channels 28 through 39 In the RSE and NRSE modes ACH lt 28 39 gt represent Channels 28 through 39 and ACH lt 52 63 gt represent Channels 52 through 63 The signals on the connector are classified as analog input signals Signal connection guidelines for each of these groups are given in the following section Analog Input Signal Connections Pins 1 through 19 of the MIO subconnector and pins 1 through 50 of the extended analog input subconnector are analog input signal pins Pins 1 and 2 of the MIO su
102. Data Acquisition and Analog Output Timing Connections section in Chapter 2 Configuration and Installation for EXTCONV signal specifications After an A D conversion is initiated the ADC automatically stores the result in the ADC FIFO at the end of its conversion cycle Reading a Single Conversion Result A D conversion results are available when ADCFIFOEF is set in the Status Register and can be obtained by reading the ADC FIFO Register To read the A D conversion result use the following steps Read the Status Register 16 bit read 2 If the OVERRUN or OVERFLOW bits are set an error occurred and data was lost 3 If the ADCFIFOEF bit is set read the ADC FIFO Register to obtain the result Reading the ADC FIFO Register removes the A D conversion result from the ADC FIFO and clears the ADCFIFOEF bit if no more values remain in the FIFO The ADCFIFOEF bit indicates whether one or more A D conversion results are stored in the ADC FIFO If the ADCFIFOEF bit is not set the ADC FIFO is empty and reading the ADC FIFO Register returns meaningless data After an A D conversion is initiated the ADCFIFOEF bit is set approximately 10 usec after initiating the conversion indicating that the data conversion result can be read from the FIFO An ADC FIFO overflow condition occurs if more than 512 conversions are initiated and stored in the ADC FIFO before the ADC FIFO Register is read If this condition occurs the OVERFLOW bit is set in
103. Data Register are as follows e Counter Mode Registers for Counters 1 2 3 4 and 5 e Counter Load Registers for Counters 1 2 3 4 and 5 e Counter Hold Registers for Counters 1 2 3 4 and 5 Master Mode Register The Compare Registers for Counters 1 and 2 these registers are 16 bit registers Bit descriptions for each of these registers are included in Appendix E AMD Am9513A Data Sheet Address Base address 14 hex Type Read and write Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 0 D lt 15 0 gt These 16 bits are loaded into the Am9513A Internal Register currently selected See Appendix E AMD Am9513A Data Sheet for the detailed bit descriptions of the 18 registers accessed through the Am9513A Data Register AT MIO 64F 5 User Manual 4 52 National Instruments Corporation Chapter 4 Register Map and Descriptions Am9513A Command Register The Am9513A Command Register controls the overall operation of the Am9513A Counter Timer and controls selection of the internal registers accessed through the Am9513A Data Register Address Base address 16 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 8 1 These bits must always be set when writing to Am9513A Command Register 7 0 C lt 7 0 gt These eight bits are loaded into the Am9513A Command Register See Appendix
104. E AMD Am9513A Data Sheet for the detailed bit description of the Am9513A Command Register National Instruments Corporation 4 53 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 Am9513A Status Register The Am9513A Status Register contains information about the output pin status of each counter in the Am95134A Address Base address 16 hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 MSB 7 6 5 4 3 2 1 0 LSB Bit Name Description 15 6 X Don t care bits 5 1 lt 5 1 gt Each of these five bits returns the logic state of the associated counter output pin For example if OUTA is set then the output pin of Counter 4 is at a logic high state 0 BYTEPTR This bit represents the state of the Am9513A Byte Pointer Flip Flop This bit has no significance for AT MIO 64F 5 operation because the Am9513A should always be used in 16 bit mode on the AT MIO 64F 5 AT MIO 64F 5 User Manual 4 54 National Instruments Corporation Chapter 4 Register and Descriptions Digital I O Register Group The two registers making up the Digital I O Register Group monitor and control the AT MIO 64F 5 digital I O lines The Digital Input Register returns the digital state of the eight digital I O lines A pattern written to the Digital Output Register is driven onto the digital I O lines when the digital output drivers are enabled see the description for Command Register 2 Bit descri
105. Gate Valid to Count Source High Special Gate Notes 10 13 T o ms TEHGV2 Count Source High to Gate Valid Special Gate Notes 10 13 18 80 Notes E Enabled counter source input SRC1 5805 GATE1 GATES F1 F5 TCN 1 F FOUT G Counter gate input GATES TCN 1 Q Data Out D80 0815 1 Abbreviations used for the switching parameter symbols are given as the letter T followed by four or five characters The first and third characters represent the signal names on which the measurements start and end Signal abbrevia Read A Address C D W Write WR C Clock X2 Y Output OUT1 OUTS D Data In 080 0815 2 150 Am9513A AT MIO 64F 5 User Manual E 36 National Instruments Corporation Appendix E The second and fourth letters designate the reference states of the signals named in the first and third letters respectively using the following abbreviations H HIGH L LOW V VALID X Unknown or Don t care Z High Impedance 2 Any input transition that occurs before this minimum setup requirement will be reflected in the contents read from the status register 3 Any input transition that occurs before this minimum setup requirement will act on the counter before the execution of the operation initiated by the write and the counter may be off by one count 4 Any input transition that occurs after this minimum hold time is gua
106. I O Address Switch Settings National Instruments Corporation 2 3 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 The base address DIP switch is arranged so that a logical 1 or true state for the associated address selection bit is selected by pushing the toggle switch up or toward the top of the board Alternately a logical or false state is selected by pushing the toggle switch down or toward the bottom of the board In Figure 2 2B A9 is up true A8 through A6 are down false and A5 is up true This represents a binary value of 10001 XXXXX or hex 220 The Xs indicate don t care bits and are the five least significant bits LSBs of the address A4 through AO used by the AT MIO 64F 5 circuitry to decode the individual register selections The don t care bits indicate the size of the register space In this case the AT MIO 64F 5 uses I O address hex 220 through hex 23F in the factory default setting Note If you change the AT MIO 64F 5 base I O address you must make a corresponding change to any software packages you use with the AT MIO 64F 5 Table 2 1 lists the default settings of other National Instruments products for the PC Table 2 2 lists the possible switch settings the corresponding base I O address and the base I O address space used for that setting For more information about the I O address of your PC refer to the technical reference manual for your computer Table 2 1 Default Settings of Natio
107. II g uogos SIV NVHO dS NVHO xOPLLLXH Block Diagram 3 Analog Input and Data Acquisition Circuitry Figure 3 3 5 AT MIO 64F 5 User Manual National Instruments Corporation Theory of Operation Chapter 3 Analog Input Circuitry The analog input circuitry consists of input multiplexers multiplexer mode selection circuitry a PGIA calibration circuitry a 12 bit sampling ADC and a 16 bit 512 word deep FIFO A D Converter The ADC is a 12 bit sampling subranging ADC With 12 bit resolution the converter can resolve its input range into 4 096 different steps This resolution generates a 12 bit digital word that represents the value of the input voltage level with respect to the converter input range The ADC has two input modes that are software selectable on the AT MIO 64F 5 board on a per channel basis 5 to 5 V or 0 to 10 V The ADC on the AT MIO 64F 5 is guaranteed to convert at a rate of at least 200 ksamples sec The data format circuitry is software programmable to generate either straight binary numbers or two s complement numbers In unipolar mode values returned from the ADC are straight binary and result in a range of 0 to 4 095 In bipolar mode the ADC returns two s complement values resulting in a range of 2 048 to 42 047 Analog Input Multiplexers The input multiplexer consists of four dual eight to one CMOS analog input multiplexers preced
108. IO 64F 5 User Manual Am9513A E 16 Appendix E MODE D Rate Generator with No Hardware Gating AMD Am9513A Data Sheet MODE E Rate Generator with Level Gating Fas ema cuna omo owe owns cua curs cus cue Lowe owe ous ows ws Mode D shown in Figure 15d is typically used in frequency generation applications In this mode the Gate input does not affect counter operation Once armed the counter wiil count to TC repetitively On each TC the counter will reload itself Cer ewe cus cus cus cus om 3 Lx x Dx Xx Mode E shown in Figure 15e is identical to Mode D except the counter will only count those source edges which occur while the Gate input is active This feature allows the counting process to be enabled and disabled under hardware control A Square wave rate generator may be obtained by specifying the TC Toggled output mode Cow VALUE TC OUTPUT TC TOGGLED OUTPUT Figure 15e Mode E Waveforms Am9513A 2 131 National Instruments Corporation E 17 AT MIO 64F 5 User Manual AMD Am9513A Data Sheet MODE F Non Retriggerable One Shot 7 Mode F shown in Figure 151 provides non retriggerable one shot timing function The
109. IO 64F 5 is set up 1 Set the appropriate mode bits in Command Register 3 to enable DMA request generation 2 Access the DMATCA and DMATCB Clear Registers the TMRREQ Clear Register the DAC Clear Register and the DAQ Clear Register 3 Program the DMA controller to service DMA requests from the AT MIO 64F 5 board Refer to the BM Personal Computer AT Technical Reference manual for more information on DMA controller programming 4 Ifa DMA terminal count is received after the DMA service write O to either the appropriate DMATC Clear Register to clear the DMATCA or DMATCB bits in Status Register 1 AT MIO 64F 5 User Manual 5 30 National Instruments Corporation Chapter 5 Programming Once steps 1 through 3 are completed the DMA controller is programmed to acknowledge requests If analog input DMA is programmed the DMA controller automatically reads the ADC FIFO Register whenever an A D conversion result is available and then stores the result in a buffer in memory If the DMA controller has been programmed for analog output updating values from the buffer in memory are automatically written to the DAC upon receipt of a DMA request If both analog input and output DMA is selected then the DMA controller reads the FIFO or writes to the DACs depending on which channel requested a DMA transfer If single channel interleaved DMA is selected for writing data to the DACS then one buffer services both DAC 0 and DAC 1 This is accomplished
110. LSB Bit Name Description 15 CHAN SE Channel Single Ended This bit configures the analog input section for single ended or differential mode See Table 4 9 14 CHAN AIS Channel Analog Input Sense This bit sets the analog input section for RSE or NRSE mode See Table 4 9 Table 4 9 Input Configuration Bit Map Effect Input Mode PGIA PGIA DIFF Channels 0 to 7 Channels 8 to 15 Channels 16 to 39 Channels 40 to 63 NRSE Channels 0 to 63 AI SENSE Internal Calibration Internal Calibration Note X indicates a don t care bit lt e 2 z 2 lt 5 AT MIO 64F 5 User Manual 4 26 National Instruments Corporation Chapter 4 Register and Descriptions Bit Name Description continued 13 CHAN CAL Channel Calibration Enable This bit controls the analog input configuration switches CHAN CAL is used to disconnect the input multiplexers from the PGIA during a calibration procedure so that known internal reference signals can be routed to the amplifier See Table 4 10 Table 4 10 Calibration Channels Calibration Channels CHANSEL Effect lt 5 0 gt PGIA PGIA XXX000 AI GND XXX001 AO GND XXX010 DAC 0 OUT XXXO011 DAC 1 OUT XXX100 AI GND XXX101 5 110 DACOOUT XXXI111 DAC 1 OUT 12 CHAN_BIP Channel Bipolar This bit configures the ADC for unipolar or bipolar mode When CHAN_BIP is clear the ADC is configured for uni
111. Low Pulse Width Note 13 a 7o _ OE E EE e i E ET Re ______ meweamewen _____ Len puse p ENTRE ECL Count Source High to Gate Valid Level Gating Hold Time Notes 7 9 10 ______ 22 ms Count Source High to Read Low Set up Time Notes 2 386 ms n Count Source High to Write High Set up Time Notes 3 7 TC Output TEHYV Count Source High to Out Valid Note 7 immediate or Delayed Toggie Output Comparator Output TN FN High Noe 1 ________________ 175 j Gate Valid to Count Source High Level Gating Setup Time Notes 7 9 10 ______ 22 i00 ns TGVGV Gate Valid to Gate Valid Gate Pulse Duration Notes 8 10 2 145 ms TGVWH Gate Valid to Write High Notes 310 ___ __ _______ gt 99 j m LT Raa e Ga TRHEH Reed High to Count Source High Notes 4 7 ______ 9 _ _ Road High to Data Out Invalid ael gt L InMQZ Read High to Data Out at High Impedance Data Bus Release Timo 7 21 85 ms _ ___ Read High to Read Low Read Recovery Time ___ _________ gt 390 _ ns TRHSH __ Read High to CS High Note 12 o1 LLLTRHwL Read High to Write Low Read Recovery Time _________ gt __ __ Read tow to Data Out Vaid O
112. M command is executed during the cycle preceding TC the counter will go immediately to TC This occurs because the LOAD operation is performed by generating a pseudo count pulse internal to the Am9513A and the Am9513A is expecting to go into TC on the next count pulse The reload source used to reload the counter will be the same as that which would have been used if the TC were generated by a source edge rather than by the LOAD operation Execution of a LOAD or LOAD AND ARM command while the counter is in TC will cause the TC to end For Armed counters in all modes except S or V the LOAD source used will be that to be used for the upcoming TC The LOADing operation will not alter the selection of reload source for the upcoming TC For Disarmed counters in modes except S or V the reload sources used will be the LOAD register For modes S or V the reioad source will be selected by the GATE input regardless of whether the counter is Armed or Disarmed 9513 30 Appendix National Instruments Corporation Appendix E Special considerations apply when modes with alternating reload sources are used Modes a LOAD command drives the counter to TC in these modes the reload source for the next TC will be from the opposite reload location In other words the LOAD generated TC will cause the reload sources to alternate just as a TC generated by a source edge would Note that if second LOAD comma
113. Mode G is shown in Fig ure 15g DDI XOX Figure 154 Mode F Waveforms 2 132 AT MIO 64F 5 User Manual Am9513A 18 Appendix E National Instruments Corporation Appendix E AMD Am9513A Data Sheet ome LN iD NE 004650 Figure 15g Mode Waveforms MODE H Software Triggered Delayed Puise One Shot with Hardware Gating cus Mode shown in Figure 15h is identical to Mode G except that the Gate input is used to qualify which source edges are to be counted The counter must be armed for counting to occur Once armed the counter will count ail source edges that occur while the Gate is active This permits the Gate to tum the count process on and off As with Mode G the counter will be reloaded from the Hold register on the first TC and reloaded from the Load register and disarmed on the second TC This mode allows the Gate to contro the extension of both the initial output delay time and the pulse width MODE Hardware Triggered Delayed Pulse Strobe cis cura cm2 cunt omo xT x cvs cma om2 xix xix Mode 1 shown in Figure 15i is identical to Mode G except that counting will not begin until a Gate edge is ap
114. Programming the Sample Counter s Counters 4 and 5 of the Am9513A Counter Timer are used as the sample counter The sample counter tallies the number of A D conversions initiated by Counter 3 or EXTCONV and inhibits conversions when the desired sample count is reached If the desired sample count is 65 536 or less only Counter 4 needs to be used making Counter 5 available for general purpose timing applications If the desired sample count is greater than 65 536 both Counters 4 and 5 must be used AT MIO 64F 5 User Manual 5 12 National Instruments Corporation Chapter 5 Programming Sample Counts 2 through 65 536 Use the following programming sequence to program the sample counter for sample counts up to 65 536 The minimum permitted sample count is 2 writes are 16 bit operations values given are hexadecimal 1 Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register 2 Write 1025 to the Am9513A Data Register to store the Counter 4 mode value for posttrigger acquisition modes Write 9025 to the Am9513A Data Register to store the Counter 4 mode value for pretrigger acquisition modes 3 Write FFOC to the Am9513A Command Register to select the Counter 4 Load Register 4 Write the sample count value to the Am9513A Data Register to store the Counter 4 load value Ifthe sample count is between 2 and FFFF 65 535 decimal write the sample count to the Am9513A Data Register Ifthe sample
115. RTRIG National Instruments Corporation Reference DIG GND DIG GND DIG GND DIG GND DIG GND DIG GND DIG GND DIG GND DIG GND C 3 MIO Subconnector Description continued Scan Clock This pin pulses once for each A D conversion in the scanning modes The low to high edge indicates when the input signal can be removed from the input or switched to another signal External Strobe Writing to the EXTSTROBE Register results in a minimum 500 nsec low pulse on this pin External Trigger In posttrigger data acquisition sequences a high to low edge on EXTTRIG initiates the sequence In pretrigger applications the first high to low edge of EXTTRIG initiates pretrigger conversions while the second high to low edge initiates the posttrigger sequence External Gate When EXTGATE is low A D conversions are inhibited When EXTGATE is high A D conversions are enabled External Convert A high to low edge on EXTCONV causes an A D conversion to occur Conversions initiated by the EXTCONV signal are inhibited outside of a data acquisition sequence and when gated off SOURCE This pin is from the Am9513A Counter 1 signal GATE This is from the Am9513A Counter 1 signal OUTPUT This pin is from the Am9513A Counter 1 signal External Timer Trigger If selected a high to low edge on EXTTMRTRIG results in the output DACS being updated with the value written to the
116. Register 4 44 General Event Strobe Register 4 45 DMA Channel Clear RES ister o deste eite 4 46 DMATCA Clear Petre ence nasa aen ie e 4 47 DNIXTCBCISar e 4 48 External Strobe Register 4 49 Calibration DAC 0 Load 4 50 Am9513A Counter Timer Register Group seeeeeeeeeenene 4 51 Amo9513A Data 4 52 Am9513A Command 1 4 53 Am9515A Status Reglsteta ue ee et taies 4 54 Digital Regi ster in 4 55 Digital Input Register iier ite rite te tote ect 4 56 Digital Output Res ister tgp 4 57 RTSI Switch Register Group iere eee ort ee eet Dose 4 58 RTSI Switch edit anata eats 4 59 RTSI Switch Strobe 1 cele elec 4 60 Chapter 5 PrLOSPADIBIBE 5 1 Register Programming Considerations 1 00 5 1 Resource Allocation 1 5 1 Initializin
117. TRIG Stenal ie Alene eal eds 2 32 Signal sone of dona M Dus EMT ease 2 33 Event Counting Application with External Switch Gating 2 34 Frequency Measurement Application eese 2 35 General Purpose Timing 10 5 2 36 AT MIO 64F 5 Block enne enne enne nnns 3 1 PC I O Channel Interface Circuitry Block 3 3 Analog Input and Data Acquisition Circuitry Block Diagram 3 5 ADC Conversion TIMME zio ettari E de eeu 3 8 Single Channel Posttrigger Data Acquisition Timing eee 3 9 Single Channel Pretrigger Data Acquisition Timing eee 3 10 Scanning Posttrigger Data Acquisition 3 11 Interval Scanning Posttrigger Data Acquisition Timing ees 3 12 Analog Output Circuitry Block 3 13 Analog Output Waveform Circuitry 3 15 Posted DAC Update Se 3 16 Analog Output Waveform Circuitry eese nennen 3 17 FIFO Cyclic Waveform Generation with Disable ess 3 17 FIFO Programmed Cyclic Waveform 3 18 FIFO Pulsed W
118. Type Write only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Initiates a single ADC conversion Note A D conversions can be initiated in one of two ways by accessing the Single Conversion Register or by applying an active low signal on the EXTCONV signal The EXTCONV signal is connected to pin 40 on the MIO subconnector to OUT3 of the Am9513A and to the AO pin of the RTSI bus switch If the Single Conversion Register is to initiate A D conversions all other sources of conversion should be inhibited to avoid an OVERRUN condition AT MIO 64F 5 User Manual 4 40 National Instruments Corporation Chapter 4 Register and Descriptions DAC Event Strobe Register Group The DAC Event Strobe Register Group consists of three registers that when written to cause the occurrence of certain events on the AT MIO 64F 5 board such as clearing flags and updating the analog output DACs Bit descriptions of the three registers making up the DAC Event Strobe Register Group are given on the following pages National Instruments Corporation 4 41 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 TMRREQ Clear Register Accessing the TMRREQ Clear Register clears the TMRREQ and DACCOMP bits after a TMRTRIG pulse is detected Clearing TMRREQ when interrupt or DMA mode is enabled clears the respective interrupt or DMA request Address Base address 1F hex Type Read only Word Size 8 bi
119. UMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks LabVIEW NI DAQ and RTSI are trademarks of National Instruments Corporation Product and company names listed are trademarks or trade names of their respective companies Warning Re
120. _ _ M LI Lej __TRLOX Read Low to Data Bus Drven Data Bus Orive Time ___ 7 1 20 20 ns Read Low to Read High Read Pulse Duration Note 322 ie _ ns CS tow to Read Low Noto 12 es TStwH __ CS Low to Write High Note 13 o o rt 9 Write High to 020020002120 ml enl we Heg Ner a Write High to Count Source High Notes 5 7 1510 ee RN RC RR E LL b Write High to write Low Write Recovery Time Note 16 1 i900 _ TWHYV Write High to Out Valid Notes 6 14 oaa 0s _TWLWH Write Low to Write High Write Pulse Duration Note 12 _ gt T wo T _ m TGVEH2 Gate Vaid to Count Source High Special Gate Notes 10 13 i 22 200 s L TEHMGV2 Count Source High to Gate Valid Special Gate Notes 10 1 3 12 so ns Notes E Enabled counter source input SRC1 SRC5 1 Abbreviations used for the switching parameter symbols are SAT GATES F1 5 1 given as the letter T followed by four or five characters The _ first and third characters represent the signal names on 8 De Ou Dee Dae GATES which the measurements start and end Signal abbrevia Read RD tions used are S Chip Select CE A Address C D W Write WR C Clock X2 Y O
121. able the automatic sequencing functions When 14 1 the contents of the Data Pointer can be changed only directly by entering command When 14 0 several types of automatic sequencing of the Data Pointer are available These are described in the Data Pointer register section of this document AMD Am9513A Data Sheet Figure 12 Gating Control Thus the host processor by controlling MM14 may repetitive ly read write a single internal location may sequentially read write groups of locations Bit MM14 can be loaded by writing to the Master Mode register or can be set or cleared by Software command Scaler Ratios Master Mode bit MM15 controls the counting configuration of the Frequency Scaler counter When 15 0 the Scaler divides the oscillator frequency in binary steps so that each Subirequency is 1 16 of the preceding frequency When 15 1 the Sealer divides in BCD steps so that adjacent frequencies are related by ratios of 10 instead of 16 see Figure 13 Binary Scaling Scaling MM15 1 MM15 0 osc osc F1 10 F1 16 F1 100 F1 256 F1 1 000 F1 4096 F1 10 000 F1 65 536 Figure 13 Frequency Scaler Ratios Am9513A 2 127 National Instruments Corporation E 13 AT MIO 64F 5 User Manual AMD Am9513A Data Sheet Appendix E Counter Mode A ao ean 1 9 9 9 9 9 9 9 9 9 9
122. ace timing signals interrupt circuitry and DMA arbitration circuitry The PC I O channel interface circuitry generates the signals necessary to control and monitor the operation of the AT MIO 64F 5 multiple function circuitry The PC I O channel has 24 address lines the AT MIO 64F 5 uses 10 of these lines to decode the board address Therefore the board address range is 000 to hex SA5 through SA9 are used to generate the board enable signal SAO through SA4 are used to select individual onboard registers The address decoding circuitry generates the register select signals that identify which AT MIO 64F 5 register is being accessed The AT MIO 64F 5 is factory configured for a base address of 220 hex With this base address all of the registers on the board will fall into the address range of 220 hex to 23F hex If this address range conflicts with any other equipment in your PC you must change the base address of the AT MIO 64F 5 or of the other device See Chapter 2 Configuration and Installation for more information The PC I O channel interface timing signals are used to generate read and write signals and to define the transfer cycle size A transfer cycle can be either an 8 bit or a 16 bit data I O operation The AT MIO 64F 5 returns signals to the PC I O channel to indicate when the board has been accessed when the board is ready for another transfer and the data bit size of the current I O transfer You must pay particular attenti
123. adecimal 1 Write FF03 to the Am9513A Command Register to select the Counter 3 Mode Register 2 Write the mode value to the Am9513A Data Register to store the Counter 3 mode value Am9513A counter mode information can be found in Appendix E AMD Am9513A Data Sheet Use one of the following mode values 8225 Selects 5 MHz clock from SOURCE2 pin 8B25 Selects 1 MHz clock 8C25 Selects 100 kHz clock 8D25 Selects 10 kHz clock 8 25 Selects 1 KHz clock 8F25 Selects 100 Hz clock 8525 Selects signal at SOURCES input as clock counts the rising edge of the signal 6 MHz maximum 3 Write FFOB to the Am9513A Command Register to select the Counter 3 Load Register Write 2 to the Am9513A Data Register to store the Counter 3 load value Write FF44 to the Am9513A Command Register to load Counter 3 Write FFF3 to the Am9513A Command Register to step Counter 3 down to 1 Write the desired sample interval to the Am9513A Data Register to store the Counter 3 load value Ifthe sample interval is between 2 and FFFF 65 535 decimal write the sample interval to the Am9513A Data Register Ifthe sample interval is 10000 65 536 decimal write 0 to the Am9513A Data Register 8 Write FF24 to the Am9513A Command Register to arm Counter 3 After you complete this programming sequence Counter 3 is configured to generate A D conversion pulses as soon as application of a trigger causes it to be enabled
124. aded from the Hold register On the second TC the counter will be reloaded from the Load register and counting will stop until a new gate edge is issued to the counter Note that unlike Mode K new Gate edges are required after every second TC to continue Am9513A O National Instruments Corporation E 21 MODE N Sottware Triggered Strobe with Level Gating and Hardware Retriggering cunts ours curis oma cus curo cue cus uvm x x x 7 CMS CM3 cm2 xt xt x Mode shown in Figure 15n provides a software triggered Strobe with level gating that is also hardware retriggerable The counter must be issued an ARM command before counting can occur Once armed the counter will count ail Source edges which occur while the gate is active and disregard those source edges which occur while the Gate is inactive This permits the Gate to tum the count process on and off After the issuance of the ARM command and the application of an active Gate the counter will count to TC Upon reaching TC the counter will reload from the Load register and automatically disarm itself inhibiting further count ing Counting will resume upon the issuance of a new ARM command All active going Gate edges issued to an armed Counter will cause a retrigger operation Upon application of the Gate edge the counter contents will be saved in the Hold register On the first qualifie
125. al Chapter 5 Figure 3 19 in Chapter 3 Theory of Operation diagrams the AT MIO 64F 5 RTSI switch connections RTSI Switch Signal Connection Considerations The AT MIO 64F 5 board has a total of nine signals connected to the seven A side pins of the RTSI crossbar switch These same signals also appear at the AT MIO 64F 5 I O connector As shown in Table 5 2 two AT MIO 64F 5 signals are connected to pin A2 and two signals are connected to pin A4 The routing of these signals is further controlled by the bits A4DRV A4RCV A2DRV and A2RCV in Command Register 2 e To drive the RTSI switch A2 with the signal OUT2 set the AZDRV bit in Command Register 2 Otherwise clear the A2DRV bit e To drive the signal from pin A2 of the RTSI switch set the A2RCV bit in Command Register 2 Otherwise clear the 2 bit Note If both the A2DRV and A2RCV bits are set the signal is driven by the signal OUT2 This arrangement is probably not desirable e To drive the RTSI switch pin A4 with the signal OUTS set the A4DRV bit in Command Register 2 Otherwise clear the A4DRV bit To drive the signal TMRTRIG from pin A4 of the RTSI switch set the A4RCV bit in Command Register 2 Otherwise clear the A4RCV bit Note If both the A4DRV and A4RCV bits are set the TMRTRIG signal is driven by the signal OUTS AT MIO 64F 5 User Manual 5 26 National Instruments Corporation Chapter 5 Programming Programmin
126. al Connections section later in this chapter Figure 2 10 shows a schematic diagram of this configuration Input Polarity and Input Range The AT MIO 64F 5 has two polarities unipolar input and bipolar input Unipolar input means that the input voltage range is between 0 and Vref where Vref is a positive reference voltage Bipolar input means that the input voltage range is between 2 and Vref 2 The AT MIO 64F 5 has a unipolar input range of 10 V and a bipolar input range of 10 V 5 V Polarity and range settings are programmed on a per channel basis through the configuration memory register Considerations for Selecting Input Ranges Input polarity and range selection depend on the expected input range of the incoming signal A large input range can accommodate a large signal variation but worsens the voltage resolution Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range For best results the input range should be matched as closely as possible to the expected range of the input signal For example if the input signal is certain not to be negative below 0 V a unipolar input is best However if the signal is negative inaccurate readings will occur if unipolar input polarity is used The software programmable gain on the AT MIO 64F 5 increases its overall flexibility by matching the input signal ranges to those that the AT MIO 64F 5 ADC can accommodate The AT MIO
127. al sources Pins B6 through BO select any of the pins A6 through 0 as signal sources For example the pattern 011 for S2 through SO in the control field selects the signal connected to pin B3 as the signal source for pin The bit labeled OUTEN is the output enable bit for that pin If the OUTEN bit is set the pin is driven by the selected source signal the pin acts as an output pin If the OUTEN bit is cleared the pin is not driven regardless of the source signal selected instead the pin can be used as an input pin If the preceding control field contains the pattern 0111 the signal connected to pin B3 Trigger Line 3 appears at pin AO On the AT MIO 64F 5 board this arrangement allows the EXTCONV signal to be driven by Trigger Line 3 Conversely if the B4 control field contains National Instruments Corporation 5 29 AT MIO 64F 5 User Manual Programming Chapter 5 the pattern 1011 the signal connected to pin A5 appears at pin B4 This arrangement allows Trigger Line 4 to be driven by the AT MIO 64F 5 OUTI signal In this way boards connected via the RTSI bus can send signals to each other over the RTSI bus trigger lines To program the RTSI switch complete these steps 1 Calculate the 56 bit pattern based on the desired signal routing a Clear the OUTEN bit for all input pins and for all unused pins b Select the signal source pin for all output pins by setting bits S2 through SO to the source pin number
128. all be changed by writing directly to the Master Mode register After power on reset or a Master Reset command the Master Mode register is cleared to an all zero condition This resuits in the following configuration Time of Day disabled Both Comparators disabled FOUT Source is frequency F1 FOUT Divider set for divide by 16 FOUT gated on Data 8 bits wide Data Pointer Sequencing enabled Frequency Scaler divides in binary 2 125 AT MIO 64F 5 User Manual AMD 9513 Data Sheet FOUT Divider 0000 Divide by 16 0001 by 1 0010 by 2 0011 by 3 0100 Divide by 4 0101 Divide by 5 0110 Divide by 6 0111 Oivide by 7 1000 Divide by 1001 Divide by 9 1010 Divide by 10 1011 Divide by 11 1100 Divide by 12 1101 Divide by 13 1110 Divide by 14 1111 Divide by 15 FOUT Source 0000 0001 SRC 1 0010 SRC 2 0011 SRC3 0100 4 0101 SRC 5 0110 1 0111 2 1000 3 1001 4 1010 5 1011 F1 1100 F2 1101 F3 1110 Fa 1171 25 L FOUT Gate 0 FOUT On 1 FOUT ON Low Z to GNO Bus Width 0 8 Bit Bus 1 16 8 Bus Data Pointer Control 0 Enable increment 1 Disable increment Senter Control Binary Oivision 1 BCD Division Compere 2 Enebie 0 Oisabled 1 Enabled Compare 1 Enable 0 Disabled 1 Enabled Mode 00 TOO Disabied 01
129. ally by using the EXTTMRTRIG signal from the I O connector This signal updates the DACs when A4RCV is disabled and the appropriate DAC waveform mode is programmed through one of the registers in the AT MIO 64F 5 register set The analog output DACS are updated by the high to low edge of the applied pulse Figure 2 16 shows the timing requirements for the EXTTMRTRIG signal AT MIO 64F 5 User Manual 2 32 National Instruments Corporation Chapter 2 Configuration and Installation ty 50 nsec minimum DACs update 100 nsec from this point Figure 2 16 EXTTMRTRIG Signal Timing The minimum pulse width allowed is 50 nsec The DACs are updated within 100 nsec of the high to low edge There is no maximum pulse width limitation EXTTMRTRIG should be high for at least 50 nsec before going low The EXTTMRTRIG signal is one load and is pulled up to 5 V through a 10 kQ resistor General Purpose Timing Signal Connections The general purpose timing signals include the GATE and OUT signals for the Am9513A Counters 1 2 and 5 SOURCE signals for Counters 1 and 5 and FOUT signal generated by the Am9513A Counters 1 2 and 5 of the Am9513A Counter Timer can be used for general purpose applications such as pulse and square wave generation event counting pulse width time lapse and frequency measurements For these applications SOURCE and GATE signals can be directly applied to the counters from the I O connector The counters ar
130. an internal counter pulse from Counters 1 2 3 or 5 of the Am9513A Counter Timer it can be supplied from the EXTTMRTRIG signal at the I O connector or it can be obtained by accessing a register in the AT MIO 64F 5 register set In the posted update mode requests for writes to the DAC are generated from the TMRREQ signal and can be acknowledged in one of three ways either polled I O through monitoring the TMRREQ signal in Status Register 1 interrupts or DMA All three response mechanisms will have a delay associated with them in how fast they can respond to the requesting signal DMA will have the fastest response followed by polled I O and finally interrupts The advantage of using interrupts is that the CPU is not solely dedicated to monitoring Status Register 1 and can simultaneously perform other tasks If writes generated from these requests updated the DAC immediately there could be significant jitter in the resulting output waveform so values are written to a buffer where they are updated later with a precisely timed update signal Figure 3 11 depicts the timing for the posted DAC update mode Update Trigger LI LJ L TMRREQ l l l DAC Write LX 0 0 0 Figure 3 11 Posted DAC Update Timing In Figure 3 11 the update trigger signal serves to update the previously written value to the DAC In the posted update mode the DAC FIFO is used to buffer the data Requests are generated either whe
131. and in the non A Am9513 device Master Reset Coding iQ C6 C5 C4 Ci CO 1 1 71 1 1 1 14 Description The Master Reset command duplicates the action of the power on reset circuitry disarms all counters enters 0000 in the Master Mode Load and Hold registers and enters 9800 hex the Counter Mode registers Following either a power up or software reset the LOAD command should be applied to all the counters to clear any that may be a TC state The Data Pointer register should also be set to a legal value since reset does not initialize it A complete reset operation follows 1 Using the procedure given in the Command Initiation section of this document enter the FF hex command to perform a software reset 2 Using the Command Initiation procedure enter the LOAD command for ail counters opcode SF hex 3 Using the procedure given in the Setting the Data Pointer Register section of this document set the Data Pointer to a valid code The legal Data Pointer Codes are given in Figure 8 The Master Mode Counter Mode Load and Hold registers can now be initialized to the desired values Am9513A E 32 National Instruments Corporation Appendix E AMD Am9513A Data Sheet ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Commercial C Devices Storage Temperature 765 C to 150 Temperature
132. ange A unipolar output has an output voltage range of 0 to Vref 1 LSB V and accepts straight binary input values A bipolar output has an output voltage range of Vref to Vref 1 LSB V and accepts two s complement input values One LSB is the voltage increment corresponding to an LSB change in the digital code word For unipolar output 1 LSB V ref 4 096 For bipolar output 1 LSB Viep 2 048 The voltage reference source for each DAC is selectable through one of the AT MIO 64F 5 registers and can be supplied either externally at the EXTREF input or internally The external reference can be either a DC or an AC signal If an AC reference is applied the analog output channel acts as a signal attenuator and the AC signal appears at the output multiplied by the digital code divided by 4 096 for unipolar output or 2 048 for bipolar output The internal reference is a5 V reference multiplied by 2 Using the internal reference supplies an output voltage range of 0 to 9 9976 V in steps of 2 44 mV for unipolar output and an output voltage range of 10 to 9 9951 V in steps of 4 88 mV for bipolar output Gain calibration for the DACs is intended only for the internal reference it will only add a variable offset to the external reference Offset calibration can be applied to both references Analog Output Calibration Output voltage accuracy is assured through the use of the onboard calibration circuitry of the AT MIO 64F 5 This circuitry uses a
133. arallel Gate On FOUT Coding C C6 C5 1 1 C2 Co 0 0 1 0 Description This command clears Master Mode bit 12 without affecting other bits in the Master Mode register MM12 controls the output status of the FOUT signal When MM12 is 2 146 AT MIO 64F 5 User Manual cleared FOUT will become active and will drive out the selected and divided FOUT signal MM12 may also be controlled by loading the full Master Mode register in parallel When FOUT is gated on or off a transient pulse may be generated on the FOUT signal Disable Prefetch for Write Operations Coding gt A o m Description This command disables the prefetch circuitry during Write operations if does not affect Read operations This reduces the write recovery time and allows the user to use block move instructions for initialization of the Am9513A registers Once prefetch is disabled for writing Enable Prefetch for Write or a Reset command is necessary to re enable the prefetch circuitry for writing Note This command is only available in Am9513A de vices it is an illegal command in the non A Am9513 device Enable Prefetch for Write Operations Coding C7 C6 C5 C3 C2 CO Description This command re enables the prefetch Circuitry for Write operations It is used only to terminate the Disable Prefetch Command Note This command is only available Am9513A de vices it is an illegal comm
134. are media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTR
135. ated in timer waveform generation when the DACCOMP bit in Status Register 1 is set prematurely If DACFIFOEF is clear when another update occurs then an error has occurred This error indicates an underrun condition where rates are above the maximum rate of the DMA controller or interrupt handling capabilities The error condition is cleared by writing to the TMRREQ Clear Register or the DAC Clear Register Programming the Digital I O Circuitry The digital input circuitry is controlled and monitored using the Digital Input Register the Digital Output Register and the two bits DIOPAEN and DIOPBEN in Command Register 2 See the register bit descriptions earlier in this chapter for more information To enable digital output port A set the DIOPAEN bit in Command Register 3 To enable digital output port B set the DIOPBEN bit in Command Register 3 When a digital output port is enabled the contents of the Digital Output Register are driven onto the digital lines corresponding to that port The digital output for both ports A and B are updated by writing the desired pattern to the Digital Output Register In order for an external device to drive the digital I O lines the input ports must be enabled Clear the DIOPAEN bit in Command Register 3 if an external device is driving digital I O lines ADIO lt 3 0 gt Clear the DIOPBEN bit in Command Register 3 if an external device is driving digital I O lines BDIO lt 3 0 gt The Digital Input Register
136. ating Signals National Instruments Corporation 2 25 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 Single Ended Connections for Grounded Signal Sources NRSE Configuration If a grounded signal source is to be measured with a single ended configuration then the AT MIO 64F 5 must be configured in the NRSE input configuration The signal is connected to the positive input of the AT MIO 64F 5 PGIA and the signal local ground reference is connected to the negative input of the AT MIO 64F 5 PGIA The ground point of the signal should therefore be connected to the AI SENSE pin Any potential difference between the AT MIO 64F 5 ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the and this difference is rejected by the amplifier On the other hand if the input circuitry of the AT MIO 64F 5 is referenced to ground such as in the RSE input configuration this difference in ground potentials appears as an error in the measured voltage Figure 2 10 shows how to connect a grounded signal source to an AT MIO 64F 5 board configured for nonreferenced single ended input The AT MIO 64F 5 analog input circuitry must be configured for NRSE input configuration to make these types of connections Configuration instructions are included in Chapter 4 Register Map and Descriptions Ground Referenced Signal Source Measured m Voltage I O Connector AT
137. ation 2 10 Configuration and Status Register Group 4 4 to 4 22 Command Register 1 4 5 to 4 7 Command Register 2 4 8 to 4 10 5 31 Command Register 3 4 11 to 4 15 Command Register 4 4 16 to 4 18 overview 4 4 register map 4 1 Status Register 1 4 19 to 4 21 Status Register 2 4 22 5 26 continuous channel scanning definition 5 7 programming 5 7 to 5 8 continuous scanning data acquisition timing 3 11 counter block diagram 3 21 counter timer See Am9513A Counter Timer Register Group Am9513A System Timing Controller custom cables 1 5 customer communication viii F 1 cyclic waveform generation See DAC waveform circuitry and timing waveform generation programming CYCLICSTOP bit 3 17 to 3 18 4 18 5 18 D D lt 11 0 gt bit 4 33 4 34 D 15 0 bit 4 24 4 52 DAC Clear Register 4 44 5 23 5 26 5 30 DAC Event Strobe Register Group 4 41 to 4 44 DAC Clear Register 4 44 5 23 5 26 5 30 DAC Update Register 4 43 register map 4 2 TMRREQ Clear Register 4 42 5 23 5 26 5 30 5 31 DAC FIFO cyclic waveform generation 5 18 DAC waveform and circuitry timing 3 15 to 3 17 National Instruments Corporation Index 9 AT MIO 64F 5 User Manual Index DMA operations 5 30 programmed cycle waveform generation 5 19 DAC Update Register 4 43 DAC waveform circuitry and timing 3 14 to 3 19 See also waveform generation programming analog output waveform circuitry illustration 3 17 block diagram 3 15 DACMB lt 3 0
138. ation memory with a depth of 512 Thus the configuration memory can hold up to 512 configuration values for channel gain mode and range settings National Instruments Corporation 6 3 AT MIO 64F 5 User Manual Calibration Procedures 0110 16 384 0101 8 192 0100 4 096 0011 2 048 0010 1 024 ADC FIFO Length ON gt DAC FIFO Length Chapter 6 0110 16 384 0101 8 192 0100 4 096 0011 2 048 0010 1 024 00012 512 00002 256 00012 512 0000 256 7 6 51 4 3 21110 5 LSB Figure 6 4 ADC and DAC FIFO Depth Field If the ADC and DAC FIFO Depth Field contains the binary value 00010011 then the AT MIO 64F 5 board that was accessed contains an ADC FIFO buffer of depth 512 and a DAC FIFO buffer of depth 2 048 This information is extremely useful in determining how many values to read from the ADC FIFO or write to the DAC FIFO when a half full interrupt is generated For example if it is known that the ADC FIFO is 512 values deep and a half full interrupt is generated then 256 values can be read in at once without checking the Status Register O to see if the FIFO contains values Alternately if the DAC FIFO is 2 048 values deep and a half full interrupt is generated then 1 024 values can be read This can have a significant performance impact on software speed Reserved Reserved Reserved Reserved Reserved DACI Range DACO Range f gt Range 6 4 2
139. ause the onboard reference is very stable with respect to time and temperature it is seldom necessary to use the reference calibration routine Every year should be sufficient or whenever operating the board at an ambient temperature that is more than 20 C from the temperature at which the reference value was last determined Factory calibration is performed at approximately 25 C Analog Input Calibration To null out error sources that compromise the quality of measurements your input calibration routine should calibrate the analog input circuitry by adjusting the following potential sources of e Pregain offset offset error at the input of the e Postgain offset offset error at the input of the ADC e Unipolar offset additional postgain offset present only in unipolar mode Gain error of the analog input circuitry AT MIO 64F 5 User Manual 6 6 National Instruments Corporation Chapter 6 Calibration Procedures these error sources may be calibrated without making any connections to the AT MIO 64F 5 A properly calibrated board will be accurate in both bipolar and unipolar modes without adjustment Pregain offset contributes gain dependent error to the analog input system This offset is multiplied by the gain of the PGIA To calibrate this offset the routine should ground the inputs of the PGIA measure the input at two different gains in bipolar mode and adjust CALDACO until the measured offset
140. aveform Generation Timing 3 18 Digital I O Circuitry Block Diagram 3 19 Timing I O Circuitry Block Diagram oe dope 3 20 Counter Block Diagram u c i eo oh iita lone tacta 3 21 RTSI Bus Interface Circuitry Block Diagram eee 3 23 Initializing the Am9513A Counter Timer eee 5 3 Single Conversion Programming sese enne nennen eter 5 4 Single Channel Data Acquisition Programming eee 5 6 Continuous Scanning Data Acquisition Programming eee 5 8 Interval Scanning Data Acquisition Programming eee 5 0 AT MIO 64F 5 User Manual xiv National Instruments Corporation Figure 5 6 Figure 5 7 Figure 5 8 Figure 5 9 Figure 5 10 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure B 1 Figure C 1 Figure D 1 Table 1 1 Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 Table 4 9 Table 4 10 Table 4 11 Table 4 12 Table 4 13 Table Table Contents Resetting an Am9513A Counter Timer eese Cyclic Waveform Programming Programmed Cycle Waveform Programming eere Pulsed Cyclic Waveform Programming 52 222 5 0 6
141. bconnector and pin 26 of the extended analog input subconnector are AI GND signal pins AI GND is an analog input common signal that is routed directly to the ground tie point on the AT MIO 64F 5 These pins can be used for a general analog power ground tie point to the AT MIO 64F 5 if necessary Pin 19 of the MIO subconnector and pin 25 of the extended analog input subconnector comprise the AI SENSE signal In NRSE mode AI SENSE is connected internally to the negative input of the AT MIO 64F 5 PGIA In the DIFF and RSE modes this signal is driven by AI GND or left unconnected Each subconnector individually buffers the AI SENSE signal with AT MIO 64F 5 User Manual 2 18 National Instruments Corporation Chapter 2 Configuration and Installation a 1 2 resistor From either AI SENSE pin to the board there is 1 2 of resistance However from the AI SENSE signal at pin 19 to the AI SENSE signal at pin 25 there is 2 4 of resistance Pins 3 through 18 of the MIO subconnector are lt 0 15 gt signal pins while the remaining ACH lt 16 63 gt signal pins are located on the extended analog input subconnector These pins tied to the 64 analog input channels of the AT MIO 64F 5 In single ended mode signals connected to ACH lt 0 63 gt are routed to the positive input of the AT MIO 64F 5 PGIA In differential mode signals connected to lt 0 7 gt and ACH lt 16 39 gt are routed to the positive input of
142. be performed on a single channel configuration selection before switching to the next configuration memory selection Continuous Scanning Data Acquisition Timing Continuous scanning data acquisition uses the configuration memory register to automatically sequence from one analog input channel setting to another during the data acquisition sequence Continuous scanning cycles through the configuration memory without any delays between cycles Scanning is similar to the single channel acquisition in the programming of both the sample interval counter and the sample counter Scanning data acquisition is enabled through a register in the AT MIO 64F 5 register set Figure 3 7 shows the timing for a continuous scanning data acquisition sequence Trigger DAQPROG CONVERT Channel SCANCLK DAQCMPLT Interrupt DAQCLEAR Figure 3 7 Scanning Posttrigger Data Acquisition Timing In this sequence the timing is the same as the single channel acquisition except for the addition of the channel sequencing and the generation of the SCANCLK signal The first sampled channel is Channel 0 followed in time by Channel 1 and finally Channel 2 After this the sequence is repeated For this example the sequence consists of Channels 0 1 and 2 which are cycled through twice to generate six values of conversion data After the six samples have been acquired the sample counter terminates the data acquisition sequence The SCANCLK signal is generated t
143. by interleaving the data in the buffer The first location in the buffer should hold the first value to be transferred to DAC 0 the second should hold the first value to be transferred to DAC 1 the third should hold the second value to be transferred to DAC and so on If dual channel DMA operation has been selected for DMA requesting service DMA channel A and memory buffer A DMA A are served first When a DMA terminal count is received the board automatically switches the DMA operation to DMA channel B and memory buffer B DMA B Therefore the board can collect data to or from one buffer and simultaneously service data in another buffer If the DMA controller is programmed for auto reinitialize mode DMA A and DMA B are continuously served in turn If dual channel DMA operation has been selected to service both analog outputs memory buffer A DMA channel A and memory buffer B DMA channel B are concurrently serviced with buffer A serving DAC 0 and buffer B serving DAC 1 Interrupt Programming Seven different interrupts are generated by the AT MIO 64F 5 board Whenever a conversion is available to be read from the ADC FIFO Whenever the ADC FIFO is more than half full e Whenever a data acquisition sequence completes Whenever a DMA terminal count is received e Whenever a falling edge on the TMRTRIG pin of the Am9513A is detected e Whenever the DAC FIFO is less than full Whenever the DAC FIFO is half full These int
144. c control logic and contro registers Counters 1 and 2 have additional Alarm registers and comparators associated with them pius the extra logic necessary for operating in 24 hour time of day mode For real time operation the time of day logic will accept 50Hz 60Hz or 100Hz input frequencies Each general counter has a single dedicated output pin It may be turned off when the output is not of interest or may be configured in a variety of ways to drive interrupt controllers Dartington butfers bus drivers etc The counter inputs the Other hand are specifically not dedicated to any given interface line Considerable versatility is available tor configur ing both the input and the gating of individual counters This not only permits dynamic reassignment of inputs under soft ware control but aiso allows multiple counters to use a single input and a single gate pin to control more than one counter Indeed a single pin can be the gate for one counter and at the same time the count source for another Figure 5 Counter Logic Groups 3 4 and 5 Am9513A E 8 National Instruments Corporation Appendix E Element Pointer 00 Mode Register 01 Load Register 10 Register AMD Am9513A Data She GROUP ANO ELEMENT ADORESS COUNTER 1 MODE REGISTER COUNTER t LOAD REGISTER COUNTER NOLO REGISTER counrens 2 3 5 uco LOAD ANO WOLD REGISTERS MASTER MODE REGISTER Figure 6 Am9513A Register Access
145. can then be read to monitor the state of the digital I O lines as driven by the external device The logic state of all eight digital I O lines can be read from the Digital Input Register If the digital output ports are enabled the Digital Input Register serves as a read back register that is you can determine how the AT MIO 64F 5 is driving the digital I O lines by reading the Digital Input Register If any digital I O line is not driven it floats to an indeterminate value If more than one device is driving any digital I O line the voltage at that line may also be indeterminate In these cases the digital line has no meaningful logic value and reading the Digital Input Register may return either 1 or 0 for the state of the digital line AT MIO 64F 5 User Manual 5 26 National Instruments Corporation Chapter 5 Programming Programming the Am9513A Counter Timer Counters 1 2 and 5 of the Am9513A Counter Timer are available for general purpose timing applications The programmable frequency output pin FOUT is also available as a timing signal source These applications and a general description of the Am9513A Counter Timer are included in the Data Acquisition and Analog Output Timing Connections section in Chapter 2 Configuration and Installation The Timing I O Circuitry section in Chapter 3 Theory of Operation explains how the Am9513A is used on the AT MIO 64F 5 board Initialization of the Am9513A as required by AT MIO 64F
146. ce Considerations of the input and output signais for the Am9513A are specified with logic levels compatible with those of standard TTL circuits In addition to providing TTL compatible voltage levels other output conditions are specified to help configure non standard interface circuitry The logic level specifications take into account all worst case combinations of the three variables that affect the logic level thresholds ambient tem perature supply voltage and processing parameters A change in any of these toward nominal values will improve the actual operating margins and will increase noise immunity l Unprotected open gate inputs of high quality MOS transistors exhibit very high resistances on the order of perhaps 1015 ohms it is easy therefore in some circumstances for charge to enter the gate node of such an input faster than it can be discharged and consequently for the gate voitag to rise high enough to break down the oxides and destroy the transistor Am9513A National Instruments Corporation AMD Am9513A Data Sheet All inputs to the Am9513A include protection networks to help prevent damaging accumulations of static charge The protec tion circuitry is designed to slow the transitions of incoming current surges and to provide low impedance discharge paths for voltages beyond the normal operating levels Note howev er that input energy levels can nonetheless be too high to be successfully absorbed Conv
147. channels each having its own gain mode and range setting The channels are scanned in a round robin fashion separated in time by the programmed sample interval The final mode is the interval scanning mode This mode should be used if more than one channel needs to be monitored but not scanned at full speed Interval scanning sequences through the scan list with each channel conversion separated in time by the programmed sample interval then waits a scan interval before rescanning the list of channels The programming of each of these acquisition modes is described in the following sections Single Conversions Using the SCONVERT or EXTCONV Signal Programming the analog input circuitry to obtain a single A D conversion involves the following sequence of steps listed in Figure 5 2 Clear the A D circuitry Select a single analog input channel gain mode and range Initiate a single A D conversion Read the A D conversion result Figure 5 2 Single Conversion Programming AT MIO 64F 5 User Manual 5 4 National Instruments Corporation Chapter 5 Programming Generating a Single Conversion An A D conversion can be initiated in one of two ways a software generated pulse or a hardware pulse To initiate a single A D conversion through software access the Single Conversion Register To initiate a single A D conversion through hardware apply an active low pulse to the EXTCONV pin on the AT MIO 64F 5 I O connector See the
148. chapter describes in detail the address and function of each of the AT MIO 64F 5 control and status registers Note If you plan to use a programming software package such as NI DAQ or LabWindows with your AT MIO 64F 5 board you need not read this chapter However you will gain added insight into your AT MIO 64F 5 board by reading this chapter Register Map The register map for the AT MIO 64F 5 is shown in Table 4 1 This table gives the register name the register offset address the type of the register read only write only or read and write and the size of the register in bits The actual register address is obtained by adding the appropriate register offset to the I O base address of the AT MIO 64F 5 Registers are grouped in the table by function Each register group is introduced in the order shown in Table 4 1 then described in detail including a bit by bit description Table 4 1 AT MIO 64F 5 Register Map Register Name Offset Address Type Size Hex Configuration and Status Register Group Command Register 1 Write only Command Register 2 Write only Command Register 3 Write only Command Register 4 Write only Status Register 1 Read only Status Register 2 Read only Analog Input Register Group ADC FIFO Register Read only CONFIGMEM Register Write only Analog Output Register Group DACO Register Write only Register Write only continues National Instruments Corporation 4 1 AT MIO 64F 5 User Manual
149. cifications Gain error Using internal reference After calibration Before calibration Temperature coefficient Using external reference Temperature coefficient Output voltage ranges software selectable Current drive capability Output noise Output impedance External reference input impedance External reference input range External reference bandwidth 3 dB Appendix A 0 002 20 ppm maximum 0 44 10 ppm C 0 25 0 1 adjustable with to 50 mV offset 5 ppm C 0 to 10 V unipolar mode 10 V bipolar mode 10 mA short circuit protected 0 5 mV rms DC to 1 MHz 0 1 Q maximum 100 GQ 12V protected to x15 V power off 30 V power on DC to 500 kHz Explanation of Analog Output Specifications Offset error is the amount of possible voltage offset error in the analog output circuitry expressed in mV Gain error is the amount of possible deviation from ideal gain of the analog output circuitry expressed as a proportion of the gain The total linear error for a DAC at a given output voltage is the output voltage times the gain error plus the offset error Relative accuracy in a DAC is the same as integral nonlinearity because no uncertainty is added by quantization Unlike an ADC every digital code in a DAC represents a specific analog value rather than a range of values The relative accuracy of the system is therefore limited to the worst case deviation from the ideal correspond
150. circuitry may not function In such a configuration the software reset command must be issued following power up to reset the Am9513A Read The active low Read signal is conditioned by Chip Select and indicates that internal information is to be transferred to the data bus The source will be determined by the being addressed and for Data Port reads by the contents of the Data Pointer register WA and Should be mutually exclusive Write The active iow Write signal is conditioned by Chip Select and indicates that data bus information is to be transferred to an internal location The destination will be determined by the being addressed and tor Data Port writes by the contents of the Data Pointer register and RD should be mutually exciusive Control Data The Controi Data signal selects source and destination locations for Read and Write operations on the data bus Control Write operations load the Command register and the Data Pointer Control Read operntions output the Status register Data Read arid Data Write transfers communicate with ali other internai registers Indirect addressing at the data port is controlled internally by the Data Pointer register 2 120 Am9513A AT MIO 64F 5 User Manual National Instruments Corporation Appendix E awe aa ew P Figure 1 Interface Signal Summary Figure 1 summarizes the interface signals and their abbreviations for the STC Figure 2 Data Bus Assignments Interfa
151. cted through software The reference can be either internal or external whereas the range can be either bipolar or unipolar Analog Output Reference Selection Each DAC can be connected to the AT MIO 64F 5 internal reference of 10 V or to the external reference signal connected to the EXTREF pin on the I O connector This signal applied to EXTREF must be between 10 and 10 V Both channels need not be configured for the same mode Analog Output Polarity Selection Each analog output channel can be configured for either unipolar or bipolar output A unipolar configuration has a range of 0 to Vref at the analog output A bipolar configuration has a range of V ref to Vet at the analog output Vref is the voltage reference used by the DACs in the analog output circuitry and can be either the 10 V onboard reference or an externally supplied reference between 10 and 10 V Both channels need not be configured for the same range National Instruments Corporation 2 9 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 Selecting a bipolar range for a particular DAC means that any data written to that DAC will be interpreted as two s complement format In two s complement mode data values written to the analog output channel range from 2 048 to 2 047 decimal 800 to 7FF hex If unipolar range is selected data is interpreted in straight binary format In straight binary mode data values written to the analog output channel rang
152. cular counter in the Am9513A use the following programming sequence All writes are 16 bit operations values given are hexadecimal The equation 2 ctr 1 means 2 raised to ctr 1 If ctr is equal to 4 then 2 ctr 1 results in 2 3 or 2 2 2 or 8 This result can also be obtained by shifting left three times AT MIO 64F 5 User Manual 5 16 National Instruments Corporation Chapter 5 Write 2 ctr 1 to the Am9513A Command Register Write ctr to the Am9513A Command Register Write 0x0004 to the Am9513A Data Register Write OxFFOS ctr to the Am9513A Command Register Write 0x0003 to the Am9513A Data Register Write OxFF40 2 4 ctr 1 to the Am9513A Command Register Write OxFF40 2 4 ctr 1 to the Am9513A Command Register Programming Disarm X mode Point to the Counter X mode register Store the Counter X mode value Point to the Counter X load register Store a nonterminal count value Load Counter X Load Counter X guarantee nonterminal count state Figure 5 6 Resetting an Am9513A Counter Timer National Instruments Corporation 5 17 AT MIO 64F 5 User Manual Programming Chapter 5 Programming the Analog Output Circuitry The voltages at the analog output circuitry output pins pins DACO OUT and DACI OUT on the AT MIO 64F 5 I O connector are controlled by loading the DAC in the analog output channel with a 16 bit digital co
153. d Installed e Operating System e Operating System Version e Programming Language e Programming Language Version Other Boards in System e Base I O Address of Other Boards DMA Channels of Other Boards e Interrupt Level of Other Boards Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title AT MIO 64F 5 Manual Edition Date February 1994 Part Number 320487 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway MS 53 02 MS 53 02 Austin TX 78730 5039 512 794 5678 Index Numbers Symbols 5 V power pins warning against connecting 2 30 5 V signal 2 15 C 2 A A2DRV bit 4 8 A2RCN bit 4 8 A4DRYV bit 4 8 AARCN bit 4 8 5 26 A6 through 0 bits 5 29 ACH lt O 15 gt signals 2 14 2 ACH lt 16 27 gt signals 2 18 D ACH lt 28 39 gt signals 2 18 D ACH lt 40 51 gt signals 2 18 D lt 52 63 gt signals 2 18 D A D conversion results in ADC FIFO 4 24 reading single conv
154. d in order to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is one that is connected in some way to the building system ground and is therefore already connected to common ground point with respect to the AT MIO 64E5 board assuming that the PC AT is plugged into the same power system Nonisolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 mV and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improperly measured this difference may show up as an error in the measurement The following connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal Input Configurations The AT MIO 64F 5 can be configured for one of three input modes NRSE RSE or DIFF The following sections discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources Table 2 5 summarizes the recommended input configuration for both types of signal sources AT MIO 64F 5 User Manual 2 20 Nat
155. d source edge after application of the retriggering gate edge the contents of the Load register will be transferred into the counter Counting will resume on the second qualified source edge after the retriggering Gate Occur while the Gate is active 2 135 AT MIO 64F 5 User Manual AMD Am9513A Data Sheet RAN Figure 15 Mode L Waveforms CO GEND CD C ED Figure 15n Mode N Waveforms MODE O Software Triggered Strobe with Edge Gating and Hardware Retriggering owas eua uris wre ew euro one mx 5 oma Mode shown in Figure 150 is similar Mode except that counting will not begin until an active going Gate edge is applied to an armed counter and the Gate level is not used to 2 136 AT MIO 64F 5 User Manual E 22 modulate counting The counter must be armed before appli cation of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded irrespective of the Gate level the counter will count source edges after the triggering Gate edge until the first TC On the first TC the counter will be reloaded from the Load register and disarmed command and a new Gate edge must be applied in that order to initiate a new counting cycie Unlike Modes C F and L which disregard the Gate input once counting
156. data is interpreted in two s complement form National Instruments Corporation 4 33 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 Register Writing to the DACI Register loads the value written to the analog output DAC channel 1 in immediate update mode If posted update mode is used the value written to the DACI Register is buffered and updated to the analog output DAC channel 1 only after an access to the DAC Update Register or a timer trigger is received in one of the prescribed paths Address Base address 12 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 12 X Don t care bits 11 0 D lt 11 0 gt Data bus to the analog output DACs The data written to the DACs is interpreted in straight binary form when DAC channel 1 is configured for unipolar operation When DAC channel is configured for bipolar operation the data is interpreted in two s complement form AT MIO 64F 5 User Manual 4 34 National Instruments Corporation Chapter 4 Register Map and Descriptions ADC Event Strobe Register Group The ADC Event Strobe Register Group consists of five registers that when written to cause the occurrence of certain events on the AT MIO 64F 5 board such as clearing flags and starting A D conversions Bit descriptions of the six registers making up the ADC Event Strobe Register Group are given on the following pages
157. ddress These register size accesses must be adhered to for proper board operation Performing a byte access on a word location is an invalid operation and should be avoided The converse is also true Performing a word access on a byte location is also an invalid operation and should be avoided You should pay particular attention to the register sizes because they are very important AT MIO 64F 5 User Manual 4 2 National Instruments Corporation Chapter 4 Register and Descriptions Register Description Format The remainder of this register description chapter discusses each of the AT MIO 64F 5 registers in the order shown in Table 4 1 Each register group is introduced followed by a detailed bit description of each register The individual register description gives the address type word size and bit map of the register followed by a description of each bit The register bit map shows a diagram of the register with the MSB shown on the left bit 15 for a 16 bit register bit 7 for an 8 bit register and the LSB shown on the right bit 0 A square is used to represent each bit Each bit is labeled with a name inside its square An asterisk after the bit name indicates that the bit is inverted negative logic In many of the registers several bits are labeled with an X indicating don t care bits When a register is read these bits may appear set or cleared but should be ignored because they have no significance The bi
158. de The DAC is loaded by writing the digital code to the DACO and Registers and then the converted output is available at the I O connector Writing to the DACO Register controls the voltage at the DACO OUT pin while writing to the DACI Register controls the voltage at the DACI OUT pin The analog output on pins DACO OUT and DACI OUT can be updated in one of three ways immediately when DACO or DAC1 is written to when an active low pulse is detected on the TMRTRIG signal or when the DAC Update Register is strobed The TMRTRIG signal is either the EXTTMRTRIG signal from the I O connector or an internal signal from the output of Counters 1 2 3 or 5 depending on the state of the A4RCV bit in Command Register 2 The update method is selected through mode bits in the Command Register 4 In the waveform mode where a timer trigger generates an update for the DACs and a request for new data the DAC FIFO is used to buffer the incoming data to both of the DAC channels Because this FIFO is 2 048 values deep the last value buffered by the DAC FIFO could lag the output of the DAC channel by up to 2 048 times the update interval Requests can be programmed to be generated whenever the DAC FIFO is not full or only when the FIFO is less than half full If the half full method is used 1 024 values can be written at once without reading the DAC FIFO flags after each subsequent transfer to keep from overfilling the FIFO This mode results in a signif
159. de of the noise the character of the noise can be determined National Instruments has determined that the character of the noise in the AT MIO 64F 5 is fairly Gaussian so the noise specifications given are the amounts of pure Gaussian noise required to produce our readings Overvoltage Protection The amount of input overvoltage the AT MIO 64F 5 can tolerate is limited primarily by the current handling of the input multiplexers While each input can safely handle its rated overvoltage it would be unwise to stress all inputs simultaneously Survival with more than one input of any multiplexer at maximum overvoltage is not guaranteed unless the overvoltages are of the opposite sign The 64 input channels are divided among the four input multiplexers in the following groups ACHO ACH15 ACH16 ACH23 and ACH40 ACH47 ACH24 ACH31 and 48 55 and ACH32 ACH39 and ACH56 ACH63 It is important to realize that the overvoltage specification is a survival specification only This means that the board will not be damaged by application of the specified overvoltage It does not mean that measurement integrity will be preserved even if the channel being measured is not the one being subjected to overvoltage stress Analog Data Acquisition Rates Single Channel Acquisition Rates The AT MIO 64F 5 operates at a data acquisition rate of at least 200 ksamples sec Permissible data acquisition rates are determined by the minimum A D conversion time of t
160. e the counter contents are saved in the Hold register On the first source edge after the retriggering Gate edge the Load register contents will be transferred into the counter Counting will resume on the second source edge after the retriggering Gate edge 2 137 E 23 AT MIO 64F 5 User Manual AMD 9513 Data Sheet CED Ce OUTPUT TOGGLEO OUTPuT f X Figure 15q Mode Q Waveforms INININININININININFNTNTNTINTNTNTNININC Figure 15 Mode R Waveforms MODE S RELOAD SOURCE Fows owe owss owz owr owe T curo cuna Px Tx owe cma ow 947 ome ows owe cme cw Str be In this mode the reload source for LOAD commands spective of whether the counter is armed or disarmed and for TC initiated reloads is determined by the Gate input The Gate input in Mode S is used only to select the reload source not to start or modulate counting When the Gate is Low the Load register is used when the Gate is High the Hold register is used Note the Low Load High Hold mnemonic convention Once armed the counter will count to TC twice and then disarm itself On each TC the counter will
161. e Immediate update mode is self evident You write a value to the DAC and its voltage is immediately available at the output In posted update mode the voltage is not available at the output until a timer trigger signal initiates an update This mode has advantages in waveform generation applications which need precisely timed updates that are not software dependent AT MIO 64F 5 User Manual 3 14 National Instruments Corporation Chapter 3 Theory of Operation DAC Waveform Circuitry Figure 3 10 depicts the three different data paths to the analog output DACs Update Serial RTSI Data RTSI Latch R_Latch LATCHEN Local Latch Local Data Bus DAC Data Bus LATCHEN Control Circuitry Control Circuitry DACFIFOHF DACFIFORT DACEIFOEF DACFIFORS Di DACFIFORD RENE To Figure 3 10 Analog Output Waveform The local latch is used for immediate updating of the DACs When data is written to the DACs in immediate updating mode the data is directly routed to the DACS to be converted to a voltage at the output In this mode the Update signal is held low or true The only path available for data transfer to the DACS in the immediate update mode is the local latch The path that the data takes to the DACs is determined by the DAC mode enabled through a register in the AT MIO 64F 5 register set The DAC FIFO and RTSI latch are used for posted updating of the DACs Data written to the DACS is buffered by t
162. e CONFIGMEMLD Register should be strobed following a DAQ Clear strobe AT MIO 64F 5 User Manual 4 38 National Instruments Corporation Chapter 4 Register and Descriptions DAQ Start Register Accessing the DAQ Start Register location initiates a multiple A D conversion data acquisition operation Note Several other pieces of AT MIO 64F 5 circuitry must be set up before a data acquisition run can occur See Chapter 5 Programming Address Base address 1D hex Type Read only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Initiates a programmed data acquisition sequence Note Multiple A D conversion data acquisition operations can be initiated in one of three ways by accessing the Start DAQ Register or by detecting an active low signal on either the EXTTRIG or the RTSITRIG signal The EXTTRIG signal is connected to pin 38 on the I O connector To trigger the board with the Start DAQ Register the RTSITRIG signal in Command Register 1 must be cleared In addition either the EXTTRIG signal should be unasserted or the DIS signal in Command Register 4 must be set Otherwise strobing the Start DAQ Register has no effect National Instruments Corporation 4 39 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 Single Conversion Register Accessing the Single Conversion Register location initiates a single A D conversion Address Base address 1D hex
163. e from 0 to 4 095 decimal to FFF hex Digital I O Configuration The AT MIO 64F 5 contains eight lines of digital I O for general purpose use The eight digital I O lines supplied are configured as two 4 bit ports Each port can be individually configured through programming of a register in the board register set as either input or output At system startup and reset the digital I O ports are both configured for input Board and RTSI Clock Configuration When multiple AT Series boards are connected via the RTSI bus you may want all of the boards to use the same 10 MHz clock This arrangement is useful for applications that require counter timer synchronization between boards Each AT Series board with a RTSI bus interface has an onboard 10 MHz oscillator Thus one board can drive the RTSI bus clock signal and the other boards can receive this signal or disconnect from it Many functions performed by the AT MIO 64F 5 board require a frequency timebase to generate the necessary timing signals for controlling ADC conversions DAC updates or general purpose signals at the I O connector You select this timebase through programming one of the registers in the AT MIO 64F 5 register set The AT MIO 64F 5 can use either its internal 10 MHz timebase or it can use a timebase received over the RTSI bus In addition if the board is configured to use the internal timebase it can also be programmed to drive its internal timebase over the RTSI bus t
164. e programmed for various operations The Am9513A Counter Timer is described briefly in Chapter 3 Theory of Operation For detailed programming information consult Appendix E AMD Am9513A Data Sheet For detailed applications information consult the 9513 9513 System Timing Controller technical manual published by Advanced Micro Devices Inc Pulses and square waves can be produced by programming Counter 1 2 or 5 to generate a pulse signal at its OUT output pin or to toggle the OUT signal each time the counter reaches the terminal count For event counting one of the counters is programmed to count rising or falling edges applied to any of the Am9513A SOURCE inputs The counter value can then be read to determine the number of edges that have occurred Counter operation can be gated on and off during event counting Figure 2 17 shows connections for a typical event counting operation in which a switch is used to gate the counter on and off National Instruments Corporation 2 33 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 SOURCE GATE Signal Source DIG GND MIO Subconnector AT MIO 64F 5 Board Figure 2 17 Event Counting Application with External Switch Gating To perform pulse width measurement a counter is programmed to be level gated The pulse to be measured is applied to the counter GATE input The counter is programmed to count while the signal at the GATE input is either high o
165. e to the channel configuration memory accessing the CONFIGMEMLD Register loads the first channel configuration value Writing to the CONFIGMEMLD Register again loads the second channel configuration value and so on Strobing the DAQ Clear Register resets the channel configuration memory to the first value but does not load the value This does not clear the memory of any values written to it prior to the DAQ Clear strobe After strobing the DAQ Clear Register the CONFIGMEMLD Register should be strobed to load the first value A scanned data acquisition can be initiated from any location in the channel configuration memory by using this method National Instruments Corporation 4 37 AT MIO 64F 5 User Manual Register Map and Descriptions Chapter 4 DAQ Clear Register Accessing the DAQ Clear Register location clears the data acquisition circuitry Address Base address 19 hex Type Read only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Cancels any data acquisition operation in progress empties ADC FIFO clears the OVERRUN bit in Status Register 1 clears the OVERFLOW bit in Status Register 1 clears the DAQCOMP bit in Status Register 1 clears any pending ADC interrupt and resets the configuration memory to the initial value no values are lost Note If the channel configuration memory contains valid information and no new values are to be added before restarting the data acquisition sequence th
166. e toggie bit for even longer counts This is easily accomplished by selecting a TC Toggled output mode and wiring OUTN to one of the SRC inputs Gating Control Counter Mode bits CM15 CM14 CM13 specify the hardware gating options When no gating is selected 000 the Am9513A O National Instruments Corporation on the status of the Gating Contro field and bits CMS and E 29 AMD Am9513A Data Sheet Counter will proceed unconditionally as long as it is armed For any other gating mode the count process is conditioned by the specified gat ng configuration For a code of 100 in this field counting can proceed only when the pin labeled GATEN associated with Counter N is at a logic high level When it goes LOW counting is simply suspended until the Gate goes HIGH again A code of 101 performs the Same function with an opposite active polarity Codes 010 and 011 offer the same function as 100 but specify alternate input pins as Gating Sources This allows any of three interface pins to be used as gates for given counter On Counter 4 for example pin 34 pin 35 or pin 36 may be used to perform the gating function This also allows a single Gate pin to simulta neously control up to three counters Counters 1 and 5 are considered adjacent when using TCN 1 001 Gate N 1 010 and Gate N 1 011 controis For codes of 110 or 111 in this field counting proceeds after the specified active Gate edge until one or
167. each rising edge on GATE2 is encountered The terminal count active low edge will restart the waveform generation process National Instruments Corporation 5 25 AT MIO 64F 5 User Manual Programming Chapter 5 Servicing Update Requests Updating the DACs using a timer signal can be handled using either polled I O interrupts or DMA requests Upon the application of a falling edge signal to the TMRTRIG signal both DACs are updated and TMRREQ in Status Register 1 is set and if DMA or interrupts are enabled a request is generated TMRTRIG can be connected to selected internal signals on the RTSI bus with set or the external signal EXTTMRTRIG with A4RCV cleared In the polled I O mode the TMRREQ signal must be monitored in the Status Register to determine when the previous value has been updated to the DAC and a new value is required The most desirable solution involves the use of interrupts because the PC is not dedicated to monitoring the Status Register If interrupts are enabled an interrupt occurs when TMRREQ is set In interrupt mode TMRREQ must be cleared using the TMRREQ Clear Register before exiting the interrupt routine This clears the interrupt request The best method of servicing update requests is with DMA since this is done in parallel with the PC CPU If DMA is enabled DMA requests are generated when TMRREQ is set When the DMA controller acknowledges the request TMRREQ is automatically cleared An error is indic
168. eared the Digital Output Register drivers are set to a high impedance state therefore an external device can drive the DIO lt 4 1 gt digital lines National Instruments Corporation 4 11 AT MIO 64F 5 User Manual Register and Descriptions Bit 12 11 10 Name DMATCINT DACCMPLINT DAQCMPLINT I O INT DMACHA DMACHB AT MIO 64F 5 User Manual Chapter 4 Description continued DMA Terminal Count Interrupt Enable This bit controls the generation of an interrupt when a DMA terminal count pulse is received from the DMA controller in the PC AT If DMATCINT is set an interrupt request is generated when the DMA controller transfers the final value on the primary DMA channel channel A or the secondary DMA channel channel B The interrupt request is serviced by strobing the appropriate DMATC Clear Register When DMATCINT is cleared no DMA terminal count interrupts are generated DAC Complete Interrupt Enable This bit controls the generation of an interrupt when a DAC sequence completes If DACCMPLINT is set an interrupt request is generated when the sequence completes The interrupt request is serviced by strobing the TMRREQ Clear or DAC Clear Register When DACCMPLINT is cleared completion of a sequence does not generate an interrupt A DAC sequence ends by running its course or when an error condition occurs such as UNDERFLOW DAQ Complete Interrupt Enable This bit controls the generation
169. ection 2 9 reference selection 2 9 theory of operation 3 14 Analog Output Register Group 4 31 to 4 34 analog output voltage versus digital code bipolar mode 4 31 to 4 32 unipolar mode 4 31 DACO Register 4 33 DACI Register 4 34 overview 4 31 to 4 32 register map 4 1 analog output signal connections 2 27 to 2 28 analog output specifications differential nonlinearity A 6 AT MIO 64F 5 User Manual Index 4 National Instruments Corporation Index gain error A 6 list of A 5 to A 6 offset error A 6 relative accuracy A 6 AO GND signal 2 14 2 27 to 2 28 C 2 AT bus interface 2 3 AT MIO 64F 5 See also specifications theory of operation block diagram 3 1 board description 1 1 to 1 2 analog input 1 1 analog output 1 1 digital and timing I O 1 2 definition v illustration of 1 2 initializing 5 2 kit contents 1 3 optional equipment 1 4 to 1 5 optional software 1 3 parts locator diagram 2 2 register map 4 1 to 4 2 unpacking 1 6 uses 1 2 AT MIO 64F 5 PGIA analog input circuitry 3 6 Channel Gain Select GAIN 2 0 bit 4 28 common mode signal rejection considerations 2 26 to 2 27 differential connections 2 21 to 2 24 illustration 2 19 input signal connections 2 18 to 2 19 single ended connections 2 24 2 26 National Instruments Corporation Index 5 AT MIO 64F 5 User Manual Index B B6 through BO bits 5 29 base I O address default settings for National Instrument products 2 4
170. ed by DAC 1 If DACIDSP is cleared the serial RTSI link is disabled DAC 0 DSP Link Enable This bit controls the serial link from the AT DSP2200 to DAC 0 of the analog output section If DACIDSP is set then the serial link is enabled Data is sent from the AT DSP2200 over the RTSI bus and is accepted by DAC O If DACIDSP is cleared the serial RTSI link is disabled DAC Mode Select These bits control the mode used for writing to and updating the DACs is used to select the number of reads from the DAC FIFO per update signal If DACMB3 is clear there will be only one read of the DAC FIFO per update If DACMB3 is set the circuitry will determine whether to perform one read or two reads from the DAC FIFO depending on the data in the FIFO See Table 4 6 for available modes and bit patterns Table 4 6 Analog Output Waveform Modes Waveform Mode Mode Description Single update with no timed interrupts Single update with timed interrupts DMA access through DAC FIFO with single requesting DMA access through DAC FIFO with half flag requesting FIFO continuous waveform generation buffer in DAC FIFO Programmed cycle waveform generation Counter 1 stops after N cycles Programmed cycle waveform generation Counter 2 stops after N cycles Programmed cycle waveform generation Counter 5 stops after N cycles Pulsed waveform Counter 1 stops after N cycles Counter 2 restarts DAC Update Gate This bit contro
171. ed by input protection resistors and the input multiplexer has 16 analog input channels Analog input overvoltage protection is x25 V powered on and 15 V powered off Input signals should be in the range of 10 to 10 V for bipolar operation and 0 to 10 V for unipolar operation Bipolar or unipolar mode configuration is programmed on a per channel basis and is controlled through one of the registers in the AT MIO 64F 5 register set Analog Input Configuration Inputs can be configured for differential or single ended signals on a per channel basis through a register in the AT MIO 64F 5 register set In addition single ended inputs can be configured for referenced or nonreferenced signals In the differential configuration one of input Channels 0 through 7 or 16 through 39 is routed to the positive input of the PGIA and one of Channels 8 through 15 or 40 through 63 is routed to the negative input of the PGIA In the single ended configuration one of input Channels 0 through 63 is routed to the positive input of the PGIA The negative input of the PGIA in single ended mode is connected to either the input ground or the AI SENSE signal at the I O connector depending on the software configuration PGIA The PGIA fulfills two purposes on the AT MIO 64F 5 board It converts a differential input signal into a single ended signal with respect to the AT MIO 64F 5 ground for input common mode signal rejection This conversion allows the input analog signa
172. ed or Floating Signal Sources Figure 2 8 shows how to connect a floating signal source to an AT MIO 64F 5 board configured in the DIFF input mode The AT MIO 64F 5 analog input circuitry must be configured for DIFF input to make these types of connections Configuration instructions are included in Chapter 4 Register Map and Descriptions Floating Signal Source ACH 8 15 2 lt 40 63 gt V Measured m Voltage Bias Current Return Paths Input Multiplexers AISENSE I O Connector AT MIO 64F 5 Board in the DIFF Input Configuration Figure 2 8 Differential Input Connections for Nonreferenced Signals Figure 2 8 shows two bias resistors connected in parallel with the signal leads of a floating signal source If the source is truly floating it is not likely to remain within the common mode signal range of the PGIA and the PGIA will saturate causing erroneous readings You must reference the source to AI GND The best way is simply to connect the positive side of the signal to the positive input of the and connect the negative side of the signal to AI GND as well as to the negative input of the PGIA This works well for DC coupled sources with low source impedance less than 100 2 However for larger source impedances this connection leaves the differential signal path significantly out of balance Noise which couples electrostatically onto the positive line does not couple onto the negative
173. ed to the multiplexer output of Channels 8 through 15 and 40 through 63 Referenced single ended configuration has up to 64 single ended inputs with the negative input of the PGIA referenced to analog ground NRSE Nonreferenced single ended configuration has up to 64 single ended inputs with the negative input of the tied to AI SENSE and not connected to ground While reading the following paragraphs you may find it helpful to refer to the Analog Input Signal Connections section later in this chapter which contains diagrams showing the signal paths for the three configurations DIFF Input 32 Channels DIFF input means that each input signal has its own reference and the difference between each signal and its reference is measured The signal and its reference are assigned an input channel This is the recommended configuration With this input configuration the AT MIO 64F 5 can monitor up to 32 different analog input signals This configuration is selected via software See AT MIO 64F 5 User Manual 2 6 National Instruments Corporation Chapter 2 Configuration and Installation the configuration memory register and Table 4 9 in Chapter 4 Register Map and Descriptions The results of this configuration are as follows e One of channels 0 through 7 or 16 through 39 is tied to the positive input of the of channels 8 through 15 or 40 through 63 is tied to the negative input of the
174. ed with the analog input section and four calibration DACS with the analog output section two for each output channel After the calibration process is complete each calibration DAC is at a known value Because these values are lost when the board is powered down they are also stored in the onboard EEPROM for future referencing Figure 6 1 shows where information is stored in the EEPROM Factory Information Factory Reference Factory Bipolar Area A DAC Channel T Gan DAC Channel 1 Offset DAC Channel 0 Gain DAC Channel 0 Offset ADC Unipolar Offset User References D GENERA 0 ser Reference 4 MSB 0 ser Reference 4 LSB 0 ser Reference 3 MSB 0 ser Reference 3 LSB 0 ser Reference 2 MSB 0 ser Reference 2 LSB _ 0 ser Reference 1 MSB 0 ser Reference 1 LSB Figure 6 1 AT MIO 64F 5 EEPROM Map cc National Instruments Corporation 6 1 AT MIO 64F 5 User Manual Calibration Procedures Chapter 6 The AT MIO 64F 5 is factory calibrated before shipment and the associated calibration constants are stored in the factory area of the EEPROM Table 6 1 lists what is stored in the EEPROM factory area Table 6 1 EEPROM Factory Area Information Location Description Year of reference calibration for example 92 1992 Month of reference calibration for example 2 February Day of reference calibration for example 29 29th Reserved Board code AT MIO 64F 5 3 Revision and Subr
175. ee Figure 19 TC Terminal Count On each Terminal Count TC the counter will reload itseif from the Load or Hold register TC is defined as that period of time when the counter contents would have been zero had no reload occurred Some special conditions apply to counter operation immediately before and during TC 1 In the clock cycle before TC an internal signal is generated that commits the counter to go to TC on the next count and retriggering by a hardware Gate edge Modes N and or a software LOAD or LOAD AND ARM command will not extend the time to TC Note that the next count driving the counter to TC can be caused by the application of a count source edge in level gating modes the edge must occur while the gate is active or it will be disregarded by the application of a LOAD or LOAD AND ARM command see 2 below or by the application of a STEP command 2 1f a LOAD or LOAD AND ARM command is executed during the cycle preceding TC the counter will immediately go to TC if these commands are issued during TC the TC state will immediately terminate 3 When TC is active the counter will always count the next Source edge issued to it even if it is disarmed or gated off during TC This means that TC will never be active for longer than one count period and it may in fact be shorter if amp STEP command or a LOAD or LOAD AND ARM command is applied during TC see item 2 above This also means that a counter t
176. ee analog input configuration input multiplexers See also CONFIGMEM Register address selection bits CHANSEL lt 5 0 gt 4 27 to 4 28 description 3 6 input polarity and range configuring 2 8 actual range and measurement precision versus input range selection and gain 2 8 considerations for selecting ranges 2 8 installation See also configuration hardware installation 2 10 to 2 11 unpacking the AT MIO 64F 5 1 6 lt 2 gt bit 4 15 integral nonlinearity A 3 internal update counter selecting 5 23 interrupts bit settings generation of interrupts 4 13 to 4 14 interrupt level selection 4 15 configuration 2 5 default settings for National Instrument products 2 4 PC I O channel interface 3 4 programming 5 31 interval channel scanning definition 5 7 programming 5 8 to 5 10 interval scanning data acquisition timing 3 12 INTGATE bit 4 6 I O connector pin assignments A T MIO 64F 5 I O connector 2 12 B 1 extended analog input subconnector 2 17 D 1 MIO subconnector 2 13 I O INT bit 4 12 J jumpers and switches base I O address factory settings 2 3 default settings for National Instrument products 2 4 example base I O address switch settings 2 3 switch settings with base I O address and address space 2 5 National Instruments Corporation Index 15 AT MIO 64F 5 User Manual Index L LabWindows software 1 3 linear errors equivalent gain and offset errors in 12 bit systems A 3 gain error
177. eeeeeeeeeeeeeee enne ennt etes 5 30 Interrupt Programming idiot oreste ot ater aeei It uus tocius Idque dus 5 31 Chapter 6 Calibration Procedures ooo ee e M aces 6 1 Calibration Equipment ccs tel 6 5 Calibration A 6 5 Calibration Channels usi lod edle ter ca Aaa add dede 6 6 Reference Calibration s uota oct eun DS Eq pud ttam anuli aS 6 6 Analog Input Calibration 6 6 Znalos Outpat cea peste oe RSS 6 7 Appendix A Specifications t OIM 1 Analog EA LAUS 1 Explanation of Analog Input A 2 AT MIO 64F 5 User Manual Xii National Instruments Corporation Contents Tangat EIOS assieme ee toi tari SP tma oda ERU HND P KD USt 2 No litbat ENOS occa eee Ue REVUES UO 3 Io Y 4 versas PM Mann nz Ban GEM DON MB NU A 4 ACHMSINOH 6 2 4 Single Channel Acquisition Rates 2 22 2 4 Multiple Chan
178. eese 2 1 Board SALTON od su Ute Me tst aree node 2 1 sis Matte 2 3 Base UO Address 2 3 Interrupt and DMA Channel 2 5 Analog Input Configuratiol ed Serio ele nee 2 6 Input otl edo edat 2 6 DIFP Input 32 Channels 5i rone tH eet tni 2 6 RSE Input 64 Channels 25 ti en cecdeasasuasacsvansccerssecedastdesdaceastes 2 7 NRSE Input 64 Channels oon petere 2 7 Input Polarity and Input 2 8 Considerations for Selecting Input Ranges 2 8 Analog Output Configuration 2 9 Analog Output Reference Selection decise tertie testo te desee aeri 2 9 Analog Output Polarity Selection oed e ote eee Pape erecta 2 9 Digital Conf Surau DD aia 2 10 Board and RTSI Clock Configuration eese nennen nennen nennen 2 10 Hardware Installation d AE od eR 2 10 Signal Connections cesses ve Seded edle ae ORTA 2 11 MIO Subconnector Signal Connection Descriptions ees 2 14 Extended Analog Input Subconnector Signal Descriptions 2 18 T
179. egister set The general location of the registers in the I O space of the PC is determined by the base address selection whereas the specific location of the registers within the register set is determined by the AT MIO 64F 5 decode circuitry Figure 2 1 shows the parts locator diagram of the AT MIO 64F 5 board National Instruments Corporation 2 1 AT MIO 64F 5 User Manual Chapter 2 Configuration and Installation osn osn National Instruments Corporation sn 6015 een MRE Ss 000 10000 009005 00000971 iens MIC raat 5b i EE qu teca 8558 ERG ERG S 001000000 002002000 900000000 000000000 Hed 5 86 ON 00090002 10010200200 0009000000 00000 ce 10000200 88Z882588HASZZA2382 8 gan 90 07 8832 ces w E eg aides Cee MA Soc 8 8 3 S 558 2 2 58 oa 8 a 02020 LP Se pg n E gue 2n c 909004 000900 00 can o E o n eee 7882 BE Pee Hesiod Bostock pom ma WU e 89 526 oia MT EE 48 rS 8 HER EXE a fr sm Stn NM 700019007 Y 5 885
180. en the first DMA channel terminal count is reached the circuitry automatically sequences the second DMA channel When the second DMA channel terminal count is reached the circuitry returns to the first DMA channel for servicing The effect of the DMA channel Clear Register is to initialize this circuitry Address Type Word Size Bit Map Strobe Effect Base address OB hex Read only 8 bit Not applicable no bits used Clears the dual DMA channel circuitry dual DMA mode only AT MIO 64F 5 User Manual 4 46 National Instruments Corporation Chapter 4 Register and Descriptions DMATCA Clear Register Accessing the DMATCA Clear Register will clear the DMATCA signal in Status Register 1 and it will acknowledge the interrupt generated from the Channel A terminal counter interrupt When the selected DMA channel A reaches its terminal count the DMATCA signal in the Status Register is asserted If DMATC interrupts are enabled an interrupt will also be generated Address Base address 19 hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Clears the DMATCA signal in Status Register 1 and acknowledges an interrupt from a DMA channel A terminal count National Instruments Corporation 4 47 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 DMATCB Clear Register Accessing the DMATCB Clear Register clears the DMATCB signal in Status Register 1 a
181. ence a straight line excepting noise If a DAC has been perfectly calibrated then the relative accuracy specification reflects its worst case absolute error Differential nonlinearity in a DAC is a measure of deviation of code width from 1 LSB Fora DAC code width is the difference between the analog values produced by consecutive digital codes A specification of x1 LSB differential nonlinearity ensures that the code width is always greater than 0 LSBs guaranteeing monotonicity and less than 2 LSBs AT MIO 64F 5 User Manual A 6 National Instruments Corporation Appendix Digital I O Compatibility Output current source capability Output current sink capability Timing I O Number of channels Resolution Base clock available Base clock accuracy Compatibility Counter input frequency Specifications TTL compatible Can source 2 6 mA and maintain V at 2 4 V Can sink 24 mA and maintain Vo at 0 5 V 3 counter timers 1 frequency output 16 bit for 3 counter timers 4 bit for frequency output channel 5 MHz 1 MHz 100 kHz 10 kHz 1 kHz 100 Hz 0 01 TTL compatible inputs and outputs Counter gate and source inputs are pulled up with 4 7 resistors onboard 6 9 MHz maximum 145 nsec period with a minimum pulse width of 70 nsec Power Requirement from PC I O Channel Power consumption Physical Board dimensions T O connector Operating Environment Component temperature Relative hu
182. ensure that they meet all three linearity specifications defined in this appendix National Instruments Corporation A 3 AT MIO 64F 5 User Manual Specifications Appendix A Differential nonlinearity DNL is a measure of deviation of code widths from their theoretical value of 1 LSB The width of a given code is the size of the range of analog values that can be input to produce that code ideally 1 LSB A specification of 1 LSB differential nonlinearity ensures that no code has a width of 0 LSBs that is no missing codes and that no code width exceeds 2 LSBs Noise System noise is the amount of noise seen by the ADC when there is no signal present at the input of the board The amount of noise that is reported directly without any analysis by the ADC is not necessarily the amount of real noise present in the system unless the noise is considerably greater than 0 5 LSB rms Noise that is less than this magnitude produces varying amounts of flicker and the amount of flicker seen is a function of how near the real mean of the noise is to a code transition If the mean is near or at a transition between codes the ADC flickers evenly between the two codes and the noise is seen as very nearly 0 5 LSB If the mean is near the center of a code and the noise is relatively small very little or no flicker is seen and the noise is reported by the ADC as nearly 0 LSB From the relationship between the mean of the noise and the measured rms magnitu
183. ent with the Data Pointer prefetches are also performed after each write to the Data 2 124 AT MIO 64F 5 User Manual through the Data port the Data Pointer register is updated to special prefetch latch at the interface pad logic When the user _ port and after execution of the Load Data Pointer com Data port Transfers Alarm Reg 1 ELEMENT CYCLE Alarm Reg 2 Master Mode Reg Status Reg CONTROL GROUP CYCLE STATUS CYCLE 15001240 Figure 9 Data Pointer Sequencing 1 The Data Pointer register should always be reloaded before reading from the Data port if a command other than Load Data Pointer was issued to the Am9513A following the last Data port read or write The Data Pointer does not have to be ioaded again if the first Data port transaction after a command entry is a write since the Data port write will automatically cause new prefetch to occur 2 Operating modes and X allow the user to save the counter contents in the Hold register by applying an active going gate edge If the Data Pointer register had been pointing to the Hold register in question the pre fetched vaiue will not correspond to the new value saved in the Hold Register To avoid reading an incorrect value a new Load Data Pointer command should be issued before attempting to read the saved data A Data port write to another register will also initiate a prefetch subsequent reads will
184. entional design storage and handling precautions should be observed so that the protec tion networks themselves are not overstressed Within the limits of normal operation the input protection circuitry is inactive and may be modeled as lumped series RC as shown in Figure 3 a The functionally active input connection during normai operation is the gate of a MOS transistor No active sources or drains are connected to the inputs so that neither transient nor steady state currents are impressed on the driving signals other than the charging or discharging of the input capacitance and the accumulated leakage associated with the protection network and the input circuit a AF002521 Figure 3 input Circuitry The only exception to the purely capacitive input case is the X2 crystal input As shown in Figure 3 b an internal resistor connects X1 and X2 in addition to the protection network The resistor is a modestly high value of more than 100kohrns Fanout from the driving circuitry into the Am9513A inputs will generally be limited by transition time considerations rather than DC current limitations when the loading is dominated by conventional MOS circuits in an operating environment all inputs should be terminated so they do not float and therefore will not accumulate stray static charges Unused inputs shouid be tied directly to Ground or VCC as appropriate An input in use wil have some type of logic output driving it and te
185. er 3 7 AT MIO 64F 5 PGIA 3 6 block diagram 3 5 dither circuitry 3 7 input multiplexers 3 6 analog output circuitry 3 12 to 3 14 block diagram 3 13 calibration 3 14 circuitry 3 13 configuration 3 14 AT MIO 64F 5 block diagram 3 1 DAC waveform circuitry and timing 3 14 to 3 19 AT MIO 64F 5 User Manual Index 22 National Instruments Corporation Index FIFO continuous cyclic waveform generation 3 17 to 3 18 FIFO programmed cyclic waveform generation 3 18 FIFO pulsed waveform generation 3 18 to 3 19 waveform circuitry 3 15 waveform timing circuitry 3 16 to 3 17 data acquisition timing circuitry 3 8 to 3 10 block diagram 3 5 data acquisition rates 3 12 multiple channel scanned data acquisition 3 10 to 3 12 single channel data acquisition 3 8 to 3 10 single read timing 3 8 digital I O circuitry 3 19 to 3 20 functional overview 3 1 to 3 2 PC I O channel interface circuitry 3 2 to 3 4 RTSI bus interface circuitry 3 23 to 3 24 timing I O circuitry 3 20 to 3 23 time lapse measurements 2 34 timing connections 2 30 to 2 37 data acquisition timing connections 2 30 to 2 33 EXTCONV signal 2 31 EXTGATE signal 2 32 EXTSTROBE signal 2 30 to 2 31 EXTTMRTRIG signal 2 32 to 2 33 EXTTRIG signal 2 31 to 2 32 SCANCLK signal 2 30 general purpose connections 2 33 to 2 37 event counting application with external switch gating 2 34 frequency measurement 2 34 to 2 35 GATE SOURCE and OUT signals 2 33 to 2 37 i
186. erates both positive and negative numbers The binary format used is determined by the mode in which the ADC is configured The bit pattern returned for either format is given as follows Address Base address 00 hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D10 D9 bs D7 D6 D5 D3 D2 DI DO MSB LSB Bit Name Description 15 0 D lt 15 0 gt Local data bus bits When the ADC FIFO is addressed these bits are the result of a sign extended 12 bit ADC conversion Values read range from 0 to 4 095 decimal 0 0000 to OxFFF when the ADC is in unipolar mode and 2 048 to 2 047 decimal OxF800 to Ox7FF when the ADC is in bipolar mode The A D conversion result can be returned from the ADC FIFO as a two s complement or straight binary value depending on the input mode set by the ADC_BIP bit in the configuration memory location for the converted channel If the analog input circuitry is configured for the unipolar input range straight binary format is implemented Straight binary format returns numbers between 0 and 4 095 decimal when the ADC FIFO Register is read If the analog input circuitry is configured for the bipolar input ranges two s complement format is used Two s complement format returns numbers between 2 048 and 2 047 decimal when the ADC FIFO Register is read Table 4 7 shows input voltage versus A D conversion value f
187. ering E 29 hold register E 11 initializing 5 2 to 5 3 input circuitry E 7 interface considerations E 7 interface signal summary E 7 load data pointer commands E 10 load register E 11 master mode control options E 11 to E 13 master mode register bit assignments E 12 mode waveforms E 15 to E 26 ordering information E 3 to E 5 output control E 26 to E 28 output control logic E 27 pin description E 6 prefetch circuit E 10 programming 5 27 register access E 9 specifications E 33 to E 37 status register E 10 to E 11 switching test circuit E 37 switching waveforms E 38 TC terminal count E 28 TEHWH TGVWH timing diagram E 40 timing I O circuitry 3 20 to 3 23 troubleshooting E 39 analog data acquisition rates multiple channel scanning rates A 5 single channel rates A 4 analog input circuitry See also Analog Input Register Group A D converter 3 6 ADC FIFO buffer 3 7 AT MIO 64F 5 3 6 block diagram 3 5 calibration 3 7 clearing 5 10 dither circuitry 3 7 input configuration 3 6 input multiplexers 3 6 programming 5 4 to 5 10 data acquisition sequences with channel scanning 5 7 to 5 10 single channel data acquisition sequence 5 5 to 5 6 single conversions using SCONVERT or EXTCONV signal 5 4 to 5 6 theory of operation 3 6 to 3 7 analog input configuration 2 6 to 2 8 available input configurations for AT MIO 64F 5 2 6 CHAN AIS and CHAN SE bit settings 4 26 CHAN CAL bit settings 4 27 DIFF
188. errupts can be enabled either individually or in any combination In any of the interrupt modes it is a good practice to confirm the source of the interrupt through reading Status Register 1 If ADC FIFOEF ADC FIFOHF is true a conversion interrupt has occurred Reading from the ADC FIFO Register clears these interrupt conditions Writing to the DAQ Clear Register also clears these conversion interrupts If DAQCOMP is set the interrupt results from the completion of a data acquisition operation This interrupt is cleared by writing to the DAQ Clear Register If TMRREQ is set a DAC update interrupt has occurred Writing to the TMRREQ Clear Register clears this interrupt condition In the case that waveform generation is disabled in Command Register 2 the DACs are not updated and the TMRREQ signal can be used as a timer interrupt If DMATCA or DMATCB is set a DMATC INT has occurred on either DMA channel A or B Writing to the DMATCA or DMATCB Clear Register clears this interrupt condition National Instruments Corporation 5 31 AT MIO 64F 5 User Manual Chapter 6 Calibration Procedures This chapter discusses the calibration resources and procedures for the AT MIO 64F 5 analog input and analog output circuitry The calibration process involves reading offset and gain errors from the analog input and analog output sections and writing values to the appropriate calibration DACS to null out the errors There are four calibration DACs associat
189. ersion result 5 5 straight binary mode A D conversion values 4 24 two s complement mode A D conversion values 4 24 A D converter 3 6 ADC conversion timing 3 8 ADC Event Strobe Register Group 4 35 to 4 40 CONFIGMEMCLR Register 4 29 4 36 5 10 5 11 CONFIGMEMLD Register 4 29 4 37 5 10 5 11 DAQ Clear Register 4 38 5 10 5 30 5 31 DAQ Start Register 4 39 register map 4 2 Single Conversion Register 4 40 ADC FIFO buffer ADC conversion timing 3 8 analog input circuitry 3 7 ADC FIFO Register clearing interrupts 5 31 description 4 24 to 4 25 reading single conversion result 5 5 servicing the data acquisition operation 5 16 BUSY bit 4 22 ADCDSP bit 4 11 ADCFIFOEF bit 4 20 5 5 5 16 5 30 5 31 ADCFIFOHF bit 4 19 5 16 5 30 5 31 ADCFIFOREQ bit 4 18 ADCREQ bit 4 13 address decoder circuitry 3 3 address latches 3 3 address lines 3 3 ADIO lt 0 3 gt signal 2 14 3 19 C 2 2 2 2 2 National Instruments Corporation Index 1 AT MIO 64F 5 User Manual Index ADIO lt 3 0 gt bit 4 56 4 57 5 26 AI GND signal definition 2 14 C 2 D 2 differential connections 2 23 to 2 24 extended analog input subconnector signal connections 2 18 single ended connections 2 25 AI SENSE signal definition 2 14 C 2 D 2 DIFF input 2 7 extended analog input subconnector signal connections 2 18 NRSE input 2 7 RSE input 2 7 single ended connections 2 24 Am9513A Counter Timer Register Group 4 51 to
190. es 16 bit Counter Mode CM register used to control all of the individual options available with its associated general counter These options include output configuration count control count source and gating control Figure 16 shows the bit assignments for the options in detail Note that generally each counter is indepen dently configured and does not depend on information outside its Counter Logic Group The Counter Mode register should be loaded only when the counter is Disarmed Attempts to load the Counter Mode register when the counter is armed may result in erratic counter operation B 2 140 AT MIO 64F 5 User Manual lt REGSTER X L N N X L WF004773 Figure 15x Mode X Waveforms NL After power on reset or a Master Reset command the Counter Mode registers are initialized to a preset condition The vaiue entered is 0800 hex and results in the following control configuration Output low impedance to ground Count down Count binary Count once Load register selected No retriggering F1 input source selected Positive true input polarity No gating Output Control Counter mode bits CMO through CM2 specify the output control configuration Figure 17 shows a schematic represen tation of the output control logic The OUT pin may be off a high impedance state or it may be inactive with a low impedance to ground The three remaining valid combinations represent the active high active lo
191. ete this programming sequence Counter n is configured to count the DAC buffer retransmit signal from SOURCES as soon as the load arm counter command is written Programming the Waveform Cycle Interval Counter To program the cycle interval Counter for a pulsed cyclic waveform generation mode use the following programming sequence writes are 16 bit operations values given are hexadecimal 1 Write FF02 to the Am9513A Command Register to select the Counter 2 Mode Register 2 Write the mode value to the Am9513A Data Register to store the Counter 2 mode value Am9513A counter mode information can be found in Appendix E AMD Am9513A Data Sheet C225 Selects 5 MHz clock from SOURCE2 pin CB25 Selects 1 MHz clock CC25 Selects 100 kHz clock CD25 Selects 10 kHz clock CE25 Selects 1 kHz clock CF25 Selects 100 Hz clock C525 Selects signal at SOURCES input as clock counts the rising edge of the signal 6 MHz maximum 3 Write FFOA to the Am9513A Command Register to select the Counter 2 Load Register 4 Write the desired cycle interval plus one to the Am9513A Data Register to store the Counter 2 load value 5 Write FF42 to the Am9513A Command Register to load Counter 2 6 Write FFF2 to the Am9513A Command Register to decrement Counter 2 7 Write FF22 to the Am9513A Command Register to arm Counter 2 After you complete this programming sequence Counter 2 is configured to count the desired interval after
192. evision field Configuration memory depth ADC and DAC FIFO depths 119 Factory reference value MSB 118 Factory reference value LSB Area information Reserved Reserved Factory DAC Channel 1 bipolar gain Factory DAC Channel 1 bipolar offset Factory DAC Channel 0 bipolar gain Factory DAC Channel 0 bipolar offset Factory ADC gain Factory ADC unipolar offset Factory ADC postgain offset Factory ADC pregain offset Area information Reserved Reserved Factory DAC Channel 1 unipolar gain Factory DAC Channel 1 unipolar offset Factory DAC Channel 0 unipolar gain Factory DAC Channel 0 unipolar offset Factory ADC gain Factory ADC unipolar offset Factory ADC postgain offset Factory ADC pregain offset When the AT MIO 64F 5 board is powered on or the conditions under which it is operating change the calibration DACS should be loaded with values from the EEPROM or if desired the board can be recalibrated The AT MIO 64F 5 calibration process is not difficult or lengthy and requires no external equipment or wiring Calibration is performed by calling the MIO Calibrate function in NI DAQ The function calibrates the board and performs the necessaray EEPROM reads and writes and calibration DAC writes AT MIO 64F 5 User Manual 6 2 National Instruments Corporation Chapter 6 Calibration Procedures The EEPROM is a 128 bit by 8 bit storage area that contains a permanent storage area and a modifiable storage area The permanent st
193. example switch settings 2 3 factory settings 2 3 switch settings with base I O address and address space 2 5 BDIO lt 0 3 gt signal 2 15 3 19 C 2 BDIO lt 3 0 gt bit 4 56 4 57 5 26 BIPDACO bit 4 9 BIPDAC1 bit 4 9 bits A2DRV 4 8 A2RCV 4 8 A4DRV 4 8 4 8 5 26 A6 through 5 29 BUSY 4 22 ADCDSP 4 11 ADCFIFOEF 4 20 5 5 5 16 5 30 5 31 ADCFIFOHF 4 19 5 16 5 30 5 31 ADCFIFOREQ 4 18 ADCREQ 4 13 ADIO lt 3 0 gt 4 56 4 57 5 26 B6 through BO bits 5 29 BDIO lt 3 0 gt 4 56 4 57 5 26 BIPDACO 4 9 BIPDACI 4 9 BYTEPTR 4 54 C 7 0 4 53 CFGMEMEF 4 21 CHAN AIS 4 26 CHAN BIP 4 27 CAL 4 27 DSP 4 29 GHOST 4 29 CHAN LAST 4 28 5 11 CHAN SE 4 26 CHANSEL lt 5 0 gt 4 27 to 4 28 GAIN 2 0 4 28 CLKMODEB lt 1 0 gt 4 16 CNT32 16 4 6 5 13 5 14 CYCLICSTOP 3 17 to 3 18 4 18 5 18 D lt 11 0 gt 4 33 4 34 D lt 15 0 gt 4 24 4 52 DACODSP 4 17 DACOREQ 4 14 DACIDSP 4 17 AT MIO 64F 5 User Manual Index 6 National Instruments Corporation Index bits continued DACIREQ 4 14 DACCMPLINT 4 12 DACCOMP 4 21 5 23 5 26 DACFIFOEF 4 21 5 26 DACFIFOFF 4 21 5 30 DACFIFOHF 4 21 5 30 DACGATE 4 17 DACMB lt 3 0 gt 4 17 DAQCMPLINT 4 12 DAQCOMP 4 19 DAQEN 4 6 5 8 5 9 DAQPROG 4 19 DB_DIS 4 18 DIOPAEN 4 11 DIOPBEN 4 11 DITHER 4 5 DMACHA 4 12 DMACHAB lt 2 0 gt 4 9 DMACHB 4 12 DMACHBB lt 2 0 g
194. f acquiring A D data from a single channel or multiple channels Prior to any of these operations the channel gain mode and range settings must be configured This is accomplished through writing to a register in the AT MIO 64F 5 register set Single Read Timing The simplest method of acquiring data from the A D converter is to initiate a single conversion and then read the resulting value from the ADC FIFO buffer after the conversion is complete A single conversion can be generated three different ways applying an active low pulse to the EXTCONV pin of the I O connector generating a falling edge on the sample interval counter output pin Counter 3 of the Am9513A Counter Timer or strobing the appropriate register in the AT MIO 64F 5 register set Any one of these operations will generate the timing shown in Figure 3 4 The ADC_BUSY signal status can be monitored through a status register on the AT MIO 64F 5 CONVERT ADC_BUSY FIFO_LD Figure 3 4 ADC Conversion Timing When the ADC value is shifted into the ADC FIFO buffer by LD a signal is generated that indicates valid data is available to be read Single conversion timing of this type is appropriate for reading channel data on an ad hoc basis However if a sequence of conversions is needed this method is not very reliable because it relies on the software to generate the conversions in the case of the strobe register If finely timed conversions are desired that requ
195. f the port When a port is not enabled reading the Digital Input Register returns the state of the digital I O lines driven by an external device Both the digital input and output registers are TTL compatible The digital output ports when enabled are capable of sinking 24 mA of current and sourcing 2 6 mA of current on each digital I O line When the ports are not enabled the digital I O lines act as high impedance inputs The external strobe signal EXTSTROBE shown in Figure 3 16 is a general purpose strobe signal Writing to an address location on the AT MIO 64F 5 board generates an active low 500 nsec pulse on this output pin EXTSTROBE is not necessarily part of the digital I O circuitry but is shown here because it can be used to latch digital output from the AT MIO 64F 5 into an external device Timing I O Circuitry The AT MIO 64F 5 uses an Am9513A Counter Timer for data acquisition timing and for general purpose timing I O functions An onboard oscillator is used to generate the 10 MHz clock Figure 3 17 shows a block diagram of the timing I O circuitry 10 MHz Am9513A Five Channel Counter Timer 16 Am9513A 5 Q E SOURCE4 RTSI Bus CONVERT EXTTRIG Acquisition SCANCLK Timing CONFIGCLK Figure 3 17 Timing I O Circuitry Block Diagram AT MIO 64F 5 User Manual 3 20 National Instruments Corporation Chapter 3 Theory of Operation The Am9513A contains five indepe
196. ff On each TC the counter will reload from the Load register and automatically disarm itself inhibiting further counting unit a new ARM command is issued 15 2 129 AT MIO 64F 5 User Manual AMD Am9513A Data Sheet Figure 15b Mode B Waveforms MODE C Hardware Triggered Strobe CMt5 omia 3 12 CM10 LEE x x x J x x CM7 5 2 Mode C shown in Figure 15c is identical to Mode A except that counting will not begin until a Gate edge is applied to the armed counter The counter must be armed before application of the triggered Gate edge Gate edges applied to a disarmed counter are disregarded The counter will start counting on the first source edge after the triggering Gate edge and continue counting until TC At TC the counter will reload from the Load register and automatically disarm itself Counting will then remain inhibited until a new ARM command and a new Gate edge are applied in that order Note that after application of a triggered Gate edge the Gate input will be disregarded for the remainder of the count cycle This differs from Mode where the Gate can be modulated throughout the count cycie to stop and start the counter OX VALUE TC OUTPUT TC TOGGLED QUTPUT 2 2 Figure 15 Mode Waveforms 2 130 AT M
197. full control of the buffer it can start stop and restart the generation of the waveform as programmed An example of this added functionality is shown in Figure 3 13 DACFIFORT CYCLICSTOP Figure 3 13 FIFO Cyclic Waveform Generation with Disable In this example the entire buffer fits within the DAC FIFO After the waveform is initiated it cycles and recycles through the buffer The end of the buffer is indicated by the DACFIFORT signal or DAC FIFO Retransmit This is a signal generated by the hardware in cyclic mode to trigger the DAC FIFO to retransmit its buffer The CYCLICSTOP signal is programmable through a register in the AT MIO 64F 5 register set If this bit is cleared the DAC FIFO hardware runs ad infinitum or until the timer update pulse triggering is disabled If necessary National Instruments Corporation 3 17 AT MIO 64F 5 User Manual Theory of Operation Chapter 3 the waveform can be stopped by disabling the timer trigger The result of this action is to leave the DAC at some unknown value for example the last updated value The advantage of the CYCLICSTOP control signal is that DAC updating ends gracefully When this signal is set the waveform ends after it encounters the next retransmit signal Thus it will always end in a known state at the end of the buffer FIFO Programmed Cyclic Waveform Generation One step beyond the continuous waveform generation is the programmed cyclic waveform generat
198. g programming steps for posttrigger and pretrigger modes as well as internal and external timing The instructions in the blocks of the following flow chart are enumerated in the Data Acquisition Programming Functions section later in this chapter Clear the A D circuitry Program a single analog input channel gain mode and range Program the sample interval counter Program the sample counter Enable a single channel data acquisition operation Apply a trigger Service the data acquisition operation Figure 5 3 Single Channel Data Acquisition Programming AT MIO 64F 5 User Manual 5 6 National Instruments Corporation Chapter 5 Programming Programming Data Acquisition Sequences with Channel Scanning The preceding data acquisition programming sequence programs the AT MIO 64F 5 for multiple A D conversions on a single input channel The AT MIO 64F 5 can also be programmed for scanning multiple analog input channels with different gain mode and range settings during the data acquisition operation The sequence of A D channels and configuration settings called the scan sequence is programmed into the channel configuration memory There are two types of multiple A D conversions with channel scanning continuous channel scanning and interval channel scanning Continuous channel scanning cycles through the scan sequence in the channel configuration memory and repeats the scan sequence until the sample counter terminates
199. g the 64S ious tea Sa c nei pete 5 2 the AMIS 5 2 Programming the Analog Input 5 4 Single Conversions Using the SCONVERT or EXTCONV Signal 5 4 National Instruments Corporation AT MIO 64F 5 User Manual Contents Generating a Single Conversion sees enne enne nnne 5 5 Reading a Single Conversion Result eene 5 5 Programming a Single Channel Data Acquisition Sequence 5 5 Programming Data Acquisition Sequences with Channel Scanning 5 7 Continuous Channel Scanning Data Acquisition eene 5 7 Interval Channel Scanning Data Acquisition eee 5 8 Data Acquisition Programming Functions esee rennen 5 10 Clearing the Analog Input Circuitry 5 10 Programming Single Analog Input Channel Configurations 5 10 Programming Multiple Analog Input Channel Configurations 5 11 Programming the Sample Interval Counter eee 5 11 Programming the Sample 5 12 Programming the Scan Interval Counter eee 5 14
200. g the RTSI Switch The RTSI switch is a 7x7 crossbar switch that can be programmed to connect any of the signals on the A side to any of the signals on the B side and vice versa To do this a 56 bit pattern is shifted into the RTSI switch by writing one bit at a time to the RTSI Switch Shift Register and then writing to the RTSI Switch Strobe Register to load the pattern into the RTSI switch The 56 bit pattern is made up of two 28 bit patterns one for side and one for side B of the RTSI switch The low order 28 bits select the signal sources for the B side pins The high order 28 bits select the signal sources for the A side pins Each of the 28 bit patterns are made up of seven 4 bit fields one for each pin The 4 bit field selects the signal source and the output enable for the pin Figure 5 10 shows the bit map of the RTSI switch 56 bit pattern Bit Number 43 39 1 55 51 47 35 31 27 9 15 11 7 3 0 5 LS Control 31 30 29 28 Figure 5 10 RTSI Switch Control Pattern M B Bit Number In Figure 5 10 the fields labeled A6 through AO and B6 through BO are the 4 bit control fields for each RTSI switch pin of the same name The 4 bit control field for pin AO is shown in Figure 5 10 The bits labeled S2 through SO are the signal source selection bits for the pin One of seven source signals can be selected Pins A6 through AO can select any of the pins B6 through BO as sign
201. ganized as follows Chapter 1 Introduction describes the AT MIO 64F 5 lists the contents of your AT MIO 64F 5 kit the optional software and the optional equipment and explains how to unpack the AT MIO 64F 5 Chapter 2 Configuration and Installation explains the board configuration installation of the AT MIO 64F 5 into the PC signal connections to the AT MIO 64F 5 and cable considerations e Chapter 3 Theory of Operation contains a functional overview of the AT MIO 64F 5 and explains the operation of each functional unit making up the AT MIO 64F 5 e Chapter 4 Register Map and Descriptions describes in detail the address and function of each of the AT MIO 64F 5 control and status registers Chapter 5 Programming contains programming instructions for operating the circuitry on the AT MIO 64F 5 e Chapter 6 Calibration Procedures discusses the calibration resources and procedures for the AT MIO 64F 5 analog input and analog output circuitry e Appendix A Specifications lists the specifications of the AT MIO 64F 5 e Appendix B AT MIO 64F 5 I O Connector describes the pinout and signal names for the AT MIO 64F 5 100 pin I O connector e Appendix C MIO SubConnector describes the pinout and signal names for the AT MIO 64F 5 50 pin MIO subconnector e Appendix D Extended Analog Input SubConnector describes the pinout and signal names for the 50 pin extended analog input subconnector of the AT MIO 64F 5 e A
202. garding Medical and Clinical Use of National Instruments Products National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment Preface This manual describes the mechanical and electrical aspects of the AT MIO 64F 5 board and contains information concerning its operation and programming The AT MIO 64F 5 is a high performance multifunction analog digital and timing I O board for the IBM PC AT and compatible computers and EISA personal computers PCs Organization of This Manual The AT MIO 64F 5 User Manual is or
203. gh noisy environments Differential signal connections reduce picked up noise and increase common mode noise rejection Differential signal connections also cause input signals to float within the common mode limits of the PGIA National Instruments Corporation 2 21 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 Differential Connections for Ground Referenced Signal Sources Figure 2 7 shows how to connect a ground referenced signal source to an AT MIO 64F 5 board configured in the DIFF input mode The AT MIO 64F 5 analog input circuitry must be configured for DIFF input to make these types of connections Configuration instructions are included in Chapter 4 Register Map and Descriptions lt 0 7 gt lt 16 39 gt Ground Referenced Signal Source ACH 8 15 lt 40 63 gt Measured Voltage Common Mode Noise Ground Potential and so on Input Multiplexers AISENSE AI GND I O Connector AT MIO 64F 5 Board in the DIFF Input Configuration Figure 2 7 Differential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the AT MIO 64F 5 ground shown as Vom in Figure 2 7 AT MIO 64F 5 User Manual 2 22 National Instruments Corporation Chapter 2 Configuration and Installation Differential Connections for Nonreferenc
204. gister Programming the Sample Interval Counter Counter 3 of the Am9513A Counter Timer is used as the sample interval counter Counter 3 can be programmed to generate an active low pulse once every N counts N is referred to as the sample interval that is the time between successive A D conversions N can be between 2 and 65 536 One count is equal to the period of the timebase clock used by the counter The following internal clocks are available to the Am9513A 5 MHz 1 MHz 100 kHz 10 kHz 1 KHz and 100 Hz In addition the sample interval timer can use signals connected to any of the Am9513A SOURCE input pins Using the EXTCONV signal from the I O connector to control multiple A D conversions involves disabling the sample interval counter This counter should be left in the high impedance state see the Resetting a Single Am9513A Counter Timer section later in this chapter Conversions are generated by the falling edge of the EXTCONV signal Although EXTCONV may be pulsing conversions do not begin until after an active low pulse on Start or the EXTTRIG signal Conversions are automatically halted irrespective of the EXTCONV signal when the sample counter reaches zero National Instruments Corporation 5 11 AT MIO 64F 5 User Manual Programming Chapter 5 To program the sample interval counter for internal conversion signals use the following programming sequence All writes are 16 bit operations All values given are hex
205. gister in posted update mode sets the TMRREQ signal in Status Register 1 and generates an interrupt or DMA request if enabled National Instruments Corporation 4 43 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 DAC Clear Register Accessing the DAC Clear Register clears parts of the DAC circuitry including emptying the DAC FIFO Address Type Word Size Bit Map Strobe Effect Base address 1E hex Read only 8 bit Not applicable no bits used Empties the DAC FIFO clears the TMRREQ bit in Status Register 1 and its associated interrupts and clears the DACCOMP bit in Status Register 1 and its associated interrupts AT MIO 64F 5 User Manual 4 44 National Instruments Corporation Chapter 4 Register and Descriptions General Event Strobe Register Group The General Event Strobe Register Group consists of five registers that when written to cause the occurrence of certain events on the AT MIO 64F 5 board such as clearing flags and starting A D conversions Bit descriptions of the six registers making up the General Event Strobe Register Group are given on the following pages National Instruments Corporation 4 45 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 DMA Channel Clear Register Accessing the DMA Channel Clear Register clears the circuitry associated with dual channel DMA operation Two DMA channels are programmed for dual channel DMA Wh
206. gnals F1 F5 cannot be directly monitored by the user The phase difference between these signals will manifest itself by causing counters using two different F signals to count at different times on simultaneous transi tions in the F signals 1 X2 12 This timing specification assumes that CS is active when ever RD or WA are active CS may be held active indefinitely 13 This parameter assumes X2 is driven from an external gate with a square wave t 14 This parameter assumes that the write operation is to the command register 15 This timing specification applies to single action com mands only 6 g LOAD ARM SAVE etc For doubie action commands such as LOAD AND ARM DISARM AND SAVE TWHEH minimum 700 ns 16 short data write mode TWHRL and TWHWL mini mum 1000 ns 17 This parameter applies to the hardware retrigger save modes N O Q R and X CM7 1 and CM15 CM13 lt gt 000 This parameter ensures that the gating pulse initiates a hardware retrigger save operation 18 This parameter applies to hardware load source select modes S and V CM 1 and 15 CM13 000 This parameter represents the minimum hold time to ensure that the GATE input selects the correct load source on the active source edge SWITCHING TEST CIRCUIT 003853 This test circuit is the dynamic load of a Teradyne J941 Am9513A National Instruments Corporation E 37
207. h 7 should be used because these are the only 16 bit channels available If the board is used in an EISA computer all channels are capable of 16 bit transfers and can be used National Instruments Corporation 2 5 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 The AT MIO 64F 5 does not use and cannot be configured to use the 8 bit channels 0 through 3 on the PC I O channel for 16 bit transfers Analog Input Configuration The analog input section of the AT MIO 64F 5 is software configurable You can select different analog input configurations by programming the appropriate register in the AT MIO 64F 5 register set The following paragraphs describe in detail each of the analog input categories Input Mode The AT MIO 64F 5 offers three different input modes nonreferenced single ended input referenced single ended RSE input and differential DIFF input The single ended input configurations use up to 64 channels The DIFF input configuration uses up to 32 channels Input modes are programmed on a per channel basis for multimode scanning For example you can configure the circuitry to scan 48 channels 16 differentially configured channels and 32 single ended channels The three input configurations are described in Table 2 3 Table 2 3 Available Input Configurations for the AT MIO 64F 5 DIFF Differential configuration has up to 32 differential inputs with the negative input of the PGIA ti
208. hat is disarmed or stopped on TC is actually disarmed stopped immediately following TC AT MIO 64F 5 User Manual This may cause count sequences different from what a user might expect Since the counter is always reloaded at the start of TC and since it always counts at the end of TC the counter contents following TC will differ by one from the reloaded value irrespective of the operating mode used If the reloaded value was 0001 for down counting 9999 BCD for BCD up counting or FFFF hex for binary up counting the count at the end of TC will drive the counter into TC again regardless of whether the counter is gated off or disarmed As long as these values are reloaded the TC output will stay active If a TC Toggled output is selected it will toggle on each count Execution of a LOAD LOAD AND ARM or STEP command with these counter contents will act the same as application of a source pulse causing TC to remain active and amp TC Toggled output to toggie Count Controi Counter Mode bits CM3 through CM7 specify the various options available for direct control of the counting process CM3 and CM4 operate independently of the others and control up down and BCD binary counting They may be combined freely with other control bits to form many types of counting configurations The other three bits and the Gating Control field interact in complex ways Bit CM5 controis the repetition of the count process When CMS 1 counting will p
209. he DAC FIFO to be updated at a later time The DAC FIFO can buffer up to 2 048 values before updating the DAC The RTSI latch is a special case of the posted update mode because data is not directly written to the AT MIO 64F 5 board from the PC but it is received serially from the AT DSP2200 In this case only one value can be buffered before updating the DAC In the posted update mode you can use any one of the three paths to transfer data to the DACs Data can be sent through the FIFO and local latch concurrently or separately In this instance the value written to the DAC through the local latch is not updated until the update pulse trigger occurs If the RTSI latch is used to transfer serial data from the AT DSP2200 over the RTSI bus no other transferring path is allowed In other words data cannot be transmitted serially over the RTSI bus to DAC channel 0 and transferred through the FIFO to DAC channel 1 at the same time These modes are mutually exclusive National Instruments Corporation 3 15 AT MIO 64F 5 User Manual Theory of Operation Chapter 3 DAC Waveform Timing Circuitry Waveform timing implies precise updating of the analog output DACs to create a pure waveform without any jitter or uncertainty This timing is accomplished by posting updates to the DACs Posted update mode configures the DACS to buffer values written to them and update the output voltage only after a trigger signal This trigger signal can come in the form of
210. he amount of voltage generated by the DAC when it is set to produce V To correct this offset error the calibration routine should write a value of 0 to each DAC and adjust CALDAC4 and CALDAC6 until it measures the same voltage between each analog output and AO GND as it measures with both inputs grounded Gain error in the analog output circuitry is the sum of the gain errors contributed by the components in the output circuitry This error is a voltage difference between the desired voltage and the actual output voltage generated that is proportional to the DAC output voltage To correct the gain error the output calibration routine should set each analog output to 5 V and measure the difference between each output and the internal voltage reference It should then set each analog output to 0 and measure the difference between each output and AOGND Finally it should measure the difference between AOGND and AIGND these measurements need to be combined with the value of the onboard reference as recovered from the EEPROM to accurately determine the actual magnitude of a nominal 5 V step on the analog outputs CALDACS and CALDAC7 should then be adjusted so that this value is exactly 5 V This procedure is insensitive to offset gain and linearity errors in the analog input circuitry Gain adjustment may however have a small effect on offset error so for best results analog output gain should be calibrated before analog output offset The
211. he system This minimum conversion time is the sum of the conversion time of the ADC and the time required for the input sample and hold amplifier to acquire the input signal and settle to 12 bit accuracy 0 0196 The sum of conversion time and acquisition time for the sampling ADC used on the AT MIO 64F 5 is guaranteed to be less than 5 usec and is typically 4 6 psec AT MIO 64F 5 User Manual A 4 National Instruments Corporation Appendix Specifications Multiple Channel Scanning Acquisition Rates The maximum multiple channel scanning acquisition rate is identical to the single channel acquisition rate for all gains No extra settling time is necessary between channels as long as the gain is constant When scanning among channels at various gains the settling times may increase When the PGIA switches to a higher gain the signal on the previous channel may be well outside the new smaller range For instance suppose a 4 V signal is connected to Channel 0 and a 1 mV signal is connected to Channel 1 and suppose the PGIA is programmed to apply a gain of 1 to Channel 0 and a gain of 100 to Channel 1 When the multiplexer switches to Channel 1 and the PGIA switches to a gain of 100 the new full scale range is x50 mV if the ADC is in bipolar mode The approximately 4 V step from 4 V to 1 mV is 4 000 of the new full scale range To settle within 0 012 120 ppm of the 50 mV full scale range on Channel 1 the input circuitry has to settle
212. he timer update TMRREQ is set whenever the DAC FIFO is ready to receive data or a pulse has occurred TMRTRIG signal in the interrupt mode TMRREQ generates an interrupt or DMA request only if the proper mode is selected according to Table 4 3 In DMA transfer mode TMRREQ is automatically cleared when the DAC is written to In interrupt and programmed I O modes TMRREQ must be cleared by strobing the TMRREQ Clear Register 4 20 National Instruments Corporation Chapter 4 Bit Name 6 DACCOMP 5 DACFIFOFF 4 DACFIFOHF 3 DACFIFOEF 2EEPROMDATA IBEPROMCD 0 CFGMEMEF National Instruments Corporation 4 21 Register Map and Descriptions Description continued DAC Sequence Complete This bit reflects the status of the DAC sequence termination circuitry When the DAC sequence has normally completed or ended on an error condition the DACCOMP bit is set If DACCOMP is set prematurely this indicates an error condition If interrupts are enabled an interrupt will be generated on this condition The interrupt is serviced by strobing the TMRREQ Clear or DAC Clear Register While the sequence is in progress the DACCOMP bit is cleared DAC FIFO Full Flag This bit reflects the state of the DAC FIFO If DACFIFOFF is clear the DAC FIFO is full and is not ready to receive data If DACFIFOFF is set the DAC FIFO is not full and is able to continue receiving data If the appropriate DAC and I O modes are
213. hen Counter 4 and Counter 5 reach zero Programming the Scan Interval Counter Counter 2 of the Am9513A Counter Timer is used as the scan interval counter Counter 2 can be programmed to generate a pulse once every N counts N is referred to as the scan interval which is the time between successive scan sequences programmed into the mux channel gain memory N can be between 2 and 65 536 One count is equal to the period of the timebase clock used by the counter The following clocks are available internal to the Am9513A 5 MHz 1 MHz 100 kHz 10 kHz 1 kHz and 100 Hz In addition the scan interval timer can use signals connected to any of the Am9513A SOURCE input pins To program the scan interval counter use the following programming sequence All writes are 16 bit operations values given are hexadecimal 1 Write FF02 to the Am9513A Command Register to select the Counter 2 Mode Register AT MIO 64F 5 User Manual 5 14 National Instruments Corporation Chapter 5 Programming 2 Write the mode value to the Am9513A Data Register to store the Counter 2 mode value Use one of the following mode values 8225 Selects 5 MHz clock Counter 2 Source signal 8B25 Selects 1 MHz clock 8 25 Selects 100 kHz clock 8D25 Selects 10 kHz clock 8 25 Selects 1 KHz clock 8F25 Selects 100 Hz clock 8525 Selects signal at SOURCES input as clock counts the rising edge of the signal 6 MHz maximum 3 Write FFOA to the Am95
214. icant performance increase in polled I O or interrupt servicing of the DACs The waveform circuitry is configured through mode bits in Command Register 4 to perform one or two DAC writes per update pulse If two DAC channels are being used and single update mode is clear is enabled only one value is read from the DAC FIFO and written to the appropriate DAC channel per update pulse The result is that the channel updates are out of phase with respect to each other If the dual update mode is used DACMODEB3 is set the circuitry will read up to two values from the DAC FIFO and write them to the appropriate DAC channels If the dual update mode is enabled and only one DAC is used then the circuitry will perform only one FIFO read and DAC write per update pulse Notice that if two channels are used the DACO value must be written to the DAC FIFO before the DACI value Cyclic Waveform Generation The simplest mode of waveform generation is the cyclic mode in which an internal or external timing signal is used to update the DACs In this case DAC updating begins when the timing signal starts and ends when the timing signal is removed A special case of this mode occurs when the buffer fits entirely within the DAC FIFO where it is cycled through If this is true and the CYCLICSTOP bit in Command Register 4 is set DAC updating stops at the next end of buffer This provides a known final value for the DACs To update the analog o
215. in Chapter 2 Configuration and Installation and in Appendixes C and D AT MIO 64F 5 User Manual National Instruments Corporation Appendix C MIO Subconnector AI GND ACHO ACHI ACH2 ACH3 ACH4 ACHS ACH6 ACH7 AI SENSE DACI OUT AO GND ADIOO ADIOI ADIO2 ADIO3 DIG GND 45V EXTSTROBE EXTGATE SOURCEI OUTI GATE2 SOURCES OUTS rw w o fu jo 5 5 5 e ramas 2 w lo to lu te fe 5 8 5 S15 2 je 8 8 s o 51 o This appendix describes the pinout and signal names for the AT MIO 64F 5 50 pin MIO subconnector Figure C 1 shows the AT MIO 64F 5 50 pin MIO subconnector AI GND ACH8 ACH9 ACH10 ACHII ACHI2 ACHI3 14 15 DACO OUT EXTREF DIG GND BDIOO BDIOI BDIO2 BDIO3 5 SCANCLK EXTTRIG EXTCONV GATEI EXTTMRTRIG OUT2 GATES FOUT Figure C 1 50 pin MIO Subconnector Pin Assignment National Instruments Corporation C 1 AT MIO 64F 5 User Manual MIO Subconnector Appendix C MIO Subconnector Signal Connection Descriptions Pin 1 2 3 18 19 20 21 22 23 24 33 25 27 29 31 26 28 30 32 34 35 Signal Name AI GND ACH lt 0 15 gt AI SENSE DACO OUT DAC1 OUT EXTREF AO GND DIG GND ADIO lt 0 3 gt BDIO lt 0 3 gt 5 V AT MIO 64F 5 User Manual Reference N A AI GND AI GND AO GND AO GND AO GND N A N A
216. in LSBs is independent of the gain setting Postgain offset is the total of the voltage offsets contributed by the circuitry from the output of the PGIA to the ADC input including the ADC s own offsets To calibrate this offset the routine should ground the inputs of the PGIA measure the input at two different gains in bipolar mode and adjust CALDACI until the measured offset is proportional to gain setting Unipolar offset is additional postgain offset that is present only in unipolar mode It is due to inaccuracy in the circuitry that switches between bipolar and unipolar modes To calibrate this offset the routine should ground the inputs of the PGIA in bipolar mode and adjust CALDAC1 to yield a small positive measured offset typically two or three LSBs Then it should switch the board to unipolar mode and adjust CALDAC2 to yield the same offset in LSBs as that measured in bipolar mode Finally CALDACI should be restored to its previous value If the three offset DACS are adjusted in this way there is no significant residual offset error and reading a grounded channel returns on average less than 0 5 LSB regardless of gain setting the stages up to and including the input of the ADC contribute to the gain error of the analog input circuitry With the set to a gain of 1 the gain of the analog input circuitry is ideally 1 The gain error is the deviation of the gain from 1 and appears as a multiplication of the input vo
217. ing the AT MIO 64F 5 Normally however you should not need to read the low level programming details in the user manual because the NI DAQ software package for controlling the AT MIO 64F 5 is included with the board Using NI DAQ is quicker and easier than and as flexible as using the low level programming described in Chapter 5 Programming You can use the AT MIO 64F 5 with LabVIEW for Windows or LabWindows for DOS LabVIEW and LabWindows are innovative program development software packages for data acquisition and control applications LabVIEW uses graphical programming whereas LabWindows enhances Microsoft C and QuickBASIC Both packages include extensive libraries for data acquisition instrument control data analysis and graphical data presentation Part numbers for these software packages are listed in the following table National Instruments Corporation 1 3 AT MIO 64F 5 User Manual Introduction Chapter 1 LabVIEW for Windows 776670 01 LabWindows Standard package 776473 01 Advanced Analysis Library 776474 01 Standard package with the Advanced Analysis Library 776475 01 Optional Equipment Table 1 2 Optional Equipment Equipment Part Number CB 100 I O connector block 0 5 m cable 776455 01 1 0 m cable 716455 02 Type NB5 100 conductor ribbon cable 0 5 m cable 181304 05 1 0 m cable 181304 10 SCXI signal conditioning chassis SCXI 1000 4 slot chassis 776570 SCXI 1001 12 slot chassis TI6571 XX SCXI signal condit
218. ing the required ARM command for modes which count repetitively 5 1 2 128 AT MIO 64F 5 User Manual output waveform and a TC Toggled output waveform are shown for each mode The symbols L and are used to represent count values equal to the Load and Hold register contents respectively The symbois and N represent arbitrary count values For each mode the required bit pattern in the Counter Mode register is shown don t care bits are marked X These figures are designed to clarify the mode descriptions the Am9513A Electrical Specification should be used as the authoritative reference for timing relationships between signals Am9513A E 14 National Instruments Corporat on Appendix E To keep the following mode descriptions concise and to the point the phrase source edges is used to refer to active going source edges only not to inactive going edges Simi larly the phrase gate edges refers only to active going gate edges Also again to avoid verbosity and euphuism the descriptions of some modes state that a counter is stopped or disarmed a TC inhibiting further counting As is fully explained in the TC section of this document for these modes the counter is actually stopped or disarmed following the active going source edge which drives the counter out of TC in other words since a counter in the TC state always counts irrespective of its gating or arming status the stopping
219. into one of the eight selected 8 bit calibration DACs Address Base address OA hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Updates a selected calibration DAC AT MIO 64F 5 User Manual 4 50 National Instruments Corporation Chapter 4 Register Map and Descriptions Am9513A Counter Timer Register Group The three registers making up the Am9513A Counter Timer Register Group access the onboard counter timer The Am9513A controls onboard data acquisition timing as well as general purpose timing for the user The Am9513A registers described here are the Am9513A Data Register the Am9513A Command Register and the Am9513A Status Register The Am9513A contains 18 additional internal registers These internal registers are accessed through the Am9513A Data Register A detailed register description of all Am9513A registers is included in Appendix E AMD Am9513A Data Sheet Bit descriptions for the Am9513A Counter Timer Register Group registers are given in the following pages National Instruments Corporation 4 51 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 Am9513A Data Register With the Am9513A Data Register any of the 18 internal registers of the Am9513A can be written to or read from The Am9513A Command Register must be written to in order to select the register to be accessed by the Am9513A Data Register The internal registers accessed by the Am9513A
220. into the Master Mode register See the Data Pointer Register section of this document for additional information on Data Pointer sequencing Enable 16 Bit Data Bus Coding C6 C5 C4 C2 CO Description This command sets Master Mode bit 13 without affecting other bits in the Master Mode register MM13 controis the muitiplexer the data bus buffer When MM13 is Set no multiplexing takes place and all 16 external data bus lines are used to transfer information into and out of the STC 13 may aliso be controlled by loading the full Master Mode register in parallel Enabie 8 Bit Data Bus Coding 6 C5 C2 C1 Description This command clears Master Mode bit 13 without affecting other bits in the Master Mode register MM13 controls the multiplexer in the data bus buffer When 13 is cleared the multiplexer is enabled and 16 bit internal informa tion is transferred eight bits at a time to the eight low order external data bus lines MM13 may also be controlled by loading the full Master Mode register in parallel Gate Off FOUT Coding 8 8 8 g 8 8 C1 1 m 8 1 E Description This command sets Master Mode bit 12 without affecting other bits in the Master Mode register MM12 controis the output state of the FOUT signal When gated off the FOUT line will exhibit a low impedance to ground MM12 may be controlled by loading the full Master Mode register in p
221. ion This mode is also available only when the entire buffer fits within the DAC FIFO Figure 3 14 shows the operation of this mode DACFIFORT 5 _ AX 3 X 2 X 1 AK 0 5 COUNTER 1 2 or 5 Figure 3 14 FIFO Programmed Cyclic Waveform Timing In this case one of the counters in the Am9513A Counter Timer is programmed to count the number of DAC FIFO Retransmit signals When the counter counts the appropriate number of occurrences it terminates the waveform sequence A bit is available in Status Register 1 to indicate termination of a waveform sequence FIFO Pulsed Waveform Generation Another step beyond cycle counting is pulsed waveform generation Again this mode is applicable only if the entire buffer fits within the DAC FIFO Figure 3 15 shows the operation of this mode and the resulting waveform DACFIFORT CIRI 2 2 CTR 1 Output Lo I I CTR 2 Terminal Count Figure 3 15 FIFO Pulsed Waveform Generation Timing AT MIO 64F 5 User Manual 3 16 National Instruments Corporation Chapter 3 Theory of Operation In the pulsed waveform application Counter 1 of the Am9513A is programmed to count the number of retransmit signals before terminating the sequence At this point Counter 2 serves as an interval timer waiting a programmed amount of time and then restarting the sequence This process proceeds ad infinitum until the timer trigger is removed or disabled or the CYCLICSTOP bit is se
222. ion analog input A 3 analog output A 6 resetting hardware after data acquisition operation 5 16 to 5 17 RETRIG DIS bit 4 6 RSE See referenced single ended RSE input RSI bit 4 59 RTSI bus interface circuitry 3 23 to 3 24 RTSI bus trigger line programming 5 27 to 5 28 RTSI clock configuration CLKMODEB lt 1 0 gt bit for selecting 4 16 timebase selection 2 10 RTSI latch 3 15 RTSI switch control pattern 5 29 definition 3 24 programming 5 28 to 5 31 selecting internal update counter 5 23 signal connections 5 27 to 5 28 RTSI Switch Register Group 4 58 to 4 60 register map 4 2 RTSI Switch Shift Register 4 59 RTSI Switch Strobe Register 4 60 RTSICLK signal 3 23 RTSITRIG bit 4 7 30 5 30 5 31 5 30 5 31 S 52 through SO bits 5 29 sample counters programming 5 12 to 5 14 sample counts 2 through 65 536 5 13 sample counts greater than 65 536 5 13 to 5 14 sample interval counter programming 5 11 to 5 12 sample interval timer 3 8 to 3 9 scan interval 5 7 scan interval counter programming 5 14 to 5 15 scan sequence 5 7 SCANCLK signal definition 2 15 C 2 AT MIO 64F 5 User Manual Index 20 National Instruments Corporation Index multiple channel data acquisition 3 11 timing applications 3 22 timing connections 2 30 SCANDIV bit 4 5 5 11 SCANEN bit 4 6 5 8 5 9 SCLK bit 4 5 SCN2 bit 4 6 5 10 SDATA bit 4 5 signal connections 2 11 to 2 37 analog output signal connections 2 27 to
223. ion operation through hardware apply an active low pulse to the EXTTRIG pin on the AT MIO 64F 5 I O connector See the Data Acquisition and Analog Output Timing Connections section in Chapter 2 Configuration and Installation for EXTTRIG signal specifications National Instruments Corporation 5 15 AT MIO 64F 5 User Manual Programming Chapter 5 Once the trigger is applied Counter 3 generates pulses initiating A D conversions once every sample interval until the sample counter reaches zero In the pretrigger mode these conversions are not counted by the sample counter Counting begins only after the application of a second hardware or software trigger condition and continues until the sample counter reaches zero A D conversion data stored before receipt of the EXTTRIG or DAQ Start signal are pretrigger samples Servicing the Data Acquisition Operation Once the data acquisition operation is initiated with the application of a trigger the operation must be serviced by reading the ADC FIFO The ADC FIFO can be serviced in two different ways One method is to monitor the ADCFIFOEF to read the A D conversion result every time one becomes available Another method is to monitor the ADCFIFOHF flag and read in values only when the ADC FIFO is at least half full If the FIFO is half full a block of 256 values can be consecutively read in The advantage of this second method is that Status Register 1 needs to be read only once for every 256 val
224. ional Instruments Corporation Chapter 2 Configuration and Installation Table 2 5 Recommended Input Configurations for Ground Referenced and Floating Signal Sources Type of Signal Recommended Input Configuration Ground referenced nonisolated outputs plug in instruments NRSE Floating batteries thermocouples isolated outputs DIFF with bias resistors RSE Differential Connection Considerations DIFF Input Configuration Differential connections are those in which each AT MIO 64F 5 analog input signal has its own reference signal or signal return path These connections are available when the AT MIO 64F 5 is configured in the DIFF input mode Each input signal is tied to the positive input of the PGIA and its reference signal or return is tied to the negative input of the PGIA When the AT MIO 64F 5 is configured for differential input each signal uses two multiplexer inputs one for the signal and one for its reference signal Therefore with a differential configuration up to 32 analog input channels are available Differential input connections should be used when any of the following conditions are present e You are connecting 32 or fewer signals to the AT MIO 64F 5 Input signals low level less than 1 V e Leads connecting the signals to the AT MIO 64F 5 are greater than 10 ft e Any of the input signals require a separate ground reference point or return signal signal leads travel throu
225. ioning modules SCXI 1100 32 channel differential multiplexer amplifier 716572 00 SCXI 1120 8 channel isolated analog input 716572 20 SCXI 1121 4 channel isolated transducer amplifier with excitation 776572 21 SCXI 1140 8 channel simultaneously sampling differential amplifier 716572 40 SCXI 1180 feedthrough panel 716572 80 SCXI 1181 breadboard 716572 81 AMUX 64T analog multiplexer board without cable 776366 90 with 0 2 m ribbon cable 776366 02 with 0 5 m ribbon cable 776366 05 with 1 0 m ribbon cable 776366 10 with 2 0 m ribbon cable 776366 20 AT Series RTSI bus cables for 2 boards 776249 02 3 boards 776249 03 4 boards 776249 04 5 776249 05 continues AT MIO 64F 5 User Manual 1 4 National Instruments Corporation Chapter 1 Introduction Table 1 2 Optional Equipment Continued Equipment Part Number Cable adapter board for signal conditioning 776336 10 SC 2050 without cable SC 2060 optically isolated digital input board with conductor cable 776336 01 776336 11 SC 2061 optically isolated digital output board with 26 conductor cable 776336 02 776336 12 5 2062 electromechanical relay digital control board with 26 conductor cable 776358 90 776358 92 General purpose termination breadboard 776358 192 SC 2070 without cable 776579 90 SC 2072 without cable SC 2072D without cable BNC 2080 BNC adapter board without cable 776290 18 Digital signal conditioning modules SSR Series mounting rack and 1 0 m cable 8
226. ire triggering and gating then it is necessary to program the board to automatically generate timed signals that initiate and gate conversions This is known as a data acquisition sequence A data acquisition operation refers to the process of taking a sequence of A D conversions with the sample interval the time between successive A D conversions carefully timed The data acquisition timing circuitry consists of various clocks and timing signals Three types of data acquisition are available with the AT MIO 64F 5 board single channel data acquisition multiple channel data acquisition with continuous scanning and multiple channel data acquisition with interval scanning All data acquisition operations work with pretrigger and posttrigger modes with either internal or external timing signals Pretriggering acquires data before a software or hardware trigger is applied Posttriggering acquires data only after a software or hardware trigger is received Single Channel Data Acquisition Timing The sample interval timer is a 16 bit down counter that can be used with the six internal timebases of the Am9513A to generate sample intervals from 0 4 usec to 6 sec see the Timing I O Circuitry section later in this chapter Conversion intervals of less than 5 psec will result in an overrun condition Counter 3 of the Am9513A Counter Timer is used to generate conversion AT MIO 64F 5 User Manual 3 6 National Instruments Corporation Chapter 3 Theory of O
227. is bit controls DMA requesting and interrupt generation from D A updates If this bit is set an interrupt or DMA request is generated when the DAC is ready to receive data If this bit is cleared no DMA request or interrupt is generated To select a specific mode refer to Table 4 3 for available modes and associated bit patterns 3 DRVAIS Drive Analog Input Sense This signal controls the AI SENSE signal at the I O connector AI SENSE is always used as an input in the NRSE input configuration mode irrespective of DRVAIS If DRVAIS is set then AI SENSE is connected to board ground unless the board is configured in the NRSE mode in which case AI SENSE is used as an input If DRVAIS is cleared AI SENSE is used as an input in the NRSE input configuration and is not driven otherwise AT MIO 64F 5 User Manual 4 14 National Instruments Corporation Chapter 4 Register Map and Descriptions Bit Name Description continued 2 0 INTCHB lt 2 0 gt Interrupt Channel Select These bits select the interrupt channel available for use by the AT MIO 64F 5 See Table 4 4 Table 4 4 Interrupt Level Selection Bit Pattern Effect Interrupt Level Enabled ea T Eg 5444444 National Instruments Corporation 4 15 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 Command Register 4 Command Register 4 contains 16 bits that control the AT MIO 64F 5 board clock selecti
228. l to be extracted from common mode voltage or noise before being sampled and converted The PGIA also applies gain to the input signal amplifying an input analog signal before sampling and conversion to increase measurement resolution and accuracy Software selectable gains of 0 5 1 2 5 10 20 50 and 100 are available through the AT MIO 64F 5 PGIA on a per channel basis AT MIO 64F 5 User Manual 3 6 National Instruments Corporation Chapter 3 Theory of Operation Dither Circuitry When you enable the dither circuitry you add approximately 0 5 LSB rms of white Gaussian noise to the signal to be converted by the ADC This addition is useful for applications involving averaging to increase the resolution of the AT MIO 64F 5 to more than 12 bits as in calibration or spectral analysis In such applications noise modulation is decreased and differential linearity is improved by the addition of the dither For high speed 12 bit applications not involving averaging or spectral analysis you may want to disable the dither to reduce noise Enabling and disabling of the dither circuitry is accomplished through software see Chapter 4 Register Map and Descriptions When taking DC measurements such as when calibrating the board enable dither and average about 1 000 points to take a single reading This process removes the effects of 12 bit quantization and reduces measurement noise resulting in improved resolution Dither or additive white noi
229. le Figure 16 shows the bit assignments for the Counter Mode registers Alarm Registers and Comparators Added functions are available in the Counter Logic Groups for Counters 1 and 2 see Figure 4 Each contains a 16 bit Alarm register and a 16 bit Comparator When the vaiue in the Counter reaches the value in the Alarm register the Compara tor output will go true The Master Mode register contains bits to individually enable disable the comparators When enabled the comparator output appears on the OUT pin of the associated counter in place of the normal counter output The output will remain true as long as the comparison is true that is until the next input causes the count to change The polarity of the Comparator output will be active high if the Output Control field of the Counter Mode register is 001 or 010 and active low if the Output Control field is 101 MASTER MODE CONTROL OPTIONS The 16 bit Master Mode MM register is used to control those internal activities that are not controlled by the individual Counter Mode registers This includes frequency control Time of Day operation comparator controls data bus width and data pointer sequencing Figure 11 shows the bit assign ments for the Master Mode register This section describes the use of each controi field Master Mode register bits MM12 MM13 and MM14 can be individually set and reset using commands issued to the Command register In addition they can
230. left over results from previous conversions Programming Single Analog Input Channel Configurations The analog input channel gain mode and range for single conversion and single channel acquisition are selected by writing a single configuration value to the CONFIGMEM Register This register offers a window into the channel configuration memory The CONFIGMEMLD Register must then be strobed to load this channel configuration information See the CONFIGMEM Register bit description in Chapter 4 Register Map and Descriptions for analog input channel and configuration bit patterns Set up the bits as given in the CONFIGMEM Register bit description and write to the CONFIGMEM Register Remember that the channel configuration memory must be first initialized with an access to the CONFIGMEMCLR Register After the channel configuration memory is configured it needs to be written to only when the analog input channel or configuration settings need to be changed AT MIO 64F 5 User Manual 5 10 National Instruments Corporation Chapter 5 Programming Programming Multiple Analog Input Channel Configurations During a scanning data acquisition operation a selected number of locations in the channel configuration memory are sequenced through by the acquisition circuitry A new channel configuration value is selected after each A D conversion The first conversion is performed on the first channel setting in the memory The second conversion is performed
231. lines These lines are capable of inducing currents in or voltages on the AT MIO 64F 5 signal lines if they run in parallel paths at a close distance Reduce the magnetic coupling between lines by separating them by a reasonable distance if they run in parallel or by running the lines at right angles to each other National Instruments Corporation 2 37 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 Donot run AT MIO 64F 5 signal lines through conduits that also contain power lines e Protect AT MIO 64F 5 signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running the AT MIO 64F 5 signal lines through special metal conduits Cabling Considerations National Instruments has a cable termination accessory the CB 100 for use with the AT MIO 64F 5 board This kit includes two terminated 50 conductor flat ribbon cables and two CB 50 connector blocks Signal I O leads can be attached to screw terminals on the connector block and thereby connected to the AT MIO 64F 5 I O connector The CB 100 is useful for prototyping an application or in situations where AT MIO 64F 5 interconnections are frequently changed When you develop a final field wiring scheme however you may want to develop your own cable This section contains information and guidelines for designing custom cables In making your own cabling you may decide to shield your cables The following guidelines
232. ls the update circuitry for the DACs in the delayed update mode If DACGATE is set updating of the DACs is inhibited Values can be directly written to the DAC but not through the DAC FIFO If DACGATE is cleared updating of and writing to the DACS proceeds normally lt a National Instruments Corporation 4 17 AT MIO 64F 5 User Manual Register and Descriptions Bit Name 6 DB DIS 5 CYCLICSTOP 4 ADCFIFOREQ 3 SRC3SEL 2 GATE2SEL 1 FIFO DAC 0 EXTTRIG DIS AT MIO 64F 5 User Manual Chapter 4 Description continued Double Buffering Disable This bit controls the updating of the DACs If DB DIS is set writes to the DACs in immediate and delayed update mode are neither double buffered nor deglitched If DB DIS is cleared the DACSs are double buffered and deglitched Cyclic Stop Enable This bit controls when a DAC sequence terminates If this bit is set when operating the DACs through the FIFO in a cyclic mode the DAC circuitry will halt when the next end of buffer is encountered If this bit is clear when the DACS are in a cyclic mode the DAC circuitry will restart transmission of the buffer after reaching the final point in the buffer This bit is functional only when the DAC circuitry is in cyclic mode and data is stored exclusively in the DAC FIFO ADC FIFO Request This bit controls the ADC FIFO Interrupt and DMA Request mode When ADCFIFOREQ is set ADC interrupt DMA reques
233. ltage being measured To eliminate this error source the routine should measure the input first with the inputs grounded and then with the inputs connected to the internal voltage reference It should then adjust CALDAC3 until the difference between the measured voltages is equal to the value of the reference as stored in the onboard EEPROM Once the board is calibrated at a gain of 1 there is only a small residual gain error 0 02 maximum at the other gains The gain adjustment may have a small effect on postgain offset and unipolar offset so for best results gain should be calibrated before postgain offset and unipolar offset Analog Output Calibration To null out error sources that affect the accuracy of the output voltages generated the output calibration routine should calibrate the analog output circuitry by adjusting the following potential sources of error Analog output offset error Analog output gain error Both of these error sources may be calibrated without making any connections to the AT MIO 64F 5 However the errors will differ between unipolar and bipolar modes so separate calibrations will be necessary for each mode National Instruments Corporation 6 7 AT MIO 64F 5 User Manual Calibration Procedures Chapter 6 Offset error in the analog output circuitry is the total of the voltage offsets contributed by the components in the output circuitry This error which is independent of the DAC output voltage is t
234. ly the Group field is sequenced This is the Hold cycle It allows the Hold registers to be sequentially accessed while bypassing the Mode and Load registers The third type of sequencing is the Control cycle If G4 G2 G1 111 and E2 E1 11 the Element Pointer will be incremented through the values 00 01 and 10 with no change to the Group Pointer When G4 G2 G1 111 and E2 E1 11 no incrementing takes place and only the Status register will be available through the Data port Note that the Status register can also always be read directly through the Control port For these auto sequencing modes if an 8 bit data bus is used the Byte pointer will toggle after every data transfer to allow the least and most significant bytes to be transferred before the Element or Group fields are incremented Prefetch Circuit To minimize the read access time to intemal Am9513A registers a prefetch circuit is used tor all read operations through the Data port Following each read or write operation point to the next register to be accessed Immediately following this update the new register data is transferred to a performs a subsequent read of the Data port the data bus drivers are enabled outputting the prefetched data on the bus Since the internal data register is accessed prior to the start of the read operation its access time is transparent to the user To keep the prefetched data consist
235. m in the posted update mode EXTTMRTRIG will also generate a timed interrupt if enabled AT MIO 64F 5 User Manual MIO Subconnector Pin 45 46 47 48 49 50 Signal Name GATE2 OUT2 SOURCES GATES OUTS FOUT AT MIO 64F 5 User Manual Reference DIG GND DIG GND DIG GND DIG GND DIG GND DIG GND C 4 Appendix C Description continued GATE2 This pin is from the Am9513A Counter 2 signal OUTPUT This pin is from the Am9513A Counter 2 signal SOURCES This pin is from the Am9513A Counter 5 signal GATES This pin is from the Am9513A Counter 5 signal OUTS This pin is from the Am9513A Counter 5 signal Frequency Output This pin is from the Am9513A FOUT signal National Instruments Corporation Appendix D Extended Analog Input Subconnector This appendix describes the pinout and signal names for the 50 pin extended analog input subconnector of the AT MIO 64F 5 Figure D 1 shows the 50 pin extended analog input subconnector Figure D 1 Extended Analog Input Subconnector Pin Assignment National Instruments Corporation AT MIO 64F 5 User Manual Extended Analog Input Subconnector Appendix D Extended Analog Input Subconnector Signal Descriptions Pin Signal Name Reference Description 1 24 lt 16 27 gt AI GND Analog Input Channels 16 through 27 and ACH lt 40 51 gt AI GND 40 through 51 In the differential mode the input is
236. m one counter to the SOURCE signal of another counter The counters can then be treated as one 32 bit or 48 bit counter for most counting applications The signals for Counters 1 2 and 5 and the FOUT output signal are directly tied from the Am9513A input and output pins to the I O connector In addition the GATE SOURCE and OUT pins are pulled up to 5 V through a 4 7 resistor The input and output ratings and timing specifications for the Am9513A signals are given as follows Absolute maximum voltage input rating 0 5 V to 7 0 V with respect to DIG GND Am9513A digital input specifications referenced to DIG GND input logic high voltage 2 2 V minimum input logic low voltage 0 8 V maximum Input load current 10 maximum Am9513A digital output specifications referenced to DIG GND V on Output logic high voltage 2 4 V minimum Vo output logic low voltage 0 4 V maximum output source current at Voy 200 maximum Io output sink current at Vo 3 2 mA maximum National Instruments Corporation 2 35 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 Output current high impedance state 25 maximum Figure 2 19 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of the Am95134A V SOURCE VIL 145 nsec minimum tsc tsp 70 nsec minimum t 100 nsec minimum t gh 10 nsec minimum t gw 145
237. midity Storage Environment Temperature Relative humidity National Instruments Corporation 2 0 A typical at 5 VDC 13 3 by 4 5 in 100 pin male ribbon cable connector separable into two 50 pin female ribbon cable connectors 0 to 50 C 5 to 90 noncondensing 55 to 150 C 5 to 90 noncondensing A 7 AT MIO 64F 5 User Manual Appendix AT MIO 64F 5 I O Connector This appendix shows the pinout and signal names for the AT MIO 64F 5 100 pin I O connector National Instruments Corporation 1 AT MIO 64F 5 User Manual AT MIO 64F 5 I O Connector AI GND AI GND ACHO 8 ACHI ACH9 ACH2 ACH10 ACH3 4 ACH12 5 ACH6 ACH14 ACH7 15 AI SENSE DACO OUT DACI OUT EXTREF AO GND DIG GND ADIOO BDIOO ADIOI BDIOI ADIO2 BDIO2 ADIO3 BDIO3 DIG GND 5 5 SCANCLK EXTSTROBE EXTTRIG EXTGATE EXTCONV SOURCEI GATEI OUTI EXTTMRTRIG GATE2 OUT2 SOURCE5 GATES OUTS FOUT Figure B 1 AT MIO 64F 5 I O Connector Pin Assignment ACHI6 ACH40 ACH17 ACH41 ACH 18 ACH42 ACH19 ACH43 ACH20 ACH44 ACH21 ACH45 ACH22 ACH46 ACH23 ACH47 ACH24 ACH48 ACH25 ACH49 ACH26 ACH50 ACH27 ACHSI AISENSE AIGND ACH28 ACH52 ACH29 ACH53 ACH30 54 ACH3I 55 ACH32 ACH56 ACH33 ACH57 ACH34 58 ACH35 ACH59 ACH36 ACH60 ACH37 ACH6I ACH38 ACH62 ACH39 ACH63 Appendix B Detailed signal specifications are included
238. n Chapter 5 Programming This chapter contains programming instructions for operating the circuitry on the AT MIO 64F 5 Programming the AT MIO 64F 5 involves writing to and reading from the various registers on the board The programming instructions list the sequence of steps to take The instructions are language independent that is they instruct you to write a value to a given register to set or clear a bit in a given register or to detect whether a given bit is set or cleared without presenting the actual code Note If you plan to use a programming software package such as NI DAQ or LabWindows with your AT MIO 64F 5 board you need not read this chapter Register Programming Considerations Several write only registers on the AT MIO 64F 5 contain bits that control a number of independent pieces of the onboard circuitry In the instructions for setting or clearing bits specific register bits should be set or cleared without changing the current state of the remaining bits in the register However writing to these registers simultaneously affects all register bits You cannot read these registers to determine which bits have been set or cleared in the past therefore you should maintain a software copy of the write only registers This software copy can then be read to determine the status of the write only registers To change the state of a single bit without disturbing the remaining bits set or clear the bit in the software copy and
239. n Set Toe tr PT Ta re Nt Gem out COW for counter N lt lt OUOU Sep comer NOU eed 3 counter N 001 lt N 101 LG a Pt L9 LS Se Disable Data Pointer Sequencing ________________ LO 1 0 Se Gate off j Se Enter 16 bit bus mode Not to be used for asynchronous operations Unused except when XXX 111 001 or 000 Figure 20 Am9513A Unused Command Codes Arm Counters Coding C5 C3 C2 CO Description Any combination of counters as specified by the S field will be enabled for counting A counter must be armed before counting can commerce Once armed the counting process may be further enabled or disabled using the hard ware gating facilities This command can oniy arm do nothing for a given counter a zero in the S field does not disarm the counter ARM and DISARM commands can be used to gate counter operation on and off under software control DISARM com mands entered while a counter is in the TC state will not take effect until the counter leaves TC This ensures that the counter never latches up in a TC state The counter may leave the TC state because of application of a count source edge execution of a LOAD or LOAD AND ARM command
240. n and pulsed cyclic waveform generation To update the analog output DACs in programmed cycle waveform generation mode complete the sequence of programming steps in Figure 5 8 The instructions in the blocks of the following flow chart are enumerated in the Waveform Generation Programming Functions section later in this chapter Clear the analog output circuitry including the DAC FIFO Yes Set the AA4RCV bit in Clear the A4RCV bit in Command Register 2 Command Register 2 Select the update counter via RTSI programming Program the update interval counter Program the cycle counter Set the waveform generation mode Enable updating Service update requests Figure 5 8 Programmed Cycle Waveform Programming AT MIO 64F 5 User Manual 5 20 National Instruments Corporation Chapter 5 Programming One disadvantage of the programmed cycle waveform generation is that it uses yet another counter to perform the cycle counting For this mode the SRC3SEL bit in Command Register 4 must be set so that the programmed counter can count the buffer retransmit signals from the source line of Counter 3 Counter 1 2 or 5 can be used to count buffer cycles in this mode If Counter 5 is being used for the update signal then only Counters 1 and 2 are available for cycle counting Once the cycle counter reaches the end of its count DAC updating is halted irrespective of the update signal Pulsed Cyclic Waveform Generation An extension of
241. n interval scanning a scan list can consist of any number of scan sequences Whenever a configuration memory location is selected the information bits contained in that memory location are applied to the analog input circuitry For scanning operations a counter steps through successive locations in the configuration memory at a rate determined by the scan clock With the configuration memory therefore an arbitrary sequence of channels with separate gain mode and range settings for each channel can be clocked through during a scanning operation AT MIO 64F 5 User Manual 3 10 National Instruments Corporation Chapter 3 Theory of Operation A SCANCLK signal is generated from the sample interval counter This signal pulses once at the beginning of each A D conversion and is supplied at the I O connector During multiple channel scanning the configuration memory location pointer is incremented repeatedly thereby sequencing through the memory and automatically selecting new channel settings during data acquisition The signal used to increment the configuration memory location pointer is generated from the SCANCLK signal Incrementing can be identical to SCANCLK sequencing the configuration memory location pointer once after every A D conversion or it can also be generated by dividing SCANCLK by Counter 1 of the Am9513A Counter Timer With this method the location pointer can be incremented once every N A D conversions so that N conversions can
242. n the FIFO is not full or when the FIFO is less than half full One of these two signals generates the TMRREQ signal In the example above requesting is generated when the FIFO is not full Because each update removes a value from the DAC FIFO each update also results in the TMRREQ signal being asserted This sequence of events continues until the output buffer data is exhausted There are effectively two different modes in which to operate the DAC FIFOs in posted update mode Data flows in and out at equal rates or data is initialized in the FIFO and once updating begins the data is cycled through when the end of the FIFO buffer is encountered If waveform cycles involving more than 2 048 values are required data must continuously flow into and out of the FIFO buffer to be replenished If waveform cycles of less than 2 048 points are required the data can be transferred to the DAC FIFO only once where it can be cycled through to generate a continuous waveform This mode removes the burden on the PC to continuously transfer new data to the DAC FIFO buffer allowing it to perform other operations In both cases waveforms like the one shown in Figure 3 12 can be realized AT MIO 64F 5 User Manual 3 16 National Instruments Corporation Chapter 3 Theory of Operation Figure 3 12 Analog Output Waveform Circuitry Whether the waveform size is greater than or less than 2 048 points a waveform can be generated that is seamless that is there
243. nal Instruments Corporation Acronyms Preface The following acronyms are used in this manual AC A D ADC AWG BCD CPU D A DAC DC DIFF DIO MSB NRSE PGIA RSE RTSI SCXI SDK TTL VDC alternating current analog to digital analog to digital converter American Wire Gauge binary coded decimal central processing unit digital to analog digital to analog converter direct current differential digital input output dual inline package direct memory access differential nonlinearity electrically erased programmable read only memory Extended Industry Standard Architecture first in first out high speed CMOS TTL compatible integral nonlinearity input output light emitting diode least significant bit most significant bit nonreferenced single ended programmable gain instrumentation amplifier referenced single ended Real Time System Integration Signal Conditioning eXtension Interface Software Developers kit transistor transistor logic volts direct current Related Documentation The following document contains information that you may find helpful as you read this manual IBM Personal Computer AT Technical Reference manual You may also want to consult the following Advanced Micro Devices manual if you plan to program the Am9513A Counter Timer used on the AT MIO 64F 5 e Am9513A Am9513 System Timing Controller technical manual For more information on the effects of dither see the following ar
244. nal Instruments Products for the PC DMA Channel Interrupt Level Base I O Address AT A2150 None None 120 hex AT AO 6 10 Channel 5 Lines 11 12 1 hex AT DIO 32F Channels 5 6 Lines 11 12 240 hex AT DSP2200 None None 120 hex AT GPIB Channel 5 Line 11 2 hex AT MIO 16 Channels 6 7 Line 10 220 hex AT MIO 16D Channels 6 7 Lines 5 10 220 hex AT MIO 16F 5 Channels 6 7 Line 10 220 hex AT MIO 16X None None 220 hex AT MIO 64F 5 None None 220 hex GPIB PCII Channel 1 Line 7 2B8 hex GPIB PCIIA Channel 1 Line 7 02E1 hex GPIB PCIII Channel 1 Line 7 280 hex Lab PC Channel 3 Line 5 260 hex PC DIO 24 None Line 5 210 hex PC DIO 96 None Line 5 180 hex PC LPM 16 None Line 5 260 hex PC TIO 10 None Line 5 1A0 hex These settings are software configurable and are disabled at startup time AT MIO 64F 5 User Manual 2 4 National Instruments Corporation Chapter 2 Configuration and Installation Table 2 2 Switch Settings with Corresponding Base I O Address and Base I O Address Space Switch Setting Base I O Address Base I O Address Space A9 A8 7 5 Used hex 000 E00 Reserved 100 100 11F 120 120 13F 140 140 15F 160 160 17F 180 180 19F 1A0 1A0 IBF 1C0 1C0 1DF 1 0 200 200 21F 220 220 23F 240 240 25F 260 260 27F 280 280 29F 2A0 2A0 2BF 2 0 2 0 2DF 2E0 2E0 2FF 300 300 31F 320 320 33F 340 340 35F 360 360 37F 380 380 39F 3A0 3A0 3BF
245. nd acknowledges the interrupt generated from the Channel B terminal counter interrupt When the selected DMA channel B terminal count is reached the DMATCB signal in Status Register 1 is asserted If DMATC interrupts are enabled an interrupt will also be generated Address Base address 09 hex Type Read only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Clears the DMATCB signal in Status Register 1 and acknowledges an interrupt from a DMA channel B terminal count AT MIO 64F 5 User Manual 4 48 National Instruments Corporation Chapter 4 Register and Descriptions External Strobe Register Accessing the External Strobe Register location generates an active low signal at the EXTSTROBE output of the primary MIO connector This signal has a minimum low time of 500 nsec The EXTSTROBE pulse is useful for several applications including generating external general purpose triggers and latching data into external devices for example from the digital output port Address Base address 1E hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Generates an active low pulse at the I O connector of at least 500 nsec duration National Instruments Corporation 4 49 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 Calibration DAC 0 Load Register Accessing the Calibration DAC 0 Load Register loads the serial data previously shifted
246. nd is issued during the LOAD generated TC or during any other TC for that matter the second LOAD command will terminate the TC and cause a reload from the source designated for use with the next TC The second LOAD will not alter the reload source for the next TC since the second LOAD does not generate a TC reload Sources alternate on TCs only not on LOAD commands Load and Arm Counters Coding C C6 CS C2 CO 0 1 1 55 54 53 52 St Description Any combination of counters as specified in the S field will be first loaded and then armed This command is equivalent to issuing a LOAD command and then an ARM command A LOAD AND ARM command which drives a counter to TC generates the same sequence of operations as execution of a LOAD command and then an ARM command modes which disarm on TC Modes A C and and Modes G 1 and 5 if the current is the second in the cycle the ARM part of the LOAD AND ARM command will re enable counting for another cycle In modes which alternate reload sources Modes G L the ARMing operation will cause the next TC to reload from the HOLD register irrespective of which reload Source the current TC used This command should not be used during asynchronous operations Disarm Counters Coding C C6 65 C2 Ci CO 11 0 55 54 S3 52 1 Description Any combination of counters as specified by the S field will be disabled from counting A disarmed
247. ndent 16 bit counter timers a 4 bit frequency output channel and five internally generated timebases The five counter timers can be programmed to operate in several useful timing modes The programming and operation of the Am9513A are presented in detail in Appendix E AMD Am9513A Data Sheet The Am9513A clock input is one tenth the BRDCLK frequency selected by the W1 and W2 jumpers The factory default for BRDCLK is 10 MHz which generates a 1 MHz clock input to the Am9513A The Am9513A uses this clock input plus a BRDCLK divided by two input at Source 2 to generate six internal timebases These timebases can be used as clocks by the counter timers and by the frequency output channel When BRDCLK is 10 MHz the six internal timebases normally used for AT MIO 64F 5 timing functions are 5 MHz 1 MHz 100 KHz 10 kHz 1 kHz and 100 Hz The 16 bit counters in the Am9513A can be diagrammed as shown in Figure 3 18 SOURCE COUNTER Figure 3 18 Counter Block Diagram Each counter has a SOURCE input pin a GATE input pin and an output pin labeled OUT The Am9513A counters are numbered 1 through 5 and their GATE SOURCE and OUT pins are labeled GATE N SOURCE N and OUT N where N is the counter number For counting operations the counters can be programmed to use any of the five internal timebases any of the five GATE and five SOURCE inputs to the Am9513A and the output of the previous counter Counter 4 uses Counter 3 output and so on A co
248. nel Scanning Acquisition Rates esses A 5 OUIBUE 5 Explanation of Analog Output Specifications 2 22 2 2 2 2 6 junio A 7 oit E I D RR A PCR 7 Power Requirement from PONO Channel cesezcnceeeszs uestro ag rotis 7 igno 7 Operating Environment 00 cannaronenarcorncenasanssgegaconsnnnsensonsennenssensrsasnsnenennenngeensnatgennsseoneee A 7 SLOPAS EU 7 Appendix B KO P B 1 Appendix C Ig ee tomas EEN ctn atico 1 Appendix D Extended Analog Input Subconnector sees D 1 Appendix E AMD AmSS ISA Data Sheet 5 s errore EEEIEE E 1 Appendix F Customer Communibpation cio n ct t E REL REESE QU tc dete F 1 ee a ee AERE ae Index 1 National Instruments Corporation xiii AT MIO 64F 5 User Manual Contents Figure 1 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 2 8 Figure 2 9 Figure 2 10 Figure 2 11 Figure 2 12 Figure 2 13 Figure 2 14 Figure 2 15 Figure 2 16 Figure 2 17 Figure 2 18 Figure 2 19 Fig
249. neration 5 18 to 5 19 multiple analog input channel configurations 5 11 programmed cycle waveform generation 5 19 to 5 21 AT MIO 64F 5 User Manual Index 10 National Instruments Corporation Index pulsed cyclic waveform generation 5 21 to 5 23 resetting hardware 5 16 to 5 17 sample counter s 5 12 to 5 14 sample interval counter 5 11 to 5 12 scan interval counter 5 14 to 5 15 servicing data acquisition operations 5 16 single analog input channel configurations 5 10 single channel data acquisition sequence 5 5 to 5 6 single conversions 5 4 to 5 5 flow chart 5 4 generating single conversions 5 5 reading single conversion result 5 5 waveform cycle counter 5 24 to 5 25 waveform cycle interval counter 5 25 waveform generation functions 5 23 to 5 26 data acquisition rates multiple channel scanning rates A 5 single channel rates A 4 data acquisition timing circuitry block diagram 3 5 definition 3 7 multiple channel scanned data acquisition 3 10 to 3 12 rates of data acquisition 3 8 single channel data acquisition 3 8 to 3 10 single read timing 3 8 theory of operation 3 8 to 3 10 data acquisition timing connections 2 30 to 2 33 EXTCONV signal 2 31 EXTGATE signal 2 32 EXTSTROBE signal 2 30 to 2 31 EXTTMRTRIG signal 2 32 to 2 33 EXTTRIG signal 2 31 to 2 32 SCANCLK signal 2 30 data buffers PC I O channel interface circuitry 3 3 DB DIS bit 4 18 default settings for National Instrument products 2 4
250. nominal unadjusted gain error of each analog output channel is 0 2596 CALDACS and CALDAC7 adjust this gain error by lowering the value of the reference voltage by an adjustable amount between 0 and 50 mV or 0 to 0 5 of 10 V Thus the nominal gain adjustment range for a 10 V reference internal or external is 0 25 However the calibration mechanism is not designed to accommodate other reference voltages Thus when using an external reference it is advisable to set the gain CALDAC to 0 and to account for the 0 25 gain error of the analog output channel either in software or with external hardware AT MIO 64F 5 User Manual 6 6 National Instruments Corporation Appendix Specifications This appendix lists the specifications of the AT MIO 64F 5 These are typical at 25 C unless otherwise stated The operating temperature range is 0 to 50 C A warmup time of at least 15 min is required Analog Input Number of input channels Analog resolution Maximum sampling rate Relative accuracy nonlinearity quantization error see explanation of specifications Integral nonlinearity INL Differential nonlinearity DNL 0 2 LSB typical Differential analog input ranges Common mode input range Overvoltage protection lt 0 63 gt and AI SENSE Common mode rejection ratio Bandwidth 3 dB Input bias current Input offset current DIFF NRSE mode Input impedance Gains National Instruments Corporation 64
251. nput and output ratings 2 35 to 2 36 time lapse measurement 2 34 pins for 2 30 timing I O circuitry 3 20 to 3 23 block diagram 3 20 counter block diagram 3 21 timing I O specifications A 7 timing signals PC I O channel interface 3 3 TMRREQ bit 4 20 5 23 5 26 5 31 TMRREQ Clear Register 4 42 5 23 5 26 5 30 5 31 TMRTRIG signal definition 4 8 RTSI switch 3 24 servicing update requests 5 26 trigger applying 5 15 to 5 16 two s complement mode A D conversion values 4 24 to 4 25 U unpacking the AT MIO 64F 5 1 6 update counter selecting 5 23 update interval counter programming 5 23 to 5 24 National Instruments Corporation Index 23 AT MIO 64F 5 User Manual Index W waveform generation programming See also DAC waveform circuitry and timing clearing analog output circuitry 5 23 cyclic waveform generation 5 18 to 5 19 programmed cycle waveform generation 5 19 to 5 21 pulsed cyclic waveform generation 5 21 to 5 23 selecting internal update counter 5 23 update interval counter 5 23 to 5 24 waveform cycle counter 5 24 to 5 25 waveform cycle interval counter 5 25 servicing update requests 5 26 AT MIO 64F 5 User Manual Index 24 National Instruments Corporation
252. nsec between them The SOURCE signal shown in Figure 2 19 represents any of the signals applied at the SOURCE inputs GATE inputs or internal timebase clocks See Appendix E AMD Am9513A Data Sheet for further details Specifications for signals at the GATE input are referenced to the signal at the SOURCE input or one of the Am9513A internally generated signals Figure 2 19 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low at least 100 nsec before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by tgsy and tgh in Figure 2 19 Similarly the gate signal must be held for at least 10 nsec after the rising or falling edge of a source signal for the gate to take effect at that source edge The gate high or low period must be at least 145 nsec in duration If an internal timebase clock is used the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources Signals generated at the OUT output are referenced to the signal at the SOURCE input or to one of the Am9513A internally generated clock signals Figure 2 19 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 300
253. nstruments Corporation Chapter 3 Theory of Operation REF Selection DACI OUT Offset 10 V INT REF z Q Q Pa I O Connector DACOWR DACO OUT EXTREF From Gain DACO _ Figure 3 9 Analog Output Circuitry Block Diagram REF Selection Analog Output Circuitry Each analog output channel contains a 12 bit DAC reference selection switches unipolar bipolar output selection switches and output data coding circuitry The DAC in each analog output channel generates a voltage proportional to the input voltage reference Vref multiplied by the digital code loaded into DAC Each DAC can be loaded with a 12 bit digital code by writing to registers on the AT MIO 64F 5 board The output voltage is available on the AT MIO 64F 5 I O connector DACO OUT and DACI OUT pins The analog output of the DACS is updated to reflect the loaded 12 bit digital code in one of the following three ways e Immediately when the 12 bit code is written to the DACs in immediate update mode When an active low pulse is detected on the TMRTRIG signal in posted update mode When the Update Register is strobed in posted update mode National Instruments Corporation 3 13 AT MIO 64F 5 User Manual Theory of Operation Chapter 3 Analog Output Configuration The DAC output amplifiers can be configured through one of the AT MIO 64F 5 registers to generate either a unipolar voltage output or a bipolar voltage output r
254. nter 5 24 to 5 25 waveform cycle interval counter 5 25 waveform generation functions 5 23 to 5 26 data acquisition sequences with channel scanning 5 7 to 5 10 continuous channel scanning 5 7 to 5 8 interval channel scanning 5 8 to 5 10 digital I O circuitry 5 26 initialization Am9513A 5 2 to 5 3 AT MIO 64F 5 5 2 register programming considerations 5 1 resource allocation considerations 5 1 RTSI bus trigger line 5 27 to 5 28 RTSI switch 5 28 to 5 31 DMA operations 5 30 to 5 31 AT MIO 64F 5 User Manual Index 16 National Instruments Corporation Index interrupt programming 5 31 RTSI switch signal connections 5 28 single channel data acquisition sequence 5 5 to 5 6 single conversions generating 5 5 reading results 5 5 pseudosimultaneous scanning 5 7 pulse width measurement 2 32 pulsed cyclic waveform generation 5 21 to 5 23 pulses producing 2 33 R referenced single ended RSE input configuration 2 7 definition 2 7 single ended connections for floating signal sources 2 25 registers ADC Event Strobe Register Group 4 35 to 4 40 CONFIGMEMCLR Register 4 29 4 36 5 10 5 11 CONFIGMEMLD Register 4 29 4 37 5 10 5 11 DAQ Clear Register 4 38 5 10 5 30 5 31 DAQ Start Register 4 39 Single Conversion Register 4 40 Am9513A Counter Timer Register Group 4 51 to 4 54 Am9513A Command Register 4 53 Am9513A Data Register 4 52 Am9513A Status Register 4 54 programming 5 11 to 5 15 5 23 to 5 25 5 27
255. ntrol and Gating Control bit combinations Figure 16 Counter Mode Register Bit Assignments National Instruments Corporation Figure 17 Output Control Logic Am9513A E 27 2 141 AT MIO 64F 5 User Manua H d 2 142 AMD 9513 Data Sheet Figure 18 Counter Output Waveforms The other output form TC Toggled uses the trailing edge of TC to toggle a flip flop to generate an output level instead of a pulse The toggle output is half the frequency of TC The TC Toggled output will frequently be used to generate variable duty cycle square waves in Operating Modes G through K in Mode L the TC Toggled output can be used to generate a one shot function with the delay to the start of the output pulse and the width of the output pulse separately programma bie With selection of the minimum delay to the start of the puise the output will toggle on the second source pulse following application of the triggering Gate edge Note that the TC Toggled output form contains no implication about whether the output is active high or active low Unlike the TC output which generates a transient pulse which can clearly be active high or active low the TC Toggled output waveform only flips the state of the output on each TC The sole criterion of whether the TC Toggied output is active high or active low is the level of the output at the start of the count Cycle This can be controlled by the Set and Clear Output commands S
256. o another board that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is then divided by 10 and used as the Am9513A frequency source The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal Hardware Installation You can install the AT MIO 64F 5 in any available 16 bit expansion slot in your AT Series computer However to achieve best noise performance you should leave as much room as possible between the AT MIO 64F 5 and other boards and hardware The AT MIO 64F 5 does not work if installed in an 8 bit expansion slot PC Series After you have made any necessary changes verified and recorded the switches and jumper settings a form is included for this purpose in Appendix F Customer Communication you are ready to install the AT MIO 64F 5 AT MIO 64F 5 User Manual 2 10 National Instruments Corporation Chapter 2 Configuration and Installation The following are general installation instructions but consult your PC user manual or technical reference manual for specific instructions and warnings 1 Turn off your computer 2 Remove the top cover or access port to the I O channel 3 Remove the expansion slot cover on the back panel of the computer 4 Insert the AT MIO 64F 5 into a 16 bit slot Do not force the board into place Verify that there are no extended components on the circuit board of the computer that may to
257. o indicate when the input signal can be removed from the conversion channel This signal is available at the I O connector and can be used to control external multiplexers for higher channel count applications The rising edge of SCANCLK signals when the ADC has acquired the input signal and no longer needs to have it held available In the scanning acquisition modes this signal pulses for every conversion National Instruments Corporation 3 11 AT MIO 64F 5 User Manual Theory of Operation Chapter 3 Interval Scanning Data Acquisition Timing Interval scanning assigns a time between the beginning of consecutive scan sequences If only one scan sequence is in the configuration memory list the circuitry stops at the end of the list and waits the necessary interval time before starting the scan sequence again If multiple scan sequences are in the configuration memory list the circuitry stops at the end of each scan sequence and waits the necessary time interval before starting the next scan sequence When the end of the scan list is reached the circuitry stops and waits the necessary time interval before sequencing through the channel information list again Figure 3 8 shows an example of the interval scanning sequence timing Trigger DAQPROG CONVERT Channel COUNTER2 SCANCLK Interrupt DAQCLEAR Figure 3 8 Interval Scanning Posttrigger Data Acquisition Timing In interval scanning applications the first
258. of an interrupt when a data acquisition sequence completes If DAQCMPLINT is set an interrupt request is generated when the data acquisition operation completes The interrupt request is serviced by strobing the DAQ Clear Register When DAQCMPLINT is cleared completion of a data acquisition sequence does not generate an interrupt A data acquisition sequence ends by running its course or when an error condition occurs such as OVERRUN or OVERFLOW Input Output Interrupt Enable This bit along with the appropriate mode bits enables and disables I O interrupts generated from the AT MIO 64F 5 To select a specific mode refer to Table 4 3 for available modes and associated bit patterns DMA Channel A Enable This bit controls the generation of DMA requests DMA channel A as selected in Command Register 2 DMA requests are generated from A D conversions as well as from timer updates If DMACHA is set then requesting is enabled for DMA channel A If DMACHA is cleared no DMA requests are generated on DMA channel A To select a specific mode refer to Table 4 3 for available modes and associated bit patterns DMA Channel B Enable This bit controls the generation of DMA requests on DMA channel B as selected in Command Register 2 DMA requests are generated from A D conversions as well as from timer updates If DMACHB is set requesting is enabled for DMA channel B If DMACHB is cleared no DMA requests are generated on DMA channel B To
259. olled by pulses applied to the EXTCONV pin If Counter 3 is used to control A D conversions its output signal can be monitored at the EXTCONV pin A D conversions generated by either the EXTCONV signal or the sample interval counter are inhibited outside of a data acquisition sequence and when gated by either the hardware EXTGATE signal or software command register gate Note EXTCONV and the output of Counter 3 of Am95134A are physically connected together on AT MIO 64F 5 If Counter 3 is used in an application the EXTCONV signal must be left undriven Conversely if EXTCONV is used in an application Counter 3 must be disabled EXTTRIG Signal Any data acquisition sequence can be initiated by an external trigger applied to the EXTTRIG pin Applying a falling edge to the EXTTRIG pin starts the sample and sample interval counters thereby initiating a data acquisition sequence Figure 2 15 shows the timing requirements for the EXTTRIG signal National Instruments Corporation 2 31 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 tw 50 nsec minimum First A D conversion starts within 1 sample interval from this point Figure 2 15 EXTTRIG Signal Timing The EXTTRIG pin is also used to initiate AT MIO 64F 5 pretriggered data acquisition operations In pretriggered mode data is acquired after the first falling edge trigger is received but no sample counting occurs until after a second falling
260. on Appendix E CM6 Hardware Retriggering Whenever hardware retriggering is enabled Modes N O Q and R ali active going Gate edges initiate retrigger opera tions On application of the Gate edge the counter contents will be transferred to the Hold register On the first qualified Source edge after application of the retriggering Gate edge the Load register contents will be transferred into the counter Qualified source edges are edges which occur while the Counter is gated on and Armed This means that if level gating is used the edge occurring on active going gate transitions will initiate a retrigger Similarly when edge gating is enabled an edge used to start the counter will also initiate a retrigger The first count source edge applied after the Gate edge will not increment decre ment the counter but retrigger it LOAD LOAD AND ARM or a STEP Command occurs between the retriggering Gate edge and the first qualified Source edge will be interpreted as a source edge and transfer the Load register contents into the counter There after the counter will count ail qualified source edges When some form of Gating is specified CM7 controls hard ware retriggering In this case when CM7 0 hardware retriggering does not occur when CM7 1 the counter is retriggered any time an active going Gate edge occurs Retriggering causes the counter value to be saved in the Hold register and the Load register con
261. on serial DAC link over the RTSI bus DAC mode selection and miscellaneous configuration bits Bits 8 15 of this register are cleared upon power up or following a reset condition Bits 0 7 of this register are undefined upon power up and are not cleared after a reset condition These bits should be initialized through software Address Base address 06 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 MSB 7 6 D 4 3 2 1 0 S LSB Bit Name Description 15 4 CLKMODEB lt 1 0 gt Clock Mode Select These bits control the selection of the board clock and RTSI bus clock Upon power up CLKMODEBI and CLKMODEBO are cleared In this condition the board is configured for internal 10 MHz operation For other available modes see Table 4 5 for bit patterns Table 4 5 Board and RTSI Clock Selection Bit Effect Pattern i RTSI Clock Board Clock Internal 10 MHz Internal 10 MHz Driven onto board clock Received from RTSI clock CLKMODEBO Q gt Q Ee AT MIO 64F 5 User Manual 4 16 National Instruments Corporation Chapter 4 Bit Name 13 DACIDSP 12 DACODSP 11 8 DACMB lt 3 0 gt 7 DACGATE Register Map and Descriptions Description continued DAC 1 DSP Link Enable This bit controls the serial link from the AT DSP2200 to DAC 1 of the analog output section If DACIDSP is set then the serial link is enabled Data is sent from the AT DSP2200 over the RTSI bus and is accept
262. on each bit in the S field corresponds to one of five general counters 51 Counter 1 S2 Counter 2 etc When S bit is one the specified operation is performed on the counter so designated when an S bit is a Zero no operation occurs for the corresponding counter This type of command format has three basic advantages It saves host software by allowing any combination of counters to be acted on by a single command It allows simultaneous action on multiple counters where synchronization of commands is important It allows counter specific service routines to control individual counters without needing to be aware of the operating context of other counters Three of the commands use a 3 bit binary code N4 N2 N1 to identify the affected counter a 001 programs counter 1 etc Unlike the previousty mentioned commands these commands allow you to program only one counter at a time 2 143 AT MIO 64F 5 User Manual AMD Am9513A Data Sheet Command Code ED MCN cs cs G 000 G 110 52 51 couning for af 35 135 sz 51 Lond contents of spocited sourco imo coms opr ts sep ss 5 51 toad and Ama comes _ ro e pss 55 52 51 and Save al or ss 9e 51 Save an seco counters Hon OOO OOOO Paco Do ss sep Ss Se 51 counters 11 L
263. on the selected DAC update signal Counters 3 and 4 of the Am9513A are dedicated to data acquisition timing and therefore are not available for general purpose timing applications Signals generated at OUT3 and OUTA are sent to the data acquisition timing circuitry GATE3 is controlled by the data acquisition timing circuitry OUT3 is internally connected to EXTCONV so that when internal data acquisition sequences OUT3 are used EXTCONV should be disconnected or tristated For the same reason if external data acquisition sequences EXTCONV are used OUTS3 should be programmed to the high impedance state Counter 5 is sometimes used by the data acquisition timing circuitry and concatenated with Counter 4 to form a 32 bit sample counter The SCANCLK signal is connected to the SOURCE3 input of the Am9513A and OUT is sent to the data acquisition timing circuitry This allows Counter 1 to be used to divide the SCANCLK signal for generating the CONFIGCLK signal See the Data Acquisition Timing Circuitry section earlier in this chapter Counter 2 is sometimes used by the data acquisition timing circuitry to assign a time interval to each cycle through the scan sequence programmed in the channel configuration register This mode is called interval channel scanning See the Multiple Channel Data Acquisition section earlier in this chapter AT MIO 64F 5 User Manual 3 22 National Instruments Corporation Chapter 3 Theory of Operation The Am
264. on to the AT MIO 64F 5 register sizes An National Instruments Corporation 3 3 AT MIO 64F 5 User Manual Theory of Operation Chapter 3 8 bit access to a 16 bit location and vice versa is invalid and will cause sporadic operation The interrupt control circuitry routes any enabled board level interrupt requests to the selected interrupt request line The interrupt requests are tristate output signals that allow the AT MIO 64F 5 board to share the interrupt line with other devices Eight interrupt request lines are available for use by the AT MIO 64F 5 IRQ3 IRQ4 5 IRQ7 IRQ10 IRQ11 IRQ12 and IRQ15 These interrupt levels are selectable from one of the registers in the AT MIO 64F 5 register set Six different interrupts can be generated by the AT MIO 64F 5 Each of the following cases is individually enabled and cleared When the ADC FIFO buffer is ready to be serviced e When a data acquisition operation completes including an OVERFLOW or OVERRUN error When a DMA terminal count pulse is received on DMA channel DMA channel When the DAC FIFO buffer is ready to be serviced e When a DAC sequence completes including an UNDERFLOW error e When a falling edge signal is detected on the DAC update signal internal or external The DMA control circuitry generates DMA requests whenever an A D measurement is available from the ADC FIFO and when the DAC FIFO is ready to receive more data The DMA circuitry supports
265. onal Instruments Corporation 5 9 AT MIO 64F 5 User Manual Programming Chapter 5 Setting the SCN2 bit in Command Register 1 enables the use of a scan interval during multiple A D conversions The scan interval counter gives each cycle through the scan sequence a time interval The scan interval counter begins counting at the start of the scan sequence programmed into the channel configuration memory When the scan sequence terminates the next cycle through the scan sequence does not begin until the scan interval counter has reached its terminal count Be sure that the scan interval counter allows enough time for all conversions in a scan sequence to occur so that conversions are not missed Data Acquisition Programming Functions This section provides a detailed explanation of the functions necessary to program the analog input for single and multiple channel A D conversions Clearing the Analog Input Circuitry The analog input circuitry can be cleared by strobing the DAQ Clear Register This operation leaves the analog input circuitry in the following state Analog input error flags OVERFLOW and OVERRUN are cleared e Pending data acquisition interrupt requests are cleared e ADC FIFO is emptied DAQCOMP flag in the Status Register is cleared Empty the ADC FIFO before starting any A D conversions This action guarantees that the A D conversion results read from the FIFO are the results from the initiated conversions and are not
266. one value should be written and loaded into the channel configuration register National Instruments Corporation 4 29 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 Table 4 11 Extended Analog Input Connections Extended Analog Input Connector CHANSEL lt 5 0 gt Selected Analog Input Channels Single Ended Differential 010000 16 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 AT MIO 64F 5 User Manual 4 30 National Instruments Corporation Chapter 4 Register and Descriptions Analog Output Register Group The two registers making up the Analog Output Register Group access the two analog output channels Data can be transferred to the DACS in one of three ways depending on the mode configuration in Command Register 4 according to Table 4 6 Data can be directly sent to the DACs from the local data bus buffered from the local bus by the DAC FIFOs or received serially from the AT DSP2200 across the RTSI bus There are two methods of updating the DACS immediate and posted In the immediate update mode data transferred to the DACS is not buffered and is immediately converted
267. or disarming of the count sequence is delayed until TC is terminated MODE A Software Triggered Strobe with No Hardware Gating 15 om14 CMI3 2 1 1 cme x 7 TC OUTPUT Am9513A National Instruments Corporation gt COMMAND _ eX Figure 15a Mode A Waveforms AMD Am9513A Data Sheet Mode A shown in Figure 15a is one of the simplest operating modes The counter will be available for counting source edges when it is issued an ARM command On each TC the counter will reload from the Load register and automatically disarm itself inhibiting further counting Counting will resume when a new ARM command is issued MODE B Software Triggered Strobe with Level Gating Fass Gua curs cun cus curo cus x x X X TX 7 cw B shown in Figure 15b is identical to Mode A except that source edges are counted only when the assigned Gate is active The counter must be armed before counting can occur Once armed the counter will count source edges which occur while the Gate is active and disregard those edges which occur while the Gate is inactive This permits the Gate to turn the count process on and o
268. or Pin Assignment Figure 2 4 shows the pin assignment for the 50 pin MIO subconnector AI GND ACHO ACHI ACH2 ACH3 4 5 ACH6 ACH7 AI SENSE DACI OUT AO GND ADIOO ADIOI ADIO2 ADIO3 DIG GND 5 V EXTSTROBE EXTGATE SOURCEI OUTI GATE2 SOURCES OUTS AI GND ACH8 ACH9 ACH10 11 12 13 14 15 DACO OUT EXTREF DIG GND BDIOO BDIOI BDIO2 BDIO3 5 SCANCLK EXTTRIG EXTCONV GATEI EXTTMRTRIG OUT2 GATES FOUT Figure 2 4 50 Pin MIO Subconnector Pin Assignment National Instruments Corporation AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 MIO Subconnector Signal Connection Descriptions Pin 1 2 3 18 19 20 21 22 23 24 33 Signal Name AI GND lt 0 15 gt AI SENSE DACO OUT DACI OUT EXTREF AO GND DIG GND 25 27 29 31 ADIO lt 0 3 gt AT MIO 64F 5 User Manual Reference N A AI GND AI GND AO GND AO GND AO GND N A N A DIG GND 2 14 Description Analog Input Ground These pins are the reference point for single ended measurements and the bias current return point for differential measurements Analog Input Channels 0 through 15 In the DIFF mode the input is configured for up to 32 channels with lt 0 15 gt representing differential channels 0 through 7 In the RSE and NRSE modes the input is configured for up to 64 channels with
269. or bipolar voltage output range An onboard 10 V reference is the internal reference to the circuitry of the DAC A 2 048 word DAC FIFO buffer allows seamless waveform generation at the maximum rate without data loss The DAC FIFO can perform cyclic waveform generation directly from the FIFO independent of the PC interface You can use the analog output circuitry for internal timer and external signal update capability for waveform generation You calibrate the analog output circuitry through the NI DAQ software provided with the board This software adjusts the DAC offset and gain errors of each channel to zero by means of board level calibration DACs Calibration DAC constants resulting from the calibration procedure may be stored in the onboard EEPROM for later use See Chapter 6 Calibration Procedures for additional information on calibration procedures for the AT MIO 64F 5 National Instruments Corporation 1 1 AT MIO 64F 5 User Manual Introduction Chapter 1 Digital and Timing I O In addition to the analog input and analog output capabilities of the AT MIO 64F 5 the AT MIO 64F 5 also has eight digital I O lines that can sink up to 24 mA of current and three independent 16 bit counter timers for frequency counting event counting and pulse output applications The AT MIO 64F 5 has timer generated interrupts a high performance RTSI bus interface and four triggers for system level timing Figure 1 1 shows the AT MIO 64F 5 board
270. or straight binary format and unipolar input range Table 4 8 shows input voltage versus A D conversion value for two s complement format and bipolar input range AT MIO 64F 5 User Manual 4 24 National Instruments Corporation Chapter 4 Register Map and Descriptions Table 4 7 Straight Binary Mode A D Conversion Values Input Voltage A D Conversion Result Gain 1 Range 0 to 10 V OV 2 44 mV 2 5 V 5 0 V 7 5 V 9 999847 V To convert from the ADC FIFO value to the input voltage measured use the following formula V ADC reading 10 V 4 096 Gain Table 4 8 Two s Complement Mode A D Conversion Values A D Conversion Result Range 10 to 10 Input Voltage Gain 0 5 10 0 V 9 9951 V 5 V 4 88 mV 0 0 V 4 88 mV 5V 9 9951 V To convert from the ADC FIFO value to the input voltage measured use the following formula V ADC reading 5 V 2 048 Gain National Instruments Corporation 4 25 AT MIO 64F 5 User Manual Register Map and Descriptions Chapter 4 CONFIGMEM Register The CONFIGMEM Register controls the input channel selection multiplexers gain range and mode settings and can contain up to 512 channel configuration settings for use in scanning sequences Address Base address 08 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 amp MSB 7 6 5 4 3 2 1 0 CHANSELI CHANSELO CH GAIN CH GAINO CHAN LAST CHAN_GHOST CHAN DSP
271. orage area consists of locations 96 through 127 While at the factory these locations can be accessed for a read or a write operation but in the field these locations can only be read from These locations cannot and should not be written to This allows for a permanent set of calibration values that cannot be erased The modifiable area consists of locations 0 through 95 These locations can always be read from and written to Included in this area are the load area user areas and user reference areas Notice that the load area contains constants that are loaded at initialization by the software to place the board in a known and calibrated state Revision SEX f Subrevision 0000 A Figure 6 2 Revision and Subrevision Field If the Revision and Subrevision Field contain the binary value 00100010 this signifies that the accessed AT MIO 64F 5 board is at Revision C and Subrevision 2 This number can be very useful in tracking boards in the field and in answering questions concerning board operation Board operation sometimes varies depending on the revision or subrevision of the board 0110 16 384 0101 8 192 Reserved 0100 4 096 0011 2 048 fo CONFIGMEM Length 0010 17024 0001 512 0000 256 Figure 6 3 Configuration Memory Depth Field If the Configuration Memory Depth Field contains the binary value XXXX0001 where X indicates don t care bits this signifies that the accessed AT MIO 64F 5 board contains a configur
272. orporation 4 13 AT MIO 64F 5 User Manual Register Map and Descriptions Chapter 4 Bit Name Description continued Table 4 3 DMA and Interrupt Modes Continued WM Mode Description channel A trom ADC vitn timer interop 0 B 10 DACI wiin ADC iner 0 Channels A and B to DACs 0 and 1 double buffered with ADC interrupt Channel A and Channel B to DACO double buffered with ADC interrupt 0 Channel A and Channel B to double buffered with ADC interrupt Channels and B to DACs 0 and 1 sync double channel with ADC interrupt 1 Channels and B from ADC double buffered with timer interrupt 1 a 1 1 Channel A to DACO and Channel from ADC 1 a a 1 0 Channel Ato and Channel from ADC Channel to and interleaved and Channel B from ADC 5 DACIREQ DAC 1 Request Enable This bit controls DMA requesting and interrupt generation from D A updates If this bit is set an interrupt or DMA request is generated when the DAC is ready to receive data If this bit is cleared no DMA request or interrupt is generated To select a specific mode refer to Table 4 3 for available modes and associated bit patterns 2 s e gt s Sto penso 21444 4 DACOREQ DAC 0 Request Enable Th
273. output for a total of four possible output signals generated for one timing mode The GATE and OUT pins for Counters 1 2 and 5 and SOURCE pins for Counters 1 and 5 of the onboard Am9513A are located on the AT MIO 64F 5 I O connector A falling edge signal on the EXTTRIG pin of the I O connector or writing to the STARTDAQ register during a data acquisition sequence sets the flip flop output signal connected to the GATE4 input of the Am9513A and can be used as an additional gate input This mode is also used in the pretrigger data acquisition mode The flip flop output connected to GATE4 is cleared when the sample counter reaches TC when an overflow or overrun occurs or when the DAQ Clear Register is written to An overrun is defined as an error generated when the ADC cannot keep up with its programmed conversion speed The Am9513A SOURCES pin is connected to the AT MIO 64F 5 RTSI switch which means that a signal from the RTSI trigger bus can be used as a counting source for the Am9513A counters The Am9513A OUTI OUT2 OUT3 EXTCONV and OUTS pins can be used in several different ways If waveform generation is enabled an active low pulse on the output of the counter selected through the RTSI switch updates the analog output on the two DACs The counter outputs can also be used to trigger interrupt and DMA requests If the proper mode is selected in Command Register 2 an interrupt or DMA request occurs when a falling edge signal is detected
274. p 4 45 to 4 50 Calibration DAC 0 Load Register 4 50 DMA Channel Clear Register 4 46 DMATCA Clear Register 4 47 5 23 DMATCB Clear Register 4 48 5 23 External Strobe Register 4 49 register map 4 2 general purpose timing connections 2 33 to 2 37 event counting application with external switch gating 2 34 frequency measurement 2 34 to 2 35 GATE SOURCE and OUT signals 2 33 to 2 34 input and output ratings 2 35 to 2 36 time lapse measurement 2 34 ground referenced signal sources definition and requirements 2 20 differential connections 2 22 recommended configurations for ground referenced and floating signal sources 2 21 single ended connections 2 26 30 5 30 5 31 5 30 5 31 H hardware installation 2 10 to 2 11 resetting after data acquisition operation 5 16 to 5 17 I immediate update mode 3 14 to 3 15 initialization Am9513A System Timing Controller 5 2 to 5 3 AT MIO 64F 5 User Manual Index 14 National Instruments Corporation Index AT MIO 64F 5 5 2 input configurations See also CONFIGMEM Register common mode signal rejection 2 26 to 2 27 differential input floating signal sources 2 23 to 2 24 general considerations 2 21 ground referenced signal sources 2 22 recommended configurations for ground referenced and floating signal sources 2 21 single ended connections floating signal RSE sources 2 25 general considerations 2 24 to 2 25 grounded signal NRSE sources 2 26 input mode S
275. parailel resonant fundamental mode type An RC or LC or other reactive network may be used instead of a crystal For driving from an external frequency source X1 should be left open and X2 should be connected to a TTL source and a pull up resistor Frequency Out The FOUT output is derived from a 4 bit counter that may be programmed to divide its input by any integer value from 1 through 16 inclusive The input to the counter is selected from any of 15 sources including the internal scaled oscillator frequencies FOUT may be gated on and off under software control and when off will exhibit a low impedance to ground Control over the various FOUT options resides in the Master Mode register After power up FOUT provides a frequency that is 1 16 that of the osciliator The input source on power up is F1 Gate The Gate inputs may be used to control the operations of individual counters by determining when counting may proceed The same Gate input may control up to three counters Gate pins may also be selected s count sources for any of the counters and for the FOUT divider The active polarity for a selected Gate input is programmed at each counter Gating function options allow level sensitive gating or edge initiated gating Other gating modes are available including one that aliows the Gate input to select between two counter output frequencies gating functions may also be disabled The active Gate input is conditioned by an auxiliary input
276. peration interval timing signals The sample interval timer can also use any of the external clock inputs to the Am9513A as a timebase During data acquisition the sample interval counts down at the rate given by the internal timebase or external clock Each time the sample interval timer reaches zero it generates an active low pulse and reloads with the programmed sample interval count initiating a conversion This operation continues until data acquisition halts External control of the sample interval is possible by applying a stream of pulses at the EXTCONV input In this case you have complete external control over the sample interval and the number of A D conversions performed All data acquisition operations are functional with external signals to control conversions This means that in a data acquisition sequence that employs external conversion timing conversions are inhibited by the hardware until a trigger condition is received then the programmed number of conversions occurs and conversions are inhibited after the sequence completes When using internal timing the EXTCONV signal at the I O connector must be left unconnected or in the high impedance state Data acquisition can be controlled by the onboard sample counter This counter is loaded with the number of posttrigger samples to be taken during a data acquisition operation The sample counter can be 16 bit for counts up to 65 535 or 32 bit for counts up to 222 1 If a 16 bit
277. plied to an armed counter The counter must be armed before application of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded An armed counter will start counting on the first source edge after the triggering Gate edge Counting will then proceed in the same manner as in Mode After the second TC the counter will disarm itself An ARM command and Gate edge must be issued in this order to restart counting Note that after application of a triggering Gate edge the Gate input will be disregarded until the second TC This differs from Mode where the Gate can be modulated throughout the count cycle to stop and start the counter Figure 15h Mode H Waveforms Am9513A National Instruments Corporation E 19 2 133 AT MIO 64F 5 User Manual AMD Am9513A Data Sheet MODE J Variable Duty Cycle Rate Generator with No Hardware Gating Fewss eua uia owns euro owe cus Ex Ex LX TX x cus cus cw ome ono J shown in Figure 15 will find the greatest usage in frequency generation applications with variable duty cycle requirements Once armed the counter will count continuously until it is issued a DISARM command On the first TC the counter will be reloaded from the Hoid register Counting will then proceed until the second TC at which time the counter will be reloaded from the Load register
278. polar operation and values read from the ADC FIFO are in straight binary format When CHAN is set the ADC is configured for bipolar operation and values The FIFO values are two s complement and automatically sign extended 11 6 CHANSEL lt 5 0 gt Input Channel Select These six bits control the input multiplexer address setting for selecting the analog input channel routed to the ADC In single ended mode only one analog input channel is selected In differential mode two analog input channels are selected See Table 4 11 and the following table for the mapping of analog input channels in the different input configurations National Instruments Corporation 4 27 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 Bit Name Description continued Primary MIO Connector Selected Analog Input Channels CHANSEL lt 5 0 gt Single Ended Differential and 8 1 and 9 2 10 3 and 11 4 and 12 5 and 13 6 and 14 7 and 15 000000 000001 000010 000011 000100 000101 000110 000111 001000 0 and 8 001001 1 and 9 001010 2 and 10 001011 3 and 11 001100 4 and 12 001101 5 and 13 001110 6 and 14 001111 7 and 15 5 3 CH GAIN 2 0 Channel Gain Select These three bits control the gain setting of the input PGIA for the selected channel The following gains can be selected on the AT MIO 64F 5 2CHAN LAST Channel Last This bit should be set
279. ppendix E AMD Am9513A Data Sheet contains the manufacturer data sheet for the AMD Am9513A System Timing Controller integrated circuit Advanced Micro Devices Inc This controller is used on the AT MIO 64F 5 e Appendix Customer Communication contains forms you can use to request help from National Instruments or to comment on our products and manuals The ndex contains an alphabetical list of key terms and topics in this manual including the page where each one can be found National Instruments Corporation AT MIO 64F 5 User Manual Preface Conventions Used in This Manual The following conventions are used in this manual italic Italic text denotes emphasis a cross reference or an introduction to a key concept NI DAQ NI DAQ is used throughout this manual to refer to the NI DAQ software for DOS Windows LabWindows unless otherwise noted PC PC refers to the IBM PC AT and compatible computers and to EISA personal computers Abbreviations The following metric system prefixes are used with abbreviations for units of measure in this manual The following abbreviations are used in this manual A amperes dB decibels ft feet F farads hex hexadecimal Hz hertz ksamples 1 000 samples M megabytes of memory m meters Q ohms percent ppm parts per million rms root mean square sec seconds V volts Vref reference voltage Vrms volts root mean square AT MIO 64F 5 User Manual vi Natio
280. provide puises or leveis and can be active high or active low The counters can be programmed to count up or down in either binary BCD The host processor may read an accumulated count at any time without disturbing the counting process Any of the counters may be internally concatenated to torm any effective counter length up to 80 bits BLOCK DIAGRAM Am9513A AT MIO 64F 5 User Manual 2 Appendix E AMD 9513 Data Sheet CONNECTION DIAGRAMS Top View DG812 GATE OBTUGATE 4A OG10 GATE 2 GNO CD005212 Note Pin 1 is marked for orientation ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges The order number Valid Combination is formed by a combination of a Device Number b Speed Option if applicable Type ____ OPTIONAL PROCESSING Blank Standard processing 8 Bumin d TEMPERATURE RANGE C Commercial 0 to 70 Industrial 40 to 85 C c PACKAGE TYPE P 40 Pin Plastic DIP PD 040 D 40 Pin Ceramic DIP 040 J 44 Pin Plastic Leaded Chip Carrier PL 044 b SPEED OPTION Not Applicable amp DEVICE NUMBER DESCRIPTION Am9513A System Timing Controlier Valid Combinations Valid Combinations list configurations planned to be supported in Valid Combinations volume for this device Consuit the local AMD sales office
281. ptions of the two registers making up the Digital I O Register Group are given on the following pages National Instruments Corporation 4 55 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 Digital Input Register The Digital Input Register when read returns the logic state of the eight AT MIO 64F 5 digital I O lines Address Base address 1C hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 MSB 7 6 5 4 3 2 1 0 BDIO3 BDIO2 BDIO BDIOO ADIO3 ADIO2 ADIOI ADIOO LSB Bit Name Description 15 8 X Don t care bits 7 4 BDIO lt 3 0 gt These four bits represent the logic state of the digital lines BDIO lt 3 0 gt 3 0 ADIO lt 3 0 gt These four bits represent the logic state of the digital lines ADIO lt 3 0 gt AT MIO 64F 5 User Manual 4 56 National Instruments Corporation Chapter 4 Register and Descriptions Digital Output Register Writing to the Digital Output Register controls the eight AT MIO 64F 5 digital I O lines The Digital Output Register controls both ports A and B When either digital port is enabled the pattern contained in the Digital Output Register is driven onto the lines of the digital port Address Base address 1C hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 5 DNE NE RC ONE NE NUN MSB 7 6 5 4 3 2 1 0 BDIO3 BDIO2 BDIO1 BDIOO ADIO3 ADIO2 ADIOI ADIOO LSB Bit Name Description 15 8 0 Reserved
282. put will go into TC if programmed to be in the active High or active Low terminal count modes The only two ways out of TC in this case are Arming the counter and having an active source con nected to it ssuing another step command Troubleshooting Symptom Solution 10 Timing parameters TEHWH and TGVWH are specified as negative The diagrams in Figure A3 show the relationship between these signals 11 In mode X the counter will count all qualified source edges until the second not the first TC and then stop 12 A TC can occur when the counters are loaded if the counter was stopped at or 999940 in the count up mode or at count 0001 when counting down This is because an internal TC is generated which forces TC to be generated on the next count pulse 13 In modes that aiternate the reload source between the load and the hold registers e 9 mode J if the counter is disarmed at 00014 for down counting or 999919 for BCD up counting or FFFF for binary up counting and rearmed the reload source after the first TC will be the ioad register instead of the hold register To avoid this issue a software dummy toad to the counter immediately after the disarm command 14 in the down counting mode of the Am9513A if a 0001 is loaded into the counter and another LOAD COUNTER command is issued the TC of that counter will go active If the load register contents are subsequently changed and the counter armed
283. r low If the counter is programmed to count an internal timebase then the pulse width is equal to the counter value multiplied by the timebase period For time lapse measurement a counter is programmed to be edge gated An edge is applied to the counter GATE input to start the counter The counter can be programmed to start counting after receiving either a high to low edge or a low to high edge If the counter is programmed to count an internal timebase then the time lapse since receiving the edge is equal to the counter value multiplied by the timebase period To measure frequency a counter is programmed to be level gated and the rising or falling edges are counted in a signal applied to a SOURCE input The gate signal applied to the counter GATE input is of some known duration In this case the counter is programmed to count either rising or falling edges at the SOURCE input while the gate is applied The frequency of the input signal is then the count value divided by the known gate period Figure 2 18 shows the connections for a frequency measurement application A second counter can also be used to generate the gate signal in this application AT MIO 64F 5 User Manual 2 34 National Instruments Corporation Chapter 2 Configuration and Installation Signal Source DIG GND MIO Subconnector AT MIO 64F 5 Board Figure 2 18 Frequency Measurement Application Two or more counters can be concatenated by tying the OUT signal fro
284. rack to rack Consult the specification for the rack you intend to use for the location of any polarizing key The recommended manufacturer part numbers for this polarizing key are as follows e Electronic Products Division 3M part number 3439 2 T amp B Ansley Corporation part number 609 0005 Unpacking Your AT MIO 64F 5 board is shipped in an antistatic package to prevent electrostatic damage to the board Several components on the board can be damaged by electrostatic discharge To avoid such damage in handling the board take the following precautions e Touch the antistatic package to a metal part of your PC chassis before removing the board from the package Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not install a damaged board into your computer AT MIO 64F 5 User Manual 1 6 National Instruments Corporation Chapter 2 Configuration and Installation This chapter explains the board configuration installation of the AT MIO 64F 5 into the PC signal connections to the AT MIO 64F 5 and cable considerations Board Configuration The AT MIO 64F 5 contains one DIP switch to configure the base address selection for the AT bus interface The remaining resource selections such as DMA and interrupt channel selections are determined by programming the individual registers in the AT MIO 64F 5 r
285. ransient pulses as short as half the period of the FOUT Source may appear on the FOUT pin Tuming the FOUT gate on or off can also generate a transient This should be considered when using FOUT as a system clock source Am9513A E 12 Appendix E National Instruments Corporation Appendix E Bus Width Bit MM13 controls the multiplexer at the data bus interface in order to configure the part for an 8 bit or 16 bit extemal bus The intemal bus is always 16 bits wide When MM13 1 16 bit data is transferred directly between the intemal bus and ail 16 of the extera bus lines In this configuration the Byte Pointer bit in the Data Pointer register remains set at ali times When MM13 0 16 bit internal data is transferred a byte at a time to and from the eight low order external data bus lines The Byte Pointer bit toggies with each byte transfer in this mode When the Am9513A is set to operate with an 8 bit data bus width pins DB8 through DB15 are not used for the data bus and are available for other functions Pins DB13 through DB15 should be tied high Pins 088 through 0812 are used as auxiliary gating inputs and are labeled GATE1A through GATESA respectively The auxiliary gate pin GATENA is logically ANDed with the gate input to Counter N as shown in Figure 12 The output of the AND gate is then used as the gating signal for Counter N Data Pointer Sequencing Bit MM14 controls the Data Pointer logic to enable or dis
286. ranteed to not influence the contents read from the Status register on the current read operation 5 Any input transition that occurs after this minimum hold time is guaranteed to be seen by the counter as occurring after the action initiated by the write operation and the counter may be off by one count 6 This parameter applies to cases where the write operation causes a change in the output bit 7 The enabled count source is one of F1 F5 TCN 1 SRC1 SRC5 GATE1 GATE 5 as selected in the applicable Counter Mode register The timing diagram assumes the counter counts on rising source edges The timing specifications are the same for falling edge counting B This parameter applies to edge gating CM15 CM13 110 or 111 and gating when both CM7 1 and CM15 13 000 This parameter represents the minimum GATE pulse width needed to ensure that the pulse initiates Counting or counter reloading 9 parameter applies to both edge and level gating CM15 CM13 001 through 111 and 0 This pa AMD Am9513A Data Sheet rameter represents the minimum setup or hold times to ensure that the Gate input is seen at the intended level on the active source edge and the counter may be off by one Count 10 This parameter assumes that the GATENA input is unused 16 bit bus mode or is tied high In cases where the GATENA input is used this timing specification must be met by both the GATE and GATENA inputs 11 Si
287. ration Chapter 1 Introduction What Your Kit Should Contain The contents of the AT MIO 64F 5 kit part number 776655 01 are listed as follows Kit Component Part Number AT MIO 64F 5 board 181395 01 AT MIO 64F 5 User Manual 320487 01 NI DAQ software for DOS Windows LabWindows with manuals 776250 01 NI DAQ Software Reference Manual for DOS Windows LabWindows 320498 01 NI DAQ Function Reference Manual for DOS Windows LabWindows 320499 01 If your kit is missing any of the components contact National Instruments Your AT MIO 64F 5 is shipped with the NI DAQ software for DOS Windows LabWindows NI DAQ has a library of functions that can be called from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation digital I O counter timer SCXI RTSI and self calibration NI DAQ maintains a consistent software interface among its different versions so you can switch between platforms with minimal modifications to your code NI DAQ comes with language interfaces for Professional BASIC Turbo Pascal Turbo C Turbo C Borland C and Microsoft C for DOS and Visual Basic Turbo Pascal Microsoft C with SDK and Borland C for Windows NI DAQ software is on high density 5 25 in and 3 5 in diskettes Optional Software This manual contains complete instructions for directly programm
288. rcuitry Analog input circuitry Data acquisition timing circuitry Analog output and timing circuitry DAC waveform generation and timing circuitry Digital I O circuitry Timing I O circuitry RTSI bus interface circuitry The internal data and control buses interconnect the components The theory of operation of each of these components is explained in the remainder of this chapter PC I O Channel Interface Circuitry The AT MIO 64F 5 board is a full size 16 bit PC I O channel adapter The PC I O channel consists of a 24 bit address bus a 16 bit data bus a DMA arbitration bus interrupt lines and several control and support signals The components making up the AT MIO 64F 5 PC I O channel interface circuitry are shown in Figure 3 2 AT MIO 64F 5 User Manual 3 2 National Instruments Corporation Chapter 3 Theory of Operation Address Address Address Register Latches Decoder Selects PCI O Channel Read and Write I O Channel Timing Signals Control Lines Interface 16 Data Buffers Internal Data Bus S e 5 AT MIO 64F 5 DMA Request DMA Request Control DMA Circuitry AT MIO 64F 5 Acknowledge DMA Acknowledge and Terminal Count IRQ AT MIO 64F 5 Contro Interrupt Circuitry Request Figure 3 2 PC I O Channel Interface Circuitry Block Diagram The PC I O channel interface circuitry consists of address latches address decoder circuitry data buffers PC I O channel interf
289. resetting after data acquisition operation 5 16 to 5 17 resource allocation programming considerations 5 1 Analog Input Register Group 4 23 to 4 30 ADC FIFO Register 4 24 to 4 25 5 5 5 16 5 31 CONFIGMEM Register 4 26 to 4 30 5 10 5 11 Analog Output Register Group 4 31 to 4 34 analog output voltage versus digital code 4 31 to 4 32 DACO Register 4 33 DACI Register 4 34 Configuration and Status Register Group 4 4 to 4 22 Command Register 1 4 5 to 4 7 Command Register 2 4 8 to 4 10 5 31 Command Register 3 4 11 to 4 15 Command Register 4 4 16 to 4 18 Status Register 1 4 19 to 4 21 Status Register 2 4 22 5 26 DAC Event Strobe Register Group 4 41 to 4 44 DAC Clear Register 4 44 5 23 5 26 5 30 DAC Update Register 4 43 TMRREQ Clear Register 4 42 5 23 5 26 5 30 5 31 description format 4 3 Digital I O Register Group 4 55 to 4 57 Digital Input Register 3 19 to 3 20 4 56 National Instruments Corporation Index 19 AT MIO 64F 5 User Manual Index Digital Output Register 3 19 4 57 General Event Strobe Register Group 4 45 to 4 50 Calibration DAC 0 Load Register 4 50 DMA Channel Clear Register 4 46 DMATCA Clear Register 4 47 5 23 DMATCB Clear Register 4 48 5 23 External Strobe Register 4 49 programming considerations 5 1 register map 4 1 to 4 2 register sizes 4 2 RTSI Switch Register Group 4 58 to 4 60 RTSI Switch Shift Register 4 59 RTSI Switch Strobe Register 4 60 relative accuracy specificat
290. rmination during operation will not be a problem Where inputs are driven from logic external to the card containing this chip however on board termination should be provided to protect the chip when the board is unplugged the input would otherwise ficat A pull up resistor or a simple inverter or gate will suffice 2 121 AT MIO 64F 5 User Manual AMD Am9513A Data Sheet DETAILED DESCRIPTION The 951 System Timing Controller STC is a support device for processor oriented systems that is designed to enhance the available capability with respect to counting and timing operations it provides the capability for programmable frequency synthesis high resolution programmabte duty cycie waveforms retriggerable digital timing functions time of day clocking coincidence alarms complex pulse generation high resolution baud rate generation frequency shift keying stop watching timing event count accumulation waveform analysis amp nd many more A variety of programmable operating modes and control features allow the Am9513A to be personalized for Particular applications as well as dynamically reconfigured under program control The STC includes five general purpose 16 bit counters A variety of internal frequency sources and external pins may be selected as inputs for individual counters with software select able active high or active low input polarity Both hardware and sof
291. roceed the specified mode unti the counter is disarmed When 5 0 the count process will proceed only until one full cycle of operation occurs This may occur after one or TC events The counter is then disarmed automatically The single or double TC requirement will depend on the state of other control bits Note that even if the counter is automatical ly disarmed upon a TC it always counts the count source edge which generates the trailing TC edge When TC occurs the counter is always reloaded with a value from either the Load register of the Hold register Bit CM6 specifies the source options for reloading the counter When CM6 0 the contents of the Load register will be transferred into the counter at every occurrence of TC When CM6 1 the counter reload location will be either the Load or Hold Register The reload location in this case may be controlled externally by using a Gate pin Modes S and V or may alternate on each TC Modes G through L With alternating Sources and with the TC Toggled output selected the duty cycle of the output waveform is controlled by the relative Load and Hold values and very fine resolution of duty cycles ratios may be achieved CM7 controls the special gating functions that allow retriggering and the selection of Load or Hold sources for counter reloading The use and definition of CM7 will depend Am9513A E 28 Appendix E National Instruments Corporati
292. s 2 27 to 2 28 definition 2 14 C 2 EXTREFDACO bit 4 9 EXTREFDAC bit 4 9 EXTSTROBE signal definition 2 15 C 2 digital I O circuitry 3 20 timing connections 2 30 to 2 31 EXTTMRTRIG signal definition 2 16 C 3 servicing update requests 5 26 timing connections 2 32 to 2 33 EXTTRIG signal applying a trigger 5 15 definition 2 15 C 3 programming sample interval counter 5 11 RTSI switch 3 24 single channel data acquisition timing 3 8 to 3 9 timing applications 3 22 timing connections 2 31 to 2 32 EXTTRIG DIS bit 4 18 F field wiring considerations 2 37 to 2 38 FIFO continuous cyclic waveform generation 3 17 to 3 18 FIFO DAC bit 4 18 FIFO programmed cyclic waveform generation 3 18 National Instruments Corporation Index 13 AT MIO 64F 5 User Manual Index FIFO pulsed waveform generation 3 18 to 3 19 floating signal sources description of 2 20 differential connections 2 23 to 2 24 recommended configurations for ground referenced and floating signal sources 2 21 single ended connections 2 25 FOUT signal 2 16 2 35 2 36 3 24 5 27 C 3 frequency measurement 2 34 to 2 35 functional overview See theory of operation G gain error analog input circuitry A 2 to A 3 analog output circuitry A 6 GATE OUT and SOURCE timing signals 2 33 to 2 37 3 21 to 3 22 3 24 GATE signal 2 15 3 GATE2 signal 2 16 C 3 GATE2SEL bit 4 18 5 23 GATES signal 2 16 C 3 General Event Strobe Register Grou
293. s of the DMA process on the selected DMA channel A When the DMA operation is completed DMATCA goes high and remains high until cleared by strobing the DMATCA Clear Register DMA Terminal Count Channel B DMATCB reflects the status of the DMA process on the selected DMA channel B When the DMA operation is completed DMATCB goes high and remains high until cleared by strobing the DMATCB Clear Register Overflow This bit indicates whether the ADC FIFO has overflowed during a sample run OVERFLOW is an error condition that occurs if the FIFO fills up with A D conversion data and A D conversions continue If OVERFLOW is set A D conversion data has been lost because of FIFO overflow If OVERFLOW is clear no overflow has occurred If OVERFLOW occurs during a data acquisition operation the data acquisition is terminated immediately This bit is reset by strobing the DAQ Clear Register Overrun This bit indicates whether an A D conversion was initiated before the previous A D conversion was complete OVERRUN is an error condition that can occur if the data acquisition sample interval is too small sample rate is too high If OVERRUN is set one or more conversions were skipped If OVERRUN is clear no overrun condition has occurred If OVERRUN occurs during a data acquisition operation the data acquisition is immediately terminated This bit is reset by strobing the DAQ Clear Register Timer Request This bit reflects the status of t
294. s Corporation Chapter 5 Programming Write OXFFFF to the Am9513A Issue a master reset operation Command Register Write OxFFEF to the Am9513A Enable 16 bit access mode Command Register Write OXFF17 to the Am9513A Point to the master mode register Command Register Write OxF000 to the Am9513A Load the master mode value Data Register Write OxFFOO ctr to the Point to the counter mode register Am9513A Command Register Write 0x0004 to the Am9513A Store the counter mode value Data Register Write OxFFOS ctr to the Point to the counter load register Am9513A Command Register Write 0x0003 to the Am9513A Store an inactive count value Data Register Increment Ctr Write 5 to the Am9513A Load all counters Command Register Figure 5 1 Initializing the Am9513A Counter Timer National Instruments Corporation 5 3 AT MIO 64F 5 User Manual Programming Chapter 5 Programming the Analog Input Circuitry The analog input circuitry can be programmed for a number of different modes depending on the application If single channels are to be monitored on an ad hoc basis then the single conversion mode can be used If a number of consecutive conversions on any one given channel are required the single channel data acquisition mode should be used If more than one channel needs to be monitored with multiple conversions per channel the scanning data acquisition mode should be used This mode scans through a programmed number of
295. s permanently stored in the EEPROM on the AT MIO 64F 5 With this stored reference value the AT MIO 64F 5 board can be recalibrated without additional external hardware at any time under any number of different operating conditions in order to remove errors caused by temperature drift and time The AT MIO 64F 5 is calibrated at the factory in both unipolar and bipolar modes and these values are also permanently stored in the EEPROM Calibration constants can be read from the EEPROM then written to the calibration DACS that adjust pregain offset postgain offset and gain errors associated with the analog input section There is an 8 bit pregain offset calibration DAC an 8 bit postgain offset calibration DAC an 8 bit unipolar offset calibration DAC and an 8 bit gain calibration DAC Functions are provided with the board to calibrate the analog input section access the EEPROM on the board and write to the calibration DACs When the AT MIO 64F 5 leaves the factory locations 96 through 127 of the EEPROM are protected and cannot be modified Locations 0 through 95 are unprotected and can be used to store alternate calibration constants for the differing conditions under which the board is used Refer to Chapter 6 Calibration Procedures for additional calibration information National Instruments Corporation 3 7 AT MIO 64F 5 User Manual Theory of Operation Chapter 3 Data Acquisition Timing Circuitry This section details the different methods o
296. s register should be initialized through software Address Base address 00 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 MSB 7 6 5 4 3 2 1 0 sans soe eme ame 9 Td LSB Bit Name Description 15 EEPROMCS EEPROM Chip Select This bit controls the chip select of the onboard EEPROM used to store calibration constants When EEPROMCS is set the chip select signal to the EEPROM is enabled Before EEPROMCS is brought high SCLK should first be pulsed high to initialize the EEPROM circuitry 14 SDATA Serial Data This bit is used to transmit a single bit of data to the EEPROM and both of the calibration DACs 13 SCLK Serial Clock A low to high transition of this bit clocks data from SDATA into the EEPROM when EEPROMC S is set and the calibration DAC If EEPROMCS is cleared toggling SCLK does not affect the EEPROM Serial data is always loaded into the calibration DACs but the information is not updated until after the application of the appropriate load signal 12 SCANDIV Scan Divide This bit controls the configuration memory sequencing during scanned data acquisition If SCANDIV is set then sequencing is controlled by Counter 1 of the Am9513A Counter Timer If SCANDIV is cleared the configuration memory is sequenced after each conversion during scanning 11 DITHER Dither When this bit is set 0 5 LSBs of white Gaussian noise is added to the selected analog input signal
297. se has the effect of forcing quantization noise to become a zero mean random variable rather than a deterministic function of input For more information on the effects of dither see Dither in Digital Audio by John Vanderkooy and Stanley P Lipshitz Journal of the Audio Engineering Society Vol 35 No 12 Dec 1987 ADC FIFO Buffer When an A D conversion is complete the ADC circuitry shifts the result into the ADC FIFO buffer The FIFO buffer is 16 bits wide and 512 words deep This FIFO serves as a buffer to the ADC and is beneficial for two reasons Any time an A D conversion is complete the value is saved in the FIFO buffer for later reading and the ADC is free to start a new conversion Secondly the FIFO can collect up to 512 A D conversion values before any information is lost thus software or DMA has extra time 512 times the sample interval to catch up with the hardware If more than 512 values are stored in the FIFO without the FIFO being read from an error condition called FIFO overflow occurs and A D conversion information is lost When the ADC FIFO contains a single A D conversion value or more it can generate a DMA or interrupt request to be serviced Analog Input Calibration Measurement reliability is assured through the use of the onboard calibration circuitry of the AT MIO 64F 5 This circuitry uses a stable internal 5 VDC reference that is measured at the factory against a higher accuracy reference then its value i
298. ses 2 33 Field Wiring Considerations eiecit tute pter ya NU SERIA P SUPR eR esee lods 2 37 Cabling Considerations 22 ea au ur END 2 38 Chapter 3 Theory of Operation cuoi ene tee in tme me 3 1 Puncttonal mme o Md opas MM LUE 3 1 PC I O Channel Interface Circuitry ois erm hoo oot 3 2 Analog Input and Data Acquisition 3 4 Adalog Input 3 6 3 6 Analog Input Multplexetsics E aded uode da Fey Qo esse 3 6 Analog Input 3 6 E e goed ay 3 6 ADC FIFO Buller vetet eain ds 3 7 Analog Input Calibration tence ies tato oci dec bete 3 7 Data Acquisition Timing Circuitry 3 8 single Read Dg eoe E e o desea idis 3 8 Single Channel Data Acquisition Timing eee 3 8 Multiple Channel Data 3 10 Continuous Scanning Data Acquisition Timing esee 3 11 Interval Scanning Data Acquisition Timing eene 3 12 Acquisition Rales
299. single ended 32 differential 12 bit 1 in 4 096 200 ksamples sec minimum 1 5 LSB maximum over temperature 0 8 LSB typical 1 LSB maximum over temperature 0 3 LSB typical 1 LSB maximum no missing codes over temperature 5 V or 0 to 10 V software selectable Each input to the instrumentation amplifier should remain within 12 V of AIGND at any gain or range 15 V power off 25 V power on 80 dB minimum 100 dB typical gain 0 5 86 dB minimum 106 dB typical gain 1 92 dB minimum 107 dB typical gain 2 94 dB minimum 107 dB typical gain 5 DC to 380 KHz all gains 200 pA 100 pA 100 GQ in parallel with 100 pF 0 5 1 2 5 10 20 50 and 100 software selectable 1 AT MIO 64F 5 User Manual Specifications Appendix A Pregain offset error After calibration 10 uV maximum Before calibration 2 2 mV maximum Temperature coefficient 5 Postgain offset error After calibration 0 4 mV maximum Before calibration 100 mV maximum Temperature coefficient 240 Gain error relative to reference After calibration 0 004 40 ppm maximum Before calibration any gain 0 8 Gain 1 0 02 200 ppm maximum with gain error adjusted to 0 at gain 1 Temperature coefficient any gain 25 ppm C System noise excluding quantization noise Bipolar 10 V range 0 2 LSB rms for gains 0 5 to 50 dither off 0 4 LSB rms for gain 100 dither off 0 5 LSB rms dither on Onboard reference 5
300. sponds to one and LOW corresponds to zero These lines act as inputs when WR and CS are active and as outputs when AD and CS are active When CS is inactive these pins are placed in a high impedance state After power up or reset the data bus will be configured for 8 bit width and will use onty DBO through 087 080 is the least significant and 087 is the most significant bit position The data bus may be reconfigured for 16 bit width by changing a control bit in the Master Mode register This is accomplished by writing an 8 bit command into the iow order DB lines while holding the 0813 0815 lines at a logic high level Thereafter ail 16 lines can be used with as the teast significant and 0815 as the most significant bit When operating in the 8 bit data bus environment 088 0815 will never be driven active by the Am8513A 088 through DB12 may optionally be used as additional Gate inputs see Figure 2 If unused they should be heid HIGH When pulled LOW GATENA signal will disable the action of the corri ing counter gating 0813 0815 should be held HIGH 8 bit bus mode whenever CS and W are Simultaneously active Chip Select The active low Chip Select input enables Read and Write operations on the data bus When Chip Select is HIGH the Read and Write inputs are ignored The first Chip Select signal after power up is used to clear the power on reset circuitry t Chip Select is tied to ground permanentty the power on reset
301. ss This bit indicates whether a data acquisition operation is in progress If DAQPROG is set a data acquisition operation is in progress If DAQPROG is cleared the data acquisition operation has completed 13 ADCFIFOHF ADC FIFO Half Full Flag This bit reflects the state of the ADC FIFO If the appropriate conversion interrupts are enabled see Table 4 3 and ADCFIFOHF is clear the current interrupt indicates at least 256 A D conversions are available in the ADC FIFO To clear the interrupt read the ADC FIFO until it is empty ADCFIFOEF is clear If ADCFIFOHF is set less than 256 ADC conversions are available in the ADC FIFO National Instruments Corporation 4 19 AT MIO 64F 5 User Manual Register and Descriptions Bit Name 12 ADCFIFOEF 11 DMATCA 10 DMATCB 9OVERFLOW 7 TMRREQ AT MIO 64F 5 User Manual Chapter 4 Description continued FIFO Empty Flag This bit reflects the state of the FIFO If ADCFIFOEF is set one or more A D conversion results can be read from the ADC FIFO If the appropriate conversion interrupts are enabled see Table 4 3 and ADCFIFOEF is set the current interrupt indicates that A D conversion data is available in the ADC FIFO To clear the interrupt the FIFO must be read until it is empty If ADCFIFOEF is cleared ADC FIFO is empty and no conversion interrupt request is asserted DMA Terminal Count Channel A DMATCA reflects the statu
302. stable internal 5 VDC reference that is measured at the factory against a higher accuracy reference then its value is permanently stored in the EEPROM on the AT MIO 64F 5 With this stored reference value the AT MIO 64F 5 board can be recalibrated without external hardware at any time under any number of different operating conditions in order to remove errors caused by temperature drift and time The AT MIO 64F 5 is factory calibrated in both unipolar and bipolar modes and these values are also permanently stored in the EEPROM Calibration constants can be read from the EEPROM then written to the calibration DACs that adjust offset and gain errors associated with each analog output channel For each DAC channel there is an 8 bit offset calibration DAC and an 8 bit gain calibration DAC Functions are provided with the board to calibrate the analog output section access the EEPROM on the board and write to the calibration DACs When the AT MIO 64F 5 leaves the factory locations 96 through 127 of the EEPROM are protected and cannot be modified Locations 0 through 95 are unprotected and can be used to store alternate calibration constants for the differing conditions under which the board is used Refer to Chapter 6 Calibration Procedures for additional calibration information DAC Waveform Generation Timing and Circuitry There are primarily two modes under which the DACs in the analog output section operate immediate update and posted updat
303. ster 3 contains 16 bits that control the ADC link to the AT DSP2200 digital I O port interrupt and DMA modes and interrupt channel selection The contents of this register are defined to be cleared upon power up and after a reset condition Address Base address 04 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 MSB 7 6 4 3 2 1 0 DMACHB ADCREQ DACIREQ DACOREQ DRVAIS INTCHB2 INTCHBO LSB Bit Name Description 15 ADCDSP ADC DSP Link Enable This bit controls the serial link from the A D converter to the AT DSP2200 If ADCDSP is set then the serial link is enabled Data from channels that have been marked in the channel configuration memory will be transmitted over the RTSI bus If ADCDSP is cleared the serial RTSI link is disabled irrespective of the marking of channels in the channel configuration memory 14 DIOPBEN Digital I O Port B Enable This bit controls the 4 bit digital output port B If DIOPBEN is set the Digital Output Register drives the DIO lt 8 5 gt digital lines at the I O connector If DIOPBEN is cleared the Digital Output Register drivers are set to a high impedance state therefore an external device can drive the DIO 8 5 digital lines 13 DIOPAEN Digital I O Port A Enable This bit controls the 4 bit digital output port A If DIOPAEN is set the Digital Output Register drives the DIO lt 4 1 gt digital lines at the I O connector If DIOPAEN is cl
304. t Digital I O Circuitry The AT MIO 64F 5 has eight digital I O lines These eight digital I O lines are divided into two ports of four lines each and are located at pins ADIO lt 3 0 gt and BDIO lt 3 0 gt on the I O connector Figure 3 16 shows a block diagram of the digital I O circuitry Digital 4 Output Register BDIO lt 3 0 gt I O Connector PC I O Channel B A 4 EXTSTROBE EXT STROBE WR Figure 3 16 Digital I O Circuitry Block Diagram The digital I O lines are controlled by the Digital Output Register and monitored by the Digital Input Register The Digital Output Register is an 8 bit register that contains the digital output values for both ports 0 and 1 When port 0 is enabled bits lt 3 0 gt in the Digital Output Register are driven onto digital output lines ADIO lt 3 0 gt When port 1 is enabled bits lt 7 4 gt in the Digital Output Register are driven onto digital output lines BDIO lt 3 0 gt National Instruments Corporation 3 19 AT MIO 64F 5 User Manual Theory of Operation Chapter 3 Reading the Digital Input Register returns the state of the digital I O lines Digital I O lines ADIO lt 3 0 gt are connected to bits lt 3 0 gt of the Digital Input Register Digital I O lines BDIO lt 3 0 gt are connected to bits lt 7 4 gt of the Digital Input Register When a port is enabled the Digital Input Register serves as a read back register returning the digital output value o
305. t 4 9 DMATCA 4 20 5 23 5 31 DMATCB 4 20 5 23 5 31 DMATCINT 4 12 DRVAIS 4 14 EEPROMCD 4 21 EEPROMCS 4 5 EEPROMDATA 4 21 EISA DMA 4 9 EXTREFDACO 4 9 EXTREFDACI 4 9 EXTTRIG DIS 4 18 FIFO DAC 4 18 GATE2SEL 4 18 5 23 INTCHB lt 2 0 gt 4 15 INTGATE 4 6 I O INT 4 12 OUT 5 1 4 54 OUTEN 5 30 OVERFLOW 4 20 5 5 5 16 OVERRUN 4 20 5 5 5 16 RETRIG DIS 4 6 RSI 4 59 RTSITRIG 4 7 52 through SO bits 5 29 SCANDIV 4 5 5 11 SCANEN 4 6 5 8 5 9 SCLK 4 5 SCN2 4 6 5 10 SDATA 4 5 SRC3SEL 4 18 TMRREQ 4 20 5 23 5 26 5 31 board and RTSI clock selection See RTSI clock configuration board configuration See configuration 5 5s 2 National Instruments Corporation Index 7 AT MIO 64F 5 User Manual Index BRDCLK frequency 3 21 3 23 BYTEPTR bit 4 54 C lt 7 0 gt bit 4 53 cables and cabling cabling considerations 2 38 custom cables 1 5 field wiring considerations 2 37 to 2 38 Calibration DAC 0 Load Register 4 50 calibration procedures analog input calibration 3 7 6 6 to 6 7 analog output calibration 3 14 6 7 to 6 8 calibration DACs 1 1 6 5 CHAN CAL bit for controlling analog input configuration 4 27 EEPROM ADC and DAC FIFO Depth field 6 4 Area Information field 6 4 Configuration Memory Depth Field 6 3 EEPROM map 6 1 factory area information 6 2 Revision and Subrevision field 6 3 storage area 1 1 6 3 equipment requirements 6 5 reference calibration 6
306. t Bit Map Not applicable no bits used Strobe Effect Clears the TMRREQ signal in Status Register 1 and its associated interrupts and clears the DAC COMP signal in Status Register 1 and its associated interrupt The analog output DACS can be updated internally and externally in the waveform generation mode through the control of A4RCV If A4RCV is enabled internal updating is selected and any signal from the RTSI switch can control the updating interval If OUT2 is to be used for updating the DACs A2DRV must also be enabled If OUTS is to be used A4DRV must be enabled as well If A4RCV is disabled external updating is selected and the EXTTMRTRIG signal from pin 44 of the primary MIO connector is used for updating In all cases a falling edge on the selected signal triggers the updating mechanism in posted update mode This trigger also sets the TMRREQ bit in Status Register 1 and generates an interrupt or DMA request if so enabled AT MIO 64F 5 User Manual 4 42 National Instruments Corporation Chapter 4 Register and Descriptions DAC Update Register Accessing the DAC Update Register with posted update mode enabled updates both DACO and DACI simultaneously with the previously written values and removes DAC FIFO data for DACO DAC1 or both as programmed Address Base address 18 hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used Strobe Effect Updates latched DAC values to the DAC Re
307. t a full 32 bit compare must be true in order to generate a true signal on OUT2 OUT will continue as usual to reflect the state of the 16 bit comparison between Alarm 1 and Counter 1 2 126 AT MIO 64F 5 User Manual FOUT Source Master Mode bits MM4 through specify the source input for the FOUT divider Fifteen inputs are available for selection and they include the fivo Source pins the five Gate pins and the five internal frequencies derived from the oscillator The 16th combination of the four control bits ail zeros is used to assure that an active frequency is available at the input to the FOUT divider following reset FOUT Divider Bits MM8 through MM11 specify the dividing ratio for the FOUT Divider The FOUT source selected by bits MM4 through is divided by an integer value between 1 and 16 inclusive and is then passed to the FOUT output buffer After power on or reset the FOUT divider is set to divide by 16 FOUT Gate Master Mode bit MM12 provides a software gating capability for the FOUT signal When MM12 1 FOUT is off and in a low impedance state to ground MM12 may be set or cleared in conjunction with the loading of the other bits in the Mastor Mode register alternatively there are commands that allow 12 to be individually set or cleared directly without chang ing any other Master Mode bits After power up or reset FOUT is gated on When changing the FOUT divider ratio or FOUT source t
308. t map field for some registers states not applicable no bits used Accessing these registers generates a strobe in the AT MIO 64F 5 These strobes are used to initiate some onboard event to occur For example they can be used to clear the analog input circuitry or to start a data acquisition operation The data is ignored when writing to these registers therefore any bit pattern suffices Likewise data returned from a strobe register read access is meaningless National Instruments Corporation 4 3 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 Configuration and Status Register Group The six registers making up the Configuration and Status Register Group allow general control and monitoring of the AT MIO 64F 5 hardware Command Registers 1 2 3 and 4 contain bits that control operation of several different pieces of the AT MIO 64F 5 hardware Status Registers 1 and 2 can be used to read the state of different pieces of the AT MIO 64F 5 hardware Bit descriptions of the six registers making up the Configuration and Status Group are given on the following pages AT MIO 64F 5 User Manual 4 4 National Instruments Corporation Chapter 4 Register and Descriptions Command Register 1 Command Register 1 contains 12 bits that control AT MIO 64F 5 serial device access and data acquisition mode selection The contents of this register are not defined upon power up and are not cleared after a reset condition Thi
309. te 0 to Command Registers lt 1 4 gt 2 Access the following strobe registers CONFIGMEMCLR Register DAQ Clear Register DMATC A and B Clear Registers DMA Channel Clear Register DAC Clear Register TMRREQ Clear Register 3 Initialize the Am9513A see the next section Initializing the 9513 4 Disable all RTSI switch connections see the Programming the RTSI Switch section later in this chapter This sequence leaves the AT MIO 64F 5 circuitry in the following state and interrupts are disabled The DMA circuitry is cleared The outputs of counter timers are in the high impedance state The analog input circuitry is initialized The analog output is in immediate update mode The ADC and DAC FIFOs are cleared The DIO ports and B are set for input mode Initializing the Am9513A Use the sequence in Figure 5 1 to initialize the Am9513A Counter Timer writes are 16 bit operations All values are given in hexadecimal After this sequence of writes the Am9513A Counter Timer is in the following state 16 bit mode is enabled The BCD scaler division is selected The FOUT signal is turned off e All counter OUT output pins are set to the high impedance output state e All counters are loaded with a nonterminal count value For additional details concerning the Am9513A Counter Timer see Appendix E AMD Am9513 Data Sheet AT MIO 64F 5 User Manual 5 2 National Instrument
310. te to modulate the duty cycle of the output waveform It can affect both the HIGH and LOW portions of the output waveform 9513 20 Appendix National Instruments Corporation Appendix E AMD Am9513A Data Sheet x ON Lf Figure 15 Mode J Waveforms 007 DED ED CO CO x X CO CO CO cs S NN NL WFO004891 Figure 15k Mode K Waveforms MODE L Hardware Triggered Delayed Puise One Shot wis cuna cur 1 1 CMe 2 Pots Mode L shown in Figure 151 is similar to Mode J except that counting will not begin until a Gate edge is applied to armed counter The counter must be armed before application of the triggering Gate edge Gate edges applied to a disarmed source edges after the triggering Gate edge arid counting will Proceed until the second TC Note that after application of a triggering Gate edge the Gate input will be disregarded for the remainder of the count cycle This differs from Mode where the gate can be modulated throughout the count cycle to stop and start the counter On the first TC after application of the triggering Gate edge the counter will be relo
311. tents to be transferred into the counter When No Gating is specified the definition of CM7 changes In this case when CM7 0 the Gate input has no effect on the counting when CM7 1 the Gate input specifies the source selecting either the Load or Hold register used to reload the counter when TC occurs Figure 14 shows the various available control combinations for these interrelated bits Count Source Selection Counter Mode bits CM8 through CM12 specify the source used as input to the counter and the active edge that is counted Bit CM12 controls the polarity for all the sources logic zero counts rising edges and logic one counts falling edges Bits CM8 through CM11 select 1 of 16 counting sources to route to the counter input Five of the available inputs are internal frequencies derived from the internal oscillator see Figure 13 for frequency assignments Ten of tho available inputs are interface pins five are labeled SRC and five are labeled GATE The 16th available input is the TC output from the adjacent lower numbered counter The Counter 5 TC wraps around to the Counter 1 input This option allows internal concatenating that permits very iong counts to be accumulated Since all five Counters may be concatenated it is possible to configure a counter that is 80 bits long on one Am9513A chip When TCN 1 is the source the count rippies between the connected counters External connections can also be made and can use th
312. ter 5 4 Write the 16 LSBs of the sample count value minus 1 to the Am9513A Data Register to store the Counter 4 load value e If the 16 LSBs are all 0 write FFFF 5 Write FF48 to the Am9513A Command Register to load Counter 4 6 Write 0 to the Am9513A Data Register to store 0 into the Load Register for Counter 4 reloading 7 Write FF28 to the Am9513A Command Register to arm Counter 4 8 Write FF05 to the Am9513A Command Register to select the Counter 5 Mode Register 9 Write 25 to the Am9513A Data Register to store the Counter 5 mode value 10 Write FFOD to the Am9513A Command Register to select the Counter 5 Load Register 11 Take the 16 MSBs of the sample count and complete the following steps Ifthe 16 LSBs of the sample count are all 0 or all 0 except for a 1 in the LSB write the 16 MSBs to the Am9513A Data Register to store the Counter 5 load value Otherwise add 1 to the 16 MSBs of the sample count and write that value to the Am9513A Data Register to store the Counter 5 load value 12 Write FF70 to the Am9513A Command Register to load and arm Counter 5 13 Set the CNT32 16 bit in Command Register to notify the hardware that both Counters 4 and 5 will be used as the sample counter After you complete this programming sequence Counter 4 is configured to count A D conversion pulses generated by Counter 3 and Counter 5 decrements every time Counter 4 reaches zero The data acquisition operation is terminated w
313. ter in this chapter Figure 2 9 shows a schematic diagram of this configuration NRSE Input 64 Channels NRSE input means that all input signals are referenced to the same common mode voltage but this common mode voltage can float with respect to the analog ground of the AT MIO 64F 5 board This common mode voltage is subsequently subtracted by the input PGIA This configuration is useful when measuring ground referenced signal sources See the Types of Signal Sources section later in this chapter for more information National Instruments Corporation 2 7 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 With this input configuration the AT MIO 64F 5 can measure up to 64 different analog input signals This configuration is selected via software See the configuration memory register and Table 4 9 in Chapter 4 Register Map and Descriptions for additional information The results of this configuration are as follows AI SENSE is tied into the negative input of the PGIA e Multiplexer outputs are tied together into the positive input of PGIA e Multiplexer control is configured to control up to 64 input channels Note The NRSE input mode is the only mode in which the AI SENSE signal from the I O connector is used as an input In all other modes AI SENSE is programmed to be unused or driven with the board analog input ground Considerations for using the NRSE input configuration are discussed in the Sign
314. that exceed any of the maximum ratings of input or output signals on the AT MIO 64F 5 can result in damage to the AT MIO 64F 5 board and to the PC Maximum input ratings for each signal are given in this chapter under the discussion of that signal National Instruments is not liable for any damages resulting from such signal connections National Instruments Corporation 2 11 AT MIO 64F 5 User Manual Configuration and Installation Chapter 2 AIGND ACHI6 AIGND 40 17 ACH8 18 9 42 ACH2 19 10 ACH43 ACH3 ACH20 ACH44 ACH4 21 12 ACH45 5 ACH22 ACH46 ACH6 ACH23 14 ACH47 ACH7 ACH24 ACHI5 48 AISENSE ACH25 DACO OUT ACH49 DACI OUT ACH26 EXTREF ACH50 AO GND ACH27 DIG GND ACHSI ADIOO 5 BDIOO AIGND ADIOI ACH28 BDIOI 52 ADIO2 ACH29 BDIO2 53 ADIO3 ACH30 BDIO3 54 DIG GND 5 55 5V ACH32 SCANCLK ACH56 EXTSTROBE ACH33 EXTTRIG 57 ACH34 EXTCONV 58 SOURCEI ACH35 GATEI ACH59 OUTI ACH36 EXTTMRTRIG ACH60 GATE2 ACH37 OUT2 ACH61 SOURCES ACH38 GATES ACH62 OUTS ACH39 FOUT ACH63 MIO Subconnector Extended Analog Input Pins Subconnector Pins Figure 2 3 AT MIO 64F 5 I O Connector Pin Assignment AT MIO 64F 5 User Manual 2 12 National Instruments Corporation Chapter 2 Configuration and Installation MIO Subconnect
315. the Load register The counter may be retriggered at any time by presenting an active going Gate edge to the Gate input The retriggering Gate edge will transfer the contents of the counter into the Hold register The first qualified source edge after the retrig gering Gate edge will transfer the contents of the Load register into the Counter Counting will resume on the second qualified source edge after the retriggering Gate edge Quali fied source edges are active going edges which occur while the Gate is active Am9513A National Instruments Corporation MODE R Retriggerable One Shot ___ x x x X 1 EEEREENENENENENEN Mode R shown in Figure 15r is similar to Mode Q except that edge gating rather than level gating is used In other words rather than use the Gate level to qualify which source edges to count Gate edges are used to start the counting operation The counter must be armed before application of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded After application of a Gate edge an armed counter will count all source edges until TC irrespective of the Gate level On the first TC the counter will be reloaded from the Load register and stopped Subsequent counting will not occur until a new Gate edge is applied All Gate edges applied to the counter including the first used to trigger counting initiate a retrigger operation Upon application of a Gate edg
316. the PC National Instruments is not liable for damages resulting from such a connection Timing Connections Pins 36 through 50 of the MIO subconnector are connections for timing I O signals Pins 36 through 40 and pin 44 carry signals used for data acquisition timing and analog output triggering These signals are explained in the next section Data Acquisition Timing Connections Pins 41 through 50 carry general purpose timing signals and analog output provided by the onboard Am9513A Counter Timer These signals are explained in the General Purpose Timing Signal Connections section later in this chapter Data Acquisition and Analog Output Timing Connections The data acquisition and analog output timing signals are SCANCLK EXTSTROBE EXTTRIG EXTGATE and EXTTMRTRIG SCANCLK Signal SCANCLK is an output signal that generates a low to high edge whenever an A D conversion begins SCANCLK pulses only when scanning is enabled on the AT MIO 64F 5 SCANCLK is normally low and pulses high for approximately 4 usec after the A D conversion begins low to high edge can be used to clock external analog input multiplexers The SCANCLK signal is driven by one CMOS TTL gate EXTSTROBE Signal A low pulse of no less than 500 nsec is generated on the EXTSTROBE pin when the External Strobe Register is accessed See the External Strobe Register section in Chapter 4 Register Map and Descriptions for more information Figure 2 1
317. the Status Register to alert you that one or more A D conversion results have been lost because of FIFO overflow Strobing the DAQ Clear Register resets this error flag An ADC overrun condition occurs if an attempt is made to start a new conversion while the previous conversion is being completed If this condition occurs the OVERRUN bit is set in Status Register 1 to indicate an error condition or that an invalid operation occurred Strobing the DAQ Clear Register resets this error flag Programming a Single Channel Data Acquisition Sequence The following programming sequence for sample counts less than 65 537 leaves the data acquisition circuitry in a retriggerable state The sample interval and sample counters are reloaded at the end of the data acquisition to prepare for another data acquisition operation The counters do not need reprogramming and the next data acquisition operation starts when another trigger condition is received National Instruments Corporation 5 5 AT MIO 64F 5 User Manual Programming Chapter 5 In posttrigger sequences the sample counter starts counting after receipt of the first trigger while in the pretrigger acquisition mode the sample counter does not start counting until a second trigger condition occurs The data acquisition operation is initiated by writing to the DAQ Start Register or by a falling edge on the EXTTRIG signal Programming multiple A D conversions on a single channel requires the followin
318. the data acquisition There is no delay between the cycles of the scan sequence Continuous channel scanning can be thought of as a round robin approach to scanning multiple channels Interval channel scanning gives each scan sequence a programmed time interval called a scan interval Each cycle of the scan sequence begins at the time interval determined by the scan interval If the sample interval counter is programmed for the minimum time required to complete an A D conversion interval channel scanning can be thought of as a pseudosimultaneous scanning of multiple channels that is all channels in the scan sequence are read as quickly as possible at the beginning of each scan interval Continuous Channel Scanning Data Acquisition Use the programming steps listed in Figure 5 4 to program continuous scanning of multiple A D conversions for posttrigger and pretrigger modes as well as internal and external timing The instructions in the blocks of the following flow chart are enumerated in the Data Acquisition Programming Functions section later in this chapter National Instruments Corporation 5 7 AT MIO 64F 5 User Manual Programming Chapter 5 Clear the A D circuitry Program multiple analog input channels gains modes and ranges Program the sample interval counter Program the sample counter Enable a scanning data acquisition operation Apply a trigger Service the data acquisition operation Figure 5 4 Continuo
319. the gain times the pregain offset error Gain error is the amount of possible deviation from ideal gain expressed as a proportion of the gain AT MIO 64F 5 User Manual A 2 National Instruments Corporation Appendix Specifications The total linear measurement error for a given input voltage takes into account all gain and offset errors but does not include any nonlinear errors such as relative accuracy It is the sum of the gain error times the input voltage the gain times the pregain offset error and the postgain offset Tables 1 2 list equivalent offset and gain errors for 12 bit ADC systems and may be useful for comparing systems They also apply to 12 bit DAC systems Table A 1 Equivalent Offset Errors in 12 Bit Systems Range LSB Voltage of FSR 01010 V 5 244 mV 0 0244 Table A 2 Equivalent Gain Errors in 12 Bit Systems Range LSB of FSR PPM of Gain 0 to 10 V 1 0 0244 0 0244 244 ppm 5to5V 1 0 0244 0 0488 488 ppm Nonlinear Errors Relative accuracy is a measure of the linearity of an ADC However relative accuracy is a tighter specification than a nonlinearity specification Relative accuracy as used in this manual indicates the maximum deviation from a straight line for the analog input to digital output transfer curve based on the locations of the code transitions If an ADC has been calibrated perfectly then this straight line is the ideal transfer function and the
320. ticle e Dither in Digital Audio by John Vanderkooy and Stanley P Lipshitz Journal of the Audio Engineering Society Vol 35 No 12 Dec 1987 National Instruments Corporation vii AT MIO 64F 5 User Manual Preface Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix F Customer Communication at the end of this manual AT MIO 64F 5 User Manual viii National Instruments Corporation Contents Chapter 1 Introductions i cates ews SU n Medi 1 1 Board De setipEofrcs soe esses dici votes e ein dts cos Laducpetun fades Code Posi 1 1 Analog boot t E 1 1 1 1 Digital and Timing 1 2 What Your Kit Should d ce Gi 1 3 Optional SoftWare tialis eine ee EE 1 3 odis ad ge eae 1 4 Custom i CE EDI 1 5 Unpacking spisso tet tie adi temen 1 6 Chapter 2 Configuration and Installation
321. ting signal such as the DAQPROG signal In addition the sample counter Counter 4 is programmed to count the number of conversions generated In this case the sample counter is programmed to count 10 samples then stop the acquisition sequence National Instruments Corporation 3 9 AT MIO 64F 5 User Manual Theory of Operation Chapter 3 A signal is generated at the end of the sequence to indicate its completion An interrupt request can be generated from this signal if desired Because the sample counter begins counting immediately after the application of the trigger this is a posttrigger sequence If samples are necessary before and after the trigger then a pretrigger sequence is needed This sequence is described in the following paragraphs Figure 3 6 depicts a pretrigger data acquisition sequence It is called a pretrigger sequence because the first trigger initiates the sample interval timer without enabling the sample counter Conversions occur after this initial trigger and are stored in the ADC FIFO for later retrieval in the same way they are for a posttrigger sequence After a second trigger is received the sample counter begins counting conversions In this example there are three pretrigger samples and seven posttrigger samples Only the number of posttrigger samples is programmable Trigger DAQPROG CONVERT od doe o 0 50 1 Samp CTR Gte Sample CTR 6 5 4 3 2 1 7 _ 6 DAQCMPIT Interr
322. to the appropriate voltage at the output In the posted update mode data is converted to an output voltage only after a falling edge is detected on the TMRTRIG signal or the DAC Update Register is strobed In the immediate update mode and the serial mode the DAC FIFOs are not utilized In all other output modes the DAC FIFOs are used The output voltage generated from the digital code depends on the configuration unipolar or bipolar of the associated analog output channel This configuration is determined by control bits in the Command Register 2 Configuration bits in Command Register 2 determine if the digital code written to the DACS is in straight binary form or in a two s complement form Table 4 10 shows the output voltage versus digital code for a unipolar analog output configuration Table 4 11 shows the voltage versus digital code for a bipolar analog output configuration The formula for the voltage output versus digital code for a unipolar analog output configuration is as follows Vout Vref digital code 4 096 where is the reference voltage applied to the analog output channel The digital code in the above formula is a decimal value ranging from 0 to 4 095 Table 4 10 Analog Output Voltage Versus Digital Code Unipolar Mode Digital Code Voltage Output Decimal Hex Vref 10 V The formula for the voltage output versus digital code for a bipolar analog output configuration in two s complement form is as follo
323. to within 0 000346 3 ppm of the 4 V step It may take as long as 100 psec for the circuitry to settle this much In general this extra settling time is not needed when the PGIA is switching to a lower gain Because of the problems with settling times multiple channel scanning is not recommended unless sampling rates are low enough or it is necessary to simultaneously sample several signals as close as possible The data is much more accurate and channel to channel independent if you acquire data from each channel independently for example 100 points from Channel 0 then 100 points from Channel 1 then 100 points from Channel 2 and so on If however all of the channels are scanned at the same gain the circuitry settles to full 12 bit accuracy 0 5 LSB in under 5 usec and the channels be scanned at the full rate of 200 ksamples sec Analog Output Number of output channels 2 Type of DAC 12 bit multiplying Data transfers DMA programmed I O or interrupts Maximum update rate 1 Msamples sec FIFO data regeneration Output settling time to 0 01 FSR 4 usec for a 20 V step Output slew rate 25 V usec Relative accuracy nonlinearity 0 5 LSB maximum 0 25 LSB typical Differential nonlinearity 1 LSB maximum monotonic over temperature Offset error After calibration 0 8 mV maximum Before calibration 120 mV maximum Temperature coefficient 50 uV C National Instruments Corporation 5 AT MIO 64F 5 User Manual Spe
324. tput Capacitance dine nat end ws a ve 1 o 31 26 20 Guaranteed by design ux SWITCHING TEST INPUT OUTPUT WAVEFORMS 138pF 24V I c 0 8 77 POINTS x2 WF004810 i Crystal is fundamental mode parallel resonant 32 pF load capacitance less than 100 Q ESR Co less than 100 pF 0 45 TCO02000 Am9513A 2 147 National Instruments Corporation E 33 AT MIO 64F 5 User Manual AMD Am9513A Data Sheet The second and fourth ietters designate the reference states of the signals named in the first and third letters respectively using the following abbreviations H HIGH L LOW VALID X Unknown or Don t care Z High impedance 2 Any input transition that occurs before this minimum setup requirement will be reflected in the contents read from the Status register 3 Any input transition that occurs before this minimum setup requirement will act on the counter before the execution of the operation initiated by the write and the counter may be off by one count 4 Any input transition that occurs after this minimum hold time is guaranteed to not influence the contents read from the status register on the current read operation is guaranteed to be seen by the counter as occurring after ho Arton by tha write operation and the counter may be off by count 6 This parameter applies to cases where the write operation causes a change in the
325. ts are generated when the ADC FIFO is half full In this case the request is removed only when the ADC FIFO has been emptied of all its data When ADCFIFOREQ is cleared ADC interrupt DMA requests are generated when a single conversion is available in the FIFO In this case the request is removed when the ADC FIFO is empty Source 3 Select This bit is used to configure the signal connected to Source 3 of the Am9513 Counter Timer If SRC3SEL is set Source 3 is connected to the DAC FIFO retransmit signal In the FIFO programmed cycle waveform modes this bit should be set so the counter can access to the DAC FIFO retransmit signal If SRC3SEL is cleared Source 3 is connected to the SCANCLK signal Gate 2 Select This bit is used to configure the signal connected to Gate 2 of the Am9513 Counter Timer If GATE2SEL is set Gate 2 is connected to Out 1 of the Am9513 This bit should be set when using the FIFO pulsed waveform generation mode If GATE2SEL is cleared Gate 2 is connected to the internal Gate 2 circuitry on the AT MIO 64F 5 FIFO or DAC Write Select This bit controls the destination of writes to the analog output DACs DMA transfers to the DACs are always buffered by the DAC FIFO Programmed I O writes are routed either to the DACs or through the DAC FIFO by using the FIFO DAC bit If FIFO DAC is set programmed I O writes to the DACs are buffered by the DAC FIFO If FIFO DAC is cleared programmed I O writes to the DACs b
326. ts of your AT MIO 64F 5 kit the optional software and optional equipment and explains how to unpack the AT MIO 64F 5 Board Description Analog Input The AT MIO 64F 5 is a high performance multifunction analog digital and timing I O board for the The AT MIO 64F 5 has a 5 usec 12 bit sampling ADC that can monitor a single input channel or scan through the 64 single ended or 32 differential channels expandable with National Instruments multiplexing products at a programmable gain of 0 5 1 2 5 10 20 50 or 100 for unipolar or bipolar input ranges A 512 word ADC FIFO buffer can perform seamless data acquisition at the maximum rate without data loss Internal or external triggering and sampling are supported If signal conditioning or additional analog inputs are required you can use the SCXI signal conditioning modules SCXI multiplexer products or the AMUX 64T multiplexer board You can use the NI DAQ software included with the AT MIO 64F 5 to calibrate the analog input circuitry This software adjusts the offset and gain errors to zero by means of board level calibration DACs You can store calibration DAC constants resulting from the calibration procedure in the onboard EEPROM for later use See Chapter 6 Calibration Procedures for additional information on calibration procedures for the AT MIO 64F 5 Analog Output The AT MIO 64F 5 also has two double buffered multiplying 12 bit DACs that may be configured for a unipolar
327. ts related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax ___ Phone ___ Computer brand Model Processor Operating system Speed MHz RAM M Display adapter Mouse yes no Other adapters installed Hard disk capacity M Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps will reproduce the problem AT MIO 64F 5 Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products AT MIO 64F 5 Revision e Base I O Address of AT MIO 64F 5 Factory Setting hex 0220 DMA Channels of AT MIO 64F 5 e Interrupt Level of AT MIO 64F 5 e Input Configuration DIFF RSE or NRSE e NI DAQ or LabWindows Version Other Products Computer Make and Model e Microprocessor e Clock Frequency of Video Boar
328. tware gating of each counter is available Three state outputs for each counter provide either pulses or levels The Counters can be programmed to count or down in either binary or BCO The accumulated count may be read without disturbing the counting process Any of the counters may be internally concatenated to form an effective counter length of up to 80 bits The Am9513A block diagrams indicate the interface signals and the basic flow of information Internal control lines and the intemal data bus have been omitted The contro and data registers are connected to a common intemal 16 bit bus The external bus may be 8 or 16 bits wide in the 8 bit mode the internal 16 bit information is multiplexed to the iow order data bus pins DBO through 087 An intemal oscillator provides a convenient source of frequen cies for use as counter inputs The oscillator s frequency is controlled at the X1 and X2 interface pins by an external reactive network such as a crystal The oscillator output is divided by the Frequency Scaler to provide several sub frequencies One of the scaled frequencies or one of ten input signals may be selected as an input to the FOUT divider and then comes out of the chip at the FOUT interface pin The STC is addressed by the external system as two locations a Contro port and a Data port The Control port Figure 4 Counter Logic Groups 1 and 2
329. two TC events occur Within this interval the Gate input is ignored except for the retriggering option When repetition is selected a cycle will be repeated as soon as another Gate edge occurs With repetition selected any Gate edge applied after TC goes active will start a new count cycle Edge gating is useful when implementing a digital single shot since the gate can serve as a convenient firing trigger A 001 code in this field selects the TC not TOGGLE output from the adjacent lower numbered counter as the gate This is useful for synchronous counting when adjacent counters are concatenated COMMAND DESCRIPTIONS The command set for the Am9513A aliows the host processor to customize and manage the operating modes and features for particular applications to initialize and update both the data and control information and to manipulate operating bits during operation Commands are entered direct ly into the 8 bit Command register by writing into the Control port see Figure 6 available commands are described in the following text Figure 19 summarizes the command codes and includes a brief description of each function Figure 20 shows all the unused code combinations unused codes should not be entered into the Command register since undefined activities may occur Six of the command types are used for direct software control of the counting process and they each contain a 5 bit S field In a linear select fashi
330. uch or be in the way of any part of the AT MIO 64F 5 Attach a RTSI cable to the RTSI connectors to connect AT Series boards to each other 5 6 Screw the AT MIO 64F 5 mounting bracket of the to the back panel rail of the computer 7 Check the installation 8 Replace the cover The AT MIO 64F 5 board is installed and ready for operation Signal Connections This section describes input and output signal connections to the AT MIO 64F 5 board via the AT MIO 64F 5 I O connector This section also includes specifications and connection instructions for the signals given on the AT MIO 64F 5 I O connector The I O connector contains 100 pins that can be split into two standard 50 pin connectors via a cable assembly such as a NBS ribbon cable see Figure 1 2 One 50 pin connector contains signals associated with the generic MIO circuitry whereas the other 50 pin connector contains signals for extended analog input channels Figure 2 3 shows the pin assignments for the 100 pin primary AT MIO 64F 5 I O connector Figures 2 4 and 2 5 show the pin assignments for the 50 pin MIO subconnector and the 50 pin extended analog input subconnector The signal descriptions for pins 1 through 50 of the 100 pin primary connector are the same as those of the MIO subconnector pins and the signal descriptions for pins 51 through 100 of the 100 pin primary connector are the same as the extended analog input subconnector pins Warning Connections
331. ues while the first method requires one status register to be read per ADC FIFO read To service the data acquisition operation perform the following sequence until the data acquisition has completed 1 Read Status Register 1 16 bit read 2 If the OVERRUN or OVERFLOW bits are set the data acquisition sequence has been halted because one of these error conditions has occurred Clear the A D circuitry by writing to DAQ Clear Register and determine the cause of the error OVERRUN and OVERFLOW are explained in step 3 of the Programming the Analog Input Circuitry section earlier in this chapter 3 If the ADCFIFOEF bit is set or the ADCFIFOHF bit read ADC FIFO Register to obtain the result s Interrupts or DMA can also be used to service the data acquisition operation These topics are discussed later in this chapter Resetting the Hardware after a Data Acquisition Operation After a data acquisition operation terminates if no errors occurred and the sample count was less than or equal to 10000 hex the AT MIO 64F 5 is left in the same state as it was at the beginning of the data acquisition operation The counters do not need to be reprogrammed another data acquisition operation begins when a trigger is received If the next data acquisition operation requires the counters to be programmed differently the Am9513A counters that were used must be disarmed and reset Resetting a Single Am9513A Counter Timer To reset a parti
332. umes that CS is active when ever RD or WA are active CS may be held active indefinitely UT 13 This parameter assumes X2 is driven from an external gate with a square wave 14 This parameter assumes that the write operation is to the command register 15 This timing specification applies to single action com mands only e g LOAD ARM SAVE etc For doubie action commands such as LOAD AND ARM and DISARM AND SAVE TWHEH minimum 700 ns 16 short data write mode TWHRL and TWHWL mini mum 1000 ns 17 This parameter applies to the hardware retrigger save modes N and X CM7 1 and CM15 CM13 lt gt 000 This parameter ensures that the gating pulse initiates a hardware retrigger save operation 18 This parameter applies to hardware load source select modes S and V CM7 1 and CM15 CM13 000 This parameter represents the minimum hold time to ensure that the GATE input selects the correct load source on the active source edge Am9513A E 34 Appendix E National Instruments Corporation Appendix E AMD Am9513A Data Sheet SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise Note 1 C D C D Valid to Read Low ____________________________________ to Read Low ae Valid to Write Valid to Write High O mM PR Ra ep Xi low D Pues TCLCH Xj iow to X2 High X2
333. unter can be configured to count either falling or rising edges of the selected input The counter GATE input allows counter operation to be gated Once a counter is configured for an operation through software a signal at the GATE input can be used to start and stop counter operation The five gating modes available with the Am9513A are as follows No gating Level gating active high Level gating active low e Low to high edge gating e High to low edge gating National Instruments Corporation 3 21 AT MIO 64F 5 User Manual Theory of Operation Chapter 3 A counter can also be active high level gated by a signal at GATE N 1 and GATE N 1 where N is the counter number The counter generates timing signals at its OUT output pin The OUT output pin can also be set to a high impedance state or a grounded output state The counters generate two types of output signals during counter operation terminal count pulse output and terminal count toggle output Terminal count is often referred to as TC A counter reaches TC when it counts up or down and rolls over In many counter applications the counter reloads from an internal register when it reaches TC In TC pulse output mode the counter generates a pulse during the cycle that it reaches TC and reloads In TC toggle output mode the counter output changes state after it reaches TC and reloads In addition the counters can be configured for positive logic output or negative inverted logic
334. upt CL DAQCLEAR Figure 3 6 Single Channel Pretrigger Data Acquisition Timing The pretrigger sequence is programmed in much the same way as a posttrigger sequence The sample interval timer is programmed to generate conversion pulses under a gate signal and the sample counter is programmed to count the number of conversions The only difference between pretrigger and posttrigger sequences for all data acquisition modes is that the sample counter waits for a gating signal in the pretrigger mode before beginning the count For posttrigger sequences the sample timer is independent of the gating signal and for pretrigger sequences the sample timer is dependent on the gating signal Multiple Channel Data Acquisition Multiple channel data acquisition is performed by enabling scanning during data acquisition Multiple channel scanning is controlled by the configuration memory register The configuration memory register consists of 512 words of memory Each word of memory contains a multiplexer address for input analog channel selection a gain setting a mode setting single ended or differential and a range setting unipolar or bipolar Each word of memory also contains a bit for synchronizing scanning sequences of different rates a bit enabling serial data transmission of channel conversion data over the RTSI bus to the AT DSP2200 digital signal processing board and a bit indicating if the entry is the last in the scan sequence I
335. ure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17 Figure 3 18 Figure 3 19 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figures AT MIO 64P55 BOSE tests iet phot ae odo Pie ead 1 2 AT MIO 64F 5 Parts Locator Diagram eene 2 2 Example Base I O Address Switch Settings eee 2 3 gt 64 5 VO C ODBDeCtOf iei renti reete etti e pet oria pi 2 12 3D Pib MIO SUDCODIGCIOE tees etai predi ek ta Dni Vb e b ites 2 13 Extended Analog Input Subconnector eene 2 17 64 5 iatna iaai 2 19 Differential Input Connections for Ground Referenced Signals 2 22 Differential Input Connections for Nonreferenced Signals 2 23 Single Ended Input Connections for Nonreferenced or Floating Signals 2 25 Single Ended Input Connections for Ground Referenced Signals 2 26 Analog Output Connections us ouo se Eo Fu ao tese open aie 2 28 Digital WO Connect Ons s coucou iata 2 29 EXTSIROBE Signal Tinney aote ranae 2 30 EXICONV Signal Timing 2 31 EXT
336. ure of 25 C After the value of the reference is determined the value should be stored in the EEPROM so that it can be used by the input and output calibration routines The calibration procedure which determines the reference value is explained in the Reference Calibration section later in this chapter Locations have been provided in the EEPROM to accommodate user calibration constants see Figure 6 1 For best measurement results the AT MIO 64F 5 onboard reference needs to be measured to 0 012 120 ppm accuracy According to standard practice the equipment used to calibrate the AT MIO 64F 5 should be 10 times as accurate that is the equipment should have 0 001 10 ppm rated accuracy Practically speaking calibration equipment with four times the accuracy of the item under calibration is generally considered acceptable Four times the accuracy of the AT MIO 64F 5 is 0 003 30 ppm To redetermine the value of the reference on the AT MIO 64F 5 board you will need the following equipment A precision DC voltage source usually a calibrator Voltage 5 0 to 10 0 V Accuracy 0 001 10 ppm standard 0 003 30 ppm sufficient It is important to realize that inaccuracy of the internal voltage reference results only in gain error Offset error is unaffected If an application can tolerate slight gain inaccuracy there should not be a need to redetermine the value of the onboard reference Calibration DACs There are eight 8
337. us Scanning Data Acquisition Programming Setting the SCANEN bit in conjunction with the DAQEN bit in Command Register 1 enables scanning during multiple A D conversions The SCANEN bit must be set regardless of the type of scanning used continuous or interval otherwise only a single channel is scanned Interval Channel Scanning Data Acquisition Follow the programming steps listed in Figure 5 5 to program scanned multiple A D conversions with a scan interval pseudosimultaneous for posttrigger and pretrigger modes as well as internal and external timing The instructions in the blocks of the following flow chart are enumerated in the Data Acquisition Programming Functions section later in this chapter AT MIO 64F 5 User Manual 5 6 National Instruments Corporation Chapter 5 Programming Clear the A D circuitry Program multiple analog input channels gains modes and ranges Program the sample interval counter Program the sample counter Program the scan interval counter Enable an interval scanning data acquisition operation Apply a trigger Service the data acquisition operation Figure 5 5 Interval Scanning Data Acquisition Programming Setting the SCANEN bit in conjunction with the DAQEN bit in Command Register 1 enables scanning during multiple A D conversions The SCANEN bit must be set regardless of the type of scanning used continuous or interval otherwise only a single channel is scanned Nati
338. utput OUT1 OUTS D Data DBO DB15 National Instruments Corporation E 35 AT MIO 64F 5 User Manual AMD Am9513A Data Sheet Appendix E SWITCHING CHARACTERISTICS over MILITARY operating range for SMD DESC and APL Products Group A Subgroups 9 10 11 are tested uniess otherwise noted _ 513 Parameter Description pe es 25 ___ C D Valid to Read Low 5 Valid Write High ___ 1 _ X2 High io X2 High X2 Period Note 13 L3 le TcHcL X2 High to X2 Low X2 High Pulse Width Note 13 ds TCLCH X2 Low to X2 High X2 Low Pulse Width Note 13 _ ls TDVWH Dai Vaid torte High ___ _ Count Source High to Count Source High Source Cycle Time Note 7 FEB _ core sowon pua oan vn TEHFV ____ Count Source High FOUT Valid Note 7 ___ 99 s Count Source High to Gate Valid Level Gating Hold Time tere i e Oe vaa Tera Sara oa Teo Count Source High to Read Low Set up Time Notes 2 7 TEHWH Count Source High to Write High Set up Time Notes 3 7 100 ns meom CC Do e Comparator Output 390 FN High io FN 1 Valid Note 17 eraser Te Notes 7 9 10 TGVGV Gate Valid to Gate Vaid Gate Duration Notes 8 1 __ 6
339. utput DACS in cyclic waveform generation mode the following sequence of programming steps in Figure 5 7 must be followed The instructions in the blocks of the following flow chart are enumerated in the Waveform Generation Programming Functions section later in this chapter AT MIO 64F 5 User Manual 5 16 National Instruments Corporation Chapter 5 Programming Clear the analog output circuitry including the DAC FIFO Yes Set the A4RCV bit in Clear the A4RCV bit in Command Register 2 Command Register 2 Select the update counter via RTSI programming Program the update interval counter Set the waveform generation mode Enable updating Service update requests Figure 5 7 Cyclic Waveform Programming Programmed Cycle Waveform Generation A superset of the waveform functionality exists if DAC data buffer is less than or equal to 2 048 for one channel or less than or equal 1 024 per DAC for two channels In these cases the entire buffer resides wholly within the DAC FIFO where the waveform circuitry cycles through the buffer when the end is reached This removes a large burden on the PC bus for continually updating data in the DAC FIFO Also due to the smaller buffer size the hardware has more National Instruments Corporation 5 19 AT MIO 64F 5 User Manual Programming Chapter 5 control over the updating and cycling through of the buffer This enables the waveform circuitry to perform cycle counting programmed cycle generatio
340. ved Advanced Micro Devices Inc 1990 Data Book Personal Computer Products Processors Coprocessors Video and Mass Storage National Instruments Corporation 1 AT MIO 64F 5 User Manual AMD Am9513A Data Sheet 2 116 Am9513A System Timing Controller FINAL DISTINCTIVE CHARACTERISTICS Alarm comparators on counters 1 and 2 Programmable count gate source selection Programmable input and output polarities SMO DESC qualified GENERAL DESCRIPTION The Am9513A System Timing Controller is an LSI circuit designed to service many types of counting sequencing and timing applications It provides the capability tor pro grammable frequency synthesis high resolution program duty cycle waveforms retriggerable digital one puise generation high resolution baud rate generation frequency shift keying stop watching timing event count accumulation waveform analysis etc A variety of program operating modes and control features allows the 9513 to be personalized for particular applications as well as dynamically reconfigured under program control The STC includes five general purpose 16 bit counters variety of internal frequency sources and external pins may be selected as inputs tor individual counters with software selectable active high or active low input polarity Both hardware and software gating of each counter is available Three state outputs for each counter
341. w if CM2 1 When the high impedance option is selected and the comparator is enabled the status register bit will reflect an active high comparator output When the low impedance to Ground option is selected and the comparator is enabled the Status register bit will reflect an active low comparator output The Status register is normally accessed by reading the Control port see Figure 6 but may also be read via the Data port as part of the Control Group POINTER DFO01900 Figure 10 Status Register Bit Assignments DATA PORT REGISTERS Counter Logic Groups As shown in Figures 4 and 5 each of the five Counter Logic Groups consists of a 16 bit general counter with associated control and output logic a 16 bit Load register a 16 bit Hold register and a 16 bit Mode register In addition Counter Groups 1 and 2 aiso include 16 bit Comparators and 16 bit Alarm registers The comparator alarm functions are con trolled by the Master Mode register The operation of the Counter Mode registers is the for all five counters The host CPU has both read and write access to all registers in the Counter Logic Groups through the Data The counter itself is never directly accessed Load Register The 16 bit read write Load register is used to control the effective length of the general counter Any 16 bit value may be written into the Load register That value can then be transferred into the counter each time the Terminal Count T
342. w or TC Toggle output wavetorms One output form available is called Terminal Count TC and represents the period in time that the counter reaches an equivalent value of zero TC will occur on the next count when the counter is at 0001 for down counting at 9999 BCD for BCD up counting or at FFFF hex for binary up counting Figure 18 shows a Terminal Count pulse and an example Context that generated it The TC width is determined by the period of the counting source Regardless of any gating input or whether the counter is Armed or Disarmed the termina count will go active for only one clock cycle Figure 18 assumes active high source polarity counter armed counter decrementing an external reload value of The counter will always be loaded from an external location when TC occurs the user can choose the source location and the value If a non zero value is picked the counter will never really attain a zero state and TC will indicate the counter state that would have been zero had no parallel transfer occurred Am9513A E 26 Appendix E National Instruments Corporation Appendix E 3883888 3 al 114548 0 o af AMD Am9513A Data Sheet iil i FIT iiu i IT i 100 inactive Output High Impedance 101 Active Low Termina Count Pulse 110 legal 111 DF003784 Note See Figure 15 for restrictions on Count Co
343. when the unit is operating with an external 8 bit data bus See Data Bus description Schmitt trigger circuitry on the GATE inputs allows slow transition times to be used Source The Source inputs provide external signals that may be counted by any of the counters Any Source line may be routed to any or all of the counters and the FOUT divider The active polarity tor a B selected SRC input is programmed at each counter Any duty cycle waveform will be accepted as long as the minimum pulse width is at least half the period of the maximum specified counting frequency for the part Schmitt trigger circuitry on the SRC inputs allows siow transition times to be used OUT1 OUTS Counter Each 3 state OUT signal is directly associated with a corresponding individual counter Depending on the counter configuration the OUT signal may be a pulse a square wave or a complex duty cycle wavelorm OUT puise polarities are individually programmable The output circuitry detects the counter state that would have been ail bits zero the absence of reinitialization That information is used to generate the selected waveform type An optional output mode for Counters 1 and 2 overrides the normai output mode and provides a true OUT signal when the counter contents match the contents of an Alarm register 080 087 Data Bus The 16 bidirectional Data Bus lines are used for information exchanges with the host processor 0815 HIGH on a Data Bus line corre
344. where is the signal at the positive input of the and V is the signal at the negative input of the PGIA Both Vt and V are measured with respect to AI GND Analog Output Signal Connections Pins 20 through 23 of the MIO subconnector are analog output signal pins Pins 20 and 21 of the MIO subconnector are the DACO OUT and DACI OUT signal pins OUT is the voltage output signal for analog output Channel 0 DAC1 OUT is the voltage output signal for analog output Channel 1 Pin 22 of the MIO subconnector EXTREF is the external reference input for both analog output channels Each analog output channel must be configured individually for external reference selection in order for the signal applied at the external reference input to be used by that channel Analog output configuration instructions are in the Analog Output Configuration section earlier in this chapter The following ranges and ratings apply to the EXTREF input Normal input voltage range 10 V peak with respect to AO GND Usable input voltage range 12 V peak with respect to AO GND Absolute maximum ratings 30 V peak with respect to AO GND Pin 23 of the MIO subconnector AO GND is the ground reference point for both analog output channels and for the external reference signal Figure 2 11 shows how to make analog output connections and the external reference input connection to the AT MIO 64F 5 board National Instruments Corporation 2 27
345. will be no gaps or missed points in the output waveform If a point is missed for any reason the waveform circuitry will automatically stop updating the DAC and a waveform error signal will be generated that can be monitored in Status Register 1 An error condition or underflow occurs when data is extracted from the DAC FIFO faster than it enters such that at one point the DAC FIFO becomes empty Underflow errors occur because of software or hardware latencies in acknowledging the signal requesting more data for the DAC FIFOs This condition can be prevented in the cyclic mode where the buffer resides wholly in the DAC FIFO and is cycled through to generate a continuous waveform The advantage of having the data in the DAC FIFO is that the FIFO never needs to have the data refreshed therefore it is never empty Rather than requesting new data the FIFO simply reuses existing data removing a large demand on the PC bus bandwidth Maximum updating performance is achieved in this mode because it does not rely on the speed of the computer All described waveform modes involving cycling within the DAC FIFO can also be accomplished without the entire buffer fitting inside the FIFO However this requires more software intervention and therefore results in a slower rate and decreased reliability FIFO Continuous Cyclic Waveform Generation In addition to allowing better performance the cyclic mode provides greater flexibility Because the hardware is in
346. ws Vout Vref digital code 2 048 National Instruments Corporation 4 31 AT MIO 64F 5 User Manual Register and Descriptions Chapter 4 where is the positive reference voltage applied to the analog output channel The digital code in the preceding formula is a decimal value ranging from 2 048 to 2 047 Table 4 11 Analog Output Voltage Versus Digital Code Bipolar Mode Digital Code Voltage Output Hex Reference 10 V Bit descriptions for the registers making up the Analog Output Register Group are given on the following pages AT MIO 64F 5 User Manual 4 32 National Instruments Corporation Chapter 4 Register and Descriptions DACO Register Writing to the DACO Register loads the value written to the analog output DAC channel 0 in immediate update mode If posted update mode is used the value written to the DACO Register is buffered and updated to the analog output DAC channel 0 only after an access to the DAC Update Register or a timer trigger is received in one of the prescribed paths Address Base address 10 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 12 X Don t care bits 11 0 D lt 11 0 gt Data bus to the analog output DACs The data written to the DACs is interpreted in straight binary form when DAC channel 0 is configured for unipolar operation When DAC channel 0 is configured for bipolar operation the
347. y for the proper sequencing of events Still other registers perform functions by accessing them either by reading from or writing to their location However these registers do not retain pertinent data when written to nor do they provide pertinent status information when read The PC defines accesses to plug in boards to be I O mapped accesses within the I O space of the computer Locations are either written to or read from as bytes or words Each register in the register set is mapped to a certain offset from the base address selection of the board as read or write and as a word or byte location as defined by the decode circuitry Base I O Address Selection The AT MIO 64F 5 is configured at the factory to a base I O address of 220 hex This base address setting is suitable for most systems However if your system has other hardware at this base I O address you must change either the AT MIO 64F 5 base address DIP switch or the other hardware base address to avoid a conflict Figure 2 2 shows a graphical representation of the base address selection DIP switch and also shows how to reconfigure the selected base address 1 2 3 4 5 Switch up for 1 Switch down for 0 o o 5 lt lt lt lt A Switches Set to Base I O Address of Hex 000 U104 1 2 3 4 5 Switch up for 1 Switch down for 0 Ov NOON lt lt lt lt lt B Switches Set to Base I O Address of Hex 220 Factory Setting Figure 2 2 Example Base
348. ypass the DAC FIFO and are transmitted directly to the DACs External Trigger Disable This bit gates the EXTTRIG signal from the I O connector If EXTTRIG DIS is set triggers from EXTTRIG are ignored by the AT MIO 64F 5 circuitry If this bit is cleared triggers from the EXTTRIG signal are able to initiate data acquisition sequences 4 18 National Instruments Corporation Chapter 4 Register and Descriptions Status Register 1 Status Register 1 contains 16 bits of AT MIO 64F 5 hardware status information including interrupt analog input status analog output status and data acquisition progress Address Base address 4 18 hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 MSB 7 6 5 4 3 2 1 0 TMRREQ DACCOMP DACFIFOFF DACFIFOHF DACFIFOEF EEPROMDATA EEPROMCD CFGMEMEF LSB Bit Name Description I5 DAQCOMP Data Acquisition Complete This bit reflects the status of the data acquisition termination signal If DAQCOMP is set and either OVERFLOW or OVERRUN is also set the current acquisition sequence ended on an error condition If DAQCOMP is set and neither OVERFLOW nor OVERRUN is set the data acquisition operation has completed without error When DAQCOMP is set and ADCREQ in Command Register 3 is also set enabled interrupt or DMA requests are generated until the ADC FIFO is empty DAQCOMP is cleared by strobing the DAQ Clear Register 14 DAQPROG Data Acquisition Progre
349. ypes of Signal Source AREIS n ERE ERR a eR ee 2 20 Bloating Signal SOUEIGGS door eminent geiler Des ee ke site gnus 2 20 Ground Referenced Signal Sources sene 2 20 Input C Ong uFatlOfis scc 2 20 Differential Connection Considerations DIFF Input Configuration 2 21 Differential Connections for Ground Referenced Signal Sources 2 22 Differential Connections for Nonreferenced or Floating Signal Mu PES 2 23 Single Ended Connection Considerations esses 2 24 Single Ended Connections for Floating Signal Sources RSE niic I Mp E 2 25 National Instruments Corporation ix AT MIO 64F 5 User Manual Contents Single Ended Connections for Grounded Signal Sources NRSE Configuration duces 2 26 Common Mode Signal Rejection Considerations 2 26 Analog Output Signal 5 cons vs we en 2 27 Digital I O Signal Connections Dae ite tta era an 2 28 Power Connections o get Ce depu UT 2 30 Timing Connections e se ME ove Ru ae 2 30 Data Acquisition and Analog Output Timing Connections 2 30 General Purpose Timing Signal Connections es

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