XEM3001v2 User`s Manual
Contents
1. A mechanical drawing of the XEM3001 is shown below Dimensions are mils 1mil 0 001 un less otherwise noted oO 800 00 3 00mm 200 00 3 me 0000000000088 HH 0000000000880 88 000o o IVOREAIENVSQAQQQNVQG0Q0008 a Q i aie UAENUVEGAIAVVOEQINGONIEGH Pa 23 e oo J 88 me e S E ee g Me io CE e e un 500 J 3200 00 mil gt 3500 00 mil www opalkelly com 5 XEM300102 User s Manual The PCB is 3 5 x 2 0 88 9mm x 50 8mm with four mounting holes spaced as shown in the figure These mounting holes are electrically connected to the ground plane The three FPGA access ports JP1 JP2 and JP3 are located on a 0 1 grid so that the entire board may be attached to a standard prototyping board The JTAG header JP4 is also on this grid Functional Block Diagram 1 PLL CLK PESEE gt XBUS JP3 36 1 0 1 GCLK 141 0 N 2 GCLK N Host Interface Spartan 3 FPGA oa 5s XC3S400 4PQ208 3 PLL CLKs 12 1 0 CY22150 i 4 Pushbuttons 1 PLL CLK 361 0 1 GCLK 8 LEDs ee YBUS JP2 Power Supply The XEM3001 is a bus powered device in its default configuration J1 jumper inserted That is it takes power from the 5 V USB power and generates the voltages it needs from there To do so the XEM3001 has small linear regulators for 3 3 V 2 5 V and 1 8 V External power may be applied to any of the 3 3 V pins on JP1 JP2 or JP3 as long as the J1 jumper is removed2. 6 www opalkelly com XEM300102 User s Manual WARNING For use in bus powered mode always insert jumper J1 BEFORE connecting the device to the USB USB 2 0 Interface The XEM3001 uses a Cypress CY68013 FX2 USB microcontroller to make the XEM a USB 2 0 peripheral As a USB peripheral the XEM is instantly recognized as a plug and play peripheral on millions of PCs More importantly FRGA downloads to the XEM happen blazingly fast virtual instruments under FrontPanel update quickly and data transfers are much faster than the parallel port interfaces common on many FPGA experimentation boards The USB interface also allows the XEM to be bus powered which means it is ultra portable requiring just a USB cable and the proper drivers to connect to any supporting PC including laptops On board Peripherals The XEM3001 is designed as a low cost barebones device However a few key peripherals have been added for convenience EEPROM A small serial EEPROM is attached to the USB microcontroller on the XEM3001 but not directly available to the FPGA The EEPROM is used to store boot code for the microcontroller as well as PLL configuration data and a device identifier string The PLL configuration data is loaded from EEPROM and used to reconfigure the PLL each time a new configuration file is loaded to the FPGA Therefore stable and active clocks will be pres ent on the FPGA pins as soon as it comes out of configuration The stored PLL confi
3. by Opal Kelly s FrontPanel software FrontPanel augments the limited peripheral support with a host of PC based virtual instruments such as LEDs hex displays pushbuttons toggle buttons and so on Essentially this makes your PC a reconfigu rable I O board and adds enormous value to the XEM3001 as an experimentation or prototyping system Programmer s Interface In addition to complete support within FrontPanel the XEM3001 is also fully supported by the FrontPanel programmer s interface API a powerful C class library available to Windows and Linux programmers allowing you to easily interface your own software to the XEM In addition to the C library wrappers have been written for Java and Python making the API available under those languages as well Java and Python extensions are available under Win dows and Linux Complete documentation and several sample programs are installed with FrontPanel 8 www opalkelly com XEM300102 User s Manual FPGA Pin Connections Host Interface There are 24 pins that connect the on board USB microcontroller to the FPGA These pins com prise the host interface on the FPGA and are used for configuration downloads After configura tion these pins are used to allow FrontPanel communication with the FPGA If the FrontPanel okHostInterface module is instantiated in your design you must map the in terface pins to specific pin locations using Xilinx LOC constraints This may be done usin
4. 7 s Opal Kelly ee _ DA 566 oe seine ABj0 6 OS XEM3001v2 User s Manual A business card sized 3 5 x 2 0 experimentation board featuring the Xilinx Spartan 3 FPGA 50o 000900022 The XEM3001 is a small business card sized FPGA board featuring the Xilinx Spartan 3 FPGA De signed as a bare bones system the XEM3001 is an excellent experimenting or prototyping system which provides access to nearly all I O pins on the 208 pin Spartan 3 device The USB 2 0 interface provides fast downloads and easy access with FrontPanel software An on board PLL provides flexible clock generation for a variety of applications and on board pushbuttons and LEDs allow simple user interfacing when FrontPanel components don t suit the purpose Dozens of pins at 0 1 spacing are provided and easily fit onto a standard prototyping board with 0 1 hole spacing Software documentation samples and related materials are Copyright 2005 2014 Opal Kelly Incorporated Opal Kelly Incorporated Portland Oregon http www opalkelly com All rights reserved Unauthorized duplication in whole or part of this document by any means except for brief excerpts in published reviews is prohibited without the express written permission of Opal Kelly Incorporated Opal Kelly the Opal Kelly Logo and FrontPanel are trademarks of Opal Kelly Incorporated Linux is a registered trademark of Linus Torvalds Microsoft and Windows are both regi
5. In this case the 5 V USB power is not used and the device consumes no bus current Computers and USB hubs often have USB ports that do not provide bus power These are called unpowered ports In order to be operated as a bus powered device the XEM3001 must be connected to a USB port that provides bus power You should check with the hub or computer manufacturer to verify that the port provides bus power The XEM3001 may also be self powered by removing jumper J1 This jumper connects the 3 3 V regulator to the 3 3 V supply plane on the board By removing this jumper the 3 3 V supply and therefore the derived 2 5 V and 1 8 V supplies are disconnected from bus power 3 3 Volts must be supplied externally either to the device side of the jumper the pin closer to the U1 marking or to one of the 3 3 V pins on JP1 JP2 or JP3 IMPORTANT NOTE Under normal operating conditions and with an unconfig ured FPGA the XEM3001 draws approximately 125 mA from the 3 3 V node FPGA current draw is impossible to predict because it strongly depends on the implemented design and clocking rates Current requirements of the FPGA can be estimated using Xilinx power estimation tools and should be considered if you think you may be getting close to USB limits The current can easily be mea sured by removing the J1 jumper and placing a current meter across the leads If you need to exceed the 500 mA limit make sure to apply external power and remove J1
6. ation Dialog you can configure the clock signal present on this pin JP3 is a 50 pin dual row 100 mil header providing access to FPGA Banks 2 and 3 Several pins of this header are dedicated to power supply 3 3VDD and DGND Pin 47 of this header is con nected to a global clock input on the FPGA and can therefore be used as an input to the global clock network Pin 48 on this header is SYSCLK4 and is directly connected to LCLK4 pin 12 on the Cypress CY22150 PLL Using FrontPanel s PLL Configuration Dialog you can configure the clock signal present on this pin www opalkelly com XEM300102 User s Manual Mechanical Drawing 2 000 aa 1 900 1 850 1 300 0 970 R y 0 800 rie 7 do 4 3 0 150 ro Be 09 0 150 0 750 2 590 3 150 _ 3 350 All dimensions are in inches www opalkelly com 13
7. g the Xilinx constraints editor or specifying the constraints manually in a text file An example is shown below Xilinx constraints for okHostInterface pin mappings www opalkelly com 9 XEM3001v2 User s Manual hi in lt gt hi in lt 1 gt hi in lt 2 gt hi in lt 3 gt hi in lt 4 gt hi in lt 5 gt hi in lt 6 gt hi in lt 7 gt hi_out lt gt hi_out lt 1 gt hi inout lt gt hi inout lt 1 gt hi inout lt 2 gt hi inout lt 3 gt hi inout lt 4 gt hi inout lt 5 gt hi inout lt 6 gt hi inout lt 7 gt hi inout lt 8 gt hi inout lt 9 gt hi inout lt 10 gt hi inout lt 11 gt hi inout lt 12 gt hi inout lt 13 gt hi inout lt 14 gt hi inout lt 15 gt P79 lai P58 P78 P61 P62 P63 P64 ipei P85 ERE P68 P724 p742 P86 P87 P90 P92 P93 P94 P95 P96 P97 P100 P101 P102 Each of the samples installed with FrontPanel includes a copy of a template constraints file that lists all the XEM3001 pins and maps them to the appropriate FPGA pins using LOC location constraints You can use this template to quickly get the pin locations correct on a new design LEDs and Pushbuttons There are eight LEDs and four pushb
8. guration may be changed at any time using FrontPanel s PLL Configuration Dialog The EEPROM also stores a device identifier string which may be changed at any time using FrontPanel The string serves only a cosmetic purpose and is used when multiple XEM devices are attached to the same computer so you may select the proper active device Cypress CY22150 PLL A multi output single VCO PLL can provide up to five clocks three to the FPGA and another two to the expansion connectors JP2 and JP3 The PLL is driven by a 48 MHz signal output from the USB microcontroller The PLL can output clocks up to 150 MHz and is configured through the FrontPanel software interface or the FrontPanel API LEDs and Pushbuttons Eight LEDs and four pushbuttons are available for general use as debug inputs and outputs Expansion Connectors Three 0 1 spaced expansion connectors JP1 JP2 JP3 are available to connect the XEM to your devices These connectors provide 3 3v power ground PLL outputs and 88 FPGA pins for general I O All expansion connectors are on a 0 1 grid so that the entire XEM can piggy back onto a standard 0 1 PCB protoboard www opalkelly com 7 XEM300102 User s Manual NOTE The expansion connectors are not installed at the factory to provide you the flexibility of installing your choice of expansion directly soldering wires or using stacking or right angle connectors FrontPanel Support The XEM30071 is fully supported
9. modules It provides additional information on pin capabilities pin character istics and PCB routing Additionally Pins provides a tool for generating constraint files for place and route tools Pins can be found at the URL below O http www opalkelly com pins JP4 JTAG Connector JP1 JP4 is the 8 pin JTAG connector on board and is connected only to the FPGA These pins can be connected to an external JTAG command converter such as the Xilinx JTAG cables for addi tional programming capability The JP4 pins are connected as shown below JPapin Signal e ho s mo JP1 is a 20 pin dual row 100 mil header four pins of which are dedicated to power supply The other 16 pins connect directly to the Spartan 3 on Banks 0 and 1 Pins 17 and 18 of the header www opalkelly com 11 XEM300102 User s Manual 12 JP2 JP3 connect to global clock pins on the FPGA and can therefore be used as clock inputs to the inter nal clock network All 16 FPGA pins may be used as general purpose input output JP2 is a 50 pin dual row 100 mil header providing access to FPGA Banks 6 and 7 Several pins of this header are dedicated to power supply 3 3VDD and DGND Pin 4 of this header is con nected to a global clock input on the FPGA and can therefore be used as an input to the global clock network Pin 3 on this header is SYSCLK5 and is directly connected to LCLK5 pin 14 on the Cypress CY22150 PLL Using FrontPanel s PLL Configur
10. stered trademarks of Microsoft Corporation All other trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed Revision History Date Description S 20040901 Initial release 20041103 Added PLL and JTAG JP4 connections 20050315 Changes for XEM3001v2 20050420 Updated mechanical drawing 20140330 Replace pin list tables with reference to Pins Introducing the XEM3001 PCB Footprint Functional Block Diagram Power Supply USB 2 0 Interface On board Peripherals EEPROM Cypress CY22150 PLL LEDs and Pushbuttons Expansion Connectors FrontPanel Support Programmer s Interface FPGA Pin Connections Host Interface LEDs and Pushbuttons PLL Connections Expansion Connectors JP4 JTAG Connector Contents XEM300102 User s Manual 4 www opalkelly com XEM300102 User s Manual Introducing the XEM3001 The XEM3001 is a small business card sized 3 5 x 2 0 FPGA board featuring the Xilinx Spar tan 3 FPGA Designed as a full featured starter system the XEM3001 provides access to nearly all I O pins on the 208 pin Spartan 3 device The XEM3001 is ideally suited to experiments based on the FrontPanel virtual instrumentation platform integration into prototype development or as a quick and easy way to add USB capability to an existing device PCB Footprint
11. uttons on the XEM3001 Each is wired directly to the FPGA as shown in the tables below Ds pe C Button FPGAPin The LED anodes are connected to a pull up resistor to 3 3VDD and the cathodes wired directly to the FPGA To turn ON an LED the FPGA pin should be brought low To turn OFF an LED the FPGA pin should be brought high The pushbuttons are connected between their respective FPGA pin and DGND The FPGA side of the connection has a pull up resistor to 3 3VDD Therefore in the pressed state the FPGA pin will be at DGND low and in the unpressed state the FPGA pin will be at 3 3VDD high Note that the pushbuttons are not debounced on the XEM3001 In order to deglitch the signals from the pushbuttons proper debouncing should be done inside the FPGA 10 www opalkelly com XEM300102 User s Manual PLL Connections The PLL contains six output pins one of which is left unconnected The other five are labelled SYS_CLK1 through SYS_CLK5 SYS_CLK4 connects to JP3 and SYS_CLK5 connects to JP2 The other three pins are connected directly to the FPGA The table below illustrates the PLL connections PLLPin Clock Name LCLK1 SYS_CLK1 FPGA P80 LCLK2 SYS_CLK2 FPGA P77 ce wai Expansion Connectors The XEM3001 has locations for three expansion connectors in addition to a JTAG connector Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration
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