IE-703242-G1-EM1 In-Circuit Emulator Option Board for V850ES
Contents
1. 24 2421 MAin SOCKEIS des oed anne eed De Lo atta 24 2 4 2 Clock Connectors 24 2 4 3 Other 24 2 5 Clock Operation 25 2 5 1 ECC e tht ra oet e Lon ated ond oe he ane 25 2 5 2 Sub Clock Rea e DD HERE AUAM aye 26 Chapter3 Operating 29 3 1 Reset source monitor 29 3 2 Standby release ee ee 29 3 3 Port direction setting for peripheral function 29 3 4 Programmable peripheral area 29 3 5 Other precautions eee eee Mee ee ete ieee ad 29 Chapter 4 Differences between Target Device and Emulation Board 31 41 BCU bus control 31 4 2 Load on voltage supply 31 4 3 Reset input rarae lll Ae ee te ee ee ee 31 4 4 REGC pim i27 ee cia ues ei Aa 31 4 5 Clock oscillator 31 4 6 Vpp pin WR NR RC RON CR2. X9 ae 4 N gt e gt 5 1 703242 1 SS 71235 01 TP1 Anti Stotic 5 i 3v i TP26 rao 182 9 T 10 00 52 00 B4 pm 112 50 E 8 195 00 E rm 205 00 Preliminary Users Manual U16345EE1VOUMOO 35 MEMO 36 Preliminary User s Manual U16345EE1VOUMOO Appendix B Index A AVDD pini veu fei ub ecu 32 AVDD Selectlol iore te ite oho Turca bci Ede eh i aH 22 PAN SS PIN tre ec a D etate Pues esee Lope a C A Sag o Dade 32 AV SS selection 4 4s ds eode dec ideis deg Aude xu id arc s 23 B BCU bus control unit 31 BPG tegisterz s et igit ed E 29 clock CONMOCIOMS E Ro ed ime dared ee ee a D RE d gen 24 25 SUD Glocke 4a tice tee a Rap 26 clock oscillator inputs 1 31 du eset ea aut dod op Meca Seo aa os io OE d 24 d Ud A Erico Te en 24 urea RA EE atii ac e E aw Voss t PO te 24
3. Don t care internal use only Target power on Nete Main Power on Note See2 4 Main Sockets and Connectors for target power switching Preliminary Users Manual U16345EE1VOUMOO 21 Chapter 2 Name and Functions of Components 2 3 Jumper Settings This chapter describes the function of the jumpers used to configure the IE 703242 G1 EM1 2 3 1 Overview The following table sums up the jumpers and connectors used to configure the IE 703242 G1 EM1 for the desired operation Table 2 2 Component Overview Component Function Described in JP1 Select sub clock signal generated by timer circuit Clock Connectors JP2 AVpp input voltage selection Jumper JP2 AVDD selection JP3 AVss input voltage selection Jumper JP3 AVSS selection SO1 Socket for alternative main clock oscillator Clock Connectors SO2 Socket for target connection Main Sockets CN1 CN2 CN3 Connection to IE V850ES G1 emulator Main Sockets Socket for main clock crystal and capacitors Clock Connectors Socket for sub clock crystal and capacitors Clock Connectors Internal use don t press SW3 Internal use don t press 2 3 2 Jumper JP2 AVpp selection This function is used to select the input signal for the AVpp pin of the I O chip on the IE 703242 G1 EM1 emulation board Table 2 3 Jumper JP2 AVpp selection 1 2 default Connect AVpp to target 2 3 Connect AVpp to internal buffered 5 V supply
4. 24 CNG se qu a a OG aver OM aede el aoa ed he 24 configuration hardware 1 4 11 connection emulation board IE V850ES G1 17 D diferentes doe eee een EE ne he Se tan GG ais Shen a ea o usps 31 diIMENSIONS ERE Uv Aree a 13 E emulationjDOard ware ned IURE NR Wee Ra waa PN ERR Paden 12 F frequency operation frequency 4 13 H humidity environmental humidity 13 IE 70000 CD IESA cz rh ERI REL Sable Ree ee eel es 12 IE 70000 MC SV3 2 12 70000 ad op Ba edes ee etd bd es dO 12 IE 703242 GS EMIT eh eed hr bea 12 IE V850ESsQ lias aban teen tanita ees um he axe 12 1 12 interface network interface Card 12 PG interface card oce a RS din ed ead a bue des a a EN 12 J Pl
5. 1 3 Features When Connected to IE V850ES G1 Table 1 2 Features of IE 703242 G1 EM1 Parameter Value Operation frequency max 16 MHz Main clock Operation Temperature range 0 to 40 C Storage temperature range 15 to 60 C Environmental humidity range 10 80 RH Supply voltage 4 5 V to 45 5 V 596 Supply current 300 mA Power dissipation 1W Q 16 MHz Weight 300g Dimensions Nete 205 mm x 140 mm x 20 mm Note Please refer to the appendix Mechanical data Preliminary Users Manual U16345EE1VOUMOO 13 Chapter1 Overview 1 4 Function Specifications When Connected to IE V850ES G1 Table 1 3 Functional Specifications of IIE 703242 G1 EM1 Parameter Specification Internal ROM 1 Emulation memory capacity User memory 4 MB Coverage memory capacity Internal ROM 256 KB for execution pass detection External memory 1 MB Coverage memory capacity External memory 1 MB for memory access detection Coverage memory capacity Internal ROM 256 KB for branching entry number counting External memory 1 Trace memory capacity 168 bits x 32 K frames Time measurement function On chip timer 3 8 bit external trace possible External logic probe Event setting for trace break possible Event break Step execute break Forced break Break function Fail safe break Illegal access to peripheral I O Access to guard sp
6. NEC Preliminary User s Manual IE 703242 G1 EM1 In Circuit Emulator Option Board for V850ES GB1 Hardware Documen t No U16345EE1VOUMOO Date Published July 2002 NEC Corporation 2002 Printed in Germany NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field wnen exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices
7. 8 oe ve 22 o 0 21 19g _Be c E 5 C53 od Hh o 9 1 8 so aa 200 5 2 C29 660 5 vw C30 C96 Z 071 2 v o m a OTP os o 5 R34 MRO Pu C10 1047 R35 ET 09 97 o is icis 2 23 P ad 1025 8 re cao M J BC 4 787 5 L 3 MRE J T J 1C14 ee o L s a e EE C93 URS 1 1 SS 1 5 9 R32 2 a 8 87 E S OON x 2 z a 5 i S 2 Ls C48 75 A is og Fc2 1021 9 Eo ell 10 20 amp 202285 2 g 2 C54 104 Icio 2 8 oz e g Bl n S i 8 2 x C sg s ave i 2 8 jc 8 o i Preliminary User s Manual U16345EE1VOUMOO Chapter 2 and Functions of Components 2 2 Status LEDs Some of the LEDs of IE V850ES G1 are controlled by IE 703242 G1 EM1 to output status information Refer to the IE V850ES G1 User s Manual for information on the LEDs controlled by the IE V850ES G1 itself Figure 2 3 LEDs controlled by IE 703242 G1 EM1 TRG EXTD LED1 LED2 LED3 LED4 _ LEDS5 OC CoO Remark For information about external trigger inputs and output refer to IE V850ES G1 User s Manual Table 2 1 LEDs controlled by IE 703242 G1 EM1 Colour Function Target reset Don t care internal use only
8. Specifications of 703242 61 14 LEDs controlled by 703242 61 21 Component 22 Jumper JP2 AVpp selection 22 Jumper selection 23 iE 24 Clock Connectors 24 Pin list according to their emulation location 32 Preliminary Users Manual U16345EE1VOUMOO 9 10 Preliminary User s Manual U16345EE1VOUMOO Chapter1 Overview The IE 703242 G1 EM1 is an option board for the IE V850ES G1 in circuit emulator Using the IE 703242 G1 EM1 in conjunction with the IE V850ES G1 hardware and software developed for V850ES GB1 can be debugged efficiently This manual describes the basic setup procedure and configuration settings of the 850 5 1 when used together with IE 703242 G1 EM1 1 1 Hardware Configuration Figure 1 1 IE 703242 G1 EM1 hardware configuration Additional 5 Hardware Probe cable General purpose extension probe cable SWEX 100SD1 for target connection For use as emulation system for V850ES GB1 connect this board to the In Circuit Emulator IE V850ES G1 Additional Hardware In Circuit Emulator IE V850ES G1 Emulation board IE 703242 G1 EM1 For connection of the IE V850ES G1 to PC Interface Card a PC Insert to the resp
9. a timer circuit provided on the emulation board can be used for the sub clock See also 2 5 Clock Operation 4 6 Vpp pin Vpp pin of the I O chip on the emulation board is connected to the target connector with a load of 10 KQ series resistor On the emulation board it is only monitored and not used internally Correct connection on the target board must be assured Preliminary Users Manual U16345EE1VOUMOO 31 Chapter 4 Differences between Target Device and Emulation Board 4 7 AVpp AVss pins and pins of the I O chip on the emulation board be disconnected from the target con nector ADC values and the load on AVpp and AVss pins may differ in that case Table 4 1 Pin list according to their emulation location 1 3 woen Fue Shifter 1 AVpp AVpp Venus internal 2 AVss AVss Venus internal POO INTPO Venus 4 P01 P01 INTP1 Venus 5 P02 PO2 INTP2 Venus 6 Venus 7 P04 PO4 INTP4 Venus 8 5 PO5 INTP5 Venus 9 Vppso Vppso S buffered 10 REGCO REGCO S not connected 11 Vssso 5 0 S Ground 12 X1 X1 not connected 13 X2 X2 not connected 14 RESET buffered 15 XT1 XT1 not connected 16 2 XT2 not connected 17 NMI Venus 18 6 6 V
10. the emulator behaves like the real chip in the target system Small differences occur however This chapter lists differences between the emulation system and the V850ES GB1 4 1 BCU bus control unit The BCU is established within an FPGA Therefore this could be slightly different to the real chip 4 2 Load on voltage supply pins The I O chip is supplied by a power supply the emulation board Therefore the load on the power supply of the target board is very low compared to the real chip 4 3 Reset input The reset pin of the target connector is not connected to the reset pin of the I O chip directly It also has got a 10 KO pull up resistor connected to it The input characteristic differs from the real chip 4 4 REGC pin The REGC pin of the target connector is not connected to the corresponding pin of the I O chip On the emulation board a capacitor is connected to the REGC pin of the I O chip internally 4 5 Clock oscillator inputs The pins for main clock connection X1 and X2 as well as the pins for sub clock connection CL1 CL2 XT1 XT2 of the I O chip on the emulation board are not connected to the target connector If a crystal is to be used for the clock generator it must be connected to the respective connector on the emulation board which is located electrically close to the I O chip Crystal operation from the target board is not possible Alternatively a dedicated C MOS oscillator can be used for the main clock and
11. 22 Preliminary User s Manual U16345EE1VOUMOO Chapter 2 Name and Functions of Components 2 3 3 Jumper selection This function is used to select the input signal for the AVgg pin of the I O chip on the IE 703242 G1 EM1 emulation board Table 2 4 Jumper AVss selection Position Function 1 2 default Connect AV gs to target 2 3 Connect AVgg to GND Preliminary Users Manual U16345EE1VOUMOO 23 Chapter 2 Name and Functions of Components 2 4 Main Sockets and Connectors This chapter describes the main sockets and connectors of the IE 703242 G1 EM1 This includes sockets for connection to the IE V850ES G1 emulator and connections to a target board as well as connectors used for clock selection and configuration 2 4 1 Main Sockets The main sockets described here are used for proper installation of the IE 703242 G1 EM1 in the IE V850ES G1 emulator and for connection of a target board when the emulator is connected to external hardware Table 2 5 Main Sockets Socket is used to connect probe adapter SWEX 100SD1 when the In Circuit Emulator is connected to external target hardware 502 Connection between the IE 703242 G1 EM1 the IE V850ES G1 CN1 CN2 CN3 emulator 2 4 2 Clock Connectors These are used to configure clock oscillators of the IE 703226 G1 MC to run at the desired operation frequency Table 2 6 Clock Connectors Connector Socket Function Socket for main cl
12. GA via L S 63 PCM1 PCM1 CLOCKOUT FPGA via L S 64 PCM2 PCM2 FPGA via L S 65 Vss31 Vss31 S Ground 66 REGC1 REGC1 S not connected 67 PCM3 PCM4 FPGA via L S 68 PDHO PDHO FPGA via L S 69 PDH1 PDH1 FPGA via L S 70 PDH2 PDH2 FPGA via L S 71 PDH3 PDH3 FPGA via L S 72 PDH4 PDH4 FPGA via L S Preliminary User s Manual U16345EE1VOUMOO 33 Chapter 4 Differences between Target Device and Emulation Board Table 4 1 Pin list according to their emulation location 3 3 default Emulated by Alternative single chip Venus chip Shifter connected to PDH5 FPGA via L S PCTO FPGA via L S PCT1 FPGA via L S PCT4 FPGA via L S PCT6 FPGA via L S P20 RXD61 INTP8 P21 TXD61 22 5101 P23 SO01 P24 SCKO1 P25 P30 TI50 TO50 P31 TI51 TO51 P32 T152 TO52 P33 TICO0 TOCO P34 TICO1 P711 ANIH 1 P710 ANI10 P79 ANI9 P78 ANI8 P77 ANI7 P76 ANI6 P75 ANI5 P74 ANI4 P73 ANI3 P72 ANI2 P71 ANI1 P70 ANIO Pin Function 34 Preliminary User s Manual U16345EE1VOUMOO Appendix Mechanical Data Figure A 1 Mechanical Data A amp S D 1 5 3 502 5 2 N e 100 76 5 SI y E ole S je 1 5 GND
13. Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function 2 Preliminary User s Manual U16345EE1VOUMOO MS DOS and MS Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries PC AT and PC DOS are trademarks of IBM Corp The related documents in this publication may include preliminary versions However preliminary versions are not marked as such The export of this product from Japan is regulated by the Japanese government To export this product may be prohibited without governmental license the need for which must be judged by th cu
14. M a COR Ne 5 ONE OR URN aa QNI TRO 31 4 7 AVpp AVss pins IT PITT 32 Appendix A Mechanical 35 AppendbcB InideX uu sk meteor OR wa ain ee UR CR RR 37 Preliminary Users Manual U16345EE1VOUMOO 5 Preliminary User s Manual U16345EE1VOUMOO Figure 1 1 Figure 1 2 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure A 1 List of Figures IE 703242 G1 EM1 hardware configuration 11 System Configuration ea ie Ue ede ee 15 IE 703242 G1 EM1 top 40422 00 0 000 nennen 19 IE 703242 G1 EM1 bottom 00 000 00000 1 20 LEDs controlled by 703242 1 21 Main Clock 25 Sub Clock 26 Mechanical Data wit cites eias eed i i lal del 35 Preliminary Users Manual U16345EE1VOUMOO 7 Preliminary User s Manual U16345EE1VOUMOO Table 1 1 Table 1 2 Table 1 3 Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 4 1 List of Tables Components of Emulation System 12 Features of 1 703242 91 1 enne nnne 13 Functional
15. ace Write to the ROM space Caution Some of the functions may not be supported depending on the debugger used 14 Preliminary User s Manual U16345EE1VOUMOO Chapter1 Overview 1 5 System Configuration The system configuration when connecting the IE V850ES G1 to the IE 703242 G1 EM1 anda personal computer PC AT or compatible is shown below Figure 1 2 System Configuration 4 Em imt E Target lt 4 gt lt 10 gt system ITITTI 11 Target system Remark 1 PC 2 Debugger Sold separately 3 Device file Included with the IE 703242 G1 EM1 4 PC interface board Sold separately 5 PC interface cable Included with the IE V850ES G1 Sold separately 6 Power supply cable Included with the IE V850ES G1 Sold separately 7 In circuit emulator IE V850ES G1 Sold separately 8 In circuit emulator emulation board IE 703242 G1 EM1 This product 9 Extension probe SWEX 100SD1 Sold separately 10 YQPACK100SD Sold separately 11 NQPACK100SD Sold separately Preliminary Users Manual U16345EE1VOUMOO 15 Chapter1 Overview 1 6 Package Contents The packing box contains the following items 1 Hardware 1 pcs IE 703242 G1 EM1 1 pcs Antistatic bag 6 sets Screws washers 2 Documentation 1 pcs Read IE 703242 G1 EM1 1 pcs Operating precautions 1 pcs Hardware tool registration card 1 pcs Notificati
16. ain oscillator when standby mode is released 3 3 Port direction setting for peripheral function When a peripheral function is used the direction setting for the respective port bit of the V850ES GB1 real chip is not set automatically The port bit direction has to be programmed according to the requirement of the peripheral function by setting the port mode register In the FPGA on the emulation board port mode setting is not necessary when a peripheral function is used Therefore on the emulator ports emulated by the FPGA behave different from the real chip This only affects bit 1 of port PCM CLOCKOUT function Therefore if the CLOCKOUT function is to be used the respective bit positions of registers PMCM and have to be set accordingly 3 4 Programmable peripheral area The usable settings for the BPC register limit usage to the first 32MB of the total address range There fore the programmable peripheral area must be set to an address range within the first 32 MB 3 5 Other precautions Take note of the differences between the In Circuit Emulator and the real chip described in Chapter 4 Differences between Target Device and Emulation Board Preliminary Users Manual U16345EE1VOUMOO 29 MEMO 30 Preliminary User s Manual U16345EE1VOUMOO Chapter 4 Differences between Target Device and Emulation Board When the In Circuit Emulator is connected to a target system for debugging the V850ES GB1 is emu lated which means that
17. anization CS 01 2
18. ations for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 01 Fax 0211 65 03 327 Sucursal en Espa a Madrid Spain 091 504 27 87 Fax 091 504 28 60 Succursale Frangaise V lizy Villacoublay France 01 30 67 58 00 01 30 67 58 99 Filiale Italiana Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 Branch Netherlands Eindhoven The Netherlands Tel 040 244 58 45 Fax 040 244 45 80 Branch Sweden Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 United Kingdom Branch Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea 02 528 0303 02 528 4411 NEC Electronics Singapore Pte Ltd Singapore Tel 65 253 8311 65 250 3583 Electronics Taiwan Ltd Taipei Taiwan 02 2719 2377 02 2719 5951 NEC do Brasil S A Electron Devices Division Guarulhos Brasil 55 11 6465 6810 Fax 55 11 6465 6829 Pre
19. ective expansion IE 70000 PCI IF A slot of the PC IE 70000 CD IF A IE 70000 PCI IF A for PCI socket IE 70000 CD IF A for PCMCIA socket Preliminary Users Manual U16345EE1VOUMOO 11 Chapter1 Overview 1 2 Components of the Emulation System For order codes of the components that may be used in an emulation system for V850ES GB1 refer to the following table Table 1 1 Components of Emulation System Component Order Code Comment In Circuit Emulator IE V850ES G1 Main board for CPU emulation and trace Notes 1 2 Emulation board IE 703242 G1 EM1 Emulation board for V850ES GB1 Notes 1 2 Probe cable SWEX 100SD1 Probe cable for target connection Note 2 Board socket for target connection soldered on target P t NQPACK100SD robe to target connector NQ board Nete 2 Probe to target connector YOPACK100SD Probe connection fixed on NQPACK100SD Note 2 Probe to target connector YQSOCKET100SDF Distance socket optional PC interface card IE 70000 PCI IF A PCI interface card for host connection Note 3 PC interface card IE 70000 CD IF A PCMCIA interface card for host connection Nete 3 Network interface IE 70000 MC SV3 Network interface for host connection Note 3 Notes 1 Required for stand alone operation no target connection 2 Required for operation with target hardware 3 The interfaces are alternative one is mandatory 12 Preliminary User s Manual U16345EE1VOUMO00 Chapter1 Overview
20. enus 19 10 10 5100 Venus 20 P11 11 5000 Venus 21 12 12 5 00 Venus 22 P13 P13 RXD60 INTP7 Venus 23 P14 P14 TXD60 Venus 24 15 15 Venus 25 P40 P40 KRO Venus 26 P41 P41 KR1 TIGOO Venus 27 P42 P42 KR2 TIGO1 TOGO1 Venus 28 P43 P43 KRS TIGO2 TOGO 2 Venus 29 P44 P44 KR4 TIGO3 TOGO3 Venus 30 P45 P45 KR5 TIGO4 TOG04 Venus 31 P46 P46 KR6 TIGO5 Venus 32 P47 P47 KR7 Venus 33 P50 P50 Venus 32 Preliminary User s Manual U16345EE1VOUMOO Chapter 4 Differences between Target Device and Emulation Board Table 4 1 Pin list according to their emulation location 2 3 PinFuncion feu vo recA vate Shifter P51 P52 P53 P54 DCTXDO P55 DCRXDO P56 P57 PCSO FPGA via L S PCS1 FPGA via L S PDLO FPGA via L S PDL1 FPGA via L S PDL2 FPGA via L S PDL3 FPGA via L S PDL4 FPGA via L S PDL5 FPGA via L S PDL6 FPGA via L S 50 PDL7 PDL7 FPGA via L S 51 PDL8 PDL8 FPGA via L S 52 PDL9 PDL9 FPGA via L S 53 PDL10 PDL10 FPGA via L S 54 PDL11 PDL11 FPGA via L S 55 PDL12 PDL12 FPGA via L S 56 PDL13 PDL13 FPGA via L S 57 Vpp Vpp S not connected 58 PDL14 PDL14 FPGA via L S 59 PDL15 PDL15 FPGA via L S 60 Vpps1 Vpps1 5 buffered 61 Vss51 Vsss1 5 Ground 62 PCMO PCMO FP
21. et system Preliminary Users Manual U16345EE1VOUMOO 17 MEMO 18 Preliminary User s Manual U16345EE1VOUMOO Chapter 2 Name and Functions of Components This chapter describes the names and functions of the components of IE 703242 G1 EM1 Also jumpers and switches used for configuration of the tool are described here 2 1 Name and Functions of IE 703242 G1 EM1 Components Figure 2 1 703242 1 top view z9 2 M ed A JP2 B6 5 gta 402 yva 8 1 3 m lt 6 E a lt 2 0 01 LT o JP1 4 S OS CNS D CN6 4 Y o 2 gO Og 5 a e 2 3 95 m ri 1 E d ine E a 2 2 m V 2 N Gi E 3 5 ol Preliminary Users Manual U16345EE1VOUMOO 19 20 Chapter 2 Name and Functions of Components Figure 2 2 JE 703242 G1 EM1 bottom view 28 C57 66 C65 56 2 v UR c ic 81 5 98 5 c69 OQ gt 74 o d R 2 C67 o hs c68 g 288 1 52 2 064 9 zg TP25 a 2 x TP24 9 mi y or 8 TP23 1 2 C58 _ 0 25 J 8 B g g o 4 M 8
22. ies See So EE See 24 BD OL an crc 22 Jc 23 jumper settings ure de ete Breed trei ted xe ente Yet me Rule e ART seti gs 22 Preliminary Users Manual U16345EE1VOUMOO 37 Appendix B L LED StatUS rds oe LU o ore M memory coverage emulation da order code oscillator crystal for sub COCK RC for sub clock PCI interface card PCMCIA interface card DIN car e ae eR precautions probe cable R REG G pin uses Re a eee ee ee reset RSM register 5 settings Clock 05 jumper configuration 501 502 specifications functional elus imul aoe co hh standby release Status LED iuo yee ech supply a Rae depu rael VONAGE xe gi Rr EET E ER RAE S RU SWEX 100SD1 T temperature operation STOLAGS DP V view bottom view of emulation board top view of emulation board VPP pin Index 38 Preliminary User s Manual U16345EE1VOUMOO YQPACK100SD Appendix B Index YQSOGCKET100SD 1 t fe o n Ee ed e D ae e Y eb deer dos Dog Preliminary User s Manual U16345EE1VOUMOO 39 40 Preliminary User s Manual U16345EE1VOUMOO Alth
23. liminary User s Manual U16345EE1VOUMOO Table of Contents Chapter 1 Overview is 662 040800 peevn bay bee eee 11 1 1 Hardware 11 1 2 Components of the Emulation 12 1 3 Features When Connected to 850 5 61 13 1 44 Function Specifications When Connected to 850 5 1 14 1 5 System 15 1 6 Package Contents iR Genie ee ieee Eu 16 1 7 Connection between IE V850ES G1 and IE 703242 G1 EM1 17 1 8 Power up sequence 17 Chapter 2 Name and Functions of 19 2 1 and Functions of IE 703242 G1 EM1 19 2 2 Status LEDS 2 dui M reir s M rptu he 21 2 3 JumperSettings 22 25301 OVETVIOW ret rte dated det bee hearts A t Lou std iad 22 2 3 2 Jumper JP2 AVpp 5 22 2 3 8 Jumper AVgs 23 2 4 Main Sockets and
24. n of customer s equipment shall be done under the full responsibility of customer NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC semiconductor products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to semiconductor products developed based on a customer designated quality assurance program for a specific application The recommended applications of a semiconductor product depend on its quality grade as indicated below Customers must check the quality grade of each semiconductor product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equip ment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobile
25. ock crystal and capacitors Socket for sub clock crystal and capacitors Socket for main clock oscillator to be used alternatively instead of CN6 Select sub clock signal generated by timer circuit alternative to CN6 2 4 3 Other Components Further connectors and test points are used for internal testing during production and maintenance and are not listed here 24 Preliminary User s Manual U16345EE1VOUMOO Chapter 2 Name and Functions of Components 2 5 Clock Operation This chapter describes the operation of the clock generation of IE 703242 G1 EM1 The V850ES GB1 features two clock oscillators a main clock oscillator for normal operation and a sub clock oscillator that allows to run the microcontroller at a slow operation speed to implement certain power save functions 2 5 1 Main Clock The main clock oscillator of the V850ES GB1 and also IE 703242 G1 EM1 operates at frequencies up to 16 MHz On the emulation board the source for the main clock can either be a crystal or a dedicated C MOS oscillator By default a crystal is used which is assembled to the respective connector CN6 Alternatively a dedicated C MOS oscillator in DIL Package may be used In this case the crystal and capacitors must be removed from CN6 and a crystal oscillator must be mounted to socket SO1 Figure 2 4 Main Clock Configuration Venus I O chip X2 IF HUE M Caution Since the clock inputs X1 and X2
26. of the I O chip are not connected to the target crys tal or oscillator operation from the target board is not possible Crystal or Oscillator provided on the emulation board must be used Preliminary Users Manual U16345EE1VOUMOO 25 Chapter 2 Name and Functions of Components 2 5 2 Sub Clock The V850ES GB1 is available in different versions that feature different sub clock oscillators for device operation at low frequencies Crystal oscillator RC oscillator If a crystal oscillator is used for the sub clock oscillator a crystal of a fixed frequency of 32 768 KHz and capacitors must be connected to the connector CN9 For emulation of the RC oscillator a dedicated timer circuit on the emulation board can be used This timer circuit generates an adjustable frequency in the range of 40 to 100 KHz If the timer circuit is used the sub clock crystal and capacitors must be disconnected from CN9 and jumper JP1 must be shorted By default the timer circuit is configured to operate at a frequency of about 100 KHz To adjust the operating frequency of the sub clock timer circuit R28 R29 and C77 on the emulation board must be changed Figure 2 5 Sub Clock Configuration Venus chip XT1 XT2 Oscillator Circuit IF MUP di 32 768 KHz Caution Since the clock inputs CL1 and CL2 XT1 and XT2 respectively are not connected to the target crystal or RC oscillator operation from the ta
27. on on internet software update provision 1 pcs Read me first 1 pcs User s manual 3 Software Device Files on Floppy Disk 16 Preliminary User s Manual U16345EE1VOUMOO Chapter1 Overview 1 7 Connection between IE V850ES G1 and IE 703242 G1 EM1 The procedure for connecting the IE V850ES G1 and the IE 703242 G1 EM1 is shown below 2 109 2 e Disconnect the power from IE V850 ES G1 Remove the cover of the IE V850ES G1 Make jumper settings on main board of IE V850ES G1 as described 2 3 Jumper Settings Place the IE 703242 G1 EM1 over the main board of IE V850ES G1 so that the board connectors are in the correct position Press IE 703242 G1 EM1 carefully so that the connection to the main board is secured Fix the IE 703242 G1 EM1 to the main board using the screws delivered with the board If the tool is used with a target board for emulation connect the probe adapter SWEX 100SD1 to the appropriate socket SO2 of IE 703242 G1 EM1 Close the cover of the IE V850ES G1 Reconnect the power to the IE V850ES G1 If the tool is used with a target board for emulation connect the target socket probe adapter to the emulation target emulation target powered off Cautions 1 Connect carefully so as not to break or bend connector pins 2 Take care to match pin 1 when connecting the probe adapter to the probe socket of IE 703242 G1 EM1 1 8 Power up sequence Power on the emulation system first then power on the targ
28. ough NEC has taken all possible steps 55 0 to ensure thatthe documentation supplied to our customers is complete bug free From and up to date we readily accept that errors may occur Despite all the care and precautions we ve taken you may Name encounter problems in the documentation Please complete this form whenever Company you d like to report errors or suggest improvements to us Tel FAX Address Thank you for your kind support North America Hong Kong Philippines Oceania Asian Nations except Philippines NEC Electronics Inc NEC Electronics Hong Kong Ltd NEC Electronics Singapore Pte Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax 465 250 3583 Fax 41 800 729 9288 1 408 588 6130 CE tronics Hong Kong Ltd NECS iconductor Technical ectronics Hong Kong Ltd emiconductor Technical Hotline Pe COMES e MODO omer Fax 81 44 435 9608 Market Communication Dept Fax 482 2 528 4411 Fax 49 211 6503 274 South America Taiwan NEC do Brasil S A NEC Electronics Taiwan Ltd Fax 455 11 6462 6829 Fax 886 2 2719 5951 would like to report the following error make the following suggestion Document title Document number Page number If possible please fax the referenced page or drawing Document Rating Excellent Acceptable Clarity Technical Accuracy Org
29. rget board is not possible Crystal or RC oscillator provided on the emulation board must be used 26 Preliminary User s Manual U16345EE1VOUMOO Chapter 2 Name and Functions of Components To change the operation frequency of the oscillator circuit R28 R29 and C77 must be selected using the following formulae a R28 2 R29 C77 1 44 R28 Roe 2 f C77 Remark Use R28 and R29 in the Range 1 lt R lt 10 MO and C77 in the Range 1 nF lt C lt 10 uF Preliminary Users Manual U16345EE1VOUMOO 27 MEMO 28 Preliminary User s Manual U16345EE1VOUMOO Chapter 3 Operating Precautions Be aware of the following operating precautions when using the IE 703242 G1 EM1 3 1 Reset source monitor flag The reset source reset caused by external reset input or watchdog timer can not be distinguished by the RSM register of the clock controller during emulation mode Oscillation stabilization time is skipped after a watchdog timer reset during sub watch mode 3 2 Standby release The main oscillator of the V850ES GB1 I O chip on the emulation board is always running can not be switched off Therefore no oscillation stabilization time is required when stop mode or sub watch mode of V850ES GB1 is released As a consequence of this the V850ES GB1 I O chip on the ICE will wake up immediately from sub watch or stop mode whereas the V850ES GB1 real chip always assures the oscillation stabilization time for the m
30. s trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifi cally designed for life support Specific Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC semiconductor products is Standard unless otherwise expressly specified in NEC s data sheets or data books etc If customers wish to use NEC semiconductor products in applications not intended by NEC they must contact an NEC sales representative in advance to determine NEC s willingness to support a given application Notes 1 NEC as used in this statement means NEC Corporation and also includes its majority owned subsidiaries 2 NEC semiconductor products means any semiconductor product developed or manufactured by or for NEC as defined above M5 2000 03 Preliminary Users Manual U16345EE1VOUMOO Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify e Device availability e Ordering information e Product release schedule e Availability of related technical literature e Development environment specifications for example specific
31. stomer The export or re export of this product from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative The information in this document is current as of 30 07 2002 The information is subject to change without notice For actual design in refer to the latest publications of NEC s data sheets or data books etc for the most up to date specifications of NEC semiconductor products Not all products and or types are available in every country Please check with an NEC sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC NEC assumes no responsibility for any errors that may appear in this document NEC does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the desig
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