Hardware User`s Manual
Contents
1. a a nnns 29 Figure8 10 VADJ Circuit Structure 30 Figure8 11 SDA SCL GA1 0 FMC3 JTAG Circuit Structure 33 Figure8 12 C2M Circuit Structure a nnn nnns nnn nnn nnne nnns 33 Figure8 13 VADJ Iden 34 Figure8 14 RS232C Connector Layout 42 leit LED L I uu uu ullu 42 Figureg 16 GPIO uu 43 Figure5 17 DIPFSW Tm 44 Figure8 18 PUSHSW 45 Figures 19 Power Connector for lr D 46 Figure8 20 Patten 46 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T S8X475 T PCIEXP Hardware User s Manual I ee VI LIT ag List of Tables Table 1 Details of Onboard Oecllator nnne 15 Table 2 FMC1 Connector bBmout 17 Table FMC2 Connector Pinout Table 24 Table 4 Connector Pinout Table 31 Table 5 DDR3 SO DIMM 1 Pinout nnne 35 Table 6 DDR3 SO DIMM 2 Pinout Table nnnm 37 Table 7 PCI Express Edge Pinout Table nnns 40 Table 8 PCI Express Lane Width Configuration 41 Table 92. CLK Mec P GND __ __ 0 1 4 M2C P HADO P CC ND Lues s ME 1 cc ADE JAJE N dt EE EE HA13 P _ DET Mec T GND GND NC LAT P Lu SC i Connector LPG Connectar _ LPC Connector LPG Connector Figure8 3 High Pin Cont Pin Layout J F E D C 1 ELE Zorki vec COND Tekmen f ne cukowcP NC pO _ NC AN CH ae ole 70 c L e u L GND NC GND LPC LFC Connector LPG Connector a O 2 LPC Connector Figure8 4 Low Pin Cont Pin Layout Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual 1 levi um ag 8 3 1 FMC1 HPC Connector High Pin Count The board uses the High Pin Count connector Due to limitation of the number of FPGA pins Banks all FMC connector pins are not connected The connector is interfaced as shown below HighSpead XC6VLX240T 365T TX 8ch RX 8ch XC6VLX550T XC6VSX475T TX10ch RX 10ch LowSpead XC6V
3. Connector Samtec MMCX J P H ST TH1 General Purpose l F GPIO FCI 95278 101A14LF 12 00 63 02 ei u 80 09 50 01 ES 6D 392 CO Figure7 1 Board Dimension Diagram Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I levi um 8 Description of Each Component 8 1 Power Supply Structure The following figure provides the internal power supply structure FPGA Vccint 4 LTM4601A 1 LTM4601A 1 1 0V 36 0A FPGA VccAux LTM4619 2 5V FPGA Vcco gt 2 5V 4 0A FPGA MGTAVcc Bias LT3070 Vin FPGA gt 1 0 5 0 Power FPGA MGTAVtt 1 2V 6 0A FPGA Vcco p gt DDR3 VDD VDDQ LTM4616 1 5V 8 0A FPGA p DDR3 VDD VDDQ 1 5V 8 0A FPGA Vref LTC3413 DDR3 Vref Vtt Vin 0 75V 3 0 SI FPGA Vref LTC3413 DDR3 Vref Vtt Vin 0 75V 3 0A Option Power x3 LTM8025 12 0 1 0 5 0 6 0 Option Power i LTM4619 2 5V Option Power x3 Option Power x3 3 3 4 0 FPGA S3 Vccaux gt Other VDD VDDQ 3 3V 30A Config FPGA S3 Vccint Power LTC3417A 1 2 15 FPGA S3 Vcco 2 5V 1 0A Figure8 1 Power Supply Structure About p
4. nie mw reme o NO rem rem ww warren sie ane Pens eb x TGS err Lal weng 6 rem mee 7 rem Lal mee 5 1 1 The PCI Express lane width depends the type of a resistor to be installed Table 8 shows PCI Express lane width configuration Table 8 PCI Express Lane Width Configuration Device Lane R89 R9 R91 Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I levi UT ag 8 6 RS232C UART Interface The board provides a RS232C interface as a means of communication with an external device RS232C driver IC U14 TI MAX3318EI The RS232C connector J9 uses 5 pin 2 54mm pitch pin header gelt Hz UT 4 anurz SAREAN Inala UPGLUFF RLADN MAXSS18EIPYUR Figure8 14 RS232C Connector Layout FPGA MAXGSIBEIPW Signal Name o ors Table 9 UART Pinout Table 8 7 LED The board has eight LEDs All these LEDs will be turned on when High is output from FPGA Figure8 15 LED Layout Table 10 LED Pinout Table Device FPGA D1 pe SEL e me 24 pe Te LED6 7 1 03 TOKYO ELECTRON DEVICE LIMITED
5. GND GN OH WO W N IO N GND 40 Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475T PCIEXP Hardware User s Manual inreviun LL Emme _ 2 RRE P31 25 y o 2sF H28 N N N O CA G29 29 27 m 28 0 N A Co CO 6 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I ee VI LIT ag 1 SCL SDA Test point for 122 communication with the FMC mezzanine card Figure8 11 SDA SCL GA1 0 FMC3 JTAG Circuit Structure 2 GA 1 0 It is connected to test point 3 JTAG TCK TMS TDI TDO TRST_L TDI and TDO have loopback structure for JTAG communication from the FMC mezzanine card TCK TMS and TRST_L are used for test point only By default this loopback function is not provided because the R230 resistor is not installed 4 C2M This is connected to the test point and a pull up resistor to 3 3V power supply Figure8 12 PG_C2M Circuit Structure 5 PRSNT_M2C This is connected to the FPGA and a pull up resistor to the 2 5V power supply Rev 1 03 TOKYO ELECTRON DEVIC
6. TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I ee VI LIT ag 8 8 GPIO Interface The board has a 14 pin header J15 Of them 10 signals are connected to FPGA The interface has a 2 5V voltage level 1 m a Nd NN ds n xa 0 III 2 z 1 d i EL 1 m CON 14 Figure8 16 GPIO Pin Layout Table 11 GPIO Pinout Table ol E SR a AF 18 AUS 2 5 6 A32 15 15 AB33 7 8 15 15 AD37 6 9 10 GPIO7 AJ37 14 GND GND Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I ee VI LIT ag 8 9 DIPSW The board has an 8 pole DIPSW When the DIPSW is set to the ON side it generates Low on the associated FPGA pin FT fi HI 211 F 254 2 EM 11114213 4144 494 47k RN L 11 4 7K RN 21 Wa uu uj L l Du K ei Li a TEL n ux A 10 DSW DSWS a 0 d DSWS Eng DENT CHS 086 DGND Figure8 17 DIPSW Structure Table 12 DIPSW Pinout Table 34 ze ms Rev 1 03 TOKYO ELECTRON DEVICE LIMITED 44 TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Man
7. A 97 98 ao C84 27 vp 99 i VD 105 106 VOD VD 10021 VDD vb _ 17 1 VOD 27 Kso 121 122 MI VD 131414 vD LL NC 125126 VREFCA ys _ 127 128 vs Ns 133134 Ves AA 37 E24 0084 137 138 Ves ______ vs 139 140 Dass E20 37 37 121 085 143 144 Ves 145 146 0044 C201 37 37 J20 Dou 149 15 Ves IL 151 152 posi 120 37 vys 155 156 Ves ys 161 162 vs Rev 1 03 TOKYO ELECTRON DEVICE LIMITED 36 TB 6V LX240T 365T 550T S8X475 T PCIEXP Hardware User s Manual 1 ee VI LIT ag DQ49 165 166 DQ53 ss o 36 Dase 169 170 0 6 E18 36 2 pens 17311 36 H18 I ee 36 818 0051 te 0060 P17 __ 0061 P16 e Freie C18 DM 187 189 Ni8 0068 191 P18 193 195 ______ SA 197 198 NC 199 20 SDA 5 36 SAt 201 202 51 B18 36 Table 6 DDR3 SO DIMM 2 Pinout Table mE e 190 192 194 196 198 Wem 605 m ______ Ns ajia Ves 28 015 1
8. TB 6V LX240T 3651 550T SX475T PCIEXP Hardware User s Manual 1 ee VI LIT ag 6 1 240 365 550 5 475 Hardware User s Manual Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I ee VI LIT ag Revision History Rev 0 02 2010 02 26 Modify Figures and tables Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 3651 550T SX475T PCIEXP Hardware User s Manual I ee VI LIT ag Table of Contents 15 e u 0000805 9 0 000000 555 59908 6 2 Related Documents and Board Accessories 9 5805 7 9 Poa 9 5 Block Diagram ccccccseeeeecceeeeeeeneeeeeeceaeeeeeseaseeeeseueeeecseeeeesaaeeeesseaeeeessageeeeseaeeeessaeeeeessaeeeseneass 10 View of Ihe DO ANG rettet r rr 11 15 IC p EE 12 Description OI Each Componei uuu ___ ___ 13 9 1 Power Supply 13 ESO 22 14 8 3 FMC Connector ur e 16 831 FMC1 HPC Connector Highli Piri 17 8 3 2 2 HPC Connector High Pin CGoumnt a 24 8 3 3 LPC Co
9. 22 27 109 110 27 22 VD VOD Wer 103114 _ 22 _ 22 27 5 115 116 AU29 22 wi pp 22 Aa 119 120 28 22 22 CSIMNC 121 122 vo 123 124 LL NC 11251128 VREECA Vs 1127 1281 vs Rev 1 03 TOKYO ELECTRON DEVICE LIMITED 38 TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I ee VI LIT ag 33 AJ17 DQ32 129 130 DQ36 AK14 33 x 133 134 88 8 0054 137 138 e AA ______ 139 140 0038 ARI9 33 88 15 0035 414414 Vs ______ 145 146 0044 AN9 3 88 BBI8 Dou 149 150 __ AA ______ ss 151 152 00558 AYi9 33 ys _ 155 156 ei ss __ 161 162 __ Ns 167 168 vs 82 Aves 0086 171 172 __ vs 173 174 0054 AW3 32 82 1 17 178 Ves Vvs 179 180 0960 9 32 82 0057 183 184 Vs AA ______ ss 185 186 0578 AP20 32 vs 491490 vs 195 196 __ ______ SA 1197 198 EVENT DA LL SA 20122 SL AT21 1 03 TOKYO ELECTRON DEVICE LIMITED 39 TB 6V LX240T 3651 550T SX475T PCIEXP Hardware User s Manual
10. TB 6V LX240T 365T 550T SX475T PCIEXP Hardware User s Manual I levi um ag 7 Power Supply The board provides a 12V to the 12POV pin and a 3 3V to the 3P3V and 3P3VAUX pins 5V 3 3V and 2 5V are also selectable VADJ pins as shown in Figure 8 8 The target pins are E39 F40 G39 and 40 The voltage supply can be provided by short circuiting one portion of JP3 and JP4 respectively The power status can be monitored by the adjacent LED Caution Do not short circuit more than two portions of JP3 and JP4 respectively Short circuit the same portion of and 5 OP 33V OP 25V JP5 JP6 TMM 103 064 D SM TMM 103 064 D SM 2 5V LED O BR1111C DGND Figure8 7 VADJ Circuit Structure VIO B M2C The VIO B M2C terminal of the J39 and K40 pins can be monitored by TP95 VREF A M2C VREF B M2C The board provides the TP90 Test Pad to monitor the VREF A 2 terminal of the H1 pin and theTP92 Test Pad to monitor the VREF B M2C terminal of the K1 pin Rev 1 03 TOKYO ELECTRON DEVICE LIMITED 23 TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual 1 Un B 8 3 2 2 HPC Connector High Pin Count The board uses the High Pin Count connector Due to limitation of the number of FPGA pins Banks all FMC connector pins are not connected The connector is interfaced as shown below HighSpead XC6VLX240T 365T TX 8ch RX XC6VLX550T XC6VSX475T 10ch RX 10ch LowSpead XC6VLX2
11. 17 18 B39 26 __ Vs Vs 26 038 Das 22 0012 26 C88 009 23 24 0013 236 26 __ 8 25 26 26 AM 008 27 28 26 26 A40 0051 29 30 B36 27 vs 31 32 vs 26 G34 35 36 0015 C40 26 Vss ve 26 037 0016 39 4 0020 Fa 26 26 042 0017 41 42 __ ys 43 44 vs 26 E40 45 46 F42 26 26 D40 0082 47 48 Ves 49 50 0022 042 2 26 019 mine 551 56 624 37 37 G23 0024 57 58 0029 C28 37 _ 37 H23 59 6 Ves ______ 61 62 Dass Fee 37 37 B22 63 64 0053 G22 37 ys 65 66 vs 37 824 0026 167 68 Daso F20 37 37 A24 0027 69 70 DOS B23 37 ys 71172 ys J v 751761 VDD Rev 1 03 TOKYO ELECTRON DEVICE LIMITED 35 TB 6V LX240T 365T 550T S8X475 T PCIEXP Hardware User s Manual 1 ee VI LIT ag NC 77 78 NC A15 D37 27 27 130 79 80 14 E32 27 vo 82 27 231 A9 85 86 JC3 27 v 8 27 833 A8 89 E35 2 vD 93 94 WOOD 27 1 a 95 9B A2 6127 27
12. 365T 550T SX475 T PCIEXP Hardware User s Manual 1 ee VI LIT ag ww pj 9 __ ___________ y 5 Lesser memes 3 oe e e 4 oo mew a xn s e E n s o s ow E Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I UT ag 1 RES1 0 It is connected to test point 2 SCL SDA Test point for DC communication with the FMC mezzanine tur gt Le oh WH LI ei eu Cupra TEREE L EH zn d pRES Lal gt os Figure8 5 SDA SCL GA1 0 FMC1 JTAG Circuit Structure 3 GA 1 0 It is connected to test point 4 FMC1 JTAG TCK TMS TDI TDO TRST_L TDI and have a loopback structure for JTAG communication from the FMC mezzanine card TCK TMS and TRST L are used for test point only By default this loopback function is not provided because the R225 resistor is not installed 5 PG C2M PG M2C It is connected to the test point and the pull up resistor to the 3 3V power supply CH Shit Fue SPT en MET E Frid aH IED GN Figure8 6 PG_C2M PG_M2C Circuit Structure 6 PRSNT_M2C It is connected to the FPGA and the pull up resistor to the 2 5V power supply Rev 1 03 TOKYO ELECTRON DEVICE LIMITED 22
13. UART Pinout Tabie U uuu u uu ________ A 42 Table LED Pinout Table uuu lll l uu ar ARAE mr Te uad Aa 42 Table 11 GPIO Pinout Table _____________ __ 43 Table 12 DIPSW Pinout Table 44 Table 15 PU SASW PINOUT E 45 Table 14 External Power Supply Connector Pinout Table 46 Table 15 Battery Control signal Pinout Table 46 Table 16 SPI Flash PinOUt Ee wawa LI rx edic waw cr prc 46 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T S8X475 T PCIEXP Hardware User s Manual I ee VI LIT ag 1 Introduction Thank you for purchasing the TB 6V LX240 365T 550T SX475T PCIEXP board Before using the product be sure to carefully read this User Manual and fully understand how to correctly use the product Read through this manual and always keep it handy Safety Precautions Be sure to observe these precautions Observe the precautions listed below to prevent injuries to you or other personnel or damage to property e Before using the product read these safety precautions carefully to assure correct use e These precautions contain serious safety instructions that must be observed e After reading through this manual be sure to always keep it handy The following conventions are used to indicate and classify precautions in this manual Failure to observe precautions can result in injury to people or damage to property Indic
14. application that requires high reliability Repair of this product is carried out by replacing it on a chargeable basis not repairing the faulty devices However non chargeable replacement is offered for initial failure if such notification is received within two weeks after delivery of the product The specification of this product is subject to change without prior notice The product is subject to discontinuation without prior notice Becareful when inserting a memory module into the onboard DIMM socket Limit the number of trials of inserting the memory module into the DIMM socket to 25 Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475T PCIEXP Hardware User s Manual I ee VI LIT ag 2 Related Documents and Board Accessories Related documents All documents relating to this board can be downloaded from our website Please refer to attached paper of the products Board Fixer Fan heat sink set Fan 1 Heat sink 1 M3 X 20 screw 2 Washer 2 XH connector JST 1 DDR 8 SO DIMM 1G byte SanMax SMD N1G88 13H or equivalent 2 Board Accessories Board foot set Rubber foot 7 M3 X 6 screw 14 M3 X 10 spacer 7 AC DC power supply 12V 15A power supply 1 power supply cable with a power switch 1 DOC power supply cable 1 microSD card for Config 2Gbyte 1 3 Overview This board is the high speed and high density PC Express Gen2 evaluation board equipped w
15. your hand close to it Otherwise it may cause injury to persons Never touch a rotating cooling fan Do not place the product on unstable locations Otherwise it may drop or fall resulting in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or electric shock may occur Do not touch the product with a metallic object Otherwise a fire or electric shock may occur Do not place the product in dusty or humid locations or where water may splash Otherwise a fire or electric shock may occur Do not get the product wet or touch it with a wet hand Otherwise the product may break down or it may cause a fire smoking or electric shock Do not touch a connector gold plated portion on the product Otherwise the surface of a connector may be contaminated with sweat or skin oil resulting in contact failure of a connector or it may cause a malfunction fire or electric shock due to static electricity TOKYO ELECTRON DEVICE LIMITED Rev 1 03 TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I ee VI LIT ag A Caution Do not use or place the product in the following locations Humid and dusty locations Airless locations such as closet or bookshelf Locations which receive oily smoke or steam Locations exposed to direct sunlight Locations close to heating equipment Closed inside of a car where the temperature becomes high Staticky locations Locations
16. 08 test pad to monitor the VREF B M2C terminal of the pin Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I levi um ag 8 3 3 LPC Connector Low Pin Count The board uses the Low Pin Count connector Due to limitation of the number of FPGA pins Banks all FMC connector pins are not connected The connector is interfaced as shown below HighSpead XC6VLX240T 365T TX Och RX Och XC6VLX550T XC6VSX475T RX ich LowSpead XC6VLX240T 365T LA OPair 0 XC6VLX550T XC6VSX475T LA 34Pair 72 Table 4 shows the FMC3 connector pinout table for FPGA Table 4 FMC3 Connector Pinout Table BakNo PinNo Dp JenNo BakNo 13 memene ci gt ES 6 10 A9 MGTREFCLK1P_118 MGTREFCLK1N_118 DP0_M2C_P GND O B7 _ _ op op 18 ar 126 9 is 008801 20 b X s O P 030 N24 N25 PO Co tmon 15 LAON faso 2 28 a e cw o Mu 18 aan 029 28 LAN ho eo pre e oun LIMEN eme 8 Jl ____ oe alen Aew s ee LAZ P Joel wel 7 wen 27 wen __ 28 GND ss GND GN
17. 1 levi um ag 8 5 PCI Express Edge Interface The board allows a PCI Express x8 8 Lane Gen2 connection Table 7 PCI Express Edge Pinout Table Pho A _ pomems 0 oom w ie ww w a w J e mem s mer ll mem _ NENNEN NEN SS aW we mem NENNEN aan Las luese 2 3 4 SS 7 gt e rem w E on E 20 22 MGTTXN3_113 Pere AES MGTRXPEOYS gt rem es mm EN MEN PERI 2 rem as X reme sam _ ww __ MGTRXPO_113 ___ 113 AK3 A2 NEN MGTTXNO_113 MGTTXP3_112 MGTTXN3 112 PERP3 ELEM zl E Lus EM NENNEN As MGIRXPA As 112 Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 3651 550T SX475T PCIEXP Hardware User s Manual 1 ee VI LIT ag MGTTXP2 112
18. 2908 05WB MG MODE Switch COPAL 5 7051 AREA Switch microSD Config Cotroller COPAL 5 7050 OSC SOMHz XC3S 700 FG484 AVX KC3225A Push Switch ALPS SKQYAA NAND FLASH x2 MICRON MT 29 4 16 FAN Power Puls sensor MODEpin Switc ST COPAL B3B XH A FAN Alarm CHS 04B Note The gray areas are supported by the TB 6VLX550T SX475T PCIEXP inreviun MMCX Connector Santec MMCX J P H ST TH Pair MMCX Connector Santec MMCX J P H ST TH MMCX Connector Santec Bee MMCX J P H ST TH Pair lt lt 7 ICS85411AM Pair MMCX Connector Pair Santec P H ST TH uu CLK Buffer Programmable CLK Pair IDT pap assasi IDT lt 7 ICS8S411AM CSg3PN625A X tal 25MH Abracon 8 25 000MHZ B2 OSC 266 667 lt 7 ON Semiconductor NBXSBAO2ILNITAG RS232C Buffer RS232 TI HARWN MAX3318E M20 9773646 5 GP VO 10 10pin FCI 95278 101A14LF System Monitor Connector Santec TMM 107 06 L D SM A CLK GTX 1pair 10 8pair GTX FMCI High pin count GC2pair 1O 34424420 pair Sarrtec ASP 134486 01 400pin lO 2pair GTX GC2pair IOX34424 pair Santec IO 20pair FMC3 Low pin count CLK GTX 1pair 10 1pair GTX Santec GC 2pair IO 34pair ASP 134603 01 160pin Level Shifter SPI FLASH TI Numonyx 108 25 128 VMF6 J TAG Connector MOLEX 878
19. 32 1420 Figure5 1 Block Diagram Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual inreviun ag 6 External View of the Board The following figures show the external views of the board Corfig Config 2 Gonnectar3 FPGA Monitor High DONE Low DONE GTA GLK FMG2 Power RE Config Input Power DI W Push SW LED POWER Carne FANPOWER HANDFLASH Config Config miero FPGA ano Gannectorl 65232 High 0806265 66M FMC1 Power PCI Exprese YTAG FPGA Backup Battery MMCX CLE Input Edge Config moda SYSTEM Monitor Config AREA Select Figure6 1 Component Side of the Board Config DDR3 SODIMM DDR3 SODIMM 2 OSC25M NANDFLASH Fl EA Ds IT Dr Ei w Figure6 2 Solder Side of the Board Rev 1 03 TOKYO ELECTRON DEVICE LIMITED 11 TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual 1 ee VI LIT ag 7 Board Specification External Dimensions W 300mm x H 130mm non compliance with PCI Express specification Number of Layers 16 Layers Board Thickness 1 7mm Material FR 4 FPGA Xilinx XCeVLX240T 365T 550T 2FFG1759 XC6VSX475T 2FFG1759 SPI FLASH Numonyx M25P128 VMF6 FMC Connector High Pin Samtec ASP 134486 01 FMC Connector Low Pin Samtec ASP 134603 01 DDR3 SO DIMM SanMax SMD N1G88 13H
20. 40T 365T LA 34Pair 72 HA 24 48 XC6VLX550T XC6VSX475T LA 34Pair 72 HA24Pair 48 HB 20 40 Table 3 shows the FMC2 connector pinout table for FPGA Table 3 FMC2 Connector Pinout Table BakNo Pnno a B _ BakNo mms EHS 2 17 7 meer gt wamxw2 17 Fe DeiMeCN wo 2 Pp 5 Dromen aee MGTRXN3 _ 17 65 Ku ew s _ ars n7 ppamece Iw __ ew hel s mames ne s 56 MOTRXN3 16 ne 15 p WwcP op LI MOTRXN2 116 te Damon 15 X 16 2 MGTRXPi 16 eme e S women s ne pswcP is op 116 Pa 095 19 Gv 20 MGTREFCLKOP 116 GND MGTREFCLKOP 116 M7 MGTREFCLKON_116_ eap DPiC2MN 23 GND M8 St 22 02 ______ a ARI egg i Pene ane werxe nz op LI Ha Eo ATS sssi x j ew l _ fate TT 063 30 L werxw n REGN se
21. 6 006 AN29 28 J ys j 28 28 DQ9 23 24 0913 25 23 Ns _ 25 26 Vs ______ Ns _ 31132 vs ______ ssf 37 38 vs 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 3651 550T SX475T PCIEXP Hardware User s Manual 1 ee VI LIT ag AR33 DQ17 41 42 DQ21 AJ26 23 0 2 0528 45 46 AW33 23 28 47 48 Vs 49 50 0922 AH26 23 28 AKe7 0019 53 54 Vs vs 55 56 0028 ATIG 33 88 4 59 60 Vs ______ 61 62 00538 33 ys 665 66 vs 38 17 0026 67 68 0030 17 33 88 18 69 70 0031 ATi7 3 ______ ys _ 71172 Ve nc 177 78 AW28 22 82 26 2 79 80 AW30 22 se 22 26 __ 12 _ 83 84 2 22 82 avai a9 85 86 7 22 77740877 87 WOOT 22 28 89 90 A6 _ 2 22 22 a we 0992 A4 201 22 v 193 94 L pase ___ ___ 9596 SS E ML IS NEM OM 99 100 VDD oe Lui zs 22 103 104 CKi amp AV28 22 22 AW3 aio 107 108 AN28 22
22. Drome DP7 C2M COMN 116 33 EE ES 36 warme ne 37 38 NN p NEN MEN NDS DP6 C2M N MGTTXN1_116 MGTTKPO 116 DP5 C2M P ep MGTTXNO 116 DPs ceMN 39 op 44 ms Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475T PCIEXP Hardware User s Manual I ee VI LIT ag www 9 0 am D wem nal oo e me ol 9 w d ze LA10_P LAO9 P LA10 N LAO9 4 5 Lee F LA13 P MGTREFCLKOP_117 9 MGTREFCLKON_117 LA14 LA13 N LA17 LA18 N CC LA23_P LA23 N LA27_P LA26 LA26_N IL IL IL IL IL IL N 1 03 TOKYO ELECTRON DEVICE LIMITED 25 TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual 1 um ag C NEN eet GND o Rev 1 03 TOKYO ELECTRON DEVICE LIMITED 26 TB 6V LX240T 365T 550T SX475T PCIEXP Hardware User s Manual inreviun ag e f ee _ 5 L ml zs L 2 L39 L40 CA O esch 5 sesch esch sch Oo o O
23. E LIMITED 33 TB 6V LX240T 365T 550T SX475T PCIEXP Hardware User s Manual I ee VI LIT ag 6 Power Supply The board provides a 12V to the 12POV pin and 3 3V to the 3P3V and pins 5V 3 3V and 2 5V are also selectable for VADJ pins as shown in Figure 8 14 Target pins G39 and H40 The power supply can be provided by short circuiting one portion of JP7 and JP8 respectively The power status can be monitored by the adjacent LED Caution Do not short circuit more than two portions of JP7 and JP8 respectively Short circuit the same portion of JP7 and JP8 45 OP 433 OP 25 VADJ JP7 JP8 TMM 103 06 L D SM TMM 103 06 L D SM 2 5V LED O FM VADJ AA1111C Q8 DTD113ZU BR1111C Q10 DTD113ZU DGND Figure8 13 VADJ Circuit Structure VREF A M2C The VREF A M2C terminal of the H1 pin can be monitored by the onboard TP113 test Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 3651 550T SX475T PCIEXP Hardware User s Manual 1 ee VI LIT B 8 4 DDR3 SO DIMM Interface The board provides two SanMax 1GByteDDR3 SO DIMM SMD N1G88 13H connectors Tables 5 and 6 show the pinout for FPGA Table 5 DDR3 SO DIMM 1 Pinout Table L1 1 2 vws 7 8 Ve ___ 9 10 poso H35 26 26 C89 i 12 0050 s35 26 __ ys j ves 26 B37 1516 006 237 26 26 A37
24. LX240T 365T LA 34Pair 72 HA 24Pair 48 HB 20 40 XC6VLX550T XC6VSX475T LA34Pair 72 HA24Pair 48 HB 20 40 Table 2 shows the FMC1 HPC connector pinout table for FPGA Table 2 FMC1 Connector Pinout x A B _ BakNo x j Jj 1 RE me ___ 115 ower op ___ 15 Re _ op j DP amp MeCP __ Aus Domon AUe wem _ 6 ppamece e op Mem ns va 7 ep DJ GND nl 111 Demen A8 _ ___ 16 ws ower 0 GNO ___ ns we DPS3MECN n 3 ss DP7_M2C_N 4 MGTRXNS 114 DP amp MCP d 3 GND ND _M2C_ ND _ 2 _ GND GND LL gl DP6 MGTRXP1 114 ll op Lil _ MOTRXN 4 GND Lodo a GND GND ND d A A MGTRXNO_114 DP5_M2C_N 20 MGTREFOLKOP 114 GND 20 GND fe Gp MN 2 op 5 p A ND ND oa _ ES EN MGTD 5 13 DP2CAMP E 7 3 4 8 7 MGTREFCLKON 114 DP1 COM P DP1 C2M N 2 MGTTXN1_115 DP2_C2M_N DP8 MGTTXPO 111 ws DP8_C2M_N MGTTXNO 111 MGTTXPO_115 D
25. O O O o J N 4 N J N lt Co C2 NIO SIS SO 2 OD lt Oo lt 23 Co Co Co Wa oO 7 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual 1 ee VI LIT ag ww 3 p __ ve ef w res memes oe LI p o e me CO CO N m N m K14 CA Wu Oo L14 AU23 024 N N gt N gt gt 03 W gt gt gt m rx elce lo IS S ale ale Gg 8 215 N E Y25 27 24 LI oo Ja 1 03 TOKYO ELECTRON DEVICE LIMITED 28 TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I ee VI LIT ag 1 RES1 0 It is connected to test point 2 SCL SDA Test point for 122 communication with the FMC mezzanine card Figure8 8 SDA SCL GA1 0 FMC1 JTAG Circuit Structure 3 GA 1 0 It is connected to test point 4 FMC2 JTAG TCK TMS TDI TDO TRST_L TDI and TDO have a loopback structure for JTAG communication from the FMC
26. P3_C2M_P MGTTXNO 115 DPS OAMN 31 ___ 32 DP7 2 GND GND GND GND A A P P T T U 3 GND 32 MGTTXP3 114 DP7 C2M N ew ___ tia AM 094 Gu Jr x Aw oan Gp LL mp Geer Ac o 7 REN 9 6 5 3 4 3 4 1 2 wemm aef man fo mb p Lee el mm Rev 1 03 TOKYO ELECTRON DEVICE LIMITED 17 TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I levi UT ag EN EM NE eet MGTRXP2 115 US DPO M2C P MGTRXNA2 115 us DPO M2C N V7 MGTREFCLKON 115 4 5 DINI sa E 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual 1 ee VI LIT ag Ime J 2 AG36 H36 gt L40 Ww sech N N N N N N N N N AR35 135 gt gt gt gt gt gt D gt gt gt gt gt gt gt gt 518 S S S t 1518 219 e N N e E V36 7 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475T PCIEXP Hardware User s Manual inreviun ag a 24 13 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T
27. ates the high possibility of serious injury or death if the product is handled Danger incorrectly Indicates the possibility of serious injury or death if the product is handled Warning incorrectly Indicates the possibility of injury or physical damage in connection with houses or Caution household goods if the product is handled incorrectly The following graphical symbols are used to indicate and classify precautions in this manual Examples Be sure to turn off the power switch Do not disassemble the product Do not attempt this Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 3651 550T SX475T PCIEXP Hardware User s Manual 1 ee VI LIT ag In the event of a failure disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately and contact our sales personnel for repair If an unpleasant smell or smoking occurs disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately After verifying that no smoking is observed contact our sales personnel for repair Do not disassemble repair or modify the product Otherwise a fire or electric shock may occur due to a short circuit or heat generation For inspection modification or repair contact our sales personnel Do not touch a cooling fan when installing it As a cooling fan rotates in high speed do not put
28. close to water or chemicals Otherwise a fire electric shock accident or deformation may occur due to a short circuit or heat generation Do not place heavy things on the product Otherwise the product may be damaged Disclaimer This product is the Xilinx Virtex6 FPGA evaluation board Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those stated Even if the product is used properly Tokyo Electron Device Limited assumes no responsibility for any damages caused by Earthquake thunder natural disaster or fire resulting from the use beyond our responsibility acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions Secondary impact arising from use of this product or its unusable state business interruption or others Use of this product against the instructions given in this manual or Malfunctions due to connection to other devices Tokyo Electron Device Limited assumes no responsibility or liability for Erasure or corruption of data arising from use of this product Any consequences or other abnormalities arising from use of this product or Damage of this product not due to our responsibility or failure due to modification This product has been developed by assuming its use for research testing or evaluation t is not authorized for use in any system or
29. ine box is supported by TB 6VLX550T SX475T PCIEXP Figure8 2 Clock Structure Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual 1 ee VI LIT ag Table 1 Details of Onboard Oscillator Name iF PCle 100M P N LVDS AK8 AK7 PIC Exress Edge via Difference Buffer LVDS Y8 Y7 MGT reference external clock CLK266M P N LVDS AY14 AY13 DDR3 IDelay clock LVDS AP11 AP12 MMOCX external clock MGT Reference Clock FPGA JC CLKO P N AD8 AD7 LVDS FPGA AV13 AV14 FPGA output clock 13 14 JC_CLK1_ P N AH8 AH7 Jitter cleaner 312 1 LVDS T8 T7 MGT Reference Clock GTX_312M 2 P N E10 E9 Clock Generator gt via Difference Buffer FMC1 GBTCLKO M2C P N LVDS AB8 AB7 FMC1 Gigabit data clock FMC1 GBTCLK1 M2C P N LVDS V8 V7 FMC1 Gigabit data clock FMC1 CLKO M2C P N LVDS AE30 AF30 FMC1 Reference Clock FMC1 J5 FMC1_CLK1_M2C_P N LVDS W30 V30 FMC1 Reference Clock FMC1_CLK2_M2C_P N LVDS AH34 AJ35 FMC1 Reference Clock FMC CLK M2C P N does not need to be LVDS differential Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475T PCIEXP Hardware User s Manual I ee VI LIT 8 3 Connector Interface This board has three Samtec FMC connectors High Pin Count 2 J5 6 Low Pin Count 1 J7 The following provides the pinout table Note that all HPC and LPC pins are not connected to the FPGA K H _ amp F E C B
30. ith Xilinx Virtex6 Series FPGA XCeVLX240T 365T 550T 2FFG1759 or XC6VSX475T 2FFG1759 4 Feature PCI Express Gen2 x8 interface High Pin Count FMC connector x 2 and Low Pin Count FMC connector 1 Due to limitation of the number of FPGA pins all the defined FMC connector pins are not connected For more information refer to the corresponding connector pinout table contained in this document DDR3 SO DIMM 1GB x 2 SanMax SMD N1G88 13H 1GByte x 2 1066Mbps Various clock sources For setting PushSWs DipSWs PinHeaders For monitoring LEDs Configuration via microSD Card Memory for CONFIG to support high speed configuration x 2 Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475T PCIEXP Hardware User s Manual 5 Block Diagram The following figure shows the block diagram of this board DDR3 50 1 _ CLKADDR CMD SanMax DATA 0 63 DQS DM SMD N1G88 13H DDR3 SO DIMM 2 1GByte CLK ADDR CMD SanMax DATA 0 63 DQS DM SMD N1G88 13H Push Switch x4 ALPS SKQYAA Dip Switch x8bit COPAL CHS 08B LED x8 Stanley BG1111C J PEN A TI Pair CDCE62002RHB 7 J ATTENUATOR IDT 22 FPGA ICS874001I 05 XCOVLX240T 365T 550T SX475T CLK Buffer 2 5 IDT 2FFG1759 Pair ICS85411AM Pair PCI Express Gen2 Edge x8 _ o A 8Pair microSD Connector 3M
31. mezzanine card and TMS TRST_L are used for test point only By default this loopback function is not provided because the R227 resistor is not installed 5 PG_C2M PG_M2C It is connected to the test point and the pull up resistor to the 3 3V power supply C GITO Ko Figure8 9 C2M PG 2 Circuit Structure 6 PRSNT_M2C is connected to the FPGA and the pull up resistor to the 2 5V power supply Rev 1 03 TOKYO ELECTRON DEVICE LIMITED 29 TB 6V LX240T 365T 550T SX475T PCIEXP Hardware User s Manual I levi um ag 7 Power Supply The board provides a 12V to the 12POV pin and a 3 3V to the 3P3V and pins 5V 3 3V and 2 5V are also selectable for VADJ pins as shown in Figure 8 11 Target pins are E39 F40 G39 and 40 The voltage supply can be provided by short circuiting one portion of JP5 and JP6 respectively The power status can be monitored by the adjacent LED Caution Do not short circuit more than two portions of JP5 and JP6 respectively Short circuit the same portion of JP5 and JP6 5V OP 33V 25 JP5 JP6 TMM 103 064 D SM TMM 103 064 D SM 2 5V LED 0 Figure8 10 VADJ Circuit Structure VIO B M2C The VIO B M2C terminal of the J39 and K40 pins can be monitored by the onboard TP111 test point VREF A M2C VREF B M2C The board provides TP107 test pad to monitor the VREF A 2 terminal of the H1 pin and the TP1
32. nfiguration using microSDCard and NandFlash Please see uSD CONF UserManual VePCIEX 1 02e pdf for more detail of microSDCard configuration Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual 1 ee VI LIT ag p TOKYO ELECTRON DEVICE PLD Solution Division URL http www inrevium jp eng x fpga board E mail psd support teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Japan 221 0056 TEL 81 45 443 4016 FAX 81 45 443 4058 Rev 1 03 TOKYO ELECTRON DEVICE LIMITED
33. nnector Low Pin Count a a 31 od DDR3 35 8 5 PCI Express Edge 40 66 R923920 UART WE REX 42 E 42 86 911111 _ ___ I 43 ANA LE ONA MZA _ YA 44 55410 PUGA xu x u 45 8 11 Power Connector Tor FAN E 46 8 12 L CO AI 46 EE 46 1 10101 00 200200 212000 vya wa wa wwa wwa uwa mwe ee eee IN 47 Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I ee VI LIT ag List of Figures 0 8 3 d Pe T o 10 Figure6 1 Component Side of the Board 11 Figure6 2 Solder Side of the Board 11 Figure7 1 Board DIMENSION DIA EE 12 Figure8 1 Power Supply Structure a 13 Fig reg 2 Clock ler EEN 14 Figure8 3 High Pin Cont Pin e 16 Figure8 4 Low Pin Cont Pin Layout 16 Figure8 5 SDA SCL GA1 0 FMC1 JTAG Circuit Structure 22 Figure8 6 PG C2M PG M20C Circuit Structure nnne nnns 22 Figure8 7 VADJ Circuit ___ d deu tassa 23 Figure8 8 SDA SCL GA1 0 FMC1 JTAG Circuit Structure 29 Figure8 9 PG_C2M PG_M2C Circuit Structure
34. ower supply input The power is provided through a 12V ATX power connector Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475 T PCIEXP Hardware User s Manual I ee VI LIT ag 8 2 Oscillator This board provides the following clock sources Ul FPGA AK amp MGTREFCLKP 112 J 10 P LXX X X X X X V8 MGTREFCLKP_115 B P EE V7 MGTREFCLKP 115 X X N AB8 MGTREFCLKP_114 AB7 MGTREFCLKP 114 cm P CLK Buffer ATTENUATOR AE30 Bank24 GC AF30 Bank24 GC GC 1 W30 Bank24 Y amp MGTREFCLKP 114 NGIXCLKINP 9 CX 3X 3X Eu pr Y7 MGTREFCLKN 114 DD dab dii GTX CLKIN N e K8 IMGTREFCLKP 116 35 Bank14 Eg AD2Bank15 AE32 Bank15 CLK Buffer Y3 T P AY 14 Bank34 GC 48 GIOMGTREFCLKP 117 266 667MHz G9 MGTREFCLKP 117 E M amp MGTREFCLKP 116 AP 11 Bank34 GC MZ MGTREFCLKP 116 e X X X X N AP12Bank34 GC U35 L12 Bank35 GC ADS amp MGTREFCLKP 113 M12 Bank35 GC AD7 MGTREFCLKN 113 E14 Bank35 GC AH8 MGTREFCLKP 112 F14 Bank35 GC V34 Bank16 U34 Bank16 7 7 P36 Bank1 P35 Bankl REF INP REF INN 7 R19 R216 FMC3 T amp MGTREFCLKP 115 P30 Bank25 TZ MGTREFCLKN 115 P3LBank25 10 117 42 Bank25 K42 Bank25 Note The portion in redl
35. ual I ee VI LIT ag 8 10 PUSHSW The board has four PUSHSWs When the PUSHSW is held down it generates Low on the associated FPGA pin Figure8 18 PUSHSW Structure Table 13 PUSHSW Pinout NU Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475T PCIEXP Hardware User s Manual I ee VI LIT ag 8 11 Power Connector for FAN This is a power supply connector for FAN It corresponds to the FAN sensor input and is connected to the CONFIG FPGA When the fan rotation is stopped the board generates Recon fig The Recon fig function can be enabled by setting the bit 4 of the CONFIG mode switch SW1 to ON or disabled by setting it to OFF Figure8 19 Power Connector for FAN Table 14 External Power Supply Connector Pinout Table 8 12 Battery Control The board has a battery control connector 913 is not installed by default mul lt Figure8 20 Battery Table 15 Battery Control signal Pinout Table Battery Input Connector 1 0 2 5V GND 8 13 SPI Flash The board has a 128Mbit SPI Flash memory All signals are connected to FPGA via level shifter U13 Table 16 SPI Flash Pinout Table SPI Flash FPGA Name Signal Name U12 Serial Data Output Q AC31 Data Input D 2 BY Rev 1 03 TOKYO ELECTRON DEVICE LIMITED TB 6V LX240T 365T 550T SX475T PCIEXP Hardware User s Manual inreviun 9 Configuration The board allows co
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