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DSP56374 Data Sheet - NXP Semiconductors

1. atchdog Timer Timing the high performance single clock per cycle DSP56300 family of programmable CMOS digital signal processors DSPs combined with the audio signal processing capability of the Freescale Semiconductor Inc Symphony DSP family as shown in Figure 1 Significant architectural enhancements include a barrel shifter 24 bit addressing and direct memory access oe Freescale Semiconductor Inc 2004 2005 2006 2007 All rights reserved freescale semiconductor Overview DMA The DSP56374 offers 150 million instructions per second MIPS using an internal 150 MHz clock Data Sheet Conventions This data sheet uses the following conventions Used to indicate a signal that is active when pulled low For example the RESET pin is active when low OVERBAR asserted Means that a high true active high signal is high or that a low true active low signal is low deasserted Means that a high true active high signal is low or that a low true active low signal is high Logic State Signal State Voltage PIN True Asserted Vit VoL PIN False Deasserted Vin PIN True Asserted Vou PIN False Deasserted Vit VoL Note Values for and Vor are defined by individual product specifications DSP56374 Data Sheet Rev 4 2 2 Freescale Semiconductor Features Y 6k x 24 2
2. Filter Figure A 2 52 pin Vdd Connections DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 55 Watchdog Timer Timing A 2 Package Information 2 1 80 Pin Package 2 MECHANICAL OUTLINES DOCUMENT NO 98ASS23237W freescale DICTIONARY PAGE 917A VERSONS UNCONTROLLED EXCEPT MEN ACCESSED FROM THE como eos verses DO NOT SCALE THIS DRAWING REV E SEATING Des 80 LD LOFP 14 X 14 PKG 0 65 MM PITCH 1 4 THICK DSP56374 Data Sheet Rev 4 2 56 Freescale Semiconductor Watchdog Timer Timing fe DOCUMENT NO 98ASS23237W E MECHANICAL OUTLINES gt n Se DIRECTLY FROM THE DOCUMENT CONTROL REROSTORY PRNTED VERSUNS DO NOT SCALE THIS DRAWING REV E SECTION R R ROTATED 90 CW 80 LD LQFP 14 X 14 PKG 0 65 MM PITCH 1 4 THICK DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 57 Watchdog Timer Timing Se 2 OUTLINES DOCUMENT NO 98ASS23237W PAGE 917A cu E DSL e aenea peg m MONTS RESERVED NOTES DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 CONTROLLING DIMENSION MILIMETER DATUM PLANE H IS LOCATED AT THE BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE DATUM E F AND D TO BE DETERMINED AT DATUM PLANE H DIMENSIONS TO BE DETERMINED AT SEATING PLANE C DIMENSIONS DO NO
3. 14 0 x ck ns deassertion 90 ick 89 FST input bl wr setup time before SCKT 2 0 x ck ns 6 edge 180 i ck 90 FST input wl setup time before SCKT 2 0 x ck ns edge 18 0 i ck 91 FST input hold time after SCKT edge 4 0 x ck ns 5 0 i ck 92 FST input wl to data out enable from high 21 0 ns impedance 93 FST input wl to transmitter 0 drive enable 14 0 ns assertion 94 Flag output valid after SCKT rising edge 14 0 x ck ns 9 0 i ck 95 HCKR HCKT clock cycle m 2XTc 13 4 ns 96 HCKT input edge to SCKT output 18 0 ns 97 HCKR input edge to SCKR output 18 0 ns Note 1 3 4 5 6 VCORE VDD 1 25 0 05 V Ty 40 C to 110 C 52 LQFP 40 C to 105 C 80 LQFP C 50 pF i ck internal clock x ck external clock ick a internal clock asynchronous mode asynchronous implies that SCKT and SCKR are two different clocks ick s internal clock synchronous mode synchronous implies that SCKT and SCKR are the same clock bl bit length wl word length wr word length relative SCKT SCKT pin transmit clock SCKR SCKR pin receive clock FST FST pin transmit frame sync FSR FSR pin receive frame sync HCKT HCKT pin transmit high frequency clock HCKR HCKR pin receive high frequency clock For the internal clock the external clock cycle is defined by Icyc and the ESAI c
4. 100 ns 24 Serial clock high period Master Bypassed 38 0 ns Very Narrow 38 0 ns Narrow 100 0 ns Wide 200 0 ns Slave Bypassed 2 0 19 6 33 0 ns Very Narrow 2 0x Tc 19 6 33 0 ns Narrow 2 0 x 86 6 100 0 ns Wide 2 0 x Tg 186 6 200 0 ns 25 Serial clock low period Master Bypassed 38 0 ns Very Narrow 38 0 ns Narrow 100 0 ns Wide 2000 ns Slave Bypassed 2 0 19 6 33 0 ns Very Narrow 2 0x Tc 19 6 33 0 ns Narrow 2 0 x 86 6 100 0 ns Wide 2 0 x To 186 6 200 0 ns 26 Serial clock rise fall time Master ns Slave 5 ns DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 35 Serial Host Interface SPI Protocol Timing Table 21 Serial Host Interface SPI Protocol Timing continued No Characteristics Mode Filter Mode Expression Min Max Unit 27 SS assertion to first SCK edge Slave Bypassed 2 0 x Tc 12 6 26 ns Very Narrow 2 0x Tc 2 6 16 ns CPHA 0 Narrow 2 0 37 48 0 ns Wide 2 0x To 87 45 0 ns CPHA 1 Slave Bypassed 10 ns Very Narrow 0 ns Narrow 0 E ns Wide 0 ns 28 Last SCK edge to SS not asserted Slave Bypassed 12 ns Very Narrow 22 ns Narrow 100 n
5. M y 2 0200505105 5 9 aa S Oo rm r iF 0 gt 6 Oo 6 6 HHT 6556509 o 0 t b t 6000 GPIO PG6 GPIO PG5 GPIO PG4 WDT TIO1 Core Vdd SCKT HCKR 1 PE2 HCKR PC2 HCKT 1 PES HCKT PC5 SCKR PCO SCKT 1 SCAN Core Gnd GPIO PG3 RESET B GPIO PG2 GPIO PG1 GPIO PGO Vdd PLLA Gnd SDO5_1_PE6 SDO4_1_PE7 SDO3 PC8 SDO2 PC9 SDO1 PC10 000_ 11 SDO3_1_PE8 5002 1 PE9 Core Vdd Core Gnd SDO 1 PE10 SDOO 1 PE11 PINIT_NMI IO Vdd XTAL EXTAL PLLD Vdd PLLD Gnd PLLP Gnd PLLP_Vdd 1 25 V Figure A 1 80 Pin Vdd Connections DSP56374 Data Sheet Rev 4 2 mum o Freescale Semiconductor MODA IRQA PHO MODB_IRQB_PH1 MODC_IRQC_PH2 MODD_IRQD_PH3 Core Vdd Core Gnd HREQ PH4 SS HA2 SCK SCL MISO SDA MOSI_HAO IO Gnd Watchdog Timer Timing i des sa Nw OQ 97086000 amp Rp E58 1 eo X x x xe 9 OU S t en 0 0 52 x 0 39 38 37 36 35 34 33 32 81 30 29 28 27 15 16 17 18 24 25 26 14 1 21 22 23 PLOCK TIO2 Core Vdd PLLA Vdd PLLA Gnd Core Gnd RESET B WDT TIO1 SDO3 PC8 5002 PC9 5001 PC10 5000 Core Vdd Core Gnd PINIT NMI XTAL EXTAL PLLD Vdd PLLD Gnd PLLP Gnd PLLP Vdd
6. 53 0 ns NMI edge trigger 8xTc 53 0 ns IRQ level trigger 12x Tc 80 0 ns 22 DMA Requests Rate Data read from ESAI ESAI 1 SHI 6xTc 400 ns Data write to ESAI ESAI 1 SHI 7XTc 46 7 ns Timer 2XTc 13 4 ns NMI edge trigger 3xTc 20 0 ns Note 1 when using fast interrupts and IRQA IRQB IRQC and IRQD are defined as level sensitive timings 19 through 21 apply to prevent multiple interrupt service To avoid these timing restrictions the Edge triggered mode is recommended when using fast interrupts Long interrupts are recommended when using Level sensitive mode 2 For PLL disable using external clock PCTL Bit 16 1 no stabilization delay is required and recovery time will be defined by the OMR Bit 6 settings For PLL enable if bet 12 of the PCTL register is 0 the PLL is shutdown during Stop Recovering from Stop requires the PLL to get locked The PLL lock procedure duration PLL Lock Cycles PLC may be in the range of 0 5 ms 5 Periodically sampled not 100 tested 4 RESET duration is measured during the time in which RESET is asserted Vpp is valid and the EXTAL input is active and valid When the Vpp is valid but the other required RESET duration conditions as specified above have not been yet met the device circuitry will be in an uninitialized state that can result in significant power consumption and heat up Designs should minimize this state
7. 61 0 MHz 55 SCL low to data out valid TvD DAT 3 4 0 9 us 56 Stop condition setup time Tsu sTo 4 0 0 6 us 57 HREQ in deassertion to last SCL edge tsu Rol 0 0 0 0 ns HREQ in set up time 58 First SCL sampling edge to HREQ output TNG RQO deassertion Filters bypassed 4X Tc 30 57 0 570 ns Very Narrow filters enabled 4X Tc 50 77 0 EE 67 0 ns Narrow filters enabled 4XTc 130 157 0 157 0 ns Wide filters enabled 4 230 257 0 257 0 ns 59 Last SCL edge to HREQ output not TAS RQO deasserted Filters bypassed 2 X Tc 4 30 44 44 ns Very Narrow filters enabled 2 X Tc 40 94 94 ns Narrow filters enabled 2 X 80 94 xd 94 ns e Wide filters enabled 2 130 144 x 144 ns 60 HREQ in assertion to first SCL edge TAS RQI Filters bypassed 4327 x 927 ns Very Narrow filters enabled 4317 917 ns Narrow filters enabled 4282 877 m ns Wide filters enabled 4227 827 ns 61 First SCL edge to HREQ is not asserted tHo Ral 0 0 0 0 ns HREQ in hold time DSP56374 Data Sheet Rev 4 2 42 Freescale Semiconductor Programming the Serial Clock Table 22 SHI 2 Protocol Timing continued Standard Standard Fast Mode Unit 5 tine 1 2 3 455 Symbol No Characteristics Expressi Min Max Min Max Note 1 VcoRE_VDD 1 25 0 05V Ty 40 C to 110
8. Signal Groupings Table 9 Serial Host Interface Signals continued Signal Name State during Signal Type Reset Signal Description MOSI Input or output Tri stated SPI Master Out Slave In When the SPI is configured as a master MOSI is the master data output line The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data MOSI is the slave data input line when the SPI is configured as a slave This signal is a Schmitt trigger input when configured for the SPI Slave mode HAO Input 2 Slave Address 0 This signal uses a Schmitt trigger input when configured for the 2 mode When configured for slave mode the HAO signal is used to form the slave device address HAO is ignored when configured for the 2 master mode This signal is tri stated during hardware software and individual reset Thus there is no need for an external pull up in this state This pin has an internal pull up resistor This input is 5 V tolerant SS Input Ignored Input SPI Slave Select This signal is an active low Schmitt trigger input when configured for the SPI mode When configured for the SPI Slave mode this signal is used to enable the SPI slave for transfer When configured for the SPI master mode this signal should be kept de asserted pulled high If it is asserted while configured as SPI master a bus error condition is flagged If SS is de asserted the SHI ignores SCK
9. 008 TIPS CS 0 2 008 T U M N 52 40 ELT ELEL EL ET TL EL ES EL EL L e VEN 4 EE cc 5 VIEN Y L UDOOGOUQULDJL EAD 000000 14 26 TITLE CASE NUMBER 848D 03 1 OF 4 60 Freescale Semiconductor Watchdog Timer Timing MECHANTGAL GUTLINES DOCUMENT 9845523228 scale DICTIONARY PARE eus WHEN ACCESSED yom DO NOT SCALE THIS DRAWING REV E BASE METAL F 252292252202 e 0 13 005 6 T L MS NG SECTION AB AB ROTATED 90 CLOCKWISE eX R RI 9 25 010 SAGE PLANE TITLE SeLD 10 X 10 RKG 065 PITCH b4 THICK PACKAGE cope DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 61 rrr Watchdog Timer Timing MECHANICAL OUTLINES DOCUMENT ND 98ASS23228W DICTIONARY PAGE ad NITE rm VERSIONS AFE UNCONTROLLED EXCEPT WEN stagen DO NOT SCALE THIS DRAWING REV E DIMENSIONS AND TOLERANCING PER ANSI Y14 5M 1982 CONTROLLING DIMENSION MILLIMETER DATUM PLANE IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE DATUMS TO BE DETERMINED AT DATUM PLANE DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE DIMENSIONS A AND DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION 15 0 25 010 PER SIDE DIME
10. 106 GPIO out rise time 13 0 ns 107 GPIO out fall time 13 0 ns Note 1 Vcore 1 25 V 0 05 V Ty 40 C to 110 C 52 LQFP 40 C to 105 C 80 LQFP C 50 pF PLL Disabled EXTAL driven by a square wave EXTAL uu DEM cu GPIO Output GPIO Output 4 NS Figure 17 GPIO Timing 19 JTAG Timing Table 27 JTAG Timing All frequencies No Characteristics Unit Min Max 108 TCK frequency of operation 1 Tc 3 maximum 10 MHz 10 0 MHz DSP56374 Data Sheet Rev 4 2 50 Freescale Semiconductor JTAG Timing Table 27 JTAG Timing continued All frequencies No Characteristics Unit Min Max 109 TCK cycle time in Crystal mode 100 0 ns 110 TCK clock pulse width measured at 1 65 V 50 0 ns 111 rise and fall times 3 0 ns 112 Boundary scan input data setup time 15 0 ns 113 Boundary scan input data hold time 24 0 ns 114 TCK low to output data valid 40 0 ns 115 TCK low to output high impedance 40 0 ns 116 TMS TDI data setup time 5 0 ns 117 TMS TDI data hold time 25 0 ns 118 TCK low to TDO data valid 44 0 ns 119 TCK low to TDO high impedance 44 0 ns Note 1 VconE vpp 1 25 V 0 05 V Ty 40 C to 110 C 52 LQFP 40 C to 105 C 80 LQFP C 50 pF 2 All timings apply to OnCE module data t
11. Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com DSP56374 Rev 4 2 1 2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters
12. 13 4 a ns 13 Syn reset deassert delay time Minimum 2x Tc 13 4 ns Maximum PLL enabled 2xTc TLock 5 0 ms 14 Mode select setup time 10 0 ns 15 Mode select hold time 10 0 ns 16 Minimum edge triggered interrupt request assertion 2 XTc 13 4 ns width 17 Minimum edge triggered interrupt request 2 XTc 13 4 mE ns deassertion width 18 Delay from interrupt trigger to interrupt code lOx To 45 72 ns execution 19 Duration of level sensitive IRQA assertion to ensure interrupt service when exiting Stop 2 3 PLL is active during Stop and Stop delay is 94 128x Tc 854 us enabled OMR Bit 6 0 e PLL is active during Stop and Stop delay is not 25x Tc 165 ns enabled OMR Bit 6 1 PLL is not active during Stop and Stop delay is 9 128 Ti ock 5 7 ms enabled OMR Bit 6 0 PLL is not active during Stop and Stop delay is 25 x Ti ock 5 ms not enabled OMR Bit 6 1 20 Delay from IRQA IRQB IRQC IRQD NMI 10x Tc 3 0 69 0 ns assertion to general purpose transfer output valid caused by first interrupt instruction execution DSP56374 Data Sheet Rev 4 2 32 Freescale Semiconductor Reset Stop Mode Select and Interrupt Timing Table 20 Reset Stop Mode Select and Interrupt Timing continued No Characteristics Expression Min Max Unit 21 Interrupt Requests Rate ESAI ESAI 1 SHI Timer 12 Tc 80 0 ns DMA 8xTc
13. 3V at Ty 25 C Maximum internal supply current is measured with VcoRE 1 30V VDD 3 46V at Ty 115 C 2 In order to obtain these results all inputs which are not disconnected at Stop mode must be terminated i e not allowed to float DSP56374 Data Sheet Rev 4 2 28 Freescale Semiconductor AC Electrical Characteristics 9 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with a maximum of 0 8 V and a minimum of 2 0 V for all pins AC timing specifications which are referenced to a device input signal are measured in production with respect to the 50 point of the respective input signal s transition DSP56374 output levels are measured with the production test machine Vor and Voy reference levels set at 1 0 V and 1 8 V respectively 10 Internal Clocks Table 18 INTERNAL CLOCKS No Characteristics Symbol Min Typ Max Unit Condition 1 Comparison Frequency Fref 5 20 MHz Fref FIN NR 2 Input Clock Frequency FIN Fref NR NR is input divider value 3 Output clock Frequency with FOUT 75 Ef x MF x FM 150 MHz _ FOUT FVCO NO where PLL enabled PDF x DF x OD NO is output divider value Tc 13 3 ns 4 Output clock Frequency with FOUT Ef 150 MHz PLL disabled 5 Duty Cycle 40 50 60 96 FVCO 300MHz 600MHz Note See users manual for def
14. 40 60 ns Narrow 3 0 x Tc 80 100 ns Wide 3 0 x Tc 120 150 ns 37 Last SCK sampling edge to HREQ output Slave Bypassed 4 0 X Tc 57 0 ns not deasserted CPHA 1 Very Narrow 4 0 x Tc 67 0 E ns Narrow 4 0 x Tc 1070 ns Wide 4 0 x Tc 157 0 ns 38 SS deassertion to HREQ output not Slave 3 0 x Tc 30 50 0 ns deasserted CPHA 0 39 SS deassertion pulse width CPHA 0 Slave 2 0 x Tc 13 4 ns 40 HREQ in assertion to first SCK edge Master Bypassed 0 5 X Tgpicc 63 ns 3 0 5 Very Narrow 0 5 x Tspicc 63 ns 3 0x Tc 5 Narrow 0 5 X Tgpicc 125 ns 3 0 5 Wide 0 5 x Tspicc 225 ns 3 0xTo 5 41 HREQ deassertion to last Master 0 ns sampling edge HREQ in set up time CPHA 1 42 First SCK edge to HREQ in not asserted Master 0 ns HREQ in hold time 43 HREQ assertion width Master 3 0 x Tc 20 ns Note 1 VCORE vpp 1 2 5 0 05 V Ty 40 C to 110 C 52 LQFP 40 C to 105 C 80 LQFP C 50 pF 2 Periodically sampled not 100 tested 3 All times assume noise free inputs All times assume internal clock frequency of 150 MHz 5 Equation applies when the result is positive DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 37 Serial Host Interface SPI Protocol Timing ss Input g s e SCK CPOL 0 N Output a SCK us a XX CSIRO QUE VND ON p
15. C 52 LQFP 40 C to 105 C 80 LQFP C 50 pF Pull up resistor R P min 1 5 kOhm 3 Capacitive load C max 50 pF All times assume noise free inputs 5 All times assume internal clock frequency of 150MHz 15 Programming the Serial Clock The programmed serial clock cycle is specified by the value of the HDM 7 0 and HRS bits of the HCKR SHI clock control register The expression for is Tc x 2 x HDM 7 0 1 x 7 x 1 HRS 1 Eqn 1 where HRS is the prescaler rate select bit When HRS is cleared the fixed divide by eight prescaler is operational When HRS is set the prescaler is bypassed HDM 7 0 are the divider modulus select bits A divide ratio from 1 to 256 HDM 7 0 00 to FF may be selected In PC mode the user may select a value for the programmed serial clock cycle from 6 x if HDM 7 0 02 and HRS 1 Eqn 2 to 4096 x Tc if HDM 7 0 FF and HRS 0 Eqn 3 The programmed serial clock cycle should be chosen in order to achieve the desired SCL serial clock cycle as shown in Table 23 Table 23 SCL Serial Clock Cycle Tsc_ Generated as Master Nominal 3x Tc 45ns TR DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 43 Enhanced Serial Audio Interface Timing SCL SDA Stop Start Figure 11 PC Timing 16 Enh
16. debugging JTAG port supporting boundary scan compliant to IEEE 1149 1 Very low power CMOS design fully static design with operating frequencies down to DC STOP and WAIT low power standby modes On chip Memory Configuration 6Kx24 Bit Y Data RAM and 4Kx24 Bit Y Data ROM 6Kx24 Bit X Data RAM and 4Kx24 Bit X Data ROM 20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism 6Kx24 Bit Program RAM Various memory switches are available See memory table below Table 1 DSP56374 Memory Switch Configurations Bit Settings Memory Sizes 24 bit words X X 0 6K 6K 6K 20K 4K 4K 0 0 1 2K 10K 6K 20K 4K 4K 0 1 1 4K 8K 6K 20K 4K 4K 1 0 1 8K 4K 6K 20K 4K 4K 1 1 1 10K 4K 4K 20K 4K 4K Peripheral Modules Enhanced Serial Audio Interface ESAD up to 4 receiver pins and up to 6 transmitter pins master or slave Ps Sony AC97 network and other programmable protocols Enhanced Serial Audio Interface I ESAI 1 up to 4 receiver pins and up to 6 transmitter pins master or slave 125 Sony AC97 network and other programmable protocols Note Available in the 80 package only Serial Host Interface SHI SPI and re protocols 10 word receive FIFO support for 8 16 and 24 bit words Three noise reduction filter modes Triple Timer module TEC Most pins of unused peripherals may be programmed as GPIO pins Up to 47 pins can be configured as GPIO on the 80 pin package and 20 pin
17. internal pull up resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 12 Freescale Semiconductor Signal Groupings Table 10 Enhanced Serial Audio Interface Signals continued Signal Name Signal Type State during Reset Signal Description FSR PC1 Input or output Input output or disconnected GPIO disconnected Frame Sync for Receiver This is the receiver frame sync input output signal In the asynchronous mode SYN 0 the FSR pin operates as the frame sync input or output used by all the enabled receivers In the synchronous mode SYN 1 it operates as either the serial flag 1 pin TEBE 0 or as the transmitter external buffer enable control TEBE 1 RFSD 1 When this pin is configured as serial flag pin its direction is determined by the RFSD bit in the RCCR register When configured as the output flag OF 1 this pin will reflect the value of the OF 1 bit in the SAICR register and the data the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode When configured as the input flag IF1 the data value at the pin will be stored in the IF1 bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode Port C1 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset i
18. is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PG12 Input GPIO Port G12 This signal is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PG13 Input GPIO Port G13 This signal is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PG14 Input GPIO Port G14 This signal is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 23 Signal Groupings 4 10 Timer Table 13 Timer Signal Signal State 9 during Signal Description Name Reset TIOO Input or GPIO Input Timer 0 Schmitt Trigger Input Output When timer 0 functions as Output external event counter or in measurement mode TIOO is used as input When timer 0 functions in watchdog timer or pulse modulation mode TIOO is used as output The default mode after reset is GPIO input This can be changed to output or configured as a timer input output through the timer 0 control status register TCSRO If TIOO is not bein
19. that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the proper
20. 0 3 to 1 6 V VPLLD_VDD VPLLP_VDD Vio vpD 0 3 to 4 0 V VPLLA VDD Maximum CORE VDD power supply ramp time Tr 10 ms All 5 0V tolerant input voltages Vin GND 0 3 to 6V V Current drain per pin excluding Vpp and GND Except 12 mA for pads listed below SCK_SCL Isck 16 mA TDO 1 24 Operating temperature range Ty 80 LQFP 105 C 52 LQFP 110 Storage temperature TsrG 55 to 125 x ESD protected voltage Human Body Model 2000 ESD protected voltage Machine Model 200 Note 1 GND 0 V Ty 40 to 110 C 52 LQFP 40 C to 105 C 80 LQFP CL 50pF 2 Absolute maximum ratings are stress ratings only and functional operation at the maximum is not guaranteed Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device 9 Operating temperature qualified for automotive applications Ty TA 8 ja x Power Variables used were Core Current 100 mA I O Current 60 mA Core Voltage 1 3 V I O Voltage 3 46 V TA 85 C 4 If the power supply ramp to full supply time is longer than 10 ms the POR circuitry will not operate correctly causing erroneous operation 6 Power Requirements To prevent high current conditions due to possible improper sequencing of the power supplies the connection shown below is recommended to be made between the DSP56374 IO VDD and Core VDD power pins DSP56374 Data Sheet Rev 4 2 26 Freescale Semiconductor Thermal Char
21. 7 Enhanced Serial Audio Interface Table 10 Enhanced Serial Audio Interface Signals State during Reset Signal Description Signal Name Signal Type HCKR Input or output GPIO High Frequency Clock for Receiver When programmed disconnected as an input this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock When programmed as an output this signal can serve as a high frequency sample clock e g for external digital to analog converters DACs or as an additional system clock PC2 Input output or Port C2 When the ESAI is configured as GPIO this signal disconnected is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This pin has an internal pull up resistor This input is 5 V tolerant HCKT Input or output GPIO High Frequency Clock for Transmitter When programmed disconnected as an input this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock When programmed as an output this signal can serve as a high frequency sample clock e g for external DACS or as an additional system clock PC5 Input output or Port C5 When the ESAI is configured as GPIO this signal disconnected is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This pin has an
22. Core Core VDD PLL PLLD_VDD Supply voltages Vppio 3 14 3 3 3 46 V I O IO VDD e PLL PLLP VDD PLL PLLA VDD Input high voltage V All pins 2 0 Vio vpp 2V Note All 3 3 V supplies must rise prior to the rise of the 1 25 V supplies to avoid a high current condition and possible system damage Input low voltage All pins Vit 0 3 ES 0 8 V Input leakage current lin 84 Clock pin Input Capacitance EXTAL Cin 4 7 pF High impedance off state input current 3 46V 10 84 Output high voltage Vou 24 V s loH 5 mA XTAL Pin lop 10 Output low voltage VoL 0 4 V lot 5mA XTAL Pin lo 10 mA Internal supply current core only at internal clock of 150 MHz n Normal mode 65 100 mA In Wait mode Iccw DE 16 mA In Stop mode lccs 1 2 mA Input capacitance Cin 10 pF Note The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode In order to obtain these results all inputs must be terminated i e not allowed to float Measurements are based on synthetic intensive DSP benchmarks The power consumption numbers in this specification are 90 of the measured results of this benchmark This reflects typical DSP applications Typical internal supply current is measured with Vcore vpp 1 25V Vpp jo 3
23. Freescale Semiconductor DSP56374 Data Sheet Technical Data Rev 4 2 1 2007 DSP56374 Data Sheet 1 Overview Table of Contents 1 The DSP56374 is a high density CMOS device with 2 OON Ce Pre 3 2 DocurnentalloD c sese 5 3 3 V inputs and outputs 4 Signal gt e tas 5 5 25 6 Power Requirements 26 This document contains information on 7 Thermal Characteristics 27 new product Specifications and 8 DC Electrical Characteristics 28 information herein are subject to change 9 AC Electrical Characteristics 29 ith T0 ERAS ORARE 29 without notice 11 External Clock Operation 29 12 Reset Stop Mode Select and Interrupt Timing 32 porca HELTAH OR NOGETS LUE 13 Serial Host Interface SPI Protocol Timing 35 example IBIS files contact sales or go 14 Serial Host Interface SHI Protocol Timing 41 to www freescale com 15 Programming the Serial Clock 43 TN 16 Enhanced Serial Audio Interface Timing 44 The DSP56374 supports digital audio applications 17 TimerTiming 49 requiring sound field processing acoustic equalization 18 0 50 and other digital audio algorithms The DSP56374 uses e E sels d
24. Interface SHI 2 Protocol Timing Table 22 SHI IC Protocol Timing Standard Standard Fast Mode Unit No Characteristics 12345 ES XX Tolerable Spike Width on SCL or SDA m Filters Bypassed 0 0 ns Very Narrow Filters enabled 10 10 ns Narrow Filters enabled m 50 50 ns Wide Fileters enabled 100 100 ns 44 SCL clock frequency FscL 100 x 400 kHz 44 SCL clock cycle 10 2 5 us 45 Bus free time Taur 4 7 1 3 us 46 Start condition set up time TsusTA 4 7 0 6 us DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 41 Serial Host Interface SHI PC Protocol Timing Table 22 SHI 2 Protocol Timing continued Standard Standard Fast Mode Unit No Characteristics 1 2345 LO 47 Start condition hold time THD STA 4 0 0 6 us 48 SCL low period Tiow 4 7 1 3 us 49 SCL high period THIGH 4 0 1 3 us 50 SCL and SDA rise time TR 5 0 5 0 ns 51 SCL and SDA fall time TF 5 0 5 0 ns 52 Data set up time TSU DAT 250 100 ns 53 Data hold time Tup DAT 0 0 0 0 0 9 us 54 DSP clock frequency Fosc Filters bypassed 10 6 28 5 MHz Very Narrrow filters enabled 10 6 28 5 MHz Narrow filters enabled 11 8 39 7 MHz Wide filters enabled 13 1
25. Master In Slave Out When the SPI is configured as a master MISO is the master data input line The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data This signal is a Schmitt trigger input when configured for the SPI Master mode an output when configured for the SPI Slave mode and tri stated if configured for the SPI Slave mode when SS is de asserted An external pull up resistor is not required for SPI operation 2 Data and Acknowledge In 2 mode SDA is a Schmitt trigger input when receiving and an open drain output when transmitting SDA should be connected to Vpp through a pull up resistor SDA carries the data for transactions data SDA must be stable during the high period of SCL The data in SDA is only allowed to change when SCL is low When the bus is free SDA is high The SDA line is only allowed to change during the time SCL is high in the case of start and stop events A high to low transition of the SDA line while SCL is high is a unique situation and is defined as the start event A low to high transition of SDA while SCL is high is a unique situation defined as the stop event This signal is tri stated during hardware software and individual reset Thus there is no need for an external pull up in this state This pin has an internal pull up resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 10 Freescale Semiconductor
26. Mode Select TMS is an input signal used to sequence the test controllers state machine TMS is sampled on the rising edge of TCK Internal Pull up resistor This input is 5 V tolerant 5 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields However normal precautions should be taken to avoid exceeding maximum voltage ratings Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level e g either GND or Vpp The suggested value for a pullup or pulldown resistor is 4 7 DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 25 Power Requirements NOTE In the calculation of timing requirements adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum A maximum specification is calculated using a worst case variation of process parameter values in one direction The minimum specification is calculated using the worst case for the same parameters in the opposite direction Therefore a maximum value for a specification will never occur in the same device that has a minimum value for another specification adding a maximum to a minimum represents a condition that can never exist Table 15 Maximum Ratings Rating Symbol Value 2 Unit Supply Voltage VCORE VDD
27. NSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0 46 018 MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0 07 003 MILLIMETERS INCHES MILLIMETERS INCHES MIN MAX MIN MAX MIN MAX MIN MAX E cUunZxcomm 10 10 PKG 0 65 PITCH 1 4 THICK PACKAGE CODE 8260 DSP56374 Data Sheet Rev 4 2 62 Freescale Semiconductor Watchdog Timer Timing DOCUMENT NO 98ASS23228W PAGE 848D ORIGINATOR REVISIONS DRAFTER E PATRICE L UPDATED DRAWNGS PER FREESCALE FORMAT KL CHIN 7 OCT 2004 ADDED REVISION HISTORY PAGE TITLE CASE NUMBER 848D 03 52LD TQFP STANDARD FREESCALE us en p pug Ce PACKAGE CODE 8260 SHEET 4 OF 4 DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 63 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com
28. PIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant HCKT_1 PE5 Input or output Input output or disconnected GPIO disconnected High Frequency Clock for Transmitter When programmed as an input this signal provides a high frequency clock source for the ESAI_1 transmitter as an alternate to the DSP core clock When programmed as an output this signal can serve as a high frequency sample clock e g for external DACs or as an additional system clock Port E5 When the ESAI 1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 17 Signal Groupings Table 11 Enhanced Serial Audio Interface_1 Signals continued Signal Name Signal Type State during Reset Signal Description FSR_1 PE1 Input or output Input output or disconnected GPIO disconnected Frame Sync for Receiver_1 This is the receiver frame sync input output signal In the asynchronous mode SYN 0 the FSR_1 pin operates as the frame sync input or output used by all the enabled receivers In the synchronous mode SYN 1 it op
29. State during Reset Signal Description SDO5 SDIO PC6 Output Input Input output or disconnected GPIO disconnected Serial Data Output 5 When programmed as a transmitter SDO5 is used to transmit data from the TX5 serial transmit shift register Serial Data Input O When programmed as a receiver 5010 is used to receive serial data into the serial receive shift register Port C6 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant SDO4 SDI1 PC7 Output Input Input output or disconnected GPIO disconnected Serial Data Output 4 When programmed as a transmitter SDOA is used to transmit data from the TX4 serial transmit shift register Serial Data Input 1 When programmed as a receiver SDI1 is used to receive serial data into the RX1 serial receive shift register Port C7 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant 003 012 8 Output Input Input output or disconnected GPIO disconnected Serial Data Output 3 When programmed as a transmitter SDO3 is used t
30. T INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 25 PER SIDE DIMENSIONS DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0 46 MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0 07 TITLE 80 LD LQFP 14 X 14 PKG STANDARD FREESCALE 0 65 MM PITCH 1 4 THICK PACKAGE CODE 8258 SHEET 3 OF 4 CASE NUMBER 917 03 DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor Watchdog Timer Timing j gt freescale 7 froescale REVISION HISTORY ELECTRONIG VERSIONS ARE UNCONTROLLED EXCEPT AEN ACCESSED Lene e m sss GARY JOHNSON REFORMAT DOCUMENT DELETED DUAL DIMENSIONS INCH AZHAR A 11 MAR 2004 CHANGED DOCUMENT TITLE FROM TOFP TO LQFP E PAREL UPDATED DRAWNGS PER FREESCALE FORMAT 7 OCT 2004 80 LQFP 14 X 14 PKG Bia M PITOA LE THIR DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 59 Watchdog Timer Timing A 2 2 52 Package gt MECHANICAL OUTLINES DOCUMENT 98ASS23228W 2 freescale DICTIONARY NX VERSIONS ARE UNCONTEDLIED EXCEPT ween DO NOT SCALE THIS DRAWING REV U SEATING PLANE SeLD TQFP STANDARD FREESCALE 10 X 10 PKG 0 65 PITCH 1 4 THICK DSP56374 Data Sheet Rev 4 2 0 2
31. acteristics External Schottky Diode Core_VDD To prevent a high current condition upon power up the IO VDD must be applied ahead of the Core VDD as shown below if the external Schottky is not used Core VDD lO VDD For correct operation of the internal power on reset logic Core_VDD ramp rate Tr to full supply must be less than 10 ms This is shown below Tr 1 25 V OV Core_VDD 7 Thermal Characteristics Table 16 Thermal Characteristics Characteristic Symbol LQFP Values Unit Natural Convection Junction to ambient thermal Roya Or Oya 68 52 LQFP C W resistance 50 80 LQFP Junction to case thermal resistance Rouc OF Oje 17 52 LQFP C W 11 80 LQFP Note 1 Junction temperature is a function of die size on chip power dissipation package thermal resistance mounting site board temperature ambient temperature air flow power dissipation of other components on the board and board thermal resistance Per SEMI G38 87 and JEDEC JESD51 2 with the single layer board horizontal 3 Thermal resistance between the die and the case top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 27 DC Electrical Characteristics 8 DC Electrical Characteristics Table 17 DC Electrical Characteristics Characteristics Symbol Min Typ Max Unit Supply voltages Vpp 1 2 1 25 1 3 V
32. anced Serial Audio Interface Timing Table 24 Enhanced Serial Audio Interface Timing No Characteristics 2 3 Symbol Expression Min Max Condition Unit 62 Clock cycle tssicc 4 6 264 x ck ns 4x Tc 264 i ck 63 Clock high period tssiccH ns For internal clock 2 7 0 5 12 8 For external clock 2 X Tc 13 4 64 Clock low period tssiccL ns For internal clock 2 6 13 4 For external clock 2 6 13 4 65 SCKR edge to FSR out bl high 17 0 x ck ns 7 0 icka 66 SCKR edge to FSR out bl low 17 0 X ck ns 7 0 icka 67 SCKR edge to FSR out wr high 19 0 ck ns 9 0 icka 68 SCKR edge to FSR out wr low 19 0 x ck ns 9 0 icka 69 SCKR edge to FSR out wl high 16 0 x ck ns 6 0 icka DSP56374 Data Sheet Rev 4 2 44 Freescale Semiconductor Enhanced Serial Audio Interface Timing Table 24 Enhanced Serial Audio Interface Timing continued No Characteristics 2 3 Symbol Expression Min Max Condition Unit 70 SCKR edge to FSR out wl low 17 0 x ck ns 7 0 icka 71 Data in setup time before SCKR SCK in 12 0 x ck ns synchronous mode edge 19 0 ick 72 Data in hold time after SCKR edge 3 5 x ck ns 9 0 i ck 73 FSR input bl
33. as the output flag OFO this pin will reflect the value of the OFO bit in the SAICR register and the data in the OFO bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode When configured as the input flag IFO the data value at the pin will be stored in the IFO bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode PCO Input output or Port CO When the ESAI is configured as GPIO this signal disconnected is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant SCKT Input or output GPIO Transmitter Serial Clock This signal provides the serial bit disconnected rate clock for the ESAI SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode or by all enabled transmitters in asynchronous mode PC3 Input output or Port C3 When the ESAI is configured as GPIO this signal disconnected is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 14 Freescale Semiconductor Signal Groupings Table 10 Enhanced Serial Audio Interface Signals continued Signal Name Signal Type
34. clocks and keeps the MISO output signal in the high impedance state HA2 Input 2 Slave Address 2 This signal uses a Schmitt trigger input when configured for the IZC mode When configured for the 2 Slave mode the HA2 signal is used to form the slave device address HA2 is ignored in the 2 master mode This pin has an internal pull up resistor This input is 5 V tolerant HREQ Input Output Tri stated Host Request This signal is an active low Schmitt trigger input when configured for the master mode but an active low output when configured for the slave mode When configured for the slave mode HREQ is asserted to indicate that the SHI is ready for the next data word transfer and de asserted at the first clock pulse of the new data word transfer When configured for the master mode HREQ is an input When asserted by the external slave device it will trigger the start of the data word transfer by the master After finishing the data word transfer the master will await the next assertion of HREQ to proceed to the next transfer This pin can also be programmed as GPIO PH4 Input output or Port H4 When HREQ is configured as GPIO this signal is individually disconnected programmable as input output or internally disconnected This pin has an internal pull up resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 11 Signal Groupings 4
35. d This pin has an internal pull up resistor This input is 5 V tolerant PH1 Input output Port H1 When the MODB IRQB is configured as GPIO this signal is or individually programmable as input output or internally disconnected disconnected MODC IRQC Input Mode Select C External Interrupt Request C MODC IRQC is an Input active low Schmitt trigger input internally synchronized to the DSP clock MODC IRQC selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing This pin can also be programmed as GPIO MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into OMR when the RESET signal is de asserted This pin has an internal pull up resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 8 Freescale Semiconductor Signal Groupings Table 8 Interrupt and Mode Control continued Signal Name PH2 Type Input output or disconnected State during Reset Signal Description Port H2 When the MODC IRQC is configured as GPIO this signal is individually programmable as input output or internally disconnected MODD IRQD PH3 Input Input output or disconnected MODD Input Mode Select D External Interrupt Request D MODD IRQD is an active low Schmitt trigger input internally
36. e MOSI MSB LSB Output HREQ Input Figure 7 SPI Master Timing CPHA 0 DSP56374 Data Sheet Rev 4 2 38 Freescale Semiconductor Serial Host Interface SPI Protocol Timing ss Input 5 SCK CPOL 0 Output ae SCK CPOL 1 Output ate 7225 L IU em MOSI Output HREQ Input Figure 8 SPI Master Timing CPHA 1 DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 39 Serial Host Interface SPI Protocol Timing SS Input er SCK CPOL 0 Input SCK CPOL 1 Input MISO Output MOSI Input HREQ Output lt Omg 26 Pa lt 23 28 gt lt lt s GH ee a ue quel OAK vara 6 34 X MSB X 30 89 4 OE TT ee vaia Figure 9 SPI Slave Timing CPHA 0 DSP56374 Data Sheet Rev 4 2 40 Freescale Semiconductor SCK CPOL 0 SCK CPOL 1 14 Serial Host Interface SHI C Protocol Timing ss N Input Input Input MISO Output MOSI Input vais QUU HREQ Output Figure 10 SPI Slave Timing CPHA 1 Serial Host
37. ected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant SCKT_1 PES Input or output Input output or disconnected GPIO disconnected Transmitter Serial Clock 1 This signal provides the serial bit rate clock for the ESAI 1 SCKT 1 is a clock input or output used by all enabled transmitters and receivers in synchronous mode or by all enabled transmitters in asynchronous mode Port E3 When the ESAI_1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 19 Signal Groupings Table 11 Enhanced Serial Audio Interface_1 Signals continued State during Signal Name Signal Type Reset Signal Description SDO5_1 Output GPIO Serial Data Output 5_1 When programmed as a disconnected transmitter SDO5_1 is used to transmit data from the TX5 serial transmit shift register SDIO_1 Input Serial Data Input 0 1 When programmed as a receiver SDIO 1 is used to receive serial data into the RXO serial receive shift register PE6 Input output or Port E6 When the ESAI_1 is configured as GPIO this disconnected signal is individually programmable as input output or internally disconnected The defa
38. eee DEI Lj 14 k u r Jp SSS Sa ROM Memory Expansion Area SHI GPIO ESAI ESAL1 Triple Interface Interface Interface Timer Program RAM 20k x 24 Peripheral Expansion Area Address Generation Internal Data Switch Do C CL j os Mgmt Glock Data ALU 1 Program ke Program ke Program 7 I ty Decode 1 Address 24 x 24 5656 bit OHIO Controller Generator Two 56 bit Accumulators 56 bit Barrel Shifter MODA IRQA GPIO MODB IRQB GPIO SEI MODC IRQC GPIO PINIT NMI MODD IRQD GPIO ESAI_1 and dedicated GPIO pins are not available in the 52 pin package Figure 1 DSP56374 Block Diagram 2 Features 2 1 DSP56300 Modular Chassis 150 Million Instructions Per Second MIPS with a 150 MHz clock at an internal logic supply QVDDL of 1 25 V Object Code Compatible with the 56K core Data ALU with a 24 x 24 bit multiplier accumulator and a 56 bit barrel shifter 16 bit arithmetic support Program Control with position independent code support DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 3 Features 2 3 Six channel DMA controller Provides a wide range of frequency multiplications 1 to 255 predivider factors 1 to 31 PLL feedback multiplier 2 or 4 Output divide factor 1 2 or 4 and a power saving clock divider 21 i 0 to 7 to reduce clock noise Internal address tracing support and OnCE for Hardware Software
39. eiver Timing DSP56374 Data Sheet Rev 4 2 48 Freescale Semiconductor Timer Timing HCKT SCKT output 95 Note Figure 14 is drawn assuming positive polarity high frequency clock THCKP 0 and positive bit clock polarity TCKP 0 Figure 14 ESAI HCKT Timing HCKR SCKR output 55 Note Figure 15 is drawn assuming positive polarity high frequency clock RHCKP 0 and positive bit clock polarity RCKP 0 Figure 15 ESAI HCKR Timing 17 Timer Timing Table 25 Timer Timing 150 MHz No Characteristics Expression Unit Min Max 98 TIO Low 2xTc 2 0 15 4 ns 99 TIO High 2x Tc 2 0 15 4 ns Note Vcore vpp 1 25 V 0 05 V Ty 40 C to 110 C 52 LQFP 40 C to 105 C 80 LQFP C 50 pF TIO Laon a S Figure 16 TIO Timer Event Input Restrictions DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 49 GPIO Timing 18 GPIO Timing Table 26 GPIO Timing No Characteristics Expression Min Max Unit 100 EXTAL edge to GPIO out valid GPIO out delay time 7 ns 101 EXTAL edge to GPIO out not valid GPIO out hold time 7 ns 102 GPIO In valid to EXTAL edge GPIO in set up time 2 ns 103 EXTAL edge to GPIO in not valid GPIO in hold time 0 ns 104 Minimum GPIO pulse high width Tc 13 19 7 ns 105 Minimum GPIO pulse low width 13 19 7 ns
40. erates as either the serial flag 1 pin TEBE 0 or as the transmitter external buffer enable control TEBE 1 RFSD 1 When this pin is configured as serial flag pin its direction is determined by the RFSD bit in the RCCR_1 register When configured as the output flag OF 1 this pin will reflect the value of the OF1 bit in the SAICR_1 register and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode When configured as the input flag IF1 the data value at the pin will be stored in the IF1 bit in the SAISR_1 register synchronized by the frame sync in normal mode or the slot in network mode Port E1 When the ESAI_1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant FST 1 PE4 Input or output Input output or disconnected GPIO disconnected Frame Sync for Transmitter_1 This is the transmitter frame sync input output signal For synchronous mode this signal is the frame sync for both transmitters and receivers For asynchronous mode FST_1 is the frame sync for the transmitters only The direction is determined by the transmitter frame sync direction TFSD bit in the ESAI_1 transmit clock control register TCCR_1 Port E4 When the ESAI_1 is configured as GPIO this
41. ft register Port C10 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant SDOO PC11 Output Input output or disconnected GPIO disconnected Serial Data Output 0 SDO O is used to transmit data from the TXO serial transmit shift register Port C11 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 16 Freescale Semiconductor Signal Groupings 4 8 Enhanced Serial Audio Interface_1 Table 11 Enhanced Serial Audio Interface_1 Signals Signal Name Signal Type State during Reset Signal Description HCKR_1 PE2 Input or output Input output or disconnected GPIO disconnected High Frequency Clock for Receiver When programmed as an input this signal provides a high frequency clock source for the ESAI_1 receiver as an alternate to the DSP core clock When programmed as an output this signal can serve as a high frequency sample clock e g for external digital to analog converters DACs or as an additional system clock Port E2 When the ESAI_1 is configured as G
42. g used it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input Internal Pull down resistor This input is 5 V tolerant TIO1 Input or Watchdog Timer 1 Schmitt Trigger Input Output When timer 1 functions as an Output Timer external event counter or in measurement mode TIO1 is used as input Output When timer 1 functions in watchdog timer or pulse modulation mode TIO1 is used as output The default mode after reset is GPIO input This can be changed to output or configured as a timer input output through the timer 1control status register TCSR1 If TIO1 is not being used it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input WDT Output WDT When this pin is configured as a hardware watchdog timer pin this signal is asserted low when the hardware watchdog timer counts down to zero Internal Pull down resistor This input is 5 V tolerant TIO2 Input or PLOCK Timer 2 Schmitt Trigger Input Output When timer 2 functions as an Output Output external event counter or in measurement mode TIO2 is used as input When timer 2 functions in watchdog timer or pulse modulation mode 2 is used as output The default mode after reset is GPIO input This can be changed to output or configured as a timer input output through the timer control status register TCSR2 If TIO2 is not being u
43. gnal Groupings Table 9 Serial Host Interface Signals Signal Name Signal Type State during Reset Signal Description SCK SCL Input or output Input or output Tri stated SPI Serial Clock The SCK signal is an output when the SPI is configured as a master and a Schmitt trigger input when the SPI is configured as a slave When the SPI is configured as a master the SCK signal is derived from the internal SHI clock generator When the SPI is configured as a slave the SCK signal is an input and the clock signal from the external master synchronizes the data transfer The SCK signal is ignored by the SPI if it is defined as a slave and the slave select SS signal is not asserted In both the master and slave SPI devices data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable Edge polarity is determined by the SPI transfer protocol 2 Serial Clock SCL carries the clock for 1 C bus transactions in the mode SCL is a Schmitt trigger input when configured as a slave and an open drain output when configured as a master SCL should be connected to Vpp through an external pull up resistor according to the I C specifications This signal is tri stated during hardware software and individual reset This pin has an internal pull up resistor This input is 5 V tolerant MISO SDA Input or output Input or open drain output Tri stated SPI
44. grammable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PG6 Input GPIO Port G6 This signal is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PG7 Input GPIO Port G7 This signal is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PG8 Input GPIO Port G8 This signal is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 22 Freescale Semiconductor Signal Groupings Table 12 Dedicated GPIO Port G Signals continued 1 eet ing Signal Description PG9 Input GPIO Port G9 This signal is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PG10 Input GPIO Port G10 This signal is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PG11 Input GPIO Port G11 This signal
45. in This pin must be connected to ground 4 4 Clock and PLL Table 7 Clock and PLL Signals Signal stele 9 during Signal Description Name Reset EXTAL Input Input External Clock Crystal Input An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL XTAL Output Chip Driven Crystal Output Connects the internal Crystal Oscillator output to an external crystal If an external clock is used leave XTAL unconnected PINIT NMI Input Input PLL Initial Nonmaskable Interrupt During assertion of RESET the value of PINIT NMI is written into the PLL Enable PEN bit of the PLL control register determining whether the PLL is enabled or disabled After RESET de assertion and during normal instruction processing the PINIT NMI Schmitt trigger input is a negative edge triggered nonmaskable interrupt NMI request internally synchronized to the internal system clock This pin has an internal pull up resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor Signal Groupings 4 5 Interrupt and Mode Control The interrupt and mode control signals select the chip s operating mode as it comes out of hardware reset After RESET is de asserted these inputs are hardware interrupt request lines Table 8 Interrupt and Mode Control State Signal Name Type during Signal Descripti
46. inition DF Division Factor Ef External Frequency Mf Multiplication Factor PDF Predivision Factor FM Frequency Multiplier OD Output Divider Tc Internal Clock Period 3 Maximum frequency will vary depending on the ordered part number 11 External Clock Operation The DSP56374 system clock is derived from the on chip oscillator or is externally supplied To use the on chip oscillator connect a crystal and associated resistor capacitor components to EXTAL and XTAL an example is shown below DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 29 External Clock Operation EXTAL XTAL Suggested component values fosc 24 576 MHz R 1M 10 C EXTAL 18 pF C XTAL 47 pF drive level of 10 uW I Calculations are for a 12 49 MHz crystal with the following parameters shunt capacitance Co of 10 pF 12 pF series resistance 40 Ohm If the DSP56374 system clock is an externally supplied square wave voltage source it is connected to EXTAL Figure 2 When the external square wave source connects to EXTAL the XTAL pin is not used Note Midpoint The midpoint is 0 5 Figure 2 External Clock Timing Table 19 Clock Operation No Characteristics Symbol Min Max Units 6 EXTAL input high Eth 3 33 50 ns 40 to 60 duty cycle 7 EXTAL input low Etl 3 33 50 ns 40 to 60 duty cycle 8 EXTAL cycle time Wi
47. inued Signal Name Signal Type State during Reset Signal Description 002_1 SDI3_1 PE9 Output Input Input output or disconnected GPIO disconnected Serial Data Output 2 When programmed as a transmitter SDOA 1 is used to transmit data from the TX2 serial transmit shift register Serial Data Input 3 When programmed as a receiver SDI3 1 is used to receive serial data into the RX3 serial receive shift register Port E9 When the ESAI_1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant SDO1 1 PE10 Output Input output or disconnected GPIO disconnected Serial Data Output 1 SDO1_1 is used to transmit data from the TX1 serial transmit shift register Port E10 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant SDOO 1 PE11 Output Input output or disconnected GPIO disconnected Serial Data Output 0 SDOO 1 is used to transmit data from the TXO serial transmit shift register Port E11 When the ESAI_1 is configured as GPIO this signal is individually programmable as input output or i
48. nternally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 21 Signal Groupings 4 9 Dedicated GPIO Port G Table 12 Dedicated GPIO Port G Signals FR Type ing Signal Description PG0 Input GPIO Port GO This signal is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PG1 Input GPIO Port G1 This signal is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PG2 Input GPIO Port G2 This signal is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PG3 Input GPIO Port G3 This signal is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PG4 Input GPIO Port G4 This signal is individually programmable as input output or disconnected output or internally disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PG5 Input GPIO Port G5 This signal is individually pro
49. o transmit data from the TX3 serial transmit shift register Serial Data Input 2 When programmed as a receiver SDI2 is used to receive serial data into the RX2 serial receive shift register Port C8 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 15 Signal Groupings Table 10 Enhanced Serial Audio Interface Signals continued Signal Name Signal Type State during Reset Signal Description SDO2 SDI3 PC9 Output Input Input output or disconnected GPIO disconnected Serial Data Output 2 When programmed as a transmitter SDO 2 is used to transmit data from the TX2 serial transmit shift register Serial Data Input 3 When programmed as a receiver 013 is used to receive serial data into the RX3 serial receive shift register Port C9 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant 001 PC10 Output Input output or disconnected GPIO disconnected Serial Data Output 1 SDO1 is used to transmit data from the TX1 serial transmit shi
50. on Reset MODA IRQA Input MODA Mode Select A External Interrupt Request A MODA IRQA is an Input active low Schmitt trigger input internally synchronized to the DSP clock MODA IRQA selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing This pin can also be programmed as GPIO MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into the OMR when the RESET signal is de asserted If the processor is in the stop standby state and the MODA IRQA pin is pulled to GND the processor will exit the stop state This pin has an internal pull up resistor This input is 5 V tolerant PHO Input output Port HO When the MODA IRQA is configured as GPIO this signal is or individually programmable as input output or internally disconnected disconnected MODB IRQB Input MODB Mode Select B External Interrupt Request B MODB IRGB is an Input active low Schmitt trigger input internally synchronized to the DSP clock MODB IRGB selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing This pin can also be programmed as GPIO MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into OMR when the RESET signal is de asserte
51. onal Signal Groupings Functional Group Number ot petanen Signals Description Power Vpp 11 Table 15 Ground GND 9 Table 5 Scan Pins 1 Table 6 Clock and PLL 3 Table 7 Interrupt and mode control Port H 5 Table 8 SHI Port H 5 Table 9 ESAI Port C4 12 Table 10 ESAI 1 Port 5 12 Table 11 DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 5 Signal Groupings 4 1 Table 3 DSP56374 Functional Signal Groupings continued Functional Group Number ot Detailed Signals Description Dedicated GPIO Port G3 15 Table 12 Timer 3 Table 13 JTAG OnCE Port 4 Table 14 Note 1 Pins are not 5 V tolerant unless noted 2 Port H signals are the GPIO port signals which are multiplexed with the MOD and HREQ signals 3 Port G signals are the dedicated GPIO port signals 1 Port C signals are the GPIO port signals which are multiplexed with the ESAI signals 5 Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals Power Table 4 Power Inputs Power Name Description PLLA VDD 1 PLL Power The voltage 3 3 V should be well regulated and the input should be provided with an extremely low impedance path to the 3 3 Vpp power rail The user must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND PLLA_VDD requires a filter as shown in Figure 1 and Figure 2 below See the DSP56374 technical da
52. ontrol register The word relative frame sync signal waveform relative to the clock operates in the same manner as the bit length frame sync signal waveform but spreads from one serial clock before first bit clock same as bit length frame sync signal until the one before last bit clock of the first word in frame Periodically sampled and not 100 tested ESAI_1 specs match those of ESAI DSP56374 Data Sheet Rev 4 2 46 Freescale Semiconductor Enhanced Serial Audio Interface Timing SCKT 63 il Input Output FST Bit Out FST Word Out Data Out Last Bit Transmitter 0 Drive Enable FST Bit In FST Word In See Note Flags Out Note network mode output flag transitions can occur at the start of each time slot within the frame In normal mode the output flag state is asserted for the entire frame period Figure 12 is drawn assuming positive polarity bit clock TCKP 0 and positive frame sync polarity TFSP 0 Figure 12 ESAI Transmitter Timing DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 47 Enhanced Serial Audio Interface Timing SCKR Input Output FSR Bit Out FSR Word Out Data In FSR Bit In FSR Word In Flags In Note Figure 13 is drawn assuming positive polarity bit clock RCKP 0 and positive frame sync polarity RFSP 0 Figure 13 ESAI Rec
53. ransfers because it uses the JTAG port as an interface TCK Input Figure 18 Test Clock Input Timing Diagram DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 51 JTAG Timing TCK Input Data Inputs Data Outputs Data Outputs Data Outputs TCK Input TDI TMS Input TDO Output TDO Output TDO Output VIL T PV Input Data Valid Output Data Valid lt Output Data Valid Figure 19 Debugger Port Timing Diagram V 4 Input Data Valid Output Data Valid lt Output Data Valid Figure 20 Test Access Port Timing Diagram DSP56374 Data Sheet Rev 4 2 52 Freescale Semiconductor 20 Watchdog Timer Timing Table 28 Watchdog Timer Timing Watchdog Timer Timing No Characteristics Expression Min Max Unit 120 Delay from time out to fall of TIO1 2 Tg 13 4 ns 121 Delay from timer clear to rise of TIO1 2xTc 13 4 ns DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 53 Watchdog Timer Timing Appendix A Package Information DSP56374 Pinout IO Vdd MODA IRQA PHO MODB_IRQB_PH1 GPIO_PG13 GPIO_PG12 MODC_IRQC_PH2 MODD IRQD PH3 GPIO PG11 Core Vdd Core Gnd GPIO PG10 GPIO_PG9 HREQ_PH4 SS_HA2 SCK_SCL MISO_SDA MOSI_HAO GPIO_PG8 GPIO_PG7 10 Gnd g Q IO 0 en x O G
54. rnal decoupling capacitors between PLLA VDD and PLLA GND DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor Signal Groupings Table 5 Grounds continued Ground Name Description PLLP_GND 1 PLL Ground The PLL ground should be provided with an extremely low impedance path to ground This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND PLLD_GND 1 PLL Ground The PLL ground should be provided with an extremely low impedance path to ground This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND CORE_GND 4 Core Ground The Core ground should be provided with an extremely low impedance path to ground This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors IO GND 2 SHI ESAI ESAI_1 WDT and Timer I O Ground IO_GND is the ground for the SHI ESAI ESAI 1 WDT and Timer I O This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors 4 3 SCAN Table 6 SCAN Signals Signal state 9 During Signal Description Name Reset SCAN Input Input SCAN Manufacturing test p
55. s Wide 200 ns 29 Data input valid to SCK edge data input Master Bypassed 0 ns set up time Slave Very Nanow 0 am Narrow 0 Ex ns Wide 0 ns 30 SCK last sampling edge to data input not Master Bypassed 3 0 X Tc 20 ns ius dpa Very Narrow 3 0 x Tc 23 2 43 2 ns Narrow 3 0 x Tc 53 2 732 ns Wide 3 0xTc 80 1000 ns 31 SS assertion to data out active Slave 5 ns 32 SS deassertion to data high impedance Slave 9 ns 33 SCK edge to data out valid Master Bypassed 3 0 x Tc 26 1 46 2 ns eR Very Narrow 3 0 x Tc 90 4 110 4 ns Narrow 3 0 x 116 4 1364 ns Wide 3 0 x 203 4 223 4 ns 34 SCK edge to data out not valid Master Bypassed 2 0 x Te 13 4 ns gata ounod ime mee Very Narrow 2 0x Tc 1 6 15 ns Narrow 2 0 x 41 6 55 ns Wide 2 0 x 91 6 105 ns 35 SS assertion to data out valid Slave 12 0 ns CPHA 0 DSP56374 Data Sheet Rev 4 2 36 Freescale Semiconductor Table 21 Serial Host Interface SPI Protocol Timing continued Serial Host Interface SPI Protocol Timing 4 No Characteristics Mode Filter Mode Expression Min Max Unit 36 SCK edge following the first SCK Slave Bypassed 3 0 x Tc 30 50 ns sampling edge to HREQ output deassertion Very Narrow 3 0 x Tc
56. s GPIO disconnected Internal Pull down resistor This input is 5 V tolerant FST PC4 Input or output Input output or disconnected GPIO disconnected Frame Sync for Transmitter This is the transmitter frame sync input output signal For synchronous mode this signal is the frame sync for both transmitters and receivers For asynchronous mode FST is the frame sync for the transmitters only The direction is determined by the transmitter frame sync direction TFSD bit in the ESAI transmit clock control register TCCR Port CA When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 13 Signal Groupings Table 10 Enhanced Serial Audio Interface Signals continued State during Signal Name Signal Type Reset Signal Description SCKR Input or output GPIO Receiver Serial Clock SCKR provides the receiver serial disconnected bit clock for the ESAI The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode SYN 0 or as serial flag O pin in the synchronous mode SYN 1 When this pin is configured as serial flag pin its direction is determined by the RCKD bit in the RCCR register When configured
57. s on the 52 pin package DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor Documentation Hardware Watchdog Timer 2 4 Packages 80 pin and 52 pin plastic LQFP packages 3 Documentation Table 2 lists the documents that provide a complete description of the DSP56374 and are required to design properly with the part Documentation is available from a local Freescale Semiconductor Inc formerly Motorola distributor semiconductor sales office Literature Distribution Center or through the Freescale DSP home page on the Internet the source for the latest information Table 2 DSP56374 Documentation Document Name Description Order Number DSP56300 Family Manual Detailed description of the 56300 family architecture and the DSP56300FM AD 24 bit core processor and instruction set DSP56374 User s Manual Detailed description of memory peripherals and interfaces DSP56374UM D DSP56374 Technical Data Sheet Electrical and timing specifications pin and package DSP56374 descriptions DSP56374 Product Brief Brief description of the chip DSP56374PB D 4 Signal Groupings The input and output signals of the DSP56374 are organized into functional groups which are listed in Table 3 The DSP56374 is operated from a 1 25 V and 3 3 V supply however some of the inputs can tolerate 5 0 V A special notice for this feature is added to the signal descriptions of those inputs Table 3 DSP56374 Functi
58. sed it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input DSP56374 Data Sheet Rev 4 2 24 Freescale Semiconductor Maximum Ratings Table 13 Timer Signal continued Signal 9 during Signal Description Name Reset PLOCK Output PLOCK When this pin is configured as a PLL lock pin this signal is asserted high when the on chip PLL enabled and locked and de asserted when the PLL enabled and unlocked This pin is also asserted high when the PLL is disabled Internal Pull down resistor This input is 5 V tolerant 4 11 JTAG OnCE Interface Table 14 JTAG OnCE Interface State Signal Signal ped Signal Description TCK Input Input Test Clock TCK is a test clock input signal used to synchronize the JTAG test logic Internal Pull up resistor This input is 5 V tolerant TDI Input Input Test Data Input TDI is a test data serial input signal used for test instructions and data TDI is sampled on the rising edge of TCK Internal Pull up resistor This input is 5 V tolerant TDO Output Tri stated Test Data Output TDO is a test data serial output signal used for test instructions and data TDO is tri statable and is actively driven in the shift IR and shift DR controller states TDO changes on the falling edge of TCK TMS Input Input Test
59. signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 18 Freescale Semiconductor Signal Groupings Table 11 Enhanced Serial Audio Interface_1 Signals continued Signal Name Signal Type State during Reset Signal Description SCKR 1 PEO Input or output Input output or disconnected GPIO disconnected Receiver Serial Clock 1 5 1 provides the receiver serial bit clock for the ESAI 1 The SCKR_1 operates as a clock input or output used by all the enabled receivers in the asynchronous mode SYN 0 or as serial flag 0 pin in the synchronous mode SYN 1 When this pin is configured as serial flag pin its direction is determined by the RCKD bit in the RCCR 1 register When configured as the output flag OFO this pin will reflect the value of the OFO bit in the SAICR_1 register and the data in the OFO bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode When configured as the input flag IFO the data value at the pin will be stored in the IFO bit in the SAISR_1 register synchronized by the frame sync in normal mode or the slot in network mode Port EO When the ESAI_1 is configured as GPIO this signal is individually programmable as input output or internally disconn
60. synchronized to the DSP clock MODD IRQD selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing This pin can also be programmed as GPIO MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into OMR when the RESET signal is de asserted This pin has an internal pull up resistor This input is 5 V tolerant Port H3 When the MODD IRQD is configured as GPIO this signal is individually programmable as input output or internally disconnected RESET Input Input Reset RESET is an active low Schmitt trigger input When asserted the chip is placed in the Reset state and the internal phase generator is reset The Schmitt trigger input allows a slowly rising input such as a capacitor charging to reset the chip reliably When the RESET signal is de asserted the initial chip operating mode is latched from the MODA MODB MODD inputs The RESET signal must be asserted during power up A stable EXTAL signal must be supplied while RESET is being asserted This pin has an internal pull up resistor This input is 5 V tolerant 4 6 Serial Host Interface The SHI has five I O signals that can be configured to allow the SHI to operate in either SPI or mode DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 9 Si
61. ta sheet for additional details PLLP_VDD 1 PLL Power The voltage 3 3 V should be well regulated and the input should be provided with an extremely low impedance path to the 3 3 Vpp power rail The user must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND PLLD_VDD 1 PLL Power The voltage 1 25 V should be well regulated and the input should be provided with an extremely low impedance path to the 1 25 Vpp power rail The user must provide adequate external decoupling capacitors between PLLD VDD and PLLD GND CORE VDD 4 Core Power The voltage 1 25 V should be well regulated and the input should be provided with an extremely low impedance path to the 1 25 Vpp power rail The user must provide adequate external decoupling capacitors lO VDD 80 pin 4 52 pin 3 SHI ESAI ESAI 1 WDT and Timer I O Power The voltage 3 3 V should be well regulated and the input should be provided with an extremely low impedance path to the 3 3 Vpp power rail This is an isolated power for the SHI ESAI ESAI_1 WDT and Timer I O The user must provide adequate external decoupling capacitors 4 2 Ground Table 5 Grounds Ground Name Description PLLA GND 1 PLL Ground The PLL ground should be provided with an extremely low impedance path to ground This connection must be tied externally to all other chip ground connections The user must provide adequate exte
62. th PLL disabled Etc 6 67 inf ns With PLL enabled 50 200 9 Instruction cycle time Icyc Tc With PLL disabled Icyc 6 67 inf ns With PLL enabled 6 67 13 33 DSP56374 Data Sheet Rev 4 2 30 Freescale Semiconductor External Clock Operation Table 19 Clock Operation continued No Characteristics Symbol Min Max Units Note Measured at 50 of the input transition The indicated duty cycle is for the specified maximum frequency for which a part is rated The minimum clock high or low time required for correct operation however remains the same at lower operating frequencies therefore when a lower clock frequency is used the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met 3 A valid clock signal must be applied to the EXTAL pin within 3 ms of the DSP56374 being powered up DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 31 Reset Stop Mode Select and Interrupt Timing 12 Reset Stop Mode Select and Interrupt Timing Table 20 Reset Stop Mode Select and Interrupt Timing No Characteristics Expression Min Max Unit 10 Delay from RESET assertion to all pins at reset 11 ns value 11 Required RESET duration Power on external clock generator PLL disabled 2 XTc 13 4 ns Power on external clock generator PLL enabled 2
63. to the shortest possible duration RESET All Pins 2222222222 Figure 3 Reset Timing DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 33 Reset Stop Mode Select and Interrupt Timing IRQA IRQB 19 18 IRQC IRQD NMI a First Interrupt Instruction Execution General Purpose JM ND a NMI WEE b General Purpose I O Figure 4 External Fast Interrupt Timing IRQA IRQC IRQD NMI 16 N IRQA 1 IRQC IRQD NMI MM _ CEN Figure 5 External Interrupt Timing Negative Edge Triggered MODA MODB MODC MODD PINIT Figure 6 Recovery from Stop State Using IRQA Interrupt Service DSP56374 Data Sheet Rev 4 2 34 Freescale Semiconductor 13 Serial Host Interface SPI Protocol Timing Serial Host Interface SPI Protocol Timing Table 21 Serial Host Interface SPI Protocol Timing No Characteristics Mode Filter Mode Expression Min Max Unit 23 Minimum serial clock cycle tspjcc min Master Slave Bypassed 10 00xTo 9 760 ns Very Narrow 10 0x To 9 76 0 ns Narrow 10 0 x 133 200 0 ns Wide 10 0 x 333 400 0 ns XX Tolerable Spike width on data or clock in Bypassed 0 ns Very Narrow 10 ns Narrow 50 ns Wide
64. ty of their respective owners Freescale Semiconductor Inc 2004 2005 2006 2007 All rights reserved lt oF 2 freescale semiconductor
65. ult state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant SDOA 1 Output GPIO Serial Data Output 4 1 When programmed as a disconnected transmitter SDOA 1 is used to transmit data from the TX4 serial transmit shift register SDI1_1 Input Serial Data Input 1_1 When programmed as a receiver SDI1 1 is used to receive serial data into the RX1 serial receive shift register PE7 Input output or Port E7 When the ESAI_1 is configured as GPIO this disconnected signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant SDO3 1 Output GPIO Serial Data Output 3 When programmed as a transmitter disconnected 5003 1 is used to transmit data from the TX serial transmit shift register SDI2 1 Input Serial Data Input 2 When programmed as a receiver SDI2_1 is used to receive serial data into the RX2 serial receive shift register PE8 Input output or Port E8 When the ESAI is configured as GPIO this signal disconnected is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56374 Data Sheet Rev 4 2 20 Freescale Semiconductor Signal Groupings Table 11 Enhanced Serial Audio Interface_1 Signals cont
66. wr high before SCKR edge 2 0 x ck ns 12 0 icka 74 FSR input wl high before SCKR edge 2 0 x ck ns 12 0 icka 75 FSR input hold time after SCKR edge 2 5 x ck ns 8 5 icka 76 Flags input setup before SCKR edge 0 0 X ck ns 19 0 icks 77 Flags input hold time after SCKR edge 6 0 x ck ns 0 0 icks 78 SCKT edge to FST out bl high 18 0 x ck ns 8 0 ick 79 SCKT edge to FST out bl low 20 0 X ck ns 10 0 i ck 80 SCKT edge to FST out wr high 20 0 x ck ns 10 0 i ck 81 SCKT edge to FST out wr low 220 x ck ns 12 0 i ck 82 SCKT edge to FST out wl high E 19 0 x ck ns 9 0 i ck 83 SCKT edge to FST out wl low 20 0 x ck ns 10 0 ick 84 SCKT edge to data out enable from high 22 0 X ck ns impedance 17 0 i ck 85 SCKT edge to transmitter 0 drive enable 17 0 X ck ns assertion 11 0 ick 86 SCKT edge to data out valid m 18 0 X ck ns 13 0 ick 87 SCKT edge to data out high impedance 21 0 x ck ns m 16 0 i ck DSP56374 Data Sheet Rev 4 2 Freescale Semiconductor 45 Enhanced Serial Audio Interface Timing Table 24 Enhanced Serial Audio Interface Timing continued No Characteristics 2 3 Symbol Expression Min Max Condition Unit 88 SCKT edge to transmitter 0 drive enable

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