OMG-530 operator`s manual
Contents
1. K3 Ss eer EE ost wt Sma Figure 6 IRQ Header E3 IRQ Mode Header E1 Header E1 N indicates the N ormal single interrupt mode Position M indicates the inclusion of a 1K ohm pull down resistor required on one port when sharing interrupts with another card For shared interrupt mode set one board to M and the other s with the jumper removed This mode allows more than one board to access a single IRQ Position T on El enables the DMA Terminal Count Interrupt Setting this jumper allows the selected DMA channel to generate an interrupt once the DMA Terminal Count has been reached See Section 4 for the status bit TC STAT position and refer to the toolkit disk for software examples Note When using multiple cards on one IRQ in shared mode be sure that only one port has the M jumper set providing the necessary pull down resistor E1 TNM Figure 7 IRQ Mode Header Omega Engineering OMG ACB 530 Page 9 Installation Installation The OMG ACB 530 can be installed in any of the PC expansion slots The OMG ACB 530 contains several jumper straps for each port which must be set for proper operation Turn off PC power Disconnect the power cord Remove the PC case cover Locate two available slots and remove the blank metal slot covers Install the Channel B cable into Box Header E4 This cable is keyed to prevent improper installation Gently insert the OMG ACB 530 into the slot Make2. the difference in voltage between a single signal and a common ground connection Differential interfaces are typically more immune to noise or voltage spikes that may occur on the communication lines Differential interfaces also have greater drive capabilities that allow for longer cable lengths RS 422 is rated up to 10 Megabits per second and can have cabling 4000 feet long RS 422 also defines driver and receiver electrical characteristics that will allow 1 driver and up to 32 receivers on the line at once RS 422 signal levels range from 0 to 5 volts RS 422 does not define a physical connector RS 530 RS 530 a k a E1A 530 compatibility means that RS 422 signal levels are met and the pin out for the DB 25 connector is specified The Electronic Industry Association EIA created the RS 530 specification to detail the pin out and define a full set of modem control signals that can be used for regulating flow control and line status The RS 530 specification defines two types of interface circuits Data Terminal Equipment DTE and Data Circuit Terminating Equipment DCE The Omega Engineering adapter is a DTE interface RS 449 RS 449 a k a E A 449 compatibility means that RS 422 signal levels are met and the pin out for the DB 37 connector is specified The EIA created the RS 449 specification to detail the pin out and define a full set of modem control signals that can be used for regulating flow control and line status Ome
3. Contents INTRODUCTION siste ee N eke Re ve ds ee SR Ne ag ee Ks VO IEN 1 WHAT S INCLUDED ees sesse aa 1 FACTORY DEFAULT SETTINGS ees aa 1 CARD SETUP icaccccccccscssccosscssscobscdsccobccosscobscdaccosccesscoscctsscoecesece 2 ADDRESS SELECTION esse ees aaa 2 PORT ENABLE DISABLE ees sesse ees ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 3 TRANSMIT CLOCK RS 485 ENABLE HEADER ES eise sesse ee A DMA CHANNEL SELECTION HEADERS E4 EI 5 DMA JUMPER OPTION TABLES 02 aaa 6 No DMA sers se BAGA NA NAALALA S E GINA 6 Single Channel DMA Half Duplex Only esse ese esse esse ees 6 Two DMA Channels Selected ee ee ee ee EE 6 Full Duplex Channel A and B with four DMA Channels 7 Full Duplex Channel A only ees ee ee ee ee ee 7 Full Duplex Channel B only sees ee ee ee ee 7 DMA ENABLE HEADER E2 ees sesse see see ee ee ee ee ee ees ee ee ee ee ee ee ee ee ee 8 IRQ SELECTION HEADER Ei 9 IRQ MODE HEADER EH 9 INSTALLATION ci esscsescsccescesessocoacescescsdssseccddccccessscvsecesdsecesssces LO CABLING OPTIONS ee ees een ee ee ee ee ee ee ee ee ee ee ee 10 TECHNICAL DESCRIPTION 00000000000000000000000000000000000000 LL FEATURES 3235508720 N EE N AN GIAN E NGA 11 Internal Baud Rate Generator sesse ee ee ee ee ee EE 11 PROGRAMMING THE OMG ACHa30 ee ee ee ee ee ee ee ee 12 Control Status Port 12 Software Examples sccsesccssseecsseeceese
4. Developers Toolkit Diskette Channel B Interface Cable J e J e User Manual Factory Default Settings The OMG ACB 530 factory default settings are as follows Base DMA Port A DMA Port B Electrical Address Specification TX 1 RX 3 TX 0 RX 2 RS 530 422 To install the OMG ACB 530 using factory default settings refer to the section on Installation For your reference record installed OMG ACB 530 settings below Base DMA Port A DMA Port B Electrical Address Specification Omega Engineering OMG ACB 530 Page 1 Installation Card Setup The OMG ACB 530 contains several jumper straps for each port which must be set for proper operation Address Selection The OMG ACB 530 occupies 8 consecutive I O locations A DIP switch SW1 is used to set the base address for these locations The OMG ACB 530 can reside in any I O location between 100 and 3F8 Hex Be careful when selecting the base address as some selections conflict with existing PC ports The following table shows several examples that usually do not cause a conflict Switch Settings Figure 1 Address Selection Table The following illustration shows the correlation between the DIP switch setting and the address bits used to determine the base address In the example below the address 300 Hex through 307 Hex is selected 300 Hex 11 0000 OXXX in binary representation 12345678 Figure 2 DIP switch Illustration Note Setting the swit
5. IVE STATEMENT ees sesse se ese ees see ee se ee ee ee ee ee ee ee ee 27 WARRANTY sessie os siese NGANGA Aina ee ie sede see 28 Figures Figure 1 Address Selection Table ssccssscssssssssscssssssssssessseoseee 2 Figure 2 DIP switch Tlustrati0n sesse sees sesse sesse ee see Ge Ge Ge ee 2 Figure 3 Clock Option RS 485 Enable Selection Header E8 4 Figure 4 DMA Selection Headers Ed E7 sees esse sesse ese sesse ees sesse see 5 Figure 5 DMA Enable Header E2 see esse esse ese sesse see see ees see ee ee ee 8 Figure 6 IRQ Header EA sees ssee sesse ee sees see es see ee ee Gee Gee Gee Gee See 9 Figure 7 IRQ Mode Header sees ssee sesse sesse ese ee See Ge AG Ge Ge ee 9 Figure 8 Asynchronous Communications Bit Diagram 22 Figure 9 Synchronous Communications Bit Diagram 23 1997 Omega Engineering Incorporated All rights reserved Introduction Introduction Overview The Omega Engineering OMG ACB 530 provides the PC with two high speed RS 530 422 485 synchronous asynchronous ports The OMG ACB 530 can be used in a variety of sophisticated communications applications such as SDLC HDLC X 25 Bi Sync Mono Sync and high speed asynchronous What s Included The OMG ACB 530 is shipped with the following items If any of these items are missing or damaged contact the supplier OMG ACB 530 Serial Interface Adapter 3 5 ACB
6. Rx and Tx to Rx Four wire mode allows full duplex data transfers RS 485 does not define a connector pin out or a set of modem control signals RS 485 does not define a physical connector Omega Engineering OMG ACB 530 Page 19 Appendix D Direct Memory Access Appendix D Direct Memory Access In many instances it is necessary to transmit and receive data at greater rates than would be possible with simple port I O In order to provide a means for higher rate data transfers a special function called Direct Memory Access DMA was built into the original IBM PC The DMA function allows the OMG ACB 530 or any other DMA compatible interface to read or write data to or from memory without using the Microprocessor This function was originally controlled by the Intel 8237 DMA controller chip but may now be a combined function of the peripheral support chip sets i e Chips amp Technology or Symphony chip sets During a DMA cycle the DMA controller chip is driving the system bus in place of the Microprocessor providing address and control information When an interface uses DMA it activates a DMA request signal DRQ to the DMA controller which in turn sends a DMA hold request to the Microprocessor When the Microprocessor receives the hold request it will respond with an acknowledge to the DMA controller chip The DMA controller chip then becomes the owner of the system bus providing the necessary control signals to complete a Mem
7. ch On or Closed corresponds to a O in the address while leaving it Off or Open corresponds to a 1 Omega Engineering OMG ACB 530 Page 2 Installation The relative I O address of the OMG ACB 530 registers are as follows Base 0 Base 1 Base 2 Base 3 Base 4 Base 5 Channel A Data Port Channel A Control Port Channel B Data Port Channel B Control Port Board Control Status Port Reset TCIRQ Port Enable Disable The OMG ACB 530 can be enabled or disabled with switch position 8 on the DIP switch The port is enabled with the switch On or Closed and disabled when Off or Open Omega Engineering OMG ACB 530 Page 3 Installation Transmit Clock RS 485 Enable Header E8 Header E8 sets the input output clock modes for the transmit clock TXC and RS 485 driver enable Please note that setting a jumper in position I and position O at the same time is not a valid option O Transmit Clock Output Channel A O Transmit Clock Output ChannelB Figure 3 Clock Option RS 485 Enable Selection Header ES In addition to RS 530 the OMG ACB 530 is capable of RS 422 and RS 485 communications E8 position EK determines whether the RS 530 and RS 485 transmit driver is enabled by the Enhanced Serial Communications Controller ESCC signal Request To Send RTS or always enabled With the jumper installed RTS enables the driver Removing th
8. dentified Configure your Omega Engineering adapter so that there is no conflict with currently installed adapters No two adapters can occupy the same I O address Make sure the Omega Engineering adapter is using a unique IRQ While the Omega Engineering adapter does allow the sharing of IRQ s many other adapters i e SCSI adapters amp on board serial ports do not The IRQ is typically selected via an on board header block Refer to the section on Card Setup for help in choosing an I O address and IRQ Make sure the Omega Engineering adapter is securely installed in a motherboard slot Use the supplied diskette and User Manual to verify that the Omega Engineering adapter is configured correctly The supplied diskette contains a diagnostic program SSDACB that will verify if an adapter is configured properly Refer to the UTIL txt file found in the UTIL sub directory on the supplied diskette for detailed instructions on using SSDACB The following are known I O conflicts 3F8 3FF is typically reserved for COM 2F8 2FF is typically reserved for COM2 3E8 3EF is typically reserved for COM3 2E8 2EF is typically reserved for COM4 This is a valid setup option for the OMG ACB 530 However since only 10 address lines are actually decoded a possible conflict with an advanced video card emulating the IBM XGA adapter 8514 register set may occur Omega Engineering OMG ACB 530 Page 16 Appendix B How To G
9. e jumper enables the driver regardless of RTS This jumper should only be installed if you are running the board in a multi drop polled environment such as RS 485 and you have software that knows how to talk on the RS 485 bus For normal point to point RS 530 and RS 422 remove this jumper Omega Engineering OMG ACB 530 Page 4 Installation DMA Channel Selection Headers E4 E7 Headers E4 E7 select Direct Memory Access DMA mode of operation Each channel of the Enhanced Serial Communications Controller ESCC will function in half duplex or full duplex DMA modes Full duplex means that DMA can be used for simultaneous transmit and receive Half duplex DMA means that you can either transmit or receive with DMA but not simultaneously The 85230 has two signals that correspond to DMA request signals WAIT REQ and DTR REQ ES amp E7 correspond to WAIT REQ and E4 amp E6 correspond to DTR REQ WAIT REQ and DTR REQ can be programmed to serve as DMA request lines DRQ by setting the appropriate bits in Write Register 1 and Write Register 14 in the 85230 WAIT REQ E5 E E7 can be programmed for Transmit or Receive DMA transfers and DTR REQ E4 E6 can be programmed for Transmit Only For additional information on the programming of the 85230 please refer to the Zilog ESCC Users Manual Please note that each DMA channel is selected by two jumpers Only one DMA channel may be selected for each header block Also refer to page 8 f
10. erator The baud rate of the ESCC is programmed under software control The standard oscillator supplied with the board is 7 3728 MHz However other oscillator values can be substituted to achieve different baud rates Omega Engineering OMG ACB 530 Page 11 Technical Description Programming the OMG ACB 530 Control Status Port The OMG ACB 530 occupies eight Input Output I O addresses The ESCC chip uses the first four while the fifth address Base 4 is the address of the on board Control Status Port This port is used to set the Data Terminal Ready DTR Remote Loopback RL Local Loopback LL signals and to enable or disable DMA under program control and to monitor the Data Set Ready DSR input signals from the modem 0 DTRA I On 0 Off DSRA I Off 0 On_ LLB 1 On 0 Off TMB 1 Off 0 On RLB 1 On 0 Off TC STAT 1 Off 0 On RE o ESCC CH B 1 On 0 Off ESCC CH A 1 On 0 Off Software Examples Omega Engineering OMG ACB 530 Page 12 Technical Description DMA Terminal Count The OMG ACB 530 can be setup to operate using a polling method interrupts or system DMA The most efficient method is a combination of DMA and interrupts The OMG ACB 530 has been optimized to generate an interrupt at the end of a DMA transfer This will allow for DMA initialization and buffer management to take place at interrupt time and provide a virtually seamless communication channel If the T option on header El is
11. eseeeeseecsseeesseeeesaes 12 DMA TERMINAL COUNT esse 0 aa 13 CONNECTOR P1 AND P2 PIN ASSIGNMENTS esse esse ee aaa 14 RS 530 422 485 Line Termination ee Ee 14 SPECIFICATIONS iis diese sd este sesse ge kes do ge ed oi ke dose 1S ENVIRONMENTAL SPECIFICATIONS ee esse esse sesse ee ee ee see ee ee ee ee ee 15 POWER CONSUMPTION ccssssseecccceecceeseeceeceasscseeeececceeeeaaneees 15 MEAN TIME BETWEEN FAILURES OMTBE ee ee ee ee ee ee ee 15 PHYSICAL DUMENSIONS ees sees esse aaa 15 APPENDIX A TROUBLESHOOTING 000000000000000000000000000 000 LO APPENDIX B HOW TO GET ASSISTANCE cccccscsscccessooee 17 APPENDIX C ELECTRICAL INTERFACE cccccscsssccesseeee 18 UE 18 EER RO OE RE RR RE 18 AE EE EE EE EE ER 18 AE ARE ER RE RE OE EE EE 19 APPENDIX D DIRECT MEMORY ACCESS cccccssscssccsssoee 20 APPENDIX E ASYNCHRONOUS AND SYNCHRONOUS COMMUNICATIONS scccccsssscscccssssccccccsccccccssscscccsssccsscsssccees DA ASYNCHRONOUS COMMUNICATIONS scccccessecceesececeeeseeeeeeees 21 SYNCHRONOUS COMMUNICATIONS 220000 as 23 APPENDIX F ACB DEVELOPER TOOLKIT DISKETTE AND ACB RESOURCE KIT ccccccsscsccccsctesscossccscccsccsssconcctsscousatescoassteccoasess 25 APPENDIX G SILK SCREEN cccsssscccssssccccccssscccesssssesesses 20 APPENDIX H COMPLIANCE NOTICES 00000000000000000 27 FEDERAL COMMUNICATIONS COMMISSION STATEMENT esse 27 EMC DIRECT
12. et Assistance Appendix B How To Get Assistance Please refer to Appendix A Troubleshooting prior to calling Technical Support Read this manual thoroughly before attempting to install the adapter in your system When calling for technical assistance please have your user manual and current adapter settings If possible please have the adapter installed in a computer ready to run diagnostics Omega Engineering maintains a home page on the World Wide Web www omega com providing utilities and new product information Technical support is available Monday to Friday from 8 30 a m to 6 00 p m Eastern time Technical support can be reached at 800 826 6342 x2295 RETURN AUTHORIZATION MUST BE OBTAINED FROM OMEGA ENGINEERING BEFORE RETURNED MERCHANDISE WILL BE ACCEPTED AUTHORIZATION CAN BE OBTAINED BY CALLING OMEGA ENGINEERING AND REQUESTING A RETURN MERCHANDISE AUTHORIZATION RMA NUMBER Omega Engineering OMG ACB 530 Page 17 Appendix C Electrical Interface Appendix C Electrical Interface RS 422 The RS 422 specification defines the electrical characteristics of balanced voltage digital interface circuits RS 422 is a differential interface that defines voltage levels and driver receiver electrical specifications On a differential interface logic levels are defined by the difference in voltage between a pair of outputs or inputs In contrast a single ended interface for example RS 232 defines the logic levels as
13. ew of the ACB product line and is available at your request Topics concerning applications and integration are covered to provide a complete overview of the versatile ACB family During ACB development if any questions comments or suggestions arise please contact Technical Support at the numbers listed at the end of this manual Omega Engineering OMG ACB 530 Page 25 Appendix G Silk Screen Appendix G Silk Screen 3 9 LN LIO me SRB en SY SERIES 3 ca 979SI1FL dl08HILIMS C89S lvl a 9x k3 bd T IMS Es Era PA SA IM cezzZILBO LI LYSELEGDX H 73 ET SLISL C 8 v zl OAV NVSNVS Coro na Don pay a3 vy RE a SLISL c een 93 OYI O3YYHSSN DYI TYAYONEN Zdy L dea 49 EI INNOD WNINRI L D YE S9YIdWNP 13 gt YNG ON N LIY 63 XM X1 OH 04 8 TIEYNI SAVNTY Cy 83 Bebe 9da JEVN YNO g v C cn suaanne Z3 EE 692 DD 1d OcZ dY LO 04 EE En Got se CO jo Ee SE Y uer PLISLO py CO Xd gn on EN g9 a CI Je KO EE 103135 TINNYHO YNG SYIAWNP 43 vas d VLISL INANI MOOT XL eg LLLY INGINO 490719 XL 0 in _ 87 SU 318VN3 SL DEG AOV ON vn ssuganinn eas EX SE 5 8 4 2 Page 26 OMG ACB 530 ineering Omega Eng Ap
14. ga Engineering OMG ACB 530 Page 18 Appendix C Electrical Interface RS 485 RS 485 is backwardly compatible with RS 422 however it is optimized for partyline or multi drop applications The output of the RS 422 485 driver is capable of being Active enabled or Tri State disabled This capability allows multiple ports to be connected in a multi drop bus and selectively polled RS 485 allows cable lengths up to 4000 feet and data rates up to 10 Megabits per second The signal levels for RS 485 are the same as those defined by RS 422 RS 485 has electrical characteristics that allow for 32 drivers and 32 receivers to be connected to one line This interface is ideal for multi drop or network environments RS 485 tri state driver not dual state will allow the electrical presence of the driver to be removed from the line The driver is in a tri state or high impedance condition when this occurs Only one driver may be active at a time and the other driver s must be tri stated The output modem control signal Request to Send RTS controls the state of the driver Some communication software packages refer to RS 485 as RTS enable or RTS block mode transfer RS 485 can be cabled in two ways two wire and four wire mode Two wire mode does not allow for full duplex communication and requires that data be transferred in only one direction at a time For half duplex operation the two transmit pins should be connected to the two receive pins Tx to
15. ga Engineering OMG ACB 530 Page 6 Installation Full Duplex Channel A and B with four DMA Channels EE EE Ch A DMA Ch 1 Receive Data 33 11 22 Ch A DMA Ch 3 Transmit Data Ch B DMA Ch 0 Receive Data Ch B DMA Ch 2 Transmit Data Full Duplex Channel A only Ch A DMA Ch 1 Receive Data 33 11 None None Ch A DMA Ch 3 Transmit Data Full Duplex Channel B only Ch B DMA Ch 1 Receive Data None None 33 11 Ch B DMA Ch 3 Transmit Data Omega Engineering OMG ACB 530 Page 7 Installation DMA Enable Header E2 Header E2 selects whether the DMA tri state drivers are enabled permanently disabled permanently or whether the DMA enable control port bit is used to enable the DMA hardware request and acknowledge signals Moving the jumper to position N disables the drivers and no DMA can be performed Note The power on reset signal resets or disables the DMA software enable signal SANSAN Figure 5 DMA Enable Header E2 Selects Software Enable Channel A Selects Always Enable Channel A Selects No DMA Channel A Selects Software Enable Channel B Selects Always Enable Channel B Selects No DMA Channel B Note Please refer to section 4 for software bit definitions and examples of DMA driver control Omega Engineering OMG ACB 530 Page 8 Installation IRQ Selection Header E3 Header E3 selects the interrupt request IRQ line for the card If no interrupt is desired remove the jumper
16. mail Internet das omega com Web Site www omega com Technical Support is available from 8 30 a m to 6 p m Eastern time Monday Friday Trademarks Omega Engineering Incorporated acknowledges that all trademarks referenced in this manual are the service mark trademark or registered trademark of the respective company OMG ACB 530 is a trademark of Omega Engineering Incorporated Omega Engineering OMG ACB 530 Page 28
17. menting a parity check to guard against data corruption Common methods are called E ven Parity or O dd Parity Sometimes parity is not used to detect errors on the data stream This is referred to as N o parity Because each bit in asynchronous communications is sent consecutively it is easy to generalize asynchronous communications by stating that each character is wrapped framed by pre defined bits to mark the beginning and end of the serial transmission of the character The data rate and communication parameters for asynchronous communications have to be the same at both the transmitting and receiving ends The communication parameters are baud rate parity number of data bits per character and stop bits i e 9600 N 8 1 Omega Engineering OMG ACB 530 Page 22 Appendix E Asynchronous and Synchronous Communications Synchronous Communications Synchronous Communications is used for applications that require higher data rates and greater error checking procedures Character synchronization and bit duration are handled differently than asynchronous communications Bit duration in synchronous communications is not necessarily pre defined at both the transmitting and receiving ends Typically in addition to the data signal a clock signal is provided This clock signal will mark the beginning of a bit cell on a pre defined transmission The source of the clock is predetermined and sometimes multiple clock signals are available For e
18. ommunicating using eight bits per character Point A is receiving a clock from point B and sampling the receive data pin on every upward clock transition Once point A receives the pre defined bit pattern sync flag the next eight bits are assembled into a valid character The following eight bits are also assembled into a character This will repeat until another pre defined sequence of bits is received either another sync flag or a bit combination that signals the end of the text e g EOT The actual sync flag and protocol varies depending on the sync format SDLC BISYNC etc For a detailed explanation of serial communications please refer to the book Technical Aspects of Data Communications by John E McNamara published by Digital Press DEC 1982 Omega Engineering OMG ACB 530 Page 24 Appendix F ACB Developer Toolkit Diskette and ACB Resource Kit Appendix F ACB Developer Toolkit Diskette and ACB Resource Kit The ACB Developer Toolkit diskette provides sample software a DOS version of the SeaMAC Driver and technical insight to aid in the development of reliable applications for the ACB family of communication cards The goal in publishing this collection of source code and technical information is two fold First to provide the developer with ample information to develop ACB based applications Second to provide a channel for suggestions into the technical support efforts The ACB Resource Kit provides a detailed overvi
19. or the DMA enable Software enable Always enabled or Never enabled option Header E2 Note If DMA is not used remove all of the jumpers on E4 E7 and install a jumper in position N of E2 A FD E4 SSS 00112233 Figure 4 DMA Selection Headers E4 E7 E4 and E5 select the DMA Channel for Channel A of the ESCC E6 and E7 select the DMA Channel for Channel B of the ESCC Note DMA Channel 0 is not available on XT class machines and DMA Channel 2 can only be used if the floppy disk DMA drivers are turned off Please refer to the toolkit disk for software examples Omega Engineering OMG ACB 530 Page 5 Installation DMA Jumper Option Tables The following tables show the jumper setting examples for each mode of DMA No DMA Ch A No DMA Ch B No DMA Single Channel DMA a Duplex Only Ch A DMA Ch 0 Half Duplex Ch B No DMA Non None None Ch A DMA Ch 1 Half Duplex Ch B No DMA etc Ch A DMA Ch 2 Hait Duplex Ch B No DMA Non None None Ch A DMA Ch 3 Half Duplex Ch B No DMA paa poge Ch B DMA Ch 0 Half Duplex Ch A No DMA None None Ch B DMA Ch 1 Half Duplex Ch A No DMA EES Ch B DMA Ch 2 Half Duplex Ch A No DMA None None Non Ch B DMA Ch 3 Half Duplex Ch A No DMA EE Two DMA Channels Selected Ch A DMA Ch 1 Half Duplex None 11 None 33 Ch B DMA Ch 3 Half Duplex Ch A DMA Ch 0 Half Duplex None None 22 Ch B DMA Ch 2 Half Duplex Ome
20. ory to I O or I O to Memory transfer When the data transfer is started an acknowledge signal DACK is sent by the DMA controller chip to the OMG ACB 530 Once the data has been transferred to or from the OMG ACB 530 the DMA controller returns control to the Microprocessor To use DMA with the OMG ACB 530 requires a thorough understanding of the PC DMA functions The ACB Developers Toolkit demonstrates the setup and use of DMA with several source code and high level language demo programs Please refer to the ESCC User s Manual for more information Omega Engineering OMG ACB 530 Page 20 Appendix E Asynchronous and Synchronous Communications Appendix E Asynchronous and Synchronous Communications Serial data communications implies that individual bits of a character are transmitted consecutively to a receiver that assembles the bits back into a character Data rate error checking handshaking and character framing start stop bits or sync characters are pre defined and must correspond at both the transmitting and receiving ends The techniques used for serial communications can be divided two groups asynchronous and synchronous When contrasting asynchronous and synchronous serial communications the fundamental differences deal with how each method defines the beginning and end of a character or group of characters The method of determining the duration of each bit in the data stream is also an important difference between as
21. pendix H Compliance Notices Appendix H Compliance Notices Federal Communications Commission Statement FCC This equipment has been tested and found to comply with the limits for Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in such case the user will be required to correct the interference at his own expense EMC Directive Statement Products bearing the CE Label fulfill the requirements of the EMC directive 89 336 EEC and of the low voltage directive 73 23 EEC issued by the European Commission To obey these directives the following European standards must be met e EN55022 Class A Limits and methods of measurement of radio interference characteristics of information technology equipment e EN50082 1 Electromagnetic compatibility Generic immunity standard Part 1 Residential commercial and light industry e EN60950 IEC950 Safety of information technology equipment including electrical business equipment Warning This is a Class A Product In a domestic en
22. puts The RS 530 specification calls for a 100 ohm 1 2 watt resistor between the signal ground and the chassis ground On the IBM PC these two grounds are already connected together therefore this resistor is omitted Omega Engineering OMG ACB 530 Page 14 Specifications Specifications Environmental Specifications Temperature 0 to 50 C 20 to 70 C Range 32 to 122 F 4 to 158 F Humidity Range 10 to 90 R H 10 to 90 R H Non Condensing Non Condensing Power Consumption Supply line 5 VDC 900 mA Mean Time Between Failures MTBF Greater than 150 000 hours Calculated Physical Dimensions Board length 5 8 inches 14 73 cm Board Height including Goldfingers 4 2 inches 10 66 cm Board Height excluding Goldfingers 3 9 inches 9 91 cm Please see Appendix G for board layout and dimensions Omega Engineering OMG ACB 530 Page 15 Appendix A Troubleshooting Appendix A Troubleshooting An ACB Developers Toolkit Diskette is supplied with the Omega Engineering adapter and will be used in the troubleshooting procedures By using this diskette and following these simple steps most common problems can be eliminated without the need to call Technical Support 1 Identify all I O adapters currently installed in your system This includes your on board serial ports controller cards sound cards etc The I O addresses used by these adapters as well as the IRQ if any should be i
23. selected an onboard latch will be set when Terminal Count for the selected DMA channel s is reached This latch will cause an interrupt to be generated and program execution will be transferred to the application Interrupt Service Routine ISR The DMA Terminal Count Interrupt condition should be reset from the ISR by writing to BASE 5 The value that is written to this I O location is irrelevant If your application or driver is interrupting on multiple conditions reading the Status Register located at Base 4 will determine the source of the interrupt ESCC or DMA Terminal Count generated Bit D3 in the Status Port corresponds to a ESCC generated interrupt and bit D5 corresponds to an interrupt generated by the end of a DMA transfer Bit D3 can only be reset by polling the ESCC to determine the interrupt source and required action necessary to reset the interrupt Please refer to the Software Toolkit and the 85230 Technical Manual for details and examples on interrupt driven and DMA programming examples Omega Engineering OMG ACB 530 Page 13 Technical Description Connector P1 and P2 Pin Assignments Receive Positive Receive Negative C LoealLoopBaek Remote Loop Back RS 530 422 485 Line Termination Typically each end of the RS 530 422 485 bus must have line terminating resistors A 100 ohm resistor is across each RS 530 422 485 input in addition to a 1K ohm pull up pull down combination that biases the receiver in
24. sure that the adapter is seated properly Attach the Channel B cable to the adjacent slot with the retaining screw If Channel B of the OMG ACB 530 is not used the adapter cable is not required Replace the cover 6 Connect the power cord aa da rd Installation is complete Cabling Options The OMG ACB 530 has a number of cabling options available These options include e CA 104 This cable provides a 6 extension for use with RS 530 422 e CA 107 This cable provides a simple interface to the RS 449 DB 37 type connector RS 530 was designed as a replacement for RS 449 Omega Engineering OMG ACB 530 Page 10 Technical Description Technical Description The OMG ACB 530 utilizes the Zilog 85230 Enhanced Serial Communications Controller ESCC This chip features programmable baud rate data format and interrupt control as well as DMA control Refer to the ESCC Users Manual for details on programming the 85230 ESCC chip Features e Two channels of sync async communications using 85230 chip e DMA supports data rate greater than million bits per second bps e Selectable Port Address IRQ level 2 9 3 4 5 7 10 11 12 15 e Selectable DMA channels 0 1 2 3 e FIA 530 422 interface with full modem control supports TD RD RTS CTS DSR DCD DTR TXC RXC LL RL TM TSET signals e Jumper options for clock source and Input Output modes e Software programmable baud rate Internal Baud Rate Gen
25. vironment this product may cause radio interference in which case the user may be required to take adequate measures Always use cabling provided with this product if possible If no cable is provided or if an alternate cable is required use high quality shielded cabling to maintain compliance with FCC EMC directives Omega Engineering OMG ACB 530 Page 27 Warranty Warranty Omega Engineering Inc warrants this product to be in good working order for a period of one year from the date of purchase Should this product fail to be in good working order at any time during this period Omega Engineering will at it s option replace or repair it at no additional charge except as set forth in the following terms This warranty does not apply to products damaged by misuse modifications accident or disaster Omega Engineering assumes no liability for any damages lost profits lost savings or any other incidental or consequential damage resulting from the use misuse of or inability to use this product Omega Engineering will not be liable for any claim made by any other related party RETURN AUTHORIZATION MUST BE OBTAINED FROM OMEGA ENGINEERING BEFORE RETURNED MERCHANDISE WILL BE ACCEPTED AUTHORIZATION CAN BE OBTAINED BY CALLING OMEGA ENGINEERING AND REQUESTING A RETURN MERCHANDISE AUTHORIZATION RMA NUMBER Omega Engineering Incorporated One Omega Drive PO Box 4047 Stamford CT 06907 800 826 6342 FAX 203 359 7990 e
26. xample if two nodes want to establish synchronous communications point A could supply a clock to point B that would define all bit boundaries that A transmitted to B Point B could also supply a clock to point A that would correspond to the data that A received from B This example demonstrates how communications could take place between two nodes at completely different data rates Character synchronization with synchronous communications is also very different than the asynchronous method of using start and stop bits to define the beginning and end of a character When using synchronous communications a pre defined character or sequence of characters is used to let the receiving end know when to start character assembly 1Bit Time Clock Bit 0 1 2 3 4 5 6 de Bit State o 1 1 0 1 0 0 0 1 1 0 1 0 1 0 Data LSB l l bk Sync Character k Data Character Figure 9 Synchronous Communications Bit Diagram Omega Engineering OMG ACB 530 Page 23 Appendix E Asynchronous and Synchronous Communications This pre defined character is called a sync character or sync flag Once the sync flag is received the communications device will start character assembly Sync characters are typically transmitted while the communications line is idle or immediately before a block of information is transmitted To illustrate with an example let s assume that we are c
27. ynchronous and synchronous communications The remainder of this section is devoted to detailing the differences between character framing and bit duration implemented in asynchronous and synchronous communications Asynchronous Communications Asynchronous communications is the standard means of serial data communication for PC compatibles and PS 2 computers The original PC was equipped with a communication or COM port that was designed around an 8250 Universal Asynchronous Receiver Transmitter UART This device allows asynchronous serial data to be transferred through a simple and straightforward programming interface Character boundaries for asynchronous communications are defined by a starting bit followed by a pre defined number of data bits 5 6 7 or 8 The end of the character is defined by the transmission of a pre defined number of stop bits usual 1 1 5 or 2 An extra bit used for error detection is often appended before the stop bits Omega Engineering OMG ACB 530 Page 21 Appendix E Asynchronous and Synchronous Communications Odd Even Idle State Remain Idle of o or Line Unused Next Start Bit ie 5 to 8 Datta Bits gt KEE EES E Stop Bits Figure 8 Asynchronous Communications Bit Diagram This special bit is called the parity bit Parity is a simple method of determining if a data bit has been lost or corrupted during transmission There are several methods for imple
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