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Rabbit 2000™ Microprocessor User`s Manual

1. c clocks HN l stop bit start bit pred ing Receiver Data Bit Asvnchronous Receive Transmitter Data Reg Full Asynchronous Transmit Bit 0 Bit 7 SCLK Synchronous Receive Transmit Transmit clock is input clock 2 Figure 32 Serial Port Synchronization To transmit in internal clock mode the user must first load the data register which must be empty and then store the send code When the shift register is finished sending the cur rent character if any the data register will be loaded into the shift register and transmitted an 8 clock burst One character can be in the process of transmitting while another character is waiting in the data register tagged with the send code The send code is effec tivelv double buffered To receive a character in internal clock mode the receive shift register should be idle The user then stores the receive code in the control register A burst of 8 clocks will be gener ated and the sender must detect the clocks and shift output data to the data line on the fall ing edge of each clock The receiver will sample the data on the rising edge of each clock The receive mode cannot double buffer characters when using the internal clock The shift register must be idle before another character receive can be initiated However the interrupt request and character ready takes place o
2. HL 10101110 5 fr 5 LO 11011101 10101110 d 9 fr s LO XOR IY d 11111101 10101110 d 9 fr s LO XOR n 11101110 4 fr L0 XOR r 10101 r 2 fr L0 ZINTACK interrupt 10 User s Manual 165 166 Rabbit 2000 Microprocessor Appendix Rabbit Programming Port The programming port provides a standard physical and electrical interface between a Rabbit based system and the Dynamic C programming platform A special interface cable and converter connects a PC serial port to the programming port The programming port is implemented by means of a 10 pin standard 2 mm connector Of course the user can change the physical implementation of the connector if he so desires With this setup the PC can communicate with the target reset it and reboot it The DTR line on the PC serial interface is used to drive the target reset line which should be drivable by an external CMOS driver The STATUS pin is used to by the Rabbit based target to request attention when a breakpoint is encountered in the target under test The SMODE pins are pulled up by 5 3 volt level from the interface They should be pulled down on the board when the interface is not in use by approximately 5k resistors to ground The target under test provides the 45 V or 3 V to the interface cable which is used to power the RS 232 driver and receiver Programming Port Pin Assignments Rabbit PQFP pins shown
3. Timer A4 Time Constant 4 Register TATSR 0ABh Timer A5 Time Constant 5 Register TAT6R 0ADh Timer Time Constant 6 Register TAT7R 0AFh Timer A7 Time Constant 7 Register 0 000 Timer B Control Status Register 0 1h 0000 Timer B Control Register TBM1R 0B2h Timer MSB 1 Reg TBLIR OB3h Timer B LSB 1 Reg TBM2R 0B4h Timer MSB 2 Reg TBL2R 0B5h Timer B LSB 2 Reg TBCMR OBEh xxxxxxxx Timer B Count MSB Reg TBCLR 0BFh Timer B Count LSB Reg User s Manual Table 6 Rabbit Internal I O Registers Address Reset Value Functionalitv SADR 0COh Serial port A data register receive send SAAR 0C lh Serial port A alternate data register transmit 9th bit SASR 0C3h Oxx00000 Serial port A status register SACR 0C4h xx000000 Serial port A control register SBDR 0D0h Serial port B data register receive send SBAR 0D 1h Serial port B alternate data register transmit 9th bit SBSR 0D2h 0 00000 Serial port B status register SBCR 0D3h xx000000 Serial port B control register SCDR 0E0h Serial port C data register receive send SCAR OEIh Serial port C alternate data register tr
4. 000 b 001 010 D 011 E 100 H 101 1 110 hi 111 f alternate destination prefix permitted only flags stored in F r in A column alternate destination prefix stores to alternate S in I column I O prefixes are allowed IOE IOI I O is source d in I column I O prefixes are allowed IOE IOI I O is dest V overflow flag set on overflow L overflow flag set if upper 4 bits of data word are zero flag not affected flag is set by operation Flag labels S sign Z zero V overflow C carry Instruction Byte 1 Byte 2 Byte 3 Byte 4 A 15 ADC A HL 10001110 5 fr sS V ADC 11011101 10001110 d 9 fr 55 ADC A IY d 11111101 10001110 d 9 fr s ADC 11001110 n 4 fr V ADC A r 10001 r 2 fr V ADC HL ss 11101101 01551010 4 fr eV ADD A HL 10000110 5 fr ADD 11011101 10000110 d 9 fr s V ADD A IY d 11111101 10000110 d 9 fr s V ADD A n 11000110 n 4 fr Vk ADD A r 10000 r 2 fr V ADD HL ss 00ss1001 2 fr ADD IX xx 11011101 00 1001 4 f ADD IY yy 11111101 00 1001 4 f ADD SP d 00100111 d 4 f ALTD 01110110 2 miel AND HL 10100110 5 fr s L0 AND IX d 11011101 10100110 d 9 fr s L0 AND IY d 11111101 10100110 d 9 fr s L0 AND HL DE 11011100 2 fr L O AND IX
5. The day of the week is not used to compute the long seconds but it is generated when computing from long seconds to the structure A utility routine setclock c is available to set the date and time in the real time clock from the Dynamic C console 16 4 WatchDog Support Software A microprocessor system can crash for a variety of reasons A software bug or an electri cal upset are common reasons When the system crashes the program will typically settle into an endless loop because parameters that govern looping behavior have been cor rupted Typically the stack becomes corrupted and returns are made to random addresses The usual corrective action taken in response to a crash is to reset the microprocessor and reboot the system The crash can be detected either because an anomaly is detected by pro gram consistency checking or because a part of the program that should be executing peri odically is not executing and the watchdog times out 142 Rabbit 2000 Microprocessor Direct detection of crashes is supported in Dynamic by certain checksumming opera tions and other causes of error that are classed as fatal errors The virtual watchdog system allows establishing multiple virtual watchdogs for different parts of the program which must be executed periodically If any of the virtual watchdogs times out then hits are withheld from the hardware watchdog and it times out resulting in a hardware reset The virtual watchdogs are imp
6. A amp HI XOR IX d 9 frs LO A amp IX d A amp XOR IY d 9 frs LO amp IY d A amp IY d XOR n 4 fr LO A A amp n A amp n XOR r 2 fr LO A A amp r amp r 18 11 8 bit Bit Set Reset and Test Instructions Instruction clk A ISZVC Operation BIT b HL 7 f s HL amp bit BIT b IX d 10 f s IX4d amp bit BIT b IX4d 10 f s Ir d amp bit BIT b r 4 f r amp bit RES b HL 10 d HL HL amp bit RES b IX d 13 d IX d IX4d amp bit RES b IX4d 13 d IY d 1 44 amp rbit RES b r 4 r amp bit SET b HL 10 b HL HL bit SET b IXHd 13 b IX d IX d bit SET b I d 13 b IY d IY d bit SET b r 4 r r rr bit 18 12 8 bit Increment and Decrement Instruction clk A ISZVC Operation DEC HL 8 f b V HL 1 DEC IX d 12 f b v IX d 1 DEC IY d 12 f b v IY d IY d 1 DEC r 2 fr vV r r 1 INC HL 8 f b V HL 41 INC 12 f b v IX d IX d 1 INC 12 f b v IY d iY4d 1 INC r 2 fr V 1 18 13 8 bit Fast A register Operations Instruction clk A ISZVC Operation CPL 2 r A NEG 4 fr 0 154 Rabbit 2000 Microprocessor RLA 2 fr RLCA 2 fr RRA 2 fr RRCA 2 fr 15 14 8 bit Shifts and
7. IY d 7 1 IY d 0 r 0 r 7 1 CY r 0 HL 6 01 0 CY r HL HL 7 IX d 6 0 0 IX d 71 IY d 6 0 0 IY d 71 r 6 0 0 CY r 7 HL 7 HL 7 11 HL 0 r HL CY User s Manual 155 18 15 18 16 18 17 SRA IX d 13 f b L IX d 7 IX d 7 1 CY IX d 0 SRA IY d 13 f b L IY d IY d 7 IY d 7 1 CY IY d 0 SRA r 4 fr L r 7 r 7 1 r 0 SRL 10 f b L 0 HL 7 1 0 SRL IX d 13 f b L IXtd 0 IX d 7 1 IX d 0 SRL IY d 13 f b L IY d 0 7 1 0 SRL r 4 fr L r 0 r 7 1 CY r 0 Instruction Prefixes Instruction clk A ISZVC Operation ALTD 2 alternate register destinatIn for next Instruction IOE 2 I O external prefix IOI 2 I O internal prefix Block Move Instructions Instruction clk A IS 2 VC Operation LDD 10 d DE HL BC BC 1 DE DE 1 HL HL 1 LDDR 647i d if BC 0 repeat LDI 10 d DE HL BC BC 1 DE DE 1 HL HL 1 LDIR 647i d if BC 0 repeat If any of the block move instructions are prefixed by an I O prefix the destination will be in the specified I O space Add 1 clock for each iteration for the prefix if the prefix is IOI internal I O If the prefix is
8. 00110100 8 f INC IX d 11011101 00110100 d 12 f b Vv INC IY d 11111101 00110100 d 12 f b Vv INC IX 11011101 00100011 4 11111101 00100011 4 00 r 100 2 fr y INC ss 00ss0011 2 r ss 00 BC 01 DE 10 HL 11 SP IOE 11011011 2 11010011 2 IP 0 11101101 01000110 4 1 11101101 01010110 4 iz IP 2 11101101 01001110 4 E Sse IP 3 11101101 01011110 4 IPRES 11101101 01011101 4 11101001 4 11011101 11101001 6 JP IX 11111101 11101001 6 f mn 11 f 010 m 7 JP mn 11000011 n m 7 JR 001 000 2 5 JRe 00011000 2 5 Note If bvte following op code is zero next sequential instruction is executed If byte is 2 11111110 jr is to itself LCALL nbr mn 11001111 n m xpc 19 EM ES LD BC A 00000010 7 do mo LD DE A 00010010 7 e eS LD HL n 00110110 n 7 d 10 HL r 01110 r 6 So LD HL d HL 11011101 11110100 d 13 d LD IX d HL 11110100 4 11 e 162 Rabbit 2000 Microprocessor LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD IXHd n IXHd r IXHd HL IXHd n IXHd r mn A mn HL mn IX IY mn ss SP n HL SP n IX SP n IY A BC
9. Master writes status register Figure 35 Slave Port Handshaking and Interrupts First Slave Rabbit Master Rabbit D0 D7 SD0 SD7 ls IORD ISRD IOWR ISWR SAO Al ISA1 SMODEO a SMODEI INTOA LLL LLLI SLAVEATTN rt TT ty 17 ISCS INTIA N 16 Second Slave Rabbit Reset Pulldown SMODEO SLAVEATIN MOPE SCS lt Z Figure 36 Typical Connection Slave Rabbit to Master Rabbit User s Manual 119 The slave port lines are shown in Figure 33 The function of these lines is described below e SDO SD7 These are bidirectional data lines and are generally connected to the data bus of the master processor Multiple slaves can be connected to the data bus The slave drives the data lines only when SCS and SRD are both pulled low e SAI SA0O These are address lines used to select one of the four data registers of the slave interface Normallv these lines are connected to the low order address lines of the master The master alwavs drives these lines which are alwavs inputs to the slave e SCS Input Slave chip select The slave ignores read or write requests unless the chip select is low If a Rabbit is used as a master this line can be connected to one of the master s programmable chip select lines I0 I7 e SRD Input If SCS is also low this line pulled low causes the contents of the regis ter selected by the address lines to be driven on t
10. Synchronization Ei Figure 8 Memory Interface Unit User s Manual 23 3 2 1 Extended Code Space A crucial element of the Rabbit memorv mapping scheme is the abilitv to execute pro grams containing up to a megabyte of code in an efficient manner This ability is absent in a pure 16 bit address processor and it is poorly supported by the Z180 through its memory mapping unit On paged processors such as the 8086 this capability is provided by pag ing the code space so that the code is stored in many separate pages On the 8086 the page size is 64K so all the code within a given page is accessible using 16 bit addressing for jumps calls and returns When paging is used a separate register CS on the 8086 is used to determine where the active page currently resides in the total memory space Special instructions make it possible to jump call or return from one page to another These spe cial instructions are called long calls long jumps and long returns to distinguish them from the same operations that only operate on 16 bit variables The Rabbit also uses a paging scheme to expand the code space beyond the reach of a 16 bit address The Rabbit paging scheme uses the concept of a sliding page which is 8K long This is the XPC segment The 8 bit XPC register serves as a page register to specify the part of memory where the window points When a program is executed in the XPC segment normal 16 bit jumps calls and returns are
11. The Rabbit is highly code compatible with the 780 and Z180 and it is easy to port non I O dependent code The main areas of incompatibility are instructions that are concerned with I O or particular hardware implementations The more important instructions that were dropped from the Z80 Z180 are automatically simulated by an instruction sequence in the Dynamic C assembler A few fairly useless instructions have been dropped and can not be easily simulated Code using these instructions should be rewritten The following Z80 Z180 instructions have been dropped and there is no exact substitute DAA HALT DI EI IM 0 IM 1 IM 2 OUT IN OUTO INO SLP OUTI IND OUTD INIR OTIR INDR OTDR TESTIO MLT SP RRD RLD CPI CPIR CPD CPDR Most of these op codes deal with I O devices and thus do not represent transportable code The only opcodes that are not processor I O related are MLT SP DAA RRD RLD CPI CPIR CPD and CPDR MLT SP is not a practical op code The codes that are concerned with decimal arithmetic DAA RRD and RLD could be simulated but the simulation is very inefficient The bit in the status register used for half carry is available and can be set and cleared using the push and pop af instructions to gain access Usually code that uses these instructions should be rewritten The instructions CPI CPIR CPD and CPDR are repeating compare instructions These instructions are not very useful because the scan stops when eq
12. XPC STACKSEG DATASEG 00 Boundary SEGSIZE 0 3 Boundary SEGSIZE 4 7 i I Stack segment 64K Extended code XPC segment 8K 4K typ segment Root segment OK 16 bit address 20 bit address Figure 21 Memorv Segments The memorv management unit accepts a 16 bit address from the processor and translates it into a 20 bit address The procedure to do this works as follows 1 Itis determined which segment the 16 bit address belongs to by inspecting the upper 4 bits of the address Every address must belong to one of the possible 4 segments 2 Each segment has 8 bit segment register The 8 bit segment register is added to the upper 4 bits of the 16 bit address to create a 20 bit address Wraparound occurs if the addition would result in an address that does not fit in 20 bits Table 18 Segment Registers Segment Register Function XPC Locates extended code segment in physical memory Read and written by processor instructions ld ld xpc a Icall lret STACKSEG 11h Locates stack segment in physical memory DATASEG 12h Locates data segment in physical memory Table 19 Segment Size Register Bits 7 4 Bits 3 0 SEGSIZE 13h Boundary address stack segment Boundary address data segment 82 Rabbit 2000 Microprocessor 8 2 Memo
13. ld a iir ld iir a ld a eir ld eir a Interrupts are initiated by hardware devices or by certain 1 byte instructions called reset instructions rst 10 rst 18 rst 20 rst 28 rst 38 The RST instructions are similar to those on the Z80 and Z180 but certain ones have been removed from the instruction set 00 08 30 The RST interrupts are not inhibited regard less of the processor priority The user is advised to exercise caution when using these in structions as they are mostly reserved for the use of Dynamic C for debugging Unlike the Z80 or Z180 the IIR register contributes the upper byte of the service routine address for RST interrupts Since interrupt routines do not affect the XPC interrupt routines must be located in the root code space However they can jump to the extended code space after saving the XPC on the stack 3 5 1 Interrupt Priority The Z80 and Z180 have two levels of interrupt priority maskable and nonmaskable The nonmaskable interrupt cannot be disabled and has a fixed interrupt service routine address of 66h The Rabbit in contrast has three levels of interrupt priority and four priority lev els at which the processor can operate If an interrupt is requested and the priority of the interrupt is higher than that of the processor the interrupt will take place after the execu tion of the current instruction is complete except for privileged instructions Multiple interrupt priorities have been establ
14. write only bits These can be read by consulting the shadow provided that the shadow register is always updated when writing to the register k GCSRShadow In order to write a write onlv register and update the shadow register the following rou tines can be used WrPortI GCSR amp GCSRShadow value update register and shadow BitWrPorti GCSR sGCSRShadow 1 5 set 1 to bit 5 of GCSR In the WrPorti routine a zero can be substituted for the pointer to the shadow register if no shadow register is to be used The pointer to the shadow register is manditory for BitWr Porti 16 2 Shadow Registers Many of the registers of the Rabbit s internal I O devices are write only Write only regis ters save gates on the chip making possible greater capabilitv at lower cost Tvpical de signs that implement external I O registers also have write only registers due to the cost saving of not having the additional hardware to make it possible to read back the register s contents Write only registers are easier to use if a memory location called a shadow reg ister is associated with each write only register In order to make the names of the shad ows easy to remember they are compounded from the internal register names used in this manual For example the regiser PADR port A data register has the shadow PADRShadow Some shadow registers are defined in the bios files as shown below the internal I O registers the shadows parallel po
15. 92 VSS Ground 2 27 39 52 77 89 User s Manual 55 Table 3 Rabbit Pin Assignments Clock for serial port A when operating in Serial Ports JCLKA svnchronous mode Alternate assignment 94 for Clock for serial port A when operating in Serial Ports CLKB svnchronous mode Alternate assignment 93 ut for PBO BA RX input Serial inputs and output for serial ports A RXB TXB Serial Ports TX D These are alternate pin assignments for 51 54 60 MET arallel port C RXD TXD output p RX input jali i ARXA input Alternate serial inputs and output for serial Serial Ports ARXB ATXB ports A and B These are alternate pin 43 46 output assignments for parallel port D PD4 PD7 Slave Port SD0 SD7 Biitreetional Ror 81 88 assignment for parallel port A SLAVEATTN Slave is requesting atten Slave Port SLAVEATTN Output tion from the master An alternate pin 100 assignment for parallel port B bit 7 Strobe used to read one of the slave Slave Port SRD Input registers An alternate pin assigmeent for 96 parallel port B bit 3 Strobe used to write a slave register An Slave Port SWR Input alternate pin assignment for parallel port B 95 bit 2 Address lines to address slave registers Slave Port SAO SAI Input An alternate pin assigment for paralle
16. Any of the 8 bit registers A B C D E H and L can be moved to any other 8 bit regis ter for example H a d e BH A bba The alternate 8 bit registers can be a destination for example 14 a c ld d b These instructions are unique to the Rabbit and require 2 bytes and four clocks because of the required prefix byte Instructions such as ld a d or Id d e are not allowed Several 16 bit register to register move instructions are available Except as noted these instructions all require 2 bytes and four clocks The instructions are listed below ld dd bc where dd is any of hl de bc 2 bytes 4 clocks 1 dd de 14 ix hl ld iy hl ld hl iy ld hl ix ld sp hl l byte 2 clocks ld sp ix ld sp iy Other 16 bit register moves can be constructed by using 2 byte moves 3 3 5 Register Exchanges Exchange instructions are very powerful because two or more moves are accomplished with one instruction The following register exchange instructions are implemented ex af af exchange af with af exx exchange hl de bc with hl de bc ex de hl exchange de and hl The following instructions are unique to the Rabbit ex de hl 1 byte 2 clocks ex de hl 2 bytes 4 clocks ex de hl 2 bytes 4 clocks User s Manual 29 The following special instructions Rabbit and Z180 Z80 exchange the 16 bit word on the top of the stack with the HL register These thr
17. IIR A MMU EIR A IIR HL IX HL IY IX HL IY HL SP HL SP IX SP IY dd BC dd 00 BC O1 DE 10 HL dd DE dd 00 BC O1 DE 10 HL Operation H lt gt SP 1 L lt gt SP IXH lt gt 8 1 lt gt SP 1 IXL lt gt SP IYL lt gt SP User s Manual 151 EX AF AF 2 AF lt gt AF EX DE HL 2 s if ALTD then DE lt gt HL else DE HL EX DE HL 4 s pE lt gt HL EX DE HL 2 s if ALTD then DE lt gt HL else DE lt gt HL EX DE HL 4 s DE lt gt HL EXX 2 BC lt gt BC DE lt gt DE HL lt gt HL ex de hl F HI L D E B C ex af af l ex de hl ex EA F H L D E B Wee exx exchange hl hl de de bc be ex de hl 18 8 Stack Manipulation Instructions Instruction ADD SP d POP IP POP IX POP IY POP zz PUSH PUSH IP IX PUSH IX PUSH zz clk A 150 1 1 1 2 2 22 0 Operation SP SP d d 0 to 255 IP SP SP SP 1 IXL SP IXH SP 1 SP SP 2 IYL SP IYH SP 1 SP SP 2 zzl SP zzh SP41 SP SP 2 zz BC DE HL AF SP 1 IP SP SP 1 SP 1 IXH SP 2 IXL SP SP 2 SP 1 IYH SP
18. IIR 20h RST 18 instruction n a IIR 00110000 IIR 30h RST 20 instruction n a IIR 01000000 IIR 40h RST 28 instruction n a IIR 01010000 IIR 50h RST 38 instruction n a IIR 01110000 IIR 70h 76 Rabbit 2000 Microprocessor Interrupts have priority 1 2 or 3 The processor operates at priority 0 1 2 or 3 If an in terrupt is being requested and its prioritv is higher than the prioritv of the processor the interrupt will take place after then next instruction The interrupt automaticallv raises the processor s prioritv to its own prioritv The old processor prioritv is pushed into the 4 po sition stack of priorities contained in the IP register Multiple devices can be requesting interrupts at the same time In each case there is a latch set in the device that requests the interrupt If that latch is cleared before the interrupt is latched by the central interrupt logic then the interrupt request is lost and no interrupt takes place This is shown in Table 16 The priorities shown in this table apply only for interrupts of the same priority level and are only meaningful if two interrupts are requested at the same time Most of the devices can be programmed to interrupt at priority level 1 2 or 3 Table 16 Interrupts Priority and Action to Clear Requests Priority Interrupt Source Action Required to Clear the Interrupt Highest External 1 Automatically by interrupt acknowledge External 0 Automat
19. SP SP 2 IP SP PCL SP41 PCH SP 2 SP SP 3 SP 1 PCH SP 2 PCI SP SP 2 PC R v v 10 18 20 28 38 only Operation CF CF IP IP 5 0 00 IP IP 5 0 01 IP IP 5 0 10 IP IP 5 0 11 IP IP 1 0 IP 7 2 A EIR A IIR A MMU EIR A IIR A XPC A No Operation IP SP SP SP 1 SP 1 IP SP SP 1 CF 1 SP 1 PCH SP 2 PCL SP SP 2 IP IP 6 The privileged instructions are described in this section Privilege means that an interrupt cannot take place between the privileged instruction and the following instruction The three Instructions below are privileged ld sp hl load the stack pointer ld sp iy ld sp ix User s Manual 157 The instructions to load the stack are privileged so that thev can be followed bv an instruc tion to load the stack segment SSEG register without the danger of an interrupt taking place with and incorrect association between the stack pointer and the stack segment reg ister For example ld sp hl ioi ld STACKSEG a The following instructions are privileged ip O shift ip left and set priority 00 in bits 1 0 1 2 3 rotate ip right 2 bits restoring previous prioritv pop ip Pop IP register from stack The instructions to modifv the IP register are privileged so that thev can be followed bv a return instructions that is guaranteed to execute before another i
20. d d m m 8 amp oa S N S N O O fr fr H HHHHHH HHHHH e p op am a ununun m User s Manual 163 LDD 11101101 10101000 10 d LDDR 11101101 10111000 6 71 4 3 LDI 11101101 10100000 10 d LDIR 11101101 10110000 6 71 4 3 LDP HL HL 11101101 01100100 12 LDP IX HL 11011101 01100100 12 SSeS LDP IY HL 11111101 01100100 12 SS hes LDP mn HL 11101101 01100101 n m 15 me LDP mn IX 11011101 01100101 n m 15 SS LDP mn IY 11111101 01100101 n m 15 LDP HL HL 11101101 01101100 10 u LDP HL IX 11011101 01101100 10 Sree LDP HL IY 11111101 01101100 10 LDP HL mn 11101101 01101101 n m 13 A DEC LDP IX mn 11011101 01101101 n m 13 LDP IX mn 11111101 01101101 n m 13 M EE LJP nbr mn 11000111 n m nbr 10 Ses LRET 11101101 01000101 13 Sa SiS MUL 11110111 12 11101101 01000100 4 fr V NOP 00000000 2 SAS vm OR HL 10110110 5 fr s LO OR IX d 11011101 10110110 d 9 fr s LO OR IY d 11111101 10110110 d 9 fr s LO OR HL DE 11101100 2 fr L0 OR IX DE 11011101 11101100 4 LO OR IY DE 11111101 11101100 4 f L OR n 11110110 n 4 fr L0 OR r 10110 r 2 fr L0 POP IP 11101101
21. parallel slave port 46 Rabbit 2000 Microprocessor The cold boot protocol accepts groups of three bvtes that define an address and a data byte Each triplet causes a write of the data byte to either memory or to internal I O space The high bit of the address is set to specify the I O space and thus writes are limited to the first 32K of either space The cold boot is terminated by a store to an address in I O space which causes execution to begin at address zero Since any memory chip can be remapped to address zero by storing in the I O space RAM can be temporarily be mapped to zero to avoid having to deal with the more complicated write protocol of flash memory which is the usual default memory located at address zero The following are the advantages of the cold boot capability e Flash memory can be soldered to the microprocessor board and programmed via a serial port or a parallel port This avoids having to socket the part or program it with a BIOS or boot program before soldering Complete reprogramming of the flash memory can be accomplished in the field This is particularly useful during software development when the development platform can perform a complete reload of software regardless of the state of the existing software in the processor The standard programming cable for Dynamic C allows the develop ment platform to reset and cold boot the target a Rabbit based microprocessor board fthe Rabbit is used as a sl
22. this signal is driven low during an external I O cycle and may be used to control 3 state enable on the bus buffer The purpose is to save power by not driving the I O address or data lines on every bus cycle 33 User s Manual 53 Table 3 Rabbit Pin Assignments I O Read Strobe NORD Output read strobe Driven low on an external bus cycle May be used to drive glue logic concerned with I O expansion such as the direction pin on a bidirectional bus buffer See also programmable strobes in port E 32 I O Write Strobe write strobe Driven low a write strobe during external I O read cycles See also programmable strobes in port E 31 I O Port A PAO PA7 Input Outp ut These 8 bits serve as general purpose input output or they serve as the data port for the slave port On reset these pins are set to inputs and they float 81 88 I O Port B PBO PB7 4 In 2 Out 2 I O Port B When used as parallel I O PB7 and PB6 are outputs only PBO PBS5 are inputs only PBO and PBI can be outputs when set up as the clock for the clocked serial ports On reset outputs are set to zero If the slave port is enabled the following alternate assignments apply PB7 SLAVEATTN slave requests attention PB5 PB4 address lines SA1 SAO for slave registers PB3 slave negative write strobe from master PB2 slave negative read
23. 2 or 3 interrupts Since code that runs at priority level 0 or 1 never disables level 2 and level 3 interrupts these interrupts will take place within about 20 clocks the length of the longest instruction or longest sensible sequence of privileged instructions followed by an unprivi leged instruction It is important that the user be careful not to overdisable interrupts in critical code sections The processor priority should not be raised above level 1 except in carefully considered situations The effect of the processor priority on interrupts is shown in Table 2 The priority of the interrupt is usually established by bits in an I O control register associated with the hard ware that creates the interrupt The 8 bit interrupt register IR holds the processor priority in the least significant 2 bits When an interrupt takes place the IR register is shifted left 2 positions and the lower 2 bits are set to equal the priority of the interrupt that just took place This means that an interrupt service can only be interrupted by an interrupt service routine for an interrupt of higher priority unless the priority is explicitly set lower by the programmer The IR register serves as a 4 word stack to save and restore interrupt prior ity It can be shifted right restoring the previous priority by a special instruction ipres Since only the current processor priority and 3 previous priorities can be saved in IP in structions are also provided to push
24. 4 To these figures must be added current consumed by memory and other devices included in the system The 32 768 clock oscillator consumes approximately 70 uA at 3 volts At 2 4 volts when backed by a battery the consumption is approximately 25 uA Current consumed by RAM or flash memory will be substantial and very significent at lower fre quencies if auto power down flash is not used At this time accurate estimates for current consumption when the main clock is provided by the 32 768 kHz oscillator are not avail able However in principle at 3 3 volts the current should consist of 90 uA for the oscilla tor and 75 uA for the processor or a total of 165 uA 138 Rabbit 2000 Microprocessor 16 Rabbit Software This chapter outlines basic low level software constructs that are recommended for use with the Rabbit microprocessor Bv following these suggestions the user will find it much easier to use the software and to avoid various pitfalls More details can be found bv consulting the Dvnamic C manual or the source code in the Dvnamic C libraries 16 1 Reading and Writing I O Registers and Shadow Registers The Rabbit has two I O spaces internal I O registers and external I O registers Access is the same as for accessing data memory except that the instruction is preceeded by a prefix 101 or ioe to indicate the internal or external I O space The fastest way to read and write I O registers in Dynamic C is to use a short
25. A DE A mn A EIR A IIR dd mn dd BC dd DE dd mn ld bc mn 1 de mn ld hl mn ld sp mn LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD EIR A HL HL d HL HL HL mn HL SP n HL IX HL IY IIR A IIR A IX mn IX SP n IX HL IX mn IY mn SP n IY HL IY mn r HL r IX d r r g r n SP HL SP IX SP IY XPC A 11011101 11011101 11111101 11111101 11111101 00110010 00100010 11011101 11111101 11101101 11010100 11011101 11111101 00001010 00011010 00111010 11101101 11101101 11101101 11101101 11101101 11101101 00dd0001 00000001 00010001 00100001 00110001 11101101 11011101 11100100 11111101 00101010 11000100 11011101 11111101 11101101 11101101 11011101 11011101 11011101 11011101 11111101 11111101 11111101 11111101 01 r 110 11011101 11111101 O1 r r 00 r 110 11111001 11011101 11111101 11101101 00110110 01110 r 11110100 00110110 01110 r 00100010 00100010 01ss0011 ERIS 11010100 11010100 01010111 01011111 01110111 01441011 01441001 01440001 a 01000111 11100100 q 11100100 01111100 01111100 01001111 01001111 00101010 11000100 01111101 00100001 00101010 11000100 01111101 00100001 01 r 110 01 r 110 J 11111001 11111001 01100111 d d d
26. as priorities allow However if the bit is cleared before the inter rupt is latched the bit will not cause an interrupt The proper rule to follow is for the inter rupt routine to handle all bits that it sees set 11 1 1 Timer A I O Registers The I O registers for Timer A are listed in Table 30 Table 30 Timer I O Registers Register Name Register Mnemonic I O address hex R W Timer A Control Status Register TACSR AO R W Timer A Control Register TACR A4 Timer A1 Time Constant 1 Register TATIR A3 W Timer A4 Time Constant 4 Register TATAR A9 Timer 5 Time Constant 5 Register TATSR AB Timer A6 Time Constant 6 Register 6 Timer A7 Time Constant 7 Register TAT7R AF w The control status register for Timer A TACSR is laid out as shown in Table 31 Table 31 Timer A Control and Status Register adr 0A0h Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit2 Bit 1 Bit 0 Read 7 count A6 count A5 count A4 count 0 0 A count 999 done done done done done Write AT interrupt A6 interrupt A5 interrupt A4 interrupt 4 Al interrupt I enable enable enable enableb enable enable Timer A Bits 1 4 71 Read only terminal count reached on timers Al and A4 A7 Reading this status register clears any bits bits 1 and 4 7 that are on Bit 0 Wirite set to a 1 to enable the clock perclk 2 for Timer A set to zero to disable the
27. be accomplished in manv wavs using the Rabbit Bv publish ing design standards or standard wavs to accomplish common objectives software and hardware support become easier 2 3 1 Programming Port Rabbit Semiconductor publishes a specification for a standard programming port see Rabbit Programming on page 167 and provides a converter cable that may be used to connect a PC serial port to the standard programming interface The interface is imple mented using a 10 pin connector with two rows of pins on 2 mm centers The port is con nected to Rabbit serial port A to the startup mode pins on the Rabbit to the Rabbit reset pin and to a programmable output pin that is used to signal the PC that attention is needed With proper precautions in design and software it is possible to use serial port A as both a programming port and as a user defined serial port although this will not be nec essary in most cases Rabbit Semiconductor supports the use of the standard programming port and the standard programming cable as a diagnostic and setup port to diagnosis problems or set up systems in the field 2 3 2 Standard BIOS Rabbit Semiconductor provides a standard BIOS for the Rabbit The BIOS is a software program that manages startup and shutdown and provides basic services for software run ning on the Rabbit 2 4 Dynamic C Software Support for the Rabbit Dynamic C is Z World s interactive C language development system Dynami
28. between registers we will refer to the registers as SPDOR writable by the slave or SPDOR readable by the master different descriptions for the same register A status register can be read by either the slave or the master The status register has full empty bits for each of the six registers A data register is considered full when it is written to by whichever side is capable of writing to it If the same register is then read by either side it is considered to be empty The flag for that register is thus set to a 1 when the reg ister is written to and the flag is set to a 0 when the register is read User s Manual 117 The registers appear to be internal I O registers to the slave To the master at least for a Rabbit master the registers appear to be external I O registers Figure 34 shows the se quence of events when the master reads writes the slave port registers SCS 5 1 SAO d X valid Read from Slave Register SRD SCS SA1 SAO Write to Slave Register SD7 SDO SWR SLAVEATTN On write to status register transitions to high Figure 34 Slave Port R W Sequencing The two SPDOR registers have special functionality not shared by the other data registers If the master writes to SPDOR an inbound interrupt flip flop is set If slave port interrupts are enabled the slave processor will take a slave port interrupt If the slave writes
29. can be modified to multiplv a signed number bv an unsigned number In that case only the unsigned number has to be tested to see if the sign is o n and in that case the signed number is added to the upper part of the product The multiply instruction can also be used to perform left or right shifts A left shift of n positions can be accomplished by multiplying by the unsigned number 2 n This works for n f 15 and it doesn t matter if the numbers are signed or unsigned In order to do a right shift by n 0 n 16 the number should be multiplied by the unsigned number 2 16 n and the upper part of the product taken If the number is signed then a signed by unsigned multiply must be performed If the number is unsigned or is to be treated as unsigned for a logical right shift then an unsigned by unsigned multiply must be per formed The problem can be simplified by excluding the case where the multiplier is gp 3 3 8 Input Output Instructions The Rabbit uses an entirely different scheme for accessing input output devices Any memory access instruction may be prefixed by one of two prefixes one for internal I O space and one for external I O space When so prefixed the memory instruction is turned into an I O instruction that accesses that I O space at the I O address specified by the 16 bit memory address used For example ioi ld a 85h loads A register with contents of internal I O register at location 85h ld iy 4000
30. cold boot from asynchronous serial port A at 2400 bps The smode pins can be used as general input pins once the cold boot is complete 35 36 1 0 Chip Selects CSO Output Memory Chip Select 0 connects directly to static memory chip chip select pin Normally this pin is used to select base flash memory that holds the program 51 Memory Chip Select 1 normally this pin is connected directly to static RAM chip select CS1 can be optionally forced continuously low under software control a feature that aids in the use of battery backed RAM when the chip select must pass through a controller that may have a slow propagation time ICS2 Output Memory Chip Select 2 connect to static memory chip Use this chip select last Output Enables OEO Output Memory Output Enable 0 connect directly to static memory chip 1 Memory Output Enable 1 alternate memory output enable allows chip selects to be shared between two memory chips 76 Write Enables WEO Output Memory Write Enable 0 connect directly to static memory chip This pin may be disabled under software control to write protect the chip 69 WEI Output Memory Write Enable 1 connect directly to static memory chip This pin may be disabled under software control to write protect the chip 80 I O Control BUFEN Output Buffer Enable
31. configure the slave with both RAM and flash memory In this case the slave will only have the program downloaded for maintenance or upgrades Usually the flash would not be written to on every startup be cause of the limited number of lifetime writes to flash memory The slaves reset in Figure 36 is under the program control of the master If the master is reset the slave will also be reset because the master s drive of the reset line will be lost on reset and the pull down resistor will pull the slaves resets low This may be undesirable because it forces the slave to crash if the master crashes and has a watchdog timeout 120 Rabbit 2000 Microprocessor 13 2 Slave Port Registers The slave port registers are listed in Table 40 These registers each of which is actually two separate registers one for read and one for write are accessible to the slave at the I O ad dresses shown in the table and they are accessible to the master at the external address shown which specifies the value of the slave address SAO SA1 input to the slave when the master reads or writes the registers The register that can be written by the slave can only be read by the master and vice versa If one side were to attempt to read a register at the same time that the other side attempted to write the register the result of the read could be scram bled However the protocols and handshaking bits used in communication are normally such that this never happens
32. consumption is dramatically decreased The current consumption is often reduced to the region of 100 u A at this clock speed The Rabbit executes about 6 instructions per millisecond at this low clock speed Generally when the speed is reduced to this extent the Rabbit will be in a tight polling loop looking for an event that will wake it up The clock speed is increased to wake up the Rabbit 128 Rabbit 2000 Microprocessor 14 8 Basic Memorv Design Normally CSO and OEO and WEO should be connected to a flash memory that holds the startup code that executes at address zero When the processor exits reset with SMODEI SMODEDO set to 0 0 it will attempt to start executing instructions at the start of the memory connected to 50 OEO and WEQ By convention the basic RAM memory should be connected to CS1 OE1 and WEI CS1 has a special property that makes it the preferred chip select for battery backed RAM A bit may be set in the MMIDR register to force CS1 to stay enabled low see Table 21 in Section 8 3 1 This capability can be used to counter a problem encountered when the chip select line is passed through a device that is used to place the chip in standby by raising CS1 when the power is switched over to battery backup The battery switchover device typically has a propagation delay that may be 20 ns or more This is enough to require the insertion of wait states for RAM access in some cases By forcing CS1 low the p
33. de 7 pophl 7 af 7 ret 8 Ne from interrupt 117 clocks to here User s Manual 113 This routine gets the interrupts turned on in about 68 clocks or 3 5 us ata clock speed of 20 MHz Although two characters may be handled out of order this will be invisible to a higher level routine checking the status of the input buffer because all the interrupts will be completed before the higher level routine can perform a check on the buffer status A typical way to organize the buffers is to have an in pointer and an out pointer that incre ment through the addresses in the data buffer in a circular manner The interrupt routine manipulates the in pointer and the higher level routine manipulates the out pointer If the in pointer equals the out pointer the buffer is considered full If the out pointer plus 1 equals the in pointer the buffer is empty increments are done in a circular fashion most easily accomplished by making the buffer a power of two in length and and ing a mask after the increment The actual memory address is the pointer plus a buffer base ad dress 12 6 1 Controlling an RS 485 Driver and Receiver RS 485 uses a half duplex method of communication One station enables its driver and sends a message After the message is complete the station disables the driver and listens to the line for a reply The driver must be enabled before the start bit is sent and not dis abled until the stop bit ha
34. each row The advantage of using open drain outputs is that if two keys in the same col umn are depressed there will not be a fight between a driver driving the line high and an other driver driving it low TE Cv DA Pw N PEE XL NU TT pay DNO Pd N V AU Figure 12 Using Open Drain Outputs for Scan 4 3 Cold Boot Most microprocessors start executing at a fixed address often address zero after a reset or power on condition The Rabbit has two mode pins SMODEO SMODE 1 see Figure 13 on page 49 The logic state of these two pins determines the startup proceedure after a re set If both pins are grounded then the Rabbit starts executing instructions at address zero On reset address zero is defined to be the start of the memory connected to the memory control lines CSO and OEO However three other startup modes are available These alternate methods all involve accepting a data stream via a communications port that is used to store a boot program in a RAM memory which in turn can be used to start any further seconary boot process such as downloading a program over the same commu nications port For a detailed description see Section 7 9 on page 79 Three communication channels may be used for the bootstrap either serial port A in asyn chronous mode at 2400 bps serial port A in synchronous mode with an external clock or the
35. floating point arithmetic is an important productivity feature in smaller systems It is easy to solve many programming problems if an adequate floating point capability is available The Rabbit s improved instruction set provides fast floating point and fast integer math capabilities The Rabbit supports four levels of interrupt priorities This is an important feature that al lows the effective use of super fast interrupt routines for real time tasks 2 1 The Rabbit 8 bit Processor vs 16 bit and 32 bit Processors The Rabbit is a 16 bit processor with an 8 bit data bus Because it make the most of its 8 bit bus and because it has a compact instructions set its performance is as good as many 16 bit processors We hesitate to compare the Rabbit to 32 bit processors but there are undoubtedly occa sions where the user can use a Rabbit instead of a 32 bit processor and save a vast amount of money Many Rabbit instructions are 1 byte long In contrast the minimum instruction length on most 32 bit RISC processors is 32 bits User s Manual 13 2 2 Overview of On Chip Peripherals The on chip peripherals were chosen based on our experience as to what tvpes of periph eral devices are most useful in small embedded svstems The major on chip peripherals are the serial ports svstem clock time date oscillator parallel I O slave port and timers These are described below 2 2 1 Serial Ports There are four serial ports designated ports
36. in 2 Pg a 1 RXA 51 p Y 2 GND 3 CLKA 94 oo 4 5 3 V 5 RESET 37 6 54 90 OQ 10 T n c 50kO 8 STATUS output 38 Pin Numbering 9 SMODE 36 GND Top Circuit side 10 SMODEI 35 GND Figure 42 Rabbit Programming Port A 1 1 Use of the Programming Port as a Diagnostic Setup Port The programming port which is already in place can serve as a convenient communica tions port for field setup diagnosis or other occasional communication need for example diagnostic port There are several ways that the port can be automatically integrated into the user s software scheme If the purpose of the port is simply to perform a setup func tion that is write setup information to flash memory then the controller can be reset through the programming port and a cold boot performed to start execution of a special program dedicated to this functionality The standard programming cable adapter connects the programming interface to a PC pro gramming port The RESET line can be asserted by manipulating DTR on the PC serial port and the STATUS line can be read by the PC as DSR on the serial port The PC can re User s Manual 167 start the target bv pulsing reset and then after a short delav sending a special character string at 2400 bps To simply restart the BIOS the string 24h 80h 80h can be sent When the BIOS is started it can tell if the programming cable is
37. in a variety of customary operating modes two of the ports can also be operated synchronously to interface with serial I O devices The baud rates can be very high 1 32 the clock speed for asynchronous operation and 1 8 the clock speed in synchronous mode In asynchronous mode the Rabbit like the Z180 supports sending flagged bytes to mark the start of a message frame The flagged bytes have 9 data bits rather than 8 data bits the extra bit is located after the first 8 bits where the stop bit is normally located and marks the start of a message frame A slave port allows the Rabbit to be used as an intelligent peripheral device slaved to a master processor The 8 bit slave port has six 8 bit registers 3 for each direction of communication Independent strobes and interrupts are used to control the slave port in both directions Only a Rabbit and a RAM chip are needed to construct a complete slave system if the clock and reset are shared with the master processor The built in battery backable time date clock uses an external 32 768 kHz crystal The time date clock can also be used to provide periodic interrupts every 488 us Typical battery current consumption is 25 with the suggested battery circuit An alternative circuit provides means for substantially reducing this current Numerous timers and counters six all together can be used to generate interrupts baud rate clocks and timing for pulse generation Rabbit 2000 Micropro
38. is a byte in the instruction word BC and DE can serve as index registers only for the special cases be low ld a bc 1 a bc ld bc a ld a de 1 a de ld de a Other 8 bit loads and stores are the following ld r hl is any of 7 registers A C E H L ld r hl same but alternate register destination ld hl r r is any of the 7 registers above or an immediate data byte 1 hl r not a legal instruction 14 r ix d r is any of 7 registers d is 128 to 4127 offset ld r ix d same but alternate destination ix d r r is any of 7 registers or an immediate data byte ld iy d r ix or iy can have offset d The following are 16 bit indexed loads and stores None of these instructions exists on the Z180 or Z80 The only source for a store is hl The only destination for a load is hl or hl ld hl sptd d is an offset from 0 to 255 16 bits are fetched to hl or hl 1 sptd hl corresponding store ld hl hl d d is an offset from 128 to 4127 uses original hl value for addressing 1 1144 h h1 d 1 ld hl hl d ld hl 4d hl ix d hl store hl at address pointed to ix plus 128 to 4127 offset 14 hi ix d ld hl ix d ld iy d hl Store hl at address pointed to by iy plus 128 to 4127 offset ld hi ivtd ld hl iy d 28 Rabbit 2000 Microprocessor 3 3 4 Register to Register Move Instructions
39. jp iy go to the routine 42 Rabbit 2000 Microprocessor 4 Rabbit Capabilities This section describes the various capabilities of the Rabbit that mav not be obvious from the technical description 4 1 Preciselv Timed Output Pulses The Rabbit can output precise pulses under software control The effect of interrupt la is avoided because the interrupt alwavs prepares a future pulse edge that is clocked into the output registers on the next clock This is shown in Figure 11 Timer Output A B C Parallel Port Output us Latency Parallel Port Output Interrupt p routine sets up B edge Timer Output Setup Register Figure 11 Timed Output Pulses The timer output in Figure 11 is periodic As long as the interrupt routine can be com pleted during one timer period an arbitrary pattern of synchronous pulses can be output from the parallel port The interrupt latency depends on the priority of the interrupt and the amount of time that other interrupt routines of the same or higher priority inhibit interrupts The first instruc tion of the interrupt routine will start executing within 30 clocks of the interrupt request for the highest priority interrupt routine This includes 19 clocks for the longest instruction to complete execution and 10 clocks for the interrupt to execute Pushing registers re quires 10 12 clocks per 16 bit register Popp
40. l bit input after boot to write slave register SMODE2 36 Startup boot mode complete control CLK 1 1 clock Programmable output 2 Peripheral clock 2 port high low Outputs 30 5 us pulse on Outputs a pulse between IWDTOUT 34 watchdog timeout pro 30 5 and 61 under cessor is also reset program control 7 88 507 507 6 87 5 6 5 6 5 86 505 505 PAA 85 SD4 SD4 PA3 84 SD3 SD3 PA2 83 SD2 SD2 PA1 82 SD1 SD1 PAO 81 SDO SDO ISLAVEATTN master PB7 100 needs attention from slave PB5 98 SA1 slave address PB4 97 SAO PB3 96 ISRD strobe for master to read a slave register PB2 95 ISWR strobe for master User s Manual 59 Table 4 Pins With Alternate Functions CLKA serial port A PBI 94 clocked mode clock CLKA bidirectional 93 CLKB bidirectional CLKB PC7 51 RXA PC6 54 TXA 5 55 RXB PCA 56 TXB 57 RXC 2 58 1 59 RXD PCO 60 TXD PD7 43 ARXA PD6 44 ATXA PDS 45 ARXB PD4 46 ATXB PD3 47 PD2 48 PDI 49 PDO 50 PE7 21 UR E UO 808 slave chip Sele b PE6 22 16 PES 23 15 INTO input PEA 24 INTI input PE3 25 2 27 12 PEI 39 m INTO input PEO 30 10 INTI input 60 R
41. locations Table 14 Watchdog Timer Test Register WDTTR adr 09h Bit s Value Description 7 0 51h Clock the least significant byte of the WDT timer from the peripheral clock Intended for chip test and code 54h below only 52h Clock the most significant byte of the WDT timer from the peripheral clock Intended for chip test and code 54h below only 53h Clock both bytes of the WDT timer in parallel from the peripheral clock Intended for chip test and code 54h below only Disable the WDT timer This value by itself does not disable the WDT 54h timer Only a sequence of two writes where the first write is 51h 52h or 53h followed by a write of 54h actually disables the WDT timer The WDT timer will be re enabled by any other write to this register other Normal clocking 32 kHz oscillator for the WDT timer This is the condition after reset The code to do this may also hit the watchdog with a 0 25 second period to speed up the reset Such watchdog code must be written so that it is highly unlikely that a crash will in corporate the code and continue to hit the watchdog in an endless loop The following suggestions will help 1 Place a jump to self before the entry point of the watchdog hitting routines This pre vents entry other than by a direct call or jump to the routine 2 Before calling the routine set a data byte to a special value and then check it in the routine to make sure the
42. management scheme 7 3 Controlling Power Consumption The processor power consumption can be traded against speed by slowing the system clock adding wait states using low power consumption instructions and for maximum power savings disabling the main system oscillator and using the real time clock oscillator to provide the clock The following power saving features can be enabled e Add memory wait states for instruction fetching Total wait states are programmable as 0 1 20r 4 Generally two wait states should use half the power of zero wait states fthe clock doubler is not already in use divide both the processor and the peripheral clock by 4 This is permissible if nothing particularly timers and serial ports depends on the peripheral clock e If the clock doubler is in use turn it off dividing both processor and peripheral by 2 Divide the processor and or peripheral clock by 8 e Run code in RAM rather than flash memory Switch the processor and peripheral clock to the 32 768 kHz oscillator and if desired disable the main oscillator 70 Rabbit 2000 Microprocessor Execute a low power instruction loop consisting mostly of instructions that don t use much power The best choice is successive mul instructions that multiply 0 x 0 No intervening instructions are needed to load the terms to be multiplied after the first mul since all registers involved stay at zero It is anticipated that these measures would re
43. not convenient tester software can make the memory safe by sending a byte sequence over the programming connection serial link The following example shows a program that can be downloaded via the cold boot proto col to make a Atmel AT29C010A 128K x 8 flash memory safe In this case the RAM connected to CS1 is used to hold a program starting at address zero The flash memory is mapped into the data segment starting at address 1000h for access to the start of the flash memory before storing this program the RAM is mapped to the first quadrant the program that resides at address zero in RAM note this program has not been tested ld a 0elh el segsize reg ioi 14 13h a 4332 13 00 data seg starts at 1000h ld a 3fh 3e 3f dataseg reg ioi ld 12h a d3 32 12 00 set data seg base of flash to 1000h ld a 0 00 for MBICR memory bank reg for flash on 50 15h a 32 15 00 bank 1 reads flash starting at 256k a 0aah aa ld 5555h 1000h a 32 55 65 first byte of unlock code 14 a 55h 3e 55 ld 2AAAh 1000h a 32 aa 2nd byte of unlock code a 0a0h 3e ld 5555h 1000h a 32 55 65 3rd byte of unlock code h1 1000h 21 00 10 point to start of flash memory 1 h1 0c3h 36 c3 jump op code inc hl 23 hl1 00h 36 00 zero inc hl 23 14 h1 00h 36 00 zero jr 18 fe end with endless loop This code can be sent by means of a sequence of triplets via the se
44. of every instruc tion See Rabbit Instructions on page 149 The Rabbit executes instructions in fewer clocks then the Z80 or Z180 The Z180 usually requires a minimum of four clocks for 1 byte opcodes or three clocks for each byte for mult byte op codes In addition three clocks are required for each data byte read or writ ten Many instructions in the Z180 require a substantial number of additional clocks The Rabbit usually requires two clocks for each byte of the op code and for each data byte read Three clocks are needed for each data byte written One additional clock is required if a memory address needs to be computed or an index register is used for addressing Only a few instructions don t follow this pattern An example is mul a 16 x 16 bit signed two s complement multiply mul is a 1 byte op code but requires 12 clocks to execute Compared to the Z180 not only does the Rabbit require fewer clocks but in a typical situ ation it has a higher clock speed and its instructions are more powerful The most important instruction set improvements in the Rabbit over the Z180 are in the following areas Fetching and storing data especially 16 bit words relative to the stack pointer or the index registers IX IY and HL 16 bit arithmetic and logical operations including 16 bit and s or s shifts and 16 bit multiply 26 Rabbit 2000 Microprocessor e Communication between the regular and alternate registers and between
45. of registers that are easily available for the programmer s use It is not intended that the alternate register set be used to pro vide a separate set of registers for an interrupt routine and Dynamic C does not support this usage because it uses both registers sets freely The IP register is the interrupt priority register It contains four 2 bit fields that hold a his tory of the processor s interrupt priority The Rabbit supports four levels of processor pri ority something that exists only in a very restricted form in the Z80 or Z180 3 2 Memory Mapping Except for a handful of special instructions see 16 bit Load and Store 20 bit Address on page 150 the Rabbit instructions directly address a 64K data memory space This means that the address fields in the instructions are 16 bits long and that the registers that may be used as pointers to memory addresses index registers ix iy program counter and stack pointer sp are also 16 bits long Because Rabbit instructions use 16 bit addresses the instructions are shorter and can exe cute much faster than for example 32 bit addresses The executable code is also very compact Even though these 16 bit addresses are a valuable asset they do create some complications because a memory mapping unit is needed in order to access a reasonable amount of memory for modern C programs 20 Rabbit 2000 Microprocessor The Rabbit memorv mapping unit is similar to but more powerful than th
46. readv received buffer emptv r busv Writing to the status register clears the transmit interrupt request FF but has no other ef fect Bit 7 receiver ready This bit is set when a byte is transferred from the receiver shift regis ter to the receiver data register The bit is cleared when the receiver data register is read The transition from to 1 sets the receiver interrupt request flip flop Bit 6 address bit or 9th 8th bit This bit is set if the character in the receiver data register has a 9th 8th bit This bit is cleared should be checked before reading data register since when the data register is read a new data value may be immedi ately loaded with a new address bit Bit 5 this bit is set if the receiver is overrun This happens if the shift register and the data register are full and a start bit is detected This bit is cleared when the receiver data register is read Bit 3 transmitter data buffer empty This bit is set when a bit is transferred from the transmitter data buffer to the transmitter shift register It is cleared when a byte is stored in the transmitter data buffer or a write operation is performed to the serial port status register This bit will request an interrupt on the transition from 0 to 1 if interrupts are enabled Bit 2 transmitter busy bit This bit is set if the transmitter shift register is busy send ing data It is set on the falling edge of the start bit which is also th
47. rene 167 A 1 1 Use of the Programming Port as a Diagnostic Setup 167 A 1 2 Alternate Programming Port 168 2 Suggested Rabbit Crystal 169 eae ea ee hui ee rt M E 171 Rabbit 2000 Microprocessor 1 Introduction Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in small and medium scale controllers The first product is the Rabbit 2000 microprocessor The Rabbit 2000 designers have had years of experience using Z80 Z180 and HD64180 microprocessors in small controllers The Rabbit shares a similar architecture and a high degree of compatibility with these microprocessors but it is a vast improvement The Rabbit has been designed in close cooperation with Z World Inc a long time manu facturer of low cost single board computers Z World s products are supported by an in novative C language development system Dynamic C Z World is providing the software development tools for the Rabbit The Rabbit is easy to use Hardware and software interfaces are as uncluttered and are as foolproof as possible The Rabbit has outstanding computation speed for a microproces sor with an 8 bit bus This is because the Z80 derived instruction set is very compact and the design of the memory interface allows maximum utilization of the memory bandwidth The Rabbit races thro
48. second by the periodic interrupt and may be read or written directly by the user s programs Since SEC TIMER is driven by the same oscillator as the real time clock there is no relative gain or loss of time between the two As part of the standard startup code SEC TIMER has bits 15 46 of the real time clock copied to it SEC TIMER holds the number of seconds since 12 AM of 1 January 1980 SEC TIMER can accomodate 136 years from 1980 or to the year 2116 Another long timer Ms TIMER counts milliseconds and can be used in a similar manner MS TIMER wraps around from max count to zero approximately every 6 weeks The software that uses the counters measures intervals correctly even if the counter used wraps arround unsigned long int read rtc void read bits 15 46 rtc void write rtc unsigned long int time write bits 15 46 note bits 0 14 and bit 47 are zeroed Two utility routines are provided that can be used to convert times between the traditional format 10 Jan 2000 17 34 12 and the seconds since 1 Jan 1980 format converts time structure to seconds unsigned long mktime struct tm timeptr seconds to structure unsigned int mktm struct tm timeptr unsigned long time The format of the structure used is the following struct tm char tm sec seconds 0 59 char tm min 0 59 char tm hour 0 59 char tm mday 1 31 char tm mon 1 12 char tm year 00 150 1900 2050 char tm wday 0 6 Oz sundav
49. segment of assembly language inserted in the C program For example compute value and write to port A data register value xty tasm ld a value value to write ioi ld PADR a write value to PADR endasm In the example above the ioi prefix changes a store to memory to a store to an internal I O port The prefix ioe is used for writes to external I O ports A series of C callable functions are available to read and write I O registers Internal I O Register Calls int RdPortI int PORT returns port high byte zero int BitRdPortI int PORT int bitcode bit code 0 7 writes 8 bits to port and shadow no shadow write if a null pointer is used for shadow void WrPortI int PORT char PORTShadow int value write to a port bit bits are numbered 7 6 1 0 void BitWrPortI int PORT char PORTShadow int value int bitcode Same external I O registers int RdPortE int adr returns contents of port high byte zero int BitRdPortE int PORT int bitcode bit code 0 7 int WrPortE int PORT char PORTShadow int value int BitWrPortE int PORT char PORTShadow int value int bitcode In order to read a port the following code could be used k RdPortI PDDR returns port D data register If the port is a write only port then the shadow register can be used to find out what the contents of the port are For example the global control status register has a number of User s Manual 139
50. serviced in 10 baud times or 86 us in order to not lose received characters If all four serial ports were operating at this receive speed it would be necessary to service the interrupt in less than 21 5 us to assure no lost characters In addition the time taken by other interrupts of equal or higher priority would have to be considered A receiver service routine might appear as follows below The byte at bu ptr is used to address the buffer where data bits are stored It is necessary to save and increment this byte because characters could be handled out of order if two re ceiver interrupts take place in quick secession receive push hl 10 save hl push de 10 save de ld hl struct 6 ld a hl 5 getin pointer 14 2 save in pointer in e inc hl 2 point to out pointer cmp a hi 5 see if in pointer out pointer buffer full jr z roverrun 5 go fix up receiver over run inc a 2 incement the in pointer and a mask 4 mask such as 11110000 if 16 buffer locs dec hl 2 ld hl a 6 update the in pointer ioe ld a SCDR 11 get data register port C clears interrupt request ipres 4 restore the interrupt priority 68 clocks to here to level before interrupt took place more interrupts could now take place but receiver data is in registers now handle the rest of the receiver interrupt routine ld hl bufbase 6 ld d 0 6 add hl de 2 location to store data ld hl a 6 put away the data byte pop
51. source of the interrupt is transmitter data register empty or trans mitter shift register idle not busy Unless the data register is empty on this edge the trans mitter does not become idle The transmitter become idle only if the data register is empty at the trailing edge of the stop bit 108 Rabbit 2000 Microprocessor Transmitter IRQ Transmitter Data Request Interrupt Buffer Emptv or Transmitter not Busv Write Transmitter Data Register or Write Status Register Receiver IRQ Receiver Data Buffer Full Read Receiver Data Register Figure 31 Generation of Serial Port Interrupts The serial port interrupt vectors are shown Table 15 in Chapter 7 12 3 Transmit Serial Data Timing On transmit if the interrupts are enabled an interrupt is requested when the transmit regis ter becomes emptv and in addition an interrupt occurs when the shift register and trans mit register both become emptv that is when the transmitter becomes idle When the transmit data register contains data and the shift register finishes sending data the data bits are clocked from the transmit register to the shift register and the shift register is never idle The interrupt request is cleared either bv writing to the data register or bv writing to the status register which does not affect the status register The data register normallv is clocked into the shift register each ti
52. strobe from master If serial port A is enabled in clocked mode then is the bidirectional clock line If serial port B is enabled in clocked mode then PBO is the bidirectional clock line 93 100 I O port C 7 4 In 4 Out I O Port C When used as a parallel port Bits 1 3 5 7 are inputs and bits 0 2 4 6 are outputs Bits 0 2 4 6 can alternately be selectivey enabled to serve as the serial data output for serial ports D C B A respectively Bits 1 3 5 7 serve as the serial data inputs for serial ports D C B A These inputs can also be read from the parallel port register when they are being used by the serial port UART 51 52 54 60 54 Rabbit 2000 Microprocessor Table 3 Rabbit Pin Assignments I O Port D PD0 PD7 Input Outp ut output open drain I O Port D Each bit may be individually selected to be an input or output Each out put may be selected to be high low drive or open drain Outputs are buffered by timer synchronizable registers for precision edge control PD6 can be programmed to be an optional serial output for serial port A PD4 can be programmed to be an optional serial output for serial port B PD7 and PD5 can be used as alternate serial inputs by serial ports A and B in which case these pins should be programmed as inputs 43 50 I O Port E 7 Input Outp ut I O Port E Each bit may be individually selec
53. the index reg isters and the regular registers is greately facilitated by new instructions In the Z180 the alternate register set is difficult to use while in the Rabbit it is well integrated with the regular register set Long calls long returns and long jumps facilitate the use of 1M of code space This removes the need in the Z180 to utilize inefficient memory banking schemes for larger programs that exceed 64K of code e Input output instructions are now accomplished by normal memory access instructions prefixed by an op code byte to indicate access to an I O space There are two I O spaces internal peripherals and external I O devices Some Z80 and Z180 instructions have been deleted and are not supported by the Rabbit see Section 19 Differences Rabbit vs Z80 Z180 Instructions on page 159 Most of the deleted instructions are obsolete or are little used instructions that can be emulated by several Rabbit instructions It was necessary to remove some instructions to free up l bvte op codes needed to implement new instructions efficiently The instructions were not re implemented as 2 byte op codes so as not to waste on chip resources on unimpor tant instructions Except for the instruction ex sp h1 the original 7180 binary encod ing of op codes is retained for all Z180 instructions that are retained 3 3 1 Instructions to Load Immediate Data To a Register A constant that follows the op code in the instruction stream can ge
54. the master by means of the two select lines and a write strobe User s Manual 15 Figure 3 shows the data paths in the slave port Rabbit B j gt Master Processor Input Register CPU Output Registers Control Slave Interface Registers Figure 3 Slave Port Data Paths The slave Rabbit can read the same registers as I O registers When incoming data bits are written into one of the registers status bits indicate which registers have been written and an optional interrupt can be programmed to take place when the write occurs When the slave writes to one of the registers carrving data bits outward an attention line is enabled so that the master can detect the data change and be interrupted if desired One line tells the master that the slave has read all the incoming data Another line tells the master that new outgoing data bits are available and have not yet been read by the master The slave port can be used to direct the master to perform tasks using a variety of communication protocols over the slave port 2 2 6 Timers The Rabbit has several timer systems The periodic interrupt is driven by the 32 768 kHz oscillator divided by 16 giving an interrupt every 488 us if enabled This is intended to be used as a general purpose clock interrupt Timer A consists of five 8 bit countdown and reload regi
55. the real time clock cannot be read in ultra slow mode because they count fast compared to the instruction execution time User s Manual 147 17 3 4 Flash Memorv Write Support A flash memorv write routine is provided This routine works differentiv or there are dif ferent routines for the cases when the memorv to be written is in the primarv code memorv or is in a separate special memorv Writes to the primarv code memorv require freezing the svstem for 10 ms or so Other writes just require that the user wait for the write to be done before doing the next write To protect the svstem identification block the program tests the absolute memorv address relative to the start of the flash memory connected to 50 WEO and OEO which is used to store the system identification block The program has to check the contents of the memory bank control registers to make this check A routine that can actually write this block is not included in the BIOS to make it hard to accidently write this block 148 Rabbit 2000 Microprocessor 18 Rabbit Instructions Summary Load Immediate Data on page 149 8 01 Indexed Load and Store on page 150 16 bit Indexed Loads and Stores on page 150 16 bit Load and Store 20 bit Address on page 150 Register to Register Moves on page 151 Exchange Instructions on page 151 Stack Manipulation Instructions on page 152 16 bit Arithmetic and Logical Operations on page 152 8 bit Arithmeti
56. the user at startup if there 18 a need to double the clock as shown in Table 8 Table 8 Global Clock Double Register GCDR adr Ofh Bit s Value Description 7 3 XXXXX These bits are ignored 2 0 000 The clock double circuit is disabled 001 8 ns nominal low time best for 30 MHz oscillator 010 10 ns nominal low time best for 25 MHz oscillator 011 12 ns nominal low time best for 20 MHz oscillator 100 14 ns nominal low time best for 18 MHz oscillator 101 16 ns nominal low time best for 16 MHz oscillator 110 18 ns nominal low time best for 14 MHz oscillator 111 20 ns nominal low time best for 12 MHz or slower oscillator When the clock doubler is used and there is no subsequent division of the clock the output clock will be asymmetric as shown in Figure 18 on page 70 The doubled clock low time is subject to wide 5096 variation since it depends on process parameters temperature and voltage The times given above are for a supply voltage of 4 V and a temperature of 25 These delay values decrease by about 15 when the voltage decreases by 5 V and increase about 25 when the voltage increases by 3 3 V The values increase or decrease by 146 for each 5 C increase or decrease in temperature The doubled clock is created by xor ing the delayed and inverted clock with itself If the original clock does not have a 50 50 duty cycle then alternate clocks will have a slightly differ
57. tion that two adjacent edges cannot be too close to each other since an interrupt must be serviced after each edge to set up the time for the next edge This restriction limits the minimum pulse width to about 5 us depending on the clock speed and interrupt priorities User s Manual 103 104 Rabbit 2000 Microprocessor 12 Rabbit Serial Ports The Rabbit has four on chip serial ports designated A B C and D the ports can per form asynchronous serial communications at high baud rates Ports A and B have the ad ditional capabilities of being able to operate as clocked ports and of being switchable to alternate I O pins Port A has the special capability of being usable to perform a cold boot of the microprocessor system Figure 29 shows a block diagram of the serial ports ACLK I 1 nput to timers A4 Serial A ge perclk 2 or pam Alternate I O perclk 2 BCLK prescaled Timer A5 SerialB gt 1 lt RX Alternate I O Timer A6 TX Serial C RX Timer 7 Serial IX RX Figure 29 Block Diagram of Rabbit Serial Ports The individual serial ports are capable of operating at baud rates in excess of 500 000 bps for asynchronous mode and 8 times faster than that for synchronous mode In asynchro nous mode either 7 or 8 data bits may be transmitted and recei
58. tionality attached to the act of writing the register An illustration of a write only register for which a shadow is unnecessary is the transmitter data register in the Rabbit serial port The transmitter data register is a write only register but there is little reason to have a shadow register since any data bits stored are transmitted promptly on the serial port 16 3 Timer and Clock Usage The real time clock or battery backable clock is a 48 bit counter that counts at 32768 counts per second The counting frequency comes from the 32 768 kHz oscillator which is separate from the main oscillator Two other important devices are also powered from the 32 768 kHz oscillator the periodic interrupt and the watchdog timer It is assumed that all measurements of time will derrive from this clock and not the main processor clock which operates at a much higher frequency e g 22 1184 MHz This allows the main processor oscillator to use less expensive ceramic resonators rather than quartz crystals Ceramic resontors typically have an error of 5 parts in 1000 while crystals are much more accurate to a few seconds per day It is not intended that the real time clock be read and written frequently The procedure to read it is lengthy and has an uncertain execution time The procedure for writing the clock is even more complicated Rather Dynamic C software maintains a long variable User s Manual 141 SEC TIMER in memory SEC TIMER is updated every
59. to physical memory chips MB2CR 16h xxxxxxxx Memory Bank 2 Control Register Controls mapping of third memory quadrant to physical memory chips MB3CR 17h xxxxxxxx Memory Bank 3 Control Register Controls mapping of fourth mem ory quadrant to physical memory chips SPDOR 20h Slave Port Register 0 Separate registers for read and write used for slave port communication SPDIR 21h Slave port register 1 User s Manual 63 Table 6 Rabbit Internal I O Registers Address Reset Value Functionalitv SPD2R 22h Slave port register 2 SPSR 023h 00000000 Slave port status register SPCR 24h 000x0000 Slave port control register PADR 30h Parallel port A data register R W PBDR 40h 00 Parallel port B data register R W PCDR 50h x0x0x0x0 Parallel port C data register PCFR 55h x0x0x0x0 function register PDDR 60h Parallel port D data register R W PDCR 64h 00 00 Port D control register PDFR 65h Port D function register PDDCR 66h D drive control register PDDDR 67h 00000000 PortD data direction register PDBOR 68h Port D bit 0 register W PDB1R 69h Bit 1 PDB2R 6Ah XXXXXXXX Bit 2 PDB3R 6Bh XXXXXXXX Bit 3 PDB4R 6Ch Bit 4 PDB5R
60. up to 1096 asymmetry 55 45 in the waveform generated by the oscillator This is because the clock doubler uses the intermediate edge to generate the double frequency A voltage between 3 V and 3 5 V should be used to minimize power consumption and the clock speed should be adjusted downward as far as feasible This will give the maximum computation per watt Table 43 Rabbit Basic Worst Case Timings Preliminary 6 24 99 3 3 V 10 5 0 V 10 2 50 V min 40 C 85 c 40 C 85 C 40 85 2 R 25 R 30 R 25 R 30 16 25 MHz 26 MHz Maximum clock speed 8 25 MHz 18 9 MHz 29 5 MHz Maximum clock speed generated 742 MHz 14 8 MHz 22 5 MHz using clock doubler 17 0 MHz 26 5 MHz Tadr clock to address out delav with 20 pf address line load Has on Minimum clock period 121 ns 61 5 ns 53 ns 39 ns 34 ns Tadr clock to address out delay with 20 pf address bus load one Tadr clock to address out delay with 70 pf address line load 398 eons iss Tsetup data setup prior to clock 12 ns 7 ns 4 ns The values in Table 43 may be improved by 6 for commercial ratings The industrial rating is the specified voltage plus or minus 1096 and a maximum temperature 85 The commercial rating is plus or minus 5 voltage and amaximum temperature of 70 The effect of temperature alone is approximately 1 worse speed for each 5 C temperature in crease User s Manual 133 The memory acces
61. 0 400 20 2752 49 3 0 88 6 82 6 57 600 18 432 542 0 96 5 91 5 115 200 124 Q 5 V 119 e 5 V 14 7456 67 8 0 119 9 33V 109 33 V 460 800 192 Q 5 V 187 5 V 14 7456 67 8 1 187 33 V 177 33 V 460 800 169 Q 5 V 164 Q 5 V 11 0592 90 5 0 164 3 3 V 154 3 3 V 115 200 259 5 V 254 5 V 7 3728 135 6 0 254 3 3 V 244 3 3 V 230 400 235 2 5 V 220 2 5 V 134 Rabbit 2000 Microprocessor The die suffers significant self heating at higher clock speeds The thermal impedance die to ambient with zero air flow is 44 C W At 5 V with 65 mA current consumption this would result in about 15 C of self heating and would reduce the maximum clock speed by approximately 390 This reduction is included in the tables above Figure 38 Figure 39 and Figure 40 illustrate the memory read and write cycles T1 T2 T3 0 8 V 1 dg AAT ICS gt lt Memory Read E Tadr D0 D7 lt SS s gsm s x 8 Tsetup 4 ns OE Tsetup 4 ns measured from 30 70 level NI JK 0 19 5 2 4 Er Tadr Memorv Write 3 state K DEM gt Tcl d 2 N IWE Figure 38 Memorv Read and Write Cvcles Tadr is the time required for the address output to reach 0 8 V This time depends on the bus loading 0 has a stronger driver and can handle larger capacitive loads than the other address lines Tsetup is the data setup ti
62. 01111110 7 POP IX 11011101 11100001 9 SS a POP IY 11111101 11100001 9 CD EE POP zz 11zz0001 7 r MEE PUSH IP 11101101 01110110 9 SSS PUSH IX 11011101 11100101 12 PUSH IY 11111101 11100101 12 PUSH zz 11220101 10 RES b HL 11001011 10 b 110 10 e s s RES b IX d 11011101 11001011 d 10 b 110 13 5 RES b IY d 11111101 11001011 d 10 b 110 13 diu Vemm RES b r 11001011 i10 b r 4 r _ RET 11001001 8 aS RET 11 f 000 8 2 RETI 11101101 01001101 12 RL 11001011 00010110 10 f b RL IX d 11011101 11001011 d 00010110 13 f b L RL IY d 11111101 11001011 d 00010110 13 f b L RL DE 11110011 2 fr L RL r 11001011 00010 r 4 fr L RLA 00010111 2 fr RLC HL 11001011 00000110 10 f b L RLC IX d 11011101 11001011 d 00000110 13 f b L RLC 11111101 11001011 d 00000110 13 f b L r RLC r 11001011 00000 r 4 fr L 164 Rabbit 2000 Microprocessor RLCA 00000111 2 fr RR HL 11001011 00011110 10 f b L RR IX d 11011101 11001011 d 00011110 13 f xL RR IY d 11111101 11001011 d 00011110 13 f bxxXL RR DE 11111011 2 fr L RR HL 11111100 2 fr L RR IX 11011101 11111100 4 f L RR IY 11111101 11111100 4 f L RR r 11001011 00011 r 4 fr L RRA 00011111 2 fr RRC HL 11001011 00001110 10 f b L RRC IX d 11011101 11001011 d 000011
63. 01h 00000000 Real Time Clock Control Register See Section 7 5 on page 71 RTCOR 02h Real Time Clock Byte 0 Register RTCIR 03h Real Time Clock Byte 1 Register RTC2R 04h Real Time Clock Byte 2 Register RTC3R 05h Real Time Clock Byte 3 Register RTC4R 06h Real Time Clock Byte 4 Register RTCSR 07h Real Time Clock Byte 5 Register WDTCR 08h 00000000 Watchdog Timer Control Register See Section 7 6 on page 73 WDTTR 09h 00000000 Watchdog Timer Test Register GOCR 0Eh 00000x00 Global Output Control Register See Section 7 4 on page 71 GCDR 0Fh 000 Global Clock Doubler Register MMIDR 10h 00000 Memorv Management I and D Space Register Controls 1 amp D space enable and batterv switchover support for 1 XPC 00000000 Not an I O register but initialized to zero bv reset STACKSEG 11h 00000000 Stack segment memory pointer Locates stack segment in physical Z180 CBR memory DATASEG 12h 00000000 Data segment memory pointer Locates data segment in physical mem Z180 BBR SEGSIZE 13h 11111231 Specifies start of data segment and start of stack segment in 64K mem Z180 CBAR OIV space MBOCR 14h 00000000 Memory Bank 0 Control Register Controls mapping of first memory quadrant 256K to physical memory chips MBICR 15h xxxxxxxx Memory Bank 1 Control Register Controls mapping of second mem ory quadrant
64. 1 d IX d L IX d 1 H r s L IX d H IX d 1 d IY d L IY d 1 H r s L H IY d 1 A ISZVC Operation L HL41 H Adr 19 16 A 3 0 150 Rabbit 2000 Microprocessor LDP IX HL LDP IY HL LDP HL HL LDP HL IX LDP HL IY LDP mn HL LDP mn IX LDP mn IY LDP HL mn LDP IX mn LDP IY mn 12 12 10 10 10 15 15 15 13 13 13 18 6 Register to Register Moves Instruction LD r g LD A EIR LD A IIR LD A XPC LD EIR A LD IIR A LD XPC A LD HL IX LD HL IY LD IX HL LD IY HL LD SP HL LD SP IX LD SP IY LD dd BC LD dd DE clk 2 oa a N P uS us ls gt gt us us sdb A A r fr fr r 18 7 Exchange Instructions Instruction EX SP HL EX SP IX EX 5 clk 15 15 15 A r I I SZV IX L IX 1 H Adr 19 16 A 3 0 IY L IY 1 H Adr 19 16 A 3 0 L HL H HL 1 Adr 19 16 A 3 0 L IX H IX 1 Adr 19 16 A 3 0 L IY H IY 1 Adr 19 16 A 3 0 mn L mn 1 H Adr 19 16 A 3 0 mn IXL mn 1 IXH Adr 19 16 A 3 0 mn IYL mn 1 IYH Adr 19 16 A 3 0 L mn H mn 1 Adr 19 16 A 3 0 IXL mn IXH mn 1 Adr 19 16 A 3 0 IYL mn mn 1 Adr 19 16 A 3 0 Operation r g r g any of B C D E H L A A EIR A
65. 1 Hardware Design of Slave Port Interconnection 120 13 2 Slave Port Registers uet en teen nea nep Ge Sash eme 121 13 3 Applications and Communications Protocols for Slaves sese 123 13 3 1 Slave Applications siii T enne nennen nennen eterne nnne enne 123 13 3 2 Master Slave Messaging Protocol semen nnennnnnnenenennenenznnennznza 123 14 Rabbit Hardware Design and Development 127 14 1 RS 485 Communication Interface essere nennen entree 127 14 2 RS 232 Communication Interface ness ener enne 127 14 3 Analog to Digital Converters eee ettet tpe SPES SA Ep sie 127 14 4 Digital to Analog Converters sese en nennen nennen 127 14 5 High Voltage DrfINer8 nette toe d iet 127 14 6 Clocks i pir empate e ipee 127 14 7 Low Power Design ihe en e er etd tee e ns 128 14 8 Basic Memory Design enr en rene en entren 129 14 8 1 Memory A ess Timeo eene leone oer erc OR 129 14 8 2 Precautions for Unprogrammed Flash Memory eee 129 14 9 PC Board Layout and Memory Line Permutation sese 131 15 Timing pe stet TUBI Ka 133 15 1 Current Consumption u eene nennen eret ne entren entren eene teneret 137 16 Rabbit Softwar un iss be Ki b i
66. 10 13 f b xL RRC IY d 11111101 11001011 d 00001110 13 f b L RRC r 11001011 00001 r 4 fr L RRCA 00001111 2 fr RST v 11 v 111 v 2 3 4 5 7 only 8 SBC IX d 11011101 10011110 d 9 fr 55 kx SBC IY d 11111101 10011110 d 9 fr s V 5 10011110 5 fr s SBC A n 11011110 4 fr V SBC A r 10011 r 2 fr V SBC HL ss 11101101 01550010 4 fr SCF 00110111 2 f 1 SET b 11001011 11 b 110 10 L SET b IX d 11011101 11001011 d 11 b 110 13 L SET b IX4d 11111101 11001011 d 11 b 110 13 L SET b r 11001011 il b r 4 r SLA HL 11001011 00100110 10 f b L SLA IX d 11011101 11001011 d 00100110 13 f L SLA IY d 11111101 11001011 d 00100110 13 f b L SLA r 11001011 00100 r 4 fr L SRA HL 11001011 00101110 10 f b L SRA IX d 11011101 11001011 d 00101110 13 f b L SRA IY d 11111101 11001011 d 00101110 13 f b L SRA r 11001011 00101 r 4 fr SRL HL 11001011 00111110 10 f b L r SRL IX d 11011101 11001011 d 00111110 13 f b SRL 4 11111101 11001011 d 00111110 13 f b SRL r 11001011 00111 r 4 fr SUB HL 10010110 5 fr s SUB IX d 11011101 10010110 d 9 fr s V SUB IY d 11111101 10010110 d 9 fr 55 kx SUB 11010110 4 fr x SUB r 10010 r 2 fr
67. 139 16 1 Reading and Writing I O Registers and Shadow Registers esses 139 16 2 Shadow Registers te ir pedet e pre re eerte teet ree ha 140 16 3 Tuner and Clock Us ge emo RR TREE Pig emen 141 16 4 WatchDog Support SoftW f _ eene 142 16 4 1 The Watchdog Hardware essere nennen nennen 143 16 4 2 Virtual Watchdog System esses nennen 143 User s Manual 17 Rabbit Standard BIOS n A A a a a 145 17 1 The BIOS More Details si iiie eei ne tk 145 17 2 BIOS Assumptions i ERSTER e E HE ESPERE RH 146 17 3 Periodic Interrupt and Real Time Clock BIOS Services semen 146 17 3 1 Real Time Clock Support a tree tte be reete 147 17 3 2 Watchdog Timer 147 17 3 3 Power Management Support a 147 17 3 4 Flash Memory Write Support sees enne ener 148 IS Rabbit Instructions u ma mb e t Dose fiti occ a Massi 149 18 1 Load Immediate Data Z irre tenerte reete tr eere eee Fen aene ere 149 18 2 Load and Store to an Immediate Address eee 150 18 3 8 bit Indexed Load and Store sia eee tee te er tren tt Eee tir e 150 18 4 16 bit Indexed Loads and Stores manner nennen nennen 150 18 5 16 bit Load and St
68. 2 IYL SP SP 2 SP 1 zzh SP 2 221 SP SP 2 zz BC DE HL AF 18 9 16 bit Arithmetic and Logical Operations Instruction ADC HL ss ADD HL ss ADD IX xx ADD IY yy ADD SP d clk A ISZ 4 fr fr Operation HL HL ss CF ss BC DE HL SP HL HL ss IX IX xx xx BC DE IY SP IY yy yy BC DE IX SP SP SP d d 0 to 255 152 Rabbit 2000 Microprocessor AND HL DE AND IX DE AND IV DE BOOL HL BOOL IX BOOL IY DEC IX DEC IY DEC ss INC INC INC IX IY ss MUL OR OR OR RL HL DE IX DE IY DE DE RR RR RR IX RR IY SBC HL ss DE HL N b ados as Nod BND A A NAAN oa BN fr fr fr fr fr fr fr ox Peee ox gGEHERHE X 0X HL HL amp DE IX IX amp DE IY IY amp DE if HL 0 HL 1 set flags to match HL if IX 0 IX 1 if IY 0 IY 1 IX IX 1 IY 1 ss ss 1 ss BC DE HL SP IX IX 1 IY IY 1 ss ss 1 ss BC DE HL SP HL BC BC DE signed 32 bit result DE unchanged HL HL DE bitwise or IX IX DE IY IY DE CY DE DE CY left shift with CF DE CY CY DE HL CY CY HL IX CY CY IX IY CY CY IY HL HL ss CY cout if ss CY hl 18 10 8 bit Arithmetic and Logi
69. 6Dh XXXXXXXX Bit 5 PDB6R 6Eh Bit 6 PDB7R 6Fh XXXXXXXX Bit 7 PEDR 70h Parallel port E data register R W PECR 74h xx00xx00 Port E control register PEFR 75h XXXXXXX Port E function register PEDDR 77h 0000000 Port E data direction register PEBOR 78h Port E bit 0 register PEBIR 79h Bit 1 PEB2R 7Ah Bit 2 PEB3R 7Bh Bit 3 PEB4R 7Ch Bit 4 PEBSR 7Dh Bit 5 PEB6R 7Eh Bit 6 64 Rabbit 2000 Microprocessor Table 6 Rabbit Internal I O Registers Address Reset Value Functionalitv PEB7R 7FH Bit 7 IBOCR 80h 00000xxx External I O control bank 0 IBICR 81h 00000xxx External I O control bank 1 IB2CR 82h 00000xxx External I O control bank 2 IB3CR 83h 00000xxx External I O control bank 3 IB4CR 84h 00000xxx External I O control bank 4 5 85 00000 External I O control bank 5 IB6CR 86h 00000xxx External I O control bank 6 IB7CR 87h 00000xxx External I O control bank 7 IOCR 98h xx000000 External interrupt O control register IICR 99h xx000000 External interrupt 1 control register TACSR 0A0h 0000xx00 Timer A Control Status Register TACR 0A2h Timer A Control Register TATIR 0A3h 0000 00 Timer A1 Time Constant 1 Register TAT4R 0A9h
70. 8 and A19 The other address lines of the 20 bit address are passed unconditionally The mem ory interface unit provides control signals for external memory chips These interface sig nals are chip selects CSO 51 CS2 output enables OEO OE1 and write enables WEO WE1 These signals correspond to the normal control lines found on static mem ory chips chip select or CS output enable or OE and write enable or WE In order to generate these memory control signals the 20 bit address space is divided into four quad rants of 256K each A bank control register for each quadrant determines which of the chip selects and which pair of output enables and write enables if any is enabled when a memory read or write to that quadrant takes place For example if a512K x 8 flash mem ory is to be accessed in the first 512K of the 20 bit address space then CSO WEO OEO could be enabled in both quadrants Figure 8 shows a memory interface unit Optional A16 inversion not presently supported by Dynamic C A16in A16 Address lines output Axxin from processor A19in Axx out from memory r 19 control unit A18i 7 A18 A19 invertable Address lines not shown m A18 by quadrant passed directly A19 subject to I amp D inversion A19in A19in L _ C80 memory p A18in CS1 seat ines 52 Optional 19 inversion memory OE0 control Read Write OE1
71. A B and D four serial ports can oper ate in an asvnchronous mode up to a baud rate of the svstem clock divided bv 32 The asynchronous ports can handle 7 or 8 data bits A 9th bit address scheme where an addi tional bit is sent to mark the first byte of a message is also supported The software can tell when the last byte of a message has finished transmitting from the output shift register correcting an important defect of the Z180 This is important for RS 485 communication because the line driver cannot have the direction of transmission reversed until the last bit has been sent In many UART s including those on the 7180 it is difficult to generate an interrupt after the last bit is sent Parity bits and multiple stop bits are not supported di rectly by the Rabbit but can be accomplished with appropriate driving software Serial ports A and B can be operated alternately in the clocked serial mode In this mode a clock line synchronously clocks the data in or out Either device of the 2 devices com municating can supply the clock When the Rabbit provides the clock the baud rate can be as fast as 1 8th of the system clock frequency or more than 3 000 000 bits per second Serial port A has special features It can be used to cold boot the system after reset Serial port A is the normal port that is used for software development under Dynamic C 2 2 2 System Clock The main oscillator uses an external crystal with a frequen
72. Bit 15 3 4 5 Atomic Moves from Memory to 1 Space To avoid disabling interrupts while copying a shadow register to its target register it is de sirable to have an atomic move from memorv to I O space This can be done using LDD or LDI instructions ld hl sh PDDDR point to shadow register ld de PDDDR set de to point to I O reg set 5 hl set bit 5 of shadow register use ldd instruction for atomic transfer ioi ldd de hl hil de When the LDD instruction is prefixed with an I O prefix the destination becomes the I O address specifed by DE The decrementing of HL and DE is a side effect If the repeating instructions LDIR and LDDR are used interrupts can take place between successive itera tions Word stores to I O space can be used to set two I O registers at adjacent addresses with a single noninterruptable instruction User s Manual 37 3 5 Interrupt Structure When an interrupt occurs on the Rabbit the return address is pushed on the stack and con trol is transferred to the address of the interrupt service routine The address of the inter rupt service routine has two parts the upper byte of the address comes from a special register and the lower byte is fixed by hardware for each interrupt There are separate reg isters for internal interrupts IIR and external interrupts EIR to specify the high byte of the interrupt service routine address These registers are accessed by special instructions
73. DE 11011101 11011100 4 f L O AND IY DE 11111101 11011100 4 f L O AND n 11100110 4 fr L O AND r 10100 r 2 fr L O BIT b HL 11001011 01 b 110 7 IDs es BIT b IX d 11011101 11001011 d 01 b 110 10 f sS b IY d 11111101 11001011 d 01 b 110 10 f s BIT b r 11001011 01 b r 4 f BOOL HL 11001100 2 fr 00 BOOL IX 11011101 11001100 4 f 00 BOOL IY 11111101 11001100 4 f 00 CALL mn 11001101 n m 12 Si gt CCF 00111111 2 f 10111110 5 f User s Manual 161 IX d 11011101 10111110 d 9 f 5 IY d 11111101 10111110 d 9 f 5 CP n 11111110 n 4 f V CP r 10111 r 2 f CPL 00101111 2 r DEC 00110101 8 f b wvy DEC IX d 11011101 00110101 d 12 f b Vv DEC 11111101 00110101 d 12 f b Vv DEC IX 11011101 00101011 4 _ DEC IY 11111101 00101011 4 _ DEC r 00 r 101 2 fr DEC ss 00551011 2 ss 00 BC O1 DE 10 HL 11 5 DJNZ j 00010000 j 2 5 r EX SP HL 11101101 01010100 15 r EX SP IX 11011101 11100011 15 SP IX 11111101 11100011 15 AF AF 00001000 2 EX DE HL 11101011 2 s EX DE HL 11100011 2 s EX DE HL 01110110 11100011 4 s EX DE HL 01110110 11100011 4 s 11011001 2
74. G IX Index registers alt accum s B SP stack pointer Alternate Registers PC program counter XPC extension of program counter SIZIxIixixIiVIxIiC IIR internal interrupt register EIR external interrupt register F fl ister 1 t CON e IP interrupt priority register S sign Z zero V overflow C carry Bits marked x are read write Figure 5 Rabbit Registers The Rabbit and the Z80 Z180 processor has two accumulators the A register serves as an 8 bit accumulator for 8 bit operations such as add or and The 16 bit register HL regis ter serves as an accumulator for 16 bit operations such as add hl de which adds the 16 bit register DE to the 16 bit accumulator HL For many operations IX or IY can substitute for hl as accumulators The register marked F is the flags register or status register and it holds a number of flags that provide information about the last operation performed The flag register cannot be accessed directly except by using the pop af and push af instructions Normally the flags are tested by conditional jump instructions The flags are set to mark the results of arith metic and logic operations according to rules that are specified for each instruction There are four unused read write bits in the flag register that are available to the user via the push User s Manual 19 af and pop af instructions These bits should be used with caution since new generation Rabbit pro
75. IOE add 2 clocks plus the number of I O wait states enabled The V flag is set when BC transitions from 1 to O If the V flag is not set another step is performed for the repeating versions of the instructions Interrupts can occurr between different repeats but not within an iter ation equivalent to LDD or LDI Return from the interrupt is to the first byte of the instruction which is the I O prefix byte if there is one Control Instructions Jumps and Calls Instruction clk A ISZVC Operation CALL mn 12 Ta SP 1 PCH SP 2 PCI PC mn SP SP 2 DJNZ j 5 r B 1 if B 0 PC PC j JP HL 4 PC HL JP IX 6 PC IX JP IY 6 PC JP f mn 7 if f PC mn JP mn 7 PC mn 156 Rabbit 2000 Microprocessor I JR JR e 5 _ LCALL xpc mn 19 LJP xpc mn 10 LRET 13 RET 8 RET 8 2 RETI 12 RST 8 18 1S Miscellaneous Instructions Instruction clk A IS CCF f IP O IP 1 IP 2 IP 3 IPRES LD A EIR LD A IIR LD A XPC LD EIR A LD IIR A LD XPC A NOP POP IP PUSH IP SCF ZINTACK fr fr R N O r K dd gd H I 18 19 Privileged Instructions if cc PC PC e PC PC e if e 0 next seq inst is executed SP 1 XPC SP 2 PCH SP 3 PCL PC mn PCL SP PCH SP41 XPC SP 2 SP SP 3 PCL SP PCH SP41 SP SP 2 if f PCL SP PCH SP 1
76. In addition bits in the control register are zeroed bits 0 1 4 5 to ensure that data 1s clocked into the output registers when loaded other registers associated with port D are not initialized on re set The following registers are described in Table 25 and in Table 26 e PDDR Parallel port D data register Read Write e PDDDR Parallel port D data direction register 1 makes the corresponding pin an output Write only PDDCR Parallel port D drive control register 1 makes the corresponding pin an open drain output if that pin is set up for output This register is zeroed by reset Write only PCFR Parallel port D function control register This port may be used to make port positions 4 and 6 be serial port outputs Write only PDBxR These eight registers may be used to set outputs on individual port positions e PDCR Parallel port D control register This register is used to control the clocking of the upper and lower nibble of the final output register of the port On reset bits 0 1 4 and 5 are reset to zero User s Manual 89 I O Data Figure 24 Parallel Port D Block Diagram ARXA gt PD7 lt pp gt ARXB gt P pps lt pp4 ATXB f inputs perclk 22 1 Driver opt
77. L 850 2 O 799 A19 VDDCI 78 VDD ICS2L 4 Ti VSS 1 810 5 160 OE1 6 150 All 1007 740 A9 CSOL 8 730 8 D70 9 720 A13 D6C 10 715 14 DSL 11 700 A17 D40 12 690 WEO D30 13 680 A18 D20 14 670 A16 DIO 15 66 1 A15 DOLI 16 650 A12 AOL 17 640 A7 AIL 18 63 A6 2 19 620 AS 20 610 A4 8 8 17 PEJOI 21 60L PCO TXD 16 6 22 S9 PCI RXD INTIB I5 50 23 58 PC2 TXC INTOB I4 24 57 PC3 RXC I3 25 5611 PC4 TXB D 20 26 55 PCS 850 27 SA PC6 TXA 28 530 VDD INTIA I1 PE1L 29 520 VSS INTOA 10 PEOC 30 510 PC7 RXA s nansutaoecgoicosuv98 BE x cg dr a ka STBREZSB EE RAR EU ZEZE lt lt lt lt Figure 13 Package Outline and Pin Assignments User s Manual 5 2 Package Mechanical Dimensions Figure 14 shows the mechanical dimensions of the Rabbit PQFP package 17 9 mm ka 23 9 mm gt E 50 e J Ph 2 10 725 0 65 mm p 0 30 mm i 4 14 625 i Cp 100 e i 30 40 80 mm 100 pin PQFP Physical Dimensions Top View Holes are optional to aid in attaching substitute connector for processor Figure 14 Mechanical Dimensions Rabbit PQFP P
78. Rabbit 20001M Microprocessor User s Manual Revision A Rabbit 2000 Microprocessor User s Manual Part Number 019 0069 Revision A Last revised on November 16 1999 Printed in U S A Copyright 1999 Rabbit Semiconductor All rights reserved Rabbit Semiconductor reserves the right to make changes and improvements to its prod ucts without providing notice Trademarks Dynamic is a registered trademark of Z World e 780 Z180 is a trademark of Zilog Inc Notice to Users Rabbit Semiconductor products are not authorized for use as critical components in life support devices or systems unless a specific written agreement regarding such intended use is entered into between the customer and Rabbit Semiconductor prior to use Life support devices or systems are devices or systems intended for surgical impantation into the body or to sustain life and whose failure to perform when properly used in accor dance with instructions for use provided in the labeling and user s manual can be reason ably expected to result in significant injury No complex software or hardware system is perfect Bugs are always present in a system of any size In order to prevent danger to life or property it is there responsibility of the system designer to incorporate redundant protective mechanisms appropriate to the risk involved Company Address Rabbit Semiconductor 2932 Spafford Street Davis California 95616 6800 USA Tele
79. Rotates RL RLA C RLC RLCA C lt a q RR L gt C RRC RRCA L gt C Instruction clk A IS RL HL 10 f b RL IX d 13 f b RL 13 f b RL r 4 fr RLC HL 10 f b RLC 13 f b RLC IY d 13 f b RLC r 4 fr RR HL 10 f b RR IX d 13 f b RR 13 f b RR r 4 fr RRC HL 10 f b IX d 13 f b IY d 13 f b RRC r 4 fr SLA HL 10 f b SLA IX d 13 f b SLA 13 f b SLA r 4 fr SRA HL 10 f b N lt Q ox PRPrPrPee xXx SLA H H H SRA SRL ox CY A A CY A A 6 0 A 7 CY A 7 A CY CY A A 0 A 7 1 CY A 0 C lt 0 gt C 0 w C Operation CY HL HL CY CY IX d IX d CY CY IY d IY d CY CY r r CY HL HL 6 0 71 CY HL 7 IXtd IX d 6 0 IXHd 71 CY IX d 7 IY d 6 0 I d 7 CY I d 7 r 6 0 r 7 CY r 7 HL CY CY HL IX d CY CY IX d IY d CY CY IY d r CY CY r HL HL 0 HL 7 11 HL 0 1 IX d 0 IX d 7 1 CY IX d 0 IY d 1 I d 0
80. SMODE pins x 00 disable slave port 00 no slave pins smodel smode0 port A is a bvte wide interrupt 1 ignore SMODE input port pp enable slave pins 01 disable slave port port interrupt port A is a byte wide priority l 3 output port x enable the slave port User s Manual 121 The functionalitv of the bits is as follows Bit 7 If set to 0 the cold boot feature will be enabled Normally this bit is set to a after the cold boot is complete The cold boot for the slave port is enabled au tomatically if SMODEI SMODEO lines are set to 0 1 after the reset ends This features disables the normal operation of the processor and causes commands to be accepted via the slave port register SPDOR These commands cause data to be stored in memory or I O space When the master that is managing the cold boot has finished setting up memory and I O space SMODE1 SMODE O pins are changed to code 0 0 which causes execution to start at address zero Typically this will start execution of a secondary boot program At some point bit 7 will be set to a 1 so that the SMODEX pins can be used as normal input pins Bits 6 5 May be used to read the input pins SMODE SMODEO Bits 3 2 Bit 3 if set to a 1 enables the slave port disabling parallel port A and vari via the slave port If bit 3 is 0 then bit 2 controls whether parallel port A is input bit 220 or output bit 2 1 Bits 1 0 This 2 bi
81. Table 40 Slave Port Registers Register Mnemonic Internal External Address Address SPDOR 20h 0 Slave Port Data x Register SPDIR 21h 1 SPD2R 22h 2 Slave Port Status Register SPSR 23h 3 Slave Port Control Register SPCR 24h N A If the user for some reason wants to depart from the suggested protocols and poll a register while waiting for the other side to write something to the register the user should be aware that all the bits might not change at the exact same time when the result changes and a transitional value could be read from the register where some bits have changed to the new value and others have not To avoid being confused by a transitional value the user can read the register twice and make sure both values are the same before accepting the value or the user can test only one bit for a change The transitional value can only exist for one read of the register and each bit will have its old value change to the new value at some point without wavering back and forth The existence of a transitional value could be very rare and has the potential to create a bug that happens often enough to be serious but so in frequently as to be difficult to diagnose Thus the user is cautioned to avoid this situation Table 41 describes the slave port control register Table 41 Slave Port Control Register SPCR adr 024h Bit 7 w o Bits 6 5 R O Bit4 Bit 3 2 w o Bits 1 0 w o 0 obev SMODE Reads
82. Value Description 7 0 Cancel byte increment mode disarm reset except code 80h Arm RTC for a reset with code 80h or reset and byte increment 40h mode with code OcOh 80h Resets all six byte counters if proceeded by arm command 40h OcOh Reset all six byte counters and enters byte increment mode precede this command with 40h arm command Increment clock s register corresponding to bit s set to 1 010 Example 01001101 increments registers 0 2 3 The bvte increment mode must be enabled Storing 00h cancels the byte increment mode 6 0 Disable the bvte increment function bv anv store with bit 6 set to zero Use code 00h 7 6 Watchdog Timer The watchdog timer is a 17 bit counter In normal operation it is driven by the 32 kHz clock When the watchdog timer reaches any of several values corresponding to a delay of from 0 25 to 2 seconds it times out When it times out it emits a l clock pulse from the watchdog output pin and it resets the processor via an internal circuit To prevent this timeout the program must hit the watchdog timer before it times out The hit is accom plished by storing a code in WDTCR Table 13 Watchdog Timer Control Register WDTCR adr z 08h Bit s Value Description 7 0 5Ah Restart hit the watchdog timer with a 2 second timeout period 57h Restart hit the watchdog timer with a 1 second timeout period 59h Restart hit the watchdog t
83. a read of this register 10 This bit combination is not possible 11 Reset occurred These bits are cleared bv a read of this register S ile 0 Read this register to clear periodic interrupt request This bit always read as zero 1 Force a periodic interrupt Processor clock from the main oscillator divided by eight 4 2 write only 000 E a Peripheral clock from the main oscillator divided eight 001 Processor clock from the main oscillator divided bv eight Peripheral clock from the main oscillator without divider 01 Processor clock from the main oscillator without divider x Peripheral clock from the main oscillator without divider 1 0 Processor clock from the 32 kHz oscillator without divider Peripheral clock from the 32KHz oscillator without divider Processor clock from the 32 kHz oscillator without divider 1 1 Peripheral clock from the 32 kHz oscillator without divider The main oscillator is turned off 1 0 write only 00 Periodic interrupts are disabled 01 Periodic interrupts use Interrupt Priority 1 10 Periodic interrupts use Interrupt Priority 2 11 Periodic interrupts use Interrupt Prioritv 3 68 Rabbit 2000 Microprocessor 7 2 Clock Doubler The clock doubler is provided to allow a lower frequencv crvstal to be used for the main oscillator and to provide an added range of clock frequencv adjustabilitv The clock dou bler uses an on chip delav circuit that must be programmed
84. abbit 2000 Microprocessor 5 6 Register and Interrupt Vector Summarv Table 5 Register and Interrupt Vector Summarv On chip peripheral I O address range ISR starting address Svstem Management 0000 0 RROO Memory Management 0001 1x No interrupts Slave Port 0010xxxx 2x RR80 Parallel Port A 0011 3x No interrupts Parallel Port B 0100xxxx 4x No interrupts Parallel Port C 0101xxxx 5x No interrupts Parallel Port D 0110 6x No interrupts Parallel Port E 0111 7x No interrupts External I O Control 1000 8x No interrupts External Interrupts 1001xxxx 9x Timer A 1010xxxx Ax RRAO Timer B 1011xxxx Bx RRBO Serial Port A 1100xxxx Cx RRCO Serial Port B 1101xxxx Dx RRDO Serial Port C 1110xxxx Ex RREO Serial Port D 1111 Fx RRFO RST 10 instruction n a RR20 RST 18 instruction n a RR30 RST 20 instruction n a RR40 RST 28 instruction n a RR50 RST 38 instruction n a RR70 User s Manual 62 Rabbit 2000 Microprocessor 6 Rabbit Internal I O Registers Table 6 Rabbit Internal I O Registers Address Reset Value Functionalitv GCSR 00h 11000000 Global Control Status Register Control of clocks periodic interrupts and monitoring of watchdog See Table 7 on page 68 RTCCR
85. abbit microprocessor and a RAM memory con nected to it The clock can be provided either by connecting a crystal or crystals to the slave or by providing an external clock which could be the master s clock The reset line of the slave would normally be driven by the master At system startup time the master re sets the slave and cold boots it via the slave port The SMODE pins must be configured for this Once the software is loaded into the slave the slave can begin to perform its function As a simple example suppose that the slave is to be used as a four port UART It has the capability to send or receive characters on any of its four serial ports Leaving aside the question of setup for paramters such as thebaud rate we could define a protocol as fol lows SPDOR readable by master is a status register with bits indicating which of the four receivers and four transmitters is ready that is has a character received or is ready to send a character SPDOR writable by the master is a control register used to send commands to the slave SPDIR is used to send or receive data characters or control bytes The line SDATAVL is wired to the external interrupt request of the master so that the master is interrupted when the slave writes to SPDOR Typically the slave will write to SPDOR when there is a change of status on one of the serial ports The line SDATRDY is wired to a port input line on the master so that the master can tell if the sl
86. ace both catcher devices associated with that interrupt are au tomatically reset If both edges are detected before the corresponding interrupt takes place because the triggering edges occur nearly simultaneously or because the interrupts are inhibited by the processor priority then there will be only one interrupt for the two edges detected The interrupt service routine can read the interrupt pins via parallel port E and determine which lines experienced a transition provided that the transitions are not too fast Interrupts can also be generated by setting up the matching port E bit as an output and toggling the bit Table 17 Control Registers for External Interrupts Reg Name Reg Address Bits 7 6 Bits 5 4 Bits 3 2 Bits 1 0 IOCR 10011000 XX INTO 4 INTO PEO Enb INTO 10011001 XX INTI PES INTI PEI Enb INTI edge triggered triggered interrupt 00 disabled 00 disabled 00 disable 10 rising 10 rising 01 pri 1 01 falling 01 falling 10 pri 2 11 both 11 both 11 pri 3 Interrupt vectors INTO EIR 00h INTI EIR O8h When it is desired to expand the number of interrupts for additional peripheral devices the user should use the interrupt routine to dispatch interrupts to other virtual interrupt rou tines Each additional interrupting device will have to signal the processor that it is re questing an interrupt A separate signal line is needed for each device so that the processor can determ
87. ackage 50 Rabbit 2000 Microprocessor Figure 15 shows the PC board footprint for the Rabbit 100 pin PQFP 1 99 mm 4 _ pin 100 x 1 75 mm pin 1 pin 30 31 16 33 mm 80 50 1 93 mm 0 36 mm 11065 mm 22 35 mm pin 51 Y Figure 15 PC Board Footprint for Rabbit 100 pin PQFP User s Manual 51 5 3 Rabbit Pin Descriptions Table 3 lists all the pins on the device along with their direction function and pin number on the package Table 3 Rabbit Pin Assignments Pin Group Pin Name Direction Function Pin Numbers Hardware CLK Output Processor clock output This signal is derrived from the main svstem oscillator and be divided 8 or doubled or both bv internal programmable circuitrv This signal is enabled after reset Under program control this pin can output the full internal clock frequency or 1 2 the internal frequencv or it can be used as a general purpose output pin under software control See Table 9 Global Output Control Register GOCR OEh on page 71 JRESET Input Master reset 37 XTALAI Input Quartz crystal for 32 KHz clock oscillator Lines to the crystal should be short and shielded from crosstalk If an ext
88. al port unit must be 16 times the baud rate in asynchronous mode and 2 times the baud rate for the clocked serial mode when the internal clock is used Timers A4 A7 supply the input clock for serial ports A F These timers can divide the frequency by any number from 1 to 256 see Chapter 11 The input frequency to the timers can be selected in different ways described in the documentation for the timers One choice is the peripheral clock divided by 2 with that choice and a well chosen crys tal frequency for the main oscillator most commonly used baud rates can be obtained down to approximately 2400 bps at the highest Rabbit clock frequencies see Section A 2 in Appendix A Table 37 lists the serial port registers 106 Rabbit 2000 Microprocessor Table 37 Serial Port Registers Address 00 01 10 11 Jon Register for A B C D Mnemonic x A B C D Data Register 11xx0000 SxDR Alternate Data Register to Send 9th 8th Address Bit s Status Register read write to clear transmit IRQ 120011 S SR Control Register write only 11 0100 5 The serial port interrupt vectors are shown Table 15 in Chapter 7 Table 38 describes the serial port status registers Table 38 Serial Port Status Registers 11 0011 xx A B C D Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 Receiver 9 8th bit Transmitter data Transmitte Overrun 0 0
89. and 40 us for a square root In comparison a 386EX processor running with an 8 bit bus at 25 MHz and using Borland C is about 10 times slower e There is a built in watchdog timer The standard 10 pin programming port eliminates the need for in circuit emulators A very simple 10 pin connector can be used to download and debug software using Z World s Dynamic C and a simple connection to a PC serial port The incremental cost of the programming port is extremely small User s Manual 9 Figure 1 shows a block diagram of the Rabbit IRESET NOWR NORD IBUFEN SMODEO SMODE1 STATUS IWDTOUT CLK Memory i 1 80 ICS1 ICS2 K II Management 4 Memory 1 Control WE1 Parallel 2 1 PortA 0 7 XTALBI Main m Parallel 7 XTALB2 Oscillator Port B 4 Parallel T Port C PCO PC7 Parallel PortD 7 Parallel PE0 PE7 Port E Serial Port A Svnch ARXA Serial Serial RXA CLKA Asvnch Svnch Bootstrap Bootstrap Serial Port B Asynchronous TXB RXB CLKB Synchronous Serial Port C Asynchronous Seria Serial Port D Asynchronous TXD RXD Serial 800 507 INTOA INT1A Slave Port 0 5 1 INTOB INT1B 185 ISRD SWR ISLAVEATTN ADDRESS BUS 2 DATA BUS 8 bits TXC RXC 16 bits Figure 1 Block Diagram of the Rabbit Microprocessor 10 Rabbit 2000 Microprocessor 1 2 Summa
90. and pop IP from using the regular stack A new prior ity can be pushed into the IP register with special instructions IP 0 IP 1 IP 2 IP 3 Table 2 Effect of Processor Priorities on Interrupts Processor pun Effect on interrupts Priority 0 interrupts priority 1 2 and 3 take place after execution of current non privileged instruction 1 Only interrupts of priority 2 and 3 take place 2 Only interrupts of priority 3 take place 3 All interrupt are suppressed except RST instruction User s Manual 39 3 5 2 Multiple External Interrupting Devices The Rabbit has two distinct external interrupt request lines If there are more than two ex ternal causes of interrupts then these lines must be shared between multiple devices The interrupt line is edge sensitive meaning that it requests an interrupt only when a rising or falling edge whichever is specified in the setup registers takes place The state of the in terrupt line s can always be read by reading parallel port E since they share pins with par allel port E If several lines are to share interrupts with the same port the individual interrupt requests would normally be or ed together so that any device can cause an interrupt If several de vices are requesting an interrupt at the same time only one interrupt results because there will be only one transition of the interrupt request line To resolve the situation and make sure that the
91. aneously then the precision will be reduced but this reduction can be minimized by careful programming 4 1 1 Pulse Width Modulation to Reduce Relay Power Typically relays need far less current to hold them closed than is needed to initially close them For example if the driver is switched to a 7596 duty cycle using pulse width modu lation after the initial period when the relay armature is picked the holding current will be approximately 75 of the full duty cycle current and the power consumption will be about 5690 as great The pulse width modulation rate may be from 5 kHz to 20 kHz If a periodic interrupt is established that interrupts every 50 us then a 5096 duty cycle could be set up for a 100 us period A 2596 5096 or 7596 duty cycle could operate on a 200 us period A 250 us pe 44 Rabbit 2000 Microprocessor riod would allow duty cycles of 20 40 60 80 The code for such an interrupt routine might appear as follows push af 10 push hl push de ld hl ptr 11 get pointer to location in array ld a maskand 9 get mask and a hi 5 get current output 1 2 maskor 9 2 ioi ld port a 13 store in port inc hl 2 point to next 14 a h1 5 check for end of array 2 jr nz step2 2 ld hi beginptr 11 reset hl to start of array step2 ld ptr hl 13 save hl pop de 7 pop hl pop af reti 7 return from interrupt 153 clocks
92. ansmit 9th bit SCSR 0E2h Oxx00000 Serial port C status register SCCR 0E3h xx00x000 Serial port C control register SDDR 0F0h Serial port D data register receive send SDAR 0FIh Serial port D alternate data register transmit 9th bit SDSR 0F2h 0 00000 Serial port D status register SDCR 0F3h xx00x000 Serial port D control register 66 Rabbit 2000 Microprocessor 7 Miscellaneous 1 Functions 7 1 Rabbit Oscillators and Clocks There are two crystal oscillators built into the Rabbit The main oscillator accepts crystals up to a frequency of 29 4912 MHz first overtone crystals only The clock oscillator re quires a 32 768 kHz crystal and can be battery backed An external oscillator or clock can be substituted for either crystal by connecting the ex ternal clock to XTALA1 or XTALBI and leaving the other crystal XTALA2 or XTALB2 unconnected If an external oscillator is used for the main clock the output pin CLK pin 1 should be used if the clock is needed externally This signal is synchronized with the internal clock In comparision the internal clock is delayed by approximately 10 nanoseconds compared to the external oscillator input XTALBI The main oscillator is normally used to derive the clock for the processor and peripherals The 32 768 kHz oscillator is normally used to clock the watchdog timer the battery back able time date clock and the periodic interru
93. ap ping of the root segment and the data segment by inverting certain bits when these seg ments are accessed Currently this functionality has no planned usage The optional enable of CS1 is valuable for systems that are pushing the access time of battery backed RAM By enabling CSI the delay time of the switch that forces CS1 high when power is off can be bypassed This feature increases power consumption since the RAM is always enabled and its access is controlled normally by OEI Table 21 MMU Instruction Data Register MMIDR 010h Bits 7 6 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 force CS1 invert A19 for invert A16 for 1 invert A19 for invert A16 always accesses in data accesses in accesses in root for accesses 000 enabled segment before data segment segment before in root seg quadrant selec quadrant selec ment tion tion 8 4 Allocation of Extended Code and Data The Dynamic C compiler compiles code to root code space or to extended code space Root code starts in low memory and compiles upward Y Variables Stacks Available RAM xcode 56 window 512 52K Stack Variables g Extended code Root i code L Root code and consta Mm A 0K Figure 22 Typical Memory Mapping and Memory Usage 84 Rabbit 2000 Microprocessor Allocation of extended code starts above the root code a
94. as a parallel port output bit that is cleared by the reset This may be interpreted as a break signal by some serial communication de vices TXA can be forced high by sending the triplet 80h 50h 40h which stores 40h in parallel port C An alternate approach is to send the triplet 80h 55h 40h which will en able the TXA output from bit 6 of parallel port C by writing to the parallel port C function register 55h The transfer rate in any bootstrap operation must not be too fast for the processor to exe cute the instruction stream The Write Empty signal acts as an interlock when using the Slave Port for bootstrap operation because the next byte should not be written to the Slave Port until the Write Empty signal is active No such interlock exists for the clocked serial and asynchronous bootstrap operation In these cases remember that the processor clock starts out in divide by eight mode with four wait states and limit the transfer rate accord ingly In asynchronous mode at 2400 bps it takes about 4 ms to send each character so no problem is likely unless the system clock is extremely slow 80 Rabbit 2000 Microprocessor 8 Rabbit Memorv Mapping and Interface See Section 3 2 on page 20 for a tutorial discussion of the Rabbit memorv mapping Figure 20 shows an overview of the Rabbit memorv mapping The task of the memorv mapping unit is to accept 16 bit addresses and translate them to 20 bit addresses The memorv interface unit accep
95. ave has accepted the command written to SPDOR 124 Rabbit 2000 Microprocessor The slave can interrupt the master at any time by storing to SPDOR It will do this every time an enabled transmitter is ready to accept a character or every time an enabled receiver receives a character When it stores to SPDOR it will store a code indicating the reason for the interrupt that is receive or transmit and channel number If the cause is receive the received character will also be placed in SPDIR writable by the slave When the mas ter is interrupted for any reason the master will sneak a peek at SPDOR by reading SPSR If the interrupt is caused by a receive character it will remove the character from SPDIR and read SPDOR to handshake with the slave If the master is interrupted for transmitter ready as determined by the sneak peek it will place the outgoing character in SPDIR and write a code to SPDOR indicating transmit and channel number This will cause the slave to be interrupted and the slave will take the character and handshake by reading SPDOR This handshake does not interrupt the mas ter User s Manual 125 126 Rabbit 2000 Microprocessor 14 Rabbit Hardware Design and Development Core designs and printed circuit board lavouts are available on the Rabbit web site A core design includes memory the microprocessor oscillator crystals the Rabbit standard programming port and in some cases a power controller and power suppl
96. ave processor the master processor can cold boot it over via the slave port This means the slave can operate without any nonvolatile memory Only RAM is required 4 4 The Slave Port The slave port allows a Rabbit to act as a slave to another processor which can also be a Rabbit The slave has to have only a processor chip a RAM chip and clock and reset sig nals that can be supplied by the master The master can cold boot and download a pro gram to the slave The master does not have to be a Rabbit processor but can be any type of processor capable of reading and writing standard registers For a detailed description See Slave Port on page 117 The slave processor s slave port is connected to the master processor s data bus Commu nication between the master and the slave takes place via three registers implemented in the Rabbit for each direction of communication for a total of six data registers In addi tion there is a slave port status register that can be read by either the master or the slave see Figure 33 on page 117 Two slave address lines are used by the master to select the register to be read or written The registers that carry data from the master to the slave ap pear as write registers to the master and as read registers to the slave The registers that operate in the opposite direction appear as read registers to the master and as write regis ters to the slave These registers appear as read write regi
97. be performed without testing for the carry The three register values can be saved and the carry test can be performed by a lower priority analysis routine Since the upper 2 bits are in the register TBCMR at ad dress OBEh and the lower 8 bits are in TBCLR at address OBFh both registers can be read with a single 16 bit I O instruction The following sequence illustrates how the registers could be captured enter from external interrupt on pulse input transition 19 clocks latency plus 10 clocks interrupt execution push af 7 push hl ioi 14 a TBCLR 11 get lower 8 bits of counter ioi ld hl TBCMR 13 get l upper h lower Timer B can be used for various purposes The 10 bit counter can be read to record the time at which an event takes place If the event creates an interrupt the timer can be read in the interrupt routine The known time of execution of the interrupt routine can be sub tracted The variable interrupt latency is then the uncertainty in the event time This can be as little 19 clocks if the interrupt is the highest priority interrupt If the system clock is 20 MHZ the counter can count as fast as 10 MHz The uncertainty in a pulse width mea surement can be nearly as low as 38 clocks 2 x 19 or about 2 us for a 20 MHz system clock Timer B can be used to change a parallel port output register at a particular specified time in the future A pulse train with edges at arbitrary times can be generated with the restric
98. bytes which are counted once every 256 clocks or every 1 128th of a second If the read cannot be performed in this time further low order bits can be ignored The RTC registers cannot be set by a write operation but they can be cleared and counted individually or by subset In this manner any register or the entire 48 bit counter can be set to any value with no more than 256 steps If the 32 KHz crystal is not installed and the input pin is grounded no counting will take place and the six registers can be used as a small battery backed memory Normally this would not be very productive since the cir cuitry needed to provide the power switchover could also be used to battery back a regular low power static RAM Table 10 Real Time Clock Read Registers Real Time Clock x Holding Register RTCOR R W Address 00000010 RTCIR Address 00000011 RTC2R Address 00000100 RTC3R Address 00000101 RTCAR Address 00000110 RTCSR Address 00000111 Table 11 Real Time Clock RTCxR Data Registers Bit s Value Description 7 0 Read The current value of the 48 bit holding register is returned Writing to the RTCOR transfers the current count of the RTC to six holding Write registers while the RTC continues counting 72 Rabbit 2000 Microprocessor Table 12 Real Time Clock Control Register RTCCR adr 01h Bit s
99. c C runs on a PC under Windows 95 98 or Windows NT It provides a combined compiler editor and debugger The usual method for debugging a target system based on the Rabbit is to im plement the 10 pin programming connector that connects to the PC serial port via a stan dard converter cable Dynamic C libraries contain highly perfected software to control the Rabbit These includes drivers utility and math routines and the debugging BIOS for Dy namic C In addition the internationally known real time operating system uC OS II is being ported to the Rabbit and will be available with some versions of Dynamic C 18 Rabbit 2000 Microprocessor 3 Details on Rabbit Microprocessor Features 3 1 Processor Registers The Rabbit s registers are nearly identical to those of the 7180 or the 780 Figure 5 shows the register lavout The XPC and IP registers are new The EIR register is the same as the 780 I register and is used to point to a table of interrupt vectors for the externally gener ated interrupts The IIR register occupies the same logical position in the instruction set as the Z80 R register but its function is to point to an interrupt vector table for internally gen erated interrupts A F IX IP E L 8 16 bit IY D E registers SP IIR B C PC EIR XPC A F A 8 bit accumulator H L F flags register D HL 16 bit accumulator 1
100. c and Logical Operations on page 153 8 bit Bit Set Reset and Test Instructions on page 154 8 bit Increment and Decrement on page 154 8 bit Fast A register Operations on page 154 8 bit Shifts and Rotates on page 155 Instruction Prefixes on page 156 Block Move Instructions on page 156 Control Instructions Jumps and Calls on page 156 Miscellaneous Instructions on page 157 Privileged Instructions on page 157 Key n 8 bit data item bit offset alternate destination prefix permitted and the flags stored in F in A column alternate destination prefix stores to alternate in I column I O prefixes are allowed IOE IOI I O is source in I column I O prefixes are allowed IOE IOI I O is dest overflow flag set on overflow overflow flag set if upper 4 bits of data word are zero flag not affected flag is set by operation Flag labels S sign Z zero V overflow C carry Mob EE Stee 4 A I 18 1 Load Immediate Data Instruction clk A 152 Operation LD IX mn 8 IX mn LD IY mn 8 mn LD dd mn 6 r dd mn LD r n 4 r ren User s Manual 149 18 2 Load and Store to an Immediate Address Instruction LD mn A LD A mn LD mn HL LD mn IX 10 mn IY LD mn ss LD HL mn LD IX mn LD mn LD dd mn clk 10 9 13 15 15 15 11 13 13 13 18 3 8 bit Indexed Load and Sto
101. cal Operations Instruction A HL A IX d A 4 A n A r A HL A IX d A 4 A n A r HL IX d IX d AND n AND r HL IX d IX d CP n CP r HL IX d clk N 4 10 O N A O N BO O UN BO fr fr fr fr fr fr fr fr fr fr fr fr H m FF 8 00 8 38 3 t xt t 39 FN ttt lt lt lt lt lt H t Hi HH lt lt lt lt lt lt lt lt lt lt lt OO O O O OP O s FT Operation HL CF IX d CF IY d CF n CF r CF HL IX d IY d n r HL IX d IY d n amp r HL IX d IY d n T gt p p p p p p p p pr p pr p p mm mom F gt p gt p p p p p p p p p p p p p p p p pp r HL A IX d User s Manual 153 OR 9 frs LO 44 OR n 4 fr LO A A n OR r 2 fr LO A A r SBC IX d 9 V CY SBC IY d 9 IY d CY SBC A HL 5 V CY SBC A n 4 fr V A A n CY cout if r CY A SBC A r 2 fr V A A r CY cout if r CY A SUB HL 5 frs V HL SUB IX d 9 fr s A A SUB IY d 9 5 IY d SUB 4 fr V A A n SUB r 2 fr V A A r XOR HL 5 frs LO A amp HL
102. call came from the right caller If not go into an endless loop with interrupts disabled 3 Maintain data corruption flags and or checksums If these go wrong go into an end less loop with interrupts off 7 7 System Reset The Rabbit has a master reset input RESET which initializes everything in the device except for the RTC This reset is delayed until the completion of any write cycles in progress to prevent any potential corruption of memory If no write cycles are in progress the reset takes effect immediately 74 Rabbit 2000 Microprocessor The purpose of inhibiting the completion of reset until write cycles in progress are com pleted is to protect variables in battery backed memory from corruption when a reset takes place However if the power controller responsible for battery switchover blocks the chip select signal to the RAM the writes in progress with be aborted in any case This is not necessarily serious as software schemes can be used to protect critical variables in battery backed memory The reset sequence requires a minimum of 128 cycles of the fast oscillator to complete even if no write cycles were in progress at the start of the reset Reset forces both the pro cessor clock and the peripheral clock in the divide by eight mode Note that if the proces sor is being clocked from the 32 kHz oscillator the 128 cycles of the fast oscillator will probably not be sufficient to allow any writes in progress to be com
103. cess is that most instructions continue to use 16 bit addressing Only when an out of range transfer of control is made does a 20 bit trans fer of control need to be made The beauty of having a 4K minimum step in page align ment while the size of the page is 8K is that code can be compiled continuously without gaps caused by change of page When the page is moved by 4K the previous end of code is still visible in the window provided that the midpoint of the page was crossed before moving the page alignment As the compiler compiles code in the extended code window it checks at oportune times to see if the code has passed the midpoint of the window or F000 When the code passes F000 the compiler slides the window down by 4K so that the code at F000 x becomes resident at 000 This results in the code being divided into segments that are typically AK long but which can very short or as long as 8K Transfer of control can be accom plished within each segment by 16 bit addressing 20 bit addressing is required between segments User s Manual 85 FFFF E000 FFFF E000 4K pages Memory View in 8K window each segment Figure 23 Compilaton of Code Segments in Extended Memory 86 Rabbit 2000 Microprocessor 9 Parallel Ports The Rabbit has five 8 bit parallel ports designated A B C D and E The pins used for
104. cessor The built in main clock oscillator uses an external crystal or more usually a ceramic resonator Typical resonator frequencies are in the rang eof 1 8 MHz to 29 5 MHz Since precision timing is available from the separate 32 768 kHz oscillator a low cost ceramic resonator with 1 2 percent error is generally satisfactory The clock can be dou bled or divided by 8 to modify speed and power dynamically The I O clock which clocks the serial ports is dividedseparately so as not to affect baud rates and timers when the processor clock is divided or multiplied For ultra low power operation the processor clock can be driven from the separate 32 768 kHz oscillator and the main oscillator can be powered down This allows the processor to operate at approximately 100 uA and still execute instructions at the rate of approximately 10 000 instructions per second This is a powerful alternative to sleep modes of operation used by other processors The current is approximately 65 mA at 25 MHz and 5 V The current is proportional to voltage and clock speed at 3 3 V and 7 68 MHz the current would be 13 mA and at 1 MHz the current is reduced to less than 2 mA Flash memory with automatic power down from AMD should be used for operation at the lowest power The excellent floating point performance is due to a tightly coded library and powerful processing capability For example a 25 MHz clock takes 14 us for a floating add 13 us for a multiply
105. cessors could use these bits for new purposes The registers IX and HL can also serve as index registers Thev point to memorv ad dresses from which data bits are fetched or stored Although the Rabbit can address a megabyte or more of memory the index registers can only directly address 64K of mem ory except for certain extended addressing Idp instructions The addressing range is expanded by means of the memory mapping hardware see Memory Mapping on page 20 and by special instructions For most embedded applications 64K of data mem ory as opposed to code memory is sufficient The Rabbit can handle a megabyte of code space in an efficient manner The register SP points to the stack that is used for subroutine and interrupt linkage as well as general purpose storage A feature of the Rabbit and the Z80 Z180 is the alternate register set Two special in structions swap the alternate registers with the regular registers The instruction ex af af exchanges the contents of AF with AF The instruction exx exchanges HL DE and BC with HL DE and BC Communication between the regular and alternate register set in the original Z80 architecture was difficult because the exchange instructions provided the only means of communication between the regular and alternate register sets The Rabbit has new instructions that greatly improve communication between the regular and alter nate register set This effectively doubles the number
106. cillators and Clocks eese eren nennen nennen nennen 67 7 2 Clock Doublet ss suan Eth eter eei o p tt ondes 69 7 3 Controlling Power Consumption eese eene en enne nennen trennen 70 7 4 Output Pins CLK STATUS WDTOUT IOBEN eerte 71 7 5 Time Date Clock Real Time Clock nnne 71 7 6 Watchdog Timer ze eI ERE RCURUR ON URP pO qd RS 73 7 7 System RESET issir 74 7 8 Rabbit Interrupt Structure ss mem eene nennen enne entren aa 75 7 81 External Interrupts eee ete He ed pm te t etes 77 7 9 Bootstrap Operation eene eret reine 79 Rabbit Memory Mapping and Interface 8l 8 1 Unit oco entente te te ee ER ees 81 8 2 Memory Interface Unit ete dee IER S eect as 83 8 3 Memory Bank Control Register Functions eese nennen 83 8 3 1 Optional A16 A19 Inversions by Segment CS1 Enable 84 8 4 Allocation of Extended Code and 84 8 5 How the Compiler Compiles to Memory eese 85 Parallel POPs u EUER A 87 9 1 Parallel Port Assisi A i i E ee ne sS 87 9 2 Parallel Port B regne teneo pred qui 88 9 3 Parallel Port C s y n Re D
107. clock perclk 2 in Figure 27 on page 97 Bits 1 and 4 7 are written write only to enable the interrupt for the corresponding timer User s Manual 99 The control register TACR is laid out as shown in Table 32 Timer A Control Register adr OA4h Bit 7 Bit 6 Bit 5 Bit 4 Bits 3 2 Bits 1 0 A7 A6 5 4 Source 7 Source Source 5 Source 4 not used 00 Interrupt disabled O pclk 2 O pclk 2 O pclk 2 O pclk 2 ignored 01 Enable priority 1 interrupt 1 1 1 1 1 1 1 1 10 Enable priority 2 interrupt 11 Enable priority 3 interrupt The time constant register for each timer is simply an 8 bit data register holding a number between 0 and 255 The time constant registers are write only 11 1 2 Practical Use of Timer A Timer A is disabled bit 0 in control and status register on power up Timer A is normally set up while the clock is disabled but the timer setup can be changed while the timer is running when there is a need to do so Timers that are not used should be driven from the output of Al and the reload register should be set to 0 This will cause counting to be as slow as possible and consume minimum power Timer A has five separate subtimer units Al and A4 A5 that are also referred to as tim ers Most likely if a serial port is going to be used and a timer is needed to provide the baud clock that timer will be set up to be driven directly from the clock and the interru
108. connected because the SMODEI SMODEO pins are sensed as high This will cause the BIOS to think that it should enter programming mode The Dynamic C programming mode then can have an escape message that will enable the diagnostic serial port function Another approach to enabling the diagnostic port is to poll the serial port periodically to see if communication needs to begin or to enable the port and wait for interrupts The SMODEX pins can be used for signaling and can be detected by a poll However recall that the SMODEXx pins have a special function after reset and will inhibit normal reset be havior if not held low The pull up resistors on RXA and CLKA prevent spurious data re ception that might take place if the pins floated If the clocked serial mode is used the serial port can be driven by having two toggling lines that can be driven and one line that can be sensed This allows a conversation with a device that does not have an asynchronous serial port but that has two output signal lines and one input signal line The line TXA also called PC6 is zero after reset if cold boot mode is not enabled A possible way to detect the presence of a cable on the programming port is for the cable to connect TXA to one of the SMODE pins and then test for the connection by raising PC6 and reading the SMODE pin after the cold boot mode has been disabled A 1 2 Alternate Programming Port The programming port uses serial port A If the user needs
109. cy typically in the range from 1 8 MHz to 29 5 MHz The processor clock is derived from the oscillator output by either doubling the frequency using the frequency directly or dividing the frequency by 8 The processor clock can also be driven by the 32 768 kHz oscillator for very low power opera tion in which case the main oscillator can be shut down under software control Table 1 provides preliminary estimates of the operating power for selected clock speeds Table 1 Preliminary Operating Power Estimates at Selected Clock Speeds Clock Speed Voltage Current Power Clock Speed Voltage Current Power MHz V mA mW MHz V mA mW 25 0 5 0 80 400 6 0 2 5 10 25 12 5 5 0 40 200 3 0 2 5 5 12 12 5 3 3 26 87 1 5 25 2 5 6 6 0 3 3 13 42 0 032 2 5 0 054 0 135 14 Rabbit 2000 Microprocessor 2 2 3 Time Date Oscillator The 32 768 kHz oscillator drives an external 32 768 kHz quartz crystal The 32 768 kHz clock is used to drive a battery backable there is a separate power pin internal 48 bit counter that serves as a real time clock RTC The counter can be set and read by soft ware and is intended for keeping the date and time There are enought bits to keep the date for more than 100 years The 32 768 kHz oscillator is also used to drive the watchdog timer and to generate the baud clock for serial port A during the cold boot sequence 2 2 4 Parallel There are 40 parallel
110. duce current consumption to as low as 25 u A plus some leakage that would be significant at high operating temperatures 7 4 Output Pins CLK STATUS WDTOUT IOBEN Certain output pins can have alternate assignments as specified in Table 9 Table 9 Global Output Control Register GOCR OEh Bit s Value Description 7 6 00 CLK pin is driven with processor clock 01 CLK pin is driven with processor clock divided by 2 10 CLK pin is low 11 CLK pin is high 5 4 00 STATUS pin is active low during a first opcode byte fetch 01 STATUS pin is active low during an interrupt acknowledge 10 STATUS pin is low 11 STATUS pin is high 3 1 WDTOUTB pin is low 1 cycle minimum 2 cycles maximum of 32 kHz 0 WDTOUTB pin follows watchdog function 2 x This bit is ignored 1 0 00 IOBENB pin is active low during external I O cycles 01 IOBENB pin is active low during data memory accesses 10 IOBENB pin is low 11 IOBENB pin is high 7 5 Time Date Clock Real Time Clock The time date clock is a 48 bit ripple counter that is driven by the 32 768 kHz os cillator The RTC is a modified ripple counter composed of six separate 8 bit counters The carries are fed into all six 8 bit counters at the same time and then ripple for 8 bits The time for this ripple to take place is a few nanoseconds per bit and certainly should not should not exceed 200 ns fo
111. e Z180 mem ory mapping unit Figure 6 illustrates the relationship among the major components re lated to addressing memory Memory Memory Memo Processor Mapping lt 9 Interface lt gt Chips 16 Unit 20 Unit bits bits 20 bits plus control Figure 6 Addressing Memorv Components The memorv mapping unit receives 16 bit addresses as input and outputs 20 bit addresses The processor except for certain ldp instructions sees only a 16 bit address space That is it sees 65536 distinctly addressable bytes that its instructions can manipulate Three segment registers are used to map this 16 bit space into a 1 megabyte space The 16 bit space is divided into four separate zones Each zone except the first or root zone has a segment register that is added to the 16 bit address within the zone to create a 20 bit ad dress The segment register has eight bits and those eight bits are added to the upper four bits of the 16 bit address creating a 20 bit address Thus each separate zone in the 16 bit memory becomes a window to a segment of memory in the 20 bit address space The rel ative size of the four segments in the 16 bit space is controlled by the SEGSIZE register This is an 8 bit register that contains two 4 bit registers This controls the boundary be tween the first and the second segment and the boundary between the second and the third segment The location of the two movable segme
112. e clock edge that transfers data from the transmitter data register to the transmitter shift register The transmitter busy bit is cleared at the end of the stop bit of the character sent This bit will cause an interrupt to be latched when it goes from busy to not busy status after the last character has been sent there are no more data in the transmit ter data register Bits 0 1 4 Always read as zero User s Manual 107 Table 39 describes the serial port control registers Table 39 Serial Port Control Registers adr 11xx0100 xx A B C D Bit 7 6 Bit 5 4 Bit 3 2 Bit 1 0 00 no 01 receive 1 byte clocked mode A B 00 use port C for serial 01 use port D for serial 00 async mode 8 bits 01 async mode 7 bits 10 clocked mode 00 no interrupt 01 priority 1 interrupt 10 priority 2 10 send one byte I O A B external clock priority 3 clocked mode 1x disable receiver 11 clocked mode 11 reserved for future input internal clock A B use Bits 7 6 In asynchronous mode always store zero in these bits For ports A and B if the clocked serial mode is enabled store the code here to start an operation either receive or send If the clock is internal a burst of 8 clocks will drive the clock line In external mode the receiver or transmitter waits for an externally supplied burst of 8 clocks Bits 5 4 This enabl
113. e setin PDDDR ld hl PDDDRShadow point to shadow register ld de PDDDR set de to point to I O reg set 5 hl set bit 5 of shadow register use ldd instruction for atomic transfer ioi ldd io de hl side effect hl de In this case the 1dd instruction when used with an I O prefix provides a convenient data move from a memory location to an I O location Importantly the 1dd instruction is an atomic operation so there is no danger that an interrupt routine could change the shadow register during the move to the PDDDR register If two instructions such as the following were used instead of the Idd instruction ld a hl ld PDDDR a output to PDDDR then there is the possibility that an interrupt would take place after the first instruction change the shadow register and the PDDDR register and then after a return from the inter rupt the second instruction would execute and store an obsolete copy of the shadow regis ter in the PDDDR setting it to a wrong value There is no reason to have a shadow register for many of the registers that can be written to In some cases writing to registers is used as a handy way of changing a peripheral s state and the data bits written are ignored For example a write to the status register in the Rabbit serial ports is used to clear the transmitter interrupt request but the data bits are ignored and the status register is actually a read only register except for the special func
114. e that the watchdog will become effectively useless because when a crash takes place the program will enter an endless loop that includes a hit of the watch dog 16 4 2 The Virtual Watchdog System By default 10 virtual watchdogs are available This can be changed by a define define N WATCHDOG 15 default is 10 watchdogs To allocate a watchdog make the call N VdGetFreeWd char count establish watdog with timeout count 16 seconds To hit that watchdog use the call VdHitWd int N hit that watchdog To remove that watchdog from the table use the call VdReleaseWd int N release deestablish watchdog N User s Manual 143 144 Rabbit 2000 Microprocessor 17 Rabbit Standard BIOS Note The information in this chapter is provided for conceptual purposes An up date in the form of a software manual will clarify these issues The Rabbit standard BIOS is a package of software that handles startup shutdown and various basic features of the Rabbit Bv providing standard software to perform basic functions the user is relieved of the necessitv of re inventing this software for his own needs Further by using Z World s tested software the user greatly reduces the possibility of errors and bugs Z World provides the full source code for the BIOS so the user has the possibility of modifying it and so that the user has a ready reference to examine details of the operation of the BIOS that are not apparent from
115. e value output on pins PB6 and PB7 pack age pins 99 100 will also be low 9 3 Parallel Port C Parallel port C shown in Table 24 has four inputs and four outputs The even numbered ports PCO PC2 PC4 and PC6 are outputs The odd numbered ports PC1 PC3 PCS and PC7 are inputs When the data register is read bits 1 3 5 7 return the value of the voltage on the pin Bits 0 2 4 6 return the value of the signal driving the output buffers The signal driving the output buffers and the value of the output pin are normally the same Either the Port C data register is driving these pins or one of the serial port transmit lines is driving the pin The bits set in the PCFR Parallel Port C Function Register identify whether the data register or the serial port transmit lines were driving the pins Table 24 Parallel Port C Data Register and Function Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PCDR 1 Echo Echo Echo Echo adr 050h lm drive drive Bla drive Peu drive PC6 PC2 PCO 050h 5 5 5 5 w Drive 5 Drive x Drive 1 Drive adr 055h TXA TXB TXC TXD 88 Rabbit 2000 Microprocessor Parallel port C shares its pins with the four serial ports The parallel port input pins mav also serve as serial port inputs Serial ports A and B can alternatelv use pins in Port D as inputs and the source of the serial port inputs for these serial po
116. ear carry sbc hl de C if HL gt DE sbc hl hl hl hl C zero if no carry 1 if C inc hl 14 16 clocks total if C after first sbc result 1 else O 0ifC 1 if IC compute hl de or a clear carrv sbc hl de zero is equal bool hi force to zero 1 dec hl invert logic bool hl 12 clocks total logical not 1 for inputs equal User s Manual 35 Some simplifications are possible if one of the unsigned numbers being compared is a constant Note that the carrv has a reverse sense from sbc test for hl B is constant ld de 65535 B add hl de carry set if hl B sbc hl hl hl hl C result 1 if carry set else zero bool hi 14 total clocks true if hl B hl B B is constant not zero 14 de 65536 B add hl de sbc hl hl bool hl 14 clocks hl B B is zero ld hl 1 6 clocks hl B B is a constant not zero if B 0 always false 14 65536 B add hl de not carry if hl B sbc hl hl 1 if carry else O inc hl 14 clocks 0 if carry else 1 if no carry hl B B is constant not zero 14 de 65535 B add hl de C if hl B ccf C if true sbc hl hl if C 1 else 0 inc hl 16 clocks 1 if true else 0 hl B B is zero true if hl bool hl result in hl hl B and B is a constant not zero ld de 65536 B add hl de zero if equal bool hl inc hl res 1 1 16 clocks hl B and B bool hl inc hl res 1 1 8 clocks For signed int
117. ed by the I O bank control registers IBxCR The data direction must be set to output for the I O strobe to work e PEBxR These are individual registers to set individual output bits on or off e PECR Parallel port E control register This register is used to control the clocking of the upper and lower nibble of the final output register of the port On reset bits 0 1 4 and 5 are reset to zero Table 27 Parallel Port E Registers Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDR R W adr 070h PE7 PE6 PES PE4 PE3 PE2 PEI PEO PEFR W adr 075h alt I7 alt I6 alt I5 alt I4 alt I3 alt I2 alt alt IO PEDDR W adr 077h dir out dir out dir out dir out dir out dir out dir out dir out PEBOR W adr 078h PEO PEBIR W adr 079h PEI PEB2R W adr 07Ah PE2 PEB3R W adr 07Bh PE3 PEBAR W adr 07Ch PE4 PEBSR W adr 07Dh PES PEB6R W adr 07Eh PE6 PEB7R W adr 07Fh PE7 User s Manual 93 Table 28 Parallel Port E Control Register adr 074h Bits 7 6 Bits 5 4 Bits 3 2 Bits 1 0 00 clock upper nibble on pclk 2 01 clock on timer A1 10 clock on timer B1 11 clock on timer B2 00 clock lowe
118. ee instructions are each 2 bvtes and 15 clocks ex sp hl ex sp ix ex sp iy 3 3 6 Push and Pop Instructions There are instructions to push and pop the 16 bit registers AF HL DC BC IX and IY The registers AF HL DE and BC can be popped Popping the alternate registers is exclusive to the Rabbit and is not allowed on the Z80 7180 Examples pop hl push bc push ix push af pop de pop de pop hi 3 3 7 16 bit Arithmetic and Logical Operations The HL register is the primary 16 bit accumulator IX and IY can serve as alternate accu mulators for many 16 bit operations The Z180 Z80 has a weak set of 16 bit operations and as a practical matter the programmer has to resort to combinations of 8 bit operations in order to perform many 16 bit operations The Rabbit has many new op codes for 16 bit operations removing some of this weakness The basic Z80 Z180 16 bit arithmetic instructions are add hl ww where ww is HL DE BC SP adc hl ww add and add carry sbc hl ww sub and sub carry inc ww increment the register without affecting flags In the above op codes IX or IY can be substituted for HL The add and adc instructions can be used to left shift HL with the carry An alternate destination prefix altd may be used on the above instructions This causes the result and its flags to be stored in the cor responding alternate register If the altd flag is used when IX or IY is the destination re
119. egers the conventional method to look at the zero flag the minus flag and the overflow flag Signed 8 bit integers span the range 128 to 127 80h to 7Fh Signed 16 bit integers span the range 32768 to 4 32767 8000h to 7FFFh The sign and zero flag tell which is the larger number after the subtraction unless the overflow is set in which case the sign flag needs to be inverted in the logic that is it is wrong 36 Rabbit 2000 Microprocessor gt 18 8 IV 8 Z v S amp V A B 5 amp v 15 8 V amp Z A A gt B A lt B Another method of doing signed compare is to first map the signed integers onto unsigned integers by inverting bit 15 This is shown in Figure 10 on page 37 Once the mapping has been performed by inverting bit 15 on both numbers the comparisions can be done as if the numbers were unsigned integers This avoids having to construct a jump tree to test the overflow and sign flags An example is shown below test hl gt 5 for signed integers de 65535 5 08000h 5 mapped to unsigned integers ld bc 08000h add hl bc invert high bit add hl de 16 clocks to here carry now set if hl 5 opportunity to jump on carry subc hl hl hl hl C if C on result is 1 else zero bool hl 22 clocks total true if hl 5 else false 0111 1111 000 100 111 011 100 000 Figure 10 Mapping Signed Integers to Unsigned Integers by Inverting
120. el Port E Parallel port E shown in Figure 25 has eight I O pins that can be individually programmed as inputs or outputs Port E has a higher drive than most of the other ports PE7 is used as the slave port chip select when the slave port is enabled Each of the port E outputs can be configured as an I O strobe In addition four of the port E lines can be used as interrupt re quest inputs The output registers are cascaded and timer controlled making it possible to generate precise timing pulses scs D PE7 0 lt 16 lt q gt INT1 15 lt 4 1 INTO N A inputs I O Data perclk 2 Timer A1 Timer B1 Timer B2 PE3 lt p A 23 p lt INT1 n gt PEO A AQ mW em perclk 22 Timer A1 Timer B1 Timer B2 Figure 25 Parallel Port E Block Diagram 92 Rabbit 2000 Microprocessor The following registers are described in Table 27 and in Table 28 PEDR Port E data register Reads value at pins Writes to port E preload register PEDDR Port E data direction register Set to 1 to make corresponding pin an out put This register is zeroed on reset e PEFR Port function register Set bit to 1 to make corresponding output an I O strobe The nature of the I O strobe is controll
121. ent length Since the duty cycle of the built in oscillator can be as asymmetric as 55 45 the clock generated by the clock doubler will exhibit up to a 1096 variation in period on alternate clocks This does not affect the no wait states memory access time since two adjacent clocks are always used However the maximum allowed clock speed must be reduced by 10 if the clock is supplied via the clock doubler The only signals clocked on the falling edge of the clock are the memory and I O write pulses and these have noncritical timing Thus the length of the clock low time is noncritical as long as it is not so long as to shorten the clock high time excessively which could make the write pulse too short for the memory used This is unlikely to happen with practical clock speeds and typical static RAM memories User s Manual 69 Oscillator 45 55 Oscillator delaved and inverted Doubled clock Delav gt a time 0 45P 0 55P 0 45P 0 55P Address Example Write Data out lt Cycle y Write pulse Figure 18 Effect of Clock Doubler The power consumption is proportional to the clock frequency and for this reason power can be reduced by slowing the clock when less computing activity is taking place The clock doubler provides a convenient method of temporarily speeding up or slowing down the clock as part of a power
122. ernal clock is used this pin should be driven by the external clock 40 XTALA2 Output Quartz crystal for 32 kHz crystal oscillator Do not connect if an exernal clock is used 41 XTALBI Input Quartz crystal for main system oscillator Lines to the crystal should be short and shielded from crosstalk If an external clock is used this pin should be driven by the external clock 90 XTALB2 Output Quartz crystal for main system oscillator Do not connect if an exernal clock is used 91 CPU Buses 0 19 Address bus 7 17 20 61 68 70 75 79 D0 D7 Bidirectinal Data bus 9 16 Status Cont rol WDTOUT Output WDT timeout outputs a pulse when the internal watchdog times out May also be used to output a 30 pulse 34 Status STATUS Output Programable for functions 1 driven low on first opcode fetch cycle 2 driven low during interrupt acknowledge cycle 3 to serve as a general purpose output See Table 9 Global Output Control Register GOCR OEh on page 71 38 52 Rabbit 2000 Microprocessor Table 3 Rabbit Pin Assignments SMODEI SMODEO Input Startup mode select SMODEI pin 35 SMODEO pin 36 to detemine bootstrap procedure SMODEI 0 SMODEO 0 start executing at address zero 0 1 cold boot from slave port 1 0 clold boot from clocked serial port A 1 1
123. es by 240 a baud rate of 2400 bps can be achieved in one step The clock input to the serial port must be 16 times the baud rate for asynchronous mode and 8 times the baud rate for synchronous mode The maximum asynchronous baud rate with a 22 1184 MHz clock would be 22 118 400 2 16 691 200 Each of the five countdown registers in timer A can cause an interrupt There is one inter rupt vector for timer A and a common interrupt priority A common status register TACSR has a bit for each timer that indicates if the output pulse for that timer has taken 98 Rabbit 2000 Microprocessor place since the last read of the status register When the status register is read these bits are cleared No bit will be lost Either it will be read the status register read or it will be set after the status register read is complete If a bit is on and the corresponding inter rupt is enabled an interrupt will occur when priorities allow However a separate inter rupt is not guaranteed for each bit with an enabled interrupt If the bit is read in the status register it is cleared and no further interrupt corresponding to that bit will be requested It is possible that one bit will cause an interrupt and then one or more additional bits will be set before the status register is read After these bits are cleared they cannot cause an in terrupt If any bits are on and the corresponding interrupt is enabled then the interrupt will take place as soon
124. es the standard or alternate I O pins for the ports Alternate I O applies only to ports A and B The parallel port output function for the specified TX pin becomes disabled when the port is enabled Bits 3 2 This sets the mode of operation Modes 10 and 11 apply only to ports A and B Bits 1 0 These bits enable interrupts and set the interrupt priority 12 2 Serial Port Interrupt A common interrupt vector is used for the receive and transmit interrupts There is a sep arate interrupt request flip flop for the receiver and transmitter If either of these flip flops is set a Serial port interrupt is requested The flip flops are set by a rising edge only The flip flops are cleared by a pulse generated by an I O read or write operation as shown in Figure 31 When an interrupt is requested it will take place immediately when priorities allow and an instruction execution is complete The interrupt is lost if the request flip flop is cleared before the interrupt takes place If the flip flop is not cleared in the interrupt another interrupt will take place when priorities are lowered The receive interrupt request flip flop is set after the stop bit is sampled on receive nomi nally 1 2 of the way through the stop bit data bits are transferred on this same clock from the receive shift register to the receive data register The transmit interrupt request flip flop is set on the trailing edge of the stop bit This edge is the same whether the
125. esign rules are simple Up to six static memorv chips such as RAM and flash EPROM connect directly to the microprocessor with no glue logic Even larger amounts of memory can be handled by using parallel I O lines as high order address lines The Rabbit runs with no wait states at 24 MHz with a memory having an access time of 70 ns There are two clocks per memory access Most I O devices may be connected without glue logic The memory cycle is two clocks long A clean memory and I O cycle completely avoid the possibility of tri state fights Peripheral I O devices can usually be interfaced in a glueless fashion using pins programmable as I O chip selects I O read strobes or I O write strobe pins A built in clock doubler allows 2 frequency crystals to be used to reduce radiated emissions The Rabbit may be cold booted via a serial port or the parallel access slave port This means that flash program memory may be soldered in unprogrammed and can be reprogrammed at any time without any assumption of an existing program or bios A Rabbit that is slaved to a master processor can operate entirely with volatile RAM depending on the master for a cold program boot There are 40 parallel I O lines shared with serial ports Some I O lines are timer syn chronized which permits precisely timed edges and pulses to be generated under com bined hardware and software control There are four serial ports All four serial ports can operate asynchronously
126. even stored the same in formation to a register The master slave communication link makes possible set and forget communication protocols Either side can issue a command or request by storing data in some register and then go about its business while the other side takes care of the request according to its own time schedule The other side can be alerted by an interrupt that takes place when a store is made to register zero or it can alert itself by a periodic poll of the status register Of the three registers seen by each side for each direction of communication the first reg ister slave register zero has a special function because an interrupt can only be generated by a write to this register which then causes an interrupt to take place on the other side of the link if the interrupt is enabled One type of protocol is to store data first in registers 1 and 2 and then as the last step store to register 0 Then 24 bits of data will be available to the interrupt routine on the other side of the link Bulk data transfers accross the link can take place by an interrupt for each byte transferred similiar to a typical serial port or UART In this case a full duplex transfer can take place similar to what can be done with a UART The overhead for such an interrupt driven transfer will beon the order of 100 clocks per byte transfered assumming a 20 instruction interrupt routine In order to keep the interrupt routine to 20 instructions the
127. every 488 us If the 32 768 kHz oscillator is absent it is possible to substitute a different periodic interrupt but this alternative is not supported by Z World since it the cost of connecting a crystal is very small The periodic interrupt is used to count several memory counters that are used for general software use These counters count ticks milliseconds and seconds These counters have an exact relationship with the real time clock and the 32 768 kHz oscillator A seconds counter is generated by adding 65536 2048 32 to a 16 bit word on every tick The carry out counts the seconds counter A millisecond counter is obtained by adding 32000 to a 16 bit word on every tick The carry out occurs on an average of once per millisecond and drives the millisecond counter T he tick counter is counted 2048 times per second In addition the periodic interrupt provides support for function slicing and a real time ker nel by providing periodic calls to clock routines The periodic interrupt keeps the inter rupts turned off that is the processor priority is raised to 1 from zero for a minimum time of about 35 clocks In this way the periodic interrupt makes little contribution to interrupt latency 146 Rabbit 2000 Microprocessor 17 3 1 Real Time Clock Support If the real time clock is batterv backed which is an option in the BIOS the BIOS reads the real time clock on startup and sets up the seconds since 1980 counter svnchronized with the c
128. f virtual watchdog tim ers Routines to speed up and slow down the system clock for power management The execution speed can be controlled over a wide range e Routines to set up the mode of operation of the parallel ports and to input and output data to them User s Manual 145 e Routines to initialize the timers and manipulate them Routines to write flash memory with built in protection of the system identification area Routines to maintain an error log or operation log and to handle fatal errors and watch dog timeouts Basic services for multitasking e Routines that support a general purpose parameter setup via the programming port This system can be used in the field for such items as setting a network address or cali bration constants and setting the real time clock A download manager to be available with future releases of the BIOS e Modbus slave 17 2 BIOS Assumptions The BIOS makes certain assumptions concerning the physical configuration of the proces sor Processors are expected to have RAM connected to CS1 WEI and 1 Flash memory if present is expected to be connected to CSO WEO and OEO The crystal fre quency is expected to be n 6144 3 MHZ or else 4 6144 MHz 17 3 Periodic Interrupt and Real Time Clock BIOS Services The real time clock is driven by the 32 768 kHz oscillator which may be battery backed The periodic interrupt when enabled occurs every 16 clocks or
129. ferred automatically resets the watchdog timer However the watchdog timer still operates and bytes must be transferred often enough to prevent the watchdog timer from timing out Bootstrap operation is terminated when the SMODE pins are set to zero The SMODE pins are sampled just prior to fetching the first instruction of the bootstrap program If the SMODE pins are zero instructions are fetched from normal memory starting at address 0000h The Slave Port Control register allows the bootstrap operation to be terminated re motely Writing a one to bit 7 of this register causes the bootstrap operation to terminate immediately So the sequence 80h 24h and 80h will terminate bootstrap operation Bootstrap operation is not restricted to the time immediately after reset because the boot ROM is addressed by only the four least significant bits of the address So any time that the address ends in four zeros if the SMODE pins are non zero and bit 7 of the SPCR is Zero the bootstrap program will begin execution This allows in line downloading from the selected bootstrap port Upon completion of the bootstrap operation either by return ing the SMODE pins to zero or setting the bit in the SPCR execution will continue from where it was interrupted for the bootstrap operation The Slave Port is selected for bootstrap operation when SMODEI 5 0 1 In this case the pins of Parallel Port A are used for a byte wide data bus and selected pi
130. footprint can accept either a 128K x 8 RAM with 17 address lines ora 512K x 8 RAM with 19 address lines then address lines A18 and A19 can be in terchanged with each other but not exchanged with AO A17 Permuting lines does make a difference with flash memory If the memory is socketed and it is intended to program the memory off the board then it is probably best to keep the ad dress and data lines in their natural order However since the flash can be programmed in the circuit using the Rabbit programming port it is expected that most designers will sol der the flash memory directly to the board in an unprogrammed state In this case the per meation of data and address lines must still be taken into account because flash memory requires the use of a special unlock code that removes write protection The unlock oper ation involves a special sequence of reads and writes accessing special addresses and writ ing the unlock codes Another consideration is that the flash memory may be divided into sectors In order to modify the memory an entire sector must be written In the small sector memories the memory is divided into 1024 sectors If the largest flash memory that is usable in a partic ular design is 512K the largest sector size is 512 bytes If the smallest memory used is 128K then the smallest sector is 128 bytes In order that the sector can be contiguous for all possible types of memory the lower 7 address lines AO A6 should be
131. g ister then only the flags are stored in the alternate flag register 30 Rabbit 2000 Microprocessor The following new instructions have been added for the Rabbit Shifts rr hl rotate hl right with carry 1 byte 2 clocks note use adc hl hl for left rotate or add hl hl if no carry in is needed rr de 1 byte 2 clocks rl de rotate de left with carry l bvte 2 clocks rr ix rotate ix right with carry 2 bytes 4 clocks rr iy rotate iy right with carry Logical Operations and hl de 1 byte 2 clocks and ix de 2 bytes 4 clocks and iy de or hl de 1 byte 2 clocks or ix de 2 bytes 4 clocks or iy de The bool instruction is a special instruction designed to help test the HL register bool sets HL to the value 1 if HL is non zero otherwise if HL is zero its value is not changed The flags are set according to the result bool can also operate on IX and IY bool hl set hl to 1 if non zero set flags to match hl bool ix bool iy altd bool hl set hl an f according to hl altd bool iy modify iy and set f with flags of result The sbc instruction can be used in conjunction with the bool instruction for performing comparisions The sbc instruction subtracts one register from another and also subtracts the carry bit The carry out is inverted compared to the carry that would be expected if the number subtracted was negated and added The following examples illustrate the use of the sbc and bool i
132. get toggling the clock can simply send a clocked serial message to get the attention of the PC The intermediate communications board can accept these unsolicited messages using its clocked serial port To prevent overrunning the receiver the target can wait for a handshake signal on one of the SMODE lines or there can be suitable pre arranged delays If the PC wants attention from the target it can set a line to request attention SMODEX The target will detect this line in the periodic interrupt routine and handle the complete message in the periodic interrupt routine This may slow down target execution but the in terrupts will be enabled on the target while the message is read The intermediate board could split long messages into a series of shorter messages if this is a problem A 2 Suggested Rabbit Crystal Frequencies Table 44 on page 134 provides a list of suggested Rabbit operating frequencies The crys tal can be half the operating frequency if the clock doubler is used up to approximately 25 MHz B eyond this operating clock speed it is necessary to use an X1 crystal or an exter nal oscillator because asymetery in the waveform generated by the oscillator becomes a variation in the clock speed if the clock speed is doubled User s Manual 169 170 Rabbit 2000 Microprocessor Legal Notice Rabbit Semiconductor products are not authorized for use as critical components in life support devices or svstems unless a specific wr
133. h ioe ld hl iv45 get word from external I O location 4005h By using the prefix approach all the 16 bit memory access instructions are available for reading and writing I O locations The memory mapping is bypassed when I O operations are executed I O writes to the internal I O registers require only two clocks rather than the minimum of three clocks required for writes to memory or external I O devices 3 4 How to Do It in Assembly Language Tips and Tricks 3 4 1 Zero HL in 4 Clocks boolhl 2 clocks clears carry hl is 1 or O rr hl 2 clocks 4 total get rid of possible 1 This sequence requires four clocks compared to six clocks for 1d 11 0 User s Manual 33 3 4 2 Exchanges Not Directly Implemented HL lt gt HL eight clocks ex de hl 2 clocks ex de hl 4 clocks ex de hl 2 clocks 8 total DE lt gt DE six clocks ex de hl 2 clocks ex de hl 2 clocks ex de hl 2 clocks 6 total BC lt gt BC 12 clocks ex de hl ex de hl 4 ex de hl 22 exx 2 5322 Move between IX and DE DE IX TY gt DE DE gt IX TY jix ix gt de ex de hl ld hl ix iy 14 ix iy hl ex de hl 8 clocks total de ix iy ex de hl ld ix iy hl ex de hl 8 clocks total 3 4 3 Manipulation of Boolean Variables Logical operations involving HL when HL is a logical variable with a value of 1 or 0 this is important for the C language where
134. h registers the B1 match register and the B2 match register When the counter counts and transitions to a value equal to a match register a 1 peripheral clock long pulse is out put The match pulses can be used to cause interrupts and or clock the output registers in parallel ports D and E The match register is loaded from a preload register that can be written by an I O instruction The data bits are advanced from the preload register to the match register when the match pulse is output The I O registers for Timer B are listed in Table 33 Table 33 Timer B Registers Register Name Register Mnemonic R W pu Timer B Control Status Register TBCSR BO R W XXxxx000 Timer B Control Register TBCR Bl 00 Timer B MSB 1 Reg TBMIR B2 x Timer B LSB 1 Reg TBLIR B3 w x Timer B MSB 2 Reg TBM2R B4 w x Timer B LSB 2 Reg TBL2R B5 w x Timer B Count MSB Reg TBCMR BE R x Timer B Count LSB Reg TBCLR BF R x The control status register for Timer B TBCSR is laid out as shown in Table 34 Table 34 Timer B Control and Status Register TBCSR adr 0B0h Bits 7 3 Bit 2 Bit 1 Bit 0 Not used 1 A match with match 1 A match with match Enable the main clock register 2 was detected register 1 was detected for this timer This bit is cleared by a This bit is cleared by a read of this register a read of this register a write to this register write to this reg
135. he Rabbit can also be operated as a slave processor via a serial port and some of the protocols will work well via a serial communications connection If a serial connection is used the protocol becomes more complicated if errors in transmission need to be taken into account If the physical link can be controlled so that transmission errors do not occur a realistic possibility if the interconnection environment is controlled the se rial protocol is simpler and faster than if error correction needs to be taken into account 13 3 1 Slave Applications Motion Controller Many types of motion control require fast action may be com pute intensive or both Traditional servo system solutions may be overly expensive or not work very well because of system nonlinearities The basic communications model for a motion controller is for the master to send short messages positioning com mands to the slave The slave acknowledges execution of the commands and reports exception conditions Communications Protocol Processor Communications protocols may be very com plex may require fast responses or may be compute intensive Graphics Controller The Rabbit can be used to perform operations such as drawing geometric figures and generating characters e Digital Signal Processing Although the Rabbit is not a speciality digital signal pro cessor it has enough compute speed to handle some types of jobs that might otherwise require a speciali
136. he data bus If a Rabbit is used asa master this line is normally connected to the global I O read strobe IORD e SWR Input If SCS is also low this line causes the data bits on the data bus to be clocked into the register selected by the address lines on the rising edge of SWR or SCS whichever rises first If a Rabbit is used as a master this line is normally connected to the global I O write strobe IOWR e SLAVEATTN This line is set low asserted if the slave writes to the SPDOR register This line is set high if the master writes anything to the slave status register This line is usually connected to cause the master to be interrupted when it goes low The data lines of the slave port are shared with parallel port A that uses the same package pins The slave port can be enabled and parallel port A be disabled by storing an appropri ate code in the slave port control register SCR After the processor is reset all the pins be longing to the slave interface are configured as parallel port inputs unless SMODEI SMODEO are set to 0 1 in which case the slave port is enabled after reset and the slave starts the cold boot sequence using the slave port 13 1 Hardware Design of Slave Port Interconnection Figure 36 shows a typical circuit diagram for connecting two slave Rabbits to a master Rabbit The designer has the option of cold booting the slave and downloading the pro gram to RAM on each cold start Another option is to
137. he master is to be interrupted to acknowledge each character the slave can create an interrupt in the master bv storing a dummv character in SPDOR to create a master interrupt assuming that the SLAVEATTN line is wired to interrupt the master The acknowledgement message works in a similar manner except that the master writes a dummv character to interrupt the slave to sav that it has the character Several problems can arise if there are dual interrupts for each character transmitted One problem is that the message transmission rate will free run at a speed limited the inter rupt latencv and compute speed of each processor This could consume a high percentage of the compute resources of one or both processors starving other processes and espe cially interrupt routines for compute time If this is a problem then a timed interrupt can be used to drive the process on one side thus limiting the data transmission rate Another solution which may be better than limiting the transmission rate is to use inter rupts only for the first byte of the message on the slave side and then lower the interrupt priority and conduct the rest of the transaction as a polled transaction On the master side the entire transaction can be a polled transaction In this case the entire transaction takes place in the interrupt routine on the slave but other interrupts are not inhibited since the priority has been lowered A typical slave system consists of a R
138. ically by interrupt acknowledge Periodic 2KHz Read the GCSR Timer B Read the TBSR Timer A Read the TASR Slave Port Write SLSTAT Rx Read the SADR or SAAR Serial Port A Tx Write the SADR SAAR or SASR Rx Read the SBDR SBAR Serial Port B Tx Write the SBDR SBAR SBSR 1 Rx Read the SCDR SCAR Serial Port C l Tx Write the SCDR SCAR or SCSR Rx Read the SDDR or SDAR Lowest Serial Port D Tx Write the SDDR SDAR or SDSR In the case of the external interrupts the action that will clear the interrupt request is for the interrupt to take place which automaticallv clears the request A special action must be taken in the interrupt service routine for the other interrupts 7 8 1 External Interrupts There are two external interrupts The external interrupts take place on a transition of the input programmable for rising falling or both edges There are two interrupt pins in port E that can be enabled for each interrupt Each of the interrupt pins has its own catcher de vice to catch the edge transition and request the interrupt User s Manual 77 INTOA INTOB pulse catcher 1 gt D interrupt req0 interupt ack0 pulse catcher INTIA l INTIB Figure 19 External Interrupt Line Logic interrupt req1 biet pru o interupt ack1 When the interrupt takes pl
139. ified future time The match register has two cascaded registers the match register and the next match register The match register is loaded with the contents of the next match register when a pulse is generated This allows events to be very close together one count of Timer B Timer B can be clocked by sysc1k 2 divided by a number in the range of 1 256 Timer B can count as fast as 10 MHz with a 20 MHz system clock allowing events to be separated by as little as 100 ns Timer B and the match registers have 10 bits Using Timer B output pulses can be positioned to an accuracy of c1k 2 Timer B can also be used to capture the time at which an external event takes place in conjunction with the external interrupt line The interrupt line can be programmed to interrupt on either rising falling or both edges To capture the time of the edge the interrupt routine can read the Timer B counter The execution time of the interrupt routine up to the point where the timer is read can be subtracted from the timer value If no other interrupt is of the same or higher priority then the uncertainty in the position of the edge is reduced to the variable time of the interrupt latency or about one half the execution time of the longest instruc tion This uncertainty is approximately 10 clocks or 0 5 us for a 20 MHz clock This en ables pulse width measurements for pulses of any length with a precision of about 1 us If multiple pulses need to be measured simult
140. imer with a 500 ms timeout period 53h Restart hit the watchdog timer with a 250 ms timeout period other No effect on watchdog timer The watchdog timer may be disabled by storing a special code in the WDTTR register Normally this should not be done unless an external watchdog device is used The pur pose of the watchdog is to unhang the processor from an endless loop caused by a soft ware crash or a hardware upset It is important to use extreme care in writing software to hit the watchdog timer or to turn off the watchdog timer The programmer should not sprinkle instructions to hit the watchdog timer throughout his program because such instructions can become part of an endless loop if the program crashes and thus disable the recovery ability given by having a watchdog User s Manual 73 The following is a suggested method for hitting the watchdog An array of bytes is set up in RAM Each of these bytes is a virtual watchdog To hit a virtual watchdog a number is stored in a byte Every virtual watchdog is counted down by an interrupt routine driven by a periodic interrupt This can happen every 10 ms If none of the virtual watchdogs has counted down to zero the interrupt routine hits the hardware watchdog If any have counted down to zero the interrupt routine disables interrupts and then enters an endless loop waiting for the reset Hits of the virtual watchdogs are placed in the user s program at must exercise
141. in any number in the range from 0 to 255 The counter divides by 1 1 For example if the reload register contains 127 then 128 pulses enter on the left before a pulse exits on the right If the reload register contains zero then each pulse on the left re sults in a pulse on the right that is there is division by one Reload Register Diagram 8 bit reload register Clock i load Lq 8 bit down counter pulse on zero count out Input clock Count value 2 2 1 1 0 0 N N 1 Output pulse Figure 28 Reload Register Operation The timer systems are driven by the peripheral clock divided by two This clock is always the same as the processor clock or it is faster than the processor clock by a factor of eight The output pulses are always one clock long Clocking of the counters takes place on the negative edge of this pulse When the counter reaches zero the reload register is loaded on the next input pulse instead of a count being performed The reload registers may be reloaded at any time since the peripheral clock is synchronous with the processor clock Timers A4 A5 and A7 always provide the baud clock for serial ports A B C and D respectively Except for very low baud rates clock A1 does not need to be used to pres cale the input clock for timers A4 A7 For example if the system clock is 22 184 MHz and if the timer A4 divid
142. ine which devices are requesting an interrupt 78 Rabbit 2000 Microprocessor 7 9 Bootstrap Operation The device provides the option of bootstrap from anv of three sources from the Slave Port from Serial Port A in clocked serial mode or from Serial Port A in asvnchronous mode This is controlled the state of the SMODE pins after reset Bootstrap operation is disabled if SMODEI SMODEO 0 0 Bootstrap operation inhibits the normal fetch of code from memory and instead substi tutes the output of a small internal boot ROM for program fetches This bootstrap pro gram reads groups of three bytes from the selected peripheral device The first byte is the most significant byte of a 16 bit address followed by the least significant byte of a 16 bit address followed by a byte of data The bootstrap program then writes the byte of data to the downloaded address and jumps back to the start of the bootstrap program The most significant bit of the address is used to determine the destination for the byte of data If this bit is zero the byte is written to the memory location addressed by the downloaded address If this bit is one the byte is written to the internal peripheral addressed by the downloaded address Note that all of the memory control signals continue to operate nor mally during bootstrap Execution of the bootstrap program automatically waits for data to become available from the selected peripheral and each byte trans
143. ing registers requires 7 9 clocks Return from interrupt requires 7 clocks If three registers are saved and restored and 20 instruc tions averaging 5 clocks are executed an entire interrupt routine will require about 200 clocks or 10 us with a 20 MHz clock Given this timing the following capabilities be come possible Pulse width modulated output The minimum pulse width is 10 us If the repetition rate is 10 ms then a new pulse with 1000 different widths can be generated at the rate of 100 times per second User s Manual 43 Asvnchronous communications serial output Asvnchronous output data can be gener ated with a new pulse everv 10 us This corresponds to a baud rate of 100 000 bps Asvnchronous communications serial input To capture asvnchronous serial input the in put must be polled faster than the baud rate a minimum of three times faster with five times being better If five times polling is used then asvnchronous input at 20 000 bps could be received Generating pulses with precise timing relationships The relationship between two events can be controlled to within 10 us to 20 us Using a timer to generate a periodic clock allows events to be controlled to a precision of approximately 10 us However if Timer B is used to control the output registers a preci sion approximately 100 times better can be achieved This is because Timer B has a match register that can be programmed to generate a pulse at a spec
144. input output lines divided among five 8 bit ports designated A through E Most of the port lines have alternate functions such as serial data or chip se lect strobes Parallel ports D and E have the capability of timer synchronized outputs The output registers are cascaded Load Data Load Clock gt Port Output Timer Clock Figure 2 Cascaded Output Registers for Parallel 5 D and E Stores to the port are loaded in the first level register That register in turn is transferred to the output register on a selected timer signal The timer signal can also cause an interrupt that can be used to set up the next bit to be output on the next timer pulse This feature can be used to generate preciselv controlled pulses whose edges are positioned with high accu racv in time Applications include communications signaling pulse width modulation and driving stepper motors 2 2 5 Slave Port The slave port is designed to allow the Rabbit to be a slave to another processor which could be another Rabbit The port is shared with parallel port A and is a bidirectional data port The master can read anv of three registers selected via two select lines that form the register address and a read strobe that causes the register contents to be output by the port These same registers can be written as I O registers bv the Rabbit slave Three additional registers transmit data in the opposite direction They are written by
145. instruction to set flags if needed The sbc instruction can also be used to perform a sign extension extend sign of 1 to hl a l rla sign to carry sbc a a a is all 175 if sign negative ld h a sign extended The multiply instruction performs a signed multiply that generates a 32 bit signed result mul Signed multiply of bc and de result in hl bc 1 byte 12 clocks If a 16 bit by 16 bit multiply with a 16 bit result is performed then only the low part of the 32 bit result bc is used This counter intuitively is the correct answer whether the terms are signed or unsigned integers The following method can be used to perform a 16 x 16 bit multiply of two unsigned integers and get an unsigned 32 bit result This uses the fact that if a negtive number is multiplied the sign causes the other multiplier to be sub tracted from the product The method shown below adds double the number subtracted so that the effect is reversed and the sign bit is treated as a positive bit that causes an addi tion bc n1 1 hl bc save bc in hl 14 de n2 ld a b save sign of bc mul form product in hl bc or a test sign of bc multiplier jr p xl if plus continue add hl de adjust for negative sign in bc 1 1 de test sign of de jr nc x2 if not negative subtract other multipler from hl ex de hl add hl de x2 final unsigned 32 bit result in hl bc 32 Rabbit 2000 Microprocessor This method
146. instructions have been dropped to make available efficient 1 byte opcodes for important new instructions see Differences Rabbit vs Z80 Z180 Instructions on page 159 The advantage of this evolutionary ap proach is that users familiar with the Z80 or Z180 can immediately understand the Rabbit Existing source code can be assembled or compiled for the Rabbit with minimal changes Changing technology has made some features of the Z80 Z180 family obsolete and these have been dropped For example the Rabbit has no special support for dynamic RAM but it has extensive support for static memory This is because the price of static memory has decreased to the point that it has become the preferred choice for medium scale embedded systems The Rabbit has no support for DMA direct memory access because most of the uses for which DMA is traditionally used do not apply to embedded systems or they can be accomplished better in other ways such as fast interrupt routines external state ma chines or slave processors Our experience in writing C compilers has revealed the shortcomings of the Z80 instruc tion set for executing the C language The main problem is the lack of instructions for handling 16 bit words and for accessing data at a computed address especially when the stack contains that data New instructions correct these problems Another problem with many 8 bit processors is their slow execution and a lack of number crunching ability Good
147. interrupt routine needs to be very focused as opposed to general purpose Several methods are available to cater to a faster transfer with less computing overhead There are enough reg isters to transfer two bytes on each interrupt thus nearly halving the overhead If a ren dezvous is arranged between the processors data can be transferred at approximately 25 clocks per byte Each side polls the status register waiting for the other side to read write a data register which is then written read again by the other side 4 4 1 Slave Rabbit As A Protocol UART A prime application for the Rabbit used as a slave is to create a 4 port UART that can also handle the details of a communication protocol The master sends and receives messages over the slave port Error correction retransmission etc can be handled by the slave 48 Rabbit 2000 Microprocessor 5 Pin Assignments and Functions 5 1 Package Schematic and Pin Names 2 5 8 BEBEABRRRESRROZANAAZZ A 4545 5535858555358530253323835 CLKO 800 WE
148. ional open drain Timer A1 Timer B1 Timer B2 PD3 lt q p gt lt p PDO VAN perclk 22 Timer A1 Timer B1 Timer B2 90 Rabbit 2000 Microprocessor Table 25 Parallel Port D Registers Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 E PE7 PD6 PD5 PD4 PD3 PD2 PDI PDO out out out out out out out out cde drain drain drain drain drain drain drain drain 65h X TXA x alt TXB X X X PDDDR W dir dir dir dir dir dir dir dir adr 067h out out out out out out out PDBOR W F 068h x x x X x x x PD0 adr PDBIR W F BSh x x x x x x PDI x adr PDB2R W decak X X X X X PD2 X X adr PDB3R W d O6Bh x x x x PD3 x x x adr PDB4R W X X X PD4 x x x x adr PDBSR W ven x x PD5 X X X X X adr PDB6R W 4 6 X PD6 X X X X x x adr PDB7R W F PD7 X X X X X X X adr Table 26 Parallel Port D Control Register 064h Bits 7 6 Bits 5 4 Bits 3 2 Bits 1 0 00 clock upper nibble on pclk 2 01 clock on timer A1 10 clock on timer B1 11 clock on timer B2 gt lt 00 clock lower nibble on pclk 2 01 clock on timer A1 10 clock on timer B1 11 1 on timer B2 User s Manual 9 5 Parall
149. irection register bits are set for the desired output positions In addition the parallel port E function register must be set to 1 for each position User s Manual 95 96 Rabbit 2000 Microprocessor 11 Timers There are two timers Timer A and Timer B Timer A is intended mainly for generating the baud clock for the serial ports a periodic clock for clocking parallel ports D and E or for generating periodic interrupts Timer B can be used for the same functions but it is more flexible because the program can read the time from a continuously running counter and events can be programmed to occur at a specified future time Figure 27 shows a block diagram of Timers A and B gt Al perclk 2 2 AS Timer A System AT 10 bit counter 1 8 compare 10 bits gt Timer B Svstem match reg Timer B1 next match Timer B2 match reg next match Figure 27 Block Diagram of Timers A and B User s Manual 97 11 1 Timer A Timer A consists of five separate countdown timers A1 and 4 7 shown in Figure 27 Timers Al and A4 A7 are 8 bit countdown registers as shown in Figure 28 The reload register can conta
150. ished to make it feasible for the embedded systems programmer to have extremely fast interrupts available nterrupt latency refers to the time required for an interrupt to take place after it has been requested Generally in terrupts of the same priority are disabled when an interrupt service routine is entered Sometimes interrupts must stay disabled until the interrupt service routine is completed other times the interrupts can be re enabled once the interrupt service routine has at least 38 Rabbit 2000 Microprocessor disabled its own cause of interrupt In anv case if several interrupt routines are operating at the same prioritv this introduces interrupt latencv while the next routine is waiting for the previous routine to allow more interrupts to take place If a number of devices have in terrupt service routines and all interrupts are of the same priority then pending interrupts can not take place until at least the interrupt service routine in progress is finished or at least until it changes the interrupt priority As a rule of thumb Z World usually suggests that 100 us be allowed for interrupt latency on Z180 based controllers This can result if for example there are five active interrupt routines and each turns off the interrupts for at most 20 us The intention in the Rabbit is that most interrupting devices will use priority 1 level inter rupts Devices that need extremely fast response to interrupts will use priority level
151. ister enables the interrupt enables the interrupt User s Manual 101 The control register for Timer B TBCR is laid out as shown in Table 35 Table 35 Timer B Control Register TBCR Bits 7 4 Bits 3 2 Bits 1 0 Not used 00 Counter clocked by perclk 2 00 Interrupt disabled 01 Counter clocked by output of timer Al xx Interrupt priority xx enabled 1x Timer clocked by perclk 2 divided by 8 The MSB x registers for Timer B TBM1R TBM2R are laid out as shown in Table 36 Table 36 Timer B MSB x Register TBM1R TBM2R 0B2h 0B4h Bits 7 6 Bits 5 0 Two most significant bits of timer Not used match preload register 11 2 1 Using Timer B Normally the prescaler is set to divide perclk 2 by a number that provides a counting rate appropriate to the problem For example if the clock is 22 1184 MHz then perclk 2 is 11 0592 MHz If the prescaler is loaded with 127 it will divide the input clock by 128 and the counting rate will be 86 4 kHz which will cause a complete cycle of the 10 bit clock in 11 85 ms Each count will take 11 57 us Normally an interrupt will occur when either of the comparators in Timer B generates a pulse The interrupt routine must detect which comparator is responsible for the interrupt and dispatch the interrupt to a service routine The service routine sets up the next match value which will become the match value after the next interrupt If the cl
152. it follows that bit 12 5 Clocked Serial Ports Ports A and B can operate in clocked mode The data line and clock line are driven as shown in Figure 32 The data and clock are provided as 8 bit bursts The transmit shift register advances on the falling edge of the clock The receiver samples the data on the rising edge of the clock Clocked serial communication is half duplex A clocked serial port can transmit or receive but not both at the same time The serial port can generate the clock or the clock can be provided externally To enable the clocked serial mode a code must be in bits 3 2 of the control register en abling the clocked serial mode with either an internal clock or an external clock The tran sition between the external and the internal clock should be performed with care Normally a pullup resistor is needed on the clock line to prevent spurious clocks while neither party is driving the clock In clocked serial mode the shift register and the data register work in the same fashion as for asynchronous communications However to initiate sending or receiving a code must be stored in bits 7 6 of the control register for each byte sent or received One code spec ifies sending a byte a different code specifies receiving a byte The effect of these codes is different depending on whether the mode is internal clock or external clock 110 Rabbit 2000 Microprocessor Serial Port Input Clock inn imm 8
153. itten agreement regarding such intended use is entered into between the customer and Rabbit Semiconductor prior to use Life support devices or svstems are devices or svstems intended for surgical impantation into the bodv or to sustain life and whose failure to perform when properlv used in accor dance with instructions for use provided in the labeling and user s manual can be reason ably expected to result in significant injury No complex software or hardware system is perfect Bugs are always present in a system of any size In order to prevent danger to life or property it is there responsibility of the system designer to incorporate redundant protective mechanisms appropriate to the risk involved User s Manual 171
154. ken to make sure that a crash will not result in accidently hitting the watchdog 17 3 3 Power Management Support The power consumption and speed of operation can be throttled up and down with rough synchronism This is done by changing the clock speed clock doubler and memory wait states The range of control is quite wide 16 1 or more In addition the main clock can be switched to the 32 768 kHz clock In this case the slowdown is very dramatic perhaps 500 1 Each clock takes about 30 us and a typical instruction takes 150 us to execute At this slow speed the periodic interrupt cannot still operate because the interrupt routine would execute too slowly to keep up with an interrupt every 16 clocks Only about 3 in structions could be executed between ticks A different set of rules applies in the ultra slow mode The user will set up an endless loop to determine when to exit the ultra slow mode The user should include a call in this loop to a polling routine that is a part of the BIOS The polling routine will update the memory counters and the watchdog each time it is called It will do this by directly reading the real time clock and by catching up the memory counters If the user s routine cannot get around the loop in the maximum watchdog timer timeout time the user should put several calls to the polling routine in the loop The user should avoid indiscriminate direct access to the watchdog timer and real time clock The least bits of
155. l port 97 98 B bits 4 and 5 Chip select for slave port active low An Slave Port SCS Input alternate pin assignment for parallel port E 21 bit 7 I O strobes Each strobe uses 1 8th of the I O space or 8K addresses Each strobe can be 12 programmed as chip select read write I O Strobes 14 I5 Outputs combined read or write These are alternate 21 26 29 30 16 17 pin assignment for parallel port E bits 0 7 Each pin may be individually re assigned from parallel port to strobe functionality 56 Rabbit 2000 Microprocessor Table 3 Rabbit Pin Assignments External INTOA INTIA Interrupt 0 Inputs These pins are sampled and an interrupt request for external interrupt number 0 is latched on a specified transition pos neg either There is a separate latch for each pin Mav be enabled when this pin is set up as input for parallel port E The value of the pin mav also be read via the parallel port Uses bits 0 1 of the parallel port If parallel port is set up as output the parallel port output may be used to cause the interrupt 29 30 External INTOB INTIB Interrupt 1 Inputs These pins are sampled and an interrupt request for external interrupt number 0 is latched on a specified transition pos neg either There is a separate latch for each pin Mav be enabled when this pin is set up as input for parallel port E The value of the pin mav also be read via the para
156. l reduce the current consumption by a substan tial amount when a 3 V lithium battery is used Using this circuit the battery backed clock User s Manual 127 will require less than 25 u A If the full 3 V is used the current consumption will be ap proximately 70 u A R2 390 XTALA2 XTALB2 R2 9 CI O zo RI 15 pF etis 215 10 MQ as RI T 32 768 kHz 13 1MQ NE x E O C2 XTALA1 15 pF E XTALBI a3 pe L 32 768 kHz Circuit Main Oscillator Safetv resistor required bv 1 regulatory agencies BAT 3 0 V 220 2 k Batterv Regulator 2 2 3 V batterv backup power Sea iG NU Figure 37 Oscillator Circuits 14 7 Low Power Design The power consumption is proportional to the clock frequency and to the square of the op erating voltage Thus operating at 3 3 V instead of 5 V will reduce the power consump tion by a factor of 10 9 25 or 43 of the power required at 5 V The clock speed is reduced proportionally to the voltage at the lower operating voltage Thus the clock speed at 3 3 V will be about 2 3 of the clock speed at 5 V The operating current is reduced in proportion to operating voltage The Rabbit does not have a standby mode that some microprocessors have Instead the Rabbit has the ability to switch its clock to the 32 768 kHz oscillator This is called the sleepy mode When this is done the power
157. lemented by an array of memory counters The counters are counted down 16 times per second by the periodic interrupt routine Hit ting a virtual watchdog is performed by calling a routine that stores a count between 1 and 255 in the memory counter Virtual watchdogs may be allocated disallocated enabled and disabled One virtual watchdog is implemented by default and it is hit in the periodic inter rupt routine If the periodic interrupt stops working then the watchdog will time out The advantage of the virtual watchdogs is that if any of them fail and error is detected Directly hitting the hardware watchdog will cause an error only if every place where the watchdog is hit fails to be included in the crash loop 16 4 1 The Watchdog Hardware The Rabbit microprocessor has a hardware watchdog timer The watchdog is hit by calling a bios routine hitwd which hits it for 2 seconds or by storing a special code in the WDTCR register the code determining the time delay The watchdog is a 17 bit counter that counts toward zero at 32768 Hz provided by the 32 768 kHz oscillator A hit stores a number in the counter postponing the time when it will reach zero If hits are not frequent enought the counter will reach zero and perform a microprocessor reset Best practice requires that extreme care be taken before the program hits the watchdog If hits of the watchdog are scattered in a reckless manner througout the user s program then there is a good chanc
158. llel port Uses bits 4 5 of the parallel port If parallel port is set up as output the parallel port output mav be used to cause the interrupt 23 24 User s Manual 57 5 4 Bus Timing The external bus has essentially the same timing for memory cycles or I O cycles A memory cycle begins with the chip select and the address lines One clock later the out put enable is asserted for a read The output data and the write enable are asserted for a write TI Tw T2 x X valid X a T Notes Read mav have no wait states Address 20 for memory 16 for I O IOCSn or CSn inn OEn or IORD and BUFEN BUFEN rd wr Data for read Data for write 3 s drive starts at end of T1 WEn or Write cycles and I O read cycles have at least 1 wait state Clock may be asymmetric if clock doubler used I O chip select avail able on port E as option Figure 16 Bus Timing Read and Write 58 Rabbit 2000 Microprocessor 5 5 Description of Pins with Alternate Functions Table 4 Pins With Alternate Functions Pin Name Output Function Input Function Other Function STATUS 38 1 Low on first op code fetch 2 Low on interrupt acknowledge Programmable output port high low SMODEI 35 SMODEI SMODE2 Startup boot mode control l bit input after boot complete SMODEI SMODE2
159. lock If the clock is not batterv backed the seconds since 1980 counter is set to zero thus measuring time since startup A log of startup times and conditions is a debugging aid The time of exiting reset is recorded as well as the reason for the reset is kept in what or not be batterv backed memorv 17 3 2 Watchdog Timer Support In a well organized system the periodic interrupt should be the only place where instruc tions to hit the watchdog timer are located This is accomplished by setting up a number of virtual watchdog timers Each virtual watchdog is an 8 bit counter that is counted down 16 times per second or every 128 ticks of the real time clock If any counter reaches zero the program turns off interrupts and freezes until the hardware watchdog times out and re sets the processor The user program must hit each virtual watchdog periodically by call ing a routine with the number of the watchdog and count value to be stored The number of virtual watchdogs is itself a parameter that can be increased by a call to get the virtual watchdog routine which adds another watchdog to the list not a linked list up to the maximum number in the array Initially there is one virtual watchdog that is hit by the pe riodic interrupt itself The virtual watchdogs can be distributed across interrupts to reduce the interrupt execution time if all possible virtual watchdogs must be counted in one inter rupt Precautions are ta
160. m pled at the middle of each data bit and are shifted into the receive shift register After 7 or 8 data bits have been received the next bit will be either a 9th 8th address bit or a stop bit will be sampled If the RX line is low it is an address bit and the address bit received bit in the status register will be enabled If an address bit is detected the receiver will at tempt to sample the stop bit If the line is high when sampled it is a stop bit a new scan for a new start bit will begin after the sample point At the same time the data bits are transferred into the receive data register and an interrupt if enabled is requested On receive an interrupt is requested when the receiver data register has data This happens when data bits are transferred from the receive shift register to the data register This also sets bit 7 of the status register The interrupt request and bit 7 are cleared when the data register is read An interrupt is requested if bit 7 is high The interrupt is requested on the edge of the transmitter data register becoming empty or the transmitter shift register becoming empty The transmitter interrupt is cleared by writing to the status register or to the data register On receive the scan for the next start bit starts immediately after the stop bit is detected The stop bit is normally detected at a sample clock that nominally occurs in the center of the stop bit If there is a 9th 8th address bit the stop b
161. me relative to the clock Tsetup is specified from the 3096 7096 of the VDD voltage level Most 5 V memories have TTL compatible inputs that switch at 0 8 V and 2 0 V Approximately 2 ns must be added for a 20 pF bus loading in order to pull a low level of 0 8 V instead of 2 5 V User s Manual 135 TI Twaitl T2 T3 Memorv Read 0 19 CS gt lq Tadr KDO D7 gt Tadr 8 ns 20 pF Tsetup JOE Tsetup 4 ns measured from 3090 7090 level l XK A0 A19 CS Tadr Memory Write D0 D7 3 state K WE Tcl p gt Figure 39 Read Write with Wait States Generallv the maximum operating speed is proportional to the power supplv voltage The operating current is proportional to the voltage and so the operating power is proportional to the square of the voltage The operating power is also proportional to the clock speed Higher temperatures reduce the maximum operating speed by approximately 1 for each 5 In addition higher operating speeds increase the die temperature because of the heat generated and therefore slightly compound the adverse effects of higher temperature The Rabbit operates at 2 clocks per bus cycle plus any wait states that might be specified I O bus cycles have an automatic wait state and thus require 3 clocks plus any wait states spec ified as show
162. me the shift register finishes sending data leaving the data register emptv This causes an interrupt request The interrupt routine normallv an swers the interrupt before the shift register runs drv 9 to 11 clocks depending on the mode of operation The interrupt routine stores the next data item in the data register clearing the interrupt request and supplving the next data bits to be sent When all the characters have been sent the interrupt service routine answers the interrupt once the data register becomes emptv Since it has no more data it clears the interrupt request bv stor ing to the status register At this point the routine should check if the shift register is empty normally it won t be If it is because the interrupt was answered late the interrupt routine should do any final cleanup and store to the status register again in case the shift register became empty after the pending interrupt is cleared Normally though the inter rupt service routine will return and there will be a final interrupt to give the routine a chance to disable the output buffers as in the case for RS 485 transmission User s Manual 109 12 4 Receive Serial Data Timing When the receiver is readv to receive data a falling edge indicates that a start bit must be detected The falling edge is detected as a different Rx input between two different clocks the clock being 16x the baud rate Once the start bit has been detected data bits are sa
163. mory is an unprogrammed or improperly programmed flash memory there is a danger that the memory could be de stroyed if the write security feature of the flash memory is disabled Flash memories have a write security feature that inhibits starting write cycles unless a special code is first stored to the memory For example Atmel flash memories use the bytes AAh 55h and AOh stored to addresses AAAAh or 5555h in a particular sequence Any write executed that is not prefixed by this sequence will be ignored If the memory has write protection disabled and execution starts it is possible that an endless loop that includes a write to memory will establish itself Since the flash memory wears out after a few hundred thou sand writes the memory could be damaged in a short period of time by such a loop Un User s Manual 129 fortunatelv flash memorv is shipped from the factorv with the protection feature disabled to accomodate obsolete memorv programmers The solution to this problem is to order the memorv with the write protection enabled or to enable it with a flash programming svstem Then the memorv will be safe if it is sol dered into the Rabbit svstem If an unsafe memorv is soldered into a svstem then the memory can be powered up with the programming cable connected and a sequence can be sent using the cold boot procedure to enable the write protection Compiling any Dy namic C program to the flash will make the memory safe If this is
164. n a Rabbit microprocessor is configured as a slave parallel port A and certain other data lines are used as communication lines between the slave and the master The slave unit is a Rabbit configured as a slave The master can be another Rabbit or anv other tvpe of processor Rabbits configured as slaves can themselves have slaves The master and slave communicate with each other via the slave port The slave portis a phvsical device that includes data registers a data bus and various handshaking lines The slave port is a part of the slave Rabbit but logically it is an independent device that is used to communicate between the two processors A diagram of the slave port is shown in Figure 33 SPSR SPD2R 98 SAI 1 97 SAD Y 95 gt _21 SCS CPU 100 SLAVEATTN 81 88 lt gt 500 507 Y l4 p Figure 33 Rabbit Slave Port The slave port has three data registers for each direction of communication Three regis ters named SPDOR SPDIR and SPD2R can be written by the master and read by the slave Three different registers also named SPDOR SPDIR and SPD2R can be written by the master and read by the slave The same names are used for different registers since it is usually clear from the context which register is meant If it is necessary to distinguish
165. n in Figure 40 136 Rabbit 2000 Microprocessor TI Twaitl T2 T3 Memorv Read 1 xX A0 A15 OCS X Tadr K DO D7 Tadr 8 ns 20 pF q Tsetup JORD BUFEN Tsetup 4 ns measured from 3090 7090 level 0 15 IOCS b Tadr Memory Write D0 D7 3 state Tcl gt 4 IOWR BUFEN is default program for this pin Figure 40 I O Read and Write Cycles No Extra Wait States 15 1 Current Consumption Typical current is proportional to both clock frequency and voltage The main oscillator requires approximately 6 mA at 5V and 2 mA at 3 volts independent of frequency The ba sic current consumption for the processor exclusive of the oscillator at 5 V and 15 MHz is approximately 42 mA The following formula can be used to compute the current con sumption I 0 7 freq MHz voltage 1 27 voltage 2 7 1 3 The first term represents the power consumed by the processor The second term is the current consumed by the main oscillator If the main oscillator is disabled then this termis zero Some checkpoints for current consumption are below User s Manual 137 Figure 41 Current Versus Frequencv and Voltage Frequencv MHz Voltage Current mA 29 4912 5 107 22 0592 5 82 14 7456 5 56 14 7456 3 3 36 7 3728 3 3 19 3 6864 3 3 11 1 8432 3 3 6 9216 3 3
166. n the rising edge of the last clock pulse If the next receive code is stored before the natural location of the next falling edge an other receive will be initiated without pausing the clock To do this the interrupt has to be serviced within 1 2 clock User s Manual 111 To transmit each byte in external clock mode the user must load the data register and then store the send code When the shift register is idle and the receiver provides a clock burst the data bits are transferred to the shift register and are shifted out Once the transfer is made to the shift register a new byte can be loaded into the transmit register and a new send code can be stored To receive a byte in external clock mode the user must set the receive code for the first byte and then store the receive code for the next byte after each byte is removed from the data register Since the receive code must be stored before the transmitter sends the next byte the receiver must service the interrupt within 1 2 baud clock to maintain full speed transmission This is usually not practical unless a flow control arrangement is made or the transmitter inserts gaps between the clock bursts In order to carry on high speed communication the best arrangement will usually be for the receiver to provide the clock When the receiver provides the clock the transmitter should always be able to keep up because it is double buffered and has a full character time to answer the transmi
167. nd data Allocation normallv con tinues to the end of the flash memorv Data variables are allocated to RAM working backwards in memorv Allocation normallv starts at 52K in the 64K D space and continues The 52K space must be shared with the root code and data and is allocated upward from zero Dynamic C also supports extended data constants These are mixed in with the extended code in flash 8 5 How the Compiler Compiles to Memory The compiler actually generates code for root code and constants and extended code and extended constants It allocates space for data variables but does not generate data bits to be stored in memory In any but the smallest programs most of the code is compiled to extended memory This code executes in the 8K window from E000 to FFFF This 8K window uses paged access Instructions that use 16 bit addressing can jump within the page and also outside of the page to the remainder of the 64K space Special instructions particularly long call long jump and long return are used to access code outside of the 8K window When one of these transfer of control instructions is executed both the address and the view through the 8K window or page are changed This allows transfer to any instruction in the IM mem ory space The 8 bit XPC register controls which of the 256 4K pages the 8K window aligns with The 16 bit PC controls the address of the instruction usually in the region E000 to FFFF The advantage of paged ac
168. nerally be loaded to any register except PC AF IP and F Load to the PC is a jump instruction This in cludes the alternate registers on the Rabbit but not on the Z180 Some example instruc tions appear below 14 a 3 14 h1 456 ld bc 3567 not possible on 2180 ld h 4Ah not possible on Z180 ld ix 1234 14 c 54 Byte loads require four clocks word loads require six clocks Loads to IX IY or the alter nate registers generally require two extra clocks because the op code has a 1 byte prefix 3 3 2 Instructions to Load or Store Data from or to a Constant Address ld a mn loads 8 bits from address mn ld a mn not possible on Z180 ld mn a ld hl mn load 16 bits from the address specified by mn ld hl mn to alternate register not possible 2180 14 mn hl Similar 16 bit loads and stores exist for DE BC SP IX and IY User s Manual 27 It is possible to load data to the alternate registers but it is not possible to store and alter nate register directly to memory a mn allowed 1 mn a not a legal instruction 1 mn de not a legal instruction 3 3 3 Instructions to Load or Store Data Using an Index Register An index register is a 16 bit register usually IX IY SP or HL that is used for the address of a byte or word to be fetched from or stored to memory Sometimes an 8 bit offset is added to the address either as a signed or unsigned number The 8 bit offset
169. ns are also privileged 1 ld xpc a bit b hi 3 5 5 Semaphores Using Bit B HL The bit B HL instruction is privileged to allow the construction of a semaphore by the following code bit b hl test a bit in the byte at hl set b hl make sure bit set does not affect flag if zero flag set the semaphore belongs to us otherwise someone else has it User s Manual 41 A semaphore is used to gain control of a resource that can only belong to one task or pro gram at a time This is done by testing a bit to see if it is on in which case someone else is using the resource otherwise setting the bit to indicate ownership of the resource No in terrupt can be allowed between the test of the bit and the setting of the bit as this might al low two different program to both think they own the resource 3 5 6 Computed Long Calls and Jumps The instruction to set the XPC is privileged to so that a computed long call or jump can be made This would be done by the following sequence ld xpc a jp hl In this case A has the new XPC and HL has the new PC This code should normally be executed in the root segment so as not to pull the memory out from under the JP HL in struction A call to a computed address can be performed by the following code IY address ld a newxpc ld iy newaddress lcall docall call utility routine in the root The docall routine docall ld xpc a set xpc
170. ns of Parallel Ports B and E are used for the Slave Port control signals Only Slave Port Data Register 0 is used for bootstrap operation and any writes to the other data registers will be ignored by the processor and can actually interfere with the bootstrap operation by mask ing the Write Empty signal GW See Section 14 8 2 on page 129 for an example of using the bootstrap mode User s Manual 79 Serial Port A is selected for bootstrap operation as a clocked serial port when SMODE 10 In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel Port B is used for the serial clock Note that the serial clock must be externallv supplied for bootstrap operation This precludes the use of a serial EEPROM for bootstrap operation Serial Port A is selected for bootstrap operation as an asvnchronous serial port when SMODE 11 In this case bit 7 of Parallel Port is used for the serial data and the 32 kHz oscillator is used to provide the serial clock A dedicated divide circuit allows the use of the 32 KHz signal to provide the timing reference for the 2400 bps asynchronous transfer Only 2400 bps is supported for bootstrap operation and the serial data must be eight bits for proper operation When a bootstrap is performed using Serial Port A the TXA signal is not needed since the bootstrap is a one way communication After the reset ends and the bootstrap mode be gins TXA will be low reflecting its function
171. nstructions Test if hl de hl and de unsigned numbers 0 65535 a clear carry sbc hl de if C 0 then hl gt de else if C 1 then hl de convert the carry bit into a boolean variable in hl sbc hl hl sets hl 0 if 0 sets hl Offffh if C bool hi 11 41 if C was set otherwise 1 convert not carry bit into boolean variable in hl sbc hl hl hl 0 if C 0 else hl ffff if C 1 inc hl hl 1 if C 0 else hl 0 if C note carry flag set but zero sign flags reversed In order to compare signed numbers using the sbc instruction the programmer can map the numbers into an equivalent set of unsigned numbers by inverting the sign bit of each number before performing the comparision This maps the most negative number 08000h to the smallest unsigned number 0000h and the most positive signed number 07FFFh to the largest unsigned numbeer OFFFFh Once the numbers have been converted the com User s Manual 31 parision can be done as for unsigned numbers This procedure is faster than using a jump tree that requires testing the sign and overflow bits example test for hl de where hl and de are signed numbers invert sign bits on both add hl hl shift left ccf invert carry rr hl rotate right rl de rr de invert de sign sbc hl de no carry if hl de generate boolean variable true if hl de sbc hl hl zero if no carry else 1 inc hl 1 if no carry else zero bool use this
172. nt boundaries is determined by a 4 bit value that specifies the upper four bits of the address where the boundary is located These relationships are illustrated in Figure 7 The names given to the segments in the figure are evocative of the common uses for each segment The root segment is mapped to the base of flash memory and contains the star tup code as well as other code that may happen to be stored there The data segment usage varies depending on the overall strategy for setting up memory It may be an extension of the root segment or it may contain data variables The stack segment is normally 4K long and it holds the system stack The XPC segment is normally used to execute code that is not stored in the root segment or the data segment Special instructions support executing code that is visible in the XPC segment User s Manual 21 10000 85 XPC register 0 000 80 STACKSEG register 830007 79 DATASEG register a 0D000 80 8D000 10000 XPC Ul segment E000 stack segment D000 data segment D 7 SEGSIZE register 07000 79 7000 root segment 07000 0000 16 bit address space 00000 20 bit address space Figure 7 Example of Memory Mapping Operation 22 Rabbit 2000 Microprocessor The memory interface unit receives the 20 bit addresses generated by the memory map ping unit The memory interface unit conditionally modifies address lines A16 A1
173. nterrupt takes place This avoids the possibilitv of an ever growing stack reti pops IP from stack and then pops return address The instruction reti can be used to set both the return address and the ip in a single in struction If preceded by a 1d xpc a complete jump or call to a computed address can be done with no possible interrupt ld a xpc get and set the xpc ld xpc a The instruction 14 xpc a is privileged so that it can be followed by other code setting in terrupt priority or program counter without an intervening interrupt bit b 11 test a bit in memory The instruction bit b h1 is privileged to make it possible to implement a semaphore without disabling interrupts The following sequence is used A bit is a semaphore and the first task to set the bit owns the semaphore and has a right to manipulate the resources associated with the semaphore bit b hl set b hi jp z ihaveit here I don t have it The set instruction has no effect on the flags Since no interrupt takes place after the bit instruction if the flag is zero that means that the semaphore was not set when tested bv the bit instruction and that the set instruction has set the semaphore If an interrupt was lowed between the bit and set instructions another routine could set the semaphore and two routines could think that they both owned the semaphore 158 Rabbit 2000 Microprocessor 19 Differences Rabbit vs Z80 Z180 Instructions
174. o generate a periodic interrupt by continuously transmitting characters Since the TX output via parallel port C or D can be disabled the transmitted characters are transmitted to nowhere Because the character output path is double buff ered there will be no gaps in the character transmission and the interrupts will be exactly periodic The interrupts can happen every 9 10 or 11 baud times depending on whether 7 8 bits are transmitted and on whether the 9th 8th bit is sent 12 6 5 Working With Two Stop Bits or a Parity Bit In the 8 bit data mode the serial ports do not directly support transmitting more than one stop bit If it is desired to send more than one stop bit it is necessary to delay the trans mission of the next character for at least 1 baud time If only 7 data bits are being sent the problem is easily solved by sending 8 bits and always setting bit 7 of the byte to a 1 if an extra stop bit is desired or setting it to the parity value if a parity bitis desired No special precautions are needed if two stop bits are to be received If parity is received with 7 data bits receive the data as 8 bits and the parity will be in the high bit of the byte The scenario is more complicated when 8 data bits are used If a parity bit is to be re ceived it will appear as an address or 9th bit if a zero is transmitted for the parity bit Oth erwise the parity bit appears as an additional stop bit and the 9th bit is not detected T
175. ocked parallel ports are being used then a value will normally be loaded into some bits of the parallel port register These bits will become the output bits on the next match pulse It is neces sary to keep a shadow register for the parallel port unless the bit addressable feature of ports D and E is used If it is desired to read the time from the Timer B counter either during an interrupt caused by the match pulse or in some other interrupt routine asynchronous to the match pulse a special procedure needs to be used to read the counter because the upper 2 bits are in a dif ferent register than the lower 8 bits The following method is suggested 1 Read the lower 8 bits 2 Read the upper 2 bits 3 Read the lower 8 bits again 4 If bit 7 changed from 1 to 0 between the first and second read of the lower 8 bits there has been a carry to the upper 2 bits In this case read the upper 2 bits again and decre ment those 2 bits to get the correct upper 2 bits Use the first read of the lower 8 bits 102 Rabbit 2000 Microprocessor This procedure assumes that the time between reads can be guaranteed to be less than 256 counts This can be guaranteed in most systems by disabling the priority 1 interrupts which will normally be disabled in any case in an interrupt routine It is inadvisable to disable the high priority interrupts levels 2 and 3 as that defeats their purpose If speed is critical the three reads of the registers can
176. ol is another way to detect the start of a data frame The Modbus protocol requires that data frames begin with a minimum 3 5 character quiet time The receiver uses this 3 5 character gap to detect the start of a frame In order for User s Manual 115 the receiving ISR to detect this gap it is suggested that dummv characters be transmitted to aid in detecting the gap This can be done in the following manner The transmitter starts transmitting dummv characters when the first character interrupt is received Each time there is an interrupt either receiver data register full or transmitter data register emptv a dummv character is transmitted if the transmitter data register is emptv Al though the transmitter and receiver operate at approximatelv the same baud rate there can be a difference of up to about 5 between their baud rates Thus the receiver full and transmitter empty interrupts will become out of phase with each other assuming that the remote station transmits without gaps between characters A counter is zeroed each time a character is received and the counter is incremented each time a character is transmitted If this counter holds n this indicates that a gap has been detected in the frame the length of the gap is n 1 to n characters The start of frame could be marked by n reaching 3 indicating that the existence of a gap at least two characters long 116 Rabbit 2000 Microprocessor 13 Rabbit Slave Port Whe
177. ore 20 bit Address essere enne 150 18 6 Register to Register Moves a anh n rennen entente 151 18 7 Exchan e Instructions et a ko cete 151 18 8 Stack Manipulation Instructions entren nennen 152 18 9 16 bit Arithmetic and Logical Operations n usss 152 18 10 8 bit Arithmetic and Logical Operations sss 153 18 11 8 bit Bit Set Reset and Test Instructions nennen enne 154 18 12 8 bit Increment and Decrement eene eene nente nein nne nene 154 18 13 8 bit Fast A register Operations nn ennennnnennn nr nsa nr eren rennen 154 18 14 8 bit Shifts and Rotates ss Dn n 155 18 15 Instr ction Prefixes uenti eret pr a PTS 156 18 16 Block Move Instructions L W tenens 156 18 17 Control Instructions Jumps and Calls n nassisti 156 18 18 Miscellaneous Instructions eene eene nennen neret nenne entren nns 157 18 19 Privileged Instructions cec eite cete het etel de eee ere redeo 157 19 Differences Rabbit vs Z80 Z180 Instructions 159 20 Instructions in Alphabetical Order With Binary Encoding 161 Appendi AS EM N A 167 A 1 Rabbit Programming Port teen nete nete en
178. p hederae iem dede 88 9 4 Parallel tetti edi ehe edo 89 9 5 Parallel Port Ez eue S E Saa HI MH 92 Bank Control Registers essi cio ent ee inen o nesses rV eii 95 Rabbit 2000 Microprocessor 11 BETE 97 11 1 A B p a E E E E dt bute u hayak 98 ILLI Timer AVO Registers eene Dee eee iie 99 11 11 22 Practical Use of Timer A un tpe ee HERR etel 100 11 2 Timer m LP ES 101 11 2 1 Using mer Bis uui ee tei ed ett ee 102 I2 Rabbit Serial set n ted sud ese acci tq ense oo ev oet 9 105 12 1 Register Layout Serial Port amas enne eere 105 12 2 Serial Port l ebda hd Sadok ud dg 108 12 3 Transmit Serial Data Timing iere eee tiere eter eire riis 109 12 4 Receive Serial Data Timing eese eee entente 110 12 5 Clocked Serial eere trao iege quine imei velot 110 12 6 Serial Port Software Suggestions seen nsnsi 112 12 6 1 Controlling an RS 485 Driver and Receiver see 114 12 6 2 Transmitting Dummy Characters nee ern ern 114 12 6 3 Transmitting and Detecting a Break 114 12 6 4 Using A Serial Port to Generate a Periodic Interrupt semm 115 12 65 Working With Two Stop Bits or a Parity Bit sese 115 12 6 6 Data Framing Modbus sees eren enne 115 I3 Rabbit Slave saa asahan haah noire iii des dera tea 117 13
179. permuted as a group Address lines A7 and A8 should not be permuted at all if it is desirable to keep the larger sectors contiguous The upper 10 address lines can be permuted as a separate group The special memory chip addresses 05555h and must be accessed as part of the unlock sequence These addresses use only the first 16 address lines and have the odd and even numbered bits the same The unlock codes use the numbers 55h AAh or AOh User s Manual 131 Permuting data or address lines with flash memorv should probablv be avoided in practi cal svstems 132 Rabbit 2000 Microprocessor 15 AC Timing Specifications The Rabbit processor mav be operated at voltages between 2 5 V and 6 0 V and at temper atures from 40 C to 85 C Most users will operate the Rabbit at either 5 0 V or 3 3 V The most computation per watt is obtained at approximately 3 3 V The highest practical speed is usually obtained at 5 V or more The Rabbit is available in two versions the R 25 which has a maximum clock speed of 26 0 MHz and the R 30 which has a maximum clock speed of 29 5 MHz The R 30 has a maximum clock speed at 3 3 V 41096 of 18 9 MHz and the R 25 has a maximum clock speed of 16 25 MHz at 3 3 V The maximum clock speed at 2 5 V is 8 25 MHz for either the R 25 or R 30 If a half speed crystal is used with the clock doubler to achieve the desired clock speed the maximum clock speed must be reduced by 109 to allow for an
180. phone 530 757 8400 Facsimile 530 757 8402 Web site http www rabbitsemiconductor com Rabbit 2000 Microprocessor Table of Contents 1 PIERO CMC ELON ics ES 7 1 1 Features and SpecifiCatiObs u u ie iei cit tee 7 1 2 Summary of Rabbit Advantages nnnnnnnenzznnznnezznzznnznnnznznnnnn nr eren nennen nenne 11 2 Rabbit Design F eat rf S aaa qaqta aqhaqa est a 13 2 1 The Rabbit 8 bit Processor vs 16 bit and 32 bit Processors 13 2 2 Overview of On Chip Peripherals siisii nee ennenen ness ns sas ener 14 2 2 4 Serial Ports i a E 14 2 2 2 System Clock ote g E reo 14 2 2 3 Time Date Oscillator iR EUER A eee 15 22 4 Parallel VO t emot 15 2 25 Slave Pott zit ER DIU EPIS QNEM 15 2 2 6 mers eee PERDRE UD 16 2 3 Design Standards aa tio etc tete bete tite Gi Aer a 18 2 3 Programming Port isses eec pee tee ete beds 18 2 3 2 Standard BIOS ei Sau SDN 18 2 4 Dynamic C Software Support for the Rabbit sse 18 3 Details on Rabbit Microprocessor Features esses 19 3 1 Processor Registers teta tee ee eR iste 19 3 2 Memory Mapping iere ERE IU a bounds eese uns need ee b bens 20 32 Ext nded Code Space sone a p e ee ae 24 3 2 2 Practical Memory Considerations eee 25 3 3 Instruction Set Outline wy enit Ire erede Erie ehe
181. pleted before the reset sequence completes and the clocks switch to divide by eight mode During reset all of the memory control signals are held inactive After the RESET signal is inactive high the processor begins fetching instructions and the memory control sig nals begin normal operation Note that the default values in the Memory Bank Control registers select four wait states per access so the initial program fetch memory reads are 48 clock cycles long 8 x 2 4 Software can immediately adjust the processor timing to whatever the system requires The default selection for the memory control signals consists of CSO OEO and WEQ and writes are enabled This selection can also be immediately programmed to match the hardware configuration A typical sequence would be to speed up the clock to full speed then select the appropriate number of wait states and the chip select signals output enable signals and write enable signals At this point software would usually check the system status to determine what type of reset just occurred and begin normal operation 7 8 Rabbit Interrupt Structure An interrupt causes a call to be executed pushing the PC on the stack and starting to exe cute code at the interrupt vector address The interrupt vector addresses have a fixed lower byte value for all interrupts The upper byte is adjustable by setting the registers EIR and IIR for external and internal interrupts respectively There are only
182. port control register To make the port output store 084h in SPCR Upon reset port A is set up as an input port When the port is read the value read reflects the voltages on the pins 1 for high and 0 for low This could be different than the value stored in the output register if the pin is forced to a different state by an external voltage User s Manual 87 9 2 Parallel Port B Parallel Port B shown in Table 23 has six inputs and two outputs when used exclusivelv as a parallel port Table 23 Parallel Port B Data Register PBDR adr 040h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read PBSin PB4in PB3in PB2in PBlin PBOin drive drive Write PB7 PB6 x x x x x x When the slave port is enabled parallel port lines PB2 PB7 are assigned to various slave port functions However it is still possible to read 5 using the Port B data register even when lines PB2 PB7 are used for the slave port It is also possible to read the signal driving PB6 and PB7 this signal is on the signaling lines from the slave port logic Regardless of whether the slave port is enabled PBO reflects the input of the pin unless se rial port B has its internal clock enabled which causes this line to be driven by the serial port clock PBI reflects the input of the pin unless serial port A has its internal clock en abled On reset the output bits 6 and 7 are reset and th
183. pt The main oscillator can be shut down in a special low power mode of operation and the 32 768 kHz oscillator is then used to clock all the things normally clocked by the main oscillator This results in slower execution at low power 200 uA The on chip routing of the clocks is shown in Figure 17 The main oscillator can be dou bled in frequency and or divided by 8 If both doubling and dividing are enabled then there will be a net division by 4 The CPU clock can optionally by divided by 2 and then optionally drive the external pin CLK In many cases the clock is not needed externally and in that case CLK can be used as a general purpose output pin The divide by 2 option is available to minimize electromagnetic radiation if the is clock is driven off chip forf 2 ext pin _ disable f 2 p CLK Main O lock t 8 et Doubler CPU 32 kHz Peripheral Osc Devices To Watchdog Timer and Time Date Clock Note Peripherals cannot be clocked slower than CPU Figure 17 Clock Distribution User s Manual 67 Table 7 Global Control Status Register adr 00h Bit s Value Description 7 6 00 No reset or watchdog timer timeout since the last read read Guy 01 The watchdog timer timed out These bits are cleared by
184. pt asso ciated with that timer will be disabled Serial port interrupts are generated by the serial port logic This will isolate the serial port countdown register from the other countdown registers The value in the reload register can be changed while the timer is running to change the period of the next timer cycle When the reload register is initialized the contents of the countdown counter may be unknown for example during power up initialization If in terrupts are enabled then the first interrupt may take place at an unknown time Similarly if the timer output is being used to drive the clock for a parallel port or serial port the first clock may come at a random time If a periodic clock is desired it is probably not impor tant when the first clock takes place unless a phase relationship is desired relative to a dif ferent timers A phase relationship between two timers can be obtained in several ways One way is to set both reload registers to zero and to wait long enough for both timers to reload maxi mum 256 clocks Then both timers reload registers can be set to new values before or af ter both are clocked 100 Rabbit 2000 Microprocessor 11 2 Timer B Figure 27 on page 97 shows a block diagram of Timer B The Timer B counter can be driven directly by perclk 2 by that clock divided by 8 or by the output of timer A1 Timer B has a continuously running 10 bit counter The counter is compared against two matc
185. quently followed by an instruction to change the stack segment register If an interrupt occurs between these two instructions and the following instruction the stack will be ill defined ld sp hl ioi 1 sseg a 40 Rabbit 2000 Microprocessor The privileged instructions to manipulate the IP register are listed below ip 0 shift ip left and set prioritv 00 in bits 1 0 1 2 3 ipres rotate ip right 2 bits restoring previous prioritv reti Pops IP from stack and then pops return address pop ip pop IP register from stack 3 5 4 Critical Sections Certain library routines may need to disable interrupts during a critical section of code Generally these routines are only legal to call if the processor priority is either O or 1 A priority higher than this implies custom hand coded assembly routines that do not call general purpose libraries The following code can be used to disable priority 1 interrupts ip 1 Save previous priority and set priority to 1 c Critical section ipres restore previous prioritv This code is safe if it is known that the code in the critical section does not have an embed ded critical section If this code is nested there is the danger of overflowing the IP regis ter A different version that can be nested is the following push ip 1 Save previous priority and set priority to 1 c Critical section pop ip restore previous prioritv The following instructio
186. r all 8 bits even when operating at low voltage User s Manual 71 The 48 bits are enough bits to count up 272 vears at the 32 kHz clock frequencv con vention 12 AM on Januarv 1 1980 is taken as time zero Z World software ignores the highest order bit giving the counter a capacitv of 136 vears from Januarv 1 1980 Toread the counter value the value is first transferred to a 6 bvte holding register Then the indi vidual bvtes mav be read from the holding registers To perform the transfer anv data bits are written to RTCOR the first holding register The counter mav then be read as six 8 bit bytes at RTCOR through RTCSR The counter and the 32 kHz oscillator are powered from a separate power pin that can be provided with power while the remainder of the chip is powered down This design makes battery backup possible Since the processor operates on a different clock than the RTC there is the possibility of performing a transfer to the holding registers while a carry is taking place resulting in incorrect information In order to prevent this the processor should do the clock read twice and make sure that the value is the same in both reads If the processor is itself operating at 32 kHz the read clock procedure must be modified since a number of clock counts would take place in the time needed by the slow clocked processor to read the clock An appropriate modification would be to ignore the lower bytes and only read the upper 5
187. r ete eese e peperere s 26 3 3 1 Instructions to Load Immediate Data To a Register 27 3 3 2 Instructions to Load or Store Data from or to a Constant Address 27 3 3 3 Instructions to Load or Store Data Using an Index Register 28 3 3 4 Register to Register Move Instructions eese 29 3 329 Register Exchanges oett eere A cele iei Hc 29 3 3 6 Push and Pop nennen nennen ennt 30 3 3 7 16 bit Arithmetic and Logical Operations sse nee nn 30 3 3 8 Input Output Instructions n 33 3 4 How to Do It in Assembly Language Tips and Tricks ee 33 34 Zero HEA Clocks u ann A a Y 33 3 4 2 Exchanges Not Directly Implemented sese 34 3 4 5 Manipulation of Boolean Variables eere 34 3 44 Conipanisions Of Integers teo eleg eee e per Hed Cer etg 35 3 4 5 Atomic Moves from Memory to I O Space 37 3 5 Interr pt Str ctUre a uu 38 351 Interrupt Priority iiie eee retro EHE haqay 38 3 5 2 Multiple External Interrupting Devices seen 40 3 5 3 Privileged Instructions Critical Sections and Semaphores 40 3 54 2 Critical Sections emer rne iet dol bene ee RR Rede 41 3 5 5 Semaphores Using Bit B HL L ee
188. r nibble on pclk 2 01 clock on timer A1 10 clock on timer B1 11 clock on timer B2 94 Rabbit 2000 Microprocessor 10 I O Bank Control Registers The pins of port E can be individually set to be I O strobes Each of the eight possible I O strobes has a control register that controls the nature of the strobe and the number of wait states that will be inserted in the I O bus cycle Writes can also be suppressed for any of the strobes The types of strobes are shown in Figure 26 Each of the eight I O strobes is active for addresses occupying 1 8th of the 64K external I O address space TI Tw 2 ADDR valid write data valid write strobe read data valid read strobe chip select strobe External I O Timing with 1 wait state Figure 26 External I O Bus Cycles Table 29 shows how the eight I O bank control registers are organized Table 29 I O Bank Control Reg adr IBxCR z 08xh Bits 7 6 Bits 5 4 Bit 3 Bits 2 0 Wait state code strobe type 1 permit write Ignored 11 1 00 chip select 0 inhibit write 10 3 01 read strobe 10 7 10 write strobe 00 15 11 or of read and write strobe The I O strobes greatly simplify the interfacing of external devices On reset the upper 5 bits of each register is cleared Parallel port E will not output these signals unless the data d
189. ransmitting a parity bit is the same as sending a 9th bit if the parity bit is zero otherwise it is the same as sending an additional stop bit The only difficult thing to do is to send an additional stop bit when transmitting 8 data bits This requires leaving the transmitter idle for one baud time or longer before the next character is sent One way to do this is to use another serial port as a timer Disable the in terrupts on the port being used to transmit and at the same time the data register is loaded load a dummy character and a 9th bit in the other serial port The interrupt in the auxiliary port will occur after 11 baud times rather than 10 baud times thus guaranteeing the stop bit its full time Another way is to send a full dummy character to create a very long stop bit To avoid the long stop bit the baud timer can be speeded up while the dummy charac ter is sent to reduce the length of the extra stop bit This method will work as long as the baud rate is low enough that it can be speeded up by a factor of 10 to send the dummy character The synchronous nature of timers A4 A7 allows the divide ratio to be in creased or decreased at will without generating irregular clock pulses Yet another method is to use a timer to generate the extra 1 baud delay between characters 12 6 6 Data Framing Modbus Some protocols for example Modbus depend on a gap in the data frame to detect the be ginning of the next frame The 9th bit protoc
190. re Instruction LD A BC LD A DE LD BC A LD DE A LD HL n LD HL r LD r HL LD IX d n LD LD r IX d LD IY d n LD IY d r LD r IY d clk 18 4 16 bit Indexed Loads and Stores Instruction LD HLHd HL LD HL HL d LD SP n HL LD SP n IX LD SP n IY LD HL SP n LD IX SP n LD IY SP n LD IX d HL LD HL IX d LD IY d HL LD HL IY d clk 13 11 11 13 13 9 11 11 11 9 13 11 18 5 16 bit Load and Store 20 bit Address Instruction LDP HL HL clk 12 A ISZVC Operation d r sS mn d mn L 1041 H d mn IXL mn 1 IXH d mn IYL mn 1 d mn 551 mn 1 ssh r s L mn mn 1 s IXL mn IXH mn 1 5 IYL mn mn 1 r s ddl mn ddh mn 1 A ISZVC Operation r s A BC sS DE 4 BC A d DE A d HL n d HL r B C D E H L A r s r HL d IX d n d IX d r r sS r IX d d IY d n d Iy d r r sS r IY d A ISZVC Operation d L HL d 1 r s L HL d H HL d 1 SP n L SP n 1 H SP n IXL SP n 1 IXH SP n IYL SP n 1 r L SP n SP n 1 IXL SP n IXH SP n 1 IYL SP n SP n
191. rial port 80 14 01 I O write 01 to 0000 MBOCR select 1 map RAM to 01 00 00 write to memory address 0 00 01 el 00 02 d3 00 03 32 00 04 12 00 05 00 continue code above here 00 2b 18 last instruction 130 Rabbit 2000 Microprocessor 00 2c ef last bvte 80 24 80 start execution of program at zero The program will execute within about 10 ms 14 9 PC Board Lavout and Memorv Line Permutation In order to use the PC board real estate efficientiv it is recommended that the address and data lines to memory be permuted to minimize the use of PC board resources By permut ing the lines the need to have lines cross over each other on the PC board is reduced sav ing feed through s and space For static RAM address and data lines can be permuted freely meaning that the address lines from the processor can be connected in any order to the address lines of the RAM and the same applies for the data lines For example if the RAM has 15 address lines and 8 data lines it makes no difference if A15 from the processor connects to A8 on the RAM and vice versa Similarly D8 on the processor could connect to D3 on the RAM The only restriction is that all 8 processor data lines must connect to the 8 RAM data lines If sev eral different types of RAM can be accommodated in the same PC board footprint then the upper address lines that are unused if a smaller RAM is installed must be kept in order For example if the same
192. ropagation delay is not a factor because the RAM will be always selected and will be controlled by and WEI If this is done the RAM will consume more power while not battery backed than it would if it were run with dynamic chip select and a wait state If this special feature is used to speed up access time for battery backed RAM then no other memory chips should be connected to OE1 and WEI 14 8 1 Memory Access Time The memory access time required depends on the clock speed and the capacitive loading of the address and data lines Wait states can be specified by programming to accomodate slow memories for a given clock speed Wait states should be avoided with memory that holds programs because there is a significent slowing of the execution speed Wait states are far more important in the instruction memory than in the data memory since the great majority of accesses are instruction fetches Going from 0 to 1 wait states is about the same as reducing the clock speed by 309 Going from to 2 wait states is worth approx imately a 4596 reduction in clock speed A table of memory access times required for var ious clock speeds is given in Table 44 in Chapter 15 14 8 2 Precautions for Unprogrammed Flash Memory If a Rabbit based system is powered up and released from reset when not in one of the cold boot modes the processor attempts to begin execution by reading from address zero of the memory attached to CSO OEO and WEO If this me
193. roximately 4K long and has a 16 bit address between 000 and where n and m are on the order of few dozen bytes but can be up to 4096 bytes in length Since the window is limited to no more than 8K the compiler is unable to compile a single expression that requires more than 8K or so of code space This is not a practical consideration since expressions longer than a few hundred bytes are in the nature of stunts rather than practical programs Program code can reside in the root segment or the XPC segment Program code may also be resident in the data segment Code can be executed in the stack segment but this is usually restricted to special situations Code in the root meaning any of the segments other than the XPC segment can call other code in the root using short jumps and calls 24 Rabbit 2000 Microprocessor Code in the XPC segment can also call code in the root using short jumps and calls How ever a long call must be used when code in the XPC segment is called Functions located in the root have an efficiencv advantage because a long call and a long return require 32 clocks to execute but a short call and a short return require only 20 clocks to execute The difference is small but significent for short subroutines Compiler notices that Compiler inserts code has passed F000 long jump in code 10000 XPC segment E000 b D000 Stack segment N 000 shor
194. rts char PADRShadow PBDRShadow PCDRShadow PCFRShadow char PDDRShadow PDCRShadow PDFRShadow PDDCRShadow PDDDRShadow char PEDRShadow PECRShadow PEFRShadow PEDDRShadow char GCSRShadow global control status register char GOCRShadow global control char GCDRShadow clock doubler When manipulating I O registers and shadow registers the programmer must keep in mind that an interrupt can take place in the middle of the sequence of operations and then the interrupt routine may manipulate the same registers If this possibility exists then a solution must be crafted for the particular situation Usually it is not necessary to disable the interrupts while manipulating registers and their associated shadow registers As an example consider the parallel port D data direction register PDDDR This regis ter is write only and it contains 8 bits corresponding to the 8 I O pins of parallel port D If a bit in this register is a 1 the corresponding port pin is an output otherwise it is an in put It is easy to imagine a situation where different parts of the application such as an in terrupt routine and a background routine need to be in charge of different bits in the PDDDR register The following code sets a bit in the shadow and then sets the I O regis 140 Rabbit 2000 Microprocessor ter If an interrupt takes place between the set and the 144 and changes the shadow regis ter and PDDDR the correct value will still b
195. rts depends on the setup of the corresponding serial port control register When serving as serial inputs the data lines can still be read from the parallel port C data register The parallel port outputs can be selected to be serial port outputs bv storing bits in the corresponding positions of the Port C Function register PCFR When a parallel port output pin is selected to be a serial port output the value stored in the data register is ignored On reset the active even num bered function register bits and data register bits are zeroed This causes the port to out put zeros on the four output bits 9 4 Parallel Port D Parallel port D shown in Figure 24 on page 90 has eight pins that can programmed indi vidually to be inputs and outputs When programmed as outputs the pins can be individu ally selected to be open drain outputs or standard outputs Port D pins can be addressed by bit if desired The output registers are cascaded and timer controlled making it possi ble to generate precise timing pulses In addition port D and E outputs have a higher drive capability Port D outputs 4 and 5 can be used as alternate pins for serial port B and outputs 6 and 7 can be used as alternate pins for serial port A Alternate serial port outputs make it possible for the same serial port to connect to different communications lines that are not operating at the same time On reset the data direction register is zeroed making all pins inputs
196. rv Interface Unit The 20 bit memorv addresses generated bv the memorv mapping unit feed into the mem interface unit The memorv interface unit has a separate control register see Table 20 on page 83 for each 256K quadrant of the 1M physical memory This control register specifies how memory access requests to that quadrant are to be dispatched to the memory chips connected to the Rabbit There are three separate chip select output lines CSO CS1 and CS2 that can be used to select one of three different memory chips A field in the control register determines which chip select or none is selected for memory accesses to the quadrant The same chip select line may be accessed in more than one quadrant For example if a 512K RAM is installed and is selected by CS1 it would be appropriate to use CS1 for accesses to the 3rd and 4th quadrants thus mapping the RAM chip to addresses 80000h to OFFFFFh Table 20 Memory Bank Control Register MBxCR 14h x Bits 7 6 Bit 5 Bit 4 Bit 3 Bit 2 Bits 1 0 00 4 wait states 1 Invert 1 Invert 1 Write pro 0 use OEO WEO 00 use CSO 01 2 wait states address address tect memory 1l use OE1 WE1 01 use CS1 10 1 wait states A19 A18 this quadrant 1x use CS2 11 wait states 8 3 Memory Bank Control Register Functions Table 20 describes the operation of the four memory bank control registers Each register controls one quadrant in
197. rv of Rabbit Advantages The glueless architecture makes it is easv to design the hardware svstem There are a lot of serial ports and thev can communicate verv fast Precision pulse and edge generation is a standard feature Interrupts can have multiple priorities Processor speed and power consumption are under program control The ultra low power mode can perform computations and execute logical tests since the processor continues to execute albeit at 32 kHz The Rabbit mav be used to create an intelligent peripheral or a slave processor For example protocol stacks can be off loaded to a Rabbit slave The master can be any processor The Rabbit can be cold booted so unprogrammed flash memory can be soldered in place You can write serious software be it 1 000 or 50 000 lines of C code The tools are there and they are low in cost If you know the Z80 or Z180 you know most of the Rabbit A simple 10 pin programming interface replaces in circuit emulators and PROM pro grammers The battery backable time date clock is included The standard Rabbit chip is made to industrial temperature and voltage specifications User s Manual 11 12 Rabbit 2000 Microprocessor 2 Rabbit Design Features The Rabbit is an evolutionarv design The instruction set and the register lavout is that of the 780 and Z180 The instruction set has been augmented bv a substantial number of new instructions Some obsolete redundant Z180
198. s been sent The transmitter idle interrupt is normally used to disable the RS 485 driver and possibly enable the receiver 12 6 2 Transmitting Dummy Characters It may be desired to operate the serial transmitter without actually sending any data The output of the transmitter may be disconnected from the transmitter by manipulating the control registers for parallel port C or D which are used as output pins For example if serial port B is to be temporarily disconnected from its output pin which is bit 4 of parallel port C this can be done as follows 1 Storea 1 in bit 4 of the parallel port data output register to provide the quiescent state of the drive line 2 Clear bit 4 of the parallel port C function register so that the output no longer comes from the serial port Of course this should not be done until the transmitter is idle 12 6 3 Transmitting and Detecting a Break A break is created when the output of the transmitter is driven low for an extended period If a break is received it will appear as a series of characters filled with zeros and with the Oth bit enabled A break can be transmitted by transmitting a byte of zeros at a very slow baud rate Another method is to disconnect the transmitter and use the parallel port bit to set the line low while sending dummy characters to time out the break 114 Rabbit 2000 Microprocessor 12 6 4 Using A Serial Port to Generate a Periodic Interrupt A serial port may be used t
199. s time required for a directly interfaced memory is given by access time clock period 2 waitstates Tsetup Tadr 1 This formula remains true if the clock doubler is used except that if there are an odd number of wait states the access time must be reduced by 10 of one clock period See the diagrams below for the definition of Tsetup and Tadr If serial communication is to be used at standard baud rates then certain clock speeds must be used These clock speeds are usually multiples of 1 8432 MHz to ensure that baud rates of 57 600 bps 19 200 bps and less will be available Multiples of 3 6862 MHz ensure that baud rates of 115 200 bps 38 400 bps and less will be available Multiples of 1 2288 MHz ensure that baud rates of 38 400 bps and less will be available The standard Rabbit BIOS will accept any clock speed that is a multiple of 6144 MHz Table 44 Memory Access Time Requirements V 10 T 40 C to 85 C Clock Memory Memory Maximum PC idda Period Wait Access Time Access Time Compatible p ns States 05 V 20 pF Load 95 V 70 pF Load Baud Rate MHz ns ns bps 29 4912 34 0 56 51 921 600 27 6480 36 2 0 60 55 57 600 25 8048 38 7 0 65 59 115 200 25 8048 38 7 1 104 99 115 200 25 8048 38 7 2 142 137 115 200 24 576 40 7 0 70 65 38 400 23 9616 41 7 0 71 66 57 600 22 1184 452 0 78 73 230 400 22 1184 452 1 124 119 230 400 22 1184 452 2 169 164 23
200. se 41 3 5 6 Computed Long Calls and Jumps eese 42 User s Manual 10 Rabbit Capabilities a Reda trs isa URS A P EE 43 4 1 Precisely Timed Output PulSeS ttp eti ete etd dt entend 43 4 1 1 Pulse Width Modulation to Reduce Relay Power 44 4 2 Open Drain Outputs Used for Key eene 46 4 3 Cold Boot osi ecu dn o ecd tea ti e t e 46 4 4 The Slave Port i xtd DIU RU OCURRE 47 4 4 1 Slave Rabbit As A Protocol UART sense sena 48 Pin Assignments and Functions Pd PER INIRE 49 5 1 Package Schematic and Pin 49 5 2 Package Mechanical Dimensions enenennenezznnnnznnnznnnnnennnn ran nennen nennen 50 5 3 Rabbit Pin Descriptions eee eise etti nba sence ie eee e ees 52 5 4 Bus B i A cti Pei e debe Eoo eo i e e ety 58 5 5 Description of Pins with Alternate Functions 59 5 6 Register and Interrupt Vector Summary sess 61 Rabbit Internal I O Reglsters INE 63 Miscellaneous O F nct nS stipe oa ete te mea E ego e nee Su as 67 7 1 Rabbit Os
201. separate interrupt routines for the different devices are called a good method is to have a interrupt dispatcher in software that is aided by providing separate attention request lines for each device The attention request lines are basically the interrupt request lines for the separate devices before they are or ed together The interrupt dispatcher calls the interrupt routines for all devices requesting interrupts in priority order so that all inter rupts are serviced 3 5 3 Privileged Instructions Critical Sections and Semaphores Normally an interrupt happens at the end of the instruction currently executing However if the instruction executing is privileged the interrupt cannot take place at the end of the instruction and is deferred until a nonprivileged instruction is executed usually the next instruction Privileged instructions are provided as a handy way of making a certain oper ation atomic because there would be a software problem if an interrupt took place after the instruction Turning off the interrupts explicitly may be too time consuming or not possi ble because the purpose of the privileged instruction is to manipulate the interrupt con trols For additional information on privileged instructions see Section 18 19 Privileged Instructions on page 157 The privileged instructions to load the stack are listed below ld sp hl ld sp iy ld sp ix The following instructions to load SP are privileged because they are fre
202. service routines ISRs separate by dispatching the inter rupt to either of two different routines This is desirable to make the ISR less complex and to reduce the interrupt off time No interrupts will be lost since distinct interrupt flip flops exist for receive and transmit The dispatcher can test the receiver data register full bit to dispatch If this bit is on the interrupt is dispatched for receive otherwise for transmit The receiver receives first consideration because it must be serviced attentively or data could be lost 112 Rabbit 2000 Microprocessor The dispatcher might look as follows interrupt push af 10 ioe ld SCSR 7 get status register serial port C ora a 2 test sign bit jp m receive 7 go service the receive interrupt jp transmit 7 41 clocks to here go service transmit interrupt The individual interrupts would assume that register AF has been saved and the status reg ister loaded into register A The interrupt service routines can as a matter of good practice and obtaining optimum performance remove the cause of the interrupt and re enable the interrupts as soon as pos sible This keeps the interrupt latencv down and allows the fastest transmission speed on all serial ports Serial ports normally will all generate priority level 1 interrupts The ex ception would be if a port must operate at extremely high speed At 115 200 bps the high est speed of PC serial ports the interrupts must be
203. sters on both sides but are not true read write registers since different data may be read from what is written The master provides the clock or strobe to store data in the three write registers under its control The master also can do a write to the status register which is used as a signaling device and does not actually write to the status register The three registers that the master can write User s Manual 47 appear as read registers to the slave Rabbit The master provides an enable strobe to read the three read data registers and the status register These registers are write registers to the Rabbit The first register or the three pairs registers is special in that writing can interrupt the other processor in the master slave communications link An output line from the slave is asserted when the slave writes to slave register zero This line can be used to interrupt the master Internal circuits in the slave can be setup up to interrupt the slave when the master writes to slave register zero The status register that is available to both sides keeps score on all the registers and reports if a potential interrupt is requested by either side The status register keeps track of the full empty status of each register A register is considered full when one side of the link writes to it It becomes empty if the other side reads it In this way either side can test if the other side has modified a register or whether either side has
204. sters that can be cascaded up to two levels deep Each countdown register can be set to divide by any number between 1 and 256 The output of four of the timers is used to provide baud clocks for the serial ports Any of these registers can also cause in terrupts and clock the timer synchronized parallel output ports Timer B consists of a 10 bit counter that can be read but not written There are two 10 bit match registers and com parators If the match register matches the counter a pulse is output Thus the timer can be programmed to output a pulse at a predetermined count in the future This pulse can be used to clock the timer synchronized parallel port output registers as well as cause an in terrupt Timer B is convenient for creating an event at a precise time in the future under program control 16 Rabbit 2000 Microprocessor Figure 4 illustrates the Rabbit timers Al 4 m perclk 2 5 Timer A System AT f 10 01 counter compare m Timer B Svstem match reg Timer B1 next match Timer B2 match reg next match Figure 4 Rabbit Timers User s Manual 17 2 3 Design Standards The same functionalitv can
205. t calls Data segment retums E000 XPC N XPC N 1 PC F000 K 000 4 Root segment Illustration of sliding XPC window Figure 9 Use of XPC Segment 3 2 2 Practical Memorv Considerations The simplest Rabbit configurations have one flash memorv chip interfaced using CSO and one RAM memory chip interfaced using CS1 The smallest practical amount of flash is 128K and the smallest practical amount of RAM is 32K Smaller chips could be sup ported but such small static memories are obsolete parts so no support is offered Although the Rabbit can support code size approaching a megabyte it is anticipated that the great majority of applications will use less then 250K of code equivalent to approxi mately 10 000 20 000 C statements This reflects both the compact nature of Rabbit code and the typical size of embedded applications Directly accessible C variables are limited to approximately 44K of memory split be tween data stored in flash and RAM This will be more than adequate for many embedded applications Some applications may require large data arrays or tables that will require additional data memory For this purpose Dynamic C supports a type of extended data memory that allows the use of additional data memory even extending far beyond a mega byte User s Manual 25 Requirements for stack memory depend on the type of application and particularly whether preemptive multitasking is used If preemptive multi
206. t field sets the priority of the slave port interrupt The interrupt is disabled by 0 0 Table 42 describes the slave port status register The status register has 6 bits that are set if the particular register is full That means that the register has been written by the proces sor that can write to it but it has not been read by the processor that can read it The bits for SPDOR are used to control the slave interrupt and the handshaking lines as shown in Figure 35 Table 42 Slave Port Status Register SPSR adr 023h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 setby 1 setby 1 setby 1 setby 1 setby 1 setby 1 setby 1 set by master master master master slave slave slave master write to write to write to write to write to write to write to write to SPDOR SPD2R SPDIR SPDOR SPDOR SPD2R SPDIR SPDOR Cleared Cleared Cleared Cleared Cleared Cleared Cleared Cleared bv slave when when when bv when when when write to slave slave slave master master master slave SPSR reads reads reads write to reads reads reads register register register SPSR register register register 122 Rabbit 2000 Microprocessor 13 3 Applications and Communications Protocols for Slaves The communications protocol used with the slave port depends on the application A slave processor mav be used for various reasons Some possible applications are listed be low Keep in mind that t
207. tasking is used then each task requires its own stack Since the stack has its own segment in 16 bit address space it is easy to use available RAM memory to support a large number of stacks When a pre emptive change of context takes place the STACKSEG register can be changed to map the stack segment to the portion of RAM memory that contains the stack associated with the new task that is to be run Normally the stack segment is 4K which is typically large enough to provide space for several typically four stacks It is possible to enlarge the stack segment if stacks larger than 4K are needed If only one stack is needed then it is possible to eliminate the stack segment entirely and place the single stack in the data seg ment This option is attractive for systems with only 32K of RAM that don t need multi ple stacks 3 3 Instruction Set Outline Instructions to Load Immediate Data To a Register on page 27 Instructions to Load or Store Data from or to a Constant Address on page 27 nstructions to Load or Store Data Using an Index Register on page 28 Register to Register Move Instructions on page 29 Register Exchanges on page 29 Push and Pop Instructions on page 30 16 bit Arithmetic and Logical Operations on page 30 Input Output Instructions on page 33 In the discussion that follows we give a few example instructions in each general category and contrast the Z80 Z180 with the Rabbit For a detailed description
208. ted to be an input or output Outputs are buffered by timer synchronizable registers for precision edge control Each of the port lines can be individually selected to be an I O control signal instead of a parallel I O line Each of the 8 possible I O control signals is a strobe energized on an external I O cycle to 1 8th of the 64K external I O space Each strobe can be programmed to be a chip select a write strobe a read strobe or a combined read and write strobe Any port bit used as an I O control strobe must be programmed as an output bit If the slave port is enabled PE7 is used as the slave register chip select signal negative active PE7 should be pro grammed as an input for the slave register chip select function to work If PE7 is pro grammed as an output and set low then the slave register chip select will always be acti vated PEO and PE4 serve as alternate inputs for external interrupt 0 PE1 and PES serve as alternate inputs for external interrup 1 If PEO is enabled then PE must also be enabled and similarly for PE4 and PE5 The interrupt is triggered programmably on fall rising or both edges If both interrupts are enabled they are or ed together after edge detection has been performed on each input individually The port bits must be set up as inputs for the to use them as interrupt request inputs 21 30 Power VDD VBAT 33 3 V or 5 0 V 43 0 V battery backup 43 3 V or 5 0 V 3 28 42 53 78
209. the parallel ports are also shared with numerous other functions as shown in Table 4 on page 59 The important properties of the ports are summarized below Port A Shared with the slave port data interface Port B Shared with control lines for slave port and clock I O for clocked serial mode option for serial ports A and B Port C Shared with serial port serial data Port D 4 bits shared with alternate I O pins for serial ports A and B 4 bits not shared Port D has the ability to configure its outputs as open drain outputs Port D has output preload registers that can be clocked into the output registers under timer control for pulse generation Port D has higher current drive capability e Port E AII bits of Port E can be configured as I O strobes 4 bits of port E can be used as external interrupt inputs One bit of port E is shared with the slave port chip select Port E has output preload registers that can be clocked into the output registers under timer control for pulse generation Port E has higher current drive capability 9 1 Parallel Port A Parallel Port A has a single read write register shown in Table 22 Table 22 Parallel Port A Data Register adr 030h R W 8 bit Data Value If the slave port is enabled this register should not be used The slave port control register is used to control whether this port is an output or input To make the port input store 080h in the SPCR slave
210. the 1M address space Bits 7 6 The number of wait states used in access to this quadrant Without wait states read requires 2 clocks and write requires 3 clocks The wait state adds to these numbers Bits 5 4 These bits allow the upper address lines to be inverted This inversion occurs after the logic that selects the bank register so setting these lines has no effect on which bank register is used The inversion may be used to install a IM memory chip in the space normally allocated to a 256K chip The larger memory can then be accessed as 4 pages of 256K each There is no effect outside the quadrant that the memory bank control register is controlling Bit 3 Inhibits the write pulse to memory accessed in this quadrant Useful for protect ing flash memory from an inadvertent write pulse which will not actually write to the flash because it is protected by lock codes but will temporarily disable the flash mem ory and crash the system if the memory is used for code e Bit 2 Selects which set of the two lines OEx and WEx will be driven for memory accesses in this quadrant Bits 1 0 Determines which of the three chip select lines will be driven for memory accesses to this quadrant All bits of the control register are initialized to zero on reset User s Manual 83 8 3 1 Optional A16 A19 Inversions by Segment CS1 Enable The inversion of A19 or A16 controlled by the MMIDR register is used to redirect m
211. the documentation In general the BIOS is customized for each different controller board The BIOS has dec larations at the start of the code that define the hardware configuration and use options A general purpose BIOS is available that will work with most systems based on the Rab bit The general purpose BIOS is useful for bringing up new designs 17 1 The BIOS More Details The BIOS is compiled separatelv from the user s application It occupies space at the bot tom of the root code segment When execution of the user s program starts at address zero it starts in the BIOS There is no limit to the amount of code that can be included in the BIOS If the user compiles libraries as a part of the BIOS time can be saved since the BIOS is not recompiled except for specific reasons Normally routines that are frequently called on or that are needed for essential functions are in the BIOS When Dynamic C cold boots the target and downloads the binary image the symbol table is retained to make it possible for the user program to call entry points in the BIOS The BIOS supports the following services e System startup including setup of memory wait states and clock speed Reading and programming the real time clock Operation and management of the periodic interrupt Maintenance of memory counters that count ticks milliseconds and seconds since Jan uary 1 1980 Operation of the watchdog timer and maintenance of a system o
212. the least bit of a 16 bit integer is used to repre sent a logical result Logical not operator invert bit 0 of HL in four clocks also works for IX IY in eight clocks dec hl 1 goes to zero zero goes to 1 bool hl 1 to 1 zero to zero 4 clocks total Logical xor operator xor hl de when HL DE are 1 or 0 add hl de res 1 1 6 clocks total clear bit 1 result of if 1 1 2 34 Rabbit 2000 Microprocessor 3 4 4 Comparisions of Integers Unsigned integers may be compared by testing the zero and carry flags after a subtract op eration The zero flag is set if the numbers are equal With the SBC instruction the carry cleared is set if the number subtracted is less than or equal to the number it is subtracted from 8 bit unsigned integers span the range 0 255 16 bit unsigned integers span the range 0 65535 or a clear carry sbc hl de 1 and de B A gt B 1c A B C 2 gt amp Z A B C v 2 If A is in hl and B is in de these operations can be performed as follows assuming that the object is to set hl to 1 or 0 depending on whether the compare is true or false compute hl de unsigned integers ex de hl uncomment for de hl a clear carry sbc hl de C set if hl de sbc hl hl hl hl C 1 if carry set bool hl set to 1 if carry else zero else result unsigned integers compute hl de or de hl check for C de hl uncomment for de lt hl a cl
213. to the other SPDOR register the slave attention line SLAVEATTN pin 100 is asserted driven low by the slave processor This line can be used to create an interrupt in the master Ei ther side that is interrupted can clear the signal that is causing an interrupt request by writ ing to the slave port status register The data bits are ignored but the flip flop that is the source of the interrupt request is cleared Figure 35 shows a logical schematic of this functionality Figure 36 shows a sample connection of two slave Rabbits to a master Rabbit The master drives the slave reset line for both slaves and provides the main processor clock from its own clock There is no requirement that the master and slave share a clock but doing so makes it unnecessary to connect a crystal to the slaves Each Rabbit in Figure 36 has to have RAM memory The master must also have flash memory However the slaves do not need nonvolatile memory since the master can cold boot them over the slave port and download their program In order for this to happen the SMODEO and SMODEI pins must be properly configured as shown in Figure 36 to begin a cold boot process at the end of the slave reset 118 Rabbit 2000 Microprocessor Master writes SPDOR Slave inbound interrupt requested Visible in status register Slave writes status register Slave writes SPDOR ISLAVEATTN PB7 Tx Visible in status register
214. to use serial port A in his ap plication an alternate method of programming is possible using the same 10 program ming port For his own application the user should use the alternate I O pins for port A that share pins with parallel port D The TXA and RXA pins on the 10 pin programming port are then a parallel port output and parallel port input using pins 6 and 7 on parallel port C Using these two ports plus the STATUS pin as an output clock the user can create a synchronous clocked communication port using instructions to toggle the clock and data Another Rabbit based board can be used to translate the clocked serial signal to an asyn chronous signal suitable for the PC Since the target controls the clock for both send and receive the data transmission proceeds at a rate controlled by the target board under de velopment This scheme does not allow for an interrupt and it is not desirable to use up an external in terrupt for this purpose The serial port may be used if desired During program load be cause there is no conflict with the user s program at compile load time However the user s program will conflict during debugging The nature of the transmissions during de bugging is such that the user program starts at a break point or otherwise wants to get the attention of the PC The other type of message is when the PC wants to read or write tar get memory while the target is running 168 Rabbit 2000 Microprocessor The tar
215. total worst case 7 5 us at 20 MHz This routine would take approximately 1590 of the processor s compute time assuming 50 us between interrupts This routine could be speeded up but at the expense becoming more complicated Instead of and and or masks a higher level routine could modify the array directly and the end of the array could be detected by testing a bit pattern in HL The higher level routine would have to suppress the interrupt while changing the bit pat tern in the array or otherwise prevent erratic outputs while the array is being changed If the relay emits a whistle at the period of the modulation the acoustic energy can be spread out over the spectrum by periodically missing an off pulse creating a phase shift of 180 A faster routine that executes in two thirds the time is shown below push af 10 push hl ld hl ptr 11 ld a hl 5 ioi ld port a 13 output data inc hl ld a 0fh 4 and 1 See if hl at end of cycle jr z step2 1 ptr hl pop hl pop af reti step2 ld a beginptr ld 1 a User s Manual 45 ptr hl 13 pop hl 7 pop af reti 103 clocks total 4 2 Open Drain Outputs Used for Key Scan The parallel port D outputs can be individually programmed to be open drain This is use ful for scanning a switch matrix as shown in Figure 12 A row is driven low then the col umns are scanned for a low input line which indicates a key is closed This is repeated for
216. ts the 20 bit addresses and generates control signals applied directiv to the memorv chips Processor gt Memory gt Memory 227 Interface Ips Unit Unit Figure 20 Overview of Rabbit Memory Mapping 8 1 Memory Mapping Unit The 64K 16 bit address space accessed by processor instructions is divided into segments Each segment has a length that is a multiple of 4K Except for the extended code segment the segments have adjustable sizes and some segments can be reduced to zero size and thus vanish from the memory map The four segments are shown in the example in Figure 21 The segment size register SEGSIZE determines the boundaries marked in the diagram The extended code seg ment always occupies the addresses OEOOOh OFFFFh The stack segment stretches from the address specified by the upper 4 bits of the SEGSIZE register to ODFFFh For exam ple if the upper 4 bits of SEGSIZE are ODh then the stack segment will occupy ODOOOh ODFFFh or 4K If the upper 4 bits of SEGSIZE are greater than or equal to OEh the stack segment vanishes If these bits are set to zero the two segments below the stack segment will vanish The lower 4 bits of SEGSIZE determine the lower boundary shown in the figure If this boundary is equal to the upper boundary or greater than OEh the data segment will vanish If this segment is placed at zero the code segment will vanish User s Manual 81
217. tter data register empty interrupt The receiver will answer in terrupts that are generated on the last clock rising edge If the interrupt can be serviced within 1 2 clock there will be no pause in the data rate If it takes the receiver longer to answer then there will be a gap between bytes the length of which depends on the inter rupt latency For example if the baud rate is 400 000 bps then up to 50 000 bytes per sec ond could be transmitted or a byte every 20 us No data will be lost if the transmitter can answer its interrupts within 20 us There will be no slow down if the receiver can answer its interrupt within 1 2 clock or 1 25 us If it can answer within 1 5 clocks or 2 75 us the data rate will slow to 44 444 bytes per second If it can answer in 2 5 clocks or 6 25 us the data rate slows to 40 000 bytes per second If it can answer in 3 5 clocks or 8 75 us the data rate will slow to 36 363 bytes per second and so forth If two way half duplex communication is desired the clock can be turned around so that the receiver always provides the clock This is slightly more complicated since the re ceiver cannot initiate a message If the receiver attempts to receive a character and the transmitter is not transmitting the last bit sent will be received for all eight bits 12 6 Serial Port Software Suggestions The receiver and transmitter share the same interrupt vector but it is possible to make the receive and transmitt interrupt
218. two external interrupts generated by transitions on certain pins in parallel port E The interrupt vectors are shown in Table 15 The interrupts differ from most Z80 or Z180 interrupts in that the 256 byte tables pointed to EIR and IIR contain the actual instructions beginning the interrupt routines rather than a 16 bit pointer to the routine The interrupt vectors are spaced 16 bytes apart so that the en tire code will fit in the table for very small interrupt routines User s Manual 75 Table 15 Peripheral Device Address and Interrupt Vectors On Chip Peripheral I O Address Range ISR Starting Address System Management periodic interrupt 0000 IIR 00000000 Memory Management 0001xxxx No interrupts Slave Port 0010xxxx IIR 10000000 Parallel Port A 0011 No interrupts Parallel Port B 0100 No interrupts Parallel Port C 0101 No interrupts Parallel Port D 0110 No interrupts Parallel Port E 0111 No interrupts External I O Control 1000 No interrupts EIR 0 int 0000 External Interrupts 1001xxxx intO 1 0000000 intl 1 0001000 Timer A 1010xxxx UIR 10100000 Timer B 1011xxxx IIR 10110000 Serial Port A 1100xxxx UIR 11000000 Serial Port B 1101xxxx 11010000 Serial Port C 1110xxxx IIR 11100000 Serial Port D 1111 11110000 IIR OFOh RST 10 instruction n a IIR 00100000
219. ty processor The slave processor can process data to perform pattern recognition or to extract a specific parameter from a data stream 13 3 2 Master Slave Messaging Protocol In this protocol the master sends messages to the slave and receives an acknowledgement message The protocol can be polled or interrupt driven Generally the master sends a message that has a message type code perhaps a byte count and the text of the message The slave responds with a similar message as an acknowledgement Nothing happens un less the master sends a message The slave is not allowed to initiate a message but the slave could signal the master by using a parallel port line other than SLAVEATN or by placing data in one of the registers the master can read without interfering with the mes sage protocol The master sends a message byte by storing itin SPDOR The slave notices that SPDOR is full and reads the byte When the master notices that SPDOR is empty because the slave read it the master stores the next byte in SPDOR Either side can tell if any register is empty or full by reading the status register When the slave acknowledges the message with a reply message the process is reversed To perform the protocol with interrupts a User s Manual 123 slave interrupt can be generated each time the slave receives a character The slave can ac knowledge the master bv reading SPDOR if the master is polling for the slave response to each character If t
220. ual compare is detected Unequal compare would be more useful They are difficult to simulate efficiently so it is suggested that code using these instruc tions be rewritten which in most cases should be quite easy The following op codes are dropped RST 0 RST 8 RST 30h The remaining RST instructions are kept but the interrupt vector is relocated to a variable location the base of which is established by the EIR register RST can be simulated by a call instruction but this is not done automatically by the assembler since most of these in structions are used for debugging by Dynamic C The following instruction has had its op code changed ex sp hl old opcode OE3h new opcode OEDh 054h The following instructions use different register names 1 a eir 1 eir a was register ld iir a ld a iir was I register User s Manual 159 The following Z80 Z180 instructions have been dropped but the code shown will be sub stituted automaticallv bv the assembler planned feature call cc adr tst r hl n mlt hl mlt de mlt bc jr jp ncc xxx reverse condition call adr push de push af and r hl n pop de get a in h ld a d pop de call mlthl simulates z180 mlt hl call mltde call mltbc 160 Rabbit 2000 Microprocessor 20 Instructions in Alphabetical Order With Binarv Encoding Kev n 8 bit data item d 8 bit offset ss 00 Ol DE 10 HL il SP
221. ugh instructions Traditional microprocessor hardware and software development is simplified for Rabbit users In circuit emulators are not needed and will not be missed by the Rabbit developer Software development is accomplished by connecting a simple interface cable from a PC serial port to the Rabbit based target system 1 1 Features and Specifications 100 pin PQFP package Operating voltage 2 7 V to 5 V Clock speed to 30 MHz specifications are given for both industrial and commercial temperature and voltage ranges Rabbit microprocessors cost under 10 in moderate quantities Industrial specifications are for a voltage variation of 10 and a temperature range from 40 C to 85 C Commercial specifications are for a voltage variation of 5 and a temperature range from 0 to 70 e megabyte code space allows C programs with up to 50 000 lines of code The extended Z80 style instruction set is C friendly with short and fast instructions for most common C operations Four levels of interrupt priority make a fast interrupt response practical for critical applications The maximum time to the first instruction of an interrupt routine is about 1 us at a clock speed of 25 MHz Access to I O devices is accomplished by using memory access instructions with an I O prefix Access to I O devices is thus faster and easier compared to processors with a restricted I O instruction set User s Manual 7 The hardware d
222. used for most jumps within the win dow Normal 16 bit jumps calls and returns may also be used to access code in the other three segments in the 16 bit address space If a transfer of control to code outside the win dow is required then a long jump long call or long return is used These instructions modify both the program counter PC and the XPC register causing the XPC window to point to a different part of memory where the target of the long jump call or return is lo cated The XPC segment is always 8K long The granularity with which the XPC seg ment can be positioned in memory is 4K Because the window can be slid by one half of its size it is possible to compile continuously without unused gaps in memory As the compiler generates code resident in the XPC window the window is slid down by AK when the code goes beyond F000 This is accomplished by a long jump that reposi tions the window 4K lower This is illustrated by Figure 9 on page 25 The compiler is not presented with a sharp boundray at the end of the page because the window does not run out of space when code passes F000 unless 4K more of code is added before the win dow is slid down All code compiled for the XPC window has a 24 bit address consisting of the 8 bit XPC and the 16 bit address Short jumps and calls can be used provided that the source and target insructions both have the same XPC address Generally this means that each instruction belongs to a window that is app
223. ved The so called bit or address bit mode of operation is also supported Parity and multiple stop bits are not di rectly supported by the hardware but may be accomplished by suitable programming techniques 12 1 Register Layout Serial Port Figure 30 shows a functional block diagram of a serial port Each serial port has a data register a control register and a status register Writing to the data register starts transmis sion If the write is performed to an alternate data register address the extra address bit or 9th bit is sent When data bits have been received they are read from the data register The control register is used to set the transmit and receive parameters The status register may be tested to check various information about the operation of the serial port User s Manual 105 Read Data Write Data Data Out Data In Reg Data Out Reg for 9th bit 1 Input Shift Reg Output Shift Reg gt RX serial data in TX serial data out Bit 0 1 2 3 4 5 6 7 stp Transmitting OD6h Start Bit Stop Bit Bit 0 1 2 3 4 5 6 7 A stp Transmitting OD6h with 9th address bit 0 1 1 0 1 0 1 vf 9th bit Stop Bit TX l Start Bit Signals Shown At Microprocessor TX pin Figure 30 Functional Block Diagram of a Serial Port The clock input to the seri
224. y Although modern designs usually use at least four layer printed circuit boards two sided boards are a viable option with the Rabbit especially if the clock speed is not high and the design is intended to operate at 2 5 V or 3 3 V actors which reduce edge speed and electromag netic radiation 14 1 RS 485 Communication Interface To be added in the future 14 2 RS 232 Communication Interface To be added in the future 14 3 Analog to Digital Converters To be added in the future 14 4 Digital to Analog Converters To be added in the future 14 5 High Voltage Drivers To be added in the future 14 6 Clocks The Rabbit has two built in oscillators The 32 768 kHz clock oscillator is needed for the battery backable clock the watchdog timer and the cold boot function The main oscilla tor provides the run time clock for the microprocessor The 32 768 kHz oscillator is slow to start oscillating after power on For this reason a wait loop in the BIOS waits until this oscillator is oscillating regularly before continuing the startup procedure If the clock is battery backed there will be no startup delay since the oscillator is already oscillating The startup delay may be as much as 5 seconds Crys tals with low series resistance R 35 kO will start faster The required oscillator circuit is shown in Figure 37 If current consumption by the real time clock is important the reg ulator circuit shown in the figure below wil

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Rabbit 2000™ Microprocessor User`s Manual