Multimedia Processor for Mobile Applications (EMMA
Contents
1. Users Manual R19UH0028EJ0500 43 CHAPTER 4 USAGE 4 1 2 External Memory Access The DDR module is controlled by two clock signals MEMC CLR and MEMC_CLK270 which are supplied by the ASMU system management unit The frequency of MEMC_CLK is 133 or 166 MHz MEMC_CLK270 is obtained by shifting the phase of MEMC_CLK by 270 If there are no read write requests in the request queue DDR SDRAM enters the self refresh mode in which no clock requests are issued When a read or write request is queued the MEMC requests the issuance of a clock signal to the ASMU In normal mode the maximum frequency of MEMC CLR is 166 MHz and 133 MHz When MEMC CLR operating frequency is switched a handshake with the ASMU occurs Figure 4 1 shows the frequency switch timing The AC parameters for the timing of exiting a refresh and starting an auto refresh are optimized according to the switched operating frequency When the operating clock is switched to the system clock generated by PLL3 the frequency is judged to be low by receiving the MEMC_CLK operating frequency recognition signal sent from the ASMU and the AC parameters for DDR SDRAM are adjusted to the low frequency mode The clock frequency is switched immediately if all chips have entered the self refresh mode when clock frequency switching is requested ACK is returned immediately When a request is being processed DDR SDRAM is being accessed the clock frequency is switched after the requested ac2. Reserved ERR SECERR Reserved R 31 2 om Reserved When these bits are read O is returned for each bit ERR 1 Indicates the status of error interrupts other than the security error interrupt 0 No interrupt source 1 There is an interrupt source SECERR Indicates the status of the security error interrupt 0 No interrupt source 1 There is an interrupt source Users Manual R19UH0028EJ0500 17 CHAPTER 3 REGISTERS 3 2 4 ACPU interrupt raw status register This register MEMC INTRAWSTATUS A C00A 0018H indicates the status of the interrupt sources for the ACPU The bits corresponding to the interrupt sources are set regardless of the settings of the interrupt enable set register and the interrupt enable clear register 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 ii Reserved RAWERR SECRAWERR Reseved R 3t2 o Reserved When these bits are read O is returned for each bit RAWERR 1 Indicates the raw status of error interrupts other than the security error interrupt 0 No interrupt source 1 There is an interrupt source SECRAWERR Indicates the raw status of the security error interrupt 0 No interrupt source 1 There is an interrupt source 18 User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS 3 2 5 ACPU interrupt enable set register This register MEMC INTSET A C00A 001CH enables the issua
3. Reserved Reserved r 1 0B Reserved Wien this bit is reaa Ois retuned Reserved When this bit is read 0 is returned CS0 APD AUTO RW Specifies whether to request an automatic CSO power down 0 Normal operation 1 Requested When no received requests remain in the request queue the counter is incremented up to the value set to the CS0 1_APD_COUNT bits and then the corresponding CS automatically enters the power down mode CKE low level 38 User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS 3 2 19 Automatic DQS timing adjustment register 1 This register MEMC DDR CONFIGT1 C00A 2020H specifies the adjustment of delays in external memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Reserved Reserved When these bits are read 0 is returned for each bit MCLK_DELAY Adjusts the MCLK delay delay 1 Reserved i Reserved When these bits are read 0 is returned for each bit CLK270 DELAY Adjusts the CLK270 delay delay 4 Reserved In 15 12 EE Reserved When these bits are read 0 is returned for each bit DQS O DELAY RW i m Adjusts the delay of DQS output delay 3 Reserved R 73 om Reserved When these bits are read 0 is returned for each bit CALIBRATE_PAT R W 2 Specifies the calibration pattern pem 0 OXFFFF 0x0000 1 OXAAAA 0x5555 CALIBRATE STATE R W 1 1B Indicates the calibration status 0 Busy 1 Ready AUTO CALIBRATE R W 1B Specif
4. LENESAS User s Manual Multimedia Processor for Mobile Applications DDR SDRAM Interface EMMA Mobile Wi Document No R19UH0028EJ0500 5th edition S19254EJ5V0UMOO Date Published June 2010 2010 Renesas Electronics Corporation All rights reserved Printed in Japan MEMO 2 User s Manual R19UH0028EJ0500 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related informatio
5. OC AR co N Di o CSO STATE 15 0 DH Indicates the status of the memory connected to CSO 0x0 Idle 0x1 Extended mode register setting 0x3 Self refresh 0x5 Auto power down 0x6 Self refresh end 0x7 Deep power down 0x8 Bank precharge all bank precharge 0xA Read write OxC Forced CBR refresh OxE CBR refresh OxF Mode register setting 42 User s Manual R19UH0028EJ0500 CHAPTER 4 USAGE 4 1 External Memory Access Control 4 1 4 External Memory Access DDR SDRAM can be connected as an external memory and can be read and written in 8 burst length The DDR SDRAM is divided into four banks Consecutive reading access within a 1 KB consecutive address in the same bank CAS access can be performed efficiently However access outside the 1 KB consecutive address RAS access is less efficient Accessing a different bank is efficient The DDR scheduler sorts requests in order to make access efficient Table 4 1 Clock Counts Required for 16 Word Access Burst Length 8 Samebank eadeswie RAS 25 25 25 Other bank write read Samebank wie o readCAS 25 w 25 iw Samebank wie o readRAS 25 mw 25 25 Other bank write lt gt write Same bank write write CAS a mw a s Same bank write write RAS 25 e a 29 ohercipfeadeswig a a a a Other chip write write Settretresh recovery w e 20 Deep power down recovery e sw 7 7
6. This register MEMC CACHE MODE C00A 0000H specifies whether to cache and prefetch data for each master device 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DIS SHXB DIS MHXB DIS DHXB DIS DSPD DIS DSPI DIS ACPU 15 14 13 12 ti 10 9 8 7 6 5 4 3 2 1 0 PRE SHXB PRE MHXB PRE DHXB PRE DSPD PRE DSPI PRE ACPU Senat R aes on Ress When hese bis are reaa tee os me aw e oB oscachesdataread omine mo fens ewe n 08 Reeves erreneren ite s soa aw 22 oB oscaches data read tom he SHXB t Doos noteache da os ama aw 21 oB os caches data read tom the MHB 1 Does nocache data sowe mw 20 oB Caches data read trom the DHX 1 Does not cache data s sep aw te oB o Caches data read tom te ADSPO 1 Does nocache data een Rw sw 08 o Caches data ren rom tne ADSP 1 Doss teen fois acru mw 17 oe Caches data read trom he AGPU 1 Does not cache data eme R 169 of eent when iese bts are reno Gis euneaioreach bn Dl PRE_IMC R W 0 Does not prefetch data while reading data from the IMC peu 1 Prefetches data while reading data from the IMC mee n 7 08 Resend whenthisbtieresa oisrewmed PRE SHXB R W 0 Does not prefetch data while reading data from the SHXB adi Prefetches data while reading data from the SHXB PRE MHXB Does not prefetch data while reading data from the MHXB penna Prefetches data while reading data from the MHXB PRE DHXB Does not pref
7. 3 1 2 Memory request scheduler setting registers A 13 3 1 8 External memory control registers eeeeseeseeeeseseeeeee nennen nnne eene nnne nnne rna 14 3 2 Register Functions E 15 3 2 1 X Cache prefetch setting register A 15 3 22 junction disabling register i tert e Dre EE d n 16 3 2 8 ACPU interrupt status register sssesssssssseeseseeee eene nennen nennen nenne nennen nennen 17 3 2 4 ACPU interrupt raw status register nennen nennen nennen 18 3 2 5 AGPU interrupt enable setiregister sir ice po raa kied okan d e TREE CM RETE RA Oo 19 3 2 6 ACPU interrupt enable clear register ssssssssseeenenennnen nene enenennnenennenn 20 3 2 7 ACPU interrupt source clear register sessssesseseseeeeeenenenneen nennen 21 3 2 8 Error master ID register iE AAA EE bos 22 3 2 9 Etroraddress regiSter u cer Dc heb prb p fot a Se Ec ee der ees 23 3 2 10 Memory request scheduling mode register 24 3 2 11 Memory connection setting register A 25 3 2 12 AG timing Setting register T oie RPG n E mp 29 3 2 13 AC timing setting e TEE 30 3 2 14 Software command issuance register e 32 3 2 15 Software command issuance register 2 33 3 2 16 Refresh setting register RE 35 3 217 Refresh setting RE UE 36 3 2 18 Refresh setting register EE 38 3 2 19 Automatic DQS timing adjustment register 1 39 3 2 20 Automatic DQS timing adjustment register 32 40 3 2 21 Automatic DQS timing adjustment
8. activated In read cycles data is received latched based on the DQS signal output from external memory with delays added In write cycles data is output in synchronization with MEMC CLR270 Figure 4 2 Clock adjustment mechanism Users Manual R19UH0028EJ0500 45 46 CHAPTER 4 USAGE MEMC Conposision Clock adjustment mechanism MCLK_DELAY MCLK_DELAY CLKDELAY 270 Delay CLK 270 Delay MCLK CLK DELAY 270 DOS 0 DELAY i Delay ASMU DQS O DELAY A filial e b DATAO pam LOGIC MEMC MEMCIO DQS 3 0 DELAY Figure 4 3 Write phase adjustment WRITE adjustment Output MCLK is adjusted by changing MCLK_DELAY The phase of DQS is adjusted most suitably by changing DQS_DELAY The phase of DQ DQS is adjusted by changing CLK_DELAY_270 Figure 4 4 Read phase adjustment User s Manual R19UH0028EJ0500 CHAPTER 4 USAGE READ adjustment The phase of most suitable DQS which calculates the most suitable DQS 0123 DELAY value in calibration S W and latches READ DATA by EM1 calculation adjustment tAC max pos IE DATA fastest DATA slowest DATA Window Users Manual R19UH002
9. delays 31 30 29 28 27 26 25 24 Reserved DQSO DELAY VAL 23 22 21 20 19 18 17 16 Reserved DQS1 DELAY VAL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DQS3 DELAY VAL Function Reserved Reserved When these bits are read 0 is returned for each bit DQSO DELAY VAL Stores the result of adjusting the DQSO delay Reserved Reserved When these bits are read O is returned for each bit DQS1 DELAY VAL Stores the result of adjusting the DQS1 delay CIE wa e CTT IT meest Wren ese bis rore 0 is eure or each on Sioesite rout tango 0089 dey The optimum delay values obtained by calibration are stored in the DQSO DELAY VAL to DQS3 DELAY VAL bits When adjustment for automatic calibration is executed set the MEMCCLK270 SEL bit of the MEMCCLK270 SEL register to 1 in the ASMU Users Manual R19UH0028EJ0500 41 CHAPTER 3 REGISTERS 3 2 22 Memory status check register This register MEMC DDR STATE8 CO0A 202CH is used to monitor the status of CSO and CS1 31 30 29 28 27 26 25 24 CS1_STATE 23 22 21 20 19 18 17 16 CS1_STATE 15 14 13 12 11 10 9 8 CS0 STATE CS0 STATE CS1 STATE 31 16 DH Indicates the status of the memory connected to CS1 0x0 Idle 0x1 Extended mode register setting 0x3 Self refresh 0x5 Auto power down 0x6 Self refresh end 0x7 Deep power down 0x8 Bank precharge all bank precharge 0xA Read write OxC Forced CBR refresh OxE CBR refresh OxF Mode register setting NI o
10. disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics produc
11. register 2 41 3 2 22 Memory status check register cccececcceceseeeeeeseeeeeessaneeseseeeeesaeeesessaseeseseesesseeeeeessenaensseeneesensees 42 CHAPTER 4 USAGE ss aie ades cot cicle 43 4 1 External Memory Access Control ccccccccsseceeseeeeeeeeeseeeseseeeenseeeeseesesneesaseeeeeeeeeseeseseaeenseeeeee 43 dl External Memory ACC S Si stem bap ine Bie la ee ee ES 43 4 1 2 External Memory ACCOSS coire REPARARE EE eiin 44 d r Clock Phase Controls IR Reate ee tele ute att ie 45 AANA jArbitration zii pao BC PH iie 48 41 5 Refresh control iue ed ea ees ADELIA A nll 49 Users Manual R19UH0028EJ0500 7 4 1 6 Software command conttol eu sos sens sno e on ra eka meitat 4 1 7 Power on ott sequerce ome IA User s Manual R19UH0028EJ0500 Figure No Figure 1 1 Figure 3 1 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Table No Table 3 1 Table 3 2 Table 4 1 Table 4 2 Table 4 3 LIST OF FIGURES Title Page Block BIEL TEE 11 External Memory Address Mappimg AA 27 Timing at Which MEMC_CLK Operating Frequency Is Switched eecceseeeeeeeeeeeeeeeeeeneeeeeeeeeneeeeneeteaes 45 Clock adjustment mechahismi sss smn ee Lee kanl ra La aero ls rn 45 Write phase ad uUSsIMEN sa nn cot em eren ex Ven E np eie st den 46 RE ee NERT ET EE 46 Refresh Control Status Transitions cipe rl oj siaiu tapant 49 DDR SDRAM Power On Timing icr kras rs AE nL REESEN SEENE
12. 19UH0028EJ0500 CHAPTER 3 REGISTERS 3 2 11 Memory connection setting register This register MEMC DDR CONFIGF C00A 2000H specifies the configuration for the external memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 CS1 BANK SPLIT CS1 DOUBLE CS1 DENSITY CS1 JEDEC CS1 ENABLE 7 6 5 4 3 2 1 CS0 BANK SPLIT Cen DOUBLE CS0 DENSITY Cen JEDEC CSO ENABLE epee Reserved When these bits are read O is returned for each bit i Reserved CS1 BANK SPLIT Specifies the number of banks for interleaving for CS1 see Figure 3 1 00B 4 bank interleave 01B 2 bank interleave 10B No interleave 11B Lower two banks interleaved higher two banks not interleaved Reserved Reserved When this bit is read 0 is returned CS1_DOUBLE Indicates whether two CS1 chips 16 bit bus chip x 2 may be used 0 Not used 32 bit bus chip x 1 1 May be used 16 bit bus chip x 2 CS1_DENSITY CS1_JEDEC R W CS1_ENABLE R W CS0 BANK SPLIT T Reserved NEE Specifies the memory size of CS1 00B 128 Mb 01B 256 Mb 10B 512 Mb 11B 1 Gb a Jee SSCS Specifies whether to enable access to CS1 memory 0 Disables access 1 Enables access Specifies the number of banks for interleaving for CSO see Figure 3 1 00B 4 bank interleave 01B 2 bank interleave 10B No interleave 11B Lower two banks interleaved higher two banks not interleaved ON Reserved When this bit is read 0 i
13. 4 Bea ECH EA Users Manual R19UH0028EJ0500 27 28 CHAPTER 3 REGISTERS Table 3 2 DDR SDRAM JEDEC 32 bit bus chip x 1 256 Mb A 11 0 A 8 0 BA 1 0 16 bit bus chip x 2 256 Mb A 12 0 A 8 0 BA 1 0 512 Mb A 12 0 A 9 0 BA 1 0 areo anoo suno User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS 3 2 12 AC timing setting register 1 This register MEMC DDR CONFIGA1 C00A 2004H determines the AC timing of external memory 31 30 29 28 27 26 25 24 tDCRRD tRRD tRP 23 22 21 20 19 18 17 16 tRCD RCL WCL 15 14 13 12 11 10 9 8 R Specifies the number of cycles required from a read write command to a read write command between chips Specifying 0 is prohibited Specifies the reference clock cycles between bank activating commands Specifies the reference clock cycles from a precharge command to a bank activating command Specifies the period from a bank activating command to a read command and a bank activating command to a write command 0x3 at 166 MHz 0x2 at 133 MHz 0x1 at 100 MHz RL tRCD RCL WL tRCD WCL 1999 Specifies the read CAS latency 00B CL 2 01B CL 3 10B CL 4 11B CL 5 Specifies the write CAS latency 00B CL 1 01B CL 2 10B CL 3 11B CL 4 Reserved When this bit is read O is returned Specifies the period from a read command to a write command tRWD 4 clock cycles Reserved When this bit is read O is returned
14. 5 24 al al aif 20 19 18 old wall mj tof of ef 7 e 5 4 3 2 User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS Table 3 1 Correspondence of CPU Address and External Memory Address JEDEC CPU Address DRAM Address A6 ils AB A7 A6 as Aa fas A2 At AO BATBAQAS A7 A6 TAS aa fas A2 At AO Eau ae AS aa AS a2 At ao Badas A7 AG fas A4 as A2 ar A0 ArdArfa1das A8 A7 AG fas Ad As A2 At AO BATBAQAS A7 AG as A4 as A2 At A0 2 bank BA1 H 16b bank E Gei A2 AT 4 bank BAT T danadas A8 A7 ae as As AS A2 At AO BA BAdao as A7 AG fas faa AS A2 A1 AO 2 bank BA1 H Figure 3 1 External Memory Address Mapping BANK SPLIT register set value No bank division 0x0 e Dividing bank by 2 0x1 Dividing bank by 4 0x21 Dividing bank by 2 0x3 DDR partial refresh unit COSMO partial refresh unit Banks 0 and 1 Up to 4 KB units can be Up to 2 KB units can be Up to 1 KB units can be 2 KB units can be accessed accessed sequentially accessed sequentially accessed sequentially sequentially Banks 2 and 3 The division factor of banks can be individually specified for CS0 1 KB unit can be accessed and CS1 puo un __ sequentially 1 KB units can be accessed sequentially 2 KB units can be accessed sequentially o csi 4 KB units can be zl accessed sequentially dl
15. 8EJ0500 CHAPTER 4 USAGE 4 1 4 Arbitration 48 The DDR module arbitrates the follovving three instructions lt 1 gt Access instructions from the request queue independent of read write lt 2 gt Self refresh instructions from the IDLE REF counter or auto refresh instructions 2 types lt 3 gt Software command instructions 7 types The MEMC outputs the control signals for arbitration according to the priority shown in the following table Table 4 2 DDR Module Priority in Processing lt 2 gt lt 3 gt Self Auto Refresh Software command See Precharge all Auto refresh Self refresh Deep power down Read mode register Write mode register Auto refresh Users Manual R19UH0028EJ0500 CHAPTER 4 USAGE 4 1 5 Refresh control To retain data the MEMC refreshes DDR SDRAM at a constant interval The self refresh mode is entered vvhen no read or write request is being received after setting the CS0 1 REF AUTO bits or CS0 1SREF AUTO bits of the MEMC DDR CONFIGR2 register In other cases the number of refreshes that has been executed is counted during each refresh cycle and CBR refreshes are performed for the relevant number of times at a specific timing For the catalogue value of DDR SDRAM whose row address is allocated in 16 M word units refreshes must be executed at least 8 192 times per 64 ms once in 7 to 8 us In EM1 the refresh cycle can be specified freely for the CS0 1 REF COUNT bits of the MEMC DDR CONFIG
16. N eege 51 LIST OF TABLES Title Page Correspondence of CPU Address and External Memory Address LEDEC sss 27 DDR SDRAM JEDEG Eur ates etc ede otis c certc e raspita da enti ae eina 28 Clock Counts Required for 16 Word Access Burst Length 8 43 DDR Module Priority in Proceseimg menn nnne nennen nemen enne 48 Software e ul Il o dene denn RAUM 50 Users Manual R19UH0028EJ0500 9 CHAPTER 1 OVERVIEW The Mobile DDR SDRAM interface MEMC controls access to DDR SDRAM 1 1 Features 10 O External memory access control The MEMC has a timing controller for the external memory interface The usable memory is Mobile DDR SDRAM The maximum operating frequency is 166 MHz The MEMC can generate refresh requests to execute refreshes required for DDR SDRAM For details about the following functions see CHAPTER 4 Usage e Supported SDRAM Mobile DDR SDRAM 32 bit data bus connection one chip that has a 32 bit bus or two chips that have 16 bit buses connected in parallel Operating frequency 133 166 MHz DDR266 DDR333 CS0 and CS1 supported Maximum memory size per CS 128 MB 1 Gb x 1 chip 16 MB 128 Mb x 1 chip to 256 MB 1 Gb x 2 chips e Main functions Flexible address mapping Entering and exiting auto self refresh mode Command control via software Low power consumption due to clock control and automatic frequency control Request control The MEMC controls requests sent from various macros so as to in
17. R2 register When operation enters a refresh cycle the number of times refreshes still need to be executed is stored in the CS0 1 REF STOCK bits of the MEMC DDR CONFIGRI register When this number reaches the specified value the values of the CS0 1 STOCK MAX bits of the MEMC DDR CONFIGR2 register acceptance of requests from the request queue is forcibly suspended temporarily and a CBR refresh is executed once at the top priority While in the self refresh mode the timer that counts the refresh cycles stops temporarily and resumes when the mode is exited If refreshes still need to be executed when the self refresh mode is entered CBR refreshes are executed multiple times up to the value specified by the CS0 1 STOCK DRAIN bits of the MEMC DDR CONFIGR2 register before a self refresh is executed Figure 4 5 shows the processing from when shifting to CBR refresh execution and after shifting to the self refresh mode Refresh operation is controlled individually for CSO and CS1 Figure 4 5 Refresh Control Status Transitions Can SREF AUTO 0 CS0 REF AUTO 0 EUER AS TOUS CS0 REF AUTO 1 CS0_REF _AUTO 0 CS0 MODE SREF 0 _ _ _ _ IDLE Counter ACT Refresh Counter ACT Refresh Counter si Suspend CS0 MODE SREF 1 Resume CS0 SREF COUNT VAL CS0 SREF COUNT 88 CS0 REF STOCK 0 FIF AVALID 1 E 2 Ntimes Users Manual R19UH0028EJ0500 49 CHAPTER 4 USAGE 4 1 6 Software com
18. RMASK VV 1 Specifies whether to disable mask the issuance of error interrupts other than the security error interrupt 0 Ignored 1 Disables the sources When read 0 is returned SECERRMASK W Specifies whether to disable mask the issuance of the security error interrupt 0 Ignored 1 Disables the sources When read 0 is returned 20 User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS 3 2 7 ACPU interrupt source clear register This register MEMC INTFFCLR A C00A 0024H clears interrupt sources for the ACPU 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ERRCLR SECERRCLR Reserved Rf 312 o Reserved When these bits are read 0 is returned for each bit ERRCLR VV 1 Specifies whether to clear error interrupt sources other than the security error interrupt source 0 Ignored 1 Clears the sources When read 0 is returned SECERRCLR W Specifies whether to clear the security error interrupt source 0 Ignored 1 Clears the sources When read 0 is returned User s Manual R19UH0028EJ0500 21 CHAPTER 3 REGISTERS 3 2 8 Error master ID register This register MEMC ERRMID C00A 0068H retains the ID of a master whose request caused an error 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 MID Reserved R 318
19. SMO EE ta ecu i ty 1 i i 1 u I7 External CS CE1 pin Power down processing is always CS0 1 automatic power down request the automatic self refresh and the automatic refreshment request Disable All Bank Precharge request gt issue confirmation gt CKE Enable issue request gt Issue confirmation gt Deep power down issue CMD REQ LOCK 1 gt Issue confirmation s Do by an order of the end Users Manual R19UH0028EJ0500 51 52 Revision History Date Revision Comments February 10 2009 1 0 April 27 2009 2 0 Incremental update from comments to the 1 0 June 12 2009 3 0 Incremental update from comments to the 2 0 September 30 2009 4 0 Incremental update from comments to the 3 0 June 30 2010 5 0 Incremental update from comments to the 4 0 Users Manual R19UH0028EJ0500 RENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electroni
20. Specifies the period from a write command to a read command tWPD 4 clock cycles Reserved When this bit is read O is returned tRPD R W 000B Specifies the period from a read command to a precharge command tRPD 4 clock cycles a Reserved When this bit is read O is returned tWPD R W 011B Specifies the period from a write command to a precharge command tWPD 4 4 clock cycles Note tRCDR tRCDW 1 RL tRCDW RCL WL tRCDW WCL 1 Because the same AC parameters are applied to CSO and CS1 devices whose AC timing specifications differ cannot be connected to CSO and CS1 at the same time Reserved Users Manual R19UH0028EJ0500 29 CHAPTER 3 REGISTERS 3 2 13 AC timing setting register 2 This register MEMC DDR CONFIGA2 C00A 2008H specifies the AC timing parameters for external memory and is used to expand some functions 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 tSREX tRFC 15 14 13 12 11 10 9 Reserved LowFrqTyp DQS_mask_Ext DQS_mask DQM_HZ P 6 5 4 3 2 1 0 IO HZ CLK MODE PstamblExt PreamblExt DBParkEna di 1 2 Reserved R 31 28 0H Reserved When these bits are read 0 is returned for each bit CS1H R W 27 0B Forcibly sets CS1 to high level 0 Active 1 High level CS0H R W 26 0B Forcibly sets CSO to high level 0 Active 1 High level El R W 25 0B Specifies the state of the I O buffer for address signals 0 Active 1 Hi Z CMD_HZ R W 24 Specifies the state of the I O buffer for co
21. TE bit When a software command is executed while the CMD_STATE bit is set to 0 busy the command is ignored When a command to request that the CKE signal be enabled is issued a clock request is issued at the same time Table 4 3 Software Commands enen Jegen E 50 User s Manual R19UH0028EJ0500 CHAPTER 4 USAGE 4 1 7 Power on off sequence When the power is initially turned on the DDR_RST signal is asserted after a clock signal is supplied This signal is controlled by the ASMU Immediately after a reset first set up DDR registers such as MEMC_DDR_CONFIGF MEMC DDR CONFIGFA1 and MEMC DDR CONFIGA2 Next individually execute the initialization sequence listed in the table belovv for CSO and CS1 by using softvvare commands The sequence might differ depending on the connected DDR SDRAM For details see documents such as the data sheet for the device For safety it is recommended to set the CMD REQ LOCR bit of the MEMC DDR CONFIGC2 register to 1 to lock any requests other than the command issuance When issuing the last command set the CMD REQ LOCR bit to 0 to release the loched state Figure 4 6 DDR SDRAM Povver On Timing Power on sequence for DDR SDRAM MEMC_CLK DDR module clock i DDR_RST TO Ti T2 T3 T4 T5 T6 T7 T8 T9 T10 Tu T12 Software command issued i l CMD_ENABLE i z 1f Software command issued Initial sequence processing 7 7 i i External CKE CE2 pin SDRAM CO
22. URST and AWBURST are fixed or reserved 100B Illegal INCR burst INCR burst in byte or halfword units 101b Illegal WRAP burst Users Manual R19UH0028EJ0500 23 CHAPTER 3 REGISTERS 3 2 10 Memory request scheduling mode register This register MEMC REQSCH C00A 1000H specifies the schedule of requests for memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MXCASWN MXWTWN MXRDWN WTDNUM OH 00B 00B 00B 00B 00B Reserved Reserved When these bits are read O is returned for each bit Specifies the maximum number of times the same CS can be selected in a row 00B No specification 01B 2 times 10B 4 times 11B 6 times Specifies the maximum number of times a CAS request can be selected in a row 00B Once Performs execution immediately after receiving a CAS request 01B 2 times 10B 4 times 11B 6 times Specifies the maximum number of times a write request can be selected in a row for a read request during a write drain MXWTWN MXRDWN MTDNUM 00B No specification 01B 2 times 10B 4 times 11B 6 times Specifies the maximum number of times a read request can be selected in a row for a write request during a write drain Reserved R MXCSWN VV MXCASWN VV R R R R 00B No specification 01B 2 times 10B 4 times 11B 6 times Specifies the number of requests for starting a vvrite drain 00B 2 01B 4 10B 6 11B 8 24 User s Manual R
23. _STATE bit is set to 1 No command requests are accepted if the CMD_STATE bit is set to 0 busy upon command issuance After a command request is issued while the CMD_REQ_LOCK bit is set to 0 locked only requests for software commands are accepted When the deep power down mode is entered cancel the auto self refresh and CBR refresh for the target CS 34 User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS 3 2 16 Refresh setting register 1 This register MEMC DDR CONFIGR1 C00A 2014H individually specifies refresh cycles in external memory for CSO and CS1 31 30 29 28 27 26 25 24 CS1_REF_ CS1_REF_STOCK CS1_CBR_ CS1_REF_COUNT OVER SREF 23 22 21 20 19 18 17 16 CS1_REF_COUNT 15 14 13 12 11 10 9 8 CS0 REF CS0 REF STOCK CS0 CBR CS0 REF COUNT OVER SREF 7 6 5 4 3 2 1 0 CS0 REF COUNT CS1 REF OVER Indicates whether the number of times refreshes for CS1 still needs to be executed exceeds the maximum CS1 REF STOCK Indicates the number of times refreshes for CS1 still needs to be executed CS1 CBR SREF Specifies whether to forcibly execute a CBR refresh at least once when CS1 is in the self refresh mode CS1 REF COUNT Specifies the CS1 refresh timer counter value Refresh cycle RCLK refresh counter clock cycles x specified value CS0 REF OVER Indicates whether the number of times refreshes for CSO still needs to be executed exceeds the maximum CS0 REF STOCK 14 12 Indicates the number
24. ary information Numeric representation Binary XXXX or XXXXB or xxxb Decimal xxxx Hexadecimal xxxxH Data type Word 32 bits Halfword 16 bits Byte 8 bits All trademarks and registered trademarks are the property of their respective owners User s Manual R19UH0028EJ0500 5 Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such MC 10118A Data sheet R19DS0008EJ T u PD77630A Data nPD77630RDataSheet S19686E User s manual Audio Voice and PWM Interfaces R19UH0027EJ S19253E System Control General Purpose I O Interface R19UH0029EJ S19265E One Chip MC 10118A R19UH0030EJ S19598E S19687E old number Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document when designing 6 Users Manual R19UH0028EJ0500 CONTENTS CHAPTER T OVERVIEW M 10 LI Fears Li En UC 10 IP ZEE Id asric m XM 11 BC E Klee e VE 11 CHAPTER 2 PIN FUNCTIONS sss ormo genee oe esit acce ino me Ci Eed AEN 12 2 1 DDR SDRAM Interface Pins m ammeaamnanananamenamanamenaemammmanmmnaammmamenamerarenannrenenerenererre 12 CHAPTER 3 REGISTERS Eo eene Dee eege EES 13 S17 Ce ET 13 3 1 1 Request control registers and system cache setting registers sees e eee sseeenennnnn eil 13
25. bited CS1 STOCK MAX Specifies the maximum number of refreshes for CS1 Specifiable range 1 to 7 Specifying 0 is prohibited CS1_TIMER_RST R W 24 1B Specifies whether to reset CS1 REF COUNT CS1 REF STOCK and CS1 REF OVER 0 Reset This bit is automatically set to 1 during the next clock cycle Reserved SIE SES o a an Reserved When this bit is read 0 is returned COUNT COMMON RW Specifies whether to apply the auto refresh cycle for CSO to CS1 The counter for CS1 stops CS0 STOCK DRAIN R W 21 20 Specifies how many times a refresh is executed before CSO enters the self refresh mode Specifiable range 1 to 3 Specifying O is prohibited CS0 STOCK MAX R W 19 17 7H Specifies the maximum number of refreshes for CSO Specifiable range 1 to 7 Specifying O is prohibited 36 User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS 2 2 CS0 TIMER RST R W 16 1B Specifies whether to reset CSO_REF_COUNT CS0 REF STOCK and CS0 REF OVER 0 Reset This bit is automatically set to 1 during the next clock cycle CS1 SREF COUNT R W 15 10 1FH Specifies CS1 self refresh counter values Auto self refresh entry idle counter set value multiplied by 16 CS1 SREF AUTO R W Specifies whether to enable issuance of CS1 auto self refresh requests SREF 0 Disable 1 Enable CS1_REF_AUTO R W Specifies whether to enable issuance of CS1 auto refresh requests CBR 0 Disable 1 Enable CS0 SREF COUNT RW 7 2 1FH Specifies CSO self ref
26. crease performance and decrease power consumption The received read and write requests are held in queues in the MEMC scheduled so as to enhance the memory usage efficiency and issued to memory System cache read cache The MEMC has a system cache for temporarily storing data read from memory The read cache does not have dirty states If a read request hits this cache the request is not issued to memory As a result the latency while accessing memory is decreased and the number of memory accesses is reduced which decreases power consumption Users Manual R19UH0028EJ0500 1 2 1 3 CHAPTER 1 OVERVIEVV Block Diagram Figure 1 1 Block Diagram MEMC_CLK K System control External memory access control Internal system bus System cache DDR MCLK DDR MCLKB DDR DQN 3 0 DDR DQS 3 0 DDR WEB DDR CKE 1 0 DDR CSB 1 0 DDR RASZ DDR CASZ DDR A 13 0 DDR BA 1 0 DDR DATA 31 0 Terminology MEMC Mobile DDR SDRAM interface IMC Image composer SHXB Slow master AHB AXI bridge MHXB Media master AHB AXI bridge DHXB Display master AHB AXI bridge ADSPD Data bus for ADSP application DSP SPXK701 ADSPI Instruction bus for ADSP application DSP SPXK701 ACPU Application CPU ASMU System management unit Users Manual R19UH0028EJ0500 11 CHAPTER 2 PIN FUNCTIONS 2 1 DDR SDRAM Interface Pins aner ova ET TT TT oon sta ovat ciecen gal owatie oon os
27. cs Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd ZF No 363 Fu Shing North Road Taipei Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 1 harbourFront Avenue 06 10 keppel Bay Tower Singapore 098632 Tel 65 6213 0200 Fax 65 6278 8001 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 JIn Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2010 Renesas Electronics Corporation All rights reserved Colophon 1 0
28. dress 1 DDR SDRAM BA1 BAO A 13 0 A command that sets up an extended mode register is issued for external memory based on the address specified for the MODREG_EMRS bit A command that sets up an extended mode register is issued for external memory based on the address specified for the MODREG_MRS bit The address is fixed to OxFF FFFO When setting up a mode register and issuing the Initialize MRS or EMRS command set up this register as follows Initialize command MODREG_EMRS 2 b10 EMRS setting MODREG MRS 2 b00 MRS setting MRS command MODREG_EMRS 2 b00 MAS setting MODREG MRS 2 b00 any value EMRS command MODREG_EMRS 2 b10 EMRS setting MODREG MRS 2 b00 any value When issuing precharge commands set up this register as follows All bank precharge MODREG_MRS 10 bi Bank precharge MODREG MRS 15 14 Target bank address MODREG MRS 10 1 b0 Restriction and caution on command issuance e Requests to issue commands are ignored when the CMD STATE bit of the MEMC DDR CONFIGC2 register is set to 0 busy 32 User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS 3 2 15 Softvvare command issuance register 2 This register MEMC_DDR_CONFIGC2 C00A 2010H specifies the settings for controlling command issuance for external memory 31 30 29 28 27 26 25 24 Reserved Reserved Reserved CMD_STATE CMD_STATE CS1 CSO Reserved Reserved When these bits are read 0 is returned f
29. enesas Electronics General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied un
30. eo om o0 rem om mass ovat LT TT TT EE ene 1 om 0 Je bonsq 1 oma 0 amm CES vo Jomo Note To keep the DDR CHE pin level at 0 even if the MEMC is off the output buffer is allocated in a separate power domain Remark PD in Has a pull down resistor when in the input status 12 User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS 3 1 Registers The MEMC registers allovv vvord access only Do not access reserved registers An undefined value is returned for a read access Do not write any value other than 0 to reserved bits in each register 3 1 1 Request control registers and system cache setting registers Base address CO0A 0000H be mee CSC 000CH Reserved 0010H R mu aoU meroes regse kees R Lesen honan popu mertan sausose meve Aas A R omo onon uw pcrumensewederesse mevo menona al ba Tarraconense merona w 0028H Reserved Pm o Eo boss Jee r La Less Reserved 0070H 0080H 3 1 2 Memory request scheduler setting registers Base address CO0A 0000H Register Name Register Symbol After Reset 1000H Memory request scheduling mode register MEMC_REQSCH 0000_0000H Users Manual R19UH0028EJ0500 13 CHAPTER 3 REGISTERS 3 1 3 External memory control registers Base address CO0A 0000H 14 User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS 3 2 Register Functions 3 2 1 Cache prefetch setting register
31. etch data while reading data from the DHXB pee Prefetches data while reading data from the DHXB PRE DSPD 3 Does not prefetch data while reading data from the ADSPD pes Prefetches data while reading data from the ADSPD PRE DSPI 2 Does not prefetch data while reading data from the ADSPI pee Prefetches data while reading data from the ADSPI PRE ACPU Does not prefetch data while reading data from the ACPU Prefetches data while reading data from the ACPU EE Users Manual R19UH0028EJ0500 15 CHAPTER 3 REGISTERS 3 2 2 Function disabling register This register MEMC_DEGFUN C00A 0008H disables some of the MEMC functions 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DISCACHE INORDER Reserved R 31 2 oH Reserved When these bits are read 0 is returned for each bit DISCACHE R W 1 Disables the system cache 0 Enables use of the system cache 1 Disables use of the system cache INORDER R W 0 Issues read requests out of order 1 Issues read requests in order 16 User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS 3 2 8 ACPU interrupt status register This register MEMC_INTSTATUS_A C00A 0014H indicates the status of the interrupt sources for the ACPU 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 P
32. ferences in internal memory capacity and layout pattern When changing to products of different part numbers implement a system evaluation test for each of the products Readers Purpose Organization How to Read This Manual Conventions PREFACE This manual is intended for hardware software application system designers who wish to understand and use the DDR SDRAM interface functions of EMMA Mobile1 EM1 a multimedia processor for mobile applications This manual is intended to explain to users the hardware and software functions of the DDR SDRAM interface of EM1 and be used as a reference material for developing hardware and software for systems that use EM1 This manual consists of the following chapters e Chapter 1 Overview e Chapter 2 Pin functions e Chapter 3 Registers e Chapter 4 Usage It is assumed that the readers of this manual have general knowledge of electricity logic circuits and microcontrollers To understand the functions of the DDR SDRAM interface of EM1 in detail Read this manual according to the CONTENTS To understand the other functions of EM1 Refer to the user s manual of the respective module To understand the electrical specifications of EM1 Refer to the Data Sheet Data significance Higher digits on the left and lower digits on the right Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplement
33. g three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti
34. ies the start of automatic calibration 0 Calibration starts Delays can be added to each signal line by setting up this register The optimum delay values obtained by calibration are stored in the MEMC DDR CONFIGT3 register When the delay is adjusted using this register set the MEMCCLK270_SEL bit of the MEMCCLK270_SEL register to 1 in the ASMU User s Manual R19UH0028EJ0500 39 CHAPTER 3 REGISTERS 3 2 20 Automatic DQS timing adjustment register 2 This register MEMC DDR CONFIGT2 C00A 2024H specifies the automatic adjustment of delays in external memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 12 11 10 9 8 DQS2_DELAY 4 3 2 1 0 DQS3_DELAY After Reset Function Reserved R Reserved When these bits are read 0 is returned for each bit DQSO DELAY R W Optimizes the DQSO delay Reserved R i Reserved VVhen these bits are read O is returned for each bit DQS1 DELAY R W Optimizes the DQS1 delay R Reserved When these bits are read 0 is returned for each bit DQS2 DELAY Optimizes the DQS2 delay Reserved When these bits are read O is returned for each bit DQS3 DELAY Optimizes the DQS3 delay Delays can be added to each input DQS signal line by setting up this register 40 User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS 3 2 21 Automatic DQS timing adjustment register 3 This register MEMC DDR CONFIGT3 C00A 2028H stores the result of adjustment for automatic calibration
35. mand control By using the MEMC_DDR_CONFIGC2 register DDR SDRAM commands listed in Table 4 2 can be issued and refresh can be controlled e When setting a extended mode register of DDR SDRAM e Set the address of the command to be issued to DDR SDRAM by using the MEMC DDR CONFIGC1 register e Set the CMD SET bit of the MEMC_DDR_CONFIGC2 register to 1111B to write the mode register e Set the CMD_ENABLE bit to 0 at the same time the command is then issued e When issuing a precharge command e Set the target bank by using the MEMC_DDR_COFIGC1 register To precharge all banks set MODEREG MR S110 to 1 To precharge selected banks set MODEREG_MRS 10 to 0 and set the target bank address by using MODEREG_MRS 15 14 e Set the CMD_SET bit of the MEMC_DDR_CONFIGC2 register to 1001B to precharge banks e Set the CMD_ENABLE bit to 0 at the same time the command is then issued e When issuing other commands e Setting MEMC DDR CONFIG1 is unnecessary e Set the corresponding command by using the CMD_SET bit of the MEMC_DDR_CONFIGC2 register e Set the CMD_ENABLE bit to 0 at the same time the command is then issued Remark Commands are issued after processing of all requests If the CMD REQ LOCK bit has been set when a command is issued the subsequent requests other than those request for command issuance are held pending until the request lock is released with the CMD_REQ_LOCK bit Whether a command has been executed can be checked with the CMD_STA
36. mmand signals 0 Active 1 Hi Z tSREX R W 23 20 Specifies the period until returning from a self refresh tSREX 8 1 clock cycles Note tRFC R W 19 16 Specifies the period until returning from an auto refresh tRFC 8 clock cycles Reserved Reserved rR 15 13 oH _ Reserved When these bits are read O is returned for each bit Reserved When these bits are read 0 is returned for each bit LowFrqTyp R W 12 Switches the frequency range in the low frequency mode EGAN GK 0 30 MHz or less 1 30 MHz to 60 MHz DQS mask Ext RW ti Specifies whether to delay the input DQS mask timing by 0 5 clock cycles 0 Does not delay the timing 1 Delays the period DQS mask RW 10 9 00B Specifies how much the input DQS mask timing is delayed 00B 2 clock cycles 01B 2 5 clock cycles 10B 3 clock cycles 11B Reserved 30 User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS 2 2 R DQM HZ R W Specifies the state of the DQM signal for the I O buffer pe 0 Active 1 Hi Z IO HZ R W Specifies the state of the signal for the I O buffer 0 Active 1 Hi Z AutoPre R W Specifies whether to enable auto precharge 0 Does not enable auto precharge 1 Enables auto precharge CLK_MODE R W i Specifies the timing at vvhich read data is received 00B 2 clock cycle mode 01B 3 clock cycle mode 10B 1 clock cycle mode 11B Reserved PstamblExt R W Specifies whether to extend the period for which the DQS postamble is outp
37. n in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the followin
38. nce of interrupt requests for the ACPU Whether interrupt requests can be issued can be read from this register 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 Il Reserved ERREN SECERREN Reseved R aro o Reserved When these bits are read 0 is returned for each bit ERREN VV 1 Specifies whether to enable issuance of error interrupts other than the security error interrupt 0 Ignored 1 Enables the interrupt Indicates whether the issuance of error interrupts other than the security error interrupt is enabled 0 Disabled masked 1 Enabled SECERREN WwW Specifies whether to enable issuance of the security error interrupt 0 Ignored 1 Enables the interrupt Indicates whether the issuance of the security error interrupt is enabled 0 Disabled masked 1 Enabled Users Manual R19UH0028EJ0500 19 CHAPTER 3 REGISTERS 3 2 6 ACPU interrupt enable clear register This register MEMC INTENCLR A C00A 0020H masks disables the issuance of interrupt requests for the ACPU Whether such issuance is masked can be determined by reading the MEMC_INTSET_A register 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 lI Reserved ERRMASK SECERRMASK Reseved R ara o Reserved When these bits are read 0 is returned for each bit ER
39. o Reserved When these bits are read 0 is returned for each bit MID 7 0 Retains the ID master ID AXI ID when an error has occurred These bits are not overwritten by the master ID of a new error until the current information is cleared by setting the CLEAR bit of MEMC_ERRADR 22 User s Manual R19UH0028EJ0500 CHAPTER 3 REGISTERS 3 2 9 Error address register This register MEMC ERRADR C00A 006CH retains the type of error and the address at which the error occurred 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR 15 14 13 12 11 10 9 8 ADDR 7 6 5 4 3 2 1 0 ADDR ERR ai CLEAR VV 31 DH Specifies vvhether to clear the retained address 0 Ignored 1 Clears the address If an error occurs after this the new address is retained Indicates whether a new error address can be retained 0 A new address can be retained when an error occurs 1 A valid address is retained so a new address is not retained RDWT 30 Indicates whether the request that caused an error was for a read or write 0 Read 1 Write Reserved R 29 28 om Reserved When this bit is read O is returned ADDR 27 3 DH The value of bits 28 to 3 of the address at vvhich a request caused an error is retained ERR 2 0 000B Indicates what type of error a request caused 000B No error 011B An address outside the mounted range was requested 010B Illegal burst size A burst size larger than 64 bits was specified 011B ARB
40. of times refreshes for CSO still needs to be executed CS0 CBR SREF R W 11 1B Specifies whether to forcibly execute a CBR refresh at least once when pu CS0 is in the self refresh mode CS0 REF COUNT RW 10 0 7FFH Specifies the CSO refresh timer count value Refresh cycle RCLK refresh counter clock cycles x specified value The refresh counter is incremented during each refresh cycle by the REF_STOCK counter A refresh is executed when the self refresh mode is entered or when the refresh counter reaches the threshold User s Manual R19UH0028EJ0500 35 CHAPTER 3 REGISTERS 3 2 17 Refresh setting register 2 This register MEMC_DDR_CONFIGR2 C00A 2018H specifies the settings for a refresh in external memory 31 30 29 28 27 26 25 24 Reserved STOCK CS1 STOCK DRAIN CS1 STOCK MAX CS1 TIMER E tmo mmm PTT 23 22 21 20 19 18 17 16 Reserved COUNT CS0 STOCK DRAIN CS0 STOCK MAX CS0 TIMER a eee po mew qm CS1 SREF COUNT CS1 SREF CS1 REF AUTO AUTO CS0 SREF COUNT CS0 SREF CS0 REF AUTO AUTO 1 2 Reserved Reserved When this bit is read O is returned STOCK DRAIN TYP Specifies whether to decrement the refresh counter whether to execute CBR when no read request is being received and the number of write requests is the write buffer drain threshold value or lower CS1 STOCK DRAIN Specifies how many times a refresh is executed before CS1 enters the self refresh mode Specifiable range 1 to 3 Specifying O is prohi
41. or each bit CMD_STATE CS1 Indicates the execution status of a command requested by CS 0 Busy 1 Standby CMD STATE CSO Indicates the execution status of a command requested by CS 0 Busy 1 Standby CMD REQ LOCK Specifies the signal to lock any request other than for command issuance 0 Lock 1 Unlock CMD ENABLE Specifies whether to issue a command request 0 Requests command issuance This bit is automatically set to 1 during the next clock cycle CS1 TARGET Sets the command request flag for CS1 0 Does not set the flag 1 Sets the flag CS0 TARGET Sets the command request flag for CSO 0 Does not set the flag 1 Sets the flag User s Manual R19UH0028EJ0500 33 CHAPTER 3 REGISTERS 2 2 CMD SET R W 3 0 DH Specifies the control command 0111B Disables the CRE signal 1000B Executes the DDR SDRAM initialization sequence 1001B Precharges all banks 1010B Executes a CBR refresh 1011B Shifts to the self refresh mode 1100B Shifts to the deep power down mode 1101B Enables the CKE signal 1110B Reads from the extended mode register 1111B Writes to the extended mode register The command specified by the CMD_SET bit can be issued if a command code is specified for the target memory at the same time as the CMD_ENABLE bit is set to 0 in this register The memory assigned to CSO and CS1 can be specified as target memory at the same time Before setting the CMD_ENABLE bit make sure that the CMD
42. resh counter values Auto self refresh entry idle counter set value multiplied by 16 CS0 SREF AUTO R W 1 Specifies whether to enable issuance of CS0 auto self refresh requests SREF 0 Disable 1 Enable CS0 REF AUTO RW Specifies whether to enable issuance of CSO auto refresh requests CBR 0 Disable 1 Enable The refresh counter is incremented during each refresh cycle by the REF_STOCK counter A refresh is executed when the self refresh mode is entered or when the refresh counter reaches the threshold When the REF_STOCK counter exceeds the maximum value the CS0 1 REF OVER bits of the MEMC_DDR_CONFIGR1 register are set to 1 Users Manual R19UH0028EJ0500 37 CHAPTER 3 REGISTERS 3 2 18 Refresh setting register 3 This register MEMC DDR CONFIGR3 C00A 201CH specifies the settings for a refresh in external memory 31 30 29 28 27 26 25 24 Reserved Reserved CS1 APD COUNT Reserved CS1_APD_ AUTO CS0 APD COUNT Reserved CS0 APD AUTO Function Bit Reserved R 0H Reserved When these bits are read 0 is returned for each bit CS1 APD COUNT R W 3FH Specifies the automatic CS1 power down counter value the idle counter value Reserved R 0B Reserved When this bit is read 0 is returned CS1_APD_AUTO R W 0B Specifies whether to request an automatic CS1 power down 0 Normal operation 1 Requested CS0 APD COUNT ua Specifies the automatic CSO power down counter value the idle counter value
43. s returned CS0 DOUBLE Indicates whether two CSO chips 16 bit bus chip x 2 may be used 0 Not used 32 bit bus chip x 1 1 May be used 16 bit bus chip x 2 CS0 DENSITY Specifies the memory size of CSO 00B 128 Mb 01B 256 Mb 10B 512 Mb 11B 1 Gb 0 Non JEDEC 1 JEDEC Specifies whether to enable access to CSO memory 0 Disables access 1 Enables access Users Manual R19UH0028EJ0500 25 CS0 JEDEC CS0 ENABLE R W CHAPTER 3 REGISTERS Bank addressing can be changed individually for CSO and CS1 DDR SDRAM assigns bank addresses to column addresses consecutively and reads out up to 4 KB of data in succession However because memory is separated into banks data cannot be read consecutively when using the partial refresh function a function for retaining only specific data in memory and consecutiveness in memory areas that must be maintained is not assured Specify settings by using this register to avoid this problem Table 3 1 shows an example of address assignment and Figure 3 1 shows an overview of the mapping 26 CONFIG 7 0 1Gb 16 Jx2 Ox1F 4Bank Ox5F 2Bank 1Gb 32 J or 512Mb 16 Jx2 0x0F 4Bank 0x4F 2Bank 1Gb 32 N or 512Mb 16 Nx2 0x0D or 0x19 4Bank 0x4D or 0x59 2Bank 512Mb 32 J or 256Mb 16 Jx2 0x15 4Bank 0x55 2Bank 512Mb 32 N or 256Mb 16 Nx2 0x09 4Bank 0x49 2Bank 256Mb 32 J or 128Mb 16 x2 0x11 4Bank 0x51 2Bank 256Mb 32 N 0x05 4Bank 0x45 2Bank al 2 28 2
44. t such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for R
45. til the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to one with a different part number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different part numbers may differ because of the dif
46. tion is executed ACK is returned after execution When a CBR refresh request is received a CBR refresh is executed after the clock frequency is switched When a clock frequency switch request is received while the MEMC is exiting the self refresh mode the clock frequency is switched immediately after the self refresh mode is exited 44 User s Manual R19UH0028EJ0500 CHAPTER 4 USAGE Figure 4 1 Timing at Which MEMC CLR Operating Frequency Is Switched Sequence for changing the clock frequency from high to low MEMC_CLK DDR module clock ASMU_CLKCH_REQ Switch request signal from ASMU DDR_CLKCH_ACK Switch enable signal from DDR module ASMU_CLKFRQ ASMU_CLKFRQA Normal Half Quarter recognition signal CLK_REQ TO T 33 MHz or 66 MHz Normal mode Sequence for changing the clock frequency from low to high MEMC_CLK DDR module clock ASMU_CLKCH_REQ DDR_CLKCH_ACK ASMU_CLKFRQ ASMU CLKFRQA CKE CLK REQ TO T1 Level before switching is maintained If low DDR SDRAM is in self refresh mode several hundred ns T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 TV Normal mode 4 1 3 Clock Phase Control Addresses and commands are issued when MEMC CLK is shifted by 1809 At least 1 us is required in quarter mode Level before switching is maintaine d At least 800 ws is required when the main PLL is
47. ut during a write by 0 5 clock cycles 0 Does not extend the period 1 Extend the period PreamblExt R W Specifies whether to extend the period for which the DQS preamble is output during a write by 0 5 clock cycles 0 Does not extend the period 1 Extend the period DBParkEna R W Specifies whether to drive DQ or DQS to low level while DDR SDRAM is in the Hi Z state 0 Hi Z control 1 Drive to low level for periods other than the period when data is valid o Reserved When this bit is read O is returned Remark Because the same AC parameters are applied to CSO and CS1 devices whose AC timing specifications differ cannot be connected to CSO and CS1 at the same time Note The maximum of tSREX which can be put at the time of DDR333 166MHz movement is 6ns x 15 8 1 132 ns SDRAM with any more min standard can t be connected Users Manual R19UH0028EJ0500 31 CHAPTER 3 REGISTERS 3 2 14 Software command issuance register 1 This register MEMC DDR CONFIGC1 CO0A 200CH specifies addresses and data when the extended mode register is set up for external memory 31 30 29 28 27 26 25 24 MODREG_EMRS 23 22 21 20 19 18 17 16 MODREG_EMRS 15 14 13 12 11 10 9 8 MODREG MRS N o 63 ES wo N Er o MODREG MRS MODREG EMRS R W 31 16 4040H Specifies mode register setting command issuance address 2 DDR SDRAM BA1 BAO A 13 0 MODREG MRS R W 15 0 0003H Specifies mode register setting command issuance ad
Download Pdf Manuals
Related Search