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MC9S12XE Family Product Brief

1. e Real time interrupt for task scheduling purposes or cyclic wake up e Can be active in Pseudo Stop mode for low power precision timing tasks 2 5 15 Asynchronous Periodic Interrupt API e Available in all modes including Full Stop mode e Trimmable to 10 accuracy e Time out periods range from 0 2ms to 13s with a 0 2ms resolution 2 5 16 Pulse Width Modulator PWM e 8 channel x 8 bit or 4 channel x 16 bit Pulse Width Modulator e Programmable period and duty cycle per channel e Center or left aligned outputs e Programmable clock select logic with a wide range of frequencies e Fast emergency shutdown input 2 5 17 Multi scalable Controller Area Networks MSCAN e Up to five MSCAN modules e CAN 2 0 A B software compatible Standard and extended data frames 0 8 bytes data length Programmable bit rate up to 1 Mbps e Five receive buffers with FIFO storage scheme e Three transmit buffers with internal prioritization MC9 12XE Family Product Brief Rev 7 10 Freescale Semiconductor Features Flexible identifier acceptance filter programmable as 2x 32 bit 4x 16 bit 8x 8 bit Wake up with integrated low pass filter option Loop back for self test Listen only mode to monitor CAN bus Bus off recovery by software intervention or automatically 16 bit time stamp of transmitted received messages FULL CAN capability when used in conjunction with XGATE 2 5 18 Serial Peripheral Interface SPI Up
2. Freescale Semiconductor Inc 2008 All rights reserved 2 freescale semiconductor
3. ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number MC9S12XEPB Rev 7 05 2008 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Se
4. 7 Features 2 9 9 System Integrity Support Power on reset POR Illegal address detection with reset Low voltage detection with interrupt or reset System can run in Supervisor or User state using a new bit in the condition code register peripheral space can only be accessed in user state if enabled by a descriptor Computer Operating Properly COP watchdog Configurable as window COP for enhanced failure detection Can be initialized out of reset using option bits located in Flash Clock monitor supervising the correct function of the oscillator Memory Options 128K 256K 384K 512K 768K and 1M byte Flash 2K 4K byte Emulated EEPROM 12K 16K 24K 32K 48K and 64K Byte RAM Flash General Features 64 data bits plus 8 syndrome ECC Error Correction Code bits allow single bit failure correction and double fault detection Erase sector size 1024 bytes Automated program and erase algorithm Security option to prevent unauthorized access Sense amp margin level setting for reads Data Flash General Features 32 Kbytes of D Flash memory with 256 byte sectors for user access Dedicated commands to access D Flash memory over EFE operation Single bit fault correction and double fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Ability to pro
5. Inc 2008 All rights reserved ie Contents Application Examples oo ovsdiukecvesdee due ceusades 2 1 1 Body Controller Application Example 2 1 2 Gateway Application Example 3 TOELT e EEEN 0944 HE E ae ee ae ee oA 4 Bl BiOGK DQG 442 9444 6895560500505 clade a2 4 2 2 Peripheral and Memory Options S 12XE Family 5 2 3 Critical Performance Parameters 6 2 4 Chip Level Features 0 00000 aee 6 2 5 Module Features lt oc 5cdceteeiciecedeciawdas z Developer Environment nsss nasaan aranna 12 Document Revision History anaana aaaea aaa 14 2 freescale semiconductor Application Examples Like members of other 12X families the S12XE Family will run 16 bit wide accesses without wait states for all peripherals and memories The S12XE Family features an enhanced version of the performance boosting XGATE co processor which is programmable in C language and runs at twice the bus frequency of the 12X with an instruction set optimized for data movement logic and bit manipulation instructions and which can service any peripheral module on the device The new enhanced version has improved interrupt handling capability and is fully compatible with existing XGATE module As with the S12XD Family the S12XE Family features an enhanced MSCAN module which when used in conjunction with XGATE delivers FULL CAN performance with virtually unlimited number of mailboxes a
6. Test Entry Interrupt Module PEO MPU PE1 gt Memory Protection PE2 Ba 8 regions PE3 LU LSTRB LDS PE4 gt h ECLK PE5 gt MODA TAGLO RE PE6 Iai MODB TAGHI PE7 me XCLKS ECLKX2 EWAIT O PK 7 0 x W ADDR 22 16 Y lt j a PA 7 0 E j ADDR 15 8 5 D E a Lu PBI7 0 lt gt F ADDR 7 0 P x i O PC 7 0 E j DATA 15 8 z Z O PD 7 0 ai K DATA 7 0 PFO PF1 lt PF2 DE PF3 x a PF5 Ra SC Inter IC Module PF6 bal RX SCI3 PF7 TXD Asynchronous Serial IF lt XGATE ATDO 8 10 12 bit 16 channel ANI15 0 Analog Digital Converter ATD1 8 10 12 bit 16 channel ANI15 0 Analog Digital Converter ECT 16 bit 8 channel IOC 7 0 Enhanced Capture Timer TIM 16 bit 8 channel lOC 7 0 Timer PWM 8 bit 8 channel PWM 7 0 Pulse Width Modulator SCIO RXD Asynchronous Serial IF TXD SCI1 RXD Asynchronous Serial IF TXD SPIO pts Pem Synchronous Serial IF SPI1 Synchronous Serial IF SPI2 PTH Wake up Int Synchronous Serial IF S msCAN 2 0B TXCAN msCAN 2 0B TXCAN msCAN 2 0B TXCAN msCAN 2 0B TXCAN Asynchronous Serial IF TXD Asynchronous Serial IF TXD Asynchronous Serial IF TXD Asynchronous Serial IF TXD RX SCI2 Asynchronous Serial IF TX IIC1 SDA Ba Inter IC Module SCL pig pJ CAN4 msCAN 2 0B Figure 3 MC9S12XE Block Diagram MC9S12XE Family Product Brief Rev 7 Freescale Semiconductor PAD 15 0 PAD 31 16 PT 7 0 PRI7 0 PP 7 0 P
7. Wide single supply voltage range 3 3V 5 10 to 5 0V 10 at full performance Separate supply for internal voltage regulator and I O allow optimized EMC filtering 50MHz maximum CPU bus frequency 100MHz maximum XGATE bus frequency e Ambient temperature range 40 C to 125 C e Temperature Options 40 C to 85 C 40 C to 105 C 40 C to 125 C 2 3 2 Package Options e 208 pin MAPBGA 17mm x 17mm body size case no 1159A 01 issueB e 144 pin low profile quad flat pack LQFP 20x20mm body size 0 5mm pitch case no 918 03 e 112 pin low profile quad flat pack LQFP 20x20mm 0 65 pitch case no 987 e 80 pin quad flat pack QFP 14x14mm body 0 65mm pitch case no 841B 2 4 Chip Level Features On chip modules include the following features e Pin compatible family extends existing S12D Family e 16 bit CPUI2X e Enables higher system integrity at the MCU level MPU ECC Supervisor Mode e Enhanced SPI allows 8 or 16 bit data size e ECC on flash bit fault correction 2 bit fault detection e Improved EMC performance Separate supply for internal voltage regulator and I O allow optimized EMC filtering e Enhanced current consumption MC9S12XE Family Product Brief Rev 7 6 Freescale Semiconductor 2 9 Features Extended API up to 5 sec Module Features The following sections provide more details of the modules implemented on the MC9S12XE 2 5 1 2 5 3 Freescale Semicondu
8. have SCIO SCI1 SCI2 SCI38 SCl4 SCI5 and SCI6 Versions with 6 SCI modules will have SCIO SCI1 SCI2 SCI38 SCl4 and SCI5 Versions with 5 SCI modules will have SCIO SCI1 SCI2 SCI3 and SCI4 Versions with 4 SCI modules will have SCIO SCl1 SCl2 and SCI4 Versions with 3 SCI modules will have SCIO SCI1 and SCl2 Versions with 2 SCI modules will have SCIO and SCI1 Versions with 1 SCI module will have SCIO 3 SPI Options Versions with 3 SPI modules will have SPIO SPI1 and SP12 Versions with 2 SPI modules will have SPIO and SPI1 Versions with 1 SPI modules will have SPIO 4 IIC Options Versions with 2 IIC modules will have IICO and IIC1 Versions with 1 IIC module will have IICO A D is the number of modules total number of A D channels 6 1 O is the sum of ports capable to act as digital input or output For details see the Port Availability by Package Option table in the MCS12XE Data Sheet N MC9S12XE Family Product Brief Rev 7 Freescale Semiconductor 5 Features For additional flexibility especially for the low pin count packages several I O functions can be routed under software control to different pins For details see the Peripheral Port Routing Options in the MCS12XE Data Sheet 8 Internal only not bonded out Can only execute code from RAM 2 3 Critical Performance Parameters The following describes the critical operating parameters of the MCU 2 3 1 Operating Conditions e
9. source vreg 0 Ohm resistor going from test to ground Ground points Kit includes USB cable CodeWarrior CD 9S12XDP512 Service Pack CD EVB9S12X Evaluation Board User Manual SofTec System Software CD Status Available Now MC9S12 Code Warrior Development System gt S12X Service Pack contains CodeWarrior for OSEK Sophisticated project manager Build system with optimizing C C compiler Graphical source level debugger Fast cycle accurate simulator Code coverage and profile analysis Flash programmer Evaluation Kit for MC9S12DT256 Evaluation board BDI interface Power supplies and cables Metrowerks OSEK Real Time Operating System demo Documentation package MC9S12XE Family Product Brief Rev 7 Freescale Semiconductor 13 Document Revision History Table 2 Tools Suppliers Name Tool IDE Compiler Debugger Simulator Emulator BDM Conn conr TX TX P amp E Microcomputer Systems Inc Drivers e LIN 1 3 Master Driver S12X LIN 2 0 Master Driver 812X including XGATE e CAN Driver S12X including XGATE This includes COM and NM for specific OEM configuration 3Soft e O HIS Drivers LIN 2 0 Master and Slave Drivers ProOSEK for 812X e LIN Drivers For S12 available and compatible for S12X 4 Document Revision History Table 3 shows the revision history of this document Table 3 Revision History Location s Substantive Chang
10. Freescale Semiconductor Product Brief Document Number MC9S12XEPB Rev 7 05 2008 This document contains preview information on a new product that may be in a design phase or under development Freescale reserves the right to change or discontinue this product without notice MC9S12XE Family Product Brief 16 Bit Microcontroller Family with Enhanced System Integrity Features The new MC9S12XE Family of microcontrollers takes the innovation of today s MC9S12XD Family a step further with the introduction of new features to deliver enhanced system integrity and greater functionality These new features include a Memory Protection Unit MPU and Error Correction Code ECC on the Flash memory together with enhanced EEPROM functionality EEE an enhanced XGATE a Frequency Modulated Phase Locked Loop IPLL and a faster ATD The E Family will extend the S12X product range up to IMB of Flash memory with increased I O capability in the 208 pin version of the flagship MC9S12XEP100 Targeted at automotive multiplexing and generic auto body applications S12XE Family will deliver 32 bit performance with all the advantages and efficiencies of a 16 bit MCU It will retain the low cost power consumption EMC and code size efficiency advantages currently enjoyed by users of Freescale s existing 16 bit S12 and S12X MCU families There is a high level of compatibility between the S12XE and 12XD families Freescale Semiconductor
11. LS CAN Body Digital Outputs PWM or not Analog Inouts Diagnostic HS CAN Powertrain HS CAN Diagnostic LIN LIN Figure 1 Body Controller Application Example 1 2 Gateway Application Example In this application the MC9S12XE provides gateway functionality between its on chip CAN and LIN modules Much of the low level communications functionality is handled by the XGATE which frees the CPU to manage higher level communications and other direct connections to the module LS CAN Body M 2 Digital Inputs HS CAN Telematics Digital Outputs PWM or not HS LS CAN Chassis SCI LIN HS CAN Powertrain HS CAN Diagnostic SCI LIN LIN LIN Figure 2 Gateway Application Example MC9S12XE Family Product Brief Rev 7 Freescale Semiconductor 3 Features 2 Features Features of the S12XE Family are described in this section 2 1 Figure 3 shows a top level block diagram of the S12XE Family 128K 1M bytes Flash 12K 64K bytes RAM 2K 4K bytes EEPROM Block Diagram VDDR VDD1 VDDE Voltage Regulator VDDPLL CPU12X Debug Module BKGD Debug Module 2 data breakpoints 512 Byte Trace Buffer EXTAL Amplitude Controlled Clock Monitor Low Power Pierce or COP Watchdog Full drive Pierce Periodic Interrupt ATAS Oscillator Async Periodic Int PLL with Frequency PIT Modulation option 8ch 16 bit Timer RESET Reset Generation Enhanced Multilevel TEST and
12. SO PS1 PS2 PS3 PS4 PS5 PS6 PS7 PHO PH1 PH2 PH3 PH4 PH5 PH6 PH7 PMO PM1 PM2 PM3 PM4 PM5 PM6 PM7 PLO PL1 PL2 PL3 PL4 PL5 PL6 PL7 PJO PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 Features 2 2 Peripheral and Memory Options 12XE Family Table 1 Peripheral and Memory Options of 12XE Family Members se __ me a s 8 3 2 ach ach ach 282 152 asiexEP100 Taare 5 8 3 2 8ch Bch 8ch 2 24 119 m o s e s 4 ecm 0 ach s e 3 2 een ch ach 232 152 0S 12XEP768 gt e 3 2 ech ach ach 224 119 768K 48K ane s e s 4 ecm 0 ach are ot a e 3 2 ecm 0 ach ara 19 estanensia tare 4 6 a a 0 ae va oF fren a e s 4 e o ach a8 rape pa pe pak 0 aan fame 118 9s12xEase4 Haare a 6 3 1 ach o an 91 384k a e s a e 0 an ve 59 Ps 4 3 1 en 0 ach 224 1m9 01 2XET256 ete jig s e s 1 ech o ach ve sanea ee e ee e eek o a l a E eae e fe e eao a e 2k iN A NOTES 1 CAN Options Versions with 5 CAN modules will have CANO CAN1 CAN2 CAN3 and CAN4 Versions with 4 CAN modules will have CANO CAN1 CAN2 and CAN4 Versions with 3 CAN modules will have CANO CAN1 and CAN4 Versions with 2 CAN modules will have CANO and CAN4 Versions with 1 CAN module will have CANO SCI Options Versions with 8 SCI modules will have SCIO SCI1 SCI2 SCI38 SCl4 SCI5 SCI6 and SCI7 Versions with 7 SCI modules will
13. ctor 16 Bit CPU12X 16 bit CPU12X Compatible with MC9S12 instruction set with the exception of five fuzzy instructions MEM WAV WAVR REV REY W which have been removed Enhanced indexed addressing Access to large data segments independent of PPAGE Enhanced Interrupt Module Eight levels of nested interrupts Flexible assignment of interrupt sources to each interrupt level External non maskable high priority interrupt XIRQ Internal non maskable high priority memory protection unit interrupt Up to 24 pins on ports J H and P configurable as rising or falling edge sensitive XGATE Programmable high performance I O coprocessor module with up to 100 MIPS RISC performance Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states Performs logical shifts arithmetic and bit operations on data Can interrupt the 12X CPU signalling transfer completion Triggers from any hardware module as well as from the CPU possible Two interrupt levels to service high priority tasks Enables Full CAN capability when used in conjunction with MSCAN module Full LIN master or slave capability when used in conjunction with the integrated LIN SCI modules Memory Protection Unit MPU 8 address regions definable per active program task Address range granularity as low as 8 bytes Protection Attributes No write No execute Non maskable interrupt on access violation MC9 12XE Family Product Brief Rev
14. e s on page 2 Added block diagrams and introductory text for application example on page 3 Added block diagrams and introductory text for application example on page 4 Added VREG block and 208MBGA to Figure 3 various Made a number of typographical and editorial changes on page 4 Replaced high level block diagram with detailed block diagram on page 5 Added Table 1 on page 7 Added Table 2 various Replaced future tense with present tense on page 5 Corrected corrupted footnote font in Table 1 on page 7 Added dataflash column to Table 2 on page 7 Changed CPU compatibility text following removal of fuzzy instructions MC9S12XE Family Product Brief Rev 7 14 Freescale Semiconductor Document Revision History MC9S12XE Family Product Brief Rev 7 Freescale Semiconductor 15 THIS PAGE INTENTIONALLY BLANK How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters
15. gram up to four words in a burst sequence Emulated EEPROM General Features Automatic EFE file handling using internal Memory Controller Automatic transfer of valid EEE data from D Flash memory to buffer RAM on reset Ability to monitor the number of outstanding EEE related buffer RAM words left to be programmed into D Flash memory Ability to disable EEE operation and allow priority access to the D Flash memory Ability to cancel all pending EEE operations to allow priority access to the D Flash memory MC9S12XE Family Product Brief Rev 7 Freescale Semiconductor Features 2 5 7 Oscillator OSC LCP e Loop Control Pierce oscillator utilizing a 4MHz to 16MHz crystal e Good noise immunity e Full swing Pierce option utilizing a 2MHz to 40MHz crystal e Transconductance sized for optimum start up margin for typical crystals 2 5 8 Clock and Reset Generator CRG e Phase locked loop IPLL clock frequency multiplier Internally filtered No external components required Configurable option to spread spectrum for reduced EMC radiation frequency modulation e Fast wake up from STOP in self clock mode for power saving and immediate program execution 2 5 9 Non Multiplexed External Bus 208 pin and 144 pin packages only e Up to four chip select outputs to select 16K 1M 2M and up to 4M byte address spaces Each chip select output can be configured to complete transaction on either the time out of one of the tw
16. miconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners
17. nd retains backwards compatibility with the MSCAN module featured on existing S12 products The S12XE Family has full 16 bit data paths throughout The non multiplexed expanded bus interface available on the 144 pin versions allows an easy interface to external memories In addition to the I O ports available in each module up to 25 further I O ports are available with interrupt capability allowing wake up from STOP or WAIT mode The S12XE Family is available in 208 Pin MAPBGA 144 pin LQFP both with optional external bus 112 pin LQFP or 80 Pin QFP options 1 Application Examples The following sections describe target applications of the MC9S12XE 1 1 Body Controller Application Example In this example the MC9S12XE 1s implementing the features of a typical car body controller application The module interfaces with the main CAN buses distributed in the car using the on chip MSCAN module whereas the LIN bus communicates with functions local to the body controller In both cases the communication functions are managed by the XGATE independently of the CPU The MC9S12XE provides direct control of power drivers for lights and pumps and reading of sensors using the on chip PWM and ATD modules Finally the SPI interface to the RF receiver provides the interface to the car remote access system MC9S12XE Family Product Brief Rev 7 2 Freescale Semiconductor Application Examples Digital Inputs including Input Capture signals
18. o wait state generators or the deassertion of EWAIT signal e Supports glue less interface to popular asynchronous RAMs and Flash devices 2 5 10 Analog to Digital Converter ATD e Up to two independent ATD converters e 8 10 12 bit resolution e Multiplexer for 16 analog input channels e 3us 10 bit single conversion time e Left right signed unsigned result data e External and internal conversion trigger capability e Internal oscillator for conversion in Stop modes e Wake up from low power modes on analog comparison gt or lt match 2 5 11 Enhanced Capture Timer ECT e 8x 16 bit channels for input capture or output compare e 16 bit free running counter with 8 bit precision prescaler e 16 bit modulus down counter with 8 bit precision prescaler e Four 8 bit or two 16 bit pulse accumulators e Four channels have enhanced input capture capabilities Delay counter for noise immunity 16 bit capture buffer MC9S12XE Family Product Brief Rev 7 Freescale Semiconductor 9 Features 8 bit pulse accumulator buffer 2 5 12 Timer TIM e 8x 16 bit channels for input capture or output compare e 16 bit free running counter with 8 bit precision prescaler e One 16 bit pulse accumulator 2 5 13 Periodic Interrupt Timer PIT e Up to 8 timers with independent time out periods e Time out periods selectable between 1 and 2 4 bus clock cycles e Time out interrupt and peripheral triggers 2 5 14 Real Time Interrupt RTI
19. to three SPI modules Configurable 8 or 16 bit data size Full duplex or single wire bidirectional Double buffered transmit and receive Master or Slave mode MSB first or LSB first shifting Serial clock phase and polarity options 2 5 19 Serial Communication Interfaces SCI Up to eight SCI modules Full duplex or single wire operation Standard mark space non return to zero NRZ format Selectable IrDA 1 4 return to zero inverted RZI format with programmable pulse widths 13 bit baud rate selection Programmable character length Programmable polarity for transmitter and receiver Receive wake up on active edge Break detect and transmit collision detect supporting LIN 2 5 20 Inter IC Module IIC Up to two IC modules Compatible with Inter IC Bus standard Multi master operation Software programmable for one of 256 different serial clock frequencies Broadcast mode support MC9S12XE Family Product Brief Rev 7 Freescale Semiconductor 14 Developer Environment e 10 bit address support 2 5 21 Background Debug BDM e Background debug module BDM with single wire interface Non intrusive memory access commands Supports in circuit programming of on chip non volatile memory Supports security 2 5 22 Debugger xDBG e Four comparators A B C and D Each can monitor CPU or XGATE buses A and C compares 23 bit address bus and 16 bit data bus with mask register B and D compares 23 bit address bus onl
20. y Three comparator modes exact address match inside address range or outside address range e 64x 64 bit circular trace buffer to capture change of flow addresses or address and data of every access e Tag type or force type hardware breakpoint requests 2 5 23 On Chip Voltage Regulator VREG e Two parallel linear voltage regulators with bandgap reference e Low voltage detect LVD with low voltage interrupt LVI e Power on reset POR circuit e 3V and SV range operation e Low voltage reset LVR 2 5 24 Input Output e Upto 152 general purpose input output I O pins and 2 input only pins e Hysteresis and configurable pull up pull down device on all input pins e Configurable drive strength on all output pins 3 Developer Environment The S12XE Family of MCUs supports similar tools and third party developers as other Freescale S12X products offering a widespread established network of tools and software vendors Available support includes S12X Evaluation Board e Full standardized header ring for all pins except Oscillator and PLL MC9S12XE Family Product Brief Rev 7 12 Freescale Semiconductor Developer Environment 6 LIN Interfaces 2 RS232 2 Interfaces 3 CAN Interfaces Power Supply Connector Prototyping area USB BDM and USB2BDM interface Daughter boards with 144 112 and 80 pin devices Canned Oscillator Pierce Oscillator provision Reverse polarity protection Configuration jumpers mode pins clock

MC9S12XE Family Product Brief

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