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ECED 3204. Microprocessors - Myweb.dal.ca

1. Data Valid Data Ha d 4 b Pulse mode Dalhousie University 176 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Output Handshake Protocol Step 1 The interface unit places data on the port pins and asserts or pulses H1 to indicate that it has valid data to be output Step 2 The output device latches the data and asserts or pulses H2 to acknowledge the receipt of data Step 3 The interface unit de asserts H1 following the assertion of H2 The output device then de asserts H2 a Interlocked 8 2 Data Valid Data oo b Pulse Mode Dalhousie University 177 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Parallel UO Control Register PIOC All strobed mode and handshake are controlled by this register T 6 5 4 3 2 1 0 1002 0 0 0 0 U 1 1 Upon RESET 0 STAF Strobe A flag This bit is set when a selected edge occurs on the STRA signal STAI Strobe A interrupt enable When STAF STAI 1 an interrupt is requested to the CPU CWOM Port C wired or mode 0 All port C outputs are normal CMOS outputs 1 All port C outputs act as open drain outputs Handshake simple strobe mode select OIN Output input handshake 0 simple strobe mode 0 input handshake 1 handshake mode 1 output handshake Pulse interlocked handshake operation 0 interlocked handshake selected 1 pulse handshake selected Active edge for STRA Invert STR
2. HC11 output PortB and bidirectional PortC Seven segment displays e Hardware issues Using 11 ports to light 7 segment LED displays Controlling multiple 7 segment displays e Software issues Light patterns for digits to be displayed Table lookup Conversion of 16 bit hex format BCD format ASCII coded decimal format Strobe and handshake subsystem Design and service of parallel I O ports external to the HC1 1 Laboratory 7 Seven segment LED displays 7 Course Review 8 Final Exam Dalhousie University 7 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introduction to the Course Course Assessment Biweekly Quizzes MidTerm Exam EndofTerm Exam Dalhousie University 8 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics What is a computer An Electronic Device operating under Control of Instructions Software stored in its own Memory Unit part of its Hardware 1 Accepts Data Input 2 Processes Data Arithmetically Logically 3 Displays Information from the processing Output 4 Stores results for future use Dalhousie University 9 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Block Diagram of the Basic Computer System Computer System Processor Dalhousie University Connected Devices keyboard mouse display printer disk drives comm links etc Jose A Gonzalez Cueto ECED 3204 Mic
3. Dalhousie University 16 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics ASCII Chart ASCII CHARACTER SET 7 Bit Code I t tO CO J O GQ N OzzZrzXc rommoou r G o 3 3 lw NX XK Se Ce HAAS 0 1 2 3 4 5 6 7 8 9 A B C D E F VIAS Noa Dalhousie University 17 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Numeric Systems 1101 1000 sun 1000 Decimal Dalhousie University 18 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Memory Segments Program Contains program instructions 6 0 operation codes OpCodes instruction operands Register associated PC program counter Typical access order Top to bottom Data Holds constants amp variables used by the program Registers associated IX IY index registers Access order dependent on data structures amp program logic Stack Stores temporary variables e g subroutine parameters return addresses Register associated SP stack pointer Typical access order Last In First Out LIFO Dalhousie University 19 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Storage of 2 Byte Data in 1 Byte Memory Locations Example Storage of 16 bit number 2E0A Big Endian Order Motorola HC11 Little Endian Order MSByte Most Signi
4. The operand s absolute address appears explicitly in the 2 bytes following the OpCode any in 0000 FFFF Examples Machine Code Instruction Description B7 CO 20 STAA 020 lt 020 gt lt FO CO 1C SUBB C01C lt ACCB lt C01C gt Dalhousie University 46 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Indexed IND Index registers IX amp IY are used to calculate the effective address EA It can be any in 0000 FFFF EA Base Address Unsigned 8 bit Offset eH IX or IY Examples Machine Code Instruction Description E3 22 ADDD 22 X EA IX 22 ACCD ec ACCD lt EA EA 1 gt 18 AB 0D ADDA 0D Y EA IY 0D lt ACCA EA Dalhousie University 47 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Relative REL lt is used only by the branch instructions EA Next Instructions Address Signed 8 bit Offset OR PCuew EA Daun Offset Offset range 1285 1275 Dalhousie University 48 Jose A Gonzalez Cueto ECED 3204 Microprocessors Relative REL EA PCoLp T Offset M68HC11 Microcontroller Example Fill in the spaces in the machine code below Address Mach Code Label Operation Operand Description 000 20 there BRA C002 22 where C004 24 BCC 006 27 hang 008 25 BLO COOA 8D locc BSR 10 bytes of code subr1 CLRA
5. lt SCSR ZTDRE Is the flag SET SendChar If YES goto send next char Dalhousie University 140 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm RDRF Flag SET the SCI rx unit has a new char ready for the CPU to read CLEAR the RDR is empty no char is available to be read from SCI Example Check whether a new char is ready at the SCI for the CPU to pick up Address Definitions SCSR equ 102E Status register address Constant Definitions RDRF equ 20 Mask for RDRF flag in SCSR Instructions ACCB lt SCSR andb RDRF Is the RDRF flag SET bne ReadChar If YES goto read next char Dalhousie University 141 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm Polling Method Transmission 1 Enable the SCI tx Making TE 1 Example Idaa oraa staa 2 Read SCSR hardware requisite Idab 3 Write data to be tx to the SCDR Example Idaa staa Sending a stream of chars 4 Check SCSR until the TDRE flag is Set 5 When 1 next char is written to SCDR 6 Back to Step 3 cycle repeats until last char is sent to SCI for tx Dalhousie University 142 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm Polling Method Reception 1 Enable the SCI rx Making RE 1 Example daa SCCR2 oraa 04 staa SCCHR2 2 Check SCSR periodically until the RDRF flag is
6. Fetch High half of 16 bit Address Fetch Low half of 16 bit Address transfer High half of 16 bit Operand Data ODLO transfer Low half of 16 bit Operand Data OD transfer 8 bit Operand Data Compute operand Address uses ALU execute do the instruction Dalhousie University 85 Jose A Gonzalez Cueto M68HC11 Microcontroller ECED 3204 Microprocessors Assembly code for Cycle by Cycle Execution example Execution starts at D500 Reset vector is set to D500 Instructions a kkkkkkkkkkkk 3 Code Target Data a KKKK 3 Data List Initialization kkkkkkkkkkkkkk D500 5 TOP List 5 Code Stack Area a kkkkk A Xxx 3 STK_TOP Instruction execution is analyzed for 3 3 THIS THIS THIS and THIS instruction Jose A Gonzalez Cueto 86 Dalhousie University ECED 3204 Microprocessors M68HC11 Microcontroller The 68HC11 Instruction Execution Cycle Perform a sequence of read cycles to fetch instruction opcode byte s and address byte s if required Optionally perform read cycle s required to fetch memory operand s Perform the operation specified by the opcode Optionally write results back to a register or memory location s Example Consider the following 4 instructions Assembly instruction Memory location Machine Code LDAA D000 C000 B6 DO 00 CLRB C003 oF JSR C080 C004 BD CO 80 INC 2 C080 6C 02 Dalhousie University 8
7. Jose A Gonzalez Cueto 153 ty IVersi Dalhousie Un ECED 3204 Microprocessors M68HC11 Timer System Selecting the Free running Counter Frequency for an E clock freq 2 MHz Prescale Counter Counter Factor Updates Every Clock Freq 250 KHz Dalhousie University 154 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Flag Register TFLG1 B B B B B B B Example Clearing OCF OC3F equ 9500100000 equ 1023 Idaa Dalhousie University 155 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Example Updating TOC for a 1 5ms interval Counter clock 2MHz TCNT equ 100E Address of TONT register TOC2 equ 1018 Address of TOC register Increment equ 3000 Increment in decimal idd TCNT Initialization Increment T time std TOC2 Part of ISR Idd TOC2 OF lncrement Successful std Hardware detail SECHS When TOC2 is written compares are suspended for 1 E clock cycle Dalhousie University 156 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Controlling Port A Pin State Timer Control Register 1 TCTL1 B B B B B B 1020 oder low oL RESET 0 0 0 0 0 Example Setting PA to toggle on each None successful compare with TOC3 Disconnected Toggle OC line equ 97500
8. ACCA 2 s complement mul lt ACCB Dalhousie University 73 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Assembly Code for Laboratory 1 Part 5 May 2003 ORG D000 LDD sum Load variable sum into ACCD ABA Add lower byte to higher byte STAA sum Store it back to sum SWI Return control to BUFFALO DW 0804 END Simple Program Example Dalhousie University 74 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Assembly Code for Laboratory 1 Part 5 May 2004 ORG C500 LDD diff Load variable diff into ACCD SBA lt ACCA ACCB STAA diff Store it back to diff NOP Do nothing DB 1E 04 END Simple Program Example Dalhousie University 75 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller M68HC11 Instruction Set Logical Operations Examples andb oraa eora bitb bitb Clears Least Significant Nibble of ACCB 03 Sets Bits 0 amp 1 of ACCA 0 Toggles Bits 2 amp 3 of ACCA 01 Implicit AND ACCB lt C01C gt Flags modified ACCB not altered 319900000011 Is ACCB multiple of 4 as a result of this instruction Z is set Z 1 ACCB is multiple of 4 1004 0 X 55 Sets bits 0 2 4 amp 6 of PORTB 0 X AA Clears bits 1 3 5 7 of PORTB Dalhousie University 76 Jose A Gonzalez Cueto ECED 3204 Microproce
9. Dalhousie University 49 where there locc hang here subr1 branch always branch if higher branch if carry clear branch if Z 1 branch if lower branch to subroutine Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller The 68HC11 Machine Code A 68HC11 instruction consists of 1 to 2 bytes of opcode 0 to 3 bytes of operand information Examples Machine instruction Assembly instruction in hex format always INCB oC LDAA 129 86 1D ADDA 002F 9B 2F assembler encodes using direct addressing mode STAA 01 B7 CO 1E 500 1A 83 00 FF loop BRCLR 0 Y 80 loop 18 1F 00 80 FB Dalhousie University 50 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Decoding machine language instructions Procedure Step1 Compare the first one or two bytes with the opcode table to identify the corresponding assembly mnemonic and addressing mode Step2 Identify the operand bytes after the opcode field Step3 Write down the corresponding assembly instruction Step 4 Repeat step 1 to 3 until the machine code file is exhausted Dalhousie University 51 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Sample lookup table to be used in decoding the program segment of the next example into assembly instructions machine code assembly instruction format 01 86 8B 96 97 9B C3 C6 CB CC D3 D6 D7 DB DC DD
10. C080 first 2 cycles of Instruction 4 INC 2 X Jose A Gonzalez Cueto 124 Dalhousie University 68HC11 M68HC11 Microcontroller 68 11 68 11 AS HC373 output ECED 3204 Microprocessors 68HC11 pete ac Timing Diagram Example last 4 cycles of Instruction 4 INC 2 X from ek x from a pus EPROM from T from EPROM from aen x from Gr Jose A Gonzalez Cueto 125 Dalhousie University ECED 3204 Microprocessors Asynchronous Serial Comm Definitions TxD line Asynchronous Serial Communication duc d Lines O e Asynchronous There is no clock to establish a time reference e Serial Data is carried over the channel one bit at a time not in parallel as over the Data Bus with the CPU Dalhousie University 126 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm UART Transmitter Unit Parallel to Serial Conversion BYTE FROM gt D Dg D Dj Dj D D Dp Data Bus SHIFT TRANSMIT HOLDING ENABLE REGISTER TO CHANNEL PTT TT TTT Le TRANSMIT SHIFT REGISTER SHIFT CLOCK Line Speed e g 9600 baud 9 Also known as the BAUD RATE CLOCK Dalhousie University 127 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm UART Receiver Unit Serial to Parallel Conversion lt BYTE TO CPU gt RECEIVE HOLDING
11. REGISTER FROM CHANNEL RECEIVE SHIFT REGISTER SHIFT CLOCK Line Speed e g 9600 baud 9 Also known as the BAUD RATE CLOCK Dalhousie University 128 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm A data communication system RS 232 RS 232 Comm Link Le Ed oce P hn E e COMPUTER MODEM MODEM COMPUTER or TERMINAL or TERMINAL FSC n Or LOCAL REMOTE RS 232 Standard Establishes Electrical Mechanical Functional and Procedural Specifications for the communication interface between A Computer or DTE and a Modem or DCE 1 Data Terminal Equipment 2 Data Communication Equipment Dalhousie University 129 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm SCI Unit Registers BAUD Sets Line Speed Baud Rate SCCH 1 Control Register 1 SCCR2 Control Register 2 SCSR Status Register SCDR Data Register for both rx amp tx Dalhousie University 130 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm part Register B B B ses SLT ELIT Hate Select Bits Prescaler Select Bits T Used only in test mode For an E clock frequency 2MHz 2MH 2MH 125 000 Baud st 250Baud i i s Lan omg Dalhousie University 131 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm B
12. s19 ASCII files portable edited on any PC e Readable Hex machine code Memory addresses where code will be loaded Dalhousie University 27 Jose A Gonzalez Cueto ECED 3204 Microprocessors S Record Format M68HC11 Microcontroller S lt Type gt lt Length gt lt Address gt lt Code Data gt lt Checksum gt MEN ONE TWO 2 byte address FOUR printable chars printable printable char 0 9 chars Specify the record length in bytes counting address code data checksum fields Dalhousie University 28 TWO printable chars Executable code and or data Up to 64 bytes Least significant byte of the 1 s complement of the sum of the values in the record length address code data fields Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller S Record Example S0 OE 0000 53 52 45 43 4F 52 44 2E 42 41 4B E3 Starting Record Address Instruction Data 1 04 C000 FE 3D C000 LDX CO008 1 05 C001 CO 08 71 ph S1 04 C003 BD 7B C003 JSR C00B S1 05 C004 C0 0B 6B s 51 09 006 20 00 0A05FF04 006 BRA FE Ly v eee keier Address Checksum 8 000 UN Length Code Data CO00A 05 51 05 00 CO OF 5F COOB STX COOF 51 04 COOE 39 F4 COOE HIS S1 04 C010 00 2B CO10 00 Data 59 03 0000 FC lt Termination Record Dalhousie University 29 Jose A Gonzalez Cueto ECED 3204 Microprocessors M6
13. DO RAM chip internals ECED 3204 Microprocessors Jose A Gonzalez Cueto 118 Dalhousie University EPROM Read Cycle Address Phase Data Phase 68 11 M68HC11 Microcontroller ECED 3204 Microprocessors Ajs Ag 9 drivers off 68HC11 68HC11 22 373 delay lt HC373 output 68HCll The 68HC11 issues the address e g E034 High address byte GEO in lines A Ag and low address byte 34 in lines AD AD The low address byte is latched by the 74HC373 with the falling edge of AS before E goes high starting the data phase A A is now supplied by the 74HC373 Y7 Y7 is asserted by the decoder the 74HC138 selecting the EPROM module EPROM outputs are also enabled G goes low as well and EPROM drivers turn on Valid data B6 is driven by the EPROM into the AD AD bus serving as data bus in this second half 6 The data bus value e g B6 is latched by the CPU into one its registers with the falling edge of the E clock Jose A Gonzalez Cueto 119 ty IVersi Dalhousie Un M68HC11 Microcontroller ECED 3204 Microprocessors RAMI Read Cycle Address Phase Data Phase 68HC11 NU RAN drivers off 2 SS 68HC11 68HC11 i 98973 outil HC373 output 68HC11 D 0 The 68HC11 issues the address e g C034 High address byte 0 in lines A c and low address byte 34 in lines AD 6 The low
14. Dalhousie University NOP LDAA ADDA LDAA STAA ADDA ADDD LDAB ADDB LDD ADDD LDAB STAB ADDB LDD STD IMM IMM DIR DIR DIR IMM IMM IMM IMM DIR DIR DIR DIR DIR DIR 52 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Example Disassemble the following machine code to its corresponding assembly instructions 96 30 8B 17 97 30 CC 02 F0 Solution The disassembly process starts from the leftmost byte We next look up the machine code table to see which instruction it corresponds to Instruction 1 Step 1 The first byte 96 corresponds to the instruction LDAA DIR Step 2 The second byte 30 is the direct address Step 3 Therefore the first instruction is LDAA 30 Instruction 2 Step 1 The third byte 8B corresponds to the instruction ADDA IMM Step 2 The immediate value is 17 Step 3 Therefore the second instruction is ADDA 17 Dalhousie University 53 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Instruction 3 Step 1 The fifth byte 97 corresponds to the instruction STAA DIR Step 2 The DIR address is the next byte 30 Step 3 Therefore the third instruction is STAA 30 Instruction 4 Step 1 The seventh byte CC corresponds to the instruction LDD IMM Step 2 The IMM 16 bit value is given by the next 2 bytes 02 F0 Step 3 Therefore the fourth instruction is LDD 02F0 Dalhousie University 54 Jose A Gonzale
15. IX pointer inx Update Buffer pointer cpx END Check if Buffer end has been reached bls POLL If NOT go back wait for new data from port SWi IF YES exit to BUFFALO end Dalhousie University 188 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Alternative to define Buffer space org 0000 Start of Buffer BUF START ds 1255 One element less than total space BUF END ds 1 Last element to allow labeling it Alternative check for program end staa 0 Store it in Buffer using IX pointer END Check if last element written beq DONE If YES finish program inx If NOT update Buffer pointer amp bra POLL Go back wait for new data from port swi Exit to BUFFALO Dalhousie University 189 Jose A Gonzalez Cueto
16. TOC2 interrupt vector e g EVB jump table 4 Clear OC2F 5 Enable TOC2 interrupts i e OC2l lt 1 Dalhousie University 166 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Measuring Long Periods TIC isr Detecting amp Solving a Missed Overflow Find amp Save TIC TIC If TIC lt 0 Counter lt Counter 1 gt lt If TIC lt 5000 lt Assuming 5000 E clk cycles new read TOF gt PR PR 0 are sufficient lt If TOF is SET to have OF serviced before IC inc Counter re IncFlag 0 gt gt new lt Save Counter gt Preparing for measuring clr Counter next period clear IC F flag Acknowledge interrupt service rti If IncFlag is SET inc Counter IncFlag lt 1 gt clear TOF flag Acknowledge interrupt service rti Dalhousie University 167 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Solving a Missed Overflow Alternative No IncFlag TIC isr Find amp Save TIC If TIC lt 0 Counter Counter 1 gt If TI e lt 5000 read TOF Detecting amp Solving If TOF is SET a Missed Overflow inc Counter Save Counter Preparing for measuring Counter lt FF next period if OF missed else Save Counter Preparing for measuring Counter 00 next period if OF serviced else Save Counter Counter lt 00 gt
17. UpdatePeriod Periodhex Load IX with address of hex period HtoD Subroutine call DBUFR Reading subroutine output End of subroutine UpdatePeriod NewLineString LF CR NUL DBUFR ds 5 Variables Part of them Periodhexdw 0 end End of Program Code Main Program Example Part 2 Dalhousie University 70 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller M68HC11 Instruction Set amp Assembly Programming Bibliography 68HC11 Reference Manual Section 6 5 and Appendix A 68HC11 Programming Reference Guide Section 3 Textbook Chapter 3 e Huang 5 book Chapter 2 Dalhousie University 71 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller M68HC11 Instruction Set Load amp Store Instructions Examples 2 ACCA lt 2C C007 ACCB lt lt 007 gt staa lt 00 gt lt Register Transfer amp Exchange Instructions tab ACCB lt ACCA lt ACCB xgdx ACCD lt gt IX xgdy ACCD lt gt IY Dalhousie University 72 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller M68HC11 Instruction Set Arithmetic Instructions Examples inc Counter Counter Counter 1 deca lt ACCA 1 adda alpha ACCA lt alpha suba beta lt beta lt lt
18. address byte is latched by the 74HC373 with the falling edge of AS before E goes high starting the data phase ve Y6 is asserted by the decoder the 138 selecting the RAM module RAM outputs are also enabled G goes low and W remains high since the 68HC11 R is high Valid data B6 is driven by the RAM into the AD AD bus 6 The data bus value e g B6 is latched by the CPU into one its registers with the falling edge of the E clock Jose A Gonzalez Cueto 120 ty IVersi Dalhousie Un M68HC11 Microcontroller ECED 3204 Microprocessors RAM Write Cycle Address Phase Data Phase 68HC11 68 11 AD ADg 68 11 SS 373 sui delay lt HC373 output 68HCll i 1 i i T 1 i i i I 1 i I 1 1 1 i 1 i 1 1 t i 1 H 1 1 i H 1 H H H 1 H 1 i A 4 6 The 68HC11 issues the address e g C034 High address byte 0 in lines Ag and low address byte 34 in lines AD At the same time the 68HC11 RAW signal goes low indicating this is a write cycle since write W is active low The low address byte is latched by the 74HC373 with the falling edge of AS before E goes high starting the data phase ve Y6 is asserted by the decoder the 74HC138 selecti
19. an interface unit 1 Synchronizing data transfer between CPU and interface unit 2 Synchronizing data transfer between I O interface and I O device Control signals Interface or Strobe Signals Microprocessor CPU RAW or interrupt I O device Data Bus Data Bus Dalhousie University 172 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Synchronizing the Microprocessor CPU and the I O Interface Unit The polling method 1 for input the CPU checks a status bit of the interface unit to find out if the interface unit has received new data from the input device 2 for output the CPU checks a status bit of the interface unit to find out if it can send new data to the interface unit The interrupt driven method 1 for input the interface unit interrupts the CPU whenever it has received new data from the input device 2 for output the interface unit interrupts the CPU whenever it can accept new data from the CPU Dalhousie University 173 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Synchronizing the I O Interface Unit and Devices Brute force method useful when the data timing is unimportant 1 for input nothing special is done The CPU reads the interface unit and the interface unit returns the voltage levels on the input port pins to the CPU 2 for output nothing special is done The interface unit places
20. clear IC F flag Acknowledge interrupt service rti inc Counter clear TOF flag Acknowledge interrupt service rti Dalhousie University 168 Jose A Gonzalez Cueto M68HC11 Timer System ECED 3204 Microprocessors Hex to ACD ASCII coded decimal HtoD Subroutine Example 19 0088 digi FE o 9 A sid oam BE x E 30 0 500 eee Less sok 2 2 9 2 gene 62 4 S Oo 32 2 S jec amp z Css SCH ae 35 Aserr Jose Gonzalez Cueto 169 Dalhousie University ECED 3204 Microprocessors Parallel UO Comm Parallel PORTB Control of a Two Digit Common Anode 7 Segment LED Display 5 d Soure ya bo Re i uu dc D pe b b Ra PBo po Ra Dalhousie University 170 Jose A Gonzalez Cueto Parallel UO Comm ECED 3204 Microprocessors 88 S pot 828 PULSE ACCUMULATOR ROM 8K BYTES PERIODIC INTERRUPT RAM 256 BYTES COP WATCHDOG EEPROM 512 BYTES 8889 M68HC11 CPU INTERRUPTS OSCILLATOR POWE MODA LIR MODE SELECT MODB R 3 EXPANDED gt MC68HC11 Block Diagram Jose A Gonzalez Cueto 171 ty IVersi Dalhousie Un ECED 3204 Microprocessors Parallel UO Comm UO Transfer Synchronization The role of
21. or address Jump always to a label address in the 64KB address space bra label Branch always to an address in the range 128 4 PC 127 3 Subroutine calls jer lt label or address Jump to a subroutine starting with a label address anywhere in the 64KB address space bsr label Branch to a subroutine starting with a label associated with an address in the range 128 PC 127 PC is the address of the instruction following bsr Return from subroutine Dalhousie University 82 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller M68HC11 Instruction Set Stack Instructions 1 Saving contents of CPU registers psha pshb otoring register values to stack pshx pshy Retrieving contents of CPU registers puly pulx Restoring register values from stack pulb pula Dalhousie University 83 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Internal Description CPU Registers Bus Address Register 16 bits Address Bus Address Register 16 bits 16 bits mm Bus Data Register 8 bits Instruction Register 8 bits ATMP Temporal Address Register 16 bits DTMP Temporal Data Register 16 bits Dalhousie University 84 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Cycle Code Description Fetch instruction Opcode Fetch 8 bit address Offset
22. that stores string ABC Z to variable alphabet H Constants 00000041 CAP A equ 0000005A CAP Z equ Z Instructions 0000C000 org 000 C000 CE Idx alphabet C003 86 41 daa A C005 7 00AlphaLoop staa 0 C007 08 inx C008 4C inca C009 81 5A Z COOB 23 F8 bs AlphaLoop Variables COOD 001A alphabet ds 126 Dalhousie University 66 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller H HtoD Subroutine to convert a 16 bit hex number to a 5 digit decimal number Decimal ASCII result is stored in external 5 byte variable DBUFR On entry points to hex value to be converted All registers are unchanged upon return H public HtoD Subroutine label other module s can have access to extern DBUFR Variable label defined in other module pshy pshx Save registers pshb psha Idy DBUFR lY points to DBUFR variable Idd 0 X ACCD hex value to be converted Idx 10000 idiv IX hex 10 000 ACCD remainder r Subroutine Example Part 1 Dalhousie University 67 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Idx 100 idiv IX 11 100 new r2 xgdx IX r2 ACCA ACCB 100s digit 30 Convert to ASCII stab 2 Y Store to 100s digit in decimal buffer xgdx ACCD r2 Idx 110 idiv IX r2 10 ACCD new r ACCB 1s d
23. the data that it received from the CPU directly on the output port pins The strobe method a strobe signal is used to indicate that data are stable on I O port pins 1 for input the interface unit latches the data into its data register using the strobe signal 2 for output a the interface unit places the data received from the CPU on the output port pins and asserts the strobe signal b the output device latches the data using this strobe signal Dalhousie University 174 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Synchronizing the Interface Unit and I O Devices cont d The handshake method used when timing is crucial For input and output Two handshake signals are used to synchronize the data transfer 1 One signal call it H1 is asserted by the interface unit 2 The other signal call it H2 is asserted by the I O device Two handshake modes are available pulse mode and interlocked mode Dalhousie University 175 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Input Handshake Protocol Step 1 The interface unit asserts or pulses H1 to indicate its intention to input data Step 2 The input device puts data on the data port pins and also asserts or pulses the handshake signal H2 Step 3 The interface unit latches the data and de asserts H1 After some delay the input device also de asserts H2 s AA N N Kee a Interlocked H1
24. 010000 TCTL1 equ 1020 Clear OC line logic 07 daa CTLBYTE Set OC line logic 1 staa TCTL1 Dalhousie University 157 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Local IC OC Timer Interrupt Masks Interrupt Enable Register 1 TMSK1 B B B B B 0 0 When 0 Interrupt Inhibited Example Interrupt Enabled Enabling Interrupts from TOC4 OCAI equ 92600010000 TMSK1 equ 1022 Idaa TMSK1 oraa 4OCAI staa TMSK1 Dalhousie University 158 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Selecting Port A Triggering Event Timer Control Register 2 TCTL2 B B B B B B sel o o EDG B EDG A Configuration Capture Disabled Capture on Rising Edges Only Capture on Any Edge Rising or Falling ENEN 1 Capture on Falling Edges Only Dalhousie University 159 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Example Period Measurement using TIC3 PA TIC3 equ TCTL2 equ CTLBYTE Idaa staa Initialization idd subd Part of ISR std or Successful Idd Polling std 1014 1021 2600000001 CTLBYTE TCTL2 TIC3 PreviousReading Period TIC3 PreviousReading clear IC3F PreviousReading Period Dalhousie University ds 2 ds 2 160 Rising edge Period TIC Update TIC a Current period J
25. 04 Microprocessors JSR C080 SP cycle first half BAR lt lt PC gt C004 Cycle by cycle Execution Register Transfer Notation cycle second half PC PC 1 C005 IR BDR BD cycle first half BAR PC C005 cycle second half PC PC 1 C006 lt BDR gt SCH cycle first half BAR PC C006 cycle first half BAR lt gt C080 Note This cycle is implemented for consistency with the EXTended addressing mode likely cycle second half lt PC 1 C007 cycle second half DTMPio BDR 6C to make control logic simpler contents of C080 NOT USED by this Instruction cycle first half BAR SP DFFF SP SP 1 DFFE cycle second half BDR Hues 07 cycle first half BAR lt lt SP gt DFFE SP lt lt SP gt 1 DFFD EE cycle second half PC CO lt gt C080 Jose A Gonzalez Cueto 101 ty IVersi Dalhousie Un ECED 3204 Microprocessors M68HC11 Microcontroller Instruction INC 2 X Step 1 CPU fetches OpCode byte Step 2 CPU fetches offset byte Memory contents Address bus Memory contents Address bus Address 080 070 CO7E 2 07 6080 6081 C082 C083 Data bus Data bus C085 Before Af
26. 1 Microcontroller HC11 CPU Addressing Modes Describe the primary operand involved in an instruction Operands can be CPU registers and or Bytes from memory 1 Inherent INH 2 Immediate IMM 3 Direct DIR 4 Extended EXT 5 Indexed IND 6 Relative REL Dalhousie University 42 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Inherent INH Only CPU registers are involved in the instruction Examples Machine Code Instruction Description 1B ABA lt ACCB 5C INCB ACCB lt ACCB 1 08 INX IX lt IX 1 16 TAB ACCB ACCA Dalhousie University 43 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Immediate IMM The operand value is part of the instruction It follows the OpCode Examples Machine Code Instruction Description 86 25 LDAA 25 ACCA 25 81 24 CMPA 100100 9600100100 CC 07 D2 LDD 12002 lt 0702 Same as ACCD lt 0702 Dalhousie University 44 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Direct DIR The operand is stored in initial 256 bytes 0000 00FF Examples Machine Code Instruction Description 90 1F SUBA 1 lt ACCA lt 001F gt 96 A8 LDAA A8 ACCA lt 00A8 gt Dalhousie University 45 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Extended EXT
27. 2 Read PORTCL register Dalhousie University 183 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Port C Interlocked Output Handshake Protocol lt WRITE PORTCL PORT previous data inew port data VALID DATA Active High DATA READY plane ACK Active High from Device to HC11 Port tpwo Peripheral data write delay time 150 ns max at 2 MHz E fall to STRB delay 225 ns at 2 MHz taes STRA asserted to E fall setup time 0 ns at 2 MHz Dalhousie University 184 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Port C Output Handshake Protocol STRA is an acknowledge input driven by the external device STRB is a valid data or data ready output driven by the 68HC11 n the figure STRA activates with rising edge and STRB is active high Protocol sequence a The 68HC11 writes data into PORTCL and then asserts STRB to indicate that there are valid data on port C pins b The external device then asserts STRA to acknowledge the receipt of data which will then cause STRB to be de asserted and the STAF flag to be set c After the de assertion of STRB STRA is also de asserted STAF clearing sequence 1 Read PIOC register 2 Write PORTCL register Dalhousie University 185 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Code Example using Simple Strobe UO Addresses PIOC equ 1002 Address for the Par
28. 3204 Microprocessors Asynchronous Serial Comm MC6850 ACIA Register Selection Register Select R W Register Input RS Selected 1 Tx Data Register TDR Rx Data Register RDR Control Register CR SR Dalhousie University 146 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm Bibliography for Interrupts amp the SCI unit Textbook Section 2 1 3 Section 2 2 2 Section 2 3 1 Section 3 9 Sections 4 2 2 4 2 3 amp 4 3 HC11 Reference Manual Pink Book Section 5 5 Interrupt Process Section 9 5 2 Interrupts amp Status Flags SCI tx Section 9 6 4 Receive Status Flags amp Interrupts Dalhousie University 147 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm Interrupt Acknowledgement Procedure 1 Main program execution is suspended 2 Program state is saved to the stack 3 PC Interrupt Vector of highest priority interrupt pending Execution continues at this address 4 ISR is concluded with an RTI instruction Program state ie all CPU registers are restored PC Return Address where execution of main program resumes Dalhousie University 148 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm Example of SCI Interrupt Service Routine ISR Address Definitions SCSR equ 102E Status register address SCDR equ 102F Data register address Constant Definitions RDRF e
29. 4 Microprocessors M68HC11 Microcontroller Cycle by Cycle Execution LDAA EXT Add Data RW OP B6 1 hh 2 ll ll Dalhousie University 91 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Cycle by cycle Execution Register Transfer Notation LDAA D000 cycle first half cycle second half BAR PC C000 PC 1 C001 IR lt BDR gt B6 cycle first half cycle second half BAR lt lt PC gt C001 PC PC 1 C002 ATMP lt gt 00 E cycle first half cycle second half BAR lt lt PC gt C002 PC 1 C003 ATMP o lt BDR gt 00 cycle first half cycle second half BAR lt gt 50000 lt lt BDR gt 19 lt reg gt stands for the contents of register reg Dalhousie University 92 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Instruction CLRB Step 1 Place the value in PC on the address bus with a request to read the contents of that location Step 2 The opcode byte 5F at C003 is returned to the CPU and PC is incremented by 1 Memory contents Address bus Address C000 C001 C002 C003 004 C005 C006 C007 Data bus C008 Before After PC PC Instruction 2 Opcode read cycle Dalhousie University 93 Jose A Gonz
30. 7 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Instruction LDAA D000 Step 1 Place the value in PC on the address bus with a request to read the contents of that location Step 2 The opcode byte B6 at C000 is returned to the CPU and PC is incremented by 1 Memory contents Address bus Address C000 C001 C002 C003 004 C005 C006 C007 Data bus C008 Before After PC PC Instruction 1 Opcode read cycle Dalhousie University 88 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Step 3 CPU performs two read cycles to obtain the extended address 0000 from locations C001 and C002 At the end the value of PC is incremented to 003 Memory contents Memory contents Address bus Address Address bus Address C000 C000 C001 C001 C002 C002 C003 C003 004 C004 C005 C005 C006 C006 C007 Bala DUE C007 C008 C008 Before After first read After second read PC PC PC Instruction 1 Read cycles for address bytes Dalhousie University 89 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Step 4 The CPU performs another read to get the contents of the memory location at D000 which is 19 The value 19 will be loaded into ACCA i e 19 Memory contents Address Address bus Data bus Instruction 1 Operand read cycle Dalhousie University 90 Jose A Gonzalez Cueto ECED 320
31. 8HC11 Microcontroller Loading Executable S Records s19 into the EVB 1st Establish communication with the EVB from the PC Establish the serial connection between the COM1 Port on the PC side and the Terminal I O Port on the EVB e2nd On the BUFFALO window in MinilDE type the command gt load t hit Enter EVB ready for S record stream through t erminal port e 3rd Open a 2nd MinilDE window and connect it as a Terminal window Go to Menu Terminal gt Download File gt Browse for the S19 file to download to the EVB board Dalhousie University 30 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Loading Executable S Records into the QEVB11 Simulator a Use the Load command from the File pull down menu OR b Click on the button with the blue arrow on top of a stack of papers Locate the s19 s Record in the PC e Machine code will be loaded into RAM memory of EVB model Dalhousie University 31 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller TxD L 0 0 En CONTROL 00 05 00 A0 D7 A7 z PT LATCH 4 PE0 PE7 E T 85 2326 DRIVERS TARGET lt lt AND SYSTEM RECEIVERS TERMINAL CONTROL Figure 1 2 EVB Block Diagram Dalhousie University 32 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller A RESET SELECT P2 J2 TERMINAL CL
32. AUD Register Continued For a Highest Baud Rate of 9 600 Baud SCP SCP 1 9 600 Baud 4 800 Baud 2 400 Baud 1 200 Baud 600 Baud 300 Baud 150 Baud 75 Baud Dalhousie University 132 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm BAUD Register Continued Example Write a program segment in assembler to set the SCI unit baud rate equal to 2400 baud From previous tables we need B 1 1 and 2010 BAUD 102B Register address BAUD2400 9000110010 Control byte BAUD2400 BAUD Setting line speed to 2400 baud Dalhousie University 133 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm SCCR1 Register B Bg B 1026 WO 0 0 x L 1 Mode Selects char format Transmit Data Bit 8 Heceive Data Bit 8 e M 0 SCI rx amp tx 8 bit data frames Only SCDR is needed e M 1 SCI rx amp tx 9 bit data frames this case data bit B is transferred through Tg during tx and Rg during rx Frame Length The SCI unit always uses 1 Start Bit 8 or 9 Data Bits and 1 Stop Bit 10 or 11 bits frame total Dalhousie University 134 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm SCDR Register Receive and transmit double buffered Examples A When the unit has received new data and it is available for the CPU to read it i e RDRF condition 102F Brin
33. B For instance if the offset was 20 ie EC the high byte to be added would be FF FF instead of 00 204 ie 14 ATMPu 00 is still used IVersi Dalhousie Un ECED 3204 Microprocessors M68HC11 Microcontroller Philips Semiconductors Product specification 3 to 8 line decoder demultiplexer inverting 74HC HCT138 FUNCTION TABLE INPUTS OUTPUTS E E A Ys Ys P Ys Ys X H H H H H H TE TE H X X X X H X X X X H X X L X X X H L L H L L L L H H L L L H L H L L H H H L L H L L L L H H L L L H L H L L H H H Notes 1 H HIGH voltage level L LOW voltage level X don t care Dalhousie University 107 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller The 74HC138 Decoder When the chip is enabled i e 1 E and E f A Ag Activates Output 0 0 0 1 Input Enable Output lt l lt N Select Address Pins Input Pins Dalhousie University 108 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Address Decoding Example EVB case To Another SS Memory Module Address Bus A0 A12 Dalhousie University 109 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Memory Module Allocation using the Decoder e Lines Ay are used to address the 8K 213 locations in the module e Lines specif
34. B 0 falling edge 0 STRB active low 1 rising edge 1 STRB active high Dalhousie University 178 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Simple Strobe Mode Selected when HNDS 0 default upon RESET Port C becomes the strobe input port STRA active edge latches the values of port C pins into PORTCL reg VALID DATA Rising Edge from Device tig input setup time 60 ns at 2 MHz input hold time 100 ns at 2 MHz Port C strobed input timing Dalhousie University 179 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Simple Strobe Mode Input Port C Bit 1 of the PIOC register EGA selects the active edge of the STRA pin Reading PORTC register returns the current values on Port C pins Reading PORTCL register returns Port C values latched with last STRA active edge When enabled STAI 1 the active edge of the STRA signal will request an interrupt to the CPU The STRA interrupt vector is at F FF2 FFF3 same as for IRQ STAF clearing sequence 1 Read PIOC register 2 Read PORTCL register Dalhousie University 180 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Simple Strobe Mode Output Port B The strobe signal STRB is pulsed for two E clock cycles each time there is a write to port B CPU write 7 2 gt t Port previous port data X X X X new po
35. C400 IX SCI ISR address stx JMPTBL2 Storing Jump Address to table l Other initialization instructions aorg C400 Code to follow loaded at C400 Ier 15st Instruction of SCI ISR gt Dalhousie University 151 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Timer System Functions amp Port A Pins Dalhousie University 152 Jose A Gonzalez Cueto MCU PRESCALER E CLOCK DIVIDE BY TCNT H TCNT LO 1 4 8 OR 16 16 BIT FREE RUNNING PRI PRO COUNTER E TAPS FOR RTI INTERRUPT REQUESTS COP WATCHDOG AND FURTHER QUALIFIED 16 BIT TIMER BUS PULSE ACCUMULATOR BY I BIT IN CCR TO PULSE ACCUMULATOR OUTPUT PORTA 1 COMPARES PINS 16 BIT COMPARATOR r PATI FORCE ndi DC M68HC11 Timer System 16 BIT COMPARATOR PAG TOC2 LO NE A OC2 j OC1 16 BIT COMPARATOR t TOC3 TOC3 LO NE c 1 mtb 16 BIT COMPARATOR 7 PA4 TOC4 LO A 004 x x 16 BIT OCH OC1 E 16 BIT TIMER BUS 16 BIT LATCH lt mcr morto 16 BIT LATCH lt e IC2F mem moto icai 07 16 BIT LATCH lt BITO 2 HI 2 LO TFLG1 TMSK1 PORT A INTERRUPT NTERRUPT PIN i FLAGS ENABLES CONTROL E Main Timer System Block Diagram ECED 3204 Microprocessors
36. CAP A Checking contents of ACCB w r t A staa PORTB Writing contents of ACCA to PORTB Program Instructions Dalhousie University 61 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Advantages of Named Constants 1 Their value only needs to be changed once in the Definition Part 2 Improves readability of Assembly Code Other Examples Constants DELAY equ 2000 Delay value to initialize counter with BITMASK1 equ 9600000001 Mask used for parity bit O Bo BITMASK2 equ 9600110000 Mask used to toggle bits 4 amp 5 B amp Instructions These are just isolated examples NOT part of a program Idx DELAY Initializing delay counter IX bita BITMASK1 Checking if B is 0 or 1 lt gt even or odd anda ZBITMASK1 Does the same as bita but also modify ACCA In this case B B are cleared BITMASK2 Toggles ACCA bits 4 amp 5 B amp B5 Dalhousie University 62 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Using Variables in Assembly Programming Example Instructions These are just isolated examples NOT part of a program Counter ACCA Counter inca lt 1 staa Counter Counter ACCA updating Counter Counter Counter lt Counter 1 Equivalent to above adda Counter ACCA ACCA Counter Counter db Dalhousie University 63 Jose A Gonzalez Cueto EC
37. D 004B 00C3 MONITOR VARIABLES 00C4 00FF VECTOR JUMP TABLE WOIWI I IIIIKI NOT USED M68HC11 Microcontroller Figure 5 2 EVB Memory Map Diagram ECED 3204 Microprocessors 39 Jose A Gonzalez Cueto Dalhousie University ECED 3204 Microprocessors M68HC11 Microcontroller 8 BIT ACCUMULATORS A amp B OR 16 BIT DOUBLE ACCUMULATOR D INDEX REGISTER X INDEX REGISTER Y STACK POINTER PROGRAM COUNTER 7 0 S X H N Z vc CONDITION CODES u CARRY BORROW FROM MSB OVERFLOW ZERO NEGATIVE INTERRUPT MASK HALF CARRY FROM BIT 3 X INTERRUPT MASK STOP DISABLE M68HC11 Programmer s Model Dalhousie University 40 Jose A Gonzalez Cueto Branch Instructions M68HC11 Microcontroller Branch if Greater Than or Equal Branch if Greater Than BT x Sei Branch if Higher or Same Branch if Less Than Equal BE goes Branch if Lower same as BCS BO x Unsigned lt Branch if Lower or Same BS X Unsigned lt Branch if Less Than BT X Signed lt xp pe sms _ Branch if Bit s Clear Branch Never BRN x Branch if Bit s Set Branch if Overflow Clear EL S BES ME ECED 3204 Microprocessors Branch if Overflow Set Bit Manipulation 3 cycle NOP Bit Manipulation Jose A Gonzalez Cueto 41 ty IVersi Dalhousie Un ECED 3204 Microprocessors M68HC1
38. ECED 3204 Microprocessors Transparencies ECED 3204 Microprocessors TRANSPARENCIES Instructor Jose Gonzalez Cueto Department of Electrical amp Computer Engineering Dalhousie University Halifax Fall 2013 Dalhousie University 1 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introduction to the Course Course website http myweb dal ca gonzalej Teaching Eced3204 ECED3204 html or Dept webpage Faculty Jose Teaching Microprocessors Hardware 1 Motorola M68HC11EVB board The evaluation board or EVB Based on the M68HC11 MCU MicroController Unit Software 1 Mini IDE Integrated Development Environment Runs on PC M68HC11 Cross Assembler Building executable files Downloading of 6811 executables to the EVB PC lt gt EVB serial communication Dalhousie University 2 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introduction to the Course Software Cont d 2 Stan Simmons QEVB11 Simulator Runs on PC Simulates the EVB board in detail CPU operation bus timing serial communication and more Downloadable through link in course website Comes with tutorials Do tutorials 1 3 over weeks 1 4 Helpful for the Labs program debugging and testing Dalhousie University 3 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introduction to the Course Bibliography 1 Hughes L Hardware and Software Design for the MC68HC11 5th edit
39. ED 3204 Microprocessors M68HC11 Microcontroller Defining a Known String Example Constants CR 0D LF 0A NUL 00 Variables str1 This is string 1 str3 ABCDEFG NameStr JOSE CR LF NUL null terminated string including the format control characters Carriage Return amp Line Feed Dalhousie University 64 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Reserving arbitrary amounts of storage Example Program segment that stores string ABC Z to variable alphabet Constants CAP A equ First letter has the lowest ASCII value in the set CAP Z equ 2 Last letter Z has the highest ASCII value in the set Instructions org COOO Code below to be loaded starting at C000 Idx stalphabet pointing to alphabet loaded with its address daa CAP AlphaLoop staa 0 Store value in to address held IX inx Increment IX IX points to next byte in alphabet inca ACCA holds ASCII value for next character Z Is next char lower or same as 27 AlphaLoop If YES go back to store it and repeat cycle Variables alphabet 26 Allocates 26 bytes of memory for variable alphabet Its values are undefined initially Dalhousie University 65 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Reserving arbitrary storage List File Example Program segment
40. ER MC6885S0P ACIA MC68HC11A1 MCT4HC74 MCU FLIP FLOP MC 4HC14 INVERTER MC74HC4040 RIPPLE COUNTER R 232C RECEIVER Dalhousie University 115 PIN NOT USED DEVICE Jose A Gonzalez Cueto M68HC11 Microcontroller ECED 3204 Microprocessors lt o E a gt O D a pr G Q o e gt LLI 010 SV MC68HC1T1A1 MCU 4 osas PA US 066 PAL 6 DI 1 PA2 PA3 PA4 PA5 PE0 PE1 PE2 PE3 PET 5 PD4 PART OF MCU 1 0 PORT Pot CONNECTOR Moos EXTAL XTAL u4 RAWEPROM SOCKET 6000 gt 5 5 POWER 04 1 EN Aet qr 412 CONNECTOR 12V 12V cig 91 wei sei I 5 Jose Gonzalez Cueto 116 ty IVersi Dalhousie Un ECED 3204 Microprocessors M68HC11 Microcontroller EVB Schematic Diagram Sheet 2 Part 2 nua in A 440d 0 1 BANNOD 1SOH 1804 DI DON 30 1uNd 30123NNOO 30123NNO5 180d NEE OL03NNOO Dalhousie University 117 Jose A Gonzalez Cueto EPROM memory cell row decoder a column decoders and multiplexers M68HC11 Microcontroller D7 D6 DS D4 D3 D2 DI DO EPROM chip internals RAM memory cell D7 06 D5 D4 D3 D2 DI
41. OCK PORT SELECT CONNECTOR J4 PROGRAM EXECUTION SELECT co P gt cu RESET CONNECTOR ewiTCH 45 TERMINAL Ae BAUD RATE HOST PORT SELECT z RX SIGNAL k POWER DISABLE CONNECTOR HOST PORT CONNECTOR Figure 2 1 Connector Switch and Jumper Header Location Diagram Dalhousie University 33 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller CF 36 40 ZZ S 07 DIGITAL C10 C11 C9 ut us ss CJ M Figure 6 1 Parts Location Diagram Dalhousie University 34 Jose A Gonzalez Cueto M68HC11 Microcontroller ECED 3204 Microprocessors REFERENCE DESIGNATION C1 C5 C8 C11 C13 C14 C17 C18 C6 C7 C16 C12 C15 J1 J3 J6 J2 J4 45 R1 R3 R5 R10 R4 R11 R13 R15 R12 R16 R17 R18 XU1 XU3 XU5 XU9 XU10 NOTES Table 6 5 EVB Parts List DESCRIPTION Capacitor 0 1 uF 50 20 Capacitor 24 pF 50 Vdc 20 Capacitor 1 0 pF 50 20 Capacitor electrolytic 100 uF 50 20 Header jumper single row post 2 pin Aptronics 929705 01 02 Header jumper single row post 3 pin Aptronics 929705 01 03 Header jumper double row post 12 pin Aptronics 929715 01 06 Header double row post 60 pin Aptronics 929715 01 30 MCU port connector Connector cable 25 pin ITT DBP 25SAA terminal host UO port connector
42. Set 3 When RDRF 1 next char is read SCDR e g Idaa SCDR 4 Some processing is done if required 5 Back to Step 2 cycle repeats forever or until reception is finished Dalhousie University 143 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm Philips Semiconductors Product specification Dual D type flip flop with set and reset 7AHC HCT7A positive edge trigger FUNCTION TABLE INPUTS OUTPUTS H HIGH voltage level L LOW voltage level X 7 don t care T LOW to HIGH CP transition state after the next LOW to HIGH CP transition Fig 4 Functional diagram Dalhousie University 144 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm Directing SCI RxD pin PD to the MCUIO port connector Address Definitions FFLOP equ 5000 A decode address for the FlipFlop Constant Definitions Byte2Write equ 00 Bit 0 must be clear B 0 Instructions Byte2Write lt 0 is an alternative staa Switches PD to Target System Directing SCI RxD pin PD to the RS 232 compatible Host Computer UO port Constant Definitions Byte2Write equ Bit 0 must be set B 1 Instructions Byte2Write lt 0F staa FFLOP Switches PD to Host Comp port to communicate over an RS 232 protocol with the PC in our case Dalhousie University 145 Jose A Gonzalez Cueto ECED
43. Terminal block 4 position Electrovert 25 112 0453 power supply connector Resistor 10k ohm 596 1 4W Resistor 10M ohm 596 1 4W Resistor 27k ohm 5 1 4W Resistor 620 ohm 596 1 4W Resistor 100k ohm 5 1 4W Resistor 2 2k ohm 596 1 4W Switch pushbutton SPDT C amp K 8125 R2 7527 1 MC68HC24FN PRU L C MC74HC373N transparent latch LC 2764 8k EPROM 250 ns LC MCM6164 8k RAM user supplied L C MCM6164 8k RAM 250 ns LC MC74HC138 decoder demultiplexer LC MC74HC4066 MC14066B digital switch 1 MC1488P RS 232C driver LC MC68B50P ACIA LC MC68HC11A1FN MCU Note 1 1 C MC74HC74 D type flip flop LC MC74HC14 inverter LC MC74HC4040 binary ripple counter LC MC1489P RS 232C receiver Socket PC mount 44 pin PLCC AMP 821 551 1 use with U1 Socket 28 pin DIP Robinson Nugent ICL 286 S7 TG use with U3 U5 Socket 24 DIP Robinson Nugent ICL 246 S7 TG use with U9 Socket PC mount 52 pin PLCC AMP 821 575 1 use with U10 Crystal MCU 8 0 MHz Notes 2 amp 3 Crystal ACIA 2 4576 MHz Fabricated jumper Aptronics 929955 00 use with jumper headers J1 J6 1 MCU supplied with the EVB have the configuration CONFIG register ROMON bit cleared to disable MCU internal ROM thereby allowing external EPROM containing the BUFFALO program to control EVB operations 2 Crystal frequencies from 4 to 8 MHz up to 8 4 MHz can be used without any changes to the 24 pF c
44. ace 16 Address Bus A 5 Note The Clock Ck amp RAN signals have been omitted for simplicity Dalhousie University 24 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics UO Schemes 1 lsolated I O scheme The microprocessor has dedicated instructions for I O operations The microprocessor has a separate address space for I O devices 2 Memory mapped I O scheme The microprocessor uses the same instruction set for I O operations The I O devices and memory components are resident in the same memory space Dalhousie University 25 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Synchronizing the Microprocessor and the Interface Chip The polling method 1 for input the microprocessor checks a status bit of the interface chip to find out if the interface chip has received new data from the input device 2 for output the microprocessor checks a status bit of the interface chip to find out if it can send new data to the interface chip The interrupt driven method 1 for input the interface chip interrupts the microprocessor whenever it has received new data from the input device 2 for output the interface chip interrupts the microprocessor whenever it can accept new data from the microprocessor Dalhousie University 26 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Motorola S Records Files containing Machine Code
45. alez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Instruction 2 CLRB Execution Step 3 Once decoded the corresponding action is taken i e ACCB lt 0 No operands are read in this Instruction just a single OpCode byte Neither any memory location is written as result of the operation Dalhousie University 94 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Cycle by Cycle Execution CLRB INH Cycle Addr Data R W Dalhousie University 95 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Cycle by cycle Execution Register Transfer Notation CLRB Et 1 cycle first half cycle second half Code FOP BAR PC 0003 PC 1 C004 RAVI 1 IR lt BDR gt 5F cycle first half cycle second half Code BAR PC C004 00 R W 1 discard BDR BD Dalhousie University 96 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Instruction JSR C080 Step 1 Place the value in PC on the address bus with a request to read the contents of that location Step 2 The opcode byte BD at C004 is returned to the CPU and PC is incremented by 1 Memory contents Address bus Address C000 C001 C002 C003 C004 C005 C006 C007 Data bus C008 Before After PC PC Instruction 3 Opcode read cycle Dalh
46. allel I O Control register PORTB equ 1004 Address for Port B data register PORTCL equ 1005 Address for Port C Latched data register Constants BITMASK equ 80 Bit mask for STAF flag in PIOC register Program Code org 000 To be loaded at C000 4ZBITMASK ACCA lt STAF bit mask bita PIOC Is STAF Set beq loop If NOT loop back amp wait until it is PORTCL lf YES ACCB lt data latched in PORTCL stab PORTB sending latched value just read to Port B bra loop Branch back and keep polling STAF for next valid input data in Port C end Dalhousie University 186 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm demultiplexed address bus A15 A0 68HC11 data bus EXTERNAL INPUT PORT INTERFACE Device External Parallel Port Example Dalhousie University 187 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Code for Servicing the External Input Port PSTATUS equ 8000 Port Status Address PDATA equ 98001 Port Data Address BUF START equ 0000 Start of Buffer BUF END equ DOFF Last element in Buffer org 000 Start of code Idaa PDATA Dummy read to clear port status Idx START Initialize IX pointer daa PSTATUS Get current status anda 49601000000 Check B by masking other bits POLL If status is still zero keep polling daa PDATA If NOT get data from port staa 0 X Store it in Buffer using
47. apacitors C6 and C7 and 10M ohm resistor R5 values 3 8 MHZ crystal obtains 2 MHz E clock 9600 baud MCU SCI operation 4 MHZ crystal obtains 1 MHz E clock 4800 baud MCU SCI operation Jose A Gonzalez Cueto 35 ty IVersi Dalhousie Un ECED 3204 Microprocessors M68HC11 Microcontroller BUFFALO Commands asm br eak g o load md mm p rm assemble disassemble memory locations set clear breakpoints execute instructions load S records via serial ports display memory contents view modify memory contents proceed continue execution view modify contents of CPU registers trace execution of instructions offers commands syntax amp brief description Dalhousie University 36 Jose A Gonzalez Cueto ROM 8K BYTES M68HC11 Microcontroller Figure 1 1 Block Diagram ECED 3204 Microprocessors PARALLEL I O N e e z gt 37 Jose A Gonzalez Cueto Dalhousie University M68HC11 Microcontroller ECED 3204 Microprocessors HC11 Memory Map 0000 256 Bytes 00FF 1000 103F k 64 Bytes External Available 000 8 KBytes FFCO FFFF INTERRUPT VECTOR External Memory has a meaning only for Expanded Mode S Either or both internal ROM amp EEPROM can be disabled 38 Jose A Gonzalez Cueto Dalhousie University 0000 0035 USER RAM INTERNAL RAM 0036 004A USER STACK POINTER MCU RESERVE
48. ficant Byte Valid for all memory segments LSByte Least Significant Byte Program Data amp Stack Dalhousie University 20 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Memory Addressing Memory consists of addressable locations A memory location has 2 components address and contents address contents Data transfer between CPU and memory address bus line data bus lines Dalhousie University 21 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Memory Module Address Bus A0 A12 Dalhousie University 22 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Busses e Address Bus Set of parallel lines used to specify a memory location Unidirectional CPU Memory lines bits required to address all memory locations e g For 8K memory module 8K 2 x 210 213 locations Hence 13 lines are required Data Bus Set of parallel lines carrying data instructions e g An 8 bit CPU can transfer 8 bits 1byte of data at a time Bidirectional CPU Memory e Control Bus Setoflines controlling data transfer Example of lines CS chip selection logic Clock synch signal Unidirectional CPU Memory R W Read or Write Dalhousie University 23 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Exercise Provide this 8 bit CPU with a 64Kbyte Memory Sp
49. gs the new data byte held by the SCDR Rx buffer RDR into the CPU ACCA register B When the unit is ready to accept a new byte from the CPU for transmission e TDRE condition staa 91026 Sendsthe data byte in ACCA to the SCI unit Tx buffer for transmission Dalhousie University 135 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm SCCR2 Register B B B B L RE Receive Enable TE Transmit Enable ILIE Idle Line Interrupt Enable RIE Receive Interrupt Enable TCIE Transmit Complete Interrupt Enable TIE Transmit Interrupt Enable 102D Example A Enable the SCI unit for reception only i e need to set the RE bit Address SCCR2 1020 Constant RE equ 04 Instructions RE Load ACCA with control byte staa SCCR2 Enables SCI for reception Dalhousie University 136 Jose A Gonzalez Cueto BAUD RATE SCDR Tx BUFFER CLOCK 10 11 BIT Tx SHIFT REGISTER PIN BUFFER Que 01 CONTROL SHIFT ENABLE JAM 0s TRANSFER Tx BUFFER PREAMBLE JAM 1s FORCE PIN DIRECTION OUT TRANSMITTER CONTROL LOGIC Asynchronous Serial Comm S z SCCR2 SCI CONTROL 2 SCI Rx SCI INTERRUPT INTERNAL REQUESTS REQUEST DATA BUS A SCI Transmitter Block Diagram ECED 3204 Microprocessors Jose A Gonzalez Cueto 137 Dal
50. housie University Asynchronous Serial Comm ECED 3204 Microprocessors DDD0 1216 10 11 BIT Rx SHIFT REGISTER PDO PIN BUFFER DATA 3 EJ AND CONTROL RECOVERY cw DISABLE MSB DRIVER RE M roce DEEN RWU ul del it SCCR1 SCI CONTROL 1 SCSR SCISTATUS 1 SCDR Rx BUFFER READ ONLY SCCR2 SCICONTROL 2 SCI Tx SCI INTERRUPT Y INTERNAL REQUESTS REQUEST DATA BUS SCI Receiver Block Diagram Jose A Gonzalez Cueto 138 Dalhousie University ECED 3204 Microprocessors Asynchronous Serial Comm SCSR Register B B B B B B B 102 En FE Framing Error Flag NF Noise Error Flag OR Over Run Error Flag IDLE Idle Line Detect Flag RDRF Receive Data Register Full Flag TC Transmit Complete Flag TDRE Transmit Data Register Empty Flag Dalhousie University 139 Jose A Gonzalez Cueto ECED 3204 Microprocessors Asynchronous Serial Comm TDRE Flag SET the SCI tx unit is ready to accept a new char from the CPU CLEAR the TDR is still full the SCI unit needs time to transmit and avoid Over Run Example Check whether the CPU can send a new char to the SCI without overwriting the last one sent Address Definitions SCSR equ 102E Status register address Constant Definitions TDRE equ 80 Mask for TDRE flag in SCSR Instructions SCSR
51. igit addb 30 Convert to ASCII stab 4 Y Store to units digit in decimal buffer xgdx 10s digit addb 30 Convert to ASCII stab 3 Y Store to 10s digit in decimal buffer pula pulb Restore registers pulx puly rts Return end Subroutine Example Part 2 Dalhousie University 68 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Labels shared with other module s public DBUFR Variable label other module s can have access to extern HtoD Subroutine label defined in other module Addresses BAUD Address for the SCI line speed register SCCR1 Address for the SCI control register 1 SCSR Address for the SCI status register SCDR Address for the SCI data register FFLOP FlipFlop Address STK_TOP Address of top of stack Constants JMPOpCode equ 7E OpCode for JMP instruction TIE TE equ 88 Control byte for SCCR2 flags TE 1 TIE 1 TDRE equ 80 TDRE bit mask for SCSR DELAY equ 110667 Value used to create a 32ms delay Main Program Example Part 1 Dalhousie University 69 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Program Code 000 be loaded C000 STK TOP Initializing stack pointer MainLoop DELAY Loading delay counter DelayLoop Decrementing counter DelayLoop If counter 0 keep decrementing UpdatePeriod Goto Update Signal Period MainLoop Repeat Loop
52. ing a 1 sec Delay with TOC 1 Delay interval is triggered 15 time 30 Counter staa Counter Initialization Idd TOC addd 33920 std TOC bra Return 2 With every SUCCESSFUL COMPARE after 1 time above dec Counter Decrement Counter bmi Check if Counter lt 0 bra Return If NOT keep decrementing it Execlask jsr ProcessX If YES take action Deactivate TOC interrupt One time Task TOC OC successful compare Initialization is triggering the interval Return clear OC F gt rti Dalhousie University 164 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Example Generating a 2 sec Square Wave in PA TOC2 TOC2 isr ldaa Counter bne CountDown daa 30 Counter staa Counter Initialization Idd TOC2 Update TOC2 If Counter is 0 2 Initialize TOC2 ae So i amp Counter anda 00111111 staa TCTL1 bra Return CountDown dec Counter bne Return daa TCTL1 When Counter reaches 0 from output pin logic PA Idaa TCTL1 Disconnect TOC2 set PA line to toggle its E SC SES value with next TOC2 successful compare Return lt clear OC2F gt rti Dalhousie University 165 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Example Generating a 2 sec Square Wave cont d 2 init 1 lt Counter 0 gt 2 Set PA logic to toggle its value with the next TOC2 successful compare 3 Set up
53. ion Whale Lake Press 2004 textbook REQUIRED 2 M68HC11 Reference Manual a k a The Pink Book Motorola 3 MC68HC11A8 Programming Reference Guide Motorola REQUIRED 4 M68HCIIEVB Evaluation Board User s Manual Motorola 5 Huang H MC68HC 1 1 An Introduction Software and Hardware Interfacing 2nd edition Delmar Thomson Learning 2000 textbook in Library amp Bookstore REQUIRED 6 Gonzalez Cueto J A ECED3204 Transparencies April 2006 REQUIRED 7 Martin F Introduction to 6811 Programming Media Lab MIT 8 Spasov P Microcontroller Technology The 68 11 4th edition Prentice Hall 2002 9 Driscoll Coughlin amp Villanucci Data Acquisition and Process Control with the Microcontroller Merril Macmillan 1994 in Library Dalhousie University 4 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introduction to the Course Course Contents 1 Introduction to the course Starts on Page 2 2 Introductory topics Starts on Page 9 Basic computer architecture CPU memory components and buses Numeric systems decimal binary hexadecimal Representation of information in memory the byte Different formats unsigned signed ASCII characters and BCD representation Memory architectures memory segments from a programming point of view Memory modules and its interaction with the address data and control buses The central processing unit CPU in
54. n one row or whole chip in one operation Flash memory 1 electrically programmable many times 2 electrically erasable many times 3 can only be erased in bulk Dalhousie University 13 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Memory Organization Logical point of view Address 0000 Contents of Mem Location 0000 0001 Contents of Mem Location 0001 Each memory location is associated with an address and Serves as storage for data or program code instructions Dalhousie University 14 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Basic Unit of Memory The Byte A Memory Location B B B B B Bo enen 101110019 11111010 uu ATUYS U Most Least Significant Significant Nibble Nibble 4 C Memory Content 4C 4C 0100 1100 0100 1100 f the content of this memory location is interpreted by the CPU as an instruction Machine Code Assembler Code 4C INCA Dalhousie University 15 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Data Formats Example 1 Example 2 Formats 1 Byte Range 0100 1000 1100 1010 d 0011 0110 Signed number 128 127 72 2 96 544 lt DEL gt 48 H out of range Or ASCII character 127 Table lookup If 4A J em me 202 See http www lookuptables com for Extended ASCII codes
55. ng the RAM module RAM input buffers are enabled since the HC11 R W is gated to the RAM W with the rising of E Valid data B6 is driven by the HC11 into the AD AD bus 5 The writing of the data bus value B6 to the corresponding memory location 034 is completed once Y6 RAM 1 RAM W are deasserted once they go back high Jose A Gonzalez Cueto 121 ty IVersi Dalhousie Un ECED 3204 Microprocessors M68HC11 Microcontroller Drawing a Timing Diagram Identify the Cycle Type a EPROM Read b RAM Read oR c RAM Write Find the Chip driving the AD lines a Address phase HC11 b Data phase HC11 EPROM on RAM Include hex values for each bus i e e AD AD AND e 373 Latch Output A Dalhousie University 122 Jose A Gonzalez Cueto M68HC11 Microcontroller ECED 3204 Microprocessors Timing Diagram Example first 4 cycles of Instruction 3 JSR C080 er 1 H H I i from HC11 from from HC1 Co Gn Cos Ca Cos XC 8 from RAM from RAM from RAM 68 11 AS C HC373 output 7 Jose A Gonzalez Cueto 123 Dalhousie University M68HC11 Microcontroller ECED 3204 Microprocessors 68HC11 68HC11 77 AD AD 68HCll AS HC373 output 68HCII RAW RAM Timing Diagram Example last 2 cycles of Instruction 3 JSR
56. ontroller E ADDRESS DATA ADDR DATA ONE BUS NEN Figure 10 2 Timing Summary for Oscillator Divider Signals Dalhousie University 112 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller one bus cycle 57 50 51 52 53 54 55 56 57 50 51 address phase data phase 6HC11 A15 A8 reads 68HC11 AD7 ADO 3 writes 3 3 data from 68HC1 1 AS 74373 output Dalhousie University 113 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Decoding AD Demultiplexing in the EVB 0 12 Switch Closes when E is High 74HC138 FFFF Dalhousie University 114 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller EVB Schematic Diagram Sheet 1 UNLESS OTHERWISE SPECIFIED gt DIGITAL SWITCH U7 OPERATES AS FOLLOWS ALL RESISTORS ARE IN OHMS 15 1 4W A CONTROL PINS Gi E S 6 12 OR 13 LOGIC ZERO 0 OFF OPEN SWITCH OPERATION LOGIC ONE 1 ON CLOSED DEVICE TYPE NUMBERS LISTED BELOW 15 FOR REFERENCE ONLY DEVICE TYPE NUMBER VARIES WITH MANUFACTURER DEVICE TYPE SWITCH SYMBOL 12 12V CONTROL MC68HC24 PRU MC74HC373 TRANSPARENT LATCH 2764 8K EPROM 250ns USER SUPPLIED 8K RAM 250ns MCM6164 8K RAM 250ns MC74HC138 DECODER OEMUX DIGITAL SWITCH MC1488P RS 232C DRIV
57. ose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Example Pulse Width Measurement using TIC3 PA CTLBYTE1 equ CTLBYTE2 equ Idaa Initialization staa 9600000001 Rising edge 9600000010 Falling edge CTLBYTE1 TCTL2 lt EdgeFlag lt Rising gt If EdgeFlag Rising Idd Part of ISR std TIC3 FirstEdge Polling Idaa CTLBYTE2 Enable falling staa TCTL2 edge detection Dalhousie University 161 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Example Pulse Width Measurement cont d If EdgeFlag Falling Part of ISR subd FirstEdge or std PWidth Successful lt EdgeFlag lt Rising gt Polling daa CTLBYTE1 Enable rising staa TCTL2 edge detection FirstEdge ds 2 PWidth ds 2 EdgeFlag ds 1 Dalhousie University 162 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Using IC Timer Interrupts 1 Set the EVB jump vector for the corresponding IC function 2 Enable TIC Function in TCTL2 3 Enable local interrupt mask IC 4 Enable global interrupt mask CCR Example Enabling interrupts from TIC3 Step 3 above TMSK1 equ 1022 Address of TMSK1 register IC3I equ 9600000001 Mask TMSK1 Part of oraa IC3I Initialization staa TMSK1 Dalhousie University 163 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Timer System Example Generat
58. ousie University 97 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Step 3 CPU performs two read cycles to obtain the extended jump address C080 from locations C005 and C006 At the end the value of PC is incremented to 007 Memory contents Memory contents Address Address bus 000 C001 C002 C003 C004 C005 C006 Data bus C007 Data bus C008 Before After first read After second read PC PC ES Instruction 3 Address byte read cycles Dalhousie University 98 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Step 4 The CPU stores pushes the current value of the PC or return address C007 onto the Stack Assume SP DFFF at the time Memory contents Memory contents Address bus Address Address bu DFFB DFFC DFFD DFFE DFFF E000 E001 E002 Data bus 003 After first write After second write Before SP SP zi Step 5 The CPU assigns the PC the jump address i e PC C080 where program execution continues by fetching an OpCode at that address Instruction 3 Execution Data bus Dalhousie University 99 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Cycle by Cycle Execution Cycle yer addr Data OP BD 1 hh 2 hl hhi Rtnlo SP 1 Rtnhi Dalhousie University 100 Jose A Gonzalez Cueto M68HC11 Microcontroller ECED 32
59. qu 20 Mask for RDRF flag in SCSR Instructions isr lt SCSR SCI status bita RDRF Is there a new available char bne SCl_rx_isr If YES goto service rx Check service causes other than RDRF or just branch to rti at the end rx isr SCDR Read available char from SCI Service reception Return from ISR Dalhousie University 149 Jose A Gonzalez Cueto Asynchronous Serial Comm ECED 3204 Microprocessors Interrupt Vector Jum INTERRUPT VECTOR Serial Communications Interface SCI Serial Peripheral Interface SPI Pulse Accumulator Input Edge Pulse Accumulator Overflow Timer Output Compare 5 Timer Output Compare 4 Timer Output Compare 3 Timer Output Compare 2 Timer Output Compare 1 Timer Input Capture 3 Timer Input Capture 2 Timer Input Capture 1 Real Time Interrupt XIRO Software Interrupt SWI Illegal Opcode Computer Operating Properly COP Clock Monitor p Table Jose A Gonzalez Cueto 150 ty IVersi Dalhousie Un ECED 3204 Microprocessors Asynchronous Serial Comm Example of EVB Jump Table Update for SCI Address Definitions JMPTBL1 equ 00C4 JMP OpCode Address in Table for SCI JMPTBL2 equ 00C5 Start of Jump Address in Table for SCI Constant Definitions JMPOpCode equ 7E OpCode for JMP instruction Instructions JMPOpCode ACCA lt JMP OpCode staa JMPTBL1 Storing OpCode to table Idx
60. roller M68HC11 Instruction Set Program Control Instructions 1 Conditional branches b Comparison of unsigned numbers bhi lt label gt Unsigned gt C Z 0 bhs label Unsigned gt C20 blo lt label gt lt C 1 bls lt label gt Unsigned lt C Z 1 Example cmpa 25 bhi Higher Program control will be transferred to the instruction at label Higher IF ACCA gt 25 otherwise the instruction following bhi is executed F3 243 gt 25 execution continues at Higher Dalhousie University 80 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller M68HC11 Instruction Set Program Control Instructions 1 Conditional branches c Comparison of signed numbers bgt lt label gt Signed gt Z N V 0 label Signed gt N V 0 blt label Signed lt N V 1 be label Signed lt Z N V 1 Example cmpa 25 bgt Greater Program control is transferred to the instruction at label Greater IF the 2 s complement value in gt 25 otherwise the instruction following bgt is executed If ACCA F3 13 lt 25 37 execution continues with the instruction following bgt Dalhousie University 81 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller M68HC11 Instruction Set Program Control Instructions 2 Unconditional branches jmp label
61. roprocessors Introductory Topics Computer Hardware Organization Control Unit Common BUS Arithmetic Logic Unit MEMORY Registe rs Prog ram Data Storage Storage Unit s oc O O O oc A Output Dalhousie University 11 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Semiconductor memory types Physical viewpoint Random access memory RAM can be read amp written Volatile gt information is lost when power is turned off Read only memory ROM can be read but not written by the processor Keeps information in absence of power supply Random access memory RAM Dynamic random access memory DRAM periodic refresh is required to maintain the contents of a DRAM chip Static random access memory SRAM no periodic refresh is required Read only memory ROM Mask programmed read only memory programmed when being manufactured Programmable read only memory PROM the memory chip can be programmed by the end user Dalhousie University 12 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introductory Topics Erasable programmable ROM EPROM 1 electrically programmable many times 2 erased by ultraviolet light through a window 3 erasable in bulk whole chip in one erasure operation Electrically erasable programmable ROM EEPROM 1 electrically programmable many times 2 electrically erasable many times 3 can be erased one locatio
62. rt data P thes lt STRB SS N VALID DATA for2E cycles from t wp peripheral data write delay time HC11 port E fall to STRB valid delay time Active High Port B strobed output timing Dalhousie University 181 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Port C Interlocked Input Handshake Protocol Read PORTOL E Pecar es ee TOT RU ITI ER STRB READY d N ACK Active High READY from HC11 Port to Device Y STRA l VALID DATA Rising Edge from Device to HC11 Port Portre ACK Acknowledge line signal Dalhousie University 182 Jose A Gonzalez Cueto ECED 3204 Microprocessors Parallel UO Comm Port C Input Handshake Protocol STRA is a valid data latch command asserted by the input device active edge is rising in previous figure STRB is acknowledge ready output driven by the 68HC11 active high in figure When ready for accepting new data the HC11 asserts or pulses STRB pin The input device places data on port C pins and asserts the STRA signal 1 The active edge of STRA latches data into the PORTCL register 2 Sets the STAF flag in PIOC register and 3 De asserts the STRB signal he de assertion of STRB inhibits the external device from strobing new data into port C New data can be applied on port C pins once the CPU reads PORTCL STAF clearing sequence 1 Read PIOC register
63. ssigned to the last instruction of the previous module Dalhousie University 58 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Assembler Directives The PUBLIC directive Example H Function ASCII2Dec Allows a module to share a label e g a subroutine with other modules by making its name public or known to others public ASCII2Dec ASCII2Dec Description of what it does and parameters or variables involved org C500 Code to follow starts at C500 psha Body of the subroutine rts Dalhousie University 59 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Assembler Directives The EXTERN directive Allows a module to have access to a public label external to this module i e not defined in this module Example extern ASCII2Dec jer ASCII2Dec Call to subroutine ASCII2Dec end Dalhousie University 60 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller The EQU directive Constants Unnamed Constants Examples Ids DFFF Initializing stack pointer cmpb Compare ACCB with ASCII A 41 staa 1004 Store lt ACCA gt to PORTB data register 1004 Named Constants Examples STK TOP DFFF Top of Stack at start of program Constant CAP_A equ A ASCII for uppercase Definition PORTB equ 1004 PORTB data register address Part lds 5 TOP lnitializing stack pointer cmpb Z
64. ssors M68HC11 Microcontroller M68HC11 Instruction Set Shift and Rotate Instructions 7 6 6 43210 Nd ARITHMETIC SHIFT LEFT ARITHMETIC SHIFT RIGHT ASL ASR 7 6 5 43 2 1 O 7 6 5 4 3 2 1 O LOGICAL SHIFT LEFT LOGICAL SHIFT RIGHT LSL LSR L AE ROTATE LEFT ROTATE RIGHT ROL ROR 15 14 13 15 14 13 ARITHMETIC OR LOGICAL LOGICAL SHIFT SHIFT LEFT DOUBLE RIGHT DOUBLE ASLD OR LSLD LSRD Dalhousie University 77 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller M68HC11 Instruction Set Shift and Rotate Instructions Examples 01 1 00000001 in asla ACCA 2 2 00000010 Carry flag 0 asla ACCA 2 4 00000100 Carry flag 0 asra ACCA 2 2 00000010 Carry flag 0 Idaa 1044 F6 11110110 asra ACCA 2 Bus 11111011 Carry Flag 0 2 3 FD 11111101 Carry Flag 1 Dalhousie University 78 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller M68HC11 Instruction Set Program Control Instructions 1 Conditional branches e Modify value of PC within 128 127 1 byte signed a Testing a single CCR bit label label bcs label bcc J label Dalhousie University 79 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcont
65. struction cycle and CPU registers UO components device polling and interrupts 3 The Motorola 68HC11 MicroController Unit MCU Starts on Page 27 Microprocessors vs microcontrollers The 68HC11A8 architecture pin description operation modes Address space and memory map of the 68HC11A8 MCU Introduction to the 68HC11 I O components Ports A E CPU Registers addressing mode instruction set Assembly language programming for the 68HC11 MCU assembler directives The development process assembler linker librarian and loader Motorola S record files The 68HC1 1EVB evaluation board memory map monitor program BUFFALO commands Allocation of external memory modules Using decoders the 74HC138 Demultiplexing address and data buses the 74HC373 latch The bus cycle RAM EPROM read cycles RAM write cycle Timing diagrams Cycle by cycle CPU execution Register transfer notation Laboratories 1 Introduction to the M68HC11EVB 2 Assembly language programming and 3 Instruction execution bus cycle amp timing diagrams Dalhousie University 5 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introduction to the Course Course Contents cont d 4 Asynchronous serial communication Starts on Page 126 Introduction e UART rx amp tx units Registers and character formation handling in both directions Serial to parallel parallel to serial conversion processes Errors and error handling e The RS 232 s
66. t half cycle second half BAR lt lt PC gt C080 PC PC 1 C081 IR lt lt BDR gt 6C cycle second half PC PC 1 C082 lt BDR gt 02 ATMPu lt 00 cycle first half BAR lt lt PC gt C081 cycle first half cycle second half M68HC11 Microcontroller BAR FFFF TMPio lt lt gt lt gt lt 00 02 02 0 discard lt lt BDR gt xx u lt gt lt 04 00 0 04 cycle first half BAR lt lt ATMP gt D402 cycle first half BAR lt FFFF 1 cycle second half DTMP o lt BDR gt 39 cycle second half discard amp BDR xx DTMPio 1 3A cycle first half BAR lt ATMP gt D402 cycle second half BDR DTMP o Jose A Gonzalez Cueto 106 ty ECED 3204 Microprocessors ALU carry bit modified as a result of low half 16 bit addition ATMP is sign extended in preparation for next cycle address computation CA which involves a 16 bit addition In cases like this of a positive 8 bit offset a 00 byte is used for the high half 16 bit addition in this case with Nu In cases of a signed 8 bit offset such as in relative branch instructions the ALU sign extends ATMP o using its MSB
67. tandard The 11 and asynchronous serial communication the SCI unit SCI tx unit SCI rx unit Error handling Control status registers rx tx data registers e CPU SCI unit interaction I O methods polling amp interrupts Asynchronous serial communication and the EVB e EVBconnectors EVB serial port connectors e The SCI and ACIA as the EVB UARTs Use of the D type flipflop and digital switches e ACIA decode amp programming e BUFFALO communication the RS232 window SCI terminal and EVB ports e RS232 drivers amp receivers Interrupts The HC11 interrupt vector table e Interrupt driven I O programming with interrupts Interrupts and the M68HC11EVB evaluation board Laboratories 4 Device polling amp terminal I O 5 Asynchronous serial communication and interrupts Dalhousie University 6 Jose A Gonzalez Cueto ECED 3204 Microprocessors Introduction to the Course Course Contents cont d 5 HC11 timer system Starts at Page 152 Main timer functions Output compare software timing waveform generation nput capture measuring period amp pulse width Long periods and counter overflows Algorithms for generating and measuring slow changing signals Solving missed output compares and missed overflows Interrupt priority Real time interrupt Laboratory 6 Timer functions 6 Parallel communication Starts at Page 170 General purpose
68. ter first read After second read C082 080 C081 P PC PC Instruction 4 Read cycles for Opcode amp Offset Dalhousie University 102 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Instruction INC 2 X Step 3 Effective operand address is computed using the ALU Assuming IX D400 Operand Address IX 2 D402 Memory contents Address bus Address D3FE D3FF 2 D400 D401 D402 D403 D404 D405 Data bus D406 Step 4 The CPU puts out the effective address D402 of the operand to be read and incremented next Its value is returned in the data bus 39 Instruction 4 Computing operand address amp operand read cycle Dalhousie University 103 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Instruction INC 2 X Step 5 Executing the increment operation Result 39 1 3A Memory contents Address bus Address D3FE D3FF D400 D401 D402 D403 D404 D405 Data bus D406 Step 6 Storing the result back to the memory address Instruction 4 Increment amp write cycles Dalhousie University 104 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Cycle by Cycle Execution _ Addr OP 6C ff X ff result Dalhousie University 105 Jose A Gonzalez Cueto Cycle by cycle Execution Register Transfer Notation INC 2 X IX D400 cycle firs
69. y location of memory module in the address space Auch Active Min Max 5141312 131109 1 Address Range 0000 0001 000x 0000 1 0010 0011 001 xxxx xx 2000 3FFF 0100 0101 010x 4000 5FFF 0110 0111 011 6000 7FFF 1000 1001 100x xxxx xx 8000 9FFF 1010 1011 101x A000 BFFF 1100 1101 110x C000 DFFF 1110 1111 111x Xxxx xx E000 FFFF Note 8 memory modules 8K each could be allocated in the 64K address space Dalhousie University 110 Jose A Gonzalez Cueto KII 9 gt N MC68HC11A8 PA0 IC3 1 2 2 5 1 PA4 OC4 OC1 PAS OC3 OC1 PA6 OC2 OC1 PA7 PAVOC1 DATA BUS oic LN k e co M68HC11 Microcontroller k LN D A a gt gt gt gt gt 2 EE aon 299v9pmgo9g 1 gt i 74HC373 AN E CC D E E CC Fees sng ss3daav PD1 TxD PD2 MISO CONNECT MODA LIR PD3 MOSI JUMPER FOR PDA SCK TEST MODE WS MODB VsTpy PEO ANO 1 PE2 AN2 PE AN3 PE4 AN4 5 5 PE6 AN6 PET AN7 CONTROL BUS ECED 3204 Microprocessors Figure 2 22 Basic Expanded Mode Connections Sheet 1 of 2 Jose A Gonzalez Cueto 111 ty IVersi Dalhousie Un ECED 3204 Microprocessors M68HC11 Microc
70. z Cueto M68HC11 Microcontroller ECED 3204 Microprocessors Development Process Editor human readable results including assembly errors may link multiple OBJ files loader is part of operating system or possibly part of a debugger Computer System 55 Jose A Gonzalez Cueto Dalhousie University ECED 3204 Microprocessors M68HC11 Microcontroller Assembler Line Statement Format Label Operation Operand Comment Field Field Field Field Idab 26 Initializing Delay Counter DelayLoop dech Decrement Counter Value bne DelayLoop If Counter not Zero stay in the Loop Dalhousie University 56 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Assembler Directives The ORG directive Example Org C000 Code to follow starts at C000 Ids StkTop Initializing Stack Pointer Register org DFFF Base of stack identified with label StkTop StkTop Address DFFF is assigned to this label end P The END directive Instruct the assembler to stop the assembly process for this module Any directive or code following it is ignored Dalhousie University 57 Jose A Gonzalez Cueto ECED 3204 Microprocessors M68HC11 Microcontroller Assembler Directives The AORG directive absolute ORG Instruct the linker not to relocate the code segment following it Example aorg C300 Code to follow starts at C300 Counter No matter what memory was inca a

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