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DAQ-STC Technical Reference Manual

1. P Texti Textw M CONVERT SRC Tds Tds Tds gt gt CONVERT Name Description Minimum Maximum Tds CONVERT_SRC to CONVERT asserted 21 65 Textw CONVERT_SRC width 50 Texti CONVERT_SRC interval 100 All timing values are in nanoseconds Figure 2 20 External CONVERT_SRC Timing 2 7 7 External Triggers Each of the external signals will be latched and recognized by the DAQ STC in one of two configurations The latching of the external signal generates an internal version of the signal which the internal control circuit uses The control circuit then can recognize the internal signal and change state The latching and recognition of the external signal are software programmable to occur in synchronous mode or asynchronous mode In synchronous mode the DAQ STC is internally synchronizing the signal to prevent metastability In asynchronous mode the external signal must already be synchronized to the state clock allowing the DAQ STC to use the signal directly Each of the external inputs to the DAQ STC can be edge or level sensitive The level sensitive signals are passed directly to the latch and recognition circuitry The edge sensitive mode generates an intermediate internal signal by prelatching the external signal at its active edge This intermediate signal is routed to the latching and recognition circuitry The edg
2. N S S _ Tehft SHIFTIN fs AIFFF AIFHF K AIFEF X Y N SC_TC last Tflgreq gt Tflgreq p gt Teodreq Tflgreq R AIFREQ MEE Xt ls Name Description Minimum Maximum Tflgreq FIFO flag change to AIFREQ change 7 22 Teodreq End of acquisition to AIFREQ change 3 9 Tshft Last SC TC to SHIFTIN 0 timing values are nanoseconds Figure 2 17 Data FIFO Timing DAQ STC Technical Reference Manual 2 88 National Instruments Corporation 2 1 4 Configuration Memory The DAQ STC fully supports the FIFO based configuration memory that can be incremented on every conversion pulse The related signals are the outputs LOCALMUX CLK EXTMUX CLK EXTSTROBE and LOCALMUX FFRT and the input MUXFEF These are shown in Figure 2 18 Chapter 2 Analog Input Timing Control EXTSTROBE MUXFEF OUT CLK CONVERT SOC EXTMUX CLK LOCALMUX FFRT Testrb Texmxstrb 4 ox XX x XALCX XU Ly gt Toscmx Tsocmx pee LOCALMUX CLK JF jal Toscexmx N Tmxexmx Tert Tmxdrt Tmxfrt gt Figure 2 18 Configuration Memory Timing In Figure 2 18 the CONVERT pulse is generated internally and has a pulsewidth equal to the signal that generates the pulse one
3. Address Register Name 12 13 GO Save Registers 14 15 Save Registers 16 17 AO UI Save Registers 18 19 AO BC Save Registers 20 21 AO UC Save Registers 23 AO UD Save Register 25 AI SI2 Save Register 26 AI DIV Save Register 27 Joint Status 1 Register 28 DIO Serial Input Register 29 Joint Status 2 Register 64 65 AI SI Save Registers 66 67 AI SC Save Registers Write registers are presented in their entirety followed by read registers DAQ STC Technical Reference Manual B 8 National Instruments Corporation Appendix B Register Information Bitfields Bits in the register bit maps are organized into bitfields A bitfield can contain one or more bits Only bits with contiguous locations within a register can belong to a bitfield The high and low pairs of load and save registers for 24 bit counters are also treated as bitfields To locate a particular bitfield description within the document refer to the Bitfield Descriptions section of the chapter indicated in Table B 3 Table B 3 Bitfield Description Guide Bitfield Prefix Location in Manual Analog Trigger Chapter 10 BD Chapter 5 Clock Chapter 10 Control Chapter 7 DIO Chapter 7 AI Chapter 2 AO Chapter 3 FOUT Chapter 10 Gi Chapter 4 Source Chapter 4 Generic Status Chapter 7 Interrupt Chapter 8 Misc Counter Chapter 10 Pass Thru Chapt
4. STOP SC Counter 3 SC TC Figure 2 12 Pretrigger Acquisition Mode 2 4 3 3 Continuous Acquisition Mode In the continuous acquisition mode the STARTI trigger initiates the scan sequence The hardware continues to generate scans until the software issues an AI End On End Of Scan command an AI End On SC TC command or a software reset command The AI End On End Of Scan command terminates the scan sequence at the end of the next scan The AI End On SC TC command terminates the scan sequence at the next SC TC SC counter TC The software reset command terminates the scan sequence immediately National Instruments Corporation 2 15 DAQ STC Technical Reference Manual Chapter 2 2 4 4 Analog Input Timing Control 2 4 3 4 Staged Acquisition Staged acquisition refers to the software action required to implement more than one posttrigger acquisition sequence each having unique timing parameters This section discusses how the software might handle staged acquisition In a programming sequence that occurs prior to the START trigger software loads the parameter values for the first two acquisition sequences Software also configures the counters to switch load registers after each acquisition sequence has completed providing for the switch from one sequence to the next While the second sequence is in progress software loads the parameters for the th
5. Table 10 1 Timebases Derived from IN TIMEBASE Continued Timebase Related Bitfields Divide Options AI OUT TIMEBASE AI Output Divide By 2 1 2 AO IN TIMEBASEI AO Source Divide By 2 1 2 AO OUT TIMEBASE AO Output Divide By 2 1 2 IN TIMEBASEI Source Divide By 2 1 2 FOUT TIMEBASE FOUT Timebase Select 1 2 SERIAL TIMEBASE DIO Serial Divide 2 1 2 Slow Internal Timebase 10 4 Frequency Output The frequency output pin FOUT provides a divide down version of the master timebase for board use FOUT can output FOUT TIMEBASE divided by 1 through 16 The duty cycle is equal to 5096 when the divider setting is 1 or an even number When the divider is set to an odd number except 1 the duty cycle is less than 5096 The duty cycle is determined with the following equation duty cycle 2 N D where D the divider setting and N D 1 2 In other words the output will be high for N time base clocks and low for N 1 timebase clocks 10 5 Analog Trigger The analog trigger circuit provides a method of triggering the analog input analog output or general purpose counter timer operation based on the significant instances of an analog waveform Two voltage references LOW and HI are typically available for comparison External to the DAQ STC a comparator tests the analog waveform and generates a digital value indicating whether the analog waveform is below the LOW value or above the HI valu
6. 2 97 2 7 8 2 START Trigger and SCAN IN PROG Assertion 2 100 DAQ STC Technical Reference Manual vi National Instruments Corporation 2 8 Chapter 3 Contents 2 7 8 3 SCAN IN PROG 2 103 2 7 8 4 STOP cene e 2 103 2 7 9 Counter Outputs ete retten te reet Pee eee eerte 2 105 2 7 9 1 SE TO ante Soest uai en eC aves 2 105 2 7 92 ea ER 2 105 2 7 9 3 DIV tree REDE 2 106 2 7 10 Macro Level Analog Input Timing 2 106 2 111 External deterrere EORR 2 109 Detailed Description ii ier tree ehe 2 112 2 8 1 Internal Signals and Operation eee 2 113 2 8 2 Trigger Selection and Conditioning ees 2 119 2 8 2 1 Using Edge Detection eee 2 122 2 8 2 2 Using Synchronization eese 2 122 2 8 2 3 Trigger Signals esee eter 2 122 2 8 3 Analog Input Counters 1 eene 2 123 2 8 3 1 SC Counters a ntes e ene tren 2 124 2 8 3 2 SC neni o etse 2 124 2 8 3 3 SI Counter nne ttti e 2 126 2 8 3 4 SI Control eR RERUM 2 126 2 8 3 5 SI2 Counter 5 idee rane ra iie 2 127 2 8 3 6 507 Control ita eS 2 127 2 8 3 7 DIV Counter nne oieee dpt eR 2 128 2 8 3 8 DIV Control ie pm sane duties 2
7. 4 0 Figure 4 12 Single Pulse 4 10 Figure 4 13 Single Triggered Pulse 4 10 Figure 4 14 Retriggerable Single Pulse Generation eee 4 11 Figure 4 15 Buffered Retriggerable Single Pulse 4 12 Figure 4 16 Continuous Pulse Train Generation sse 4 13 Figure 4 17 Buffered Static Pulse Train Generation eese 4 13 Figure 4 18 Buffered Pulse Train Generation 4 14 Figure 4 19 Frequency Shift Keying 4 15 Figure 4 20 Pulse Generation for 5 4 15 Figure 4 21 Minimum Period and Minimum Pulsewidth 4 55 Figure 4 22 CTRSRC to CTROUT Timing 4 56 Figure 4 23 GATE Minimum 4 56 Figure 4 24 CTRGATE to CTROUT 4 57 Figure 4 25 CTRGATE to INTERRUPT 4 57 Figure 4 26 Setup Timing Internal Timing 4 58 Figure 4 27 Setup Timing External Timing 4 59 Figure 4 28 U D Setup Timing Internal Timing Mode 4 60 Figure 4 29 U D Setup Timing External Timing Mode 4 60 Figure 4 30 General Purpose Counter Timer Model sess 4
8. Counter Load Counter Value Counter TC G OUT Figure 4 48 Pulse Generation for ETS National Instruments Corporation 4 87 DAQ STC Technical Reference Manual Programmable Function Inputs 5 1 Overview This chapter explains the PFI module on the DAQ STC The 10 PFI lines provide a user configurable interface to the board I O connector External timing trigger and control signals can be input through the PFI and routed internally within the DAQ STC Also the PFI lines can output internally generated timing trigger and control signals on dedicated pins when the pins are not used as inputs 5 2 Features The PFI module has the following features Ten individually programmable bidirectional lines 9 mA sink current 5 mA source current Analog input timing module interface Inputs STARTI START2 START STOP SI source CONVERT source and external gate Outputs STARTI START2 START CONVERT and SCAN IN PROG Analog output timing module interface nputs STARTI START UPDATE UI source UI2 source and secondary external gate Outputs 5 and UPDATE General purpose counter timer interface Inputs GO source GO gate source and G1 gate Outputs GO source GO gate G1 source and G1 gate National Instruments Corporation 5 1 DAQ STC Technical Reference Manual Chapte
9. Second Irq B Enable Register Window Address Register Address 76 Type Write only Address 0 Type Write only 15 Reserved 15 Window Address 14 Reserved 14 Window Address 13 Reserved 13 Window Address 12 Reserved 12 Window Address 11 Pass Thru 1 Second Enable 11 Window Address 10 Gate Second Enable 10 Window Address 9 GI TC Second Irq Enable 9 Window Address 8 AO FIFO Second Irq Enable 8 Window Address 7 AO UD TC Second Irq Enable 7 Window Address 6 AO UC TC Second Irq Enable 6 Window Address 5 AO Second Enable 5 Window Address 4 AO STOP Second Irq Enable 4 Window Address 3 AO START Second Enable 3 Window Address 2 AO UPDATE Second Enable 2 Window Address 1 AO STARTI Second Enable 1 Window Address 0 AO TC Second Enable 0 Window Address Window Data Register Write Strobe 0 Register Address 1 Type Read Write Address 82 Type Write only 15 Window Data 15 Reserved 14 Window Data 14 Reserved 13 Window Data 13 Reserved 12 Window Data 12 Reserved 11 Window Data 11 Reserved 10 Window Data 10 Reserved 9 Window Data 9 Reserved 8 Window Data 8 Reserved 7 Window Data 7 Reserved 6 Window Data 6 Reserved 5 Window Data 5 Reserved 4 Window Data 4 Reserved 3 Window Data 3 Reserved 2 Window Data 2 Reserved 1 Window Data
10. Xs I Tcup2 Teup2 UPDATE2 SRC ff x gt Toup2 gt UPDATE2 OUT N Name Description Minimum Maximum Tcup2 UI2 SRC to UPDATE2 asserted 14 43 Tsup2 UPDATE2 SRC pulsewidth 1 1 Toup2 UPDATE2 OUT pulsewidth 1 3 1 5 3 5 Tcup2d OUT_CLK to UPDATE2 OUT deasserted 12 42 All timing values are in nanoseconds Figure 3 18 Secondary Analog Output Timing The numbers in parentheses indicate the number of clock periods that occur at the minimum and maximum delays because those parameters are clock edge driven with possible additional gate delays The UPDATE2 signal can be programmed to one or three output clock periods or one source clock period see AO_UPDATE2_Pulse_Width The synchronization for UPDATE2 OUT counts either three or seven output clock edges regardless of polarity National Instruments Corporation 3 93 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 3 7 6 Decoded Signal Timing The DAQ STC provides direct support for two DAC groups The output signals LDACO and LDAC1 can be directly connected to DACs These signals can be individually configured for timed or immediate update modes see DACi Update Mode In the immediate update mode LDACi is driven inactive only during either TMRDACWR or CPUDACWR This allows the DACs to immediately update to their new values In the timed update mode LDACi is a multiplexer wh
11. 4 8 4 4 2 5 Buffered Pulsewidth Measurement 4 9 4 4 3 Pulse Generation irt ttr RP RERO ER 4 9 4 4 3 1 Single Pulse Generation sese 4 9 4 4 3 2 Single Triggered Pulse Generation 4 10 4 4 3 3 Retriggerable Single Pulse Generation 4 11 4 4 3 4 Buffered Retriggerable Single Pulse Generation 4 11 4 4 4 Pulse Train 4 12 4 4 41 Continuous Pulse Train Generation 4 12 4 4 4 2 Buffered Static Pulse Train Generation 4 13 4 4 4 3 Buffered Pulse Train Generation 4 14 4 4 4 4 Frequency Shift Keying 4 14 4 4 4 5 Pulse Generation for 4 15 Ade Pininterfacezn a catt t ddan cee EORR RUP PEE EYE 4 16 DAQ STC Technical Reference Manual X National Instruments Corporation Contents 4 6 Programming Information eese ener ener ene 4 17 4 6 1 Programming for a GPCT Operation see 4 17 4 6 1 1 Overy EW iii ette diete eo Rls 4 17 4 6 1 2 Notation ni rrt rtl rrr ER 4 18 4 6 1 3 Resettifig eiie be eerte 4 18 4 6 1 4 4 18 4 6 1 5 Simple Event 4 19 4 6 1 6 Buffered Event Counting eese 4 20 4 6 1 7 Relative Position Sensing esee 4 23 4 6 1
12. Figure 2 29 START1 Delays Synchronous Mode External CONVERT DAQ STC Technical Reference Manual 2 98 National Instruments Corporation Chapter 2 Analog Input Timing Control START2 CONVERT SRC PFI1 Al_START2 RTSI_TRIGGER lt 0 6 gt RTSI_BRD lt 0 3 gt Tpfi Trtsi Tord Figure 2 30 START2 Delays Synchronous Mode External CONVERT Table 2 6 START1 and START2 Timing Synchronous Mode Name Description Minimum Maximum Tpfi Source to PFI output 10 41 Trtsi Source to RTSI output 12 46 Tbrd Source to BRD output 18 63 All timing values are in nanoseconds Asynchronous Mode When you select asynchronous mode for START or START2 the external trigger itself generates the rising edge of the output Figure 2 31 shows the propagation delays for START Figure 2 32 shows the propagation delays for START2 START1 PFIO Al_START1 RTSI_TRIGGER lt 0 6 gt RTSI BRD O0 3 J o Tpfi Trtsi Tord Figure 2 31 START1 Delays Asynchronous Mode National Instruments Corporation 2 99 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control START2 jT pfi PFI1 AI START2 N Trtsi RTSI TRIGGER O 6 RTSI BRD O0 3 X Figure 2 32 START2 Delays Asynch
13. External UPDATE START1 UPDATE MM Figure 3 10 External UPDATE Timing 3 4 5 Buffer Timing and Control for Primary Analog Output Sequences of UPDATE pulses are organized into buffers A buffer consists of a fixed number of data points that are output at a constant rate The DAQ STC can easily provide timing for multiple iterations of a single buffer MISB When a sequence of buffers is output consecutively a waveform is generated A waveform may consist of one MISB or it may consist of multiple MISBs The DAQ STC provides direct hardware support for the output of a single MISB output of one MISB followed immediately by a second MISB and output of two MISBs which alternate The DAQ STC can generate even more complex waveforms DAQ STC Technical Reference Manual 3 12 National Instruments Corporation Chapter 3 Analog Output Timing Control using software interrupts This section discusses the buffer timing modes available with the DAQ STC 3 4 5 1 Single Buffer Mode In the single buffer mode the DAQ STC provides UPDATE timing for one MISB Software programs the UC counter with the number of points in the buffer and programs the BC counter with the number of buffer repetitions The STARTI trigger initiates the analog output Single buffer mode analog output can be retriggerable or nonretriggerable In the retriggerable single buffer mode additional STARTI pulses will initiat
14. ACK Figure 3 35 START1 Routing Logic Figure 3 36 depicts the control for EXT and EXT GATE2 lt 0 9 gt MOUT N MOUT D Q OUT RTSI_TRIGGER lt 0 6 gt SRC P R POLARITY SEL lt 0 4 gt Figure 3 36 EXT_GATE and EXT_GATE2 Routing Logic Table 3 7 summarizes the selections available for each of the trigger signals through the PFI selector Table 3 7 PFI Selectors MUX 0 1 10 11 17 18 19 20 31 AO_START1_Source SW PFI lt 0 9 gt RTSI lt 0 6 gt AI STI GND AO START Source SW UC TC lt 0 9 gt RTSI lt 0 6 gt GND AO_UPDATE_Source UI_TC PFI lt 0 9 gt RTSI lt 0 6 gt GOUTI GND National Instruments Corporation 3 115 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control Table 3 7 PFI Selectors Continued MUX 0 1 10 11 17 18 19 20 31 AO Source AO TBI PFI lt 0 9 gt RTSI lt 0 6 gt TB2 GND AO UD Source AO TBLI PFI lt 0 9 gt RTSI lt 0 6 gt GO_TC TB2 GND AO UI External Gate PFI lt 0 9 gt RTSI lt 0 6 gt GND AO_UI2_External_Gate PFI lt 0 9 gt RTSI lt 0 6 gt GND Key AI STI The internal analog input signal STARTI AO TBI The internal analog output signal AO IN TIMEBASEI GO TC The signal from general purpose counter 0 GI TC The signal from general purpose counter 1 GOUTI The OUT signal fro
15. UC HOLD EXT GATE gt UC Save TMRDACWR AOFREQ 4 4 ULSRC CPUDACWR lt 4 UI2 Load A 02 Load B 008 lt 0 3 gt 4 lt 0 3 gt UPDATE 02 76 2 SRC Y Y START UPDATE2 Control 012 CE E AOFEF STOP gt 02 TC UI2_SRC gt ule UI2 Counter oo gt Control UP TC AOFFF ogic EXT 2 CPUDACREQ gt Figure 3 34 AOTM Block Diagram 3 8 1 Internal Signals and Operation Table 3 6 contains brief descriptions of the internal signals shown in the block diagram or discussed in section 3 8 Detailed Description Table 3 6 Internal Signals Signal Description AO ENDI End on UC_TC This signal is the schematic name for the synchronized version of the register map bitfield AO End On UC TC AO END2 End on BC_TC This signal is the schematic name for the synchronized version of the register map bitfield AO End On BC TC National Instruments Corporation 3 109 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control Table 3 6 Internal Signals Continued Signal Description AO IN TIMEBASEI Internal Timebase for the Analog Output Module AO TIMEBASEI can be selected to be the same as OSC or it can be OSC divided by two Related bitfield
16. _ CO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Load Load Load Load Load Load Load Load G1 Load B Registers Address 34 15 14 13 N Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Load Load G1 Load G1 Load Load Load G1 Load Load DAQ STC Technical Reference Manual Register Information Type Write only Type Write only Appendix B 15 14 13 N OO CO eK 15 14 13 N _ OO Register Information G1 Load B Registers Address 35 Type Write only Load B Load B Load B Load B Load B Load B Load B Load B Load Load Load Load Load G1 Load Load B Load B G1 Save Registers Address 14 Type Read only Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Save Value Save Value Save Value Save Value Save Value Save Value Save Value Save Value DAQ STC Technical Reference Manual Address 27 ee _ 95
17. Figure 10 3 High Window Mode DAQ STC Technical Reference Manual 10 4 National Instruments Corporation Chapter 10 Miscellaneous Functions In the middle window mode the trigger indicates when the signal value is between the LOW value and the HI value HI Value 4 ES LOW Value Trigger Eq E Figure 10 4 Middle Window Mode In the high hysteresis mode the trigger indicates when the signal value is greater than the HI value with the hysteresis specified by the LOW value Note To use analog triggering in any of the hysteresis modes reset the hysteresis register during initialization using one of the analog trigger reset bits HI Value ensina fe LOW Rp ei in fN a Trigger AEAN Re Se Figure 10 5 High Hysteresis Mode National Instruments Corporation 10 5 DAQ STC Technical Reference Manual Chapter 10 Miscellaneous Functions In the low hysteresis mode the trigger indicates when the signal value is less than the LOW value with the hysteresis specified by the HI value HI Value E RUP E LOW Valles ue N ee e a ae EA T 1 1 1 1 1 1 L 1 1 1 1 1 Trigger Figure 10 6 Low Hysteresis Mode 10 6 Test Mode The DAQ STC provides an in circuit tes
18. 2 7 2 4 1 3 Configuration FIFO and External Multiplexer Control eee 2 7 2 4 1 4 CONVERT Timing entere 2 9 2 4 2 Scan Level Timing and Control 2 11 2 4 2 1 Internal START 2 11 2 4 2 2 External START 2 12 2 4 3 Acquisition Level Timing and Control 2 14 2 4 3 1 Posttrigger Acquisition 2 14 2 4 3 2 Pretrigger Acquisition 2 14 2 4 3 3 Continuous Acquisition 2 15 2 4 3 4 Staged 2 16 2 4 3 5 Master Slave 000 2 16 2 4 4 enero diadema HO ae 2 16 2 4 4 1 Free Run Gating 2 17 National Instruments Corporation V DAQ STC Technical Reference Manual Contents 2 4 4 2 Halt Gating 2 17 2 4 5 Single Wire Mode iecore Rein 2 18 2 5 Pin Locator Interface eee etse UE URS 2 19 2 6 Programming Information 2 24 2 6 1 Register and Bitfield Programming Considerations 2 24 2 6 2 Windowing 2 25 2 6 3 Programming for an Analog Input Operation 2 25 2 6 3 1 Reseitting eoe A RR Oe POOR 2 26 2 6 3 2 Board Power up Initialization sess 2 27 2 6 3 3 Initialize Configuration Memory Output 2 28 2 6 3 4 Board Environment Setup 2 29 2 6 3 5 FIEO Requ est te ero rites 2 30 2 6 3 6 Hardware Gate Programming sees 2 30 2 6 3 7 Software G
19. Else if local buffer mode with pauses then AO_Continuous 1 AO Mute A 0 AO Mute 1 AO BC Initial Load Source 0 AO BC Load A number of buffer iterations 1 2 BC Load 1 AO UC Initial Load Source 0 AO UC Load A number of updates in each buffer X AO UC Load 1 x AO UC Load A number of updates in each buffer 1 AO BC Load B number of buffer repetitions in pause MISB 1 AO UC Load B number of updates in each buffer of pause MISB 1 AO BC Reload Mode 1 AO UC Switch Load Every BC 1 National Instruments Corporation 3 25 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control Else AO_Continuous 0 AO will stop on BC_TC or 1 AO will continue until END command AO_BC_Initial_Load_Source 0 AO_BC_Load_A number of buffer iterations 1 gt AO BC Load 1 X AO UC Initial Load Source 0 AO UC Load A z number of updates in each buffer L AO_UC_Load 1 AO UC Load number of updates in each buffer 1 last load register AO_Configuration_End 1 End critical section 3 6 1 6 Update Selection Use this function to select the update event You can specify an update rate by choosing an internally generated periodic event For waveform staging operation in the internal update mode we assume that the parameters for each stage are stored in an array defined as follows
20. RUN REUS 3 7 1 1 OUT itn DRE 372 DAQ STC Driven Analog Output 3 7 3 CPU Driven Analog Output 3 7 4 DAQ STC and CPU Driven Analog Output Timing 3 7 5 Secondary Analog Output 3 7 6 Decoded Signal 3 7 7 Local Buffer Mode 3 7 8 Unbuffered Data Interface 3 7 9 Maximum Update Rate 3 7 10 External Trigger 27 11 Tngger Output uere pre pe penc eR 3 7 11 1 STARTITTIgBetu eerte ae 37 12 3 7124 E 3 7 12 2 UG k O ui arae cos DB 3 8 Detailed Desctiption iinis is deett ere e Rees 3 8 1 Internal Signals and Operation eee 3 8 2 Trigger Selection and Conditioning eee 3 8 2 1 Using Edge Detection eee 3 8 2 2 Using Synchronization eee 3 8 2 3 Trigger Signals eene eee 3 8 3 Analog Output 3 8 3 1 UI Counter iare enne ree 3 8 3 2 3 8 3 3 Counter 3 8 3 4 UG Control 3 8 3 5 BC Counter onset aee mtn dein 3 8 3 6 BC Control ne teat der Sacer chine ke Contents National Instruments Corporation ix DAQ STC Technical Reference Manual Contents 3 8 3 7 2
21. Input rise or fall time Schmitt Buffer 15 DAQ STC Technical Reference Manual A 2 Seres 10 pF typ 25 pF max Ben 10 pF typ 25 pF max EM 10 pF typ 25 pF max 0 C min 70 max Stu min 0 8 V max bibe 2 2 V min VDD V max 0 ns min 200 ns max 0 ns min 10 ms max National Instruments Corporation Appendix A Specifications Positive Schmitt trigger voltage 1 2 V min 2 4 V max Negative Schmitt trigger voltage 0 6 V min 1 8 V max Hysteresis voltage 2 0 3 V min 1 5 V max DC Characteristics Quiescent current Vi or 0 1 WA typ 400 LA max Input leakage current IL Pin Type Min Typ Max Units IS or GND 105 10 B18TU B9TU OD18U 40 100 270 O4TU IU V1 GND 105 V1 GND 0 35 1 0 2 2 mA ID V1 VDD 45 120 300 Off state output leakage current Vo or 10 uA max Input clamp voltage IL 2 18 mA sees 1 2 V min Output short circuit current V0 fetes actes ies 250 mA min Note The rating is for only one output operating in this mode for less than 1 s Low level output current IoL Vor 2 0 4 V Pin Type Value O4TU 4 5 mA min B9TU O9TU O9 9 0 mA min B18TU OD18U 24 0 mA min Note VDD 5 V 10 TA 40 to 85
22. If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address E Mail Address Phone Fax Mail t0 Technical Publications Faxt0 Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway 512 794 5678 Austin Texas 78730 5039 Glossary Prefix Meaning Value p pico 10 12 n nano 10 9 u micro 10 6 m milli 10 3 k kilo 10 M mega 106 G giga 109 Symbol Y indicates the end of a sequence ohms A lt 1 7 gt address signal channels 1 through 7 A D analog to digital ADC A D converter ADFEF AI data FIFO empty flag ADFFF AI data FIFO full flag ADFHF AI data FIFO empty flag ADFREQ AI data FIFO half full flag ADR STARTI internal STARTI signal without Master Slave synchronization ADR START2 START signal without master slave synchronization National Instruments Corporation G 1 DAQ STC Technical Reference Manual Glossary AD START AD STARTI AD VSTART2 AI AIERROR AIFEF AIFFF AIFHF AIFIFOREQ AIFREQ AITM AI FIFO SHIFTIN AI IN TIMEBASEI AI OUT TIMEBASE AI STI AI ST2 AI STOP IN AI STOP OUT AI TBI ANALOG TRIG DRIVE ANALOG IN HI ANALOG TRIG IN LO AO AO STARTI output version of START signal output version of STARTI signal o
23. IO Bidirection Pin Register Type Write only Reserved Reserved Reserved Reserved Reserved Reserved BD 9 Pin Dir BD 9 Pin Dir BD 9 Pin Dir BD 9 Pin Dir BD 9 Pin Dir BD 9 Pin Dir BD 9 Pin Dir BD 9 Pin Dir BD 9 Pin Dir BD 9 Pin Dir National Instruments Corporation Joint Reset Register Address 72 Type Write only 15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 Software Reset 10 AO UD Configuration End 9 AO Configuration End 8 AI Configuration End 7 Reserved 6 AO UD Configuration Start 5 AO Configuration Start 4 AI Configuration Start 3 Reset 2 GO Reset 1 AO Reset O AI Reset Joint Status 2 Register Address 29 Type Read only 15 Permanent Stale Data St 14 GO Permanent Stale Data St 13 GI HW Save St 12 G0 HW Save St 11 Generic Status 10 Generic Status 9 Generic Status 8 Generic Status 7 AI Scan In Progress St 6 AI Config Memory Empty St 5 AO TMRDACWRs In Progress St 4 AI St 3 AI SOC St 2 AO STOP St 1 Output St 0 GO Output St National Instruments Corporation Appendix B Register Information Joint Status 1 Register Address 27 Type Read only 15 AI Last Shiftin St 14 AO UC Q St 13 AO UD Gate St 12 DIO Serial IO In Progress St 11 AO External Gate St 10 AI External Gate St 9 AI SD Q St 8 512 St 7 AO_Start_Sto
24. lt 0 3 gt O4TU AO Address Outputs These active high outputs indicate which DAC channel is being accessed In multiple channel analog output mode the AO_ADDR lines increment starting from 0 on each TMRDACWR trailing edge During a CPU DAC write the AO ADDR lines take on the value present on the inputs lt 0 3 gt Destination DAC address selector Related bitfields AO Multiple Channels AO Number Of Channels AOFEF IU Data FIFO Empty Flag This input is used to generate the FIFO interrupt and the FIFO request signal AOFREQ based on the status of the FIFO and to delay the TMRDACWR pulses when the AO data FIFO is empty The input polarity is selectable and the input state can be directly observed in one of the status registers Source AO data FIFO Related bitfields AO FIFO Flags Polarity AO FIFO Empty St DAQ STC Technical Reference Manual 3 16 National Instruments Corporation Chapter 3 Analog Output Timing Control Table 3 1 Pin Interface Continued Pin Name Type Description AOFFF IU Data FIFO Full Flag This input is used to generate the FIFO interrupt and the FIFO request signal AOFREQ based on the status of the FIFO The input polarity is selectable and the input state can be directly observed in one of the status registers Source AO data FIFO Related bitfields AO FIFO Flags Polarity AO FIFO Full St AOFHF IU Data FIFO Half full Flag This input is used to ge
25. SN Name Description Minimum Maximum Treqchrdy CPUDACREQ to CHRDY OUT asserted 4 12 Tcwrerdy CPUDACWR to CHRDY OUT deasserted 4 2 11 C35 OUT CLK to CPUDACWR asserted 14 15 43 47 Tcwr CPUDACWR pulsewidth 2 3 2 3 Tccwrd OUT CLK to CPUDACWR deasserted 14 12 44 37 Tctwr OUT CLK to TMRDACWR asserted 11 34 Twr TMRDACWR pulsewidth 2 31 2 3 Tctwrd OUT_CLK to TMRDACWR deasserted 11 35 timing values are in nanoseconds Figure 3 16 Analog Output Contention Timing Case A The numbers in parentheses are for DACWR lt 0 1 gt The numbers in square brackets indicate the number of clock periods that occur at the minimum and maximum delays because those parameters are clock edge driven with possible additional gate delays The CPUDACREQ signal is recognized on the falling edge of the output clock If TMRDACWR is already asserted the bus cycle is delayed to the next write slot In this case the CPUDACREQ signal was asserted immediately after the falling edge of the output clock so the DAQ STC continued with its own write cycle Each write slot is separated by one clock period as shown in the timing diagram The two signals CPUDACWR and TMRDACWR can never occur at the same time and will be separated by at least one clock period National Instruments Corporation DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control The second case occurs when the CPUDACREQ signal is reco
26. lt 0 9 gt MOUT 20101 EDGE mox MOUT R RTSI TRIGGER O 6 4 POLARITY INT CLK SEL lt 0 4 gt EXT CLK 2STAGE EXT_TIMING Q INT_CLK R NOTE Does not show all possible selections DELAYSEXTSOLS DELAY EXT TIMING ACK DAQ STC Technical Reference Manual Figure 2 47 START1 and START2 Routing Logic 2 120 National Instruments Corporation Chapter 2 Analog Input Timing Control Figure 2 48 depicts the control for EXT GATE lt 0 9 gt OUT RTSI_TRIGGER lt 0 6 gt 7 POLARITY SEL lt 0 4 gt SCAN_IN_PROG NOTE Does not show all possible selections SC_CLK 4 _ EXT_CLK EXT_TIMING Figure 2 48 EXT_GATE Routing Logic Table 2 10 summarizes the selections available for each of the trigger signals through the PFI selector Table 2 10 PFI Selectors MUX 0 1 10 11 17 18 19 31 AI_START1_Source SW PFI lt 0 9 gt RTSI lt 0 6 gt GOUTO GND AI START2 Source SW PFI lt 0 9 gt RTSI lt 0 6 gt GND AI SI Source AI TBI PFI lt 0 9 gt RTSI lt 0 6 gt TB2 GND AI CONVERT Source 50 PFI lt 0 9 gt RTSI lt 0 6 gt GOUTO GND AI START Source SI TC PFI lt 0 9 gt RTSI lt 0 6 gt SW GOUTO GND AI_STOP_Source DIV_TC SW PFI lt 0 9 gt RTSI lt 0 6 gt SD TC AI STP GND AI External Gate PFI lt 0 9 gt RTSI lt 0 6 gt
27. p Software Counter 1 2 3 Figure 4 17 Buffered Static Pulse Train Generation National Instruments Corporation 4 13 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 4 4 3 Buffered Pulse Train Generation This function is similar to buffered static pulse train generation except that the software changes the pulse parameters after the generation of each pulse The G_GATE active edge causes the counter to generate a sequence of pulses with programmable delay from trigger pulse interval and pulsewidth The counter uses G SOURCE as a timebase to generate the pulses so you specify the programmable parameters in terms of periods of the G SOURCE input After each pulse an interrupt notifies the CPU so that the interrupt software can load the parameters for the next pulse into the counter registers Dual load registers provide additional software programming flexibility Figure 4 18 shows the generation of three pulses The first pulse has a delay from trigger of three and a pulsewidth of three The second pulse has a pulse interval of four and a pulsewidth of two The third pulse has a pulse interval of three and a pulsewidth of four G GATE G SOURCE L Counter Value 2 22102103210102103210 Counter TC G_OUT Figure 4 18
28. does not occur before the next BC the error detection circuit latches an error condition 3 8 5 3 BC TC Trigger Error The BC trigger error is used in retriggerable waveform staging In retriggerable waveform staging a START trigger that occurs after the first waveform staging sequence completes causes a new waveform staging sequence to begin The software must have time to program the next waveform staging sequence between the completion of the previous waveform staging sequence and the STARTI trigger A BC TC trigger error occurs when the parameters for the next waveform staging sequence are not written in the allotted time The error detection circuit is armed on the last BC TC of the waveform staging sequence If a software clear AO BC TC Interrupt does not occur before the next START trigger the error detection circuit latches an error condition 3 8 5 4 2 TC Error During waveform staging for secondary analog output software loads the parameters for the next update interval during the previous update interval The software must complete the programming operation before the end of the current update interval A UI2 TC error occurs when the parameters for the next update interval are not written in the allotted time The error detection circuit is armed on each UI2 TC If a software clear AO UD TC Interrupt does not occur before the next TC the error detection circuit latches an error conditi
29. Interrupt AO FIFO Interrupt Enable AO FIFO Mode AO FIFO Full St AO FIFO Half Full St and AO FIFO Empty St You must change the FIFO state by dealing with the FIFO AO UPDATE Interrupt Enable AO UPDATE ST AO UPDATE Interrupt All interrupts related to analog output are in interrupt group To select the interrupt line to be used e Interrupt Output Select 0 through 7 e Interrupt Enable 1 To determine quickly if any of the group B interrupts has occurred use Interrupt B St The START and STOP interrupts are provided for a mode which is not currently supported The documentation concerning these interrupts can be ignored To select interrupt output polarity use Interrupt Output Polarity This selection depends on the board hardware design Pass Through 1 Interrupt is also in interrupt group B National Instruments Corporation 3 87 DAQ STC Technical Reference Manual Chapter 3 3 6 6 Analog Output Timing Control Programming for a Secondary Analog Output Group Operation This section contains detailed programming information for bit level programming of the secondary AOTM for specialized applications The programs are presented in a bottom up fashion This section lists functions that can be used to configure the secondary AOTM for various operations The functions are then assembled into a complete program in section 3 6 6 9 Secondary Analog Output Program 3 6 6 1 O
30. X L CONVERT Tomx Tomx POR Tmx LOCALMUX CLK MUXFEF N L Tert Tmxdrt Tmxfrt LOCALMUX_FFRT Name Description Minimum Maximum Tcconv OUT CLK to CONVERT asserted 19 58 CONVERT to LOCALMUX CLK asserted 3 8 Tmx LOCALMUX_CLK pulsewidth 0 5 1 Tmnmx Minimum LOCALMUX CLK from 13 40 OUT CLK edge Tmxdrt Trailing edge of LOCALMUX_CLK to 0 LOCALMUX_FFRT asserted Tmxfrt LOCALMUX_FFRT pulsewidth 0 5 0 5 Tert OUT_CLK to LOCALMUX_FFRT 11 35 All timing values are in nanoseconds Figure 2 19 Maximum Rate Analog Input Timing The numbers in parentheses refer to the number of clock periods that will occur at the minimum and maximum delays because those parameters are clock edge driven with possible additional gate delays 2 7 6 External CONVERT Source The DAQ STC provides a very flexible architecture to control data acquisition from an external conversion source such as the MIO board or RTSI connectors The internal control circuits are driven by CONVERT SRC In the internal CONVERT mode CONVERT SRC is equal to OSC or RTSI_OSC In the external CONVERT mode CONVERT SRC is selected to be one of the PFI lt 0 9 gt or RTSI TRIGGER O 6 inputs The timing for CONVERT SRC in the external CONVERT mode is shown in Figure 2 20 DAQ STC Technical Reference Manual 2 92 National Instruments Corporation Chapter 2 Analog Input Timing Control
31. DA STARTI STARTI without Master Slave Sync The hardware generates DA 5 by passing the output of the STARTI selector through polarity selection edge detection and synchronization bypassing the master slave synchronization EXT GATE External Gate The external gate can be used to gate the UPDATE output It is selectable from either polarity of lt 0 9 gt or from RTSI lt 0 6 gt Related bitfields AO External Gate Enable AO External Gate Select AO External Gate Polarity AO External Gate St EXT GATE2 Secondary External Gate This signal can be used to gate the UPDATE2 output It is selectable from either polarity of PFI lt 0 9 gt or from RTSI_TRIGGER lt 0 6 gt Related bitfields AO UD External Gate Enable AO 012 External Gate Select AO UD External Gate Polarity AO UI2 Gate St FSCLK Fast Update Clock This signal is the output of the UPDATE selector after polarity selection Related bitfields AI UPDATE Source Select AI UPDATE Polarity Select IN TIMEBASE2 Slow Internal Timebase This timebase is derived from the OSC input and is usually configured to be 100 kHz Related bitfields Slow_Internal_Time_Divide_By_2 Slow_Internal_Timebase INT_SCLK_SEL Internal Update Indicator This signal indicates whether internal or external UPDATE mode is selected It is 1 for internal UPDATE mode and 0 for external UPDATE mode National Instruments Co
32. Disarm G1 Analog Trigger Reset Gl Load Save Trace Gl Arm G1 HW Save Registers Type Read only GW Save Value GW Save Value GW Save Value GW Save Value GW Save Value GW Save Value Save Value GW Save Value Save Value GW Save Value GW Save Value GW Save Value GW Save Value GW Save Value GW Save Value GW Save Value National Instruments Corporation Address 37 15 14 13 N _ NUR DO Address 33 15 14 13 N _ gt 1 G1 Input Select Register Type Write only Source Polarity Output Polarity OR Gate Gate Select Load Source Gate Select Gate Select Gate Select Gate Select Gate Select Source Select Source Select Source Select Source Select Source Select Write Acknowledges Read Acknowledges G1 Load A Registers Type Write only Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load National Instruments Corporation Appendix B G1 Load A Registers Address 32 15 14 13 N
33. GATE signal controls the counter operation The signal has two states ACTIVE and INACTIVE Table 4 7 shows the input routing for GATE signal Table 4 7 G GATE Selection Gi Gate Select Source 1 10 PFI lt 0 9 gt 11 17 lt 0 6 gt 18 Internal analog input signal START2 19 Internal analog output signal 12 TC 20 OUT signal from general purpose counter 0 21 Internal analog input signal STARTI Table 4 8 shows the input conditioning for GATE signal Table 4 8 G GATE Conditioning Gi Gate Polarity Polarity 0 GATE is ACTIVE when input is high 1 G GATE is ACTIVE when input is low 4 8 4 G UP DOWN Control You can route the up down control input from a dedicated up down input pin UP DOWN for each counter Alternately the GATE input can serve as direction control input The motivation for G_GATE signal serving as the direction control is that some board implementations may not connect the dedicated UP DOWN pins to the I O connector because of pin count limitations Note On the E Series boards the DOWN control inputs UP DOWNO0 and UP DOWNI pins are tied together with the DIO lt 6 7 gt DAQ STC Technical Reference Manual 4 64 National Instruments Corporation Chapter 4 General Purpose Counter Timer Table 4 9 UP DOWN Modes Gi Up Down Mode Description 0 Software selected down cou
34. National Instruments Corporation Chapter 4 General Purpose Counter Timer Use this function to program a counter for buffered event counting Program the Gi Source to select the signal on which you want to count events Program the Gate to select the signal that causes the counter contents to be saved Function 1 Buffered Event Counting Gi_Load_Source_Select 0 Gi_Load_A initial counter value Gi_Load 1 Y Gi Source Select 0 IN or 1 through 10 lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 IN TIMEBASE2 or 19 other TC Gi Source Polarity 0 count rising edges or 1 count falling edges Gi Gate Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI lt 0 6 gt or 18 AI START2 19 UD TC or 20 other TC or 21 AI STARTI or 31 logic low Gi OR Gate 0 Gi Output Polarity 0 active low or 1 active high Gate Select Load Source 0 Gi Gate Polarity 0 disable inversion or 1 enable inversion Gi Output Mode 1 one clock cycle output or 2 toggle on TC or 3 toggle on TC or gate Gi Reload Source Switching 1 If buffered cumulative event counting then Gi Loading On Gate 0 Else Buffered noncumulative event counting Gi_Loading_On_Gate 1 Gi_Loading_On_TC 0 Gi Gating Mode 2 Gi Gate On Both Edges 0 Gi Trigger Mode For Edge Gate 3 Gi Stop Mode 0 Gi Counting
35. configuration FIFO advance signal which pulses after an integral number of CONVERTs advances the configuration FIFO to the next input channel The LOCALMUX FFRT configuration FIFO retransmit signal which pulses when the configuration FIFO empties refills the configuration FIFO The EXTMUX CLK external multiplexer clock signal which pulses on every CONVERT advances the channel multiplexer The SHIFTIN signals SHIFTIN and SHIFTIN which pulse after the ADC has completed a conversion move the data into the analog input data FIFO The AI data FIFO request signal generates a DMA request based on the analog input National Instruments Corporation 2 5 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control FIFO flags AIFEF AI data FIFO empty flag AIFHF AI data FIFO half full flag and AIFFF AI data FIFO full flag Refer to section 2 5 Pin Locator Interface for a complete description of these signals The configuration FIFO may also supply the GHOST signal which is updated on every CONVERT When the GHOST input is active the SHIFTIN pulse is suppressed following the conversion so that the ADC data is not shifted into the AI data FIFO This feature allows the DAQ STC to support multirate sampling where channels are sampled at different input rates As shown in Figure 2 2 the START pulse may come from the SI counter internal START source or the PFI selector ex
36. eee tegat pei 3 121 3 8 3 8 UD 5 rere reote 3 121 3 8 4 Interrupt Control det dee RE 3 122 3 8 5 Eirtor Detection 5 o oen ee det EOS 3 122 3 8 5 1 Overrun Error ea edicti 3 122 3 8 5 2 TG Errors iaai oos ERO 3 123 3 8 5 3 BC TC Trigger 3 123 3 8 5 4 UI2 TC hee re reote 3 123 3 8 6 Output Control eo tope ee fece eee te 3 123 3 8 7 Nominal Signal 1 3 124 Chapter 4 General Purpose Counter Timer LX MEMO cua LEE 4 1 4 1 1 Programming the sese 4 1 42 BeatUfes sues serene eere tette bp E 4 1 43 Sumplitied Model asics es ceosoe eei ns 4 2 4 4 Counter Timer Functions ceecee ri eriei enne enne nnne nnn 4 3 4 4 1 Event Counting niei PP ERR eror ea 4 3 4 4 1 1 Simple Event 4 4 4 4 1 2 Simple Gated Event 4 4 4 4 1 3 Buffered Noncumulative Event Counting 4 4 4 4 1 4 Buffered Cumulative Event Counting 4 5 4 4 1 5 Relative Position 04042421 4 6 4 4 2 eee eot ertet erre ens 4 6 4 4 2 1 Single Period Measurement 4 6 4 4 2 2 Single Pulsewidth Measurement 4 7 4 4 2 3 Buffered Period 4 7 4 4 2 4 Buffered Semiperiod
37. gt DOO NW HRN Address 15 DODO _ NW 4 tA G1 Mode Register Type Write only Reload Source Switching Loading On Gate Gate Polarity Loading On TC Counting Once Counting Once Output Mode Output Mode Load Source Select Stop Mode Stop Mode Trigger Mode For Edge Gate Trigger Mode For Edge Gate Gate On Both Edges Gating Mode Gating Mode G1 Save Registers Type Read only Save Value Save Value Save Value Save Value Save Value Save Value Save Value Save Value Save Value Save Value Save Value Save Value Save Value Save Value Save Value Save Value National Instruments Corporation G Status Register Address 4 Type Read only 15 14 13 N _ NUR O G1_Gate_Error_St GO Gate Error St TC Error St GO TC Error St No Load Between Gates St GO No Load Between Gates St Armed St GO Armed St Stale Data St GO Stale Data St Next Load Source St GO Next Load Source St Counting St GO Counting St Save St GO Save St Interrupt Ack Register Address 2 Type Write only 15 14 13 N _ gt OO
38. 2 6 3 12 Convert Signal Use this function to select the CONVERT signal You can specify the channel rate by choosing an internally generated periodic event Function AI CONVERT Signal Begin critical section AI_Configuration_Start 1 If internal CONVERT mode is selected then National Instruments Corporation Chapter 2 Analog Input Timing Control AI SC Gate Enable 0 AI Start Stop Gate Enable 0 If 512 counter will use internal time then If you want both SI 512 to use AI TIMEBASEI you must program SI to select IN TIMEBASEI and program 512 to select the SI source If SI2 will use AI IN TIMEBASEI1 then If internal START mode AND SI will use AI IN TIMEBASEI1 then AI SI2 Source Select 0 same signal selected as SI source Else AI SD Source Select 1 AI IN TIMEBASEL Else If you want SI2 to use IN TIMEBASE2 program 512 counter to use the same timebase as the SI counter and then program the SI counter to use IN TIMEBASE2 This will work well in one of the following two cases you are not using SI at all or you are using SI and it uses IN TIMEBASE2 AI SI2 Source Select 0 same signal selected as SI source AI SI Source Select 19 IN TIMEBASE2 AI SI Source Polarity 0 Else You want to use SI2 and you want to use one of the external timebases Program the SI2 counter to use the same timebase as the SI
39. AO UC Load A AO Load A AO UC Load A AO UC Load A AO UC Load B Registers Type Write only AO UC Load B UC Load AO UC Load AO UC Load AO UC Load UC Load B AO UC Load AO UC Load B UC Load AO UC Load UC Load UC Load UC Load B AO UC Load B AO Load AO UC Load National Instruments Corporation Appendix B Register Information AO UC Save Registers AO UC Save Registers Address 20 Type Read only Address 21 Type Read only 15 Reserved 15 AO UC Save Value 14 Reserved 14 AO UC Save Value 13 Reserved 13 AO UC Save Value 12 Reserved 12 AO UC Save Value 11 Reserved 11 AO UC Save Value 10 Reserved 10 AO UC Save Value 9 Reserved 9 AO UC Save Value 8 Reserved 8 AO UC Save Value 7 AO UC Save Value 7 AO UC Save Value 6 AO UC Save Value 6 AO Save Value 5 AO UC Save Value 5 AO UC Save Value 4 AO UC Save Value 4 AO UC Save Value 3 AO UC Save Value 3 AO UC Save Value 2 AO UC Save Value 2 AO UC Save Value 1 AO Save Value 1 AO UC Save Value 0 AO Save Value 0 AO Save Value AO UD Load A Register AO UD Load B Register Address 53 Type Write only Address 55 Type Write only 15 AO 012 Load 15 AO UD Load B 14 AO UD Load A 14 AO UD Load B 13 AO UD Load A 13 AO UD Load 12 AO UD Load A 12 AO UD Load B 11 AO UD Load A 11 AO UD Load B
40. Begin critical section AI_Configuration_Start 1 If continuous acquisition then AI Continuous 1 Infinite number of scans Else AI Continuous 0 If pretriggered acquisition then AI Pre Trigger 1 National Instruments Corporation 2 33 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control AI SC Load B minimal number of pretrigger scans to acquire 1 AI SC Initial Load Source 1 AI SC Reload Mode 1 alternate load register on TC Else AI Pre Trigger 0 AI SC Initial Load Source 0 AI SC Reload Mode z 0 same load register AI SC Load A number of posttrigger scans to acquire 1 AI SC Load 1 If staged acquisition then AI SC Load B sc ticks 0 1 AI SC Reload Mode 0 X AI SC Switch Load On 1 X AI Configuration End 1 End critical section 2 6 3 10 Start of Scan Use this function to select the scan start event You can specify the scan rate by choosing an internally generated periodic signal to be the START signal In a staged acquisition the number of clocks between START in each stage is contained in an array named 51 ticks If the acquisition is staged this function loads the initial value of si ticks into the SI load register to initialize the first stage The additional values in the array are written as needed by the interrupt routine see AI Staged ISR Variable si last load register int
41. If Pass Thru 0 Interrupt St is 1 then The interrupt was caused by signal entering DAQ STC through the IRQ INO pin Service the external interrupt 0 You cannot explicitly acknowledge a pass through interrupt You must perform an action external to the DAQ STC in order to clear this interrupt condition Normally board hardware should be designed so that you can cause this action To enable this interrupt set AI_Pass_Thru_0_Interrupt_Enable 1 Else if SoftCopy GO TC Interrupt Enable is 1 then If GO_TC_St 1 then The interrupt was caused by general purpose counter 0 TC Service the general purpose counter 0 TC interrupt clear this interrupt set GO_TC_Interrupt_Ack 1 To enable this interrupt set GO TC Interrupt Enable 1 Else if GO Gate Interrupt St is 1 then The interrupt was caused by appropriate event that occurred on gate of general purpose counter 0 Service the general purpose counter 0 gate interrupt To clear this interrupt set GO_Gate_Interrupt_Ack 1 To enable this interrupt set GO_Gate_Interrupt_Enable 1 Else if Soft_Copy AI_SC_TC_Interrupt_Enable is 1 then If AI SC TC 5118 1 then The interrupt was caused by AI SC_TC signal Service the AI SC_TC interrupt To clear this interrupt set AI_SC_TC_Interrupt_Ack 1 To enable this interrupt set AI SC TC Interrupt Enable 1 Else if Soft_Copy AI_START1_In
42. Interrupt_Output_On_3_Pins 0 disabled or 1 enabled 8 4 1 2 Interrupt Output Select and Enable Use the following function to select the OUT pin that will indicate an interrupt condition in the interrupt group and to enable interrupts for the group Function MSC_IRQ_Configure switch interrupt group case A Interrupt_A_Output_Select 0 through 7 lt 0 7 gt Interrupt_A_Enable 0 disabled or 1 enabled break case B Interrupt_B_Output_Select 0 through 7 lt 0 7 gt National Instruments Corporation 8 3 DAQ STC Technical Reference Manual Chapter 8 Interrupt Control Interrupt Enable 0 disabled or 1 enabled break Note Two groups can share the same IRQ_OUT pin You should set Interrupt_i_Output_Enable to 1 after selecting the interrupt polarity and appropriate IRQ_OUT pin number The described mechanism allows you to change interrupt levels during an operation However you should not change interrupt levels once an operation has begun because your ISR may not function properly 8 4 1 3 Pass Through Interrupt Two conditions external to the DAQ STC if properly connected can cause the chip circuitry to indicate an interrupt condition The input pins IRQ_IN lt 0 1 gt be used for this purpose Your board hardware must be designed with this in mind for software to be able to take advantage of this DAQ STC feature Use the following function to s
43. J NWT XL NLP Xo Xo XU NC X Xa XS Xo N Figure 3 14 DAQ STC Driven Analog Output Timing Table 3 4 DAQ STC Driven Analog Output Timing Name Description Minimum Maximum Tcp UPDATE SRC to UPDATE asserted 18 56 Tsup UPDATE pulsewidth source clocks 1 1 Toup UPDATE pulsewidth output clocks 1 3 1 5 3 5 OUT CLK to UPDATE deasserted 12 28 Tupwr UPDATE to TMRDACWR asserted 0 5 1 5 Tctwr OUT CLK to TMRDACWR asserted 11 34 Tctreq OUT CLK to TMRDACREQ asserted 10 31 Treqneg OUT CLK to TMRDACREQ deasserted 10 32 Twr TMRDACWR pulsewidth 2 3 2 3 National Instruments Corporation DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control Table 3 4 DAQ STC Driven Analog Output Timing Continued Name Description Minimum Maximum Taddr TMRDACWR to AO ADDR change 3 10 Tefset AOFEF setup to latching edge 15 ES Tefhold AOFFF hold after latching edge 0 5 clk AII timing values are in nanoseconds 3 7 3 DAQ STC Technical Reference Manual 3 88 The numbers in parentheses refer to the number of clock periods that occur at the minimum and maximum delays because those parameters are clock edge driven with possible additional gate delays The UPDATE signal can be programmed to be one or three output clock periods or one source clock period see AO UPDATE P
44. MISB 1 MISB 2 START1 UPDATE UC TC L I deri 1 Figure 3 12 Continuous Mode 3 4 5 3 Waveform Staging Waveform staging refers to the software action required to implement a sequence of more than two MISBs In a programming sequence that occurs prior to the STARTI trigger software loads the parameters for the first two MISBs Software also configures the counters to switch load registers after each MISB has completed providing for the switch from one MISB to the next While the second MISB is in progress software loads the parameters for the third MISB into the unused load registers Switching between load registers occurs at the end of each MISB that 15 at TC This arrangement allows the software a maximum latency of up to the duration of the MISB in progress to finish loading the parameters for the next MISB into the alternate load register set DAQ STC Technical Reference Manual 3 14 National Instruments Corporation Chapter 3 Analog Output Timing Control The DAQ STC provides error detection for the case in which the next parameters are not written in the allotted time The error detection circuit is armed on each TC If a software clear does not occur before the next TC the error detection circuit latches an error condition 3 4 5 4 Mute Buffers In some cases it is necessary to provide a programmable delay between MISB outputs The mute buffer provides a w
45. Mode Register address 27 This bit determines whether the hardware disarms the counter when the counter stops due to a hardware condition 0 No hardware disarm 1 Disarm at the TC that stops counting 2 Disarm at the that stops counting 3 Disarm at the TC or G_GATE that stops counting whichever comes first National Instruments Corporation 4 37 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer Gi Counting St 0 bit 2 type Read Status Register address 4 i 1 bit 3 type Read Status Register address 4 If general purpose counter i is armed this bit indicates whether the counter is counting 0 No 1 Yes If the counter is not armed this bit should be ignored Related bitfields Armed St Gi_Disarm i 0 bit 4 type Strobe in GO_Command_Register address 6 i 1 bit 4 type Strobe Gl Command Register address 7 Setting this bit to 1 disarms general purpose counter i This bit is cleared automatically Gi Disarm Copy 0 bit 15 type Strobe Gl Command Register address 7 i i bit 15 type Strobe GO Command Register address 6 Setting this bit to 1 disarms general purpose counter i This bit is cleared automatically Gi Gate Error Confirm 1 0 5 type Strobe Interrupt Ack Register address 2 i l bit 1 type Strobe Interrupt Register address 3 Setting this bit to 1 clears Gate Error St This
46. bit 10 type Strobe Interrupt Ack Register address 2 Setting this bit to 1 clears AI START2 St and acknowledges the START interrupt request in either interrupt bank if the START2 interrupt is enabled This bit is cleared automatically Related bitfields AI START2 St AI START2 Interrupt Enable START2 Interrupt Enable bit 2 type Write in Interrupt Enable Register address 73 This bit enables the START2 interrupt 0 Disabled Enabled The START interrupt is generated on valid START triggers received by the DAQ STC A valid START trigger is one that is received while the SC counter is in the WAIT2 state START2 Polarity bit 14 type Write in AI Trigger Select Register address 63 This bit determines the polarity of START trigger 0 Active high or rising edge 1 Active low or falling edge You should set this bit to 0 if AI START2 Select is set to 0 Related bitfields AI START2 Select START2 Pulse bit 1 type Strobe AI Command 2 Register address 4 Setting this bit to sends a START trigger to the SC counter if START2 software strobe is selected AI START2 Select is set to 0 This bit is cleared automatically Related bitfields AI START2 Select National Instruments Corporation 2 79 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control START2 Second Enable bit 2 type Write in Second A Enable Register address 74
47. signal pulses only when the DIV counter reaches state 0 Figure 2 5 shows the operation of these signals during a scan where four external channels are multiplexed onto each of two input channels DAQ STC Technical Reference Manual 2 6 National Instruments Corporation Chapter 2 Analog Input Timing Control START STOP CONVERT EXTMUX_CLK 4H LOCALMUX CLK DIV Counter 0 2 1 0 3 2 1 0 Figure 2 5 External Multiplexer Control 2 4 1 4 CONVERT Timing As discussed in section 2 3 Simplified Model sequences of CONVERT pulses are organized into scans which begin on START and terminate on STOP The DAQ STC can generate the timing for the individual CONVERT pulses using the SI2 counter internal CONVERT or the timing for CONVERT can come from an external source external CONVERT With an external CONVERT the SI2 counter is unused Internal CONVERT In the internal CONVERT mode the hardware generates the CONVERT pulses on SI2 TC SI2 counter TC The START trigger causes the SI2 counter to begin counting and the STOP trigger causes the SI2 counter to stop counting Refer to section 2 4 2 Scan Level Timing and Control for more information on the START trigger The STOP trigger which asserts after the appropriate number of conversions usually comes from the configuration FIFO
48. 0 BC Initial Load Source bit 2 type Write in AO Mode 2 Register address 39 If the BC counter is disarmed this bit selects the initial BC load register 0 Load register A 1 Load register B If the BC counter is armed writing to this bit has no effect Related bitfields Arm 0 BC Load bit 5 type Strobe AO Command 1 Register address 9 If the BC counter is disarmed this bit loads the BC counter with the contents of the selected BC load register If the BC counter is armed writing to this bit has no effect This bit is cleared automatically Related bitfields AO Arm AO BC Initial Load Source 0 BC Load bits lt 0 7 gt type Write in AO BC Load A Registers address 44 bits lt 0 15 gt type Write in AO BC Load A Registers address 45 This bitfield is load register A for the BC counter If load register A is the selected BC load register the BC counter loads the value contained in this bitfield on BC Load and on BC TC The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related Bitfields BC Next Load Source St AO BC Load 0 BC Load B bits lt 0 7 gt type Write in AO BC Load B Registers address 46 bits lt 0 15 gt type Write in AO BC Load B Registers address 47 This bitfield is load register B for the BC counter If load register B is the selected BC load register the BC counter loads the value contained in t
49. 1 If single channel then AO_Multiple_Channels 0 AO_Number_Of_Channels output channel number Else AO_Multiple_Channels 1 AO_Number_Of_Channels number of output channels 1 AO_Configuration_End 1 End critical section DAQ STC Technical Reference Manual 3 28 National Instruments Corporation Chapter 3 Analog Output Timing Control 3 6 1 8 LDAC Source and UPDATE Mode Use this function to set the source and update mode for the LDAC lt 0 1 gt signals Function LDAC Source And Update Mode Begin critical section AO_Configuration_Start 1 AO LDACO Source Select 0 LDACO will output UPDATE or 1 LDACO will output UPDATE2 AO DACO Update Mode z 0 immediate update mode or 1 timed update mode AO LDACI Source Select 0 LDACI will output UPDATE 1 LDACI will output UPDATE2 AO DACI Update Mode z 0 immediate update mode or 1 timed update mode AO Configuration End 1 End critical section 3 6 1 9 Stop On Error Use this function to set the error conditions upon which the AOTM will stop Function AO Errors To Stop On Begin critical section AO_Configuration_Start 1 AO_Stop_On_BC_TC_Error 0 continue on BC_TC error or 1 stop on BC_TC error AO_Stop_On_BC_TC_Trigger_Error 0 continue on BC_TC trigger error or 1 stop on BC_TC trigger error AO_Stop_On_Overrun_Error 0 continue on overrun error or 1 stop on overrun err
50. AO Number Of Channels AO Number Of Channels AO Number Of Channels AO Number Of Channels AO UPDATE2 Output Select AO UPDATE2 Output Select AO External Gate Polarity AO UPDATE2 Output Toggle AO UPDATE Output Select AO UPDATE Output Select DAQ STC Technical Reference Manual B 20 AO Mode 3 Register Address 70 Type Write only 15 Reserved 14 Reserved 13 AO UD Switch Load Next TC 12 AO UC Switch Load Every BC TC 11 AO Trigger Length 10 Reserved 9 Reserved 8 Reserved 7 Reserved 6 Reserved 5 AO Stop On Overrun Error 4 AO Stop On BC TC Trigger Error 3 AO Stop On BC TC Error 2 AO Not An UPDATE 1 AO Software Gate 0 Reserved AO Personal Register Address 78 Type Write only 9 gt tA Reserved AO Number Of DAC Packages Fast CPU TMRDACWR Pulse Width AO FIFO Flags Polarity AO FIFO Enable AO AOFREQ Polarity AO DMA PIO Control AO UPDATE Original Pulse UPDATE Pulse Timebase AO UPDATE Pulse Width BC Source Select AO Interval Buffer Mode UPDATE2 Original Pulse AO UPDATE2 Pulse Timebase UPDATE2 Pulse Width National Instruments Corporation Address 66 15 14 13 N _ NUR Address 6 15 14 13 N _ OO AO START Select Regist
51. AO STARTI Polarity 0 National Instruments Corporation 3 23 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control AO STARTI 1 AO 5 Sync 1 Else AO STARTI Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI lt 0 6 gt AO 5 Polarity 0 active high or 1 active low 5 Edge 0 edge detection disabled or 1 edge detection enabled AO 5 Sync 0 synchronization disabled or 1 synchronization enabled AO Delayed 5 0 use the STARTI trigger immediately or 1 delay the STARTI trigger by synchronizing it to the BC source X AO Trigger Length 0 PFIG AO STARTI will output STARTI or 1 PFIG AO START will output a pulse stretched version of DA STIED AO Configuration End 1 End critical section 3 6 1 5 Number of Buffers Use this function to select the number of updates to be performed corresponding to the number of points in the buffer and the number of buffer iterations If you are using the local buffer mode with mute buffers this function will set the part of the delay parameters that correspond to the number of points in the mute buffer and the number of iterations of that buffer If you are using waveform staging this function enables and disables muting for the first two buffers The variables ao load register and ao tick count to use introduced in t
52. BC clock signal binary coded decimal BC disarm signal BC hold signal BC load signal BC load source signal 6 3 DAQ STC Technical Reference Manual Glossary BC TC BC SRC C CHADDR CHRDY IN CHRDY OUT CONVERT CPU CPUDACREQ CPUDACWR CS CTRGATE CTRL lt 0 7 gt CTROUT CTRSRC D buffer repetition counter TC signal BC source signal 4 bit channel address counter board level channel ready signal channel ready output signal ADC conversion strobe signal central processing unit CPU request for access to the DAC CPU write to the DAC chip select signal general purpose counter gate signal control signal channels 0 through 7 counter output signal general purpose counter source signal D lt 0 15 gt bidirectional tri state data bus signals D A digital to analog DAC D A converter DACUPDN DAC update signal lt 0 1 gt DAC write strobe 0 through 1 DAQ data acquisition DAQ STC Technical Reference Manual G 4 National Instruments Corporation DAQ STC STIED STARTI DC DIO DIO lt 0 7 gt DIO0 SDOUT DIO4 SDIN DIV DIV_CE DIV_CLK DIV_LOAD DIV_TC DMA E EOC ETS EXTMUX_CLK EXTSTROBE EXTSTROBE SDCLK EXT_CLK EXT_DIVTC EXT_GATE National Instruments Corporation Glossary data acquisition timing controller output version of START1 start 1 signal without master slave sync direct current digital I O digital lines 0 through 7 digital I O 0 serial d
53. National Instruments Corporation 2 59 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control LOCALMUX is 1 5 2 AI OUT TIMEBASE periods 1 LOCALMUX FFRT is 0 5 AI OUT TIMEBASE periods and LOCALMUX is 0 5 1 AI OUT TIMEBASE periods LOCALMUX CLK must also be cleared by an SOC AI Output Divide By 2 bit 7 type Write in Clock and FOUT Register address 56 This bit determines the frequency of the internal timebase AI OUT TIMEBASE 0 Sameas IN TIMEBASE 1 TIMEBASE divided by two AI Overflow St bit 10 type Read in AI Status 1 Register address 2 This bit indicates the detection of an ADC overflow error 0 No error 1 Error The overflow error indicates that an attempt was made to write the ADC result to a full AI data FIFO that is the reading from the FIFO is too slow to match the writing to the FIFO If the overflow error occurs at least one point of data has been lost This bitis cleared by setting AI Error Interrupt Ack to 1 AI Overrun Mode bit 7 type Write in AI Personal Register address 77 This bit selects the period during which new CONVERT pulses are not allowed 0 From SOC to EOC 1 From SCC to the trailing edge of SHIFTIN If a CONVERT pulse occurs within the selected interval an overrun error is detected AI Overrun St bit is set to 1 Related bitfields Overrun St AI Overrun St bit 11 type Read in AI Status 1 Register address 2 This bit in
54. PFI Selection Table 4 19 summarizes the selections available for each of the trigger signals through the PFI selector Table 4 19 PFI Selectors MUX 0 1 10 11 17 18 19 20 21 31 G0 Source G TBI PFI lt 0 9 gt RTSI lt 0 6 gt TB2 G1 TC GND G0 Gate PFI lt 0 9 gt RTSI lt 0 6 gt ST2 UD TC GOUTI AI STI GND Source G TBI PFI 0 9 RTSI lt 0 6 gt TB2 GO TC GND Gate PFI 0 9 51 lt 0 6 gt ST2 UD TC GOUTO AI STI GND Key AI STI The internal analog input signal STARTI AI ST2 The internal analog input signal STARTI 50 The signal from general purpose counter 0 G1 TC The signal from general purpose counter 1 GOUTO The OUT signal from general purpose counter 0 GOUTI The OUT signal from general purpose counter 1 G TBI The internal signal IN TIMEBASEI TB2 The internal signal IN TIMEBASE2 UD TC The internal analog output signal 12 DAQ STC Technical Reference Manual 4 70 National Instruments Corporation Chapter 4 General Purpose Counter Timer a Note When the analog trigger circuit is enabled the analog trigger signal takes over the PFIO0 slot in the PFI selectors 4 8 10 Error Detection The GPCT counters can operate in buffered mode where the software must intervene at regular intervals to sustain the operation Buffered mode requires real time operation response from the software For
55. The numbers in parentheses are for DACWR lt 0 1 gt The numbers in square brackets indicate the number of clock periods that occur at the minimum and maximum delays because those parameters are clock edge driven with possible additional gate delays The CPUDACREQ signal is latched on the falling edge and recognized on the rising edge of the source clock Therefore the delay between the assertion of the CPUDACREQ signal and the assertion of the CPUDACWR signal is between 0 5 and 1 5 clock periods The signal CPUDACWR can be programmed to two or three output clock periods which is an exact number of periods see AO TMRDACWR Pulse Width No synchronization is required for this signal 3 7 4 DAQ STC and CPU Driven Analog Output Timing The possibility exists that the CPU and the DAQ STC will both attempt to write to the DACs during overlapping time periods The CPU is given priority over the DAQ STC but it cannot interrupt a DAQ STC write cycle in progress If the DAQ STC is writing to the DACs the CPU bus cycle will be extended to the next write slot This case is detailed in Figure 3 16 DAQ STC Technical Reference Manual 3 90 National Instruments Corporation Chapter 3 Analog Output Timing Control JF ny J D XL Xy X CPUDACREQ Treqchrdy N Tewrcrdy CHRDY OUT N Tecwrd Tecwr CPUDACWR Tetwrd a Tetwr awe TMRDACWR
56. gt SC LOAD SRC WE EE AIFIFOREQ START2 MUX l AIERROR STOP SC Control 9C LOAD 8 SC TC Logic SC CLK SC Counter e Interrupt 4 STARTI Sc TC SC HOLD SC GATE Control amp START2 SC 5 in gt SC Save START 4 M STOP MODE DIV Load A STARTI gt DIV_CE DIV LOAD DIV TC pO REE STOP DIV gt DIV Counter gt DIV Control Logic STARTI ScTo gt START2 SC_SRC Pi SC SRC SI Load A SI Load B ALIN TIMEBASE1 START STARTI b STOP IN 5 2 gt i 5 Routing SI SRC START SI LOAD SRC 1 lt 0 9 gt gt Logic stop 3 SCE MUX SCLK ontrol RTSI_TRIGGER lt 0 6 gt gt dom SI TC gt Logic oe Sl Counter SI TC 50 70 SI HOLD SI2 TC SIL SRC SI Save DIV TC 1 CONVERT 4 MODE SI2 Load A SI2 Load B SC TC LOCALMUX 4 Y 4 Y Output START SI2 LOAD SRC EXTMUX lt Control 52 CE MUX SCAN IN PROG START 512 LOAD aa STOP gt 52 SI2 CLK SI2 Counter SOC Control I2 TC EOC 812 TO 3 Logic SC TC gt gt Figure 2 45 AITM Block Diagram DAQ STC Technical Reference Manual 2 112 National Instruments Corporation Chapter 2 Analog Input Timing Control 2 8 1 Internal Signals and Operation Table 2 9 describes the internal signals shown in Figure 2 44 Table
57. 0 Gi Gate Polarity 0 disable inversion or 1 enable inversion Gi Output Mode 1 one clock cycle output or 2 toggle on TC or 3 toggle on TC or gate Gi Reload Source Switching 1 Gi Loading Gate 0 Gi Loading On 1 If single pulse generation then Gi Gating Mode 0 Else Single triggered pulse generation or retriggerable single pulse generation Gi_Gating_Mode 2 Gi_Gate_On_Both_Edges 0 Gi_Trigger_Mode_For_Edge_Gate 2 Gi_Stop_Mode 2 If retriggerable single pulse generation then National Instruments Corporation 4 29 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer Else Gi Counting Once 0 Single pulse generation or single triggered pulse generation Gi Counting Once 1 Gi_Up_Down 0 Gi_Bank_Switch_Enable 0 Gi_Bank_Switch_Mode 0 Gi_TC_Interrupt_Enable 0 Gi Gate Interrupt Enable 0 Use this function to program a counter for continuous pulse train generation Program the Gi Source to select the signal that you want to use as a reference clock Program the Gate to select the signal that you want to use as a hardware trigger Function Continuous Pulse Train Generation Gi_Load_Source_Select 0 Gi_Load_A delay from hardware trigger to first edge of pulse 1 L Gi_Load 1 L Gi_Load_A pulse interval 1 Gi_Load_B pulsewidth 1 Gi_Load_Source_Select 1 G
58. 10 2 timebases derived from IN TIMEBASE table 10 2 to 10 3 features 10 1 frequency output 10 3 overview 10 1 pin interface 10 9 to 10 10 programming information 10 10 to 10 15 analog trigger 10 12 bitfield descriptions 10 12 to 10 15 clock distribution 10 10 to 10 11 FOUT 10 12 test mode 10 6 to 10 9 checking input pin connectivity 10 7 input pin pairs table 10 8 to 10 9 internal gate tree structure figure 10 7 testing RESET pin 10 8 Motorola bus See bus interface module MSC Clock Configure function 10 11 MSC FOUT Configure function 10 12 5 Generic Control function 7 12 MSC Generic Status function 7 13 MSC IRQ Configure function 8 3 to 8 4 Personality function 8 3 MSC Pass Through Interrupt function 8 4 to 8 5 MSC Pass Through Second Irq function 8 5 MSC Write Strobe function 9 4 IO Pin Configure function 5 5 to 5 6 MSC RTSI Pin Configure function 6 3 multiplexer control external 2 7 to 2 9 mute buffers 3 15 DAQ STC Technical Reference Manual MUXFEF signal configuration FIFO 2 8 configuration memory timing 2 89 to 2 91 description table 2 22 nominal signal pulsewidths analog input timing control module table 2 133 analog output timing control module table 3 1124 number of scans analog input programming 2 32 to 2 33 0 OSC signal table 10 10 OUT CLK signal analog input timing control module basic analog input timing 2 86 to 2 87 descript
59. 19 TIMEBASE2 31 Logic low Related bitfields SI Source Polarity SI2 Source Select SI Special Trigger Delay bit 12 type Write in AI Mode 3 Register address 87 Setting this bitto 1 in the external START mode causes the SI counter to block START pulses for a fixed time period after the STARTI trigger This feature allows you to have an extra timing parameter in the scan timing when you use an external START Refer to section 2 4 2 Scan Level Timing and Control for more information on the SI Special Trigger Delay Notice that the time period may be expressed as the number of START pulses blocked Do not set this bit to 1 in the internal START mode SI Switch Load On SC TC bit 9 type Strobe AI Command 2 Register address 4 Setting this bit to 1 causes the SI counter to switch load registers at the next 5 TC This action is internally synchronized to the falling edge of the internal signal SI CLK You can use this bit for scan rate change during an acquisition and for staged analog input This bit is cleared automatically SI Switch Load On STOP bit 8 type Strobe AI Command 2 Register address 4 Setting this bitto 1 causes the SI counter to switch load registers upon receiving a STOP trigger This action is internally synchronized to the falling edge of the internal signal SI CLK This bit is cleared automatically AI SI Switch Load On TC bit 7 type Strobe AI Command
60. 2 114 DIV counter operation 2 129 DIV TC signal counter outputs figure 2 106 description table 2 114 pin interface description table 2 20 documentation about this manual xxiii conventions used in manual xxv National Instruments documentation xxvi organization of manual xxiii xxiv related documentation xxvi xxvii E edge detection trigger selection and conditioning analog input timing control module 2 122 analog output timing control module 3 116 electronic support services E 1 to E 2 e mail support E 2 Enable Gi Out function 4 35 end of scan analog input programming 2 37 to 2 38 ECC signal ADC control 2 7 basic analog input timing 2 86 description table 2 21 simplified analog input model 2 5 error detection analog input timing control module overflow error 2 132 overrun error 2 132 5 TC error 2 132 analog output timing control module 3 122 to 3 123 BC TC error 3 123 BC trigger error 3 123 National Instruments Corporation 1 21 Index overrun error 3 122 UI2_TC error 3 123 ETS pulse generation for description 4 15 programming 4 33 to 4 34 event counting 4 3 to 4 6 buffered cumulative event counting 4 5 buffered noncumulative event counting 4 4 to 4 5 programming buffered event counting 4 20 to 4 22 relative position sensing 4 23 to 4 24 simple event counting 4 19 to 4 20 relative position sensing 4 6 simple event counting 4 4 simple gated event counting
61. 3 4 4 2 External UPDATE i tet hei 3 12 3 4 5 Buffer Timing and Control for Primary Analog Output 3 12 3 4 5 1 Single Buffer 3 13 3 4 5 2 Continuous 3 13 3 4 5 3 Waveform 3 14 3 4 5 4 Mute Buffers ite eph Re erret 3 15 3 4 5 5 Master Slave Trigger sese 3 15 3 4 6 Secondary Analog 3 16 3 5 Pin nterface s os ue RERO UR URP REPERI tinea 3 16 3 6 X Programming 3 20 3 6 1 Programming for a Primary Analog Output Operation 3 20 3 6 1 1 OVerVIeW 1 ouest piace inopes 3 21 3 6 1 2 ReSCttin gs codo eee ebrei es 3 21 3 6 1 3 Board Power up Initialization sss 3 22 3 6 1 4 Trigger Signals cce ctis 3 23 3 6 1 5 Number of 3 24 3 6 1 6 Update Selections erines oris eines enii s 3 26 3 6 1 7 Channel erect reet 3 28 3 6 1 8 LDAC Source and UPDATE Mode 3 29 3 6 1 9 Stop Error uehementer 3 29 3 6 1 10 ptr ete 3 29 3 6 1 11 Enable Interrupts eee 3 30 3 6 1 12 3 30 3 6 1 13 Starting the Waveform 3 31 3 6 1 14 Primary Analog Output Program sess 3 31 3 6 2 Waveform Staging for Primary Analog 3 32 3 6 3 Changing Update Rate during an Output Operation for
62. 3 8 3 8 Ul2 Control UD runs unless disarmed stopped or gated The following are the UI2 counter logic equations LOAD UI2 TC AO 012 LOAD UI2 CE UI2 Arm STOP EXT GATE2 DA_SFGATE2 AO UI2 External Gate Enable National Instruments Corporation 3 121 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 3 8 4 Interrupt Control The analog output contains the hardware necessary for generating software interrupts based on several conditions The interrupt programming is accomplished using the Interrupt B Enable Register and the Second Irq B Enable Register Interrupts remain active until cleared by software Interrupts can occur under the following conditions overrun error STARTI BC TC UC TC FIFO condition UPDATE and UD TC Table 3 8 summarizes the analog output interrupts along with the condition that causes the interrupt Table 3 8 Analog Output Interrupts Interrupt Condition Error Interrupt Interrupt generated on the detection of an overrun error condition STARTI Interrupt Interrupts are generated on valid START triggers received by the DAQ STC A valid START trigger is one that is received while the BC counter is armed and in the WAITI state BC TC Interrupt Interrupts are generated on the trailing edge of BC TC UC TC Interrupt Interrupts are generated on the leading edge of UC TC FIFO Interrupt Interrupt generated on the FIFO condition indic
63. 4 4 Event Counting ISR function 4 22 EXT DIVTC signal table 2 114 EXT signal analog input timing control description table 2 114 trigger routing logic figure 2 121 analog output timing control description table 3 111 routing logic figure 3 115 EXT GATE2 signal description table 3 111 routing logic figure 3 115 external CONVERT mode CONVERT timing 2 10 to 2 11 free run gating mode timing external CONVERT figure 2 110 START and SCAN IN PROG trigger output 2 102 START trigger output 2 102 START and START triggers in synchronous mode 2 97 to 2 99 external CONVERT source 2 92 to 2 93 external gating See gating external multiplexer control 2 7 to 2 9 DAQ STC Technical Reference Manual Index external START mode scan level timing and control 2 12 to 2 13 external trigger timing 3 102 to 3 104 asynchronous edge figure 3 102 asynchronous level figure 3 102 synchronous edge external UPDATE mode figure 3 103 internal UPDATE mode figure 3 103 synchronous level external UPDATE mode figure 3 103 internal UPDATE mode figure 3 103 timing table 3 104 external triggers 2 03 to 2 97 analog input timing table 2 96 to 2 97 asynchronous edge figure 2 94 asynchronous level figure 2 94 synchronous edge external CONVERT mode figure 2 96 internal CONVERT mode figure 2 95 synchronous level external CONVERT mode figure 2 96 internal CONVERT mode figur
64. 6 type Strobe AO Command 1 Register address 9 This bit arms the BC counter The counter remains armed and the bit remains set until it 1s disarmed either by hardware or by setting AO Disarm to 1 Related bitfields AO BC Armed St AO Disarm 0 BC Armed St bit 0 type Read in AO Status 2 Register address 6 This bit indicates whether the BC counter is armed 0 Disarmed 1 Armed Related bitfields AO BC Arm 0 BC Gate Enable bit 11 type Write in AO Command 2 Register address 5 This bit enables the BC GATE 0 Disabled 1 Enabled Enabling the GATE allows external UPDATE pulses to pass only when the BC counter is enabled to count You should set this bit to 0 in the internal UPDATE mode UPDATE Source Select 15 set to 0 and to 1 otherwise Related bitfields AO UPDATE Source Select DAQ STC Technical Reference Manual 3 46 National Instruments Corporation Chapter 3 Analog Output Timing Control 0 BC Gate St bit 6 type Read in Joint Status 1 Register address 27 When GATE is enabled see AO Gate Enable this bit indicates the state of the BC GATE 0 Inactive External UPDATES are blocked 1 Active External UPDATEs are allowed to pass The BC GATE is active only when the BC counter is enabled to count When the BC GATE is disabled this bit is undefined You must disable the GATE in the internal UPDATE mode Related bitfields AO Gate Enable
65. 9 gt PFIO AI STARTI PFII AI START2 PFI2 CONV PFI3 G_SRC1 PFI4 G GATEI PFIS UPDATE PFI6 AO_START1 PFI7 AI START PFI8 G_SRCO PFI9 G GATEO POLARITY R RD WR RESET RGOUTO RMA RTM RTSI lt 0 3 gt RTSI OSC RTSI lt 0 6 gt National Instruments Corporation Glossary programmable function input signals 0 through 9 PFIO STARTI trigger from analog input PFI1 START2 trigger from analog input PFI2 ADC conversion strobe from analog input PFI3 general purpose counter 1 source PFI4 general purpose counter 1 gate PFI5 primary update from analog output PFI6 START 1 trigger from analog output PFI7 START trigger from analog input PFI8 general purpose counter 0 source PFI9 general purpose counter 0 gate active or true state of a signal i e active high or active low in Intel mode a read bus signal in Motorola mode a read write input signal active low signal that resets the DAQ STC during initialization RTSI source selection from the I O pins Return Manual Authorization RTSI trigger module Real Time System Integration board interface signal channels 0 through 3 RTSI oscillator source signal RTSI trigger signal channels 0 through 6 G 9 DAQ STC Technical Reference Manual Glossary S SC SCAN IN PROG SCKG SCLK SCLKG SC CE SC CLK SC GATE SC HOLD SC LOAD SC LOAD SRC SC SRC SC STARTI SC TC SCXI SEC IRQ OUT BANKO SEC IRQ OUT BANKI S
66. A second option for generating the STOP trigger an internal STOP is to configure the DIV counter to count the number of conversions load the DIV counter with the number of conversions per scan then use the DIV counter TC as the STOP signal However you cannot use an internal STOP and an external multiplexer at the same time because they both use the DIV counter The SI2 counter has dual load registers that allow two timing parameters at the CONVERT timing level The first parameter A gives the delay from START to the first CONVERT The second parameter B gives the delay between CONVERT pulses The SI2 reload mode setting allows the SI2 counter to alternate load registers on every STOP thus providing the dual timing feature National Instruments Corporation 2 9 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Figure 2 6 shows two scans with four internally timed CONVERT pulses each to indicate the available timing parameters The SCAN IN PROG output asserts on START and deasserts at the completion of the scan START 1 STOP SCAN IN PROG CONVERT 512 TC Timing Parameter A B Figure 2 6 Internal CONVERT Timing External CONVERT In the external CONVERT mode the externally generated CONVERT pulses enter the DAQ STC through one of the PFI lt 0 9 gt RTSI lt 0 6
67. CTR_U D is synchronized to CTRSRC before being used by the counter In order for CTR_U D to be recognized it must stabilize at least one setup time before the relevant edge of CTRSRC In the internal timing mode CTR_U D is synchronized to the inactive edge of CTRSRC In the external timing mode CTR_U D is synchronized to the active edge of CTRSRC before it enters a delay gate Figures 4 28 and 4 29 and the accompanying table indicate the setup time requirements for CTR_U D relative to the relevant edge of CTRSRC National Instruments Corporation 4 59 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer CTRSRC Counter 2 1 2 3 4 3 2 1 0 Counter TC CTR U D Name Description Minimum Maximum Tgtclk U D to CTRSRC setup 8 All timing values are in nanoseconds Figure 4 28 CTR_U D Setup Timing Internal Timing Mode Tgtclk Tgtclk H H CTRSRC Counter 2 1 2 3 4 3 2 1 0 Counter TC CTR U D Name Description Minimum Maximum Tgtclk U D to CTRSRC setup 8 All timing values are in nanoseconds Figure 4 29 CTR_U D Setup Timing External Timing Mode DAQ STC Technical Reference Manual 4 60 National Instruments Corporation Chapter 4 General Purpose Counter Time
68. Chapter 4 4 4 2 General Purpose Counter Timer 4 4 1 5 Relative Position Sensing In relative position sensing the counter tracks the relative position of an object Two types of events are possible movement in the positive direction and movement in the negative direction The positive movement event is an active edge transition on the G SOURCE input while G UP DOWN is high The negative movement event is an active edge transition on the G SOURCE input while G UP DOWN is low The software initially loads the counter with a value corresponding to the initial position of the object Positive movement events cause the counter to increment and negative movement events cause the counter to decrement Upon reaching TC the counter rolls over The user can obtain the relative position of the object at any time by asynchronously reading the counter value Figure 4 6 shows an example of relative position sensing Software Arm G UP DOWN G SOURCE ee 1 2 3 2 3 4 3 4 Counter Value 0 Figure 4 6 Relative Position Sensing Time Measurement In the time measurement functions the counter uses SOURCE as a timebase to measure the time interval between events on the G_GATE signal The following actions are available in time measurement e Rising edges on SOURCE can increment or decrement the counter during the measurement interval e Counting can begi
69. Counter Value 4 4 4 3 2102 10443 2102104 4 Counter TC G OUT Figure 4 14 Retriggerable Single Pulse Generation 4 4 3 4 Buffered Retriggerable Single Pulse Generation This function is similar to retriggerable single pulse generation except that the software updates the pulse parameters after the generation of each pulse Following the software arm every active G_GATE edge causes the counter to generate a single pulse with programmable delay and programmable pulsewidth You should specify the programmable parameters in terms of periods of the G SOURCE input After each pulse an interrupt notifies the CPU so that the interrupt software can load the counter registers with the parameters for the next pulse Dual load registers provide additional software programming flexibility Figure 4 15 shows the generation of two buffered pulses The first pulse has a pulse delay of five and a pulsewidth of three The second pulse has a pulse delay of six and a pulsewidth of four National Instruments Corporation 4 11 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer ame 0 1 2102 105 5432103210 2 G SOURCE Counter Value 4 4 4 Counter TC i G OUT Figure 4 15 Buffered Retriggerable Single Pulse Gener
70. DAQ STC A valid START trigger is one that is received while the SC counter is in the WAIT2 state The actual interrupt signal appears on the active edge of SC CLK SC TC interrupt Interrupts are generated on every SC falling edge unless the pretrigger acquisition mode is selected In the pretrigger acquisition mode the first TC falling edge does not generate an interrupt but subsequent SC TC falling edges do FIFO interrupt Interrupt generated on the FIFO condition indicated by AI FIFO Mode National Instruments Corporation 2 131 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 2 8 5 Error Detection The DAQ STC detects three analog input errors overrun overflow and SC TC error 2 8 5 1 Overrun Error An overrun error occurs when the ADC interval is not long enough to complete a conversion In hardware this is detected when a CONVERT pulse occurs before the last conversion is completed Two modes are available for the overrun error detection interval as selected by AI Overrun Mode In mode 0 the error detection interval starts on SOC and ends on In mode 1 the error detection interval starts on SOC and ends on the trailing edge of SHIFTIN 2 8 5 2 Overflow Error An overflow error occurs when an attempt is made to write the ADC result to a full AI data FIFO In hardware this is detected when a SHIFTIN pulse occurs while the AI FIFO full flag is ac
71. Description EXTSTROBE SDCLK O9TU External Strobe Serial Data Clock This active low output signal can serve as the clock signal with either the parallel or serial data or serve as a general digital output It is intended to be used in two modes software controlled mode or hardware controlled serial clock mode In the software controlled mode this bit is toggled under software control In the hardware controlled serial clock mode this pin serves as the clock signal associated with the serial data I O pins Parallel data output on DIO lines is used with the AMUX 64T Serial data I O is used with SCXI Related bitfields DIO HW Serial Enable DIO HW Serial Timebase DIO Software Serial Control STATUS lt 0 3 gt ID Status lt 0 3 gt These pins serve as a board status register Related bitfields Generic Status 7 6 Programming Information This section presents programming information that is specific to digital I O For general information about programming the DAQ STC see section 2 6 Programming Information 1 6 1 Windowed Mode Register Access Example The DAQ STC register access method is illustrated by the following C code example The following code toggles the DIO lines on the DAQ STC The AT MIO 1 E Series boards address mapping of the DAQ STC is used to illustrate the addressing and access methods for the DAQ STC define define define
72. If AO_BC_TC_St is 1 then The interrupt was caused by AO BC_TC signal Service the AO BC_TC interrupt To clear this interrupt set AO BC TC Interrupt Ack 1 To enable this interrupt set AO BC TC Interrupt Enable Else if Soft Copy AO UC TC Interrupt Enable is 1 then If AO UC TC Stis 1 then The interrupt was caused by AO UC signal Service the AO BU TC interrupt clear this interrupt set AO UC TC Interrupt 1 DAQ STC Technical Reference Manual 6 10 National Instruments Corporation Chapter 8 Interrupt Control To enable this interrupt set AO UC Enable 1 Else if Soft_Copy AO_START1_Interrupt_Enable is 1 then If AO STARTI Stis 1 then The interrupt was caused by AO START signal Service the AO START interrupt clear this interrupt set AO_START1_Interrupt_Ack 1 To enable this interrupt set AO_START1_Interrupt_Enable 1 Else if Soft_Copy AO_UPDATE_Interrupt_Enable is 1 then If AO UPDATE St is 1 then The interrupt was caused by AO UPDATE signal Service the AO UPDATE interrupt clear this interrupt set AO_UPDATE_Interrupt_Ack 1 To enable this interrupt set AO_UPDATE_Interrupt_Enable 1 Else if Soft_Copy AO_Error_Interrupt_Enable is 1 then If AO_Overrun_St is 1 then The interrupt was caused by one or both errors Service the AO error interrupt To clear this
73. Notice that it is legal to set both Loading On Gate and Loading On TC to 1 simultaneously Gi Next Load Source St 1 0 0 4 type Read Status Register address 4 i l bit 5 type Read Status Register address 4 This bit indicates the next load source of general purpose counter i 0 Load register 1 Load register B Gj No Load Between Gates St i 0 bit 10 type Read in Status Register address 4 i l bit 11 type Read in Status Register address 4 This bit indicates that a counter reload did not occur for general purpose counter i between two relevant edges DAQ STC Technical Reference Manual 4 44 National Instruments Corporation Chapter 4 General Purpose Counter Timer Gi OR Gate i 0 10 13 type Write in GO_Input_Select_Register address 36 bit 13 type Write Input Select Register address 37 This bit determines whether the selected gate signal is OR ed with the output of the other general purpose counter 0 No 1 Yes You can use setting 1 for hardware triggered buffered pulse train generation The selected gate signal is only OR ed while the counter is not counting When the counter is counting only the output of the other counter applies Gi Output Mode i 0 bits 8 9 Write in GO Mode Register address 26 bits lt 8 9 gt type Write in G1 Mode Register address 27 This bit selects the mode for OUT signal
74. On the following source edge all of the ASICs simultaneously begin the programmed acquisition sequence Master slave triggering can be used with any of the three acquisition modes pretrigger posttrigger or continuous acquisition mode Gating The DAQ STC also supports gating an additional external control layer Both an external source coming through the PFI 0 9 or RTSI lt 0 6 gt interface and software can supply the optional control signal Gating provides a mechanism to pause the data acquisition operation When the START signal is internally generated by the SI counter gating is available in two modes free run and halt When the START signal is externally generated only free run gating is available In all modes the conversion signal CONVERT is gated on a scan basis that is entire scans are gated on or off DAQ STC Technical Reference Manual 2 16 National Instruments Corporation Chapter 2 Analog Input Timing Control 2 4 4 1 Free Run Gating Mode In the free run gating mode the scan timing continues without interruption while the outputs are gated off For the internal START case the SI counter continues to count regardless of the gating signal If the external gate is asynchronous to the SI source internal START mode or to the external START the delay between active gate level and first conversion of a scan varies and can be as long as one scan interval Figure 2 13 shows two scans and the loca
75. RTSI trigger module table 6 1 to 6 2 summary of buffer types table C 7 to C 8 posttrigger acquisition mode 2 14 power up initialization See board power up initialization pretrigger acquisition mode 2 14 to 2 15 primary analog output operation programming 3 20 to 3 32 arming 3 30 to 3 31 board power up initialization 3 22 to 3 23 channel select 3 28 enable interrupts 3 30 FIFO mode 3 29 to 3 30 LDAC source and UPDATE mode 3 29 number of buffers 3 24 to 3 26 overview 3 21 resetting 3 21 to 3 22 sequence of functions 3 31 to 3 32 starting the waveform 3 30 to 3 31 stop on error 3 29 trigger signals 3 23 to 3 24 update selection 3 26 to 3 28 primary group analog output modes 3 5 to 3 7 See also analog output functions CPU driven analog output 3 6 to 3 7 DAQ STC and CPU conflict 3 7 DAQ STC driven analog output 3 6 programmable function inputs See PFI module programming See also bitfield descriptions analog input timing control module 2 24 to 2 83 arming 2 41 bitfield descriptions 2 48 to 2 83 board environment setup 2 29 to 2 30 board power up initialization 2 27 to 2 28 DAQ STC Technical Reference Manual I 30 changing scan rate during acquisition 2 43 to 2 44 convert signal 2 38 to 2 40 enable interrupts 2 40 to 2 41 end of scan 2 37 to 2 38 FIFO request 2 30 hardware gate programming 2 30 to 2 31 initialize configuration memory output 2 28 to 2 29 int
76. Read in GO HW Save Registers address 8 bits lt 0 15 gt type Read in GO HW Save Registers address 9 i l bits lt 0 7 gt Read in HW Save Registers address 10 bits lt 0 15 gt type Read in HW Save Registers address 11 This bitfield latches the contents of general purpose counter i on GATE edge appropriate for the selected gating mode Referto Gi Gating Mode for a discussion of gating modes The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related bitfields Gating Mode Gi Little Big Endian 0 bit 9 type Write in GO Command Register address 6 i l bit 9 type Write in Command Register address 7 This bit selects the load or save register segment to be used for automatic interrupt acknowledgment 0 Low register 1 High register Related bitfields Gi Read Acknowledges Write Acknowledges Gi Load 0 bit 2 type Strobe GO Command Register address 6 i l bit 2 type Strobe Command Register address 7 Setting this bitto 1 loads the contents of the selected load register into general purpose counter i This bit is cleared automatically Related bitfields Load Source Select DAQ STC Technical Reference Manual 4 42 National Instruments Corporation Chapter 4 General Purpose Counter Timer Gi Load A i 0 bits 0 7 type Write in GO Load A Registers address 28 bits lt 0
77. Reserved Reserved Reserved Reserved AI START Output Select AI SCAN IN PROG Output Select AI SCAN IN PROG Output Select AI EXTMUX CLK Output Select AI EXTMUX CLK Output Select AI LOCALMUX Output Select AI LOCALMUX Output Select AI SC TC Output Select AI SC TC Output Select AI CONVERT Output Select AI CONVERT Output Select AI SC Load A Registers Type Write only Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A National Instruments Corporation 15 14 13 N _ DO 15 14 13 N OO AI SC Load A Registers Address 19 Type Write only AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load A AI SC Load B Registers Address 21 Type Write only AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B National Instruments Corporation 15 14 13 N
78. Reserved 0 Window Data 0 Reserved National Instruments Corporation B 37 DAQ STC Technical Reference Manual Appendix B Register Information Write Strobe 1 Register Write Strobe 2 Register Address 83 Type Write only Address 84 Type Write only 15 Reserved 15 Reserved 14 Reserved 14 Reserved 13 Reserved 13 Reserved 12 Reserved 12 Reserved 11 Reserved 11 Reserved 10 Reserved 10 Reserved 9 Reserved 9 Reserved 8 Reserved 8 Reserved 7 Reserved 7 Reserved 6 Reserved 6 Reserved 5 Reserved 5 Reserved 4 Reserved 4 Reserved 3 Reserved 3 Reserved 2 Reserved 2 Reserved 1 Reserved 1 Reserved 0 Write Strobe 1 0 Write Strobe 2 Write Strobe 3 Register Address 85 Type Write only 15 Reserved 14 Reserved 13 Reserved Reserved N Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Write_Strobe_3 _ gt 1 oo DAQ STC Technical Reference Manual B 38 National Instruments Corporation Pin List This appendix contains lists of the DAQ STC pins Table C 1 in alphabetical order and Table C 2 in numerical order For more detailed information about a specific pin refer to the Pin Interface section of the chapter that discusses that pin For a list of pins discussed in each chapter refer to Figure 1 3 DAQ STC B
79. Save Value AO Save Value AO Save Value AO Save Value National Instruments Corporation Address 19 15 14 13 N _ 10 Address 5 15 14 13 N _ _ AO BC Save Registers Type Read only AO Save Value AO Save Value AO BC Save Value AO Save Value AO Save Value AO BC Save Value AO Save Value AO Save Value AO BC Save Value AO Save Value AO Save Value AO Save Value AO Save Value AO Save Value AO Save Value AO Save Value AO Command 2 Register Type Write only AO End On BC TC AO End On UC TC AO Start Stop Gate Enable AO UC Save Trace AO BC Gate Enable AO BC Save Trace AO UI Switch Load On BC TC AO UI Switch Load On Stop AO UI Switch Load On TC AO UC Switch Load On BC TC AO UC Switch Load On TC AO BC Switch Load On TC AO Mute B AO Mute A UPDATE2 Pulse STARTI Pulse National Instruments Corporation Address 9 15 14 13 N NUR DOO CO Address 38 15 14 13 N _ OO Appendix B Register Information AO Command 1 Register Type Write only AO Analog Trigger Reset AO START Pulse AO Disarm AO UD Arm Disarm AO UD Load AO UI Arm AO Load A
80. Software Arm G SOURCE 4 L Counter Value 0 1 2 3 4 5 Figure 4 2 Simple Event Counting 4 4 1 2 Simple Gated Event Counting Simple gated event counting is similar to simple event counting except that the counting process is gated that is halted and resumed GATE When GATE is active the counter counts pulses that occur on the G SOURCE signal after the software arm When GATE is inactive the counter retains the current count value Figure 4 3 shows an example of simple gated event counting where the gate action allows the counter to count only five of the pulses on SOURCE Software Arm G GATE G SOURCE FLELELELTLTLELE 1 2 3 4 5 Counter Value 0 Figure 4 3 Simple Gated Event Counting 4 4 1 3 Buffered Noncumulative Event Counting Buffered noncumulative event counting is similar to simple event counting except that there are multiple counting intervals The G_GATE signal indicates the boundary between consecutive counting intervals The counter counts the number of pulses that occur on the DAQ STC Technical Reference Manual 4 4 National Instruments Corporation Chapter 4 General Purpose Counter Timer SOURCE signal after the software arm Each active edge of GATE signal latches the count value for the current counting interval into the hardware HW save register and reloads the counter with the initial value to begin
81. analog input programming 2 31 secondary analog output operation 3 40 software controlled serial digital I O 7 12 specifications A 1 to A 4 absolute maximum ratings A 2 analog input 1 analog output A 1 DC characteristics A 3 to A 4 digital I O A 1 frequency output A 2 general purpose counter timers A 1 pin capacitance A 2 recommended operating conditions A 2 to A 3 ST_TC error 2 132 staged acquisition analog input programming 2 44 to 2 45 description 2 16 start of scans analog input programming 2 34 to 2 37 DAQ STC Technical Reference Manual Index START signal CONVERT timing external CONVERT mode 2 10 to 2 11 internal CONVERT mode 2 9 to 2 10 description table 2 118 external trigger timing 2 94 to 2 07 free run gating mode 2 17 gating 2 16 halt gating mode 2 17 to 2 18 scan level timing and control functions 2 11 to 2 13 external START mode 2 12 to 2 13 internal START mode 2 11 to 2 12 simplified analog input model 2 4 single wire mode 2 18 trigger output 2 100 to 2 102 external CONVERT mode 2 102 internal CONVERT mode 2 101 trigger routing logic figure 2 120 START signal analog input timing control module continuous acquisition mode 2 15 description table 2 118 external START mode 2 12 to 2 13 external trigger timing 2 94 to 2 96 internal START mode 2 11 interval scanning mode 2 106 to 2 108 master slave trigger 2 16 posttrigger acquisition mode 2 14 simplifi
82. it must stabilize at least one setup time before the relevant edge of CTRSRC In the internal timing mode CTRGATE is synchronized to the inactive edge of CTRSRC In the external timing mode CTRGATE is synchronized to the active edge of CTRSRC before it enters a delay gate Figures 4 26 and 4 27 and the accompanying table indicate the setup time requirements for CTRGATE relative to the relevant edge of CTRSRC Tgtclk Tgtclk CTRSRC Counter 2 1 1 1 1 0 N N 1 N 2 Counter TC CTRGATE Name Description Minimum Maximum Tgtclk CTRGATE to CTRSRC setup 8 AII timing values are in nanoseconds Figure 4 26 CTRGATE Setup Timing Internal Timing Mode DAQ STC Technical Reference Manual 4 58 National Instruments Corporation Chapter 4 General Purpose Counter Timer Tgtclk Tgtclk CTRSRC Counter 2 1 1 1 1 0 N N 1 N 2 Counter TC CTRGATE Name Description Minimum Maximum Tgtclk CTRGATE to CTRSRC setup 8 All timing values are in nanoseconds Figure 4 27 CTRGATE Setup Timing External Timing Mode 4 7 7 CTR_U D Setup In many GPCT functions for example relative position sensing the CTR_U D signal causes the counter to select between up counting and down counting In these functions
83. lt 0 9 gt or 11 through 17 RTSI TRIGGER O 6 or 18 AI START2 19 UI2 TC or 20 other TC or 21 AI STARTI or 31 logic low Gi OR Gate 0 Gi Output Polarity 0 active low or 1 active high Gate Select Load Source 0 Gi Gate Polarity 0 disable inversion or 1 enable inversion Gi Output Mode 1 one clock cycle output or 2 toggle on TC or 3 toggle on TC or gate Gi Reload Source Switching 1 Gi Loading Gate 0 Gi Loading On 1 Gi Gating Mode 2 Gi Gate On Both Edges 0 Gi Trigger Mode For Edge Gate 2 Gi Stop Mode 2 Gi Counting Once 0 Gi Up Down 0 Gi Bank Switch Enable 0 National Instruments Corporation 4 33 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer Gi Bank Switch Mode 0 Gi TC Interrupt Enable 0 Gi Gate Interrupt Enable 0 4 6 1 13 Reading the Counter Contents In several functions for example simple event counting and relative position sensing you may want to read the counter contents while the counter is armed and counting The save register allows you to access the counter contents without disturbing the counting process Use this function to read the counter contents while the counter is armed and counting The function reads the save register value several times in case a read occurs while the save register is being updated Function Gi Watch Declare variables sav
84. sample intervals 5 Switch load register on every STOP Use this setting to synchronously change the sample interval at each STOP 6 Alternate first period on every SC TC Use this setting to make the interval between the STARTI trigger and the first scan different from the scan interval 7 Switch load register on every SC TC Use this setting to synchronously change the scan interval at each SC TC SI Save Value bits lt 0 7 gt type Read in AI SI Save Registers address 64 bits lt 0 15 gt type Read in AI SI Save Registers address 65 This bitfield reflects the contents of the SI counter Reading from this bitfield while the SI counter is counting may result in an erroneous value The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address SI Source Polarity bit 4 type Write in AI Mode 1 Register address 12 This bit selects the active edge of the SI source the signal that is selected by AI SI Source Select 0 Rising edge Falling edge Set this bit to 0 if an internal timebase is used Related bitfields SI Source Select National Instruments Corporation 2 69 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control SI Source Select bits lt 6 10 gt type Write AI Mode 1 Register address 12 This bitfield selects the SI source 0 AL IN TIMEBASEI 1 10 lt 0 9 gt 11 17 RTSI lt 0 6 gt
85. 0 2 External Gate Enable bit 15 type Write in AO Trigger Select Register address 67 This bit enables the secondary external gate 0 Disabled 1 Enabled 0 UI2 External Gate Polarity bit 14 type Write in AO START Select Register address 66 This bit selects the polarity of the secondary external gate 0 Active high high enables counting 1 Active low low enables counting 0 UI2 External Gate Select bits lt 7 11 gt type Write in AO START Select Register address 66 This bit selects the secondary external gate if the secondary external gate is enabled 1 10 lt 0 9 gt 11 17 RTSI lt 0 6 gt 31 Logic low Related bitfields AO UI2 External Gate Enable 0 2 Gate St bit 13 type Read in Joint Status 1 Register address 27 This bit reflects the state of the secondary external gate The secondary external gate is set to 0 Pause the UI2 counter 1 Enable the UD counter 0 2 Initial Load Source bit 9 type Write in AO Mode 2 Register address 39 If the UI2 counter is disarmed this bit selects the initial UI2 load register 0 Load register A 1 Load register B If the UI2 counter is armed writing to this bit has no effect Related bitfields UI2 Arm DAQ STC Technical Reference Manual 3 76 National Instruments Corporation Chapter 3 Analog Output Timing Control AO UI2 Load bit 11 type Strobe AO Command 1 Register address 9 If the
86. 0 Reserved 1 TC mode The counter TC signal appears on OUT 2 Toggle output on TC mode OUT changes state on the trailing edge of counter TC 3 Toggle output on TC or gate mode OUT changes state on the trailing edge of counter TC and on the active gate edge This mode can be used for sequential scanning Related bitfields Output Polarity Gi Output Polarity i 0 01 14 type Write in GO Input Select Register address 36 bit 14 type Write in G1 Input Select Register address 37 This bit selects the polarity of the OUT pulse in the TC mode or the initial OUT level the toggle output mode 0 Active high pulse or initial low level 1 Active low pulse or initial high level Related bitfields Output Mode Gi Output St i 0 bit 0 type Read in Joint_Status_2_Register address 29 bit 1 type Read in Joint Status 2 Register address 29 This bit indicates the current OUT state after the polarity selection 0 Low 1 High Related bitfields Output Polarity National Instruments Corporation 4 45 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer Gi Permanent Stale Data St i 0 0 1 14 type Read in Joint Status 2 Register address 29 i l bit 15 type Read in Joint Status 2 Register address 29 This bit indicates the detection of a permanent stale data error 0 No error 1 Error A permanent stale data error occurs
87. 1 Register address 8 If the SI2 counter is disarmed this bit loads the SI2 counter with the contents of the selected SD load register A or B If the SI2 counter is armed writing to this bit has no effect This bit is cleared automatically SI2 Load A bits lt 0 15 gt type Write in AI SI2 Load A Register address 23 This bitfield is load register for the SI2 counter If load register is the selected 512 load register SI2 counter loads the value contained in this bitfield on SI2 Load and 50 TC Related Bitfields 512 Next Load Source 51 AI SI2 Load National Instruments Corporation 2 71 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 512 Load bits lt 0 15 gt type Write in AI SI2 Load B Register address 25 This bitfield is load register B for the SI2 counter If load register B is the selected SI2 load register 512 counter loads the value contained in this bitfield on SI2 Load and SI2 TC Related Bitfields AI 512 Next Load Source St 512 Load SI2 Next Load Source St bit 12 type Read in AI Status 2 Register address 5 This bit indicates the next load source of the SI2 counter 0 Load register A 1 Load register B AI SI2 Q St bits lt 8 9 gt type Read in Joint Status 1 Register address 27 This bitfield reflects the state of the SI2 control circuit 0 WAIT 1 1 CNT 2 WAIT 2 See section 2
88. 10 AO UD Load A 10 AO UD2 Load 9 AO 2 Load 9 AO UD Load 8 AO 02 Load 8 AO UD Load B 7 AO UD Load A 7 AO UD Load 6 AO UD Load A 6 AO UD Load 5 AO UD Load A 5 AO UD Load 4 AO UD Load 4 AO UD Load B 3 AO 2 Load 3 AO UD Load 2 AO UD Load 2 AO UD Load B 1 UD Load 1 AO UD Load B 0 AO UD Load 0 AO UD Load National Instruments Corporation DAQ STC Technical Reference Manual Appendix B Register Information AO UD Save Register AO UI Load A Registers Address 23 Type Read only Address 40 Type Write only 15 AO UD Save Value 15 Reserved 14 AO UD Save Value 14 Reserved 13 AO UD Save Value 13 Reserved 12 AO UD Save Value 12 Reserved 11 AO UD Save Value 11 Reserved 10 AO UD Value 10 Reserved 9 AO UD Save Value 9 Reserved 8 AO UD Save Value 8 Reserved 7 AO UD Save Value 7 AO UI Load 6 AO UD Save Value 6 AO UI Load A 5 AO UD Save Value 5 AO UI Load A 4 AO UD Save Value 4 AO UI Load A 3 AO UD Save Value 3 AO UI Load A 2 AO UD Save Value 2 AO UI Load 1 AO 012 Save Value 1 AO UI Load AO UD Save Value 0 AO UI Load AO UI Load A Registers AO UI Load B Registers Address 40 Type Write only Address 42 Type Write only 15 AO UI Load A 15 Reserved 14 AO UI Load A 14 Reserved
89. 14 AI STOP Polarity 13 AI STOP Sync AI STOP Edge AI STOP Select AI STOP Select AI STOP Select AI STOP Select AI STOP Select AI START Sync AI START Edge AI START Select AI START Select AI START Select AI START Select AI START Select N _ gt OO OK DAQ STC Technical Reference Manual B 16 Address 25 ee NUR DO NW HRN Address 2 9 tac NW gt AI SD Save Register Type Read only AI SD Save Value AI SD Save Value AI SD Save Value AI SD Save Value AI SD Save Value AI SD Save Value AI SD Save Value AI SD Save Value AI SD Save Value AI SD Save Value AI SD Save Value AI SD Save Value AI SD Save Value AI SD Save Value AI SD Save Value AI SD Save Value AI Status 1 Register Type Read only Interrupt A St AI FIFO Full St FIFO Half Full St AI FIFO Empty St AI Overrun St AI Overflow St AI SC TC Hrror 5 AI START2 St AI STARTI St AI SC TC St AI START St AI STOP St GO TC St GO Gate Interrupt St AI FIFO Request St Pass Thru 0 Interrupt St National Instruments Corporation AI Status 2 Register Address 5 Type Read only 15 14 13 N _ NUR DO Reserved_2000_St AI_DIV_Armed_St AI DIV Q St AI SI2 Next Load Source St AI SI2 Armed St AI SI Q St AI SI Q St
90. 2 1 Pin Interface cte pega enisi d 9 1 9 3 Programming Information 9 3 9 3 1 Programming the Write Strobes esses 9 4 9 3 2 Bitfield Descriptions nonet ette be tre 9 4 94 Timing Diagrams ouo ERE i rm Re 9 5 Chapter 10 Miscellaneous Functions 101 OVerVIewi eie ete ere eer TERRE Et Rees 10 1 10 2 eo e RB o re D HR Pee CREE E e PURA 10 1 10 3 Clock Distribution eene rt Pret prebere reme 10 2 104 Frequency s eem E here e PR iet 10 3 10 5 Analog Trigger eem eee nee SE 10 3 10 6 Test nee te ree ee ER Uie e ure dique tes 10 6 1037 Toterface s d ene ae AOR REN 10 9 10 8 Programming Information 10 10 10 8 1 Programming Clock Distribution eene 10 10 10 8 2 Programmimg FOUT 10 12 10 8 3 Programming Analog 0000002000 10 12 10 8 4 Bitfield Descriptions 022220001 00 0001000 00002 10 12 Appendix A Specifications Appendix B Register Information DAQ STC Technical Reference Manual xiv National Instruments Corporation Contents Appendix C Pin List Appendix D DAQ STC Revision History Appendix E Customer Communication Glossary Index Figures Figure 1 1 Analog Input 1 2 Figure 1 2
91. 2 9 Internal Signals Signal Description AD START Output Version of START The hardware generates this signal by passing the output of the START selector through polarity selection edge detection synchronization and additional circuitry that guarantees that AD START pulses only when the START is recognized as valid by the internal control circuits AD STARTI Output Version of START 1 This signal can come from two sources If AI Delayed STARTI 0 the hardware generates AD STARTI by passing the output of the STARTI selector through polarity selection and edge detection but not synchronization If AI Delayed 1 AD STARTI is the same as STARTI Related bitfields Delayed STARTI ADR STARTI Internal STARTI Signal without Master Slave Synchronization This signal is generated by the hardware by passing the output of the AI STARTI selector through polarity selection edge detection and synchronization synchronized to FSC_SRC bypassing master slave synchronization ADR START2 START2 without Master Slave Synchronization This signal is generated by the hardware by passing the output of the AI START2 selector through polarity selection edge detection and synchronization bypassing master slave synchronization AD VSTART2 Output Version of START2 This signal can come from two sources If AI Delayed 2 0 then the hardware generates AD VSTA
92. 2 91 description table 2 22 maximum rate analog input 2 91 to 2 92 nominal pulsewidths table 2 133 simplified analog input model 2 5 National Instruments Corporation 27 Index LOCALMUX FFRT signal configuration FIFO 2 8 configuration memory timing 2 89 to 2 91 description table 2 22 maximum rate analog input 2 91 to 2 92 nominal pulsewidths table 2 133 simplified analog input model 2 5 low level timing and control functions 2 6 to 2 11 ADC control 2 7 configuration FIFO and external multiplexer control 2 7 to 2 9 CONVERT timing 2 9 to 2 11 Data FIFO control 2 7 macro level analog input timing 2 106 to 2 108 manual See documentation master slave operation analog input programming 2 45 to 2 46 analog output programming master slave operation considerations 3 35 secondary analog output 3 45 master slave trigger analog input timing control module 2 16 analog output timing control module 3 15 to 3 16 maximum rate analog input 2 91 to 2 92 maximum update rate timing 3 101 to 3 102 Misc Counter TCs Output Enable bit 10 14 miscellaneous functions 10 1 to 10 15 analog trigger 10 3 to 10 6 high hysteresis mode figure 10 5 high window mode figure 10 4 low hysteresis mode figure 10 6 low window mode figure 10 4 middle window mode figure 10 5 DAQ STC Technical Reference Manual Index clock distribution 10 2 to 10 3 master slave distribution across RTSI bus figure
93. 2 Features 6 1 DAQ STC Technical Reference Manual Xii National Instruments Corporation Contents 6 3 Pin Interface osse doeet eer b oe inte it eH 6 1 6 4 Programming Information 02221000 10 000000 6 2 6 4 1 Programming Interface 6 2 6 4 2 Bitfield Descriptions uie 6 3 6 5 Detailed Description eie eerte esto eo itte 6 6 Chapter 7 Digital 1 0 71 OV ORVICW ssbb cases eoe etre Um iD CEPR E UR 7 1 722 Features pee eiut 7 1 73 Smphfied Model seno tru Ree erret ges 7 1 74 Overview of DIO 7 2 7 4 1 Parallel Modes ssc eniin te oem eer 7 2 7 4 1 1 Parallel rd tet 7 3 7 4 1 2 Parallel Output nenne 7 3 7 4 2 Serial Mode eT EE NIU e et ee ees 7 4 7 4 2 1 serial Input eoe estere 7 4 7 4 2 2 serial Output eee tete te 7 4 7 4 2 3 Serial YO ves vee nere trt heels 7 5 TS PumInterfacess e cec e e iE t iR 7 6 7 6 Programming Information essent nennen nennen nennen 7 7 7 6 1 Windowed Mode Register Access Example 7 7 7 6 2 Programming the Digital 2 2 20000 7 8 7 6 2 1 Parallel Digital 7 9 7 6 2 2 Hardware Controlled Serial Digital I O 7 10 7 6 2 3 Software Controlled Serial Digital I O 7 12 7 6 2 4 P
94. 2 Register address 4 Setting this bit to 1 causes the SI counter to switch load registers at its next TC This action is internally synchronized to the falling edge of the internal signal SI CLK You can use this bit for scan rate change during an acquisition This bit is cleared automatically DAQ STC Technical Reference Manual 2 70 National Instruments Corporation Chapter 2 Analog Input Timing Control SI Write Switch bit 3 type Write in AI Mode 2 Register address 13 This bit enables the write switch feature of the SI load registers Writes to SI load register A are 0 Unconditionally directed to SI load register A 1 Directed to the inactive SI load register SI2 Arm bit 12 type Strobe AI Command 1 Register address 8 Setting this bit to 1 arms the SI2 counter The counter remains armed and the bit remains set until it is disarmed either by hardware or by setting Disarm to 1 Related bitfields AI 812 Armed St AI Disarm SI2 Armed St bit 11 type Read in AI Status 2 Register address 5 This bit indicates whether the SI2 counter is armed 0 Disarmed 1 Armed Related bitfields 512 Arm SI2 Initial Load Source bit 9 type Write in AI Mode 2 Register address 13 This bit selects the initial 512 load register 0 Load register A 1 Load register B Do not change this bit while the counter is counting SI2 Load bit 11 type Strobe AI Command
95. 32 arming 3 41 notation 4 18 bitfield descriptions 3 45 to 3 84 overview 4 17 board power up initialization 3 39 pulse and continuous pulse train generation 4 28 to 4 31 pulse train generation for ETS 4 33 to 4 34 reading counter contents 4 34 reading hardware save registers 4 34 to 4 35 relative position sensing 4 23 to 4 24 resetting 4 18 simple event counting 4 19 to 4 20 single period and pulsewidth measurement 4 24 to 4 25 interrupt handling 8 5 to 8 12 Interrupt Group A 8 6 to 8 9 Interrupt Group B 8 9 to 8 12 interrupt program 8 6 interrupt interface 8 3 to 8 5 interrupt output polarity 8 3 interrupt output select and enable 8 3 to 8 4 changing update rate 3 44 to 3 45 counting for waveform staging 3 40 hardware gate programming 3 39 interrupts 3 45 master slave operation considerations 3 45 overview 3 38 resetting 3 38 software gate operation 3 40 update selection 3 40 to 3 41 waveform staging 3 42 to 3 44 bus interface module 9 3 to 9 5 bitfield descriptions 9 4 to 9 5 write strobes 9 4 digital I O 7 7 to 7 15 bitfield descriptions 7 13 to 7 15 control lines 7 12 hardware controlled serial digital I O 7 10 to 7 12 parallel al 7 9 pass through interrupt 8 4 to 8 5 roerammine the digital interface miscellaneous functions 10 10 to 10 15 s to no i analog trigger 10 12 reading status lines 7 13 bitfield descriptions 10 12 to 10 15 software controlled serial digita
96. 49 SC Control Circuit State Transitions National Instruments Corporation 2 125 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 2 8 3 3 SI Counter The SI counter is a 24 bit down counter with dual load registers The SI counter counts the interval between internal STARTS as well as the delay from the initial trigger to the start of the first internal or external START The bitfield SI Source Polarity selects the polarity of the source clock 51 SRC The counter load registers are directly accessible in write mode from the register map If the counter is disarmed AI 51 Load will load the counter with the value from the selected load register The SI Write Switch option allows the load register writes to be directed to the inactive load register During normal operation the SI counter will synchronously reload from the selected load register following SI TC Several options exist SI Reload Mode AI SI Switch Load END AI 51 Switch Load STOP and AI SI Switch Load On for the SI counter to change the selected load register under various conditions The options are alternate load registers once after each STOP switch load registers on every STOP alternate load registers once after each SC TC switch load registers on every SC switch load registers on the next TC switch load registers on the next STOP switch load registers on the next SI TC The term
97. 50 TC signal description table 2 117 DIV counter operation 2 129 signals See also pin interface specific signal names alphabetical list of pins table C 1 to C 7 analog input timing control module internal signals and operation table 2 113 to 2 119 signal definitions for timing 2 84 to 2 85 trigger selection and conditioning 2 122 to 2 123 trigger signal programming information 2 32 to 2 33 analog output timing control module internal signals and operation table 3 109 to 3 114 signal definitions for timing 3 84 to 3 86 trigger selection and conditioning 3 116 trigger signal programming information 3 23 to 3 24 summary of buffer types table C 7 to C 8 simple event counting description 4 4 programming 4 19 to 4 20 simple gated event counting 4 4 National Instruments Corporation 1 35 Index Single Period And Pulse Width Measurement function 4 24 to 4 25 single pulse generation 4 9 to 4 10 Single Pulse Generation function 4 29 to 4 30 single scan analog input programming 2 42 to 2 43 single triggered pulse generation 4 10 single buffer mode primary analog output 3 13 single period measurement 4 6 to 4 7 single pulsewidth measurement 4 7 single wire mode 2 18 Slow Internal Time Divide By 2 bit 10 14 Slow Internal Timebase bit 10 15 SOC signal ADC control 2 7 basic analog input timing 2 86 to 2 87 description table 2 23 simplified analog input model 2 5 software gate operation
98. 6 This bit indicates whether the UI2 counter is armed 0 Disarmed 1 Armed 0 UI2 Configuration End bit 10 type Strobe Joint Reset Register address 72 This bit clears AO UI2 Configuration Start which holds the secondary analog output circuitry in reset to prevent glitches on the output pins during configuration You should set this bit to 1 at the end of the UI2 counter configuration process This bit is cleared automatically Related bitfields UI2 Configuration Start 0 UI2 Configuration Start bit 6 type Strobe Joint Reset Register address 72 This bit holds the secondary analog output circuitry in reset to prevent glitches on the output pins during configuration You should set this bit to 1 at the beginning of the UI2 counter configuration process By doing this you ensure that no spurious glitches appear on the output pins and on the internal circuit components If you do not set this bit to 1 the DAQ STC may behave erroneously You can clear this bit by setting AO UD Configuration End to 1 Related bitfields UI2 Configuration End National Instruments Corporation 3 75 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 UI2 Count Enabled St bit 13 type Read in AO Status 2 Register address 6 If the UI2 counter is armed this bit indicates whether the UI2 counter is counting 0 No 1 Yes If the counter is not armed this bit should be ignored
99. 61 Figure 4 31 SOURCE 2400 0 0 neret 4 72 Figure 4 32 Simple Event Counting sees nennen nennen 4 73 Figure 4 33 Simple Gated Event Counting 4 73 Figure 4 34 Buffered Noncumulative Event 4 74 Figure 4 35 Buffered Cumulative Event Counting 4 75 Figure 4 36 Relative Position 4 75 Figure 4 37 Single Period 4 76 Figure 4 38 Single Pulsewidth Measurement eese 4 77 Figure 4 39 Buffered Period 4 78 Figure 4 40 Buffered Semiperiod 4 79 Figure 4 41 Buffered Pulsewidth Measurement sese 4 80 Figure 4 42 Single Pulse 4 81 Figure 4 43 Single Triggered Pulse 4 82 Figure 4 44 Retriggerable Single Pulse Generation sese 4 83 Figure 4 45 Continuous Pulse Train 4 84 Figure 4 46 Buffered Pulse Train Generation 4 85 Figure 4 47 Frequency Shift Keying 0 sess rennen 4 86 Figure 4 48 Pulse Generation for 4 87 Figure 7 1 Simplified Model 7 2 Figure 7 2 Parallel Inp t sciet ee neret ih ber etc 7 3 Figure 7 3 Parallel Output eise see citet e HP DRESSER 7 3 Figure 7 4 DIO Serial Input iiie deem reete 7 4 DAQ STC Technical Reference Manual x
100. A The SI counter initially loads from load register A and then the SI load source is set to B During the acquisition the SI counter reloads from load register B except for the last reload when it reloads from SI load register A Similarly the SI2 counter alternate first period reload modes provide a retriggerable method for obtaining a delay between START and CONVERT which is different from the sample interval Software stores the sample interval in SI2 load register B and the delay from START SI2 load register SI2 counter initially loads from load register A and then the SI2 load source is set to B During each scan the SI2 counter reloads from load register B except for the last reload when it reloads from SI2 load register A The DIV counter is a 16 bit binary down counter that divides down the configuration FIFO clock LOCALMUX when an external multiplexer is used It can also be used to provide an internally generated STOP trigger Each of these counters except DIV has dual load registers so that their reload value can be changed while they are counting The SI and SC counters each have a save register that can be used to hold the contents of the counter The SI 512 SC and DIV counters each have their own control block The counter control blocks are synchronous control circuits that use the counter mode information trigger and gate signals and state of the counter to generate the count enable and load c
101. AI STARTI Interrupt Enable bit 2 77 AI STARTI Polarity bit 2 77 AI STARTI Pulse bit 2 77 AI STARTI Second Enable bit 2 78 AI STARTI Select bit 2 78 AI St bit 2 78 AI STARTI Sync bit 2 78 AI START2 Edge bit 2 79 AI START2 Interrupt bit 2 79 AI START2 Interrupt Enable bit 2 79 AI START2 Interrupt Polarity bit 2 79 AI START2 Interrupt Pulse bit 2 79 AI START2 Second Enable bit 2 80 AI START2 Select bit 2 80 AI START2 St bit 2 80 AI START2 Sync bit 2 80 AI STOP Edge bit 2 81 AI STOP IN signal table 2 20 AI STOP Interrupt bit 2 81 National Instruments Corporation I 3 Index AI STOP Interrupt Enable bit 2 81 AI STOP OUT signal table 2 20 AI STOP Polarity bit 2 81 AI STOP Pulse bit 2 81 AI STOP Second Irq Enable bit 2 82 AI STOP Select bit 2 82 AI STOP St bit 2 82 AI STOP Sync bit 2 83 AI Trigger Length bit 2 83 AI Trigger Once bit 2 83 AI Trigger Signals function 2 32 to 2 33 AIERROR signal table 2 113 AIFEF signal data FIFO control 2 7 data FIFO timing 2 88 description table 2 19 AIFFF signal data FIFO control 2 7 data FIFO timing 2 88 description table 2 19 AIFHF signal data FIFO control 2 7 data FIFO timing 2 88 description table 2 19 AIFIFOREQ signal table 2 113 AIFREQ signal data FIFO timing 2 88 description table 2 20 simplified analog input model 2 5 to 2 6 AITM See analog inp
102. AO START Select Register address 66 This bitfield selects the START trigger 0 Bitfield AO START Pulse or alternate TC 1 10 lt 0 9 gt 11 17 RTSI lt 0 gt 31 Logic low This bitfield is currently not supported and it must be set to 0 DAQ STC Technical Reference Manual 3 62 National Instruments Corporation Chapter 3 Analog Output Timing Control 0 START St bit 10 type Read in AO Status 1 Register address 3 This bit indicates that a valid START signal has been received by the AOTM 0 No 1 Yes This bit is currently not supported and its setting is undefined 0 Start Stop Gate Enable bit 13 type Write in AO Command 2 Register address 5 This bit enables the start stop gate 0 Disabled 1 Enabled This bit is currently not supported and it must be set to 0 0 Start Stop Gate St bit 7 type Read in Joint Status 1 Register address 27 This bit indicates the status of the start stop gate if start stop gating is enabled 0 Inactive gate 1 Active gate This bit is currently not supported and its setting is undefined 0 START Sync bit 6 type Write in AO START Select Register address 66 This bit enables internal synchronization of the START trigger 0 Disabled 1 Enabled This bit is currently not supported and it must be set to 0 0 START1 Disable bit 12 type Write in AO Mode 2 Register address 39 This bit disables rec
103. B 2 Registers in Order of Address Address Register Name 0 Window Address Register 1 Window Data Write Register 2 Interrupt Register 3 Interrupt Register 4 Command 2 Register 5 AO Command 2 Register 6 GO Command Register 7 G1 Command Register 8 Command 1 Register 9 AO Command 1 Register 10 DIO Output Register 11 DIO Control Register 12 AI Mode 1 Register 13 AI Mode 2 Register 14 15 AI SI Load Registers 16 17 AI SI Load B Registers 18 19 AI SC Load A Registers 20 21 AI SC Load B Registers 23 AI SI2 Load A Register 25 AI SI2 Load B Register 26 GO Mode Register 27 G1 Mode Register 28 29 GO Load Registers 30 31 GO Load B Registers 32 33 Load A Registers 34 35 Load B Registers National Instruments Corporation B 5 DAQ STC Technical Reference Manual Appendix B Register Information Table B 2 Registers in Order of Address Continued Address Register Name 36 GO Input Select Register 37 Input Select Register 38 AO Mode 1 Register 39 AO Mode 2 Register 40 41 AO UI Load A Registers 42 43 AO UI Load Registers 44 45 AO BC Load A Registers 46 47 AO BC Load B Registers 48 49 AO UC Load Registers 50 51 AO UC Load B Registers 53 AO UD Load A Register 55 AO UD Load B Register 56 Clock and FOUT Register 57 IO Bidirection Pin Register 58 RTSI Trig Direction Register 59 Interru
104. Buffered Pulse Train Generation 4 4 4 4 Frequency Shift Keying FSK FSK is similar to pulse train generation in that the counter generates a train of pulses However in FSK mode the G_GATE signal modulates the frequency and duty cycle of the output train GPCT module implements frequency modulation by allowing the signal to select the load registers Figure 4 19 shows an example of FSK When G_GATE is low the counter generates a low frequency signal with a long pulsewidth When is high the counter generates a high frequency signal with a short pulsewidth DAQ STC Technical Reference Manual 4 14 National Instruments Corporation Chapter 4 General Purpose Counter Timer su CILE EIE LRL DELI START Figure 4 19 Frequency Shift Keying 4 4 4 5 Pulse Generation for ETS In pulse generation for ETS the counter produces a pulse on the output a specified delay after the first GATE active edge After each successive G_GATE active edge the counter automatically increments or decrements the delay from G_GATE This type of waveform can be used in under sampling applications where a digitizing system can sample repetitive waveforms that are higher in frequency than the Nyquist frequency of the system For this application the bandwidth of the track and hold limits the useful frequency range not the converter The i
105. CONVERT figure 2 111 theory of operation 2 17 to 2 18 hardware gate programming analog input timing control 2 30 to 2 31 secondary analog output operation 3 39 overview 2 16 2 109 software gate operation analog input timing control 2 31 secondary analog output operation 3 40 general purpose counter timer 4 1 to 4 56 counter timer functions 4 3 to 4 15 event counting 4 3 to 4 6 pulse generation 4 9 to 4 12 pulse train generation 4 12 to 4 15 time measurement 4 6 to 4 9 features 4 1 to 4 2 DAQ STC Technical Reference Manual 1 24 overview 4 1 pin interface table 4 16 programming information 4 17 to 4 52 arming 4 18 bitfield descriptions 4 35 to 4 52 buffered event counting 4 20 to 4 22 buffered period semiperiod and pulsewidth measurement 4 26 to 4 28 enabling general purpose counter timer output pin 4 35 frequency shift keying 4 31 to 4 32 notation 4 18 overview 4 17 pulse and continuous pulse train generation 4 28 to 4 31 pulse train generation for ETS 4 33 to 4 34 reading counter contents 4 34 reading hardware save registers 4 34 to 4 35 relative position sensing 4 23 to 4 24 resetting 4 18 simple event counting 4 19 to 4 20 single period and pulsewidth measurement 4 24 to 4 25 simplified model 4 2 to 4 3 specifications A 1 timing diagrams 4 53 to 4 56 CTRGATE reference pin selection table 4 54 CTRSRC minimum period and minimum pulsewidth figure 4 55 CTRSRC reference pi
106. CONVERT Oniginal Pulse AI CONVERT Pulse Timebase AI CONVERT Pulse Width SC LOAD SC Load This signal pulses to load the value from the selected SC load register into the SC counter Related bitfields SC Load SC LOAD SRC SC Load Source This signal determines which load register A or B the SC counter will use on the next reload The initial SC load source is set using AI SC Initial Load Source The SC control logic updates the load source while the AITM is counting The current load source depends on the counter state and the selected reload mode Related bitfields SC Initial Load Source SC SRC SC Source The SC source is the timebase for the SC and DIV counters In the internal CONVERT mode SC SRC is the same signal as 512 SRC In the external CONVERT mode SC SRC is equal to SCLK The external trigger and gate inputs which are not generated synchronous to the SC source outside of the AITM can and should be synchronized to the SC source inside of the AITM SC STARTI STARTI Synchronized to SC SRC This signal is generated by the hardware by passing ADR STARTI through the master slave trigger circuitry SC TC Scan Counter TC This signal indicates to the counter control logic that the programmed number of scans has been generated 50 CE SI2 Count Enable This signal enables and disables the SI2 counter Refer to section 2 8 3 6 512 Control for 512 CE logic equations
107. CONVERT output signal 0 HighZ 1 Ground 2 Enable active low 3 Enable active high This bitfield also selects the polarity of the PFIZ CONV output signal if enabled for output 0 Active low 1 Ground 2 Active low 3 Active high Related bitfields 2 Pin Dir CONVERT Pulse bit 0 type Strobe AI Command 1 Register address 8 Setting this bit to 1 produces a pulse on the CONVERT and PFI2 CONV output signals if the signals are enabled for output and if CONVERT pulses are not blocked CONVERT pulses can be blocked by the external gate the software gate the start stop gate or the SC gate The pulsewidths of the output signals are determined by AI CONVERT Pulse Width This bit is cleared automatically This bit is disabled when Configuration Start is set to 1 Related bitfields AI CONVERT Output Select BD 2 Pin Dir AI CONVERT Pulse Width CONVERT Pulse Timebase bit 11 type Write in AI Personal Register address 77 This bit determines how the pulsewidths of the CONVERT and PFI2 CONV signals are selected 0 Selected by AI CONVERT Pulse Width 1 Selected by AI CONVERT Original Pulse Related bitfields CONVERT Pulse Width AI CONVERT Original Pulse DAQ STC Technical Reference Manual 2 50 National Instruments Corporation Chapter 2 Analog Input Timing Control CONVERT Pulse Width bit 10 type Write in AI Personal Register address 77 If AI CONVERT Pulse Timeb
108. Command 2 Register address 5 Setting this bit to 1 causes the UC counter to switch load registers at the next BC This action is internally synchronized to the falling edge of the CLK This bit is cleared automatically 0 UC Switch Load On TC bit 5 type Strobe AO Command 2 Register address 5 Setting this bitto 1 causes the UC counter to switch load registers at the next TC This action is internally synchronized to the falling edge of the CLK This bit is cleared automatically 0 UC TC Interrupt Ack bit 7 type Strobe Interrupt Register address 3 Setting this bit to 1 clears AO UC St and acknowledges the UC interrupt request in either interrupt bank if the UC TC interrupt is enabled This bit is cleared automatically Related bitfields St DAQ STC Technical Reference Manual 3 70 National Instruments Corporation Chapter 3 Analog Output Timing Control 0 UC TC Interrupt Enable bit 6 type Write in Interrupt Enable Register address 75 This bit enables the TC interrupt 0 Disabled 1 Enabled UC TC interrupts are generated on the leading edge of UC TC 0 UC TC Second Irq Enable bit 6 type Write in Second Enable Register address 76 This bit enables the interrupt in the secondary interrupt bank 0 Disabled 1 Enabled UC TC interrupts are generated at the leading edge of UC TC 0 UC TC St
109. DIO Control Register address 11 If DIO HW Serial Enable is set to 0 the inverted state of this bit is reflected on the EXTSTROBE SDCLK pin Generic Status bits lt 8 11 gt type Read in Joint Status 2 Register address 29 This bitfield reflects the value of the STATUS lt 0 3 gt pins 7 7 Timing Diagrams This section presents the timing for the serial DIO mode 1 1 1 Serial Input Timing In the serial input mode the rising edge of the EXTSTROBE SDCLK signal clocks data on the DIO4 SDIN line Figure 7 7 shows the setup and hold times for serial input National Instruments Corporation 7 15 DAQ STC Technical Reference Manual Chapter 7 Digital 1 0 Tsu Th EXTSTROBE SDCLK DIO4 SDIN D D D Name Description Minimum Maximum Tsu DIO4 SDIN setup 14 Th DIO4 SDIN hold 0 timing values are in nanoseconds Figure 7 7 Serial Input Timing 1 1 2 Serial Output Timing In the serial output mode the falling edge of the EXTSTROBE SDCLK signal clocks data on the DIOO SDOUT line Figure 7 8 shows the propagation delay for serial output Tpd extstRope socLK PCO DIO0 SDOUT X X Description Minimum Maximum Tpd EXTSTROBE SDCLK to DIOO0 SDOUT 0 10 timing values are in nanoseconds Figure 7 8 Serial Output Timing DAQ STC Technical Reference Manual 7 16 National Instruments Corporation Chapter 7 Di
110. Description AIFREQ O4TU Data FIFO Request This output is a FIFO request signal that indicates that the data FIFO contains data that requires service The AIFREQ signal is generated directly from the data FIFO status flags AIFEF AIFHF and AIFFF and the internal SC_TC signal Output polarity is selectable Destination DMA Controller or CPU Options Active Low Active High Related bitfields Polarity AI FIFO Mode AI STOP IN 105 Dedicated STOP Input This input provides a optimized path for the end of scan signal LAST CH from the configuration FIFO Internally the STOP IN signal is routed directly to the STOP selector Source Configuration FIFO Related bitfields AI STOP Select AI STOP OUT O4TU Dedicated STOP Output This output reflects the state of the active high internal STOP signal The hardware generates AI STOP OUT and the internal STOP signal by passing the output of the STOP selector through polarity selection edge detection and synchronization Output polarity is selectable Related bitfields STOP Select AI STOP Polarity AI STOP Edge AI STOP Sync AI STOP St CONVERT O9TU ADC Conversion Strobe This output instructs the ADC to perform a conversion The hardware generates CONVERT by passing the internal sample clock SCLK signal through pulsewidth and polarity selection circuitry Output polarity is selectable Destination ADC Options Ac
111. GOUT signal from general purpose counter 1 G TBI The internal signal G IN TIMEBASEI SW Software strobe TB2 The internal signal IN TIMEBASE2 Note When the analog trigger circuit is enabled the analog trigger signal takes over the slot in the PFI selectors The PFI pins will power up as inputs and will primarily be used as inputs however PFI pins can also be configured as outputs When configured as an output each pin reflects the status of a particular signal related to the user timing signals The output capability on these pins is useful for synchronizing external circuitry to the board Table 5 3 indicates the internal signal that will be output on each PFI pin when the pin is configured for output Refer to section 5 3 Pin Interface for more detailed information on the internal signal tap point Table 5 3 PFI 0 9 Output Selections PFI SIGNAL 0 AI STARTI 1 AI START2 2 CONVERT 3 Source 4 Gate 5 AO UPDATE 6 AO STARTI DAQ STC Technical Reference Manual 5 8 National Instruments Corporation Chapter 5 Programmable Function Inputs Table 5 3 PFI 0 9 Output Selections PFI SIGNAL 7 AI START or AI SCAN PROG 8 G0 Source 9 GO Gate National Instruments Corporation 5 9 DAQ STC Technical Reference Manual RTSI Trigger 6 1 Overview This chapter describes the features of the RTSI trigger module RTM and explains
112. Gi Up Down 0 down counting or 1 up counting Gi_Bank_Switch_Enable 0 Gi_Bank_Switch_Mode 0 Gi_TC_Interrupt_Enable 0 Gi_Gate_Interrupt_Enable 0 4 6 1 8 Single Period and Pulsewidth Measurement Single period and pulsewidth measurement are applications in which a general purpose counter counts the edges of its source signal normally a clock between successive pairs of gate events Counter contents are saved at the second of the gate events for later retrieval i Note The second of the gate events may also be the first gate event in the next pair Single period measurement mimics the behavior of the NI DAQ functions for the Am9513 counter chip In single period measurement source edges are counted between successive pairs of active gate edges In single pulsewidth measurement source edges are counted between the time the gate signal reaches the active level and the time the gate signal reaches the inactive level The only possible error condition is rollover Rollover is explained in section 4 4 1 1 Simple Event Counting Use this function to program a counter for a single period measurement or single pulsewidth measurement Program the Gi_Source to select the signal that you want to use as a reference clock Program the Gi_Gate to select the signal on which you want to measure the period or pulsewidth Function Single_Period_And_Pulse_Width_Measurement Gi_Load_Source_Select 0 Gi_Load_A initial c
113. Internal UPDATE In the internal UPDATE mode UPDATE pulses are generated by UI TC UI counter TC The STARTI trigger causes the UI counter to begin counting The UI counter has dual load registers which allow for two timing parameters at the UPDATE timing level The first parameter gives the delay from STARTI to the first UPDATE The second parameter B gives the delay between UPDATE pulses Figure 3 9 shows a sequence of UPDATE pulses and indicates the timing parameters that are available National Instruments Corporation 3 11 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control START1 UPDATE UI TC DEM o A Timing Parameter 1 1 1 Figure 3 9 Internal UPDATE Timing 3 4 4 2 External UPDATE In the external UPDATE mode externally generated UPDATE pulses enter the DAQ STC through one of the PFI lt 0 9 gt or RTSI lt 0 6 gt inputs or general purpose counter 1 Alternately the UPDATE may come from general purpose counter 1 Only one timing parameter is available in this model the delay between UPDATE pulses This delay is determined by the period of the external UPDATE signal The delay from STARTI to the first UPDATE depends upon the relationship between the STARTI trigger and the external UPDATE and can vary Figure 3 10 shows a sequence of externally timed UPDATE pulses and indicates the delay from START to the first UPDATE
114. Level External UPDATE Mode 3 103 External Trigger Synchronous Edge External UPDATE Mode 3 103 STARTI Delays Synchronous Mode Internal UPDATE 3 105 STARTI Delays Synchronous Mode External UPDATE 3 106 STARTI Delays Asynchronous 3 107 ent een Ue 3 107 UC TC Dela Jere tte rete ete ner RO 3 108 AOTM Block Diagram eene 3 109 STARTI Routing Logic nineteenth nitentes 3 115 EXT and EXT GATE2 Routing 222 3 115 UI Control Circuit State Transitions 3 118 UC Control Circuit State 3 119 BC Control Circuit State Transitions 3 121 General Purpose Counter Timer Simplified Model 4 2 Simple Event Counting sees eene nennen 4 4 Simple Gated Event 4 4 Buffered Noncumulative Event 4 5 Cumulative Event Counting 4 5 Relative Position Sensing sese 4 6 Single Period Measurement 4 7 Single Pulsewidth 4 7 Buffered Period Measurement sse 4 8 Buffered Semiperiod 4 8 National Instruments Corporation Xvii DAQ STC Technical Reference Manual Contents Figure 4 11 Buffered Pulsewidth
115. Manual Chapter 2 Analog Input Timing Control AI Start Stop bit 3 type Write in AI Mode 1 Register address 12 This bit enables START and STOP control of the analog input operation 0 Disabled 1 Enabled You should normally set this bit to 1 Start Stop Gate Enable bit 14 type Write in AI Mode 2 Register address 13 This bit enables the start stop gate STST 0 Disabled 1 Enabled When start stop gate is enabled external CONVERT pulses pass through the DAQ STC only during the interval between the assertion of START and the assertion of STOP You should enable the start stop gate in the external CONVERT mode You must disable the start stop gate in the internal CONVERT mode Related bitfields AI Start Stop Gate St Start Stop Gate St bit 5 type Read in Joint Status 1 Register address 27 This bit indicates the status of the start stop gate if start stop gating is enabled 0 External CONVERTS are blocked because a valid START has not been received 1 External CONVERT S are allowed to pass Related bitfields AI Start Stop Gate Enable START Sync bit 6 type Write AI START STOP Select Register address 62 This bit enables internal synchronization of the START trigger 0 Disabled 1 Enabled You should normally set this bit to 1 You must set this bit to O for the single wire case START Disable bit 11 type Write in AI Command 2 Register
116. On End Of Scan AI End On SC TC Continuous SCKG STOP Trigger Once AB Mim SEIS WAIT EMKT AB CNT E K M T SCKG CONVERT Source Select SI2 TC T G H H l J DIV_LOAD EK Load DIV_CE BK CNT n CNT n 1 DIV_DISARM CNT n WAIT n 1 H I Figure 2 52 DIV Control Circuit State Transitions 2 8 4 Interrupt Control DAQ STC Technical Reference Manual The analog input contains the hardware necessary for generating software interrupts based on several conditions The interrupt programming is accomplished using the Interrupt_A_Enable_Register and the Second_Irq_A_Enable_Register Interrupts remain active until cleared by software Software can program the interrupts to occur under the following conditions overflow or overrun error START STOP START1 START2 SC_TC and FIFO condition All of the interrupts work independently with the exception of the STOP interrupt In order for the STOP interrupt to operate properly the START interrupt must also be enabled and operating In addition the START interrupt must be acknowledged prior to the assertion of the STOP signal in order for STOP to generate an interrupt When the SC_TC interrupt is enabled an interrupt is generated on every SC_TC falling edge unless the pretrigger acquisition mode is selected In the pretrigger acquisition mode the interrupt is generated only on SC_TC falling edges that occur a
117. Output Select 2 enable active low or 3 enable active high Base selection on board hardware AI EXTMUX CLK Pulse Width 0 4 5 OUT TIMEBASE periods or 1 same as LOCALMUX CLK If more than one external MUX channel corresponds to each internal channel then AI External MUX Present 1 AI DIV Load A number of external channels corresponding to each internal channel 1 L AI DIV_Load 1 Else AI External MUX Present 0 National Instruments Corporation 2 29 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Else AI External MUX Present 0 AI EXTMUX CLK Output Select 0 high 2 or 1 forced to logic low Base selection on board hardware L AI Configuration End 1 End critical section If AI External MUX Present is set to 1 you should use the DIV counter to account for the external to internal multiplexing factor In this case you cannot use the DIV counter to generate the STOP trigger 2 6 3 5 FIFO Request Use this function to select the data FIFO condition on which interrupt or DMA requests will be generated Function FIFO Request Selection Begin critical section AI_Configuration_Start 1 AI Mode 0 FIFO not empty or 1 FIFO half full or 2 FIFO full or 3 FIFO half full until FIFO empty Y AI Configuration End 1 End critical section 2 6 3 6 Hardware Gate Programming Use this function to en
118. Output Timing Control 0 Mode bits lt 14 15 gt type Write in AO Mode 2 Register address 39 This bitfield selects the data FIFO condition on which to generate the DMA request output signal AOFREQ or FIFO interrupt 0 Onempty FIFO 1 On half full or less FIFO 2 On less than full FIFO 3 Generate on half full or less FIFO but keep asserted until FIFO is full Related bitfields FIFO Interrupt Enable AO FIFO Second Enable Enable 0 FIFO Request St bit 1 type Read in AO Status 1 Register address 3 This bit indicates the status of the DMA request output signal AOFREQ and FIFO interrupt 0 Not asserted 1 Asserted AO FIFO Mode selects the condition on which to generate the DMA request and FIFO interrupt Related bitfields FIFO Mode 0 FIFO Retransmit Enable bit 13 type Write in AO Mode 2 Register address 39 This bit enables the local buffer mode 0 Disabled 1 Enabled In the local buffer mode the contents of the data FIFO are regenerated when the FIFO empties The AOTM accomplishes this by pulsing the AOFFRT signal when the FIFO empty condition is indicated the AOFEF You can use the local buffer mode when the FIFO is large enough to hold the whole waveform to be generated and the waveform does not vary in time FIFO Second Enable bit 8 type Write in Second Enable Register address 76 This bit enables the FIFO interrupt in
119. Polarity are the options for selection of STARTI synchronization edge detection and polarity STARTI is always external and should be edge detected and synchronized unless it is sourced from another DAQ STC operating from the same source clock and timing can be guaranteed STARTI is used by all counters and is therefore synchronized to both SI SRC and 5 SRC START initiates the final scan sequence in the pretrigger mode AI START2 Sync AI START2 Edge and AI START2 Polarity are the options for selection of START2 synchronization edge detection and polarity 5 2 is always external and should be edge detected and synchronized unless it is sourced from another DAQ STC operating from the same source clock and timing can be guaranteed START2 is used by the SC counter and is therefore synchronized to SC SRC START initiates a predetermined number of conversion pulses during each scan When internally generated START 15 the 51 TC signal AI START Sync AI START Edge AI START Polarity are the options for selection of START synchronization edge detection and polarity When externally generated START should be edge detected and synchronized unless it is sourced from another DAQ STC operating from the same source clock and timing can be guaranteed START is used by the SC counter and is therefore synchronized to SC SRC DAQ STC Technical Reference Manual 2 122 National Instruments Corporation 2 8 3 Chapter 2 Analog I
120. Purpose Counter Timer Figure 4 32 shows an example of simple event counting where the counter counts four events on G SOURCE The dotted line indicates where the ARM occurs G SOURCE X 1 X2X 3 X4 Counter Value 0 Figure 4 32 Simple Event Counting 4 8 11 2 Simple Gated Event Counting To use this function set G CONTROL conditioning to level gating and program the counter to count on CONTROL is synchronized by the falling edge of SOURCE to generate G CONTROL The counter increments only when CONTROL is high The HW save register switches to transparent mode on the falling edge of GATE and returns to latched mode on the next SOURCE falling edge Figure 4 33 shows an example of simple gated event counting where the gate action allows the counter to count only four of the rising edges of G SOURCE The HW save register latches the counter value each time the counting stops The dotted line indicates where the ARM occurs and the arrow indicates where the gate interrupt is generated G SOURCE G GATE o G CONTROL ar x 1X X 3 HW Save Counter Value X A 3 HW Save Register Figure 4 33 Simple Gated Event Counting National Instruments Corporation 4 73 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter
121. STARTI Pulse AI STARTI St bit 7 type Read in AI Status 1 Register address 2 This bit indicates that a valid STARTI trigger has been received by the DAQ STC 0 No 1 Yes A valid START trigger is one that is received while the SC counter is armed and in the WAIT state This bit can be cleared by setting STARTI Interrupt to 1 Related bitfields AI SC Arm AI STARTI Interrupt Refer to Table 8 2 Interrupt Condition Summary for more information START1 Sync bit 6 type Write in AI Trigger Select Register address 63 This bit enables internal synchronization of the STARTI trigger to the SC source 0 Disabled 1 Enabled You should set this bitto 1 unless STARTI is synchronized externally to the signal selected as the CONVERT source You must set this bit to 1 if AI 5 Select is set to 0 You should set this bit to 0 if the ASIC is a STARTI slave to another DAQ STC Related bitfields AI STARTI Select DAQ STC Technical Reference Manual 2 6 National Instruments Corporation Chapter 2 Analog Input Timing Control START2 Edge bit 12 type Write in AI Trigger Select Register address 63 This bit enables edge detection of the START trigger 0 Disabled 1 Enabled You should normally set this bit to 1 unless the DAQ STC is used in a very noisy environment You should set this bit to 0 if the ASIC is a START2 slave to another DAQ STC START2 Interrupt
122. Serial DIO Setup Call DIO_HW_Serial_Configure Serial DIO Start Call DIO HW Serial Initialize Serial DIO Wait Loop While DIO Serial IO In Progress St is 1 wait Wait for last bit to be transferred Delay Serial DIO Input Call DIO Serial In If you do not need serial digital output you can omit the Serial DIO Output section from your program If you do not need serial digital input you can omit the Serial DIO Input section from your program If in addition you know that no software running on your computer will need the National Instruments Corporation 7 11 DAQ STC Technical Reference Manual Chapter 7 Digital 1 0 serial digital output line during the time required for eight bits to be output serially you can also omit the Serial DIO Wait Loop section from your program To perform several serial digital I O operations in sequence the Serial DIO Wait Loop is necessary however you can exclude the Serial DIO Setup section from the programming sequence for all 8 bit data entities except the first r Note To perform serial output without the serial input the value in DIO_Serial_Data_In_St will become undefined You can perform serial output on pin DIOO and ignore serial input data You cannot perform hardware controlled serial input on pin DIO4 and software controlled parallel output on pin DIOO at the same time unless you want to keep the same value on the pin DIOO for the duratio
123. Table 9 3 Intel Bus Interface Timing Name Description Minimum Maximum Tcs ds CS DS pulsewidth 50 I Tads Address setup time Address hold time Trws Rd wr setup time Trwh Rd wr hold time 3 Tdv Data valid 13 50 Tdi Data invalid 10 Tds Data setup time 25 Tdh Data hold time 0 All timing values are in nanoseconds Number in parentheses indicates a 100 pF load The DAQ STC generates an internal read or write signal based upon the read write data strobe and chip select signals at the pins The internal signals will be asserted only when both the chip select and data strobe signals are asserted shown above as CS DS The timing parameters are all relative to the combined signal DAQ STC Technical Reference Manual 9 8 National Instruments Corporation Miscellaneous Functions 10 1 Overview This chapter discusses the miscellaneous functions not covered in the other chapters The miscellaneous functions include clock distribution the programmable frequency output analog triggering and test mode The clock distribution circuit routes the master timebase to each of the internal modules and allows the master timebase to be shared between multiple DAQ STCs The programmable frequency output provides a divide down version of the master timebase for board use The analog trigger circuit provides an alternate triggering mechanism for the AITM AOTM and GPCT that can trigger base
124. Write TT 0 4 AI SC Load A Registers Write 18 19 0x12 0x13 AI SC Load B Registers Write 20 21 0 14 0 15 AI SC Save Registers Read 66 67 0 42 43 AI SI Load A Registers Write 14 15 OxOE OxOF AI SI Load B Registers Write 16 17 0 10 0 11 AI SI Save Registers Read 64 65 0 40 0 41 AI SI2 Load A Register Write 23 Ox17 National Instruments Corporation B 1 DAQ STC Technical Reference Manual Appendix B Register Information Table B 1 DAQ STC Registers Continued Register Name Type Address Hex Address AI SI2 Load B Register Write 25 0x19 AI_SI2_Save_Register Read 25 0x19 AI START STOP Select Register Write 62 0 3 Status 1 Register Read 2 0x02 Status 2 Register Read 5 0x05 AI Trigger Select Register Write 63 Ox3F Analog Trigger Etc Register Write 61 Ox3D AO BC Load A Registers Write 44 45 0 2 0 20 AO BC Load B Registers Write 46 47 Ox2E Ox2F AO BC Save Registers Read 18 19 0 12 0 13 Command 1 Register Write 9 0x09 AO Command 2 Register Write 5 0x05 AO Mode 1 Register Write 38 0x26 AO Mode 2 Register Write 39 0x27 AO Mode 3 Register Write 70 0 46 AO Output Control Register Write 86 0x56 AO Personal Register Write 78 4 AO START Select Register Write 66 0x42 AO_Status_1_Register Read 3 0x03 AO_Status_2_Register Read 6 0x06 AO_Trigger_Select_Register Write 67 0x43 AO_UC_Load_A_Registers Write 48
125. a 16 bit sample interval counter SD and a 16 bit divide down counter DIV There are eight timing and control signals associated with the analog input These are the scan interval clock SI source sample interval clock SI2 source ADC conversion strobe CONVERT trigger STARTI second trigger START2 start scan START stop scan STOP and external gate The AITM contains independent multiplexers and conditioning circuits to derive these timing control signals from any of 10 programmable function input PFI signals lt 0 9 gt seven RTSI trigger signals RTSI_TRIGGER lt 0 6 gt or other internal signals This chapter presents a list of the AITM features followed by a simplified model that introduces a few AITM related signals an overview of each of the AITM modes a list of the external pins used by the AITM module programming information for users who need to program the hardware at a low level a complete list of the AITM timing diagrams and a detailed description of the internal workings of the AITM The final section is intended for advanced users Read section 1 1 1 Analog Input Application for more information about devices with which the AITM can work 2 1 1 Programming the AITM To program the AITM of the DAQ STC read the following e Section 1 1 1 Analog Input Application e Sections 22 Features through 2 6 Programming Information As you read section 2 6 Programming Information you will need to refer
126. a new board Related subsections within the chip can be programmed to operate at different clock rates and the necessary synchronization time can significantly affect the edges and pulsewidths of the board level signals Certain configurations of the clock rates offer very straightforward timing signals and these settings should be used for the majority of the DAQ STC designs The other modes are included to provide flexibility for unusual or currently unanticipated applications This section includes all of the timing diagrams for the AITM module of the DAQ STC and indicates the more common configurations Signal Definitions All timing in this section refers to pin to pin timing Because many of the timing parameter definitions are based on internal signals and the internal signals can be selected from a variety of sources this section defines some global signals that can refer to any one of a number of pins depending on the internal selection Some of the tables in this section indicate that the OSC pin is the reference pin with RTSI_OSC immediately following This means that you can use RTSI Clock Mode to choose between OSC and RTSI_OSC as the reference pin 2 7 1 1 CONVERT SRC CONVERT SRC is the signal that causes a CONVERT to be generated Table 2 2 indicates the pin selected as CONVERT SRC based on internal selection Table 2 2 CONVERT SRC Reference Pin Selection AI CONVERT Source Select Reference Pin 0 The CONVERT
127. a scan by using reload mode AI SI Load B number of clocks from STARTI to first START 1 AI SI Load A number of clocks between each START 1 AI SI Initial Load Source 1 L AI SI Load 1 Y AI SI Initial Load Source 0 AI SI Reload Mode 6 alternate first period on every SC TC Else Interval from the START trigger to the first start of scan is equal to the scan interval AI SI Load A number of clocks between each START 1 National Instruments Corporation 2 35 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control AI SI Initial Load Source 0 AI SI Reload Mode 0 X AI SI 1 AI SI Write Switch 0 Else External START mode is selected In the single wire for START and CONVERT case you need to set AI START Sync to 0 The single wire case is defined by START and CONVERT coming from a single external source with the same polarity In other cases it is safe to set AI START Sync to 1 It is always safe to set AI START Edge to 1 If START source and CONVERT source are equal AND START and CONVERT have the same polarity then AI START Select 1 through 10 PFI lt 0 9 gt or 11 through 17 lt 0 6 gt or 18 bitfield AI START Pulse or 19 the OUT signal from general purpose counter 0 AI START Sync 0 AI START 1 AI START Polarity 0 active high or rising edge activ
128. a write cycle signal in Motorola mode a read cycle signal general purpose write strobe signal channels 0 through 3 G 13 DAQ STC Technical Reference Manual Index A lt 1 7 gt signal table 9 2 absolute maximum ratings specifications 2 acquisition level timing and control functions 2 14 to 2 16 continuous acquisition mode 2 15 master slave trigger 2 16 posttrigger acquisition mode 2 14 pretrigger acquisition mode 2 14 to 2 15 staged acquisition 2 16 AD START signal table 2 113 AD STARTI signal table 2 113 AD VSTART 2 signal table 2 113 ADC control 2 7 ADR STARTI signal table 2 113 ADR START signal table 2 113 AI Polarity bit 2 48 AI Analog Trigger Reset bit 2 48 AI Arming function 2 41 AI Board Environmentalize function 2 29 AI Board Personalize function 2 27 AI Config Memory Empty St bit 2 49 AI Configuration End bit 2 49 AI Configuration Start bit 2 49 AI Continuous bit 2 49 AI CONVERT Original Pulse bit 2 50 AI CONVERT Output Select bit 2 50 AI CONVERT Pulse bit 2 50 AI CONVERT Pulse Timebase bit 2 50 AI CONVERT Pulse Width bit 2 51 AI CONVERT Signal function 2 38 to 2 40 AI CONVERT Source Polarity bit 2 51 AI CONVERT Source Select bit 2 51 AI Delay START bit 2 52 AI Delayed START bit 2 51 AI Delayed START bit 2 52 AI Disarm bit 2 52 National Instruments Corporation AI DIV Arm bit 2 52 AI DIV Armed
129. alternate load registers refers to the action of having one load from the secondary load register and the remaining loads from the primary load register The SI control circuit generates the count enable signals 2 8 3 4 SI Control The SI counter is controlled by a circuit whose state transitions are shown in Figure 2 50 The SI counter control circuit has two states WAIT1 and CNT1 On power up the control circuit begins in state WAIT1 and remains there until the counter is armed and a STARTI pulse is received When these two events occur the counter moves to the state and begins generating START signals internal START or begins counting the START holdoff external START On SC the required number of STARTS has been generated and the counter returns to the WAIT state The SI load signal SI LOAD enables the SI counter to reload from the selected load register on the next clock 51 LOAD is asserted when SI TC is reached or is asserted by software AI SI Load The SI count enable signal 51 CE allows the SI counter to count SI CE asserts any transition terminating at either the CNT1 or CNT2 state provided that the SI counter is armed AI SI Arm The SI disarm signal SI DISARM clears the SI Arm bit in the register map SI DISARM asserts on the transition from the CNT1 to the WAITI state when AI End On End Of Scan AI End On SC TC or AI Trigger Once is high DAQ STC Technical Reference Manual 2 126 N
130. and the selected reload mode Related bitfields Initial Load Source AO Next Load Source St AO BC Reload Mode BC SRC BC Source The BC source is the timebase for the buffer BC counter and update UC counter If an internally generated UPDATE is used the BC source is the same signal as the UI SRC If an externally generated UPDATE is used the UPDATE clock itself serves as the BC source The external trigger and gate inputs which are not generated synchronous to the BC source outside of the timer can and should be synchronized to the BC source inside of the timer DAQ STC Technical Reference Manual 3 110 National Instruments Corporation Chapter 3 Analog Output Timing Control Table 3 6 Internal Signals Continued Signal Description BC TC Buffer Repetition Counter TC This signal indicates the completion of an MISB DACUPDN DAC Update This signal appears on the UPDATE pin The hardware generates DACUPDN by passing the SCLK signal through pulsewidth and polarity selection circuitry If the UPDATE pin is configured for high impedance this signal will be GND Related bitfields AI UPDATE Output Select AI UPDATE Original Pulse AI UPDATE Pulse Timebase AI UPDATE Pulse Width STIED Output Version of START1 The hardware generates DA STIED by passing the output of the STARTI selector through polarity selection and edge detection but not synchronization
131. as a bidirectional CTRSRCO signal Related bitfields 8 Pin Dir PFI9 G GATEO B9TU PFI9 General Purpose Counter 0 Gate As an input this pin provides a signal path to the PFI selectors As an output this pin reflects the internal signal GATE from general purpose counter 0 Source Destination This pin is appropriate for use as a bidirectional CTRGATEO signal Related bitfields 9 Pin Dir 9 4 Programming Information This section presents programming information that is specific to the PFIs For general information about programming the DAQ STC see section 2 6 Programming Information 5 4 1 Programming the Pins This section contains detailed programming information for bit level programming of the PFI pins for specialized applications The DAQ STC has 10 bidirectional pins for user signals If a pin is programmed for input the PFI reflects the state of the external signal connected to the pin If a pin is programmed for output the PFI reflects the state of the internally generated signal that drives the pin The PFIs are commonly available for signal selection Use this function to configure the direction of one of the 10 PFI pins Function MSC IO Pin Configure switch pin number case 0 BD 0 Pin Dir 0 input or 1 output break case 1 BD 1 Pin Dir 0 input or 1 output break National Instruments Corporation 5 5 DAQ STC Technical Reference Manual Chapter 5
132. assignment must be performed first the second and third assignments may then be executed in any order but the fourth bitfield assignment must be executed after the second and third DAQ STC Technical Reference Manual 3 20 National Instruments Corporation Chapter 3 Analog Output Timing Control bitfield assignments Other programming constructs such as if then should be executed in the order shown FOUT_Enable 0 L FOUT_Timebase_Select 0 FOUT_IN_TIMEBASE or 1 TIMEBASE2 FOUT_Divider 0 for division factor 16 or 1 15 for division factor 1 15 L FOUT Enable 1 The directives Begin critical section and End critical section mark the beginning and end of critical sections in the ensuing pseudocode All statements under these directives must be synchronized with the interrupt service routines in other words while the code fragment under these directives is executing in the foreground all interrupt time specific code must be prevented from executing in the background Under some single tasking operating systems such as DOS the directives Begin critical section and End critical section directly map to CLI and STI instructions respectively However other operating systems may require specific primitives to achieve this functionality 3 6 1 1 Overview The DAQ STC has two groups of counters dedicated to analog output timing and control The primary group contains three counters and the secondary group contain
133. at high speeds and to increase bus bandwidth The data FIFO control signals support such a FIFO The SHIFTIN signal loads the result of each conversion into the data FIFO Three status flags indicate the amount of data stored in the FIFO and are monitored by the DAQ STC The three status flags are AIFFF AIFHF and AIFEF When the FIFO flags indicate that the FIFO level has exceeded a programmed threshold the DAQ STC notifies the host computer using either an interrupt request if the CPU performs data transfers or the DMA request signal AIFREQ if the DMA controller performs data transfers The host computer then transfers the input data stored in the data FIFO to main memory 2 4 1 3 Configuration FIFO and External Multiplexer Control Typical DAQ products provide a means of setting channel gain polarity and other configuration information for the A D subsystem Recent products offer the ability to change this information on a per conversion basis The DAQ STC fully supports a FIFO based configuration memory that can update on every CONVERT pulse Typically the configuration FIFO contains one data word for each input channel included in the scan At the National Instruments Corporation 2 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control end of the scan the FIFO read pointer is reset effectively reloading the FIFO with the configuration list The LOCALMUX signal which asserts at the same time as
134. bit 5 type Write in AO Personal Register address 78 If AO UPDATE Pulse Timebase is 0 this bit determines the pulsewidth of the UPDATE and PFIS UPDATE signals If AO UPDATE Pulse Timebase is 1 and AO UPDATE Original Pulse is 0 this bit determines the maximum pulsewidth of the UPDATE and PFIS UPDATE signals so that the pulsewidth is equal to the shorter of this pulsewidth and the original signal pulsewidth The pulsewidths are as follows 0 3 3 5 AO OUT TIMEBASE periods 1 1 1 5 AO OUT TIMEBASE periods UPDATE Second Enable bit 2 type Write in Second Enable Register address 76 This bit enables the UPDATE interrupt in the secondary interrupt bank 0 Disabled 1 Enabled UPDATE interrupts are generated on the trailing edge of UPDATE 0 UPDATE Source Polarity bit 4 type Write in AO Mode 1 Register address 38 This bit selects the active edge of the UPDATE source the signal that is selected by AO UPDATE Source Select 0 Rising edge Falling edge You must set this bit to 0 in the internal UPDATE mode Related bitfields AO UPDATE Source Select National Instruments Corporation 3 83 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 UPDATE Source Select bits lt 11 15 gt type Write in AO Mode 1 Register address 38 This bitfield selects the UPDATE source 0 The internal signal UI TC 1 10 PFI lt 0 9 gt 11 17 RTSI lt 0 gt 1
135. bit 7 type Read in Joint Status 2 Register address 29 This bit indicates whether a scan is currently in progress The bit is set when a valid START is received and the bit is cleared when a valid STOP is received SCAN IN PROG Output Select bits lt 8 9 gt type Write in AI Output Control Register address 60 This bitfield enables and selects the polarity of the SCAN IN PROG output signal 0 HighZ 1 Ground 2 Enable active low 3 Enable active high National Instruments Corporation 2 61 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control SCAN IN PROG Pulse bit 4 type Write in AI Command 1 Register address 8 Set this bitto 1 to begin a pulse on the SCAN PROG output signal if the output is enabled Set this bit to 0 to end the pulse Related bitfields AI SCAN IN PROG Output Select SC Arm bit 6 type Strobe AI Command 1 Register address 8 This bit arms the SC counter The counter remains armed and the bit remains set until it is disarmed either by hardware or by setting Disarm to 1 Related bitfields AI SC Arm St AI Disarm SC Armed St bit 0 type Read in AI Status 2 Register address 5 This bit indicates whether the SC counter is armed 0 Disarmed 1 Armed Related bitfields AI SC Arm SC Gate Enable bit 15 type Write in AI Mode 2 Register address 13 This bit enables the SC gate 0 Disabl
136. bitfield is load register A for the UC counter If load register A is the selected UC load register the UC counter loads the value contained in this bitfield on AO UC Load and on UC TC The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related bitfields AO UC Next Load Source St AO UC Load DAQ STC Technical Reference Manual 3 68 National Instruments Corporation Chapter 3 Analog Output Timing Control 0 UC Load B bits lt 0 7 gt type Write in AO UC Load B Registers address 50 bits lt 0 15 gt type Write in AO UC Load B Registers address 51 This bitfield is load register B for the UC counter If load register B is the selected UC load register the UC counter loads the value contained in this bitfield on UC Load and on UC The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related bitfields UC Next Load Source St AO UC Load 0 UC Next Load Source St bit 15 type Read in AO Status 2 Register address 6 This bit indicates the next load source of the UC counter 0 Load register A 1 Load register B UC 0 St bit 14 type Read in Joint Status 1 Register address 27 This bit reflects state of the UC control circuit 0 WAIT 1 CNT See section 3 8 Detailed Description for more information on the UC control circuit 0 UC Save St bit 7 type Read in AO Status 2 Register address
137. clear FIFO Condition To enable To select condition use To recognize National Instruments Corporation AI Error Interrupt Enable AI Overflow St and AI Overrun St AI Error Interrupt AI START Interrupt Enable AI START St AI START Interrupt AI STOP Interrupt Enable and AI START Interrupt Enable AI STOP St AI STOP Interrupt Ack AI STARTI Interrupt Enable AI STARTI St AI STARTI Interrupt Ack AI STARTO2 Interrupt Enable AI STARTO St AI STARTO2 Interrupt AI SC TC Interrupt Enable AI SC St AI SC TC Interrupt AI Interrupt Enable AI FIFO Mode AI FIFO Full St AI FIFO Half Full St and AI FIFO Empty St 2 47 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control To clear You must change the FIFO state by dealing with the FIFO All interrupts related to analog input are in interrupt group To select the interrupt line to be used Interrupt Output Select 0 through 7 Interrupt Enable 1 To determine quickly if any of the group A interrupts have occurred use Interrupt A St Notes To select interrupt output polarity use Interrupt Output Polarity This selection 2 6 9 depends on the board hardware design Pass Through 0 Interrupt is also in interrupt group A For more detailed information about the conditions that generate an interrupt refer to section 2 8 4 Interrupt Control Bitfield Descriptions Bits
138. counter and program the SI counter to use the external timebase of your choice This will work well in one of the following are not using SI at all or you are using SI and it uses the timebase you have selected here AI SI2 Source Select 0 same signal selected as SI source AI SI Source Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt AI SI Source Polarity 0 rising edge or 1 falling edge AI SI2 Load A number of clocks from START to the first CONVERT 1 AI 812 Initial Load Source 0 AI SI2 Load B number of clocks between two CONVERT signals within ascan 1 AI_SI2_Reload_Mode 1 alternate first period on every STOP L AI_SI2_Load 1 AI SI Initial Load Source 1 National Instruments Corporation 2 39 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Else AI SC Gate Enable 1 AI Start Stop Gate Enable 1 AI CONVERT Source Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI lt 0 6 gt or 19 OUT signal from general purpose counter 0 AI CONVERT Source Polarity 0 falling edge or 1 rising edge L AI Configuration End 1 End critical section Another feature the DAQ STC provides in the external CONVERT mode is SC GATE SC Counter Gate Similar to the STST_GATE the SC provides a mechanism for blocking the external CONVERT pulses If
139. counter 0 then Gj is denoting general purpose counter 1 if Gi is denoting general purpose counter 1 then Gj is denoting general purpose counter 0 4 6 1 3 Resetting Use this function to reset the GPCT Function Gi Reset 11 Gi_Reset 1 Gi Mode Register 0 Gi Command Register 0 Gi Input Select Register 0 Gi Autoincrement Register 0 Gi TC Interrupt Enable 0 Gi Gate Interrupt Enable 0 Gi Synchronized Gate 1 Gate Error Confirm 1 Gi TC Error Confirm 1 Gi TC Interrupt Ack 1 Gi Gate Interrupt 1 Autoincrement 0 4 6 1 4 Arming Use following function to arm the counter after the programming sequence is complete This function will cause the counter to begin the programmed operation Function Gi Arm 11 Gi_Arm 1 DAQ STC Technical Reference Manual 4 18 National Instruments Corporation Chapter 4 General Purpose Counter Timer 4 6 1 5 Simple Event Counting Simple event counting is an application in which a general purpose counter counts the edges of its source signal Progress of counting is observed by monitoring the counter contents which is achieved by using the software save command and a save register One variation of this application called simple gated event counting allows you to select a gate signal to pause and resume counting Note Simple event counting mimics the behavior of the NI DAQ functions for the 9513 counter c
140. counter TC signal 812 TC If a different source is selected for the SC counter CONVERT Source Select 15 not set to 0 SCKG 1 DAQ STC Technical Reference Manual 2 124 National Instruments Corporation Chapter 2 Analog Input Timing Control The SC load signal SC LOAD enables the SC counter to reload from the selected load register on the next clock SC LOAD asserts when SC TC is reached and TRANS is high or it is asserted by software 5 Load The SC count enable signal SC CE allows the SI counter to count SC CE asserts on any transition originating from or terminating at either of the PCNT or CNT states provided that the SC counter is armed SC Arm TRANS is high and EXT is enabled The SC disarm signal SC DISARM clears the 5 Arm bit in the register map SC DISARM asserts on the transition from the CNT state to WAITI state when either AI End On End Of Scan AI End On SC TC or AI Trigger Once is high START1 SC Arm START2 SC TC End On End Of Scan End On SC Al Continuous Pre Trigger TRANS Trigger Once H I J gt TRANS SCKG STOP SC LOAD GL SC Load LT o SCKG AI CONVERT Source Select 512 TC SC CE BL EXT GATE CNT n PCNT n 1 CNT n 1 SC DISARM CNT n WAIT n 1 H WAITI pe x PCNT ABK ABK Figure 2
141. define define define define define National Instruments Corporation Board_Base_Addr DAQ_STC_Base_Addr DAQ STC Window Address Reg DAQ STC Window Data Write Reg DAQ STC Window Data Read Reg DAQ STC DIO Output Register DAQ STC DIO Control Register STC DIO Outputs 7 7 0 280 0x00 Board Base Addr STC base address on the AT MIO E Series STC Base Addr 0x00 STC Base Addr 0x01 2 STC Base 0x01 2 OxOB OxFF DAQ STC Technical Reference Manual Chapter 7 Digital 1 0 main int port_val configure DIO lt 0 7 gt pins as outputs DAQ_STC_Windowed_Mode_Write DAQ_STC_DIO_Control_Register STC DIO Outputs for port val 0 port val 255 port val DAQ_STC_Windowed_Mode_Write DAQ_STC_DIO_Output_Register port_val port_val main functions to write and read from the DAQ STC in the windowed mode outp performs a 16 bit write and inp performs a 16 bit read STC Windowed Mode Write unsigned int addr int data outp DAQ_STC_Window_Address_Reg addr outp DAQ_STC_Window_Data_Write_Reg data DAQ_STC_Windowed_Mode_Read unsigned int addr int dataptr outp DAQ_STC_Window_Address_Reg addr inp DAQ_STC_Window_Data_Read_Reg amp dataptr Caution When using windowed mode accesses from interruptible process your application may no
142. divided by two AI CONVERT Pulse Timebase 0 pulsewidth is selected by AI CONVERT Pulse Width or pulse width is selected by AI CONVERT Original Pulse National Instruments Corporation 2 27 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control AI CONVERT Pulse Width 0 1 5 2 AI OUT TIMEBASE periods or 1 0 5 1 AI OUT TIMEBASE periods AI CONVERT Output Select 0 high Z or 1 ground or 2 enable active low or 3 enable active high AI FIFO Flags Polarity 0 active low or 1 active high AI LOCALMUXCLK Pulse Width 0 Retransmit 0 5 1 AI OUT TIMEBASE periods Read 1 5 2 AI OUT TIMEBASE periods or 1 Retransmit 0 5 AI output clock periods Read 0 5 1 OUT TIMEBASE periods AI AIFREQ Polarity 0 active high or 1 active low AI SC TC Output Select 0 high Z or 1 ground or 2 enable active low or 3 enable active high AI SHIFTIN Polarity 0 active low or 1 active high AI SHIFTIN Pulse Width 0 0 5 1 5 AI OUT TIMEBASE periods or 1 1 5 2 AI OUT TIMEBASE periods AI EOC Polarity 0 rising edge or 1 falling edge AI SOC Polarity 0 rising edge or 1 falling edge AI Overrun Mode 0 from SOC to EOC or 1 from SOC to the trailing edge of SHIFTIN AI SCAN PROG Output Select 0 high 2 or 1 ground or 2 enable active low or 3 enable active high AI LOCALMUX CLK Output Select 0 high Z or 1 ground or 2 enabl
143. each CONTROL pulse the counter reloads from the selected load register The HW save register switches to transparent mode on the rising edge of G_GATE and returns to latched mode on the next SOURCE falling edge Figure 4 39 shows an example of a buffered period measurement where the period is five SOURCE rising edges The dotted line indicates where the ARM occurs and the arrows indicate where the gate interrupt is generated G SOURCE eor i 4d 1 8 G CONTROL E Counter Load 1 ASA A2 4 B Counter Value 1 HW Save XX 3 5 HW Save Register Figure 4 39 Buffered Period Measurement DAQ STC Technical Reference Manual 4 78 National Instruments Corporation Chapter 4 General Purpose Counter Timer 4 8 11 9 Buffered Semiperiod Measurement To use this function set G CONTROL conditioning to edge gating double edge and program the counter to reload on CONTROL and generate interrupts on G_GATE The counter increments on every SOURCE rising edge following the ARM Every transition is synchronized by the falling edge of G SOURCE to generate a G CONTROL pulse On the SOURCE rising edge following CONTROL the counter reloads from the selected load register The HW save register switches to transparent mode on every edge of
144. each functional group in the DAQ STC as shown in Figure 1 3 DAQ STC Block Diagram Text in this font denotes text or characters that you should literally enter from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and for statements and comments taken from programs National Instruments Corporation XXV DAQ STC Technical Reference Manual About This Manual National Instruments Documentation The DAQ STC Technical Reference Manual is one piece of the documentation set for your data acquisition system You could have any of several types of manuals depending on the hardware and software in your system Use the manuals you have as follows Getting Started with SCXI If you are using SCXI this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software Your SCX hardware user manuals If you are using SCXI read these manuals next for detailed information about signal connections and module configuration They also explain in greater detail how the module works and contain application hints Your DAQ hardware user manuals These manuals have detailed information about the DAQ hardware that plugs into or is connec
145. edge gating and program the counter to reload on TC The rising edge of GATE is synchronized by the falling edge of SOURCE to generate a CONTROL pulse The counter begins decrementing after the G CONTROL pulse Whenever counter TC is reached the counter reloads and counts down to TC again The load select signal indicates whether the reload occurs from load register A or B Figure 4 45 shows an example of continuous pulse train generation with a pulse interval of four and a pulsewidth of three The dotted line indicates where the ARM occurs G SOURCE _ GcArE G_CONTROL Load Select Counter Load AAA AO X2 A1 A0 A8 A2 X1 XOX2 A1 AOAS A2 Counter Value Counter TC G OUT Figure 4 45 Continuous Pulse Train Generation DAQ STC Technical Reference Manual 4 84 National Instruments Corporation Chapter 4 General Purpose Counter Timer 4 8 11 15 Buffered Pulse Train Generation To use this function set G CONTROL conditioning to edge gating and program the counter to reload on TC and generate interrupts on TC The rising edge of is synchronized by the falling edge of SOURCE to generate CONTROL pulse The counter begins decrementing after the CONTROL pulse Whenever counter TC is r
146. features Update interval timing 24 bit update interval down counter Maximum update rate of 1 6 MHz on two output channels Maximum frequency of 20 MHz yields 50 ns resolution with a maximum interval of 0 83 s Divide by two timebase yields 100 ns resolution with a maximum interval of 1 67 s Divide by 200 timebase yields 10 us resolution with a maximum interval of 167 s Secondary update interval 16 bit counter with independent timebase selection for a secondary update group that is primarily interrupt driven External timing available for the following signals STARTI UPDATE Ulsource UD source Secondary external gate Bidirectional external timing pins Input clock sources and triggers from PFI 0 9 and RTSI lt 0 6 gt A Output the internally generated update and trigger signals to the board Programmable polarities for external UPDATE and external STARTI input Synchronously change the update interval DAQ STC Technical Reference Manual 3 2 National Instruments Corporation Chapter 3 Analog Output Timing Control e Update count 24 bit update down counter Trigger up to 224 pulses or generate updates continuously e Buffer repetition count 24 bit buffer repetition down counter Mute buffers Programmable delays between waveforms e Number of channels Upto 16 channels Higher channel count possible with external hardware e Trig
147. frequency Function Frequency Shift Keying Gi_Load_Source_Select 0 Gi_Load_A delay from software arm to first edge of pulse 1 Gi_Load 1 L Gi_Load_A pulse interval for inactive gate 1 Gi_Load_B pulsewidth for inactive gate 1 Gi_Load_Source_Select 1 Gi_Bank_Switch_Enable 1 Gi_Load_A pulse interval for active gate 1 Gi_Load_B pulsewidth for active gate 1 Gi Source Select 0 G 5 or 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 IN TIMEBASE2 or 19 other TC Gi Source Polarity 0 count rising edges or 1 count falling edges Gi Gate Select through 10 PFI lt 0 9 gt or 11 through 17 RTSI lt 0 6 gt or 18 AI START2 19 UI2 TC or 20 other TC 21 AI START or 31 logic low OR Gate 0 Gi Output Polarity 0 active low or 1 active high Gate Select Load Source 1 Gi Gate Polarity 0 disable inversion or 1 enable inversion Gi Output Mode 1 one clock cycle output or 2 toggle on TC or 3 toggle on TC or gate Gi Reload Source Switching 1 Gi Loading On Gate 0 Gi Loading On 1 Gi Gating Mode 1 Gi Gate On Both Edges 0 Gi Trigger Mode For Edge Gate 3 Gi Stop Mode 0 Gi Counting Once 0 Gi Up Down 0 Gi Bank Switch Enable 1 Gi Bank Switch Mode 0 Gi TC Interrupt Enable 0 Gi Gate Interrupt Enabl
148. frequency shift keying figure 4 15 pulse generation for ETS figure 4 15 retriggerable single pulse generation 4 11 simplified general purpose counter timer model 4 3 single pulse generation 4 10 single triggered pulse generation 4 10 OUTO RTSI IO signal table 4 16 G OUTI DIV TC OUT signal table 4 16 Source Divide 2 bit 4 52 G SOURCE signal buffered cumulative event counting 4 5 buffered noncumulative event counting 4 5 buffered period measurement 4 7 to 4 8 buffered pulse train generation 4 14 buffered pulsewidth measurement 4 9 buffered retriggerable single pulse generation 4 11 to 4 12 buffered semiperiod measurement 4 8 buffered static pulse train generation 4 13 continuous pulse train generation 4 12 to 4 13 relative position sensing 4 6 DAQ STC Technical Reference Manual Index retriggerable single pulse generation 4 11 simple event counting 4 4 simple gated event counting 4 4 simplified general purpose counter timer model 4 2 to 4 3 single pulse generation 4 9 to 4 10 single triggered pulse generation 4 10 single period measurement 4 6 to 4 7 single pulsewidth measurement 4 7 UP DOWN ZO 1 signal description table 4 16 relative position sensing 4 6 gating free run gating mode external gate timing external CONVERT figure 2 110 external gate timing internal CONVERT figure 2 109 theory of operation 2 17 halt gating mode external gate timing internal
149. gt inputs In order to preserve the concept of interval scanning with an external CONVERT the STST GATE Start Stop Gate is available The START trigger enables the STST GATE and the STOP trigger disables the STST GATE External CONVERT pulses that occur when the STST is enabled pass through the DAQ STC External CONVERT pulses that occur when the STST is disabled are blocked Timing for the external CONVERT can be arbitrarily complex depending on the behavior of the signal you select as the external CONVERT source Typically though you will select a periodic signal in which case the only timing parameter available is the delay between CONVERT pulses The delay from START to the first CONVERT depends on the relationship between the START trigger and the external CONVERT and can vary Figure 2 7 shows two scans with four externally timed CONVERT pulses each and indicates how the delay from START to the first CONVERT can vary The SCAN IN PROG output asserts on the recognition of START and deasserts on STOP DAQ STC Technical Reference Manual 2 10 National Instruments Corporation Chapter 2 Analog Input Timing Control STOP External CONVERT 1 START EL STST GATE SCAN IN PROG CONVERT Figure 2 7 External CONVERT Timing Although succe
150. hold Generates the track and hold signal National Instruments Corporation 2 3 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 2 3 Simplified Model The AITM contains the hardware necessary to generate timing and control signals for the ADC and the associated circuitry on a National Instruments DAQ board such as an MIO board Figure 2 1 shows the timing and control signals used in a typical analog input operation START1 START 1 y STOP CONVERT Figure 2 1 Typical Analog Input Waveform The primary analog input timing signal is the CONVERT pulse which instructs the ADC to begin a conversion on the selected analog input channel CONVERT pulses are organized into groups called scans In each scan the CONVERT signal pulses once for each input channel The purpose of the scan grouping is to sample multiple input channels nearly simultaneously Each scan begins with a START pulse and ends with a STOP pulse The START trigger begins the acquisition sequence Figure 2 1 above depicts an acquisition consisting of three scans with each scan sampling four input channels DAQ STC Technical Reference Manual 2 4 National Instruments Corporation Chapter 2 Analog Input Timing Control Figure 2 2 shows a simplified model of the AITM module l2 START COUNTER lt 0 9 gt gt RTSI_TRIGGER lt 0 6
151. in AI Mode 2 Register address 13 This bit selects the reload mode for the SC counter 0 No automatic change of the SC load register 1 The SC counter will switch load registers on every SC You can use setting 1 for pretrigger acquisition mode and for staged analog input SC Save St bit 2 type Read in AI Status 2 Register address 5 This bit indicates the status of the SC save register 0 SC save register is tracing the counter 1 SC save register is latched for later read Related bitfields AI SC Save Trace SC Save Trace bit 10 type Write in AI Command 2 Register address 4 Setting this bit to 1 causes the SC save register to latch the SC counter value at the next SC CLK falling edge Setting this bit to 0 causes the SC save register to trace the SC counter SC Save Value bits lt 0 7 gt type Read in AI SC Save Registers address 66 bits lt 0 15 gt type Read in AI SC Save Registers address 67 When SC Save Trace is 0 this bitfield reflects the contents of the SC counter When you set AI SC Save Traceto 1 this bitfield synchronously latches the contents of the SC counter using the SC source The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related bitfields SC Save Trace DAQ STC Technical Reference Manual 2 64 National Instruments Corporation Chapter 2 Analog Input Timing Control SC Switch Load On TC bit 4 ty
152. in which a group of channels is sampled at one rate and the sampling of channels within a group occurs at another rate The timing for this mode is shown in Figure 2 41 OSC lt gt Tstist START1 Ttcst2 START2 T gt lt stc stpst gt stst START 9 Istpc Tst2stp STOP 4 4 CONVERT SC TC Figure 2 41 Interval Scanning Mode Timing DAQ STC Technical Reference Manual 2 106 National Instruments Corporation Chapter 2 Table 2 8 Interval Scanning Mode Timing Analog Input Timing Control External Minimum in Maximum in Name Description Control Clock Periods Clock Periods Tstlst STARTI to START 0 1 1 224 1 274 1 Tstst START to START 2 2 1 224 1 224 1 Tstc START to CONVERT 0 1 1 224 224 1 Tcc CONVERT to CONVERT 2 2 1 216 216 1 Tstpc STOP to CONVERT 0 0 Tstpst STOP to START 0 0 Ttcst2 SC TC to START2 1 1 Tst2stp START2 to STOP 1 1 1 22 274 1 The numbers in parentheses are actual numbers to load into on chip counters to achieve the desired delay Table 2 8 shows the minimum number of clock periods that must occur between re
153. information that is specific to the four miscellaneous functions described in this chapter For general information about programming the DAQ STC see section 2 6 Programming Information 10 8 1 Programming Clock Distribution You must supply the DAQ STC with an external frequency source if you want to use any of the functions that depend directly on an internal timebase Three pins on the DAQ STC are provided for I O of this important signal the pins are listed and described in section 10 3 Clock Distribution IN TIMEBASE can be selected from two sources OSC or RTSI_OSC If the OSC pin is the IN TIMEBASE source the RTSI OSC pin can be used as the IN TIMEBASE signal output The IN TIMEBASE signal unmodified or divided down by 2 can be fed to the board by DAQ STC Technical Reference Manual 10 10 National Instruments Corporation Chapter 10 Miscellaneous Functions using the OUTBRD OSC pin Boards can use the output of the OUTBRD_OSC pin if a clock synchronous to the one used by the DAQ STC is needed Motivation for the three pins is master slave operation of boards connected by a RTSI bus To connect several boards in master slave fashion you should not have DAQ STCs on different boards use different oscillator frequencies as clocks because the oscillators will not be synchronized To accommodate the master slave operation program the DAQ STCs on the slave boards to input their clock from the RTSI OSC pins Program the DAQ STC on
154. input is typically fed from an analog comparator on the board National Instruments Corporation 10 9 DAQ STC Technical Reference Manual Chapter 10 Miscellaneous Functions Table 10 3 Pin Interface Continued Pin Name Type Description FOUT O9TU Frequency Output This pin is the frequency divided output Clock division rations from 1 to 16 are possible from FOUT_TIMEBASE Related bitfields FOUT_Enable FOUT_Divider FOUT_Timebase_Select OSC IS Oscillator Source OSC is a TTL compatible clock signal input that is the primary timing source for the DAQ STC Maximum frequency is 20 MHz Related bitfield RTSI_Clock_Mode OUTBRD_OSC O9TU Oscillator Source for Output to the Board This signal is an output to the board and is either RTSI_OSC or OSC depending on whether the internal clock used is OSC or RTSI OSC A divide by two version of the selected signal can also be output Related bitfields Clock Board RTSI Clock Mode Clock To Board Divide By 2 TEST IN 105 Test Input This pin invokes test mode which tri states all the output signals except TEST It is normally used only for in circuit testing During normal operation the pin should be tied to VDD Related bitfield Software Test TEST OUT 09 Text Output This pin is used for in circuit testing 10 8 Programming Information This section presents programming
155. input signal indicates end of conversion 0 Rising edge Falling edge Related bitfields AI EOC St AI EOC St bit 4 type Read in Joint Status 2 Register address 29 This bit indicates the state of the EOC pin after the polarity selection This bit is useful for device diagnostic applications Related bitfields EOC Polarity AI Error bit 13 type Strobe Interrupt Ack Register address 2 Setting this bit to 1 clears Overflow St and AI Overrun St and acknowledges the Error interrupt request in either interrupt bank if the Error interrupt is enabled This bit is cleared automatically Related bitfields Overflow St Overrun St AI Error Interrupt Enable AI Error Interrupt Enable bit 5 type Write in Interrupt Enable Register address 73 This bit enables the Error interrupt 0 Disabled Enabled The Error interrupt is generated on the detection of an overrun or overflow error condition Error Second Enable bit 5 type Write in Second Irq A Enable Register address 74 This bit enables the Error interrupt in the secondary interrupt bank 0 Disabled 1 Enabled The Error interrupt is generated on the detection of an overrun or overflow error condition DAQ STC Technical Reference Manual 2 54 National Instruments Corporation Chapter 2 Analog Input Timing Control External Gate Mode bit 8 type Write in AI Mode 3 Regi
156. interrupt set AO_Error_Interrupt_Ack 1 enable this interrupt set AO Error Interrupt Enable 1 Else if Soft Copy AO STOP Interrupt Enable is 1 then If AO STOP 5115 1 then The interrupt was caused by AO STOP signal Service the AO STOP interrupt To clear this interrupt set AO STOP Interrupt Ack 1 enable this interrupt set STOP Interrupt Enable 1 This interrupt is not supported Else if Soft Copy AO START Interrupt Enable is 1 then If AO START St is 1 then National Instruments Corporation 6 11 DAQ STC Technical Reference Manual Chapter 8 Interrupt Control The interrupt was caused by AO START signal Service the AO START interrupt To clear this interrupt set AO_START_Interrupt_Ack 1 To enable this interrupt set AO START Interrupt Enable 1 This interrupt is not supported Else done_b 1 The functions presented in this section can always be used However you can also consider them to be only examples If your application uses fewer than the full number of interrupts listed here your interrupt service programs will be more efficient if you omit appropriate parts of the code You can also improve performance by modifying the order of evaluation of interrupt causing conditions You will often be able to take advantage of your knowledge of the application to write interrupt service programs that are fine tuned to the particular
157. load register A for the SC counter If load register A is the selected SC load register the SC counter loads the value contained in this bitfield on SC Load and on SC TC The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related Bitfields AI SC Next Load Source St AI SC Load SC Load B bits lt 0 7 gt type Write in AI SC Load B Registers address 20 bits lt 0 15 gt type Write in AI SC Load B Registers address 21 This bitfield is load register B for the SC counter If load register B is the selected SC load register the SC counter loads the value contained in this bitfield on SC Load and on SC TC The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related Bitfields AI SC Next Load Source St AI SC Load SC Next Load Source St bit 1 type Read in AI Status 2 Register address 5 This bit indicates the next load source of the SC counter 0 Load register A 1 Load register B National Instruments Corporation 2 63 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control AI SC 0 St bits lt 3 4 gt type Read in AI Status 2 Register address 5 This bitfield reflects the state of the SC control circuit 0 WAIT 1 1 PCNT 2 WAIT 2 3 CNT See section 2 8 Detailed Description for more information on the SC control circuit SC Reload Mode bit 1 type Write
158. mute If shut down isr is 2 then AO UC Load B old stage uc 1 1 last load register National Instruments Corporation 3 33 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control ao tick count to tick count to 1 AO BC TC Interrupt ack 1 If ao shut down 2 then Check for error between the last BC_TC of one stage and the trigger for the next stage If AO_BC_TC_Trigger_Error_St is 1 then Inform user that a BC_TC trigger error has occurred AO_BC_TC_Trigger_Error_Confirm 1 This is optional If AO_BC_TC_Error_St is 1 then Inform user that a BC_TC error has occurred You need to reprogram analog output circuitry to get things back on track 3 6 3 Changing Update Rate during an Output Operation for Primary Analog Output Group Use this function to change the update rate during an output operation if you are not performing waveform staging The variable 1ast load register keeps track of which load registers should be used This variable was first introduced in the Counting function Function AO Rate Change Begin critical section If ao_last_load_register is A If AO_UI_Next_Load_Source_St is 0 then AO_UI_Load_B number of clocks between updates 1 If change update rate immediately then AO_UI_Switch_Load_On_TC 1 Else if change update rate a
159. not empty Selection 3 will cause the request and FIFO interrupt to assert at the end of the acquisition and remain asserted until the FIFO empties provided that SHIFTIN arrives after the trailing edge of the last SC TC The SHIFTIN signal may arrive before the trailing edge of the last SC TC if an internal CONVERT is used and the SI2 clock is slow with respect to the ADC interval In this case you should use the SC TC interrupt to initiate the final FIFO read at the end at the acquisition Related bitfields FIFO Interrupt Enable AI FIFO Second Enable Al FIFO Request St bit 1 type Read in AI Status 1 Register address 2 This bit indicates the status of the DMA request output pin AIFREQ and the FIFO interrupt 0 Not asserted 1 Asserted AI FIFO Mode selects the condition on which to generate the DMA request and FIFO interrupt Related bitfields AI Mode DAQ STC Technical Reference Manual 2 56 National Instruments Corporation Chapter 2 Analog Input Timing Control Al FIFO Second Enable bit 7 type Write in Second Enable Register address 74 This bit enables the FIFO interrupt in the secondary interrupt bank 0 Disabled 1 Enabled The FIFO interrupt is generated on the FIFO condition indicated by AI FIFO Mode Related bitfields AI FIFO Mode AI Last Shiftin St bit 15 type Read in Joint Status 1 Register address 27 This bit indicates that the last SHIFTIN of the acquisi
160. of clocks between updates The variable ao2_last_load_register introduced in this function will be used later in the waveform staging AO2_Staged_ISR and change update rate during an output operation A02 Rate Change DAQ STC Technical Reference Manual 3 40 National Instruments Corporation Chapter 3 Analog Output Timing Control Function 02 Updating Begin critical section Declare variable ao2_last_load_register Indicates the load register that was used previously AO_UI2_Source_Select 0 5 or 1 through 10 9 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 the G_TC signal from general purpose counter 0 or 1 9 the G_TC signal from general purpose counter 1 or 20 IN TIMEBASE2 AO UD Source Polarity 0 rising edge or 1 falling edge AO UD Initial Load Source A AO UD Load A number of clocks between each update 1 AO UD 1 If waveform staging then AO UD Load ui2_ticks 0 1 AO UD Switch Load Next TC 1 ao2 last load register B Else ao2_last_load_register A End critical section 3 6 6 8 Arming Use this function to arm the UI2 counter Function AO2_Arming Begin critical section AO_UI2_Arm_Disarm 1 End critical section 3 6 6 9 Secondary Analog Output Program Use this sequence of functions to program the AOTM for any secondary analog output operation Refer to section 10 8 1 Program
161. one UPDATE pulse is required for all DACs therefore the total throughput increases as the number of channels used increases This is shown in Figure 3 22 where three channels are being written UPDATE SRC K Z VY N SVS NN N N N N NN WSN Tcupd Tcupd Toup Toup UPDATE OUT BA gt Tctwr P gt Tctwr Tcwr Twr Twr Twr TMRDACWR Ej 67 N 7 Name Description Minimum Maximum Tcup UPDATE_SRC to UPDATE asserted 18 56 Toup UPDATE OUT pulsewidth 1 3 1 5 3 5 Tcupd OUT_CLK to UPDATE OUT deasserted 12 38 Tctwr OUT CLK to TMRDACWR asserted 11 34 Twr TMRDACWR pulsewidth 2 3 2 3 timing values are nanoseconds National Instruments Corporation Figure 3 22 Maximum Update Rate Timing The numbers in parentheses indicate the number of clock periods that occur at the minimum and maximum delays because those parameters are clock edge driven with possible additional gate delays The highest throughput for analog output occurs when back to back updates are programmed via the counter timer In the above example the shortest pulsewidths for each signal have been selected The UPDATE pulse is one output clock period long while each TMRDACWR signal is two output clock periods long The first TMRDACWR pulse occurs one output clock period after the UPDATE pulse and there is one output clock period between each successi
162. operation 2 123 trigger output 2 103 to 2 104 asynchronous mode figure 2 104 synchronous mode figure 2 104 trigger routing logic figure 2 120 National Instruments Corporation STST GATE signal description table 2 119 external CONVERT mode 2 10 to 2 11 synchronization trigger selection and conditioning analog input timing control module 2 122 analog output timing control module 3 116 T technical support E 1 to E 2 telephone and fax support numbers E 2 TEST signal table 10 10 test mode 10 6 to 10 9 checking input pin connectivity 10 7 input pin pairs table 10 8 to 10 9 internal gate tree structure figure 10 7 testing RESET pin 10 8 TEST OUT signal table 10 10 time measurement functions 4 6 to 4 9 buffered period measurement 4 7 to 4 8 buffered pulsewidth measurement 4 9 buffered semiperiod measurement 4 8 single period measurement 4 6 to 4 7 single pulsewidth measurement 4 7 timebases derived from IN TIMEBASE table 10 2 to 10 3 timing diagrams analog input timing control module 2 84 to 2 111 basic analog input timing 2 86 to 2 87 configuration memory 2 89 to 2 01 CONVERT SRC signal 2 84 to 2 85 data FIFOs 2 88 external CONVERT source 2 92 to 2 93 external triggers 2 03 to 2 97 National Instruments Corporation 1 37 maximum rate analog input 2 9 to 2 02 OUT signal 2 85 SCAN IN PROG deassertion 2 103 signal definitions 2 84
163. reflects the internal signal GATE from general purpose counter 1 Source Destination This pin is appropriate for use as a bidirectional CTRGATE signal Related bitfields 4 Pin Dir PFIS UPDATE B9TU PFI5 Primary Update from Analog Output As an input this pin provides a signal path to the PFI selectors As an output this pin reflects the internal AO signal DACUPDN the update signal from the analog output section Source Destination This pin is appropriate for use as a bidirectional EXTDACUPDATE signal Related bitfields BD 5 Pin Dir National Instruments Corporation 5 8 DAQ STC Technical Reference Manual Chapter 5 Programmable Function Inputs Table 5 1 Pin Interface Continued Pin Name Type Description PFI6 AO STARTI B9TU PFI6 START1 Trigger from Analog Output As an input this pin provides a signal path to the PFI selectors As an output this pin reflects the state of the active high internal AO signal STARTI The hardware generates PFI6 AO STARTI as follows If AO Trigger Length is 0 this pin reflects the internal AO signal DA STARTI If AO Trigger Length is 1 this pin reflects the internal AO signal DA_STIED after it has been pulse stretched to be 1 2 AO OUT TIMEBASE periods long Source Destination This pin is appropriate for use as a bidirectional EXTWFTRIG signal Related bitfields BD 6 Pin Dir AO Trigger Length PFI7 AI START B9T
164. selection circuits 0 Same as UI2 TC 1 Toggle on every UD TC Related bitfields Gate Select 0 UPDATE2 Pulse bit 1 type Strobe AO Command 2 Register address 5 Setting this bit to 1 produces a pulse on the UPDATE2 output signal if the output is enabled and if UPDATE2 pulses are not blocked UPDATE2 pulses can be blocked by the secondary external gate or by AO UD2 Software Gate The pulsewidth of the output signal is determined by UPDATE2 Pulse Width This bit is cleared automatically Related bitfields AO UI2 Software Gate AO UPDATE2 Pulse Width DAQ STC Technical Reference Manual 3 80 National Instruments Corporation Chapter 3 Analog Output Timing Control 0 UPDATE2 Pulse Timebase bit 1 type Write in AO Personal Register address 78 This bit determines how the pulsewidth of the UPDATE2 output signal is selected 0 Selected by AO UPDATE2 Pulse Width 1 Selected by AO UPDATE2 Original Pulse This bit is cleared automatically Related bitfields UI2 Pulse Width AO UD Original Pulse 0 UPDATE2 Pulse Width bit 0 type Write in AO Personal Register address 78 If AO UPDATE2 Pulse Timebase is 0 this bit determines the pulsewidth of the UPDATE2 signal If AO UPDATE2 Pulse Timebase is 1 and AO UPDATE2 Original Pulse is 0 this bitfield setting determines the maximal pulsewidth of the UPDATE2 signal so that the pulsewidth is equal to the shorter of this pulsewidth and the original sig
165. selects the output source for the OUTO RTSI IO bidirectional pin if the pin is configured for output 0 General purpose counter 0 output OUT 1 7 Signal from the RTSI trigger line lt 0 6 gt Related bitfields GPFO 0 OUTPUT Enable GPFO 1 Output Enable bit 15 type Write in Analog Trigger Etc Register address 61 This bit enables the OUTI DIV TC OUT output signal 0 Disabled 1 Enabled GPFO 1 Output Select bit 7 type Write in Analog Trigger Etc Register address 61 This bit selects the output source for OUTI DIV TC OUT output signal if enabled for output 0 General purpose counter output OUT 1 The internal analog input signal DIV TC Related bitfields GPFO 1 OUTPUT Enable G Source Divide By 2 bit 10 type Write in Clock and FOUT Register address 56 This bit determines the frequency of the internal timebase IN TIMEBASE 0 Sameas IN TIMEBASE 1 TIMEBASE divided by 2 DAQ STC Technical Reference Manual 4 52 National Instruments Corporation Chapter 4 General Purpose Counter Timer 4 7 Timing Diagrams All timing in this section refers to timing between pins Since many of the timing parameters are defined based on internal signals and the internal signals can be selected from a variety of sources it is convenient to define some global signals that can refer to any one of a number of pins depending on the internal signal selection Some of the tables in th
166. source clock period The LOCALMUX_CLK signal reads the next word of data from the configuration memory and is asserted by the CONVERT signal When an external multiplexer is being used the LOCALMUX_CLK signal can be programmed to occur every n conversions allowing a single data word in the configuration memory to be applied to multiple external channels The EXTMUX_CLK increments the external multiplexer and is generated once for every CONVERT pulse The DIV counter is used to count the CONVERT pulses and allows the LOCALMUX CLK signal to be generated during the DIV TC National Instruments Corporation 2 89 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control The actual signal timing parameters remain the same whether or not the DIV counter is being used The EXTSTROBE signal is intended to be used in conjunction with the digital I O lines to write data to an external multiplexer but can be used as a general strobe signal Table 2 4 Configuration Memory Timing Name Description Minimum Maximum Tcconv OUT CLK to CONVERT asserted 19 58 Tsconv CONVERT pulsewidth 1 1 Tmx LOCALMUX CLK pulsewidth 0 5 1 5 1 2 Texmx EXTMUX CLK pulsewidth 4 5 4 5 Tsocmx SOC to LOCALMUX CLK deasserted 9 26 Toscmx OUT CLK to LOCALMUX CLK 13 40 deasserted CONVERT to _ asserted 3 8 Tmxexmx LOCALMUX CLK to EXTMUX CLK 1 1 5 asserted Toscexmx Minimum EXTMUX CLK from
167. source is selected to be SI2 TC inverted The reference pin is determined by SI2 Source Select If AI SI2 Source Select is 0 the reference pin is determined by AI SI Source Select If AI SI2 Source Select is 1 the reference pin is OSC or RTSI depending on which clock mode you choose in RTSI Clock Mode 1 10 PFI lt 0 9 gt DAQ STC Technical Reference Manual 2 84 National Instruments Corporation Chapter 2 Analog Input Timing Control Table 2 2 CONVERT SRC Reference Pin Selection Continued AI CONVERT Source Select Reference Pin 11 17 RTSI lt 0 6 gt 19 The CONVERT source is selected to be the output of general purpose counter 0 The reference is determined by the GO Source Select bitfield To determine delays for this case add the source to output delay Tso from general purpose counter 0 2 7 1 2 OUT CLK OUT CLK is the AI OUT TIMEBASE signal which can come from the OSC input or the RTSI OSC input respectively depending on which clock mode you choose in RTSI Clock Mode If the output clock is set for divide by two operation each edge of OUT CLK represents a rising edge of OSC or RTSI OSC Otherwise OUT CLK and OSC or RTSI_OSC are identical National Instruments Corporation 2 85 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 2 7 2 Basic Analog Input Timing The basic analog input functionality provided
168. the SC TC SI TC DIV TC outputs 2 7 9 1 SC TC Figure 2 38 shows the delays associated with the 5 TC signal In internal CONVERT mode the SC source is OSC In external CONVERT mode the SC source is a delayed version of the external CONVERT source For this reason SC TC has additional delay in external CONVERT mode SCSouce VL Tsc Tsc SC TC N _ Name Description Minimum Maximum Tsc SC Source to SC TC internal CONVERT 16 51 Tsc SC Source to SC TC external CONVERT 26 87 timing values are in nanoseconds Figure 2 38 SC TC Delay 2 7 9 2 SI TC Figure 2 39 shows the delays associated with the SI TC signal SI Source 22 URL Dom Name Description Minimum Maximum Tsi SI Source to SI TC 13 42 timing values are in nanoseconds SI TC Figure 2 39 SI TC Delay National Instruments Corporation 2 105 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 2 7 9 3 DIV TC Figure 2 40 shows the delays associated with the DIV TC signal DIV Source Tdiv Tdiv Name Description Minimum Maximum Tdiv DIV Source to DIV_TC 15 48 All timing values are in nanoseconds DIV_TC Figure 2 40 DIV_TC Delay 2 7 10 Macro Level Analog Input Timing The interval scanning mode provides pseudosimultaneous operation
169. the internal signal AD START after it has been pulse stretched to be 1 2 AI OUT TIMEBASE periods long If AI START Output Select is 1 this pin will output the same signal as SCAN PROG National Instruments Corporation 6 7 DAQ STC Technical Reference Manual Digital 1 0 1 1 Overview This chapter describes the digital I O DIO module and explains how to use it on the DAQ STC The DIO module contains eight high current bidirectional digital I O lines and serial I O shift registers The EXTSTROBE SDCLK signal serves as the shift clock in the serial mode Eight additional output lines CTRL lt 0 7 gt are provided for use as a board level control register Four additional lines STATUS lt 0 3 gt are provided for use as a board level status register 1 2 Features The DIO module has the following features Eight individually programmable bidirectional lines 24 mA sink current 13 mA source current e Serial I O support for SCXI serial link on digital I O lines e Control and Status Registers 8 output lines for use as a board level control register 4 lines for use as a board status register 7 3 Simplified Model The DIO module contains the hardware necessary to perform serial and parallel digital I O as well as support for a status and control register interface Figure 7 1 shows a simplified model of the DIO module National Instruments Corporation 7 1 DAQ STC Technical R
170. the next counting interval An interrupt notifies the CPU after each counting interval so that the interrupt software can read the result from the HW save register Figure 4 4 shows buffered noncumulative event counting with two counting intervals Three events are counted in each of the two counting intervals Software Arm G GATE G SOURCE Counter Value 0 HW Save Register X Figure 4 4 Buffered Noncumulative Event Counting 4 4 1 4 Buffered Cumulative Event Counting Buffered cumulative event counting is similar to simple event counting except that the GATE signal indicates when to save the counter value to the HW save register The active edge latches the count value into the HW save register Counting continues uninterrupted regardless of the G_GATE activity An interrupt notifies the CPU after each active G_GATE edge so that the interrupt software can read the result from the HW save register Figure 4 5 shows cumulative event counting where the gate action causes the HW save register to save the counter contents twice Software Arm G_GATE G SOURCE Counter Value 0 1 2 3 4 5 6 7 3 Oo HW Save Register X Figure 4 5 Cumulative Event Counting National Instruments Corporation 4 5 DAQ STC Technical Reference Manual
171. the secondary interrupt bank 0 Disabled 1 Enabled The FIFO interrupt is generated on the FIFO condition indicated by AO FIFO Mode Related bitfields FIFO Mode National Instruments Corporation 3 57 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control Interval Buffer Mode bit 3 type Write in AO Personal Register address 78 This bit enables the insertion of a delay between two buffers 0 Disabled 1 Enabled This bitfield is currently not supported and it must be set to 0 0 LDACi Source Select i 0 bit 1 type Write in AO Command 1 Register address 9 i i bit 3 type Write in AO Command 1 Register address 9 If AO DACi Update Mode is 1 this bit determines the output signal for the pin LDACi 0 LDACi will output UPDATE 1 LDACi will output UPDATE2 Related bitfields AO DACi Update Mode 0 Multiple Channels bit 5 type Write in AO Mode 1 Register address 38 This bit enables multiple output channel support 0 Disabled 1 Enabled Related bitfields AO Number Of Channels 0 Mute bit 2 type Write in AO Command 2 Register address 5 This bit determines whether the programmed buffer is a mute buffer 0 Normal buffer 1 Mute buffer Set this bitto O if you want UPDATE and related signals to be generated while the BC counter is using load register A as the active load register Set this bitto 1 if you want the DAQ STC to suppress UPDATE and
172. to the LOCALMUX signal In the second option the trailing edge of LOCALMUX is latched and after one falling and one rising edge of the output clock EXTMUX CLK is asserted EXTMUX CLK is then held for 4 5 clock periods refer to AI EXTMUX CLK Pulse Width The input signal MUXFEF indicates that the configuration memory has been emptied and should be reset The LOCALMUX FFRT signal is asserted on the trailing edge of the LOCALMUX CLK signal and is deasserted after one or two output clock edges Notice that both the LOCALMUX_CLK and LOCALMUX_FFRT signals are controlled by AI LOCALMUX CLK Pulse Width therefore they will both be at either their shortest or longest settings The EXTSTROBE signal has two modes of operation It can be either a string of eight 1 2 or 10 us pulses or a software toggle Maximum Rate Analog Input When running the analog input at its maximum conversion rate the LOCALMUX CLK and LOCALMUX signals should be programmed to their shortest pulsewidths for correct operation as shown in Figure 2 19 This diagram also shows that the maximum conversion rate is equal to one half the output clock rate Up to 10 MS s is achievable with a 20 MHz oscillator and up to 5 MS s is achievable with a 10 MHz oscillator National Instruments Corporation 2 91 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control OUT CLK X N
173. to the miscellaneous functions Not all bitfields referred to in section 10 8 Programming Information are listed here To locate a particular bitfield description within this manual refer to Appendix B Register Information Analog_Trigger_Drive bit 4 type Write in Analog Trigger Etc Register address 61 This bit controls the ANALOG TRIG DRIVE output signal 0 Logic low 1 Logic high DAQ STC Technical Reference Manual 10 12 National Instruments Corporation Chapter 10 Miscellaneous Functions Analog Trigger Enable bit 3 type Write in Analog Trigger Etc Register address 61 This bit enables the analog trigger circuitry 0 Disabled 1 Enabled When the analog trigger circuit is enabled the analog trigger signal takes over the PFIO slot in the PFI selectors Analog Trigger Mode bits lt 0 2 gt type Write in Analog Trigger Etc Register address 61 This bit selects the analog trigger mode of operation if the analog trigger circuitry is enabled 0 Low window 1 High window 2 Middle window 4 High hysteresis 6 Low hysteresis Related bitfield Analog Trigger Enable Clock To Board bit 8 type Write in Clock and FOUT Register address 56 This bit enables the IN TIMEBASE to feedback or feedthrough to the board through the OUTBRD OSC pin 0 Disabled 1 Enabled Clock To Board Divide By 2 bit 9 type Write in Clock and FOUT Register address 56 If the Clock Board bit is set t
174. update modes are supported timed update and immediate update In the timed update mode LDAC lt 0 1 gt are programmed to output either UPDATE or UPDATE2 In the immediate update mode LDAC lt 0 1 gt are inverted versions of the DAC write signals TMRDACWR and CPUDACWR Output polarity is active low Destination DACs Related bitfields LDACi Source Select DACi Update Mode DAQ STC Technical Reference Manual 3 18 National Instruments Corporation Chapter 3 Analog Output Timing Control Table 3 1 Pin Interface Continued Pin Name Type Description TMRDACREQ O9TU DAQ STC Data Request This output indicates that there is no data available for the timer initiated write to the DAC The signal is used by the serial link data interface to the DAC When is active is asserted at the same time that the TMRDACWR would have been asserted had data been available TMRDACREQ is released on the AO TIMEBASE edge following AOFEF going inactive Output polarity is active high Destination Serial data interface TMRDACWR O4TU DAQ STC Write to the DAC This output serves as the DAC write signal generated by the DAQ STC whenever data from the data FIFO needs to be written to the DACs Following each UPDATE the TMRDACWR signal pulses a number of times to load data into the DACs according to the number of output channels When AOFEF is asserted the TMRDACWR pulses pau
175. 0 10 Teover2 End overrun detection mode 1 0 CONVERT to SOC 40 All timing values are in nanoseconds Figure 2 16 depicts a CONVERT pulse whose pulsewidth is determined by the output control circuit The CONVERT pulsewidth may also be selected to be equal to the signal that generates the pulse refer to AI CONVERT Pulse Timebase The SOC input notifies the DAQ STC that a conversion has been started Similarly the EOC input notifies the DAQ STC that a conversion has been completed The assertion of EOC leads to the assertion of SHIFTIN which you can use to load the acquisition data into its destination An overrun error occurs when the sampling rate is too high for the A D subsystem to maintain The time regions in which the DAQ STC can detect an overrun error are shown by the line OVER DETECT If a second CONVERT signal occurs during the indicated portion AI Overrun Error is set to 1 and an Error interrupt is generated if the Error interrupt is enabled Use Overrun Mode to configure the detect region to best match the A D subsystem by selecting whether an overrun error should be detected in just the interval labeled A or in both intervals A and B You should include the B region in the overrun detection for ADCs that tri state or otherwise output invalid data after the CONVERT signal is asserted This is due to the use of the trailing edge of the SHIFTIN signal to latch the A D data for most applications The num
176. 0 9 gt RTSI lt 0 6 gt GND AO_START1_Source SW PFI lt 0 9 gt RTSI lt 0 6 gt AI STI GND AO START Source SW PFI lt 0 9 gt RTSI lt 0 6 gt GND UC_TC AO UPDATE Source UI TC PFI lt 0 9 gt RTSI lt 0 6 gt GOUTI GND UI Source AO TBI PFI lt 0 9 gt RTSI lt 0 6 gt TB2 GND AO_UI2_Source AO TBI PFI lt 0 9 gt RTSI lt 0 6 gt GO_TC G1_TC TB2 GND AO External Gate PFI lt 0 9 gt RTSI lt 0 6 gt GND AO_UI2_External_Gate PFI lt 0 9 gt RTSI lt 0 6 gt GND G0_Source G TBI PFI lt 0 9 gt RTSI lt 0 6 gt TB2 G1_TC GND National Instruments Corporation 5 7 DAQ STC Technical Reference Manual Chapter 5 Programmable Function Inputs Table 5 2 PFI 0 9 Input Selections Continued Mux 0 1 10 11 17 18 19 20 21 31 0 Gate PFI 0 9 RTSI lt 0 6 gt AI ST2 UD TC GOUTI AI STI GND GI Source G TBI PFI 0 9 RTSI lt 0 6 gt TB2 G0 TC GND GI Gate PFI 0 9 51 lt 0 6 gt AI ST2 UD TC GOUTO AL STI GND Key AI STP The input AI STOP IN AI STI The internal analog input signal STARTI AI ST2 The internal analog input signal STARTI AI TBI The internal analog input signal AI IN TIMEBASEI AO TBI The internal analog output signal AO IN TIMEBASEI 50 TC The TC signal from general purpose counter 0 TC TC signal from general purpose counter 1 GOUTO GOUT signal from general purpose counter 0 GOUTI The
177. 0 Disarmed 1 Armed Related bitfields AI SI Arm SI Count Enabled St bit 8 type Read in AI Status 2 Register address 5 If the SI counter is armed this bit indicates whether the SI counter is enabled to count 0 No 1 Yes If the SI counter is disarmed this bit should be ignored National Instruments Corporation 2 67 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control AI SI Initial Load Source bit 7 type Write in AI Mode 2 Register address 13 If the SI counter is disarmed this bit selects the initial SI load register 0 Load register 1 Load register B If the SI counter is armed writing to this bit has no effect SI Load bit 9 type Strobe in AI Command 1 Register address 8 If the SI counter is disarmed this bit loads the SI counter with the contents of the selected SI load register A or B If the SI counter is armed writing to this bit has no effect This bit is cleared automatically SI Load bits lt 0 7 gt type Write in AI SI Load A Registers address 14 bits lt 0 15 gt type Write in AI SI Load A Registers address 15 This bitfield is load register A for the SI counter If load register A is the selected SI load register the SI counter loads the value contained in this bitfield on AI SI Load and on SI TC The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related Bitfields 51 Ne
178. 0 Tbrd Trigger to BRD output 16 56 All timing values are in nanoseconds Figure 3 31 START1 Delays Asynchronous Mode 3 7 12 Counter Outputs You can also output the internal counter TC signals to the board This section presents the output timing for the BC_TC and UC_TC outputs 3 7 12 1 BC_TC Figure 3 32 shows the delays associated with the BC_TC signal BC Source 34 5 lt Tbe Description Minimum Maximum Tbc BC Source to TC 16 94 timing values are in nanoseconds Figure 3 32 BC TC Delay National Instruments Corporation 3 107 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 3 7 12 2 UC TC Figure 3 33 shows the delays associated with the UC TC signal UC Source Tuc Tuc UC TC Name Description Minimum Maximum Tuc UC Source to TC 13 75 AII timing values are in nanoseconds Figure 3 33 UC TC Delay 3 0 Detailed Description This section describes the AOTM module in detail You need not read this section unless you need to understand the inner workings of the circuit This section refers to bitfields in the AOTM related registers in the DAQ STC register map See Appendix B Register Information for more information on the register addresses containing these bitfields Figure 3 34 shows a block diagram of
179. 0 bit 7 type Write in GO Mode Register address 26 bit 7 type Write in Mode Register address 27 If general purpose counter i is disarmed this bit selects the initial counter load register 0 Load register A 1 Load register B The source for subsequent loads depends Reload Source Switching If general purpose counter i is armed writing to this bit has no effect Related bitfields Gi Reload Source Switching Arm Arm Copy National Instruments Corporation 4 43 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer Gi Loading On Gate 0 bit 14 type Write in GO Mode Register address 26 i 1 bit 14 type Write in Mode Register address 27 This bit determines whether the gate signal causes counter reload 0 Gate signal does not cause counter reload 1 Counter is reloaded on gate edge that stops the counter unless edge gating is used and Gi Trigger Mode For Edge Gate is set to 3 In the later case counter is reloaded on every selected gate edge Reloading occurs on active source edge Notice that it is legal to set both Gi Loading On Gate and Loading On to 1 simultaneously Related bitfields Gi Trigger Mode For Edge Gate Gj Loading On TC 0 bit 12 type Write in GO Mode Register address 26 i l bit 12 type Write in Mode Register address 27 This bit determines the counter behavior on TC 0 Roll over on TC 1 Reload on TC
180. 010 Programming Interrupts for Data Acquisition on 80x86 Based Computers Interrupts related to analog output can be generated on the following analog output conditions Error overrun or overflow e not supported e not supported e STARTI e e UC IC e FIFO condition e UPDATE Basic actions required to enable detect and acknowledge the AO related interrupts follow Error To enable AO_Error_Interrupt_Enable To recognize AO_Overrun_St To acknowledge and clear AO_Error_Interrupt_Ack STOP not supported To enable AO_STOP_Interrupt_Enable To recognize AO STOP St To acknowledge and clear AO STOP Interrupt START not supported To enable AO START Interrupt Enable To recognize AO START St To acknowledge and clear AO START DAQ STC Technical Reference Manual 3 36 National Instruments Corporation Note START1 To enable To recognize To acknowledge and clear BC_TC To enable To recognize To acknowledge and clear UC_TC To enable To recognize To acknowledge and clear FIFO Condition To enable To select condition use To recognize To clear UPDATE To enable To recognize To clear Chapter 3 Analog Output Timing Control AO STARTI Interrupt Enable AO STARTI St AO STARTI Interrupt AO BC TC Interrupt Enable AO BC TC St AO BC TC Interrupt AO UC TC Interrupt Enable AO UC TC St AO UC
181. 1 this pin reflects the internal AI signal VSTARTO2 after it has been pulse stretched to be 1 2 AI OUT TIMEBASE periods long Source Destination This pin is appropriate for use as a bidirectional PRETRIG signal Related bitfields BD 1 Pin Dir AI Trigger Length DAQ STC Technical Reference Manual 5 2 National Instruments Corporation Chapter 5 Programmable Function Inputs Table 5 1 Pin Interface Continued Pin Name Type Description PFI2 CONV B9TU PFI2 ADC Conversion Strobe from Analog Input As an input this pin provides a signal path to the PFI selectors As an output this reflects the internal AI signal SCLKG the signal that appears on the CONVERT pin The hardware generates SCLKG by passing the internal AI signal SCLK through pulsewidth and polarity selection circuitry Source Destination This pin is appropriate for use as a bidirectional EXTCONV signal Related bitfields BD 2 Pin Dir AI CONVERT Output Select PFI3 G SRCI B9TU PFI3 General Purpose Counter 1 Source As an input this pin provides a signal path to the PFI selectors As an output this pin reflects the internal signal G SOURCE from general purpose counter 1 Source Destination This pin is appropriate for use as a bidirectional CTRSRC1 signal Related bitfields BD 3 Pin Dir PFI4 G_GATE1 B9TU PFIA General Purpose Counter 1 Gate As an input this pin provides a signal path to the PFI selectors As an output this pin
182. 100 to 2 103 STARTI and START2 triggers 2 97 to 2 100 STOP trigger 2 103 to 2 104 trigger output 2 97 to 2 104 trigger selection and conditioning 2 119 to 2 122 edge detection 2 122 EXT GATE routing logic figure 2 121 PFI selectors table 2 121 START and STOP routing logic figure 2 120 STARTI and START2 routing logic figure 2 120 synchronization 2 122 trigger signals 2 122 to 2 123 Index single buffer mode 3 13 waveform staging 3 14 to 3 15 DAC interface 3 8 data interfaces 3 8 to 3 11 FIFO data interface 3 8 to 3 10 serial link data interface 3 10 unbuffered data interface 3 11 primary group analog output modes 3 5 to 3 7 CPU driven analog output 3 6 to 3 7 DAQ STC and CPU conflict 3 7 DAQ STC driven analog output 3 6 secondary analog output 3 16 update timing for primary group 3 11 to 3 12 external UPDATE 3 12 internal UPDATE 3 11 to 3 12 analog output programming 3 20 to 3 84 bitfield descriptions 3 45 to 3 84 primary analog output operation 3 20 to 3 32 arming 3 30 to 3 31 board power up initialization 3 22 to 3 23 changing update rate 3 34 to 3 35 channel select 3 28 enable interrupts 3 30 FIFO mode 3 29 to 3 30 interrupts 3 35 to 3 37 LDAC source and UPDATE mode 3 29 master slave operation considerations 3 35 number of buffers 3 24 to 3 26 analog output application 1 3 to 1 4 analog output functions 3 5 to 3 16 buffer timing and control for primary
183. 11 6 Single Period Measurement To use this function set G CONTROL conditioning to edge gating and program the counter to count once The rising edge of GATE is synchronized by the falling edge of SOURCE to generate a CONTROL pulse The counter increments on every SOURCE rising edge following the CONTROL pulse On the second CONTROL pulse the counter disarms The HW save register switches to transparent mode on the rising edge of G_GATE and returns to latched mode on the next SOURCE falling edge Figure 4 37 shows an example of a single period measurement where the period of GATE is five G SOURCE rising edges The dotted line indicates where the ARM occurs and the arrows indicate where the gate interrupt is generated G SOURCE act G CONTROL Counter Value 0 xX 1X 2 X3X 4X 5 HW Save 0 5 HW Save Register Figure 4 37 Single Period Measurement DAQ STC Technical Reference Manual 4 76 National Instruments Corporation Chapter 4 General Purpose Counter Timer 4 8 11 7 Single Pulsewidth Measurement To use this function set G CONTROL conditioning to level gating and program the counter to START on CONTROL and count once is synchronized by the falling edge of G SOURCE to generate G CONTROL The counter begins incrementing when CONTROL is sensed high The c
184. 129 2 8 4 Interrupt Control te oerte Ree rH t per tt rient 2 130 2 8 5 Error D tection eter te ERST OR 2 132 2 8 5 1 Overrun Error oeseoee titan nene ree 2 132 2 8 5 2 Overflow Errot e Us 2 132 2 8 5 3 SC TC EOR eet ee teo netten 2 132 2 8 6 Nominal Signal Pulsewidths eee 2 133 Analog Output Timing Control 3 1 32 3 3 3 4 COV EL VIC Ws 2 iro fepe 3 1 3 1 1 Programming the 3 2 Features ee ORO Deren rette p QU 3 2 Simplified e eL estet e ser eee 3 4 Analog Output Functions sisisi ote tme eet tette reiten 3 5 3 4 1 Primary Group Analog Output 3 5 3 4 1 1 DAQ STC Driven Analog 3 6 3 4 1 2 CPU Driven Analog 3 6 3 4 1 3 DAQ STC and CPU 3 7 3 4 2 DAC Interface eg 3 8 National Instruments Corporation Vii DAQ STC Technical Reference Manual Contents 3 4 3 Data Interfaces scoop er cete ben dents 3 8 3 4 3 1 FIFO Data 3 8 3 4 3 2 Serial Link Data Interface 2 1 12 3 10 3 4 3 3 Unbuffered Data Interface esses 3 11 3 4 4 Update Timing for Primary Group Analog Output 3 11 3 4 4 1 Internal 3 11
185. 13 AO UI Load A 13 Reserved 12 AO UI Load A 12 Reserved 11 AO UI Load A 11 Reserved 10 AO UI Load 10 Reserved 9 AO UI Load 9 Reserved 8 AO UI Load A 8 Reserved 7 AO UI Load 7 AO UI Load B 6 AO UI Load A 6 AO UI Load B 5 AO UI Load A 5 AO UI Load 4 AO UI Load A 4 AO UI Load B 3 AO UI Load 3 AO UI Load B 2 AO UI Load A 2 AO UI Load 1 AO UI Load A 1 AO UI Load B AO UI Load 0 AO UI Load B DAQ STC Technical Reference Manual B 24 National Instruments Corporation AO UI Load Address 43 15 14 13 N _ NUR DOO O 15 14 13 N _ oo Registers Type Write only AO UI Load B AO UI Load B AO UI Load B AO UI Load B AO UI Load B AO UI Load B AO UI Load B AO UI Load B AO UI Load B AO UI Load B AO UI Load B AO UI Load B AO UI Load B AO UI Load B AO UI Load B AO UI Load B AO UI Save Registers Address 17 Type Read only AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value National Instruments Corporation Address 16 15 14 13 N DO C
186. 13 Retriggerable Single Pulse Generation To use this function set G CONTROL conditioning to edge gating and program the counter to reload on and stop at the second TC The rising edge of GATE is synchronized by the falling edge of G SOURCE to generate a G CONTROL pulse The counter begins decrementing after the CONTROL pulse Once the counter TC is reached the counter reloads and counts down to TC again On the second counter TC the counter stops to wait for another gate On the next rising edge the whole process begins again The load select signal indicates whether the reload occurs from load register or B Figure 4 44 shows an example of retriggerable single pulse generation with a pulse delay of four and a pulsewidth of two The dotted line indicates where the ARM occurs G SOURCE Hu G GATE d H _ BH o G CONTROL Load Select i li 3 2 10 10 3 X2X XoX Xo0X 3 Counter Load Counter Value Counter TC G_OUT Figure 4 44 Retriggerable Single Pulse Generation National Instruments Corporation 4 83 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 8 11 14 Continuous Pulse Train Generation To use this function set G CONTROL conditioning to
187. 15 SCAN PROG deassertion 2 103 simplified analog input model 2 5 simplified analog output model 3 4 START trigger and SCAN IN PROG assertion 2 100 external CONVERT mode 2 102 internal CONVERT mode 2 101 STARTI and START2 triggers 2 97 asynchronous mode 2 99 to 2 100 synchronous mode 2 98 to 2 99 START trigger output 3 104 to 3 107 STOP trigger 2 103 asynchronous mode 2 104 synchronous mode 2 104 RTSI trigger module 6 1 to 6 7 features 6 1 overview 6 1 pin interface 6 1 to 6 2 programming information 6 2 to 6 5 bitfield descriptions 6 3 to 6 5 MSC RTSI Pin Configure function 6 3 BRD O 1 output selections table 6 7 RTSI lt 2 3 gt output selections table 6 7 National Instruments Corporation 1 33 Index RTSI_TRIGGER lt 0 6 gt output selections table 6 6 S SC counter control circuitry 2 123 to 2 125 description 2 123 SC CE signal description table 2 115 SC counter operation 2 125 SC CLK signal table 2 115 SC DISARM signal 2 125 SC GATE signal table 2 115 SC HOLD signal table 2 115 SC LOAD signal description table 2 116 SC counter operation 2 125 SC LOAD SRC signal table 2 116 SC SRC signal table 2 116 SC STARTI signal table 2 116 SC TC signal continuous acquisition mode 2 15 counter outputs figure 2 105 description table 2 116 nominal pulsewidths table 2 133 pin interface table 2 23 posttrigger acquisition mode 2 1
188. 15 gt type Write in GO Load A Registers address 29 i 1 bits lt 0 7 gt type Write in G1_Load_A_Registers address 32 bits lt 0 15 gt type Write in Load A Registers address 33 This bitfield is load register A for general purpose counter 1 If load register is the selected load register the counter loads the value contained in this bitfield on Load on the counter TC and on the induced counter reload condition if reloading is enabled The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related Bitfields Next Load Source St Load Gi Loading On Gate Gi Load i 0 bits 0 7 Write in GO Load B Registers address 30 bits lt 0 15 gt type Write in GO_Load_B_Registers address 31 bits lt 0 7 gt Write in G1 Load B Registers address 34 bits lt 0 15 gt gt type Write in G1 Load B Registers address 35 This bitfield is load register B for general purpose counter 1 If load register is the selected load register the counter loads the value contained in this bitfield on Load on the counter TC and on the induced counter reload condition if G_GATE reloading is enabled The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related Bitfields Next Load Source St Load Gi Loading On Gate Gi Load Source Select i
189. 215 03 5472 2977 02 596 7455 5 520 3282 0348 430673 32 84 86 00 2265887 91 640 0533 08 730 43 70 056 200 51 55 02 737 4644 01635 523154 512 794 5678 National Instruments Corporation Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax Phone Computer brand Model Processor Operating system include version number Clock speed MHz RAM MB Display adapter Mouse yes Other adapters installed Hard disk capacity MB Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps reproduce the problem DAQ STC Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right
190. 3 AO Error Interrupt 3 53 AO Error Interrupt Enable 3 53 AO Error Second Enable 3 54 AO External Gate Enable 3 54 AO External Gate Polarity 3 54 AO External Gate Select 3 54 AO External Gate St 3 55 AO Fast CPU 3 55 AO FIFO Empty St 3 55 AO FIFO Enable 3 55 AO FIFO Flags Polarity 3 56 AO FIFO Full St 3 56 AO FIFO Half Full St 3 56 AO FIFO Interrupt Enable 3 56 AO FIFO Mode 3 57 AO FIFO Request St 3 57 AO FIFO Retransmit Enable 3 57 AO FIFO Second Irq Enable 3 57 AO Interval Buffer Mode 3 58 AO LDACIi Source Select 3 58 AO Multiple Channels 3 58 AO Mute A 3 58 AO Mute B 3 59 AO Not UPDATE 3 59 AO Number Of Channels 3 59 National Instruments Corporation 1 13 Index AO_Number_Of_DAC_Packages 3 60 AO_Output_Divide_By_2 3 60 AO_Overrun_St 3 60 AO_Reset 3 60 to 3 61 AO Software Gate 3 61 Source Divide 2 3 61 AO START Edge 3 61 START Interrupt 3 61 START Interrupt Enable 3 62 AO START Polarity 3 62 AO START Pulse 3 62 AO START Second Irq Enable 3 62 AO START Select 3 62 AO START St 3 63 AO START Stop Gate Enable 3 63 AO START Stop Gate St 3 63 AO START Sync 3 63 STARTI Disable 3 63 AO STARTI Edge 3 64 AO STARTI Interrupt 3 64 AO STARTI Interrupt Enable 3 64 STARTI Polarity 3 64 STARTI Pulse 3 64 AO STARTI Second Ena
191. 3 configuration FIFO control 2 7 to 2 9 configuration memory output initializing 2 28 to 2 29 configuration memory timing 2 89 to 2 01 related signals figure 2 89 timing table 2 90 continuous acquisition mode 2 15 continuous mode buffer timing and control primary analog output 3 13 to 3 14 Continuous Pulse Train Generation function 4 30 to 4 31 DAQ STC Technical Reference Manual Index continuous pulse train generation description 4 12 to 4 13 programming 4 28 to 4 31 control lines digital I O 7 12 conventions used in manual xxv CONVERT signal basic analog input timing 2 86 to 2 87 configuration memory timing 2 89 to 2 90 description table 2 20 external gating 2 109 to 2 111 gating 2 16 interval scanning mode 2 106 to 2 108 low level timing and control functions 2 6 to 2 11 ADC control 2 7 configuration FIFO and external multiplexer control 2 7 to 2 9 CONVERT timing 2 9 to 2 11 Data FIFO control 2 7 nominal pulsewidths table 2 133 selecting with AI CONVERT Signal function 2 38 to 2 40 simplified analog input model 2 4 to 2 6 single wire mode 2 18 CONVERT SRC signal basic analog input timing 2 86 external CONVERT source 2 92 to 2 93 external gating 2 110 external trigger timing 2 93 to 2 97 internal CONVERT mode 2 9 to 2 10 reference pin selection table 2 84 to 2 85 CONVERT timing See external CONVERT mode internal CONVERT mode counter contents reading 4 34 counter o
192. 3 9 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control Iteration 1 Iteration 2 UPDATE UC TC ms MN TMRDACWR AOFEF AOFFRT j Figure 3 6 Local Buffer Mode 3 4 3 2 Serial Link Data Interface In the serial link data interface mode the DACs receive analog output data through a serial data link or some other interface instead of through the analog output data FIFO In this mode the AOFEF signal is controlled by the data link When AOFEF is active the TMRDACREQ signal asserts in place of the write signal TMRDACWR indicating that data is required for a DAC write operation The assertion of TMRDACREQ initiates a transfer across the data link Once the transfer completes the AOFEF signal is released allowing the DAC write to complete Figure 3 7 shows an example waveform from a serial link data interface AOFEF is initially held active After the UPDATE pulse TMRDACREQ is asserted where the TMRDACWR pulse should be causing the serial data link to transmit data Once the serial link data transfer completes AOFEF is released allowing the write to occur UPDATE i TMRDACREQ TMRDACWR Figure 3 7 Serial Link Data Interface DAQ STC Technical Reference Manual 3 10 National Ins
193. 36 OUT Tefset MUXFEF setup to end of 21 TS LOCALMUX CLK Tmxdrt End of LOCALMUX_CLK to 0 LOCALMUX_FFRT asserted Tmxfrt LOCALMUX FFRT pulsewidth 0 5 1 0 5 1 Tort OUT CLK to LOCALMUX FFRT 11 35 deasserted Tcstrb OUT CLK to EXTSTROBE change 11 36 Texmxstrb EXTSTROBE pulsewidth see 1 1 DIO HW Serial Timebase Tcsoc CONVERT to SOC 40 All timing values are in nanoseconds The numbers in parentheses refer to the number of clock periods that will occur at the minimum and maximum delays because those parameters are clock edge driven with possible additional gate delays The trailing edge of LOCALMUX_CLK should be used to latch the new configuration information which in general should not change until the input signal has been sampled The LOCALMUX_CLK signal is asserted by the leading edge of CONVERT and is held for either two or four output clock edges regardless of polarity and then until the active edge of SOC DAQ STC Technical Reference Manual 2 90 National Instruments Corporation 2 1 5 Chapter 2 Analog Input Timing Control refer to AI LOCALMUX CLK Pulse Width This provides a fixed minimum pulsewidth but guarantees that the configuration data does not change until the input signal has been sampled The EXTMUX CLK controls the external multiplexer with one of two options and is generated at every conversion In the first option the EXTMUX is asserted by CONVERT is identical in length
194. 4 Figure 2 25 Figure 2 26 Figure 2 27 Figure 2 28 Figure 2 29 Figure 2 30 Figure 2 31 Figure 2 32 Figure 2 33 Figure 2 34 Figure 2 35 Figure 2 36 Figure 2 37 Figure 2 38 Figure 2 39 Figure 2 40 Figure 2 41 Figure 2 42 Figure 2 43 Figure 2 44 Figure 2 45 Figure 2 46 Figure 2 47 Figure 2 48 Figure 2 49 Figure 2 50 Figure 2 51 Figure 2 52 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 External Trigger Timing Asynchronous 2 222222 1 2 94 External Trigger Timing Synchronous Level Internal CONVERT 2 95 External Trigger Timing Synchronous Edge Internal CONVERT nennen 2 95 External Trigger Timing Synchronous Level External CONVERT 2 96 External Trigger Timing Synchronous Edge External CONVERT 2 96 5 Delays Synchronous Mode Internal CONVERT 2 98 5 2 Delays Synchronous Mode Internal CONVERT 2 98 STARTI Delays Synchronous Mode External CONVERT 2 98 START2 Delays Synchronous Mode External CONVERT 2 99 5 Delays Asynchronous 2 99 START2 Delays Asynchronous 2 100 START Delays Internal CONVERT eee 2 101 START Delays External CONVERT eee 2 102 SCAN IN PROG eene enne ene 2 103 STOP Delay Syn
195. 4 staged acquisition 2 16 scan functions AI Number Of Scans 2 33 to 2 34 AI Scan End 2 37 to 2 38 AI Scan Rate Change 2 43 to 2 44 Scan Start 2 34 to 2 37 2 42 to 2 43 SCAN IN PROG signal assertion analog input trigger output 2 100 to 2 102 external CONVERT mode 2 102 internal CONVERT mode 2 101 deassertion analog input trigger output 2 103 DAQ STC Technical Reference Manual Index description table 2 23 external CONVERT mode 2 10 to 2 11 external gating 2 111 internal CONVERT mode 2 10 nominal pulsewidths table 2 133 simplified analog input model 2 6 scan level timing and control functions 2 11 to 2 13 external START mode 2 12 to 2 13 internal START mode 2 11 to 2 12 SCKG signal description table 2 115 3 112 DIV counter operation 2 129 SC counter operation 2 124 SCLK signal analog input timing control module table 2 115 analog output timing control module table 3 112 SCLKG signal table 2 116 SEC IRQ OUT BANKO signal table SEC OUT BANKI signal table secondary analog output operation overview 3 16 programming 3 38 to 3 42 arming 3 41 board power up initialization 3 39 counting for waveform staging 3 40 hardware gate programming 3 39 overview 3 38 resetting 3 38 software gate operation 3 40 update selection 3 40 to 3 41 timing 3 93 Serial DIO function 7 11 serial input timing digital I O 7 15 to 7 16 serial link data interface 3 10 serial mode digita
196. 4 44 Gi OR Gate bit 4 45 Gi Output Mode bit 4 45 Gi Output Polarity bit 4 45 Gi Output St bit 4 45 Gi Permanent State Data St bit 4 46 Gi Read Acknowledges bit 4 46 Gi Reload Source Switching bit 4 46 Gi Reset bit 4 46 Gi Save Copy bit 4 47 Save St bit 4 47 Save Trace bit 4 47 Save Value bit 4 47 Seamless Pulse Train Change function 4 31 Gi Simple Event Counting function 4 19 to 4 20 Gi Source Polarity bit 4 48 Source Select bit 4 48 Stale Data St bit 4 48 Gi Stop Mode bit 4 48 Gi Synchronized Gate bit 4 49 Error Confirm bit 4 49 Gi TC Error St bit 4 49 Gi TC Interrupt bit 4 49 Gi TC Interrupt Enable bit 4 50 Gi TC Second Enable bit 4 50 Gi TC St bit 4 50 Gi Trigger Mode For Edge Gate bit 4 50 Up Down bit 4 51 Watch function 4 34 Gi Write Acknowledges Irq bit 4 51 Gi Write Switch bit 4 51 GPCT See general purpose counter timer GPFO 0 Output Enable bit 4 51 GPFO 0 Output Select bit 4 52 GPFO 1 Output Enable bit 4 52 GPFO 1 Output Select bit 4 52 DAQ STC Technical Reference Manual Index H halt gating mode external gate timing internal CONVERT figure 2 111 theory of operation 2 17 to 2 18 hardware gate programming analog input timing control 2 30 to 2 31 secondary analog output operation 3 39 hardware save registers reading 4 34 to 4 35 hardware controlled se
197. 4 53 to 4 56 assertion 2 100 to 2 102 U D reference pin selection external CONVERT mode 2 102 table 4 54 internal CONVERT mode 2 101 CTRGATE reference pin selection STARTI and START2 triggers table 4 54 2 97 to 2 100 CTRSRC minimum period and asynchronous mode 2 99 to 2 100 minimum pulsewidth synchronous mode 2 97 to 2 99 figure 4 55 STOP trigger 2 103 to 2 104 CTRSRC reference pin selection asynchronous mode 2 104 table 4 53 synchronous mode 2 104 CTRSRC to CTROUT delay trigger output analog output timing control 4 55 to 4 56 module 3 104 to 3 107 minimum pulsewidth 4 56 STARTI trigger asynchronous mode TMRDACREQ signal 3 106 to 3 107 DAQ STC driven analog output timing STARTI trigger synchronous mode 3 86 to 3 87 3 104 to 3 106 description table 3 19 serial link data interface 3 10 trigger selection and conditioning analog input timing control module simplified analog output model 3 5 2 119 to 2 122 TMRDACWR signal edge detection 2 122 DAC interface 3 8 EXT GATE routing logic DAQ STC and CPU driven analog figure 2 121 output timing 3 91 to 3 92 PFI selectors table 2 121 DAQ STC driven analog output 3 6 START and STOP routing logic DAQ STC driven analog output timing figure 2 120 3 86 to 3 88 and START2 routing logic description table 3 19 figure 2 120 FIFO data interface 3 9 synchronization 2 122 local buffer mode 3 9 to 3 10
198. 49 0 30 0 31 AO UC Load Registers Write 50 51 0 32 0 33 UC Save Registers Read 20 21 0 14 0 15 AO UI Load Registers Write 40 41 0 28 0 29 AO UI Load Registers Write 42 43 2 0 2 DAQ STC Technical Reference Manual 2 National Instruments Corporation Appendix B Register Information Table B 1 DAQ STC Registers Continued Register Name Type Address Hex Address AO UI Save Registers Read 16 17 0 10 0 11 AO UD Load A Register Write 53 0x35 AO UD Load Register Write 55 0x37 AO UD Save Register Read 23 0 17 Clock and FOUT Register Write 56 0x38 DIO Control Register Write 11 OxOB DIO Output Register Write 10 DIO Parallel Input Register Read 7 0x07 DIO Serial Input Register Read 28 Ox1C GO Autoincrement Register Write 68 0x44 G0_Command_Register Write 6 0x06 GO HW Save Registers Read 8 9 0 08 0 09 GO Input Select Register Write 36 0x24 GO Load A Registers Write 28 29 0x1C 0x1D GO Load B Registers Write 30 31 Ox1E Ox1F GO Mode Register Write 26 Ox1A GO Save Registers Read 12 13 0x0C 0x0D Gl Autoincrement Register Write 69 0x45 Command Register Write oh 0x07 G1_HW_Save_Registers Read 10 11 Ox0A OxOB Gl Input Select Register Write 37 0x25 Load Registers Write 32 33 0 20 0 21 Load Registers Write 34 35 0 22 0 23 Mode Register Write 27 Ox1B Save Registers Rea
199. 5 Table 4 10 OUT 22200202 2 00000000000000000000000200 08 4 65 Table 4 TT GOUT Polarity eiiie eerte s 4 65 Table 4 12 OUTO RTSI IO 5 4 66 Table 4 13 OUTI DIV TC OUT 4 66 Table 4 14 CONTROL Conditioning essent nennen nere 4 67 Table 4 15 Gate Actions 4 67 Table 4 16 START STOP Modes for Edge Gating sss 4 68 Table 4 17 Reload on CONTROL Selections 4 68 Table4 18 Gate een pee Ree ertet qt 4 69 Table 4 19 Selectors eese erento sette ean 4 70 Table 5 1 Pin Interf ee iue are terit ve eee d eere e ERE 5 2 Table 5 2 lt 0 9 gt Input Selections 5 7 Table 5 3 lt 0 9 gt Output 5 8 Table 6 1 coro cb etr tasto aree eee 6 2 Table 6 2 lt 0 6 gt Output 1 6 6 Table 6 3 RTSI BRD O 1 Output Selections esee 6 7 Table 6 4 RTSI lt 2 3 gt Output 6 7 Table 7 1 PinsInterface 4 7 6 Table 7 2 Serial Output Source 7 17 Table 8 1 Pin re o ettet cor occa eI athe AT Oe bebe de aes 8 2 Table 8 2 Interrupt Condi
200. 5 mA source tri state pull up 50 kQ Pin Name Type Description G_OUTO RTSI_IO B9TU Counter 0 Output RTSI IO Programmed as an input this pin provides a path to RTSI lt 0 6 gt selectors Programmed as an output this pin can output the OUT signal from general purpose counter 0 or it can output the signal present on one of the lt 0 6 gt lines Related bitfields GPFO 0 Output Select GPFO 0 Output Enable Gi Output Mode Gi Output Polarity OUTI DIV TC OUT O9TU Counter 1 Output DIV Counter Terminal Count This pin can output the OUT signal from general purpose counter 1 or it can output the internal signal EXT DIVTC from the AITM for compatibility with an SCXI scan mode Related bitfields 0 Output Select GPFO 0 Output Enable Gi Output Mode Gi Output Polarity UP DOWN O 1 ID IU Up Down Controls These pins the dedicated up down controls for the GPCTs When selected for counter control logic low indicates count down and logic high indicates count up These pins are pulled down on the first revision of the DAQ STC and pulled up on later revisions See Appendix D DAQ STC Revision History for DAQ STC revision information Related bitfields Up Down DAQ STC Technical Reference Manual 4 16 National Instruments Corporation Chapter 4 General Purpose Counter Timer 4 6 Programming Information 4 6 1 This sect
201. 50 SI2 Clock This signal is the actual clock for the SI2 counter and the SI2 control logic When the counter is not armed 512 CLK is derived from the write strobe for AI Command 1 Register so that the counter can be loaded using the load command When the counter is armed SI2_CLK is the same SI2 SRC Related bitfields 512 Load 512 LOAD SD Load This signal pulses to load the value from the selected 512 load register into 512 counter Related bitfields 512 Load DAQ STC Technical Reference Manual 2 116 National Instruments Corporation Chapter 2 Analog Input Timing Control Table 2 9 Internal Signals Continued Signal Description 50 LOAD SD Load Source This signal determines which load register A or the 512 counter will use on the next reload The initial SI2 load source is set using AI SI2 Initial Load Source The SI2 control logic updates the load source while the DAQ STC is counting The current load source depends on the counter state and the selected reload mode Related bitfields SI2 Initial Load Source 50 SRC SD Source This signal is the timebase for 512 counter It is equal to either SI SRC or AI IN TIMEBASEI Related bitfields AI SI2 Source Select SD TC 50 TC This signal is the SCLK signal when internal CONVERT is selected SI CE SI Count Enable This signal enables and disables the SI counter Refer
202. 6 This bit indicates the status of the UC save register 0 UC save register is tracing the counter 1 UC save register is latched for later read 0 UC Save Trace bit 12 type Write in AO Command 2 Register address 5 Setting this bit to 1 causes the UC save register to latch the UC counter value at the next UC CLK falling edge Setting this bit 0 causes the UC save register to trace the UC counter National Instruments Corporation 3 69 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 UC Save Value bits lt 0 7 gt type Write in AO UC Save Registers address 20 bits lt 0 15 gt type Write in AO UC Save Registers address 21 When AO Save Trace is 0 this bitfield reflects the contents of the UC counter When you set AO UC Save Trace to 1 this bitfield synchronously latches the contents of the UC counter using the UC source The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related bitfields UC Save Trace 0 UC Switch Load Every BC TC bit 12 type Write in AO Mode 3 Register address 70 This bit enables the UC counter to switch load registers on TC 0 Disabled 1 Enabled 0 UC Switch Load Every TC bit 2 type Write in AO Mode 1 Register address 38 This bit enables the UC counter to switch load register on TC 0 Disabled 1 Enabled 0 UC Switch Load On BC TC bit 6 type Strobe in
203. 8 Detailed Description for more information on the SI2 control circuit SI2 Reload Mode bit 8 type Write in AI Mode 2 Register address 13 This bit selects the reload mode for the SI2 counter 0 No automatic change of the SI2 load register 1 Alternate first period on every STOP Set this bit to 1 in the internal CONVERT mode to make the time interval between the START trigger and the first CONVERT different from the time interval between CONVERTS AI SI2 Save Value bits lt 0 15 gt type Read in AI SI2 Save Register address 25 This bitfield reflects the contents of the SI2 counter Reading from this bitfield while the 512 counter is counting may result in an erroneous value DAQ STC Technical Reference Manual 2 72 National Instruments Corporation Chapter 2 Analog Input Timing Control SI2 Source Select bit 11 type Write in AI Mode 3 Register address 87 This bit selects the SI2 source 0 same signal selected as the SI source Refer to SI Source Select 1 AL IN TIMEBASEI Related bitfields SI Source Select SOC Polarity bit 13 type Write in AI Personal Register address 77 This bit determines which edge of the SOC input signal indicates start of conversion 0 Rising edge Falling edge Related bitfields AI SOC St SOC St bit 3 type Read in Joint Status 2 Register address 29 This bit reflects the state of the SOC pin after the polarity selection
204. 8 Single Period and Pulsewidth Measurement 4 24 4 6 1 9 Buffered Period Semiperiod and Pulsewidth Measurement ERES 4 26 4 6 1 10 Pulse and Continuous Pulse Train Generation 4 28 4 6 1 11 Frequency Shift Keying 4 31 4 6 1 12 Pulse Train Generation for ETS 4 33 4 6 1 13 Reading the Counter Contents sess 4 34 4 6 1 14 Reading the Hardware Save Registers 4 34 4 6 1 15 Enabling the General Purpose Counter Timer Output 4 35 4 6 2 Bitfield Descriptions tette rettet eher 4 35 47 Timing Diagrams eee ne Riera RS 4 53 4 7 1 CTRSRC Minimum Period and Minimum Pulsewidth 4 55 4 7 2 CTRSRC to CTROUT Delay eee 4 55 4 7 3 Minimum 4 56 4 7 4 CTRGATE to CTROUT 2 4 57 4 7 5 CTRGATE eia 4 57 4 7 6 CTRGATE Setu p erem etie debes 4 58 4 7 7 CTR U D Setup noeh E Ua en 4 59 48 Detailed Description ees ottiene eet Ite eee heres 4 61 4 8 1 Internal Signals and Operation eene 4 62 4 8 2 SOURCE Selection and Conditioning esses 4 63 4 8 3 G_GATE Selection and Conditioning eene 4 64 4 8 4 UP DOWN Control eese nennen enne 4 64 4 8 5 OU
205. 9 The internal signal from general purpose counter 1 31 Logic low When you set this bit to 0 the DAQ STC is in the internal UPDATE mode When you select any other signal as the UPDATE source the DAQ STC is in the external UPDATE mode 0 UPDATE St bit 5 type Read in AO Status 1 Register address 3 This bit indicates whether an UPDATE has occurred 0 Has not occurred 1 Has occurred You can clear this bit by setting UPDATE Interrupt to 1 Related bitfields AO UPDATE Interrupt Ack Refer to Table 8 2 Interrupt Condition Summary for more information 3 7 Timing Diagrams 3 7 1 The DAQ STC is primarily a synchronous device and requires careful inspection of the timing parameters when designing a new board Related subsections within the chip can be programmed to operate at different clock rates and the necessary synchronization time can significantly affect the edges and pulsewidths of the board level signals There are certain configurations of the clock rates that offer very straightforward timing signals and it is intended that these settings be used for the majority of the DAQ STC designs The other modes are included to provide flexibility for unusual or currently unanticipated applications This section includes all of the timing diagrams for the AOTM module of the DAQ STC and indicates the more common configurations Signal Definitions All timing in this section refers to pin to pin timi
206. AC mode DACWRO pulses when a write occurs to an even channel and DACWRI pulses when a write occurs to an odd channel If you are using the DAQ STC on a device with two DACs in individual packages set this bit to 1 When you make this selection you can use pins DACWRO and DACWRI In all other cases set this bit to 0 When you choose this option you should use pin DACWRO only Refer to section 3 4 2 DAC Interface for more information on DAC modes 0 Output Divide By 2 bit 5 type Write in Clock and FOUT Register address 56 This bit determines the frequency of the internal timebase TIMEBASE 0 Sameas IN TIMEBASE 1 TIMEBASE divided by 2 0 Overrun St bit 9 type Read in AO Status 1 Register address 3 This bit indicates the detection of an overrun error 0 No error 1 Error An overrun error occurs when an UPDATE command is issued to a DAC that was not loaded with data This bit can be cleared by setting AO Error Interrupt Ack to 1 Related bitfields AO Error Interrupt Ack Note This bit may incorrectly indicate that an error occurred after the end of a waveform generation sequence if there is no more data in the buffer You can avoid this false error by transferring one more point of data to the board than the waveform generation requires AO_Reset bit 1 type Strobe Joint Reset Register address 72 Setting this bit to 1 resets the following registers to their power on state AO C
207. AI Error Interrupt 1 L DAQ STC Technical Reference Manual 2 26 National Instruments Corporation Chapter 2 Analog Input Timing Control At this point you should clear your software copies of the registers so that they will agree with the DAQ STC registers The affected registers are AI Command 1 Register AI Command 2 Register AI Mode 1 Register AI Mode 2 Register AI Mode 3 Register AI Output Control Register AI Personal Register AI START STOP Select Register AI Trigger Select Register L Reserved_One 1 AI Start Stop 1 X AI Configuration End 1 End critical section You need to perform Board Personalize function to bring into a known state You can then program the AITM for any desired operation 2 6 3 2 Board Power up Initialization Part of the AITM programming depends only on properties of the hardware surrounding the DAQ STC If you are programming a DAQ STC that is part of a data acquisition system refer to the document for register level programming for information about the proper selections to make in this function Function AI Board Personalize Begin critical section AI_Configuration_Start 1 AI_Source_Divide_By_2 0 equals IN TIMEBASE or 1 IN TIMEBASEI is IN_TIMEBASE divided by two AI Output Divide By 2 0 OUT TIMEBASE equals IN or 1 AI OUT TIMEBASE is IN TIMEBASE
208. AI SI Count Enable St Reserved AI SI Next Load Source St AI SI Armed St AI SC Q St AI SC Q St AI SC Save St AI SC Next Load Source St AI SC Armed St Analog Trigger Etc Register Address 61 Type Write only 15 14 13 N GPFO 1 Output Enable GPFO 0 Output Enable GPFO 0 Output Select GPFO 0 Output Select GPFO 0 Output Select Reserved Reserved Reserved GPFO 1 Output Select Misc Counter TCs Output Enable Software Test Analog Trigger Drive Analog Trigger Enable Analog Trigger Mode Analog Trigger Mode Analog Trigger Mode National Instruments Corporation Appendix B Register Information AI Trigger Select Register Address 63 Type Write only 15 14 13 N AI STARTI Polarity AI START2 Polarity AI START2 Sync AI START2 Edge AI START2 Select AI START2 Select AI START2 Select AI START2 Select AI START2 Select AI STARTI Sync AI STARTI Edge AI STARTI Select AI STARTI Select AI STARTI Select AI STARTI Select AI STARTI Select AO BC Load A Registers Address 44 Type Write only 15 14 13 N _ Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Loa
209. AO ADDR hold from CPUDACWR 3 12 timing values are in nanoseconds Figure 3 19 Decoded Signal Timing The numbers in parentheses for DACWR lt 0 1 gt National Instruments Corporation 3 95 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 3 7 7 Local Buffer Mode Timing The DAQ STC supports a local buffer mode for analog output which reduces analog output bus usage to zero The desired waveform is written into the data FIFO and the buffer is repeated a number of times The primary signals are UPDATE TMRDACWR AO lt 0 3 gt AOFFRT and AOFEF The UPDATE TMRDACWR and AO ADDR O 3 signals operate identically to the basic analog output case The AOFEF signal is the data FIFO empty flag and the AOFFRT signal asserts the retransmit signal on the FIFO When the FIFO becomes empty the DAQ STC asserts the AOFFRT signal which sets the FIFO read pointer back to the first location of the FIFO The waveform can then be output again as shown in Figure 3 20 DAQ STC Technical Reference Manual 3 96 National Instruments Corporation Chapter 3 Analog Output Timing Control UPDATE SRC X JJ X y XY VS Nf OUT CLK SVV VVV VVV VVV VVV VVV VVA UPDATE SRC lp Tcupd Tcupd Toup UPDATE OUT Up Tctwr Tctwr Twr Twr TMRDACWR AOFE
210. AQ STC Technical Reference Manual 1 6 programming See analog output programming simplified model 3 4 to 3 5 specifications A 1 timing diagrams 3 84 to 3 108 counter outputs 3 107 to 3 108 CPU driven analog output timing 3 88 DAQ STC and CPU driven analog output timing 3 90 to 3 92 DAQ STC driven analog output timing 3 86 to 3 88 decoded signal timing 3 94 to 3 95 external trigger timing 3 102 to 3 104 local buffer mode timing 3 96 to 3 97 maximum update rate timing 3 101 to 3 102 secondary analog output timing 3 93 signal definitions 3 84 to 3 86 trigger output 3 104 to 3 107 unbuffered data interface timing 3 98 to 3 100 trigger selection and conditioning 3 114 to 3 116 edge detection 3 116 EXT GATE and EXT GATE2 routing logic figure 3 115 PFI selectors table 3 115 to 3 116 START routing logic figure 3 115 synchronization 3 116 trigger signals 3 116 TRIG DRIVE signal table 10 9 ANALOG TRIG IN HI signal table 10 9 ANALOG TRIG IN LO signal table 10 9 analog trigger circuit 10 3 to 10 6 high hysteresis mode figure 10 5 high window mode figure 10 4 low hysteresis mode figure 10 6 low window mode figure 10 4 National Instruments Corporation middle window mode figure 10 5 programming 10 12 Analog Trigger Drive bit 10 12 Analog Trigger Enable bit 10 13 Analog Trigger Mode bit 10 13 ADDR O 3 signal CPU driven analog output 3 6 to 3 7 CPU dr
211. ART Interrupt 10 AO UPDATE Interrupt 9 AO STARTI Interrupt Ack 8 AO BC TC Interrupt Ack 7 AO UC TC Interrupt Ack 6 AO UD TC Interrupt Ack 5 AO UD TC Error Confrim 4 AO BC TC Error Confirm 3 AO BC TC Trigger Error Confirm 2 TC Error Confirm 1 Gate Error Confirm 0 Reserved Interrupt Control Register Address 59 Type Write only 15 Interrupt B Enable 14 Interrupt Output Select 13 Interrupt B Output Select 12 Interrupt Output Select 11 Interrupt Enable 10 Interrupt A Output Select 9 Interrupt Output Select 8 Interrupt A Output Select 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Pass Thru 0 Interrupt Polarity 2 Pass Thru 1 Interrupt Polarity 1 Interrupt Output On 3 Pins O Interrupt Output Polarity DAQ STC Technical Reference Manual B 34 Address 75 _ 95 WHR 5 HRN Address 57 gt NW 4 tA Interrupt B Enable Register Type Write only Reserved Reserved Reserved Reserved Pass Thru 1 Interrupt Enable Gate Interrupt Enable TC Interrupt Enable FIFO Interrupt Enable AO UD Interrupt Enable AO UC Interrupt Enable AO Error Interrupt Enable AO STOP Interrupt Enable AO START Interrupt Enable AO UPDATE Interrupt Enable AO STARTI Interrupt Enable AO BC TC Interrupt Enable
212. ASICS received the same STARTI trigger independently because different ASICs may synchronize differently In master slave triggering all DAQ STC AOTM modules are timed from a common source The master ASIC delays recognition of the STARTI trigger by one source period to allow the slave ASICs adequate time to receive the trigger On the National Instruments Corporation 3 15 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control following source edge all of the ASICs simultaneously begin the programmed waveform generation Master slave triggering can be used with any of the buffer timing modes previously discussed 3 4 6 Secondary Analog Output A secondary independent update interval output is controlled by a 16 bit binary down counter UI2 with dual load registers The analog output group served by 0012 is an interrupt driven group All the parameters except gating for the second independent update output trigger update count buffer count and addressing are handled in software 3 9 Pin Interface The I O signals relevant to the analog output are listed in Table 3 1 An asterisk following a pin name indicates that the default polarity for that pin is active low Pin Type Notation IU Input pull up 50 O4TU Output 4 mA sink 2 5 mA source tri state pull up 50 kQ O9TU Output 9 mA sink 5 mA source tri state pull up 50 kQ Table 3 1 Pin Interface Pin Name Type Description
213. ATE TMRDACWR XC X2X 4 5 9 ADDR 3 0 0 AOFEF AOFREQ Figure 3 5 FIFO Data Interface The DAQ STC also supports a local buffer mode for analog output which reduces analog output bus usage to zero In local buffer mode the desired waveform is written into the data FIFO and the FIFO contents are repeated a number of times The AOFEF signal notifies the DAQ STC that the data FIFO is empty and the AOFFRT signal instructs the data FIFO to retransmit its data When the FIFO becomes empty the DAQ STC asserts the AOFFRT signal which sets the FIFO read pointer back to the first location of the FIFO The waveform can then be output again Figure 3 6 shows an example of the local buffer mode with two iterations of a single buffer The buffer contains three data points so assume that the CPU writes three data values into the data FIFO The TMRDACWR signal transfers data from the data FIFO to the DACs After three data points are transferred the AOFEF asserts causing the AOFFRT signal to pulse This refills the FIFO with the same three data points for the next iteration of the buffer In Figure 3 6 the TC UC counter signal pulses at the end of each buffer The relationship between the UPDATE pulses and the UC counter is discussed in section 3 4 5 Buffer Timing and Control for Primary Analog Output National Instruments Corporation
214. Analog Output Application 1 3 Figure 1 3 DAQ STC Block Diagram seen enn 1 4 Figure 2 1 Typical Analog Input Waveform 2 4 Figure 2 2 AITM Simplified Model 2 5 Fisure 223 Control nee ient eH ee 2 7 Figure 2 4 Configuration FIFO Control 2 8 Figure 2 5 External Multiplexer 2 9 Figure 2 6 Internal CONVERT eee 2 10 Figure 2 7 External CONVERT 2 11 Figure 2 8 Internal 8 0 2 12 Ligure 2 9 External START RR GER RE aee 2 13 Figure 2 10 SI Special Trigger Delay seen 2 13 Figure 2 11 Posttrigger Acquisition sse 2 14 Figure 2 12 Pretrigger Acquisition 2 15 Figure 2 13 Free Run Gating 2 17 Figure 2 14 Halt Gating 2 18 Figure2 15 Smgle Wire Mode oie eere e e ient ee 2 18 Figure 2 16 Basic Analog Input eese 2 86 Figure 2 17 FIFO TININ S e s RE RES 2 88 Figure 2 18 Configuration Memory 2 89 Figure 2 19 Maximum Rate Analog Input 2 92 Figure 2 20 External CONVERT SRC 2 93 Figure 2 21 External Trigger Timing Asynchronous Level 2 94 National Instruments Corporation XV DAQ STC Technical Reference Manual Contents Figure 2 22 Figure 2 23 Figure 2 2
215. Appendix B Register Information National Instruments Corporation 6 3 DAQ STC Technical Reference Manual Chapter 6 RTSI Trigger RTSI Board Output Select 0 bits lt 0 2 gt type Write in RTSI Board Register address 81 i i bits lt 3 5 gt type Write in RTSI Board Register address 81 i 2 bits 6 8 type Write in RTSI Board Register address 81 i 3 bits lt 9 11 gt type Write in RTSI Board Register address 81 This bitfield selects the signal appearing on the RTSI BRDi pin if the pin is configured for output 0 6 RTSI lt 0 6 gt 7 Ifi 0 1 output the analog input STOP signal Ifi 2 3 output the same signal that is selected to be output on the PFI7 AI START pin Related bitfields RTSI Board Pin Dir AI START Output Select RTSI Board 7 Pin Dir i 0 bit 12 type Write in RTSI Board Register address 81 i l bit 13 type Write in RTSI Board Register address 81 i 2 bit 14 type Write in RTSI Board Register address 81 i 3 bit 15 type Write in RTSI Board Register address 81 This bit selects the direction of the bidirectional pin RTSI_BRDi 0 Input 1 Output RTSI Clock Mode bits lt 0 1 gt type Write in RTSI Trig Direction Register address 58 This bitfield selects the internal timebase by specifying the way the OSC and the RTSI OSC pins are used 0 The signal from the OSC pin will be used as the internal timebase The RTSI OSC pin will not be confi
216. C Related bitfields AI START2 Select DAQ STC Technical Reference Manual 2 80 National Instruments Corporation Chapter 2 Analog Input Timing Control STOP Edge bit 12 type Write in AI START STOP Select Register address 62 This bit enables edge detection of the STOP trigger 0 Disabled level sensitive trigger 1 Enabled edge sensitive trigger You should set this bit to 0 if STOP Select is set to 31 or if you want single channel operation You should set this bit to 1 if STOP Select is set to 0 Related bitfields AI STOP Select STOP Interrupt Ack bit 12 type Strobe Interrupt Ack Register address 2 Setting this bitto 1 clears AI STOP St and acknowledges the STOP interrupt request either interrupt bank if the STOP interrupt is enabled This bit is cleared automatically Related bitfields STOP St STOP Interrupt Enable bit 4 type Write in Interrupt Enable Register address 73 This bit enables the STOP interrupt 0 Disabled Enabled The STOP interrupt is generated on valid STOP triggers recognized by the DAQ STC A valid STOP trigger is one that is received while the SC counter is enabled to count yet after a valid START PAS Caution You must use the STOP interrupt in conjunction with the START interrupt otherwise the STOP interrupt does not execute STOP Polarity bit 14 type Write in AI START STOP Select Register address 62 This bit
217. C masks off the last UPDATE pulse to prevent an undesired output DAQ STC Technical Reference Manual 3 120 National Instruments Corporation Chapter 3 Analog Output Timing Control AB DA STARTI 24 AO BC Am i i G BC TC H AO End On BC TC 1 AO End On UC TC 2227471 J AO Continuous KT a K TRANS N AO Trigger Once CNT T i 1 K T TRANS SCKG STOP BC LOAD G K AO BC Load BC CE B K GATE CNT n CNT n 1 DISARM CNT n WAIT n 1 1 Figure 3 39 BC Control Circuit State Transitions 3 8 3 7 2 Counter The UI2 counter is a 16 bit down counter with dual load registers The UI2 counter is intended to be used in interrupt driven waveform generation The bitfield UI2 Source Select controls the UI2 SRC The choices for UI2 source are AO IN TIMEBASEI PFI lt 0 9 gt RTSI_TRIGGER lt 0 6 gt andIN TIMEBASE2 The bitfield UI2 Source Polarity selects the polarity of the source clock The counter load registers are directly accessible from the register map If the counter is disarmed UI2 Load will load the counter with the value from the selected load register During normal operation the UI2 counter will synchronously reload from the selected load register following UI2 TC The counter has the option UI2 Reload Mode to alternate load registers once after every STOP The UI2 control circuit generates the count enable signals
218. C revision information 0 Fast CPU bit 13 type Write in AO Personal Register address 78 This bit determines how long the DAQ STC deasserts CHRDY OUT following the assertion of CPUDACREQ during CPU driven analog output 0 Until the end of CPUDACWR 1 Until the start of CPUDACWR Select option 0 for slow CPU interfaces and option 1 for fast CPU interfaces Note This bit also determines how long the DAQ STC deasserts CHRDY OUT following the assertion of AOFEF during DAQ STC driven analog output in the unbuffered data interface mode 0 FIFO Empty St bit 12 type Read in AO Status 1 Register address 3 This bit reflects the state of the AOFEF input signal after the polarity selection which indicates the data FIFO status 0 Notempty Empty Related bitfields FIFO Flags Polarity 0 FIFO Enable bit 10 type Write in AO Personal Register address 78 This bit enables the TMRDACWR output signal to generate pulses after each UPDATE 0 Disabled 1 Enabled You should set this bit to 0 if there is no data FIFO on your board In this case you can use TMRDACWR as a DMA request Related bitfields AO DMA PIO Control National Instruments Corporation 3 55 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 FIFO Flags Polarity bit 11 type Write in AO Personal Register address 78 This bit selects the polarity of the data FIFO flags input signals AOFFF AOFHF an
219. CLK pulse In this mode the software must be careful not to exceed the maximum data transfer rate of the receiving device or data loss may result Figure 7 3 shows a parallel output operation where the external device receives a new data byte on each EXTSTROBE SDCLK falling edge The DAQ STC transmits the data bytes 0x55 and OxAA hex EXTSTROBE SDCLK i DIO lt 7 0 gt 0x55 OxAA SW UPDATE SW UPDATE Figure 7 3 Parallel Output National Instruments Corporation 7 3 DAQ STC Technical Reference Manual Chapter 7 Digital 1 0 1 4 2 Serial Mode In serial mode the DAQ STC exchanges 8 bit wide data with an external device through two serial pins one for each direction Three sources are available for timing the serial data transfers a 1 2 us clock 10 us clock and a software controlled clock The external device receives timing from the DAQ STC through the output EXTSTROBE SDCLK 1 4 2 1 Serial Input In serial input mode an external device transfers 8 bit serial data to the DAQ STC through the DIO4 SDIN line Software configures the external device to place a new data bit on the DIO4 SDIN line after each EXTSTROBE SDCLK falling edge and selects EXTSTROBE SDCLK to be one of the periodic timebases The DAQ STC clocks data from the DIO4 SDIN line on each EXTSTROBE SDCLK rising edge This arrangement allows data line adequate time to stabilize before reading The DAQ STC only generates enough pulses on E
220. CONVERT advances the configuration FIFO At the leading edge of the final LOCALMUX the configuration FIFO becomes empty causing MUXFEF to assert When MUXFEF asserts LOCALMUX FFRT pulses on the trailing edge of LOCALMUX causing the configuration FIFO to reload the entire configuration list Figure 2 4 shows the operation of these signals during two scans where each scan contains four channels LOCALMUX CLK EXTMUX L LOCALMUX FFRT CONVERT DIV Counter MUXFEF Figure 2 4 Configuration FIFO Control In addition to supporting the configuration FIFO the DAQ STC also supports an external multiplexer Typically analog input boards are limited to eight or 16 input channels An external multiplexer overcomes this limitation by time division multiplexing several analog signals onto each input channel Each memory location in the configuration FIFO corresponds to one input channel With an external multiplexer the configuration FIFO does not advance until all the external channels have been sampled for a given input channel The EXTMUX CLK signal is available to advance the external multiplexer To use the DAQ STC with an external multiplexer you load the DIV counter with the number of external channels corresponding to each input channel The EXTMUX signal pulses on every CONVERT but the LOCALMUX
221. D External Gate Polarity 0 active high high enables operation or active low low enables operation Else AO_UI2_External_Gate_Enable 0 End critical section National Instruments Corporation 3 39 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 3 6 6 5 Software Gate Operation To use the software gate issue the following commands e pause secondary analog output AO UD Software Gate 1 e To resume secondary AO after pause AO UD Software Gate 0 Note Software and hardware gating can be used simultaneously without any special setup The secondary analog output operation proceeds when both hardware and software gates are not in the pause state 3 6 6 6 Counting for Waveform Staging Use this function to initialize the counter for waveform staging The variable 2 tick count to use introduced in this function will be used later in the waveform staging A02 Staged ISR function Function AO2 Counting Begin critical section Declare variable ao2_tick_count_to_use Indicates the parameter in the array that should be used If waveform staging then ao2_tick_count_to_use 1 Else ao2_tick_count_to_use 0 End critical section 3 6 6 7 Update Selection Use this function to select the update event For waveform staging operation it is assumed that the parameters for each stage are stored in an array defined as follows ui2_ticks Contains the number
222. D Next Load Source St bit 3 77 AO UD Reload Mode bit 3 77 AO UD Save Value bit 3 77 AO UD Software Gate bit 3 78 AO UD Source Polarity bit 3 78 AO UD Source Select bit 3 78 AO UD Switch Load Next TC bit 3 78 AO 12 TC Error Confirm bit 3 78 AO UD TC Hrror St bit 3 79 AO UD Interrupt bit 3 79 AO UD Interrupt Enable bit 3 79 AO UD TC Second Enable bit 3 79 AO UD TC St bit 3 79 AO UPDATE Interrupt bit 3 81 AO UPDATE Interrupt Enable bit 3 81 AO UPDATE Original Pulse bit 3 82 AO UPDATE Output Select bit 3 82 National Instruments Corporation I 9 Index AO UPDATE Pulse bit 3 82 AO UPDATE Pulse Timebase bit 3 83 AO UPDATE Pulse Width bit 3 83 AO UPDATE Second Irq Enable bit 3 83 AO UPDATE Source Polarity bit 3 83 AO UPDATE Source Select bit 3 84 AO UPDATE St bit 3 84 UPDATE2 Original Pulse bit 3 80 AO UPDATE2 Output Select bit 3 80 AO UPDATE2 Output Toggle bit 3 80 UPDATE2 Pulse bit 3 80 AO UPDATE2 Pulse Timebase bit 3 81 AO UPDATE2 Pulse Width bit 3 81 AO Updating function 3 26 to 3 28 AO2 Arming function 3 40 2 Board Personalize function 3 39 AO2 Counting function 3 40 AO2 Hardware Gating function 3 39 AO2 Rate Change function 3 44 to 3 45 2 Reset function 3 38 AOFEF signal DAQ STC driven analog output timing 3 86 to 3 88 description table 3 16 FIFO data interface 3 9 local buffer mod
223. DACWR and CPUDACWR are being used Figure 3 15 shows the basic timing involved in CPU driven analog output Both modes of CHRDY OUT are shown demonstrating the savings in bus bandwidth National Instruments Corporation Chapter 3 Analog Output Timing Control NL MODE 0 CPUDACREQ ____ X py n Tregchrdy gt Tregchrdy gt Tewrchrdy CHRDY OUT M Tccwrd Tecwrd Tecwr Tecwr E CPUDACWR 1 CPUDACREQ D N 2 Tregchrdy Tewrcrdy CHRDY A N o Tccwrd 1 e Tccwrd Tecwr Tecwr or CPUDACWR Tah N ADDR 0 3 X X X X Name Description Minimum Maximum Treqchrdy CPUDACREQ to CHRDY_OUT asserted 4 12 Tewrcrdy CPUDACWR to CHRDY_OUT deasserted 11 5 Tecwr OUT CLK to CPUDACWR asserted 14 15 43 47 Tcwr CPUDACWR pulsewidth 2 3 2 3 Tccwrd OUT CLK to CPUDACWR deasserted 14 12 44 37 Tas ADDR O 3 setup to CPUDACWR 2 3 5 9 Tah ADDR O 3 hold from CPUDACWR 2 3 5 12 All timing values are in nanoseconds Figure 3 15 CPU Driven Analog Output Timing National Instruments Corporation 3 89 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control
224. DAQ DAQ STC Technical Reference Manual System Timing Controller for Data Acquisition Wy NATIONAL January 1999 Edition y INSTRUMENTS Part Number 340934B 01 Internet Support E mail support8natinst com FTP Site ftp natinst com Web Address http www natinst com Bulletin Board Support BBS United States 512 794 5422 BBS United Kingdom 01635 551422 BBS France 01 48 65 15 59 Fax on Demand Support 512 418 1111 Telephone Support USA Tel 512 795 8248 Fax 512 794 5678 International Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 288 3336 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 520 2635 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 Taiwan 02 377 1200 United Kingdom 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin Texas 78730 5039 USA Tel 512 794 0100 Copyright 1995 1998 National Instruments Corporation All rights reserved Important Information Warranty Copyright Trademarks The DAQ STC is warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receip
225. DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control In the continuous mode the DAQ STC provides UPDATE timing for more than one MISB Since each counter has two load registers the two MISB case can be handled directly in hardware For more than two MISBs software intervention is required to load the parameters for each MISB during the output of the previous MISB For example in the three MISB case software must load the parameters for MISB three during MISB two This software intervention is called waveform staging Refer to section 3 4 5 3 Waveform Staging for more information The STARTI trigger initiates the analog output Figure 3 12 shows an example of two MISBs in continuous mode The first MISB contains two iterations of a two point buffer The second MISB contains one iteration of a four point buffer Note that the UPDATE pulses for the second MISB occur at a lower rate than the UPDATE pulses for the first MISB This type of waveform is possible in the internal UPDATE mode because the UI counter can be programmed with a new value for each MISB Also note that the DAQ STC defines the UPDATE interval to last from the beginning of the current UPDATE to the beginning of the next UPDATE Thus the interval between the fourth UPDATE and the fifth UPDATE corresponds to the UPDATE interval for MISB 1 rather than the UPDATE interval for MISB 2
226. DIO_Serial_Data_In_St bits lt 0 7 gt type Read in DIO_Serial_Input_Register address 28 This bitfield is used for serial digital input on DIO4 Do not attempt to read from this register while serial digital I O is in progress Related bitfields DIO_Serial_IO_In_Progress DIO Serial Data Out bits lt 8 15 gt type Write in DIO Output Register address 10 This bitfield is used for data to be serially output on DIOO DAQ STC Technical Reference Manual 7 14 National Instruments Corporation Chapter 7 Digital 1 0 DIO Serial IO In Progress St bit 12 type Read in Joint Status 1 Register address 27 This bit indicates whether the first seven bits of serial digital I O is in progress 0 Indicates that operation is not in progress or that the last bit is being shifted out 1 Indicates that one of the first seven bits is being shifted out Note that after this bit changes from 1 to 0 there is still one more bit of data to be shifted in out You must wait one more serial clock period for the operation to finish which for example can be performed by a software delay loop or OS provided function DIO Serial Out Divide By 2 bit 13 type Write in Clock and FOUT Register address 56 Divide the clock used for serial digital I O timing by 2 provided hardware timing is used 0 No SERIAL TIMEBASE is IN TIMEBASE 1 Yes SERIAL TIMEBASE is IN TIMEBASE divided by 2 DIO Software Serial Control bit 11 type Write in
227. DOO CO eK 15 14 13 N _ 1 Appendix Register Information AI SC Load B Registers Address 20 Type Write only Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Load B AI SC Save Registers Address 66 Type Read only Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AI SC Save Value AI SC Save Value AI Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI Save Value DAQ STC Technical Reference Manual Appendix B 15 14 13 j N DOO CO 15 14 13 N _ Register Information AI SC Save Registers Address 67 Type Read only AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SC Save Value AI SI Load A Registers Address 15 Type Write only AI SI Load A AI SI Load A AI SI Load A AI SI Load A AI SI Load A AI SI Load A AI SI Load A AI SI Load A AI SI Load A AI SI Load A AI SI Load A AI SI L
228. EL lt 0 4 gt SHIFTIN SI DAQ STC Technical Reference Manual seconds samples scan counter scan in progress signal internal sample clock signal internal update signal internal sample clock signal SC count enable signal SC clock signal SC counter gate signal SC hold signal SC load signal SC load source signal SC source signal START signal synchronized to SC RC SC counter TC signal Signal Conditioning eXtensions for Instrumentation secondary interrupt output for interrupt group A secondary interrupt output for interrupt group B select signal channels 0 through 4 data shift pulse signal 24 bit scan interval counter G 10 National Instruments Corporation 50 50 512 50 LOAD 512 LOAD 512 50 SI CE SI CLK SI DISARM SI HOLD SI LOAD SI LOAD SRC SI SRC SI STARTI SI TC SOC START STARTI START2 5 5 lt 0 3 gt 5 STST SW National Instruments Corporation Glossary 16 bit scan interval counter SD count enable signal SD clock signal SD load signal SD load source signal SD source signal SD counter TC signal SI count enable signal SI clock signal SI disarm signal SI hold signal SI load signal SI load source signal SI source signal STARTI synchronized to SI SRC signal SI counter TC signal start of conversion signal start scan signal start trigger signal stop trigger used by the SC counter in the pret
229. ERO RTSI TRIGGERI RTSI TRIGGER2 RTSI TRIGGER3 RTSI TRIGGER2 RTSI TRIGGER3 RTSI 4 RTSI 5 Miscellaneous Functions The OUTO RTSI OUT OSC and TEST IN pins are not included in the internal gate tree 10 7 Pin Interface The I O signals related to the Miscellaneous Functions are listed in the following table An asterisk following a pin name indicates that the default polarity for that pin is active low Pin Type Notation IU Input pull up 50 O4TU Output 4 mA sink 2 5 mA source tri state pull up 50 kQ IS Input TTL Schmitt trigger O9TU Output 9 mA sink 5 mA source tri state pull up 50 kQ 09 Output 9 mA sink 5 mA source Table 10 3 Pin Interface Pin Name Type Description ANALOG TRIG DRIVE O4TU Analog Trigger Drive This pin controls whether the board s trigger line should be output or input This bit is driven directly from a control register on the DAQ STC Related bitfield Analog Trigger Drive ANALOG TRIG IN HI IU Analog Input Trigger High Voltage Reference This pin indicates that the analog trigger waveform has exceeded the HI voltage reference Source This input is typically fed from an analog comparator on the board ANALOG TRIG IN LO IU Analog Input Trigger Low Voltage Reference This pin indicates that the analog trigger waveform has dropped below the LOW voltage reference Source This
230. ERT SRC to BRD output START 15 53 Tscan CONVERT SRC to SCAN IN PROG 15 54 Tspfi CONVERT SRC to PFI output 15 54 SCAN IN PROG Tsbrd CONVERT SRC to BRD output 17 58 SCAN IN PROG timing values are in nanoseconds Figure 2 34 START Delays External CONVERT DAQ STC Technical Reference Manual 2 102 National Instruments Corporation Chapter 2 Analog Input Timing Control 2 1 8 3 SCAN IN PROG Deassertion You can output SCAN IN PROG on the SCAN pin PFI7 AI START or the RTSI lt 2 3 gt outputs If AI External Present is 0 SCAN PROG deasserts the SOC edge that occurs while STOP is asserted If External Mux Present is 1 SCAN IN PROG deasserts on the SOC edge that occurs while STOP and DIV TC are both asserted Figure 2 35 shows the behavior of the SCAN PROG outputs during deassertion STOP N SOC Tscan SCAN IN PROG Tpfi PFI7 AI START Tsbrd RTSI lt 2 3 gt Name Description Minimum Maximum Tscan SOC to SCAN IN PROG 8 26 Tpfi SOC to PFI output 8 27 Tsbrd SOC to BRD output 9 31 timing values are in nanoseconds 2 1 8 4 STOP Trigger Figure 2 35 SCAN PROG Deassertion You can output the STOP trigger on the dedicated output AI STOP OUT or on the RTSI BRD O 1 pins The timing for STOP depends on whether you select synchronous mode or asynchronous m
231. F JT T P Tcrtd Twrrt gt Tdafrt AOFFRT TA Name Description Minimum Maximum Tcup UPDATE SRC to UPDATE asserted 18 56 Tsup UPDATE SRC pulsewidth 1 1 Toup UPDATE OUT pulsewidth 1 3 1 5 3 5 Tcupd OUT CLK to UPDATE OUT deasserted 12 38 Tctwr OUT CLK to TMRDACWR asserted 11 34 TMRDACWR pulsewidth 2 3 2 3 Twrrt TMRDACWR to AOFFRT asserted 2 6 Tdafrt AOFFRT pulsewidth 1 1 Tertd OUT to AOFFRT deasserted 10 32 timing values are in nanoseconds The numbers in parentheses refer to the number of clock periods that occur at the minimum Figure 3 20 Local Buffer Mode Timing and maximum delays because those parameters are clock edge driven with possible additional gate delays AOFEF is recognized by the DAQ STC at the trailing edge of the TMRDACWR signal This leads to the assertion of AOFFRT which is deasserted on the next rising edge of the output clock National Instruments Corporation DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 3 7 8 Unbuffered Data Interface Timing The DAQ STC provides support for low cost DAQ boards that do not contain analog output data FIFOs A basic application could simply use the CPU driven examples given above but this wastes the host CPU resources The DAQ STC provides a DMA mode of operation where the FIFOs can be omitted Due to the pinout restriction on the DAQ STC several of the pins provide dual fu
232. Figure 3 18 Figure 3 19 Figure 3 20 Figure 3 21 Figure 3 22 Figure 3 23 Figure 3 24 Figure 3 25 Figure 3 26 Figure 3 27 Figure 3 28 Figure 3 29 Figure 3 30 Figure 3 31 Figure 3 32 Figure 3 33 Figure 3 34 Figure 3 35 Figure 3 36 Figure 3 37 Figure 3 38 Figure 3 39 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 Contents Unbuffered Data 3 11 Internal UPDATE irte 3 12 External UPDATE essere 3 12 Single Buffer e rie eaten 3 13 Continuous Mode eer ietie oss 3 14 heme p PAoa iOS ESEESE iie 3 15 DAQ STC Driven Analog Output 3 87 CPU Driven Analog Output 3 89 Analog Output Contention Timing Case 3 91 Analog Output Contention Timing Case 2 2 3 02 Secondary Analog Output 3 93 Decoded Signal Timing iter De erg esate 3 95 Local Buffer Mode Timing 3 97 Unbuffered Data Interface 3 99 Maximum Update Rate 3 101 External Trigger Asynchronous Level 3 102 External Trigger Asynchronous 3 102 External Trigger Synchronous Level Internal UPDATE Mode 3 103 External Trigger Synchronous Edge Internal UPDATE Mode 3 103 External Trigger Synchronous
233. G SOURCE as a timebase to generate the pulse so you specify the pulse parameters in terms of periods of the G SOURCE input Software implements pulse generation by loading the delay value into the counter loading the pulsewidth value into the load register and programming the counter National Instruments Corporation 4 9 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer output OUT to change states on counter TC Figure 4 12 shows the generation of a single pulse with a pulse delay of four and a pulsewidth of three Software Arm G SOURCE Counter Value 3 3 2 1 0 2 1 0 Counter TC L G_OUT HE Figure 4 12 Single Pulse Generation 4 4 3 2 Single Triggered Pulse Generation Single triggered pulse generation is similar to single pulse generation except that provides a trigger function An active G_GATE edge following the software arm causes the counter to generate a single pulse with programmable delay and programmable pulsewidth You should specify the programmable parameters in terms of periods of the G SOURCE input Single triggered pulse generation is implemented in software by loading the delay value into the counter loading the pulsewidth value into the load register programming the counter output OUT to change states on counter TC and configuring to be the trigger signal Figure 4 13 shows th
234. GND Key AI STP The input AI STOP IN AI TBI The internal analog input signal AI IN TIMEBASEI GOUTO The G_OUT signal from general purpose counter 0 SW Software strobe TB2 The internal signal IN TIMEBASE2 National Instruments Corporation 2 121 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Note When the analog trigger circuit is enabled the analog trigger signal takes over the PFIO slot in the PFI selectors 2 8 2 1 Using Edge Detection Use edge detection whenever a clock period pulse of 1 is required but the pulsewidth of the trigger signal cannot be guaranteed Internally generated triggers are automatically the correct width and need not be edge detected Software strobes do not have the correct width and should always be edge detected Edge detection of external signals can usually be performed without affecting the circuit operation 2 8 2 2 Using Synchronization Use synchronization whenever the trigger to clock timing relationship cannot be guaranteed Internally generated triggers automatically have the correct timing and need not be synchronized Software strobes do not have the correct timing and should always be synchronized Synchronization of external signals results in a one half cycle synchronization delay 2 8 2 3 Trigger Signals START initiates an interval scanning operation in the pretrigger and posttrigger modes AI STARTI Sync AI 5 Edge and 5
235. I FIFO Mode AI Error Interrupt Interrupts are generated on the detection of an analog input overrun or overflow error condition AISC TC Interrupt Interrupts are generated on every SC falling edge unless the pretrigger acquisition mode is selected In the pretrigger acquisition mode the first 5 TC falling edge does not generate an interrupt but subsequent SC TC falling edges do AI STARTI Interrupt Interrupts are generated on valid STARTI triggers received by the AITM A valid STARTI trigger is one that is received while the SC counter is armed and in state The actual interrupt signal appears on the active edge of SC CLK AI START2 Interrupt Interrupts are generated on valid START2 triggers received by the AITM A valid START2 trigger is one that is received while the SC counter is in the WAIT2 state The actual interrupt signal appears on the active edge of SC_CLK AI START Interrupt Interrupts are generated on valid START triggers received by the AITM A valid START trigger is one that is received while the SC counter is enabled to count The actual interrupt signal appears on the active edge of SC_CLK AI STOP Interrupt Interrupts are generated on valid STOP triggers recognized by the AITM A valid STOP trigger is one that is received while the SC counter is enabled to count The actual interrupt signal appears on the active edge of SC_CLK Note that this interrupt must be used in conjunction wi
236. I Interrupt Ack 1 AO UPDATE Interrupt 1 AO START Interrupt Ack 1 AO STOP Interrupt Ack 1 AO Error Interrupt 1 AO Configuration End 1 End critical section Perform the Board Personalize programming function in order to bring the primary AO module of DAQ STC into a known state You can then program the primary AO module for any desired operation 3 6 1 3 Board Power up Initialization Use this function to program software selectable options in the primary analog output module of the DAQ STC that depend on the properties of the board or device the DAQ STC is on The options include polarity and pulsewidth of commonly used signals You need to execute this function every time after you invoke the AO Reset function and before you perform any analog output operation using the DAQ STC If you are programming a DAQ STC that is a part of a data acquisition system the document describing the register level programming for that system should contain information about the proper selections to make in this function DAQ STC Technical Reference Manual 3 22 National Instruments Corporation Chapter 3 Analog Output Timing Control Function AO Board Personalize Begin critical section AO_Configuration_Start 1 AO_Fast_CPU 0 slow CPU interface or 1 fast CPU interface AO_Source_Divide_By_2 0 AO_IN_TIMEBASE1 equals IN_TIMEBASE 1 AO TIMEBASEI is IN_TIMEBASE di
237. I STOP IN pin 31 Logic low Set this bit to 31 for single channel operation if your board does not have configuration memory Related bitfields AI STOP Pulse AI STOP St bit 4 type Read in AI Status 1 Register address 2 This bit indicates that a valid STOP signal has been received by the AITM 0 No 1 Yes A valid STOP trigger is one that is received while the SC counter is enabled to count yet after a valid START This bitis cleared by setting STOP Interrupt Ack to 1 Related bitfields AI STOP Interrupt Ack Refer to Table 8 2 Interrupt Condition Summary for more information DAQ STC Technical Reference Manual 2 82 National Instruments Corporation Chapter 2 Analog Input Timing Control STOP Sync bit 13 type Write AI START STOP Select Register address 62 This bit enables internal synchronization of the STOP trigger to the internal signal FSC_SRC 0 Disabled Enabled You should set this bit to 0 if the STOP is generated by a configuration memory on your board Otherwise you should set this bit to 1 unless you can guarantee synchronization by some other means You must set this bit to 1 if AI STOP Select is set to 0 Related bitfields AI STOP Sync Trigger Length bit 15 type Write in AI Mode 3 Register address 87 This bit determines the length of the signals appearing on the bidirectional pins PFIO AI STARTI and START when the pins are configured for output I
238. I lt 0 9 gt or 11 through 17 RTSI lt 0 6 gt or 18 IN TIMEBASE2 or 19 other G TC Gi Source Polarity 0 count rising edges or 1 count falling edges Gi Gate Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 AI START2 or 19 UI2 TC or 20 other TC or 21 STARTI or 31 logic low Gi OR Gate 0 Gi Output Polarity 0 active high or 1 active low Gate Select Load Source 0 National Instruments Corporation 4 19 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer Gi Gate Polarity 0 disable inversion or 1 enable inversion Gi Output Mode 1 one clock cycle output or 2 toggle on TC or 3 toggle on TC or gate Gi Loading On Gate 0 Gi Loading On TC 20 Gi Gating Mode 1 Gi Gate On Both Edges 0 Gi Trigger Mode For Edge Gate 2 Gi Stop Mode 0 Gi Counting Once 0 Up Down 0 down counting or 1 up counting Gi Bank Switch Enable 0 Gi Bank Switch Mode 0 Gi TC Interrupt Enable 0 Gi Gate Interrupt Enable 0 4 6 1 6 Buffered Event Counting Buffered event counting is an application in which a general purpose counter counts the edges of its source signal Progress of counting is observed by monitoring the counter contents at points of interest This is achieved by using the HW save register and interrupts We define two modes of operation for this application
239. IMEBASE or 1 TIMEBASE2 FOUT_Divider 0 for division factor 16 or 1 15 for division factor 1 15 L FOUT Enable 1 The directives Begin critical section and End critical section mark the beginning and end of critical sections in the ensuing pseudocode All statements under these directives must be synchronized with the ISRs in other words while the code fragment under these directives is executing in the foreground all interrupt time specific code must be prevented from executing in the background Under some single tasking operating systems such as DOS the directives Begin critical section and End critical section directly map to CLI and STI assembly language instructions respectively However other operating systems may require specific primitives to achieve this functionality 2 6 3 1 Resetting Assume the AITM was set up to perform an unknown operation The object is to stop any activities in progress Function AI Reset 11 Begin critical section AI Reset 1 ps AI_Configuration_Start 1 gt AI SC TC Interrupt Enable 0 AI STARTI Interrupt Enable 0 AI STARTO2 Interrupt Enable 0 AI START Interrupt Enable 0 AI STOP Interrupt Enable 0 AI Error Interrupt Enable 0 AI Interrupt Enable 0 L AI_SC_TC_Error_Confirm 1 AI SC TC Interrupt Ack 1 AI STARTI Interrupt Ack 1 AI STARTO2 Interrupt 1 AI START Interrupt 1 AI STOP Interrupt Ack 1
240. If new_ticks is not 0 then AO_UI2_Load_B new_ticks 1 gt AO UD Switch Load Next 1 Else Load maximal count in an attempt to avoid getting an unnecessary UI2 TC error AO_UI2_Load_B OxFFFF gt UD Switch Load Next 1 ao2 last load register B Else If new_ticks is not 0 then AO_UI2_Load_A new_ticks 1 AO UD Switch Load Next 1 Else AO_UI2_Load_A OxFFFF X AO UD Switch Load Next 1 National Instruments Corporation 3 43 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control ao2 last load register AO UD Interrupt 1 Check for interrupt latency problem If AO 012 TC Error St is 1 then Inform user that a UI2_TC error has occurred AO_UI2_TC_Error_Confirm 1 This is optional 3 6 8 Changing Update Rate during an Output Operation for Secondary Analog Output Use this function to change the update rate during an output operation if you are not performing waveform staging The variable ao2_last_load_register keeps track of which load register should be used This variable was introduced in AO2_Updating function Function AO2 Rate Change If ao2_last_load_register is A If AO_UI2_Next_Load_Source_St is 0 then AO_UI2_Load_B number of clocks between updates 1 AO UD Switch Load Next 1 ao2 last load regist
241. If AI Pre Trigger is 0 the counters will return to idle on the first SC TC If AI Pre Trigger is 1 the counters will return to idle on the second SC TC 1 The counters will ignore SC TC Set this bit to 0 to select the pretrigger or posttrigger acquisition modes if you want to acquire a predetermined number of scans Set this bit to 1 to select the continuous acquisition mode if you wish to continuously acquire data or to perform staged analog input You can use AI End On End Of Scanand AI End On SC TC to stop an analog input operation in the continuous acquisition mode Related bitfields AI End On End Of Scan AI End On SC TC AI Pre Trigger National Instruments Corporation 2 49 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control CONVERT Original Pulse bit 9 type Write in AI Personal Register address 77 If AI CONVERT Pulse Timebase is 1 this bit determines the pulsewidth of the CONVERT and PFI2 CONV signals The pulsewidth of the CONVERT signals is 0 Equal to the pulsewidth of the signal used to generate the CONVERT signal with the maximum pulsewidth determined by AI CONVERT Pulse Width 1 Equal to the pulsewidth of the signal used to generate the CONVERT signal Related bitfields AI CONVERT_Pulse_Timebase AI CONVERT Pulse Width CONVERT Output Select bits lt 0 1 gt type Write in AI Output Control Register address 60 This bit enables and selects the polarity of the
242. Interface Continued Pin Name Type Description CPUDACREQ IU CPU Request for Access to the DAC This active low input indicates that the CPU is attempting a write cycle to the DAC The assertion of CPUDACREQ causes OUT to be deasserted immediately When the DAC becomes available the DAC STC fulfills the CPU request by passing the lowest four bits of the address lines A lt 0 3 gt onto the DAC address lines AO ADDR lt 0 3 gt and pulsing CPUDACWR signal CHRDY OUT is released when the write completes Source CPU bus interface CPUDACWR O4TU CPU Write to the DAC This active low output serves as the DAC write signal generated by the CPU The CPUDACWR signal pulses once following the assertion of CPUDACREQ Timing for CPUDACWR is based on AO_OUT_TIMEBASE and the pulsewidth is selectable Destination DACs Related Bitfields AO TMRDACWR Pulse Width DACWR lt 0 1 gt O4TU DAC Write Strobes These pins serve as write strobes for DACs combining the TMRDACWR and CPUDACWR signals In the single DAC mode DACWRO pulses on every write to an even channel and DACWRI pulses on every write to an odd channel In the dual DAC mode DACWRO pulses on every write and DACWRI is not used Output polarity is active low Destination DACs Related bitfields AO Number Of DAC Packages AO TMRDACWR Pulse Width LDAC lt 0 1 gt O4TU DAC Load These pins serve as DAC updates in the double buffered DAC case Two
243. LKG 3 The internal analog output signal DACUPDN 4 The internal analog output signal STARTI 5 The SRC signal from general purpose counter 0 6 The GATE signal from general purpose counter 0 7 RGOUTO see RTSI Sub Selection 1 8 11 The signal present at the RTSI BRD pin 0 3 The four RTSI BRD pins provide a mechanism for additional board level signals to be sent on or received from the RTSI bus Configured as an input each bidirectional RTSI BRD pin can drive any of the seven RTSI TRIGGER pins Configured as an output each pin can be driven by any of the seven RTSI TRIGGER pins RTSI BRD O 1 can also be driven by AI STOP RTSI_BRD lt 2 3 gt can also be driven by the AI START and SCAN PROG signals Tables 6 3 6 4 summarize the available output selections on RTSI_BRD lt 0 3 gt DAQ STC Technical Reference Manual 6 6 National Instruments Corporation Chapter 6 RTSI Trigger Table 6 3 RTSI_BRD lt 0 1 gt Output Selections RTSI Board Output Select SIGNAL 0 6 The signal present at the RTSI TRIGGER pin 0 6 7 AI STOP Table 6 4 RTSI BRD 2 3 Output Selections RTSI Board Output Select SIGNAL 0 6 The signal present at the RTSI TRIGGER 0 6 7 If AI START Output Select is O this pin is defined as follows If AI Trigger Length is 0 this pin reflects the internal signal AD START If AI Trigger Length is 1 this pin reflects
244. LOAD 512 Load 52 CE AI SI2 Arm CNT1 n 1 521 DISARM CNT n WAIT1 n 1 1 Figure 2 51 512 Control Circuit State Transitions 2 8 3 7 DIV Counter The DIV counter is a 16 bit down counter The DIV counter typically divides down LOCALMUX CLK when an external multiplexer is used The DIV counter uses the same clock that is selected for the SC counter SC SRC The counter load register is directly accessible from the register map If the counter is disarmed DIV Load will load the counter with the value from the load register During normal operation the DIV counter will synchronously reload from the load register following DIV TC The DIV control circuit generates the count enable signals DAQ STC Technical Reference Manual 2 128 National Instruments Corporation Chapter 2 Analog Input Timing Control 2 8 3 8 DIV Control The DIV counter is controlled by a circuit whose state transitions are shown in Figure 2 52 The DIV counter control circuit has two states WAIT and CNT On power up the control circuit begins in state WAIT and remains there until the counter is armed and a STARTI pulse is received When these two events occur the counter moves to the CNT state and begins counting On DIV TC the counter either remains counting or returns to the WAIT state depending on the signals STOP SCKG AI End On End Of Scan AI End On SC TC SC AI Continuous and Trigger Once For continuous
245. National Instruments Corporation A 3 DAQ STC Technical Reference Manual Appendix A Specifications High level output current IoH 0 4 V Pin Type Value O4TU 2 5 mA min B9TU O9TU O9 5 0 mA min B18TU 13 0 mA min Note VDD 5 V 10 TA 40 to 85 Low level output voltage lor m om diocesis 0 1 V max High level output voltage Iog s OMA 0 1 V min Note VDD 5 10 TA 40 to 85 C DAQ STC Technical Reference Manual A 4 National Instruments Corporation Register Information This appendix contains information about the DAQ STC registers and bitfields Note The addresses supplied in the following tables are in terms of 16 bit words Your DAQ board may access the STC in terms of bytes For example AI Command 2 Register is address 4 in terms of 16 bit words but is address 8 in terms of 8 bit words Refer to your appropriate RLPM for specific address information Table B 1 DAQ STC Registers Register Name Type Address Hex Address AI Command 1 Register Write 8 0x08 AI Command 2 Register Write 4 0x04 AI DIV Load A Register Write 64 0x40 AI DIV Save Register Read 26 OxlA AI_Mode_1_Register Write 12 0x0C AI Mode 2 Register Write 13 OxOD AI Mode 3 Register Write 87 0x57 AI Output Control Register Write 60 0 3 AI Personal Register
246. O CO eK Address 56 15 14 13 N _ 2 Appendix Register Information AO UI Save Registers Type Read only Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value AO UI Save Value Clock and FOUT Register Type Write only FOUT Enable FOUT Timebase Select DIO Serial Out Divide By 2 Slow Internal Time Divide By 2 Slow Internal Timebase Source Divide By 2 Clock To Board Divide By 2 Clock To Board AI Output Divide By 2 AI Source Divide By 2 AO Output Divide By 2 AO Source Divide By 2 FOUT Divider FOUT Divider FOUT Divider FOUT Divider DAQ STC Technical Reference Manual Appendix B Register Information DIO Control Register Address 11 Type Write only 15 Reserved 14 Reserved 13 Reserved Reserved N DIO_Pins_Dir DIO_Pins_Dir DIO_Pins_Dir DIO_Pins_Dir DIO_Pins_Dir DIO_Pins_Dir DIO_Pins_Dir DIO_Pins_Dir _ DOO CO DIO Software DIO HW Serial Timebase DIO HW Serial Enable DIO HW Serial Start Serial Control DIO Parallel Input Register Address 7 Type Read only 15 Reserved St 14 Reserved 1 St 13 Reserved 1 St 12 R
247. O UC Arm UC Load AO BC Arm AO BC Load AO DACI Update Mode AO LDACI Source Select AO DACO Update Mode AO LDACO Source Select AO UPDATE Pulse AO Mode 1 Register Type Write only AO UPDATE Source Select AO UPDATE Source Select AO UPDATE Source Select AO UPDATE Source Select AO UPDATE Source Select AO UI Source Select AO UI Source Select AO UI Source Select AO UI Source Select AO UI Source Select AO Multiple Channels AO UPDATE Source Polarity AO UI Source Polarity AO UC Switch Load Every TC AO Continuous AO Trigger Once DAQ STC Technical Reference Manual Appendix B Address 39 15 14 13 j N NUR ODODO Address 86 15 14 13 N _ 1 Register Information AO Mode 2 Register Type Write only AO FIFO Mode AO FIFO Mode AO FIFO Retransmit Enable 5 Disable AO UC Initial Load Source AO UC Write Switch AO UD Initial Load Source AO UD Reload Mode AO UC Initial Load Source AO UI Reload Mode AO Reload Mode AO UI Reload Mode AO UI Wirite Switch AO BC Initial Load Source AO BC Reload Mode AO BC Wirite Switch AO Output Control Register Type Write only AO External Gate Enable AO External Gate Select AO External Gate Select AO External Gate Select AO External Gate Select AO External Gate Select
248. OK GO Gate Interrupt GO TC Interrupt AI Error Interrupt AI STOP Interrupt AI START Interrupt AI START2 Interrupt AI STARTI Interrupt AI SC TC Interrupt AI SC TC Error Confirm GO TC Error Confirm GO Gate Error Confirm Reserved Reserved Reserved Reserved Reserved National Instruments Corporation Appendix B Register Information Generic Control Register Address 71 Type Write only 15 Control 14 Control 13 Control 12 Control 11 Control 10 Control 9 Control 8 Control 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Reserved Interrupt A Enable Register Address 73 Type Write only 15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 Reserved 10 Reserved 9 Pass Thru 0 Interrupt Enable 8 GO Gate Interrupt Enable 7 AI FIFO Interrupt Enable 6 GO TC Interrupt Enable 5 AI HBrror Interrupt Enable 4 STOP Interrupt Enable 3 AI START Interrupt Enable 2 AI START2 Interrupt Enable 1 AI STARTI Interrupt Enable 0 AI SC TC Interrupt Enable DAQ STC Technical Reference Manual Appendix B Register Information Interrupt B Ack Register Address 3 Type Write only 15 Gate Interrupt 14 GI TC Interrupt 13 AO Error Interrupt 12 AO STOP Interrupt Ack 11 AO ST
249. ONTROL conditioning to level gating and program the counter to reload on TC and switch the load bank selection on CONTROL The counter begins decrementing after the ARM Whenever counter TC is reached the counter reloads and counts down to TC again G_GATE is synchronized by the falling edge of G SOURCE to generate CONTROL CONTROL affects the bank select signal which indicates whether the reload occurs from bank X or Y The load select signal indicates whether the reload occurs from load register A or B Figure 4 47 shows an example of frequency shift keying When G_GATE is low pulses are generated with a pulse interval of three and a pulsewidth of two When GATE is high pulses are generated with a pulse interval of five and a pulsewidth of four The dotted line indicates where the ARM occurs G CONTROL Counter Load Counter Value 2 K1XOX 1X OX2X1KOX1XOK4 XB 2 1 2 1 XoX4X SX 2X1 XOXSX2Y 1X OK G SOURCE UI G GATE Bank Select Load Select Counter TC G OUT Figure 4 47 Frequency Shift Keying DAQ STC Technical Reference Manual 4 86 National Instrument
250. O_i_Output_Enable 1 GPFO 1 Output Select 0 Bitfield Descriptions Bits in the register bit maps are organized into bitfields A bitfield can contain one or more bits Only bits with contiguous locations within a register can belong to a bitfield The high and low pairs of load and save registers for 24 bit counters are also treated as bitfields The GPCT related bitfields are described below Not all bitfields referred to in section 4 6 Programming Information are listed here To locate a particular bitfield description within this manual refer to Appendix B Register Information Gi Analog Trigger Reset i 0 bit 3 type Strobe GO Command Register address 6 bit 3 type Strobe GI Command Register address 7 This bit clears the hysteresis registers in the analog trigger circuit Set this bit to 1 at the time you arm general purpose counter i if you want to use analog triggering in hysteresis mode for any general purpose counter i input signal Before setting this bit to 1 make sure that the analog trigger is not being used by any other part of the DAQ STC You should not set this bit to 1 in any other case This bit is cleared automatically National Instruments Corporation 4 35 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer Gj Arm i 0 bit 0 type Strobe GO Command Register address 6 bit 0 type Strobe Gl Command Register address 7 Setting this bit to 1 arm
251. Once 0 Gi Down 0 down counting or 1 up counting or 2 controlled by UP DOWNYj or 3 controlled by the internal gate value Gi Bank Switch Enable 0 Gi Bank Switch Mode 0 Gi TC Interrupt Enable 0 Gi Gate Interrupt Enable 1 National Instruments Corporation 4 21 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer The gate interrupt notifies the CPU after each counting interval so that the ISR can read the results from the HW save register In noncumulative mode the ISR checks for a stale data error indicating that the gate action was too quick to be measured by the source clock In this case the ISR ignores the counter value and writes O into the buffer Once the value from the read is stored in the buffer the ISR checks for a rollover error and a gate acknowledge latency error Use this function as an ISR for buffered event counting Function Event_Counting_ISR Declare variables 1 holds the save register value g buffer done indicates whether the event counting is complete save 1 Gi HW Save Register If noncumulative mode then check for stale data in noncumulative mode If Gi Stale Data St is 1 then stale data no source transitions between two relevant gate edges save 120 If g_buffer_done is 0 AND buffer is not full then Write save_1 into the current position in the buffer Increment the pointer to the current position
252. Primary Analog Output Group sese 3 34 3 6 4 Master Slave Operation Considerations for Primary Analog Output Group OU e HIT sets 3 35 3 6 5 Primary Analog Output Group Related Interrupts 3 35 3 6 6 Programming for a Secondary Analog Output Group Operation 3 38 3 6 6 1 OVELVIEW iie eite etu gero mU ORC ES 3 38 3 6 6 2 Resetting neither 3 38 3 6 6 3 Board Power up Initialization sess 3 39 3 6 6 4 Hardware Gate Programming sees 3 39 3 6 6 5 Software Gate Operation sse 3 40 DAQ STC Technical Reference Manual Viii National Instruments Corporation 3 6 6 6 Counting for Waveform 3 6 6 7 Update Selection reme tegere 3 6 6 8 AMID xen eene creen 3 6 6 9 Secondary Analog Output Program 3 6 7 Waveform Staging for Secondary Analog Output 3 6 8 Changing Update Rate during an Output Operation for Secondary Analog Output sese 3 6 9 Master Slave Operation Considerations for Secondary Analog 3 6 10 Secondary Analog Output Related Interrupts 36 11 Bitfield Descriptions ete ete metres Timing Diagrams inei eoe ette ere 3 7 1 Signal Definitions iiec eet 3 7 1 1 UPDATE SRC Geek ete PUDE ER 3 7 1 1
253. Programmable Function Inputs case 2 BD 2 Pin Dir 0 input or 1 output break case 3 BD 3 Pin Dir 0 input or 1 output break case 4 BD 4 Pin Dir 0 input or 1 output break case 5 5 Pin Dir 0 input or 1 output break case 6 6 Pin Dir 0 input or 1 output break case 7 BD 7 Pin Dir 0 input or 1 output If BD 7 Pin Dir is 1 then AI START Output Select 0 output AD START or 1 output AD SCAN IN PROG break case 8 BD 8 Pin Dir 0 input or 1 output break case 9 BD 9 Pin Dir 0 input or 1 output break hp Warning You must be very careful when programming bidirectional pins for output If an external signal is driving a bidirectional pin and you configure the pin for output you may cause physical damage to the DAQ STC the external circuitry or both 5 4 2 Bitfield Descriptions Bits in the register bit maps are organized into bitfields A bitfield can contain one or more bits Only bits with contiguous locations within a register can belong to a bitfield The high and low pairs of load and save registers for 24 bit counters are also treated as bitfields The PFI related bitfields are described below Not all bitfields referred to in section 5 4 Programming Information are listed here To locate a particular bitfield description within this manual refer to Appendix B Register Information DAQ STC Technical Reference Manual 5 6 National In
254. RDY CHRDY OUT Bus Interface WRITE 5 lt 0 3 gt AIFEF AIFHF AIFFF SOC EOC GHOST AI STOP IN MUXFEF Analog Input Timing Control CONVERT AI STOP OUT AIFREQ LOCALMUX CLK LOCALMUX FFRT EXTMUX CLK SCAN IN PROG SHIFTIN AI FIFO SHIFTIN SC TC SI TC DIV TC Programmable lt 0 9 gt Function Inputs e RTSI lt 0 6 gt RTSI Trigger RTSI_BRD lt 0 3 gt RTSI_OSC F IRQ_IN lt 0 1 gt RQ_OUT lt 0 7 gt SEC_IRQ_OUT_BANK lt 0 1 gt AOFEF AOFHF AOFFF CPUDACREQ Analog Output Timing Control TMRDACREQ TMRDACWR CPUDACWR AO_ADDR lt 0 3 gt UPDATE UPDATE2 AOFFRT DACWR lt 0 1 gt LDAC lt 0 1 gt AOFREQ BC_TC UC_TC Interrupt Control DIO lt 0 7 gt Digital O STATUS lt 0 3 gt CONTROL lt 0 7 gt EXTSTROBE SDCLK G_UP_DOWN lt 0 1 gt General Purpose Counter Timer OSC TEST_IN ANALOG TRIG IN LO Miscellaneous ANALOG TRIG IN HI OUTBRD OSC FOUT ANALOG TRIG DRIVE TEST OUT OUTO RTSI Functions OUT1 DIV TC OUT Figure 1 3 DAQ STC Block Diagram DAQ STC Technical Reference Manual 1 4 National Instruments Corporation Analog Input Timing Control 2 1 Overview This chapter describes the analog input timing control module AITM which generates timing for the ADC and controls signals for the associated circuitry The AITM contains a 24 bit scan interval counter 51 a 24 bit scan counter SC
255. RT figure 2 110 internal CONVERT figure 2 109 frequency output specifications 2 Frequency Shift Keying function 4 32 frequency shifting keying FSK description 4 14 to 4 15 programming 4 31 to 4 32 FSC SRC signal table 2 115 FSCLK signal analog input timing control table 2 114 analog output timing control table 3 111 FSK See frequency shifting keying FSK FTP support E 1 G GATE signal buffered cumulative event counting 4 5 buffered noncumulative event counting 4 4 to 4 5 buffered period measurement 4 7 to 4 8 buffered pulse train generation 4 14 buffered pulsewidth measurement 4 9 buffered retriggerable single pulse generation 4 11 to 4 12 buffered semiperiod measurement 4 8 buffered static pulse train generation 4 13 continuous pulse train generation figure 4 13 frequency shift keying FSK 4 14 to 4 15 minimum pulsewidth 4 56 pulse generation for ETS 4 15 retriggerable single pulse generation 4 11 National Instruments Corporation 1 23 Index simple gated event counting 4 4 simplified general purpose counter timer model 4 2 to 4 3 single triggered pulse generation 4 10 single period measurement 4 6 to 4 7 single pulsewidth measurement 4 7 G OUT signal buffered pulse train generation figure 4 14 buffered retriggerable single pulse generation figure 4 12 buffered static pulse train generation figure 4 13 continuous pulse train generation figure 4 13
256. RT SRC 4 level mode Ts_strt2 START2 setup to CONVERT 31 34 Tstrt2 START pulsewidth edge mode 6 Th strt2 START2 hold from CONVERT SRC 4 level mode Ts START setup to CONVERT SRC 29 32 DAQ STC Technical Reference Manual 2 96 National Instruments Corporation Chapter 2 Analog Input Timing Control Table 2 5 External Analog Input Timing Continued Name Description Minimum Maximum Tstrt START pulsewidth edge mode 6 Th strt START hold from CONVERT SRC 4 level mode Ts stop STOP setup to CONVERT SRC 31 34 Tstop STOP pulsewidth edge mode 6 Th stop STOP hold from CONVERT SRC 4 zs level mode All timing values are in nanoseconds 2 1 8 The numbers in parentheses indicate edge gating mode depending on which mode you specify in _ Edge AI START2 Edge AI START Edge or STOP Edge Trigger Output You can output the internal triggers to the board through the PFI or RTSI interface This section lists the propagation delays for the triggers when you configure the triggers for output to the board 2 7 8 1 START1 and START Triggers You can output the START trigger on the PFI output PFIO AI_START1 on any RTSI output You can output the START trigger on the PFI output START2 or on any output Timing for 5 and START2 depends on whether you select synchronous mode or asynchronous mode
257. RT2 by passing the output of the START2 selector through polarity selection but not edge detection or synchronization If AI Delayed 2 1 then AD VSTART 2 is the same as ADR 5 2 Related bitfields AI Delayed START2 AIERROR AI Error This signal indicates that an analog error has occurred AIFIFOREQ AI FIFO Request This signal generates AIFREQ AI IN TIMEBASEI Internal Timebase for the Analog Input Module This signal can be selected be the same as IN TIMEBASE or it can be TIMEBASE divided by two Related bitfields Source Divide By 2 National Instruments Corporation 2 113 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Table 2 9 Internal Signals Continued Signal Description AI OUT TIMEBASE AI Output Timebase This signal times the analog input output circuitry Related bitfields Output Divide By 2 DIV CE DIV Count This signal enables and disables the DIV counter Refer to section 2 8 3 8 DIV Control for the DIV CE logic equations DIV CLK DIV Clock This signal is the actual clock signal for the DIV counter and the DIV counter control logic When the counter is not armed DIV CLK is derived from the write strobe for AI Command 1 Register so that the counter can be loaded using the load command When the counter is armed DIV CLK is the same as SC Re
258. Registers address 12 bits lt 0 15 gt type Read in GO Save Registers address 13 bits lt 0 7 gt type Read Save Registers address 14 bits lt 0 15 gt gt type Read in G1 Save Registers address 15 When Save Trace and Save Trace Copy are both 0 this bitfield reflects the contents of general purpose counter i When you set Save Trace or Gi Save Trace Copy to 1 this bitfield synchronously latches the contents of the counter using the counter source The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related bitfields Save Trace Save Trace Copy National Instruments Corporation 4 47 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer Source Polarity i 0 0 15 type Write in GO Input Select Register address 36 i l bit 15 type Write Input Select Register address 37 This bit selects the active edge of the general purpose counter i source 0 Rising edge Falling edge Related bitfields Source Select Source Select i 0 015 2 6 type Write in GO Input Select Register address 36 i l bits lt 2 6 gt type Write in G1 Input Select Register address 37 This bitfield selects the general purpose counter i source 0 The internal signal G IN TIMEBASEI 1 10 PFI lt 0 9 gt 11 17 RTSI lt 0 gt 18 The internal signal IN TIMEBASE2 19 The G TC
259. SI Trig 6 Pin Dir 14 RTSI Trig 5 Pin Dir 13 RTSI Trig 4 Pin Dir RTSI Trig 3 Pin Dir RTSI Trig 2 Pin Dir RTSI Trig 1 Pin Dir RTSI Trig 0 Pin Dir Reserved N Reserved Reserved Reserved Reserved Reserved Reserved RTSI_Clock_Mode RTSI_Clock_Mode _ DAQ STC Technical Reference Manual B 36 ee NUR ADA 5 HRN eS eS DU DO 4 tA RTSI Trig B Output Register Address 80 Type Write only RTSI Sub Selection 1 Reserved Reserved Reserved RTSI Trig 6 Output Select RTSI Trig 6 Output Select RTSI Trig 6 Output Select RTSI Trig 6 Output Select RTSI Trig 5 Output Select RTSI Trig 5 Output Select RTSI Trig 5 Output Select RTSI Trig 5 Output Select RTSI Trig 4 Output Select RTSI Trig 4 Output Select RTSI Trig 4 Output Select RTSI Trig 4 Output Select Second Irq A Enable Register Address 74 Type Write only Reserved Reserved Reserved Reserved Reserved Reserved Pass Thru 0 Second Enable GO Gate Second Irq Enable AI FIFO Second Enable GO TC Second Enable AI Error Second Enable AI STOP Second Enable AI START Second Enable AI START2 Second Enable AI STARTI Second Enable AI SC TC Second Enable National Instruments Corporation Appendix B Register Information
260. SRC signal table 3 113 UI TC signal table 3 113 UI2 counter control circuitry 3 121 description 3 121 simplified analog output model 3 5 UD CE signal table 3 114 UI2_CLK signal table 3 114 UI2 LOAD signal table 3 114 UI2 LOAD SRC signal table 3 114 UD SRC signal description table 3 114 pin selection table 3 85 to 3 86 UI2_TC error 3 123 UD TC signal table 3 114 unbuffered data interface 3 11 unbuffered data interface timing 3 08 to 3 100 UPDATE modes See external UPDATE internal UPDATE update rate changing primary analog output programming 3 34 to 3 35 secondary analog output programming 3 44 to 3 45 update selection primary analog output operation programming 3 26 to 3 28 secondary analog output operation programming 3 40 to 3 41 UPDATE signal continuous mode 3 14 DAQ STC driven analog output 3 6 DAQ STC driven analog output timing 3 86 to 3 88 description table 3 20 external trigger timing 3 102 to 3 104 external UPDATE timing 3 12 FIFO data interface 3 9 internal UPDATE timing 3 11 to 3 12 local buffer mode timing 3 96 to 3 97 maximum update rate timing 3 101 DAQ STC Technical Reference Manual Index serial link data interface 3 10 simplified analog output model 3 4 to 3 5 single buffer mode 3 13 unbuffered data interface 3 11 unbuffered data interface timing 3 98 to 3 100 UPDATE SRC signal external trigger timing 3 102 to 3 104 pin selection table 3 85
261. START2 SCLKG DACUPDN DA STARTI G_SRC 0 0 RGOUTO and 5 BRD O0 3 Source Destination These pins are appropriate for use as bidirectional RTSI TRIGGER bus signals Related bitfields RTSI Trig Pin Dir RTSI Trig Output Select RTSI lt 0 3 gt B9TU RTSI Board Interface Configured as an input each bidirectional RTSI BRD pin can drive any of the seven RTSI TRIGGER pins 5 BRD O 1 can also be driven by AI STOP and RTSI_BRD lt 2 3 gt can also be driven by the AI START and SCAN IN PROG signals These pins provide a mechanism for additional board level signals to be sent on or received from the RTSI bus Related bitfields RTSI Board Pin Dir RTSI Board Output Select RTSI OSC B9TU RTSI Oscillator Source RTSI_OSC is a bidirectional pin Programmed as an input it is the alternate timing source for the DAQ STC Programmed as an output this pin carries the OSC signal The pin is used for multiple DAQ STC synchronization across the RTSI bus Source Destination RTSI bus Related bitfields RTSI Clock Mode 6 4 Programming Information This section presents programming information that is specific to the RTSI trigger For general information about programming the DAQ STC see section 2 6 Programming Information 6 4 1 Programming the RTSI Interface This section contains detailed programming information for users who need to do bit level
262. STARTI bit 3 52 Disarm bit 3 52 AO Control bit 3 53 AO End On BC TC bit 3 53 AO End On UC TC bit 3 53 AO ENDI signal table 3 109 AO END2 signal table 3 109 AO Error bit 3 53 AO Error Interrupt Enable bit 3 53 AO Error Second Enable bit 3 54 AO Errors To Stop On function 3 29 AO External Gate Enable bit 3 54 AO External Gate Polarity bit 3 54 AO External Gate Select bit 3 54 AO External Gate St bit 3 55 AO Fast CPU bit 3 55 AO FIFO Empty St bit 3 55 AO FIFO Enable bit 3 55 AO FIFO Flags Polarity bit 3 56 Full St bit 3 56 AO FIFO function 3 30 AO Half Full St bit 3 56 AO FIFO Interrupt Enable bit 3 56 AO Mode bit 3 57 AO FIFO Request St bit 3 57 AO FIFO Retransmit Enable bit 3 57 AO FIFO Second Irq Enable bit 3 57 AO IN TIMEBASE signal table 3 110 DAQ STC Technical Reference Manual Index AO Interrupt Install function 3 30 AO Interval Buffer Mode bit 3 58 AO LDAC Source And Update Mode function 3 29 AO LDACi Source Select bit 3 58 AO Multiple Channels bit 3 58 AO Mute A bit 3 58 AO Mute B bit 3 59 AO Not An UPDATE bit 3 59 AO Number Of Channels bit 3 59 AO Number Of DAC Packages bit 3 60 AO OUT TIMEBASE signal table 3 110 AO Output Divide 2 bit 3 60 AO Overrun St bit 3 60 AO Rate Change function 3 34 to 3 35 AO Reset function 3 21
263. STC 0 No 1 Yes A valid START trigger is one that is received while the BC counter is armed and in the WAIT state You can clear this bit by setting AO STARTI Interrupt Ack to 1 Related bitfields AO Arm STARTI Interrupt Ack Refer to Table 8 2 Interrupt Condition Summary for more information 0 START1 Sync bit 6 type Write in AO Trigger Select Register address 67 This bit enables internal synchronization of the STARTI trigger to the BC source 0 Disabled 1 Enabled 0 STOP Interrupt Ack bit 12 type Strobe Interrupt Ack Register address 3 Setting this bit to 1 clears AO STOP St and acknowledges the STOP interrupt request in either interrupt bank if the STOP interrupt is enabled This bit is cleared automatically This bit is currently not supported and it must be set to 0 Related bitfields STOP St National Instruments Corporation 3 65 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 STOP Interrupt Enable bit 4 type Write in Interrupt Enable Register address 75 This bit enables the STOP interrupt 0 Disabled Enabled This bit is currently not supported and it must be set to 0 0 Stop On BC TC Error bit 3 type Write in AO Mode 3 Register address 70 This bit determines whether analog output timing will stop when a BC TC error occurs 0 Continue on BC TC error 1 Stopon BC TC error AO TC Error St will be
264. St bit 2 53 AI DIV Load A bit 2 53 AI DIV Load bit 2 53 AI DIV Q St bit 2 53 AI DIV Save Value bit 2 53 AI End On End Of Scan bit 2 53 End On SC TC bit 2 54 AI Polarity bit 2 54 ECC St bit 2 54 AI Error Interrupt bit 2 54 AI Error Interrupt Enable bit 2 54 AI Error Second Enable bit 2 54 AI External Gate Mode bit 2 55 AI External Gate Polarity bit description 2 55 software gate operation 2 31 AI External Gate Select bit description 2 55 software gate operation 2 31 AI External Gate St bit 2 55 AI External MUX Present bit 2 56 AI EXTMUX Output Select bit 2 56 AI EXTMUX CLK Pulse bit 2 56 AI EXTMUX CLK Pulse Width bit 2 56 AI FIFO Empty St bit 2 57 AI FIFO Flags Polarity bit 2 57 AI Full St bit 2 57 AI FIFO Half Full St bit 2 57 AI FIFO Interrupt Enable bit 2 58 AI FIFO Mode bit 2 58 AI FIFO Request St bit 2 58 AI FIFO Second Irq Enable bit 2 59 AI FIFO SHIFTIN signal description table 2 19 simplified analog input model 2 5 to 2 6 AI Hardware Gating function 2 30 to 2 31 DAQ STC Technical Reference Manual Index AI IN TIMEBASE I signal table 2 113 AI Initialize Configuration Memory Output function 2 28 to 2 29 AI Interrupt Enable function 2 40 to 2 41 AI Last Shiftin St bit 2 59 AI LOCALMUX CLK Output Select bit 2 59 AI LOCALMUX CLK Pulse bit 2 59 AI LOCALMUX CLK Pulse Width bit 2 59 to 2 60 AI Number Of Scans functio
265. T Conditioning and Routing eee 4 65 4 8 6 CONTROL Conditioning eene 4 67 4 8 7 4 67 4 8 7 1 START STOP on 4 68 4 8 7 2 Save on G GATE erem 4 68 4 8 7 3 Reload on CONTROL eee 4 68 4 8 7 4 UP DOWN on CONTROL eee 4 69 4 8 7 5 Generate Interrupt on _ 4 69 4 8 7 6 Change Output Polarity on _ 4 69 4 8 7 7 Select Load Register on CONTROL 4 69 National Instruments Corporation DAQ STC Technical Reference Manual Contents 4 8 7 8 Disarm Counter on 4 70 4 8 7 9 Switch Load Bank Selection on G_CONTROL 4 70 4 8 8 Interrupt Control td tone tiet e RE 4 70 4 8 9 PETI S lection OUR edet euin 4 70 4810 Error sc een eee Recte tite ett 4 71 4 8 10 1 Gate Acknowledge Latency 4 71 4 8 10 2 Stale Data Error deret eet ety 4 71 4 8 10 3 Permanent Stale Data 4 71 4 8 10 4 TE Eatency Error iet eee 4 72 4 8 11 Detailed Operation by Application 4 72 4 8 11 1 Simple Event 4 72 4 8 11 2 Simple Gated Event 4 73 4 8 11 3 Buffered Noncumulative Eve
266. TC Technical Reference Manual 1 10 BC TC trigger error 3 123 BD i Pin Dir bit 5 7 bitfield descriptions analog input timing control 2 48 to 2 83 AI AIFREQ Polarity 2 48 AI Analog Trigger Reset 2 48 AI Config Memory Empty St 2 49 AI Configuration End 2 49 AI Configuration Start 2 49 AI Continuous 2 49 AI CONVERT Original Pulse 2 50 AI CONVERT Output Select 2 50 AI CONVERT Pulse 2 50 AI CONVERT Pulse Timebase 2 50 AI CONVERT Pulse Width 2 51 AI CONVERT Source Polarity 2 51 AI CONVERT Source Select 2 51 AI Delay START 2 52 AI Delayed START 2 51 AI Delayed START2 2 52 AI Disarm 2 52 AI DIV Arm 2 52 AI DIV Armed St 2 53 AI DIV Load 2 53 AI Load A 2 53 AI DIV Q St 2 53 AI DIV Save Value 2 53 AI End On End Of Scan 2 53 End SC 2 54 AI EOC Polarity 2 54 EOC St 2 54 AI Error 2 54 AI Error Interrupt Enable 2 54 AI Error Second Enable 2 54 AI External Gate Mode 2 55 AI External Gate Polarity 2 31 2 55 National Instruments Corporation AI External Gate Select 2 1 2 55 AI External Gate St 2 55 AI External Present 2 56 AI EXTMUX CLK Output Select 2 56 AI EXTMUX CLK Pulse 2 56 AI EXTMUX CLK Pulse Width 2 56 AI FIFO Empty St 2 57 AI FIFO Flags Polarity 2 57 AI FIFO Full St 2 57 AI FIFO Half Full St 2 57 AI FIFO Interrupt Enable 2 58 AI FIFO Mode 2 58 AI FIFO Request St 2 58 AI FIFO Second I
267. Technical Reference Manual Chapter 2 Analog Input Timing Control Else AI SI Switch Load SC Else Scan rate change cannot be performed 2 6 6 Staged Acquisition staged acquisition software implements more than one posttrigger acquisition sequence each having unique timing parameters The number of scans to be executed in each stage is contained in an array named ticks The variable ticks pointer is a pointer into the array and should be initialized to 1 The number of scans for the first two posttrigger acquisition sequences is programmed in the Number Of Scans function The number of clocks between START in each stage is contained in an array named si ticks The variable 51 ticks pointer is a pointer into the array and should be initialized to 1 The number of clocks for the first two posttrigger acquisition sequences is programmed in the AT Scan Start function The variable si last load register indicates which load register was accessed most recently and is initialized in the Scan Start function The SC TC interrupt notifies the CPU that the current acquisition sequence is complete so that the ISR can program the parameters for the next acquisition sequence After the parameters are loaded the ISR checks for an SC error An SC TC error occurs if the parameters for the next acquisition sequence are not written before the end of the current acquisition sequence Use the following
268. The DIV counter loads the value contained in this bitfield on DIV Load and DIV_TC Related Bitfields AI DIV Load AI DIV Q St bit 13 type Read in AI Status 2 Register address 5 This bit reflects the state of the DIV control circuit 0 WAIT 1 CNT See section 2 8 Detailed Description for more information on the DIV control circuit Al_DIV_Save_Value bits lt 0 15 gt type Read in AI DIV Save Register address 26 This bitfield reflects the contents of the DIV counter Reading from this bitfield while the DIV counter is counting may result in an erroneous value End On End Of Scan bit 14 type Strobe AI Command 2 Register address 4 Setting this bit to 1 disarms the SC 51 SI2 and DIV counters at the next STOP You can use this bit to stop the acquisition in continuous acquisition mode This bit is cleared automatically Related bitfields Continuous National Instruments Corporation 2 53 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control AI End SC TC bit 15 type Strobe in AI Command 2 Register address 4 Setting this bit to 1 disarms SC SI 512 and DIV counters at the next SC TC You can use this bit to stop the acquisition in continuous acquisition mode This bit is cleared automatically Related bitfields Continuous EOC Polarity bit 14 type Write in AI Personal Register address 77 This bit determines which edge of the EOC
269. This bit determines when the LOCALMUX CLK output signal pulses 0 Pulse on every CONVERT 1 Pulse only on CONVERTS that occur during This bit allows you to use the DIV counter for LOCALMUX signal control This is useful if one or more external multiplexers such as an AMUX 64T or SCXI are connected to the board the DAQ STC is on You should set this bit to 0 if no external multiplexers are present or if each external channel corresponds to one internal channel You should set this bitto 1 if one or more external multiplexers are present and if you are multiplexing more than one external channel onto each internal channel If this bit is set to 1 the DIV counter must be used to determine the number of EXTMUX pulses that will correspond to one LOCALMUX CLK pulse EXTMUX CLK Output Select bits lt 6 7 gt type Write in AI Output Control Register address 60 This bit enables and selects polarity for the EXTMUX output signal 0 HighZ 1 Ground 2 Enable active low 3 Enable active high EXTMUX CLK Pulse bit 3 type Strobe AI Command 1 Register address 8 Setting this bit to 1 produces a pulse on the EXTMUX output signal if the output is enabled The pulsewidth is determined by AI EXTMUX Pulse Width This bit is cleared automatically Related bitfields AI EXTMUX Output Select AI EXTMUX Pulse Width EXTMUX CLK Pulse Width bit 6 type Write
270. This bit enables the START2 interrupt in the secondary interrupt bank 0 Disabled 1 Enabled The START interrupt is generated only on valid START triggers received by the DAQ STC A valid START trigger is one that is received while the SC counter is in the WAIT state START2 Select bits lt 7 11 gt type Write in AI Trigger Select Register address 63 This bitfield selects the START trigger 0 Bitfield AI START2 Pulse 1 10 lt 0 9 gt 11 17 RTSI lt 0 gt 31 Logic low Related bitfields AI START2 Pulse START St bit 8 type Read in AI Status 1 Register address 2 This bit indicates whether a valid START trigger has been received by the SC counter in the pretrigger acquisition mode 0 No 1 Yes A valid START signal is one that is received while the SC counter is in WAIT2 state You can clear this bit by setting AI START2 Interrupt Ack to 1 Refer to Table 8 2 Interrupt Condition Summary for more information START2 Sync bit 13 type Write in AI Trigger Select Register address 63 This bit enables internal synchronization of the START2 trigger to the SC source 0 Disabled 1 Enabled You should set this bit to 1 unless START2 is synchronized externally to the signal that is selected as the CONVERT source You must set this bit to 1 if AI START2 Select is set to 0 You should set this bit to 0 if the ASIC is a START2 slave to another DAQ ST
271. This bit indicates status of the general purpose counter gate 0 Inactive gate 1 Active gate This bit can only be used in the level gating mode Note that active gate does not always mean high logic Related bitfields Gating Mode Gate Polarity Gi Gating Mode i 0 bits 0 1 Write in GO Mode Register address 26 bits lt 0 1 gt Write in Mode Register address 27 This bit enables and selects the counter gating mode 0 Gating is disabled 1 Level gating 2 Edge gating Rising edge if Gating Polarity is set to 0 Falling edge if Gi Gating Polarity is set to 1 3 Edge gating Falling edge if Gi Gating Polarity is set to O Rising edge if Gating Polarity is set to 1 When Gi Gating Mode is 0 gating disabled gate level is available only for control of counting direction up down and for no other purpose Related bitfields Gi Gating Polarity National Instruments Corporation 4 41 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer Gi HW Save St i 0 bit 12 type Read in Joint Status 2 Register address 29 i 1 bit 13 type Read in Joint_Status_2_Register address 29 This bit indicates the status of the HW save register for general purpose counter i 0 HW save register is tracing the counter 1 HW save register is latched for later read Related bitfields Save Trace Gi HW Save Value 0 bits lt 0 7 gt type
272. This bit is useful for device diagnostic applications Related bitfields AI SOC Polarity Software Gate bit 13 type Write in AI Mode 3 Register address 87 This bit controls the software gate which you can use to pause an analog input operation 0 Enable operation Pause operation Refer to section 2 4 4 Gating for more information on software gating Note that the hardware gate must be enabled in order for the software gate to operate properly Related bitfields External Gate Mode Source Divide By 2 bit 6 type Write in Clock and FOUT Register address 56 This bit determines the frequency of the internal timebase AI IN TIMEBASEI 0 Same as IN TIMEBASE 1 TIMEBASE divided by two National Instruments Corporation 2 73 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control START Edge bit 5 type Write in AI START STOP Select Register address 62 This bit enables edge detection of the START trigger 0 Disabled level sensitive trigger 1 Enabled edge sensitive trigger This bit should normally be set to 1 START Interrupt bit 11 type Strobe Interrupt Register address 2 Setting this bitto 1 clears AI START Stand acknowledges the START interrupt request in either interrupt bank if the START interrupt is enabled This bit is cleared automatically Related bitfields AI START St START Interrupt Enable bit 3 ty
273. Timer 4 8 11 3 Buffered Noncumulative Event Counting To use this function set G CONTROL conditioning to edge gating and program the counter to reload on CONTROL and generate interrupts on G_GATE The rising edge of G is synchronized by the falling edge of SOURCE to generate a CONTROL pulse The counter increments on every SOURCE rising edge following the ARM On the SOURCE rising edge following CONTROL the counter reloads from the selected load register The HW save register switches to transparent mode on the rising edge of and returns to latched mode on the next G SOURCE falling edge Figure 4 34 shows an example of buffered noncumulative event counting The dotted line indicates where the ARM occurs and the arrows indicate where the gate interrupt is generated HW Save Register G SOURCE acre Sq 1 588 G CONTROL Counter Load be be HW Save XX 3 XX 5 Counter Value XIX 2949 4 Figure 4 34 Buffered Noncumulative Event Counting 4 8 11 4 Buffered Cumulative Event Counting To use this function set G CONTROL conditioning to edge gating and program the counter to generate interrupts G_GATE The counter increments on every SOURCE rising edge following the ARM The HW save register switches to transparent mode on the rising e
274. Timer presents information about the general purpose counter timer GPCT module of the DAQ STC Chapter 5 Programmable Function Inputs explains the PFI module on the DAQ STC Chapter 6 RTSI Trigger describes the features of the RTSI trigger module RTM and explains how to program the RTSI interface Chapter 7 Digital I O describes the digital I O DIO module and explains how to use it on the DAQ STC Chapter 8 Interrupt Control describes the interrupt control module ICM its features and the conditions that cause interrupts Chapter 9 Bus Interface describes the features of the bus interface module gives programming instructions and presents the timing diagrams for the bus interface Chapter 10 Miscellaneous Functions discusses the miscellaneous functions not covered in the other chapters The miscellaneous functions include clock distribution the programmable frequency output analog triggering and test mode Appendix A Specifications contains specifications for the DAQ STC Appendix B Register Information contains information about the DAQ STC registers and bitfields Appendix C Pin List contains lists of the DAQ STC pins Appendix D DAQ STC Revision History lists the differences between the first two revisions of the DAQ STC and identifies those boards containing the first revision of the DAQ STC Appendix E Customer Communication contains forms you can use to request help from National Instru
275. U PFI7 START Trigger from Analog Input As an input this pin provides a signal path to the PFI selectors As an output this pin can reflect the state of the active high internal AI signal START or it can output the polarity selectable SCAN IN PROG signal from the AITM section If AI START Output Select is 0 the hardware generates PFI7 AI START as follows If AI Trigger Length is 0 this pin reflects the internal Alsignal AD START If AI Trigger Length is 1 this pin reflects the internal Alsignal AD START after it has been pulse stretched to be 1 2 AI OUT TIMEBASE periods long If AI START Output Select is 1 PFI7 AI START will output the same signal as SCAN IN PROG If SCAN IN PROG is configured for high impedance PFI7 AI START will output ground Source Destination This pin is appropriate to input an EXTGATE from the connector Related bitfields 7 Pin Dir AI START Output Select AI Trigger Length AI SCAN PROG Output Select DAQ STC Technical Reference Manual 5 4 National Instruments Corporation Chapter 5 Programmable Function Inputs Table 5 1 Pin Interface Continued Pin Name Type Description PFI8 G_SRCO B9TU PFI8 General Purpose Counter 0 Source As an input this pin provides a signal path to the PFI selectors As an output this pin reflects the internal signal G SOURCE from general purpose counter 0 Source Destination This pin is appropriate for use
276. UD TC interrupts are generated on the trailing edge of UPDATE2 0 Ul2 TC St bit 4 type Read in AO Status 1 Register address 3 This bit indicates whether the UI2 counter has reached TC 0 No 1 Yes To clear this bit set AO UI2 TC Interrupt Ack to 1 Related bitfields AO UD TC Interrupt Ack Refer to Table 8 2 Interrupt Condition Summary for more information National Instruments Corporation 3 79 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 UPDATE2 Original Pulse bit 2 type Write in AO Personal Register address 78 If AO UPDATE2 Pulse Timebase is 1 this bit determines the pulsewidth of the UPDATE2 signal The pulsewidth of the UPDATE signal will be 0 Equal to the pulsewidth of UI2 with the maximum pulsewidth determined by AO UPDATE2 Pulse Width 1 Equal to the pulsewidth of UI2 TC If this bit is set to 1 external gating for the UI2 counter will not work Related bitfields AO UPDATE2 Pulse Timebase AO UPDATE2 Pulse Width 0 UPDATE2 Output Select bits lt 4 5 gt type Write in AO Output Control Register address 86 This bit enables and selects the polarity of the UPDATE2 output signal 0 HighZ 1 Ground 2 Enable active low 3 Enable active high 0 UPDATE2 Output Toggle bit 2 type Write in AO Output Control Register address 86 This bit determines the behavior of the internal UI2 TC signal sent to the general purpose counter gate
277. UI2 counter is disarmed this bit loads the UI2 counter with the contents of the selected UI2 load register A or B If the 012 counter is armed writing to this bit has no effect This bit is cleared automatically Related bitfields UI2 Initial Load Source 0 UI2 Load bits lt 0 15 gt type Write in AO 012 Load A Register address 53 This bitfield is load register A for the UI2 counter If load register A is the selected UI2 load register the UI2 counter loads the value contained in this bitfield on UI2 Load and on UI2 TC Related bitfields AO UI2 Next Load Source St AO UI2 Load AO UI2 Load bits lt 0 15 gt type Write in AO 012 Load B Register address 55 This bitfield is load register B for the UI2 counter If load register B is the selected UI2 load register the UI2 counter loads the value contained in this bitfield on UI2 Load and on UD TC Related bitfields AO UI2 Next Load Source 51 AO 012 Load 0 UI2 Next Load Source St bit 12 type Read in AO Status 2 Register address 6 This bit indicates the next load source of the UI2 counter 0 Load register A 1 Load register B 0 Ul2 Reload Mode bit 8 type Write in AO Mode 2 Register address 39 This bit selects the reload mode for the UI2 counter 0 No automatic change of the UI2 load register 1 The UD counter will switch load registers on every UI2 TC 0 12 Save Value bits lt 0 15 gt type Read in AO UI2 Save Re
278. UT AOFFRT I TMRDACREQ I AOFREQ E gt DACWR lt 0 1 gt BC CONTROL COUNTER CHADDR gt LDAC lt 0 1 gt COUNTER UPDATE2 Figure 3 1 AOTM Simplified Mode One of the primary AOTM features is that a wide variety of timing signals can be selected as timing and control sources The simplified model depicts this as a select circuit which chooses between 10 PFI signals lt 0 9 gt and the seven RTSI signals RTSI lt 0 6 gt Many of the signals required for D A conversion can come from external sources routed through the selector The DAQ STC also has the ability to generate the timing sources internally The primary analog output timing signal is the UPDATE pulse The simplified model shows that the source for the UPDATE pulse may come from the UI counter internal UPDATE source or the select circuit external UPDATE source Using UPDATE as a reference the output section generates several ancillary signals used on the board The TMRDACWR output signal DAQ STC write to the DAC toggles repeatedly after each UPDATE according to the number of analog output channels to load the DACs with the next data value The CHADDR counter generates the outputs AO_ADDR lt 0 3 gt which provide the DAC destination address for the data The signals CPUDACREQ CPU request for access to the DAC and CPUDACWR CPU wri
279. V Load A AI DIV Load A AI DIV Load A N NUR Om AI Mode 1 Register Address 12 Type Write only 15 AI CONVERT Source Select 14 AI CONVERT Source Select 13 AI CONVERT Source Select AI CONVERT Source Select AI CONVERT Source Select AI SI Source Select AI SI Source Select AI SI Source Select AI SI Source Select AI SI Source Select AI CONVERT Source Polarity AI SI Source Polarity AI Start Stop Reserved One N AI Continuous _ 1 OO OK AI Trigger Once National Instruments Corporation Address 26 15 14 13 N OD Om Address 13 15 14 13 N _ 1 OO Appendix Register Information AI DIV Save Register Type Read only AI Save Value AI DIV Save Value AI DIV Save Value AI DIV Save Value AI Save Value AI Save Value AI DIV Save Value AI DIV Save Value AI DIV Save Value AI DIV Save Value AI Save Value AI Save Value AI Save Value AI DIV Save Value AI DIV Save Value AI DIV Save Value AI Mode 2 Register Type Write only AI SC Gate Enable AI Start Stop Gate Enable AI Pre Trigger AI External MUX Present Reserved Reserved AI SD Initial Load Source AI SI2 Reload Mode SI Initial Load Source AI SI Reloa
280. W Save Value GO HW Save Value DAQ STC Technical Reference Manual Appendix B Register Information GO Input Select Register G0 Load Registers Address 36 Type Write only Address 28 Type Write only 15 GO Source Polarity 15 Reserved 14 GO Output Polarity 14 Reserved 13 60 OR Gate 13 Reserved 12 GO Gate Select Load Source 12 Reserved 11 GO Gate Select 11 Reserved 10 GO Gate Select 10 Reserved 9 GO Gate Select 9 Reserved 8 GO Gate Select 8 Reserved 7 GO Gate Select 7 GO Load A 6 GO Source Select 6 GO Load A 5 GO Source Select 5 G0 Load A 4 GO Source Select 4 GO Load 3 GO Source Select 3 GO Load A 2 GO Source Select 2 90 Load A 1 GO Write Acknowledges 1 GO Load A 0 GO Read Acknowledges Irq 0 G0 Load G0 Load A Registers G0 Load B Registers Address 29 Type Write only Address 30 Type Write only 15 60 Load 15 14 60 Load 14 13 G0 Load 13 12 60 Load 12 Reserved 11 GO Load 11 Reserved 10 60 Load 10 9 60 Load 9 Reserved 8 60 Load 8 Reserved 7 G0 Load 7 GO Load 6 G0 Load 6 GO Load 5 G0 Load 5 G0 Load 4 60 Load 4 GO Load 3 G0 Load A 3 60 Load 2 G0 Load 2 G0 Load 1 G0 Load A 1 GO Load 0 GO Load A 0 GO Load DAQ STC Technical Ref
281. XTSTROBE SDCLK to complete the current 8 bit data transfer Each 8 bit transfer is initiated under software control Figure 7 4 shows a serial input operation where the DAQ STC reads the data byte Ox4B hex SW START EXTSTROBE SDCLK DIO4 SDIN ER Read Locations e R R R R R R R Input Pattern 0 4 Figure 7 4 DIO Serial Input 1 4 2 2 Serial Output In serial output mode the DAQ STC transfers 8 bit serial data to an external device through the DIOO SDOUT line Software configures the external device to read a new data bit on each EXTSTROBE SDCLK rising edge and selects EXTSTROBE SDCLK as one of the periodic timebases The DAQ STC places new data on the DIOO SDOUT line every EXTSTROBE SDCLK falling edge This arrangement allows the data line adequate time to stabilize before reading The DAQ STC generates only enough pulses on EXTSTROBE SDCLK to complete the current 8 bit data transfer Each 8 bit transfer is initiated under software control Figure 7 5 shows a serial input operation where the DAQ STC outputs the data byte 0x4B hex DAQ STC Technical Reference Manual 7 4 National Instruments Corporation Chapter 7 Digital 1 0 EXTSTROBE SDCLK DIO0 SDOUT SW START Output Pattern 0x4B 7 4 2 3 Serial 1 0 Figure 7 5 Serial Output It is possible for serial input and serial output t
282. a hardware input input the hardware up down control signal on UP DOWNTi pin For relative position sensing controlled by software set Gi Up Down 0 for initial down counting or Gi Up Down 1 for initial up counting After the counter is armed the count direction can be changed in software by writing to Up Down Function Relative Position Sensing Gi_Load_Source_Select 0 Gi_Load_A initial counter value X Gi Load 1 L Gi Source Select 0 G_IN_TIMEBASE 1 or 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI TRIGGER O 6 or 18 IN 2 or 19 other TC Gi Source Polarity 0 count rising edges or 1 count falling edges Gate Select 0 Gi OR Gate 0 Gi Output Polarity 0 active low or 1 active high Gate Select Load Source 0 Gi Gate Polarity 0 disable inversion or 1 enable inversion Gi Output Mode 1 one clock cycle output or 2 toggle on TC or 3 toggle on TC or gate Gi Reload Source Switching 1 Gi Loading Gate 0 Gi Loading On TC 0 Gi Gating Mode 2 Gi Gate On Both Edges 0 Gi Trigger Mode For Edge Gate 3 Gi Stop Mode 0 Gi Counting Once 0 If hardware controlled relative position sensing then National Instruments Corporation 4 23 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer Else Gi_Up_Down 2 Software controlled relative position sensing
283. able or disable hardware and software gating If you enable hardware gating you also select the signal that controls the gate the gate polarity and the gating mode Function AI_Hardware_Gating Begin critical section Y AI Configuration Start 1 If external gating is desired then DAQ STC Technical Reference Manual 2 30 National Instruments Corporation Chapter 2 Analog Input Timing Control AI External Gate Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI lt 0 6 gt AI External Gate Polarity 0 active high high enables operation or active low low enables operation AI External Gate Mode 0 free run gating or halt gating mode Else AI_External_Gate_Select 0 disabled gt AI Configuration 1 End critical section 2 6 3 7 Software Gate Operation In order to use the software gate the hardware gate must also be enabled If you want to use both the software and hardware gate at the same time configure the hardware gate and then start your application If you only want to use the software gate configure the hardware gate as indicated in section 2 6 3 6 Hardware Gate Programming with the following changes to the settings External 4Gate Select 31 e External Gate Polarity 1 s Note The hardware gate must be enabled in order for the software gate to operate properly To use the software gate issue the following command
284. acquisition modes the DIV counter control circuit can return to state WAIT based on the software strobes and AI END2 The internal signal SCKG controls the count operation of the DIV counter When the internal timebase 15 selected for the SC source AI CONVERT Source Select is set to 0 SCKG becomes the sample interval counter TC signal 512 TC In this mode DIV counts samples If a different source is selected for the SC counter AI CONVERT Source Select is not set to 0 then SCKG 1 In this mode DIV counts edges on the source clock The DIV load signal DIV LOAD enables the DIV counter to reload from the selected load register on the next clock DIV LOAD is asserted when DIV TC is reached and SCKG is high or is asserted by software DIV Load The DIV count enable signal DIV CE allows the DIV counter to count DIV CE asserts on any transition originating from or terminating at the CNT state provided the DIV counter is armed DIV Arm and SCKG is high The DIV disarm signal DIV DISARM clears the Arm bit in the register map DIV DISARM asserts on the transition from the CNT state to the WAIT state when AI End On End Of Scan AI End On SC TC or AI Trigger Once is high National Instruments Corporation 2 129 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control lt gt _5 1 DIV Arm TC SG End
285. ad 4 42 Load A 4 43 Load B 4 43 DAQ STC Technical Reference Manual Index Load Source Select 4 43 Gi Loading On Gate 4 44 Gi Loading On TC 4 44 Next Load Source St 4 44 Gi No Load Between Gates St 4 44 Gi OR Gate 4 45 Gi Output Mode 4 45 Gi Output Polarity 4 45 Gi Output St 4 45 Gi Permanent State Data St 4 46 Gi Read Acknowledges Irq 4 46 Gi Reload Source Switching 4 46 Gi Reset 4 46 Gi Save Copy 4 47 Save St 4 47 Save Trace 4 47 Save Value 4 47 Gi Source Polarity 4 48 Source Select 4 48 Gi Stale Data St 4 48 Gi Stop Mode 4 48 Gi Synchronized Gate 4 49 Error Confirm 4 49 Gi TC Error St 4 49 Gi TC Interrupt 4 49 Gi TC Interrupt Enable 4 50 Gi TC Second Enable 4 50 Gi TC St 4 50 Gi Trigger Mode For Edge Gate 4 50 Up Down 4 51 Gi Write Acknowledges Irq 4 51 Write Switch 4 51 GPFO 0 Output Enable 4 51 GPFO 0 Output Select 4 52 GPFO 1 Output Enable 4 52 GPFO 1 Output Select 4 52 interrupt control 8 12 to 8 14 Interrupt A Enable 8 12 Interrupt Output Select 8 12 DAQ STC Technical Reference Manual 16 Interrupt St 8 13 Interrupt B Enable 8 13 Interrupt Output Select 8 13 Interrupt St 8 13 Interrupt Output On 3 Pins 8 13 Interrupt Output Polarity 8 13 Pass Thru Interrupt Enable 8 14 Pass Thru Interrupt P
286. address 4 This bit disables recognition of the STARTI trigger 0 Enabled 1 Disabled Use this bit if you want the same STARTI trigger to start several activities First disable STARTI by setting this bit to 1 do the necessary programming on all DAQ STCs and then enable STARTI by setting this bit to O DAQ STC Technical Reference Manual 2 76 National Instruments Corporation Chapter 2 Analog Input Timing Control START1 Edge bit 5 type Write in AI Trigger Select Register address 63 This bit enables edge detection of the STARTI trigger 0 Disabled level sensitive trigger 1 Enabled edge sensitive trigger You should normally set this bit to 1 You must set this bit to 1 if AI 5 Select is set to 0 You should set this bit to 0 if the ASIC is a STARTI slave to another DAQ STC START1 Interrupt bit 9 type Strobe Interrupt Ack Register address 2 Setting this bit to 1 clears AI STARTI St and acknowledges the STARTI interrupt request in either interrupt bank if the STARTI interrupt is enabled This bit is cleared automatically Related bitfields AI STARTI St START1 Interrupt Enable bit 1 type Write in Interrupt Enable Register address 73 This bit enables the STARTI interrupt 0 Disabled Enabled The STARTI interrupt is generated on valid STARTI triggers received by the DAQ STC A valid STARTI trigger is one that is received while the SC counter is armed a
287. al Chapter 4 General Purpose Counter Timer 4 8 7 1 START STOP on G CONTROL The START STOP behavior depends upon the G CONTROL conditioning The conditioning can be set to no gating level gating or edge gating With no gating the counter is always enabled to count With level gating the counter is enabled to count only when the G CONTROL is ACTIVE unless Gi Trigger Mode For Edge Gate is set to 3 In this case the counter is always enabled to count With edge gating several modes of START STOP counting are available The START STOP counting modes are described in the following table Table 4 16 START STOP Modes for Edge Gating Gi Trigger Mode For Edge Gate Selected START STOP Mode 0 First Control ACTIVE edge starts counting the next ACTIVE edge stops counting 2 Counter begins counting when CONTROL becomes ACTIVE and then remains in the counting state 3 Counter always enabled to count 4 8 7 2 Save on G GATE If gating is enabled the counter value is saved in the HW save register The HW save register is implemented in hardware as a transparent latch Normally the latch is in hold mode On the GATE edge that generates an interrupt refer to Table 4 18 the HW save register switches to transparent mode causing the latch to load the current counter value On the next G SOURCE falling edge the latch returns to hold mode 4 8 7 3 Reload on G CONTROL Tab
288. an event comes from the configuration memory On a typical board without configuration memory the end of scan event is generated by the DIV counter Notice that the DAQ STC cannot simultaneously generate end of scan events and timing for an external signal multiplexer Function AI Scan End Begin critical section AI_Configuration_Start 1 If the end of scan is coming from the outside either PFI or Configuration FIFO then National Instruments Corporation 2 37 DAQ STC Technical Reference Manual Chapter 2 DAQ STC Technical Reference Manual 2 36 Analog Input Timing Control Else L AI STOP Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI lt 0 6 gt or 19 signal present on the AI STOP IN pin AI STOP Edge 0 AI STOP Polarity 0 active high or rising edge or 1 active low or falling edge AI STOP Sync 1 If you have a vary fast board you may need to use an asynchronous STOP AI STOP Sync 0 If more than one channel per scan then Else DIV counter is used as the STOP source AI STOP Select 0 DIV TC AI STOP 1 AI STOP 0 AI STOP Polarity 0 AI DIV Load A number of channels per scan 1 L AI_DIV_Load 1 Force START signal to be always high AI STOP Select 31 logic low AI STOP Sync 0 AI STOP Edge 0 AI STOP Polarity 1 AI Configuration End 1 End critical section
289. analog output 3 12 to 3 16 continuous mode 3 13 to 3 14 master slave trigger 3 15 to 3 16 mute buffers 3 15 overview 3 21 resetting 3 21 to 3 22 sequence of functions 3 31 to 3 32 starting the waveform 3 30 to 3 31 stop on error 3 29 trigger signals 3 23 to 3 24 update selection 3 26 to 3 28 National Instruments Corporation 5 DAQ STC Technical Reference Manual Index secondary analog output operation 3 38 to 3 42 arming 3 41 board power up initialization 3 39 changing update rate 3 44 to 3 45 counting for waveform staging 3 40 hardware gate programming 3 39 interrupts 3 45 master slave operation considerations 3 45 overview 3 38 resetting 3 38 software gate operation 3 40 update selection 3 40 to 3 41 waveform staging 3 42 to 3 44 analog output timing control module 3 1 to 3 124 block diagram 3 109 counters 3 117 to 3 121 BC control 3 120 to 3 121 BC counter 3 120 UC control 3 119 UC counter 3 118 to 3 119 UI control 3 118 UI counter 3 117 UI2 control 3 121 UI2 counter 3 121 error detection 3 122 to 3 123 BC error 3 123 BC TC trigger error 3 123 overrun error 3 122 UI2_TC error 3 123 features 3 2 to 3 3 functions See analog output functions internal signals and operation table 3 109 to 3 114 interrupt control 3 122 nominal signal pulsewidths 3 124 output control 3 123 to 3 124 overview 3 1 to 3 2 pin interface table 3 16 to 3 20 D
290. and may come from a number of different sources such as PFI RTSI software and the internal signal STARTI from the AITM 3 4 Analog Output Functions The basic analog output functionality provided by the DAQ STC is the timing of up to 16 independent double buffered DACs fed by a single FIFO Many variations on this basic function are possible This section provides an overview of the basic analog output functions and indicates some of the likely variations First a distinction between DAQ STC driven analog output and CPU driven analog output is made Next some of the methods of providing analog output data are described This is followed by a description of the parameters involved in UPDATE timing and buffer timing Finally the external gating function and secondary analog output are described 3 4 1 Primary Group Analog Output Modes Two modes of operation are possible with the AOTM DAQ STC driven analog output and CPU driven analog output In the DAQ STC driven mode the DAQ STC generates the timing necessary to move data from memory to the DACs according to the programmed instructions The programming specifies the number of points to output and in the internal UPDATE mode the rate at which to output the points In the CPU driven mode the CPU alone determines when the points are output In some cases DAQ STC driven and CPU driven analog output may occur simultaneously on different channels in which case arbitration is provided by t
291. and pulse generation functions and supply timing and trigger signals to the other modules The programmable function inputs and RTSI trigger modules have internal multiplexers to route signals among the DAQ STC and the RTSI and I O connectors so that you can operate the board with external timing and trigger signals or you can output internally generated timing and trigger signals to either connector The digital I O module enables you to transfer serial and parallel data between the CPU and an external device The interrupt control module simplifies software design by routing both board level and internally generated interrupts to the CPU subsystem and the bus interface module enables the DAQ STC to communicate easily with most computer buses Finally the miscellaneous functions module provides extra features such as clock distribution the programmable frequency output and analog triggering National Instruments Corporation 1 1 DAQ STC Technical Reference Manual Chapter 1 Introduction 1 1 DAQ STC Applications 1 1 1 The primary function of the DAQ STC is to provide timing and control for the A D and D A subsystems of a DAQ board To understand the DAQ STC you should be familiar with a typical implementation of an A D and D A board This section presents a typical implementation of these two primary functions and familiarizes you with the components controlled by the DAQ STC The remaining functions such as digital I O a
292. and returns to latched mode on the next SOURCE falling edge Figure 4 40 shows an example of buffered semiperiod measurement where the first semiperiod is four G SOURCE rising edges and the second semiperiod is three G SOURCE rising edges The dotted line indicates where the ARM occurs and the arrows indicate where the gate interrupt is generated G SOURCE G GATE KX 4 G CONTROL Counter Load YGOGOCOGOGOCOCOCGOGOCOC a a Counter Value 1 HW Save Register Figure 4 40 Buffered Semiperiod Measurement National Instruments Corporation 4 79 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 8 11 10 Buffered Pulsewidth Measurement To use this function set G CONTROL conditioning to level gating and program the counter to reload CONTROL and generate interrupts on The counter increments on every SOURCE rising edge following the ARM GATE is synchronized by the falling edge of G SOURCE to generate G CONTROL On the G SOURCE rising edge following CONTROL the counter reloads from the selected load register The HW save register switches to transparent mode on the falling edge of G_GATE and returns to latched mode on the next G SOURCE falling edge Figure 4 41 show an example of buffered pulsewi
293. ange Scan Rate during an Acquisition You can change the scan rate if you do not have special requirements on the timing for the STARTI to START in retriggerable analog input or if the acquisition is not retriggerable This will not work in the case of retriggerable analog input with nondefault START1 to START timing Assume that the sequence of START rates is stored in the array si ticks and the variable si ticks pointer indicates the current position in the array You can use the following function to change the scan rate Function Scan Rate Change If acquisition is not retriggerable OR you will change the scan rate during an acquisition then If si last load register is 0 then Tf the last load was from the last load register written to it is all right to change the rate Otherwise you cannot change the rate If AI_SI_Next_Load_Source_St is 0 then AI_SI_Load_B si ticks si ticks pointer l si ticks 1 1 si last load register l If switch SI load registers on TC then AI SI Switch Load On 1 Else AI SI Switch Load On SC Else Scan rate change cannot be performed Else If AI SI Next Load Source St is 1 then AI SI_Load_A si_ticks si_ticks_pointer 1 si_ticks_pointer 1 si_last_load_register 0 If switch SI load registers on TC then AI SI Switch Load 1 National Instruments Corporation 2 43 DAQ STC
294. ansition 4 8 7 6 Change Output Polarity on G GATE When Gi Output Mode is set to 3 the counter output G OUT toggles on GATE transition to ACTIVE and on every counter TC 4 8 7 7 Select Load Register on G CONTROL When Gi Gate Select Load Source is set to 1 an ACTIVE G CONTROL selects load register and an INACTIVE CONTROL selects load register B National Instruments Corporation 4 69 DAQ STC Technical Reference Manual Chapter 4 4 8 8 4 8 9 General Purpose Counter Timer 4 8 7 8 Disarm Counter on G CONTROL If Gi Counting Once is set to 2 or 3 the counter is disarmed following the CONTROL transition that stops the counting 4 8 7 9 Switch Load Bank Selection on G CONTROL If Gi Bank Switch Enable is set to 1 and Gi Bank Switch Mode is set to 0 and bank switching has been started an ACTIVE CONTROL selects bank X and an INACTIVE G CONTROL selects bank Y Interrupt Control The GPCT module contains the hardware necessary for generating software interrupts based on several conditions The interrupt programming is accomplished using the Interrupt Enable Register general purpose counter 0 and the Interrupt B Enable Register general purpose counter 1 Interrupts remain active until cleared by software Software can program the interrupts to occur under the following conditions assertion of counter TC and gate Refer to Table 4 18 for a description of the gate interrupt conditions
295. anual Chapter 3 Analog Output Timing Control Table 3 5 External Trigger Timing Name Description Minimum Maximum Ts strtl STARTI setup to UPDATE SRC 10 Tstrtl STARTI pulsewidth edge mode 6 Th strt1 5 hold from UPDATE SRC 10 level mode All timing values are in nanoseconds 3 7 11 Trigger Output You can output the internal triggers to the board through the PFI or RTSI interface This section lists the propagation delays for the triggers when you configure them for output to the board 3 7 11 1 START1 Trigger You can output the START 1 trigger on the PFI output PFI6 AO_START 1 or on any RTSI output Timing for the START trigger depends on whether you select synchronous mode asynchronous mode using AO STARTI Sync Synchronous Mode When you select synchronous mode for STARTI the timing depends on whether you select internal UPDATE or external UPDATE using UPDATE Source Select In the internal UPDATE mode the inactive edge of the UI source that recognizes the external trigger generates the output Figure 3 29 shows the propagation delays for STARTI DAQ STC Technical Reference Manual 3 104 National Instruments Corporation Chapter 3 Analog Output Timing Control START1 UI Source 16 START1 E Trtsi RTSI_TRIGGER lt 0 66 gt Tord RTSI_BRD lt 0 3 gt Name Description Minimum Maxi
296. application 8 4 3 Bitfield Descriptions Bits in the register bit maps are organized into bitfields A bitfield can contain one or more bits Only bits with contiguous locations within a register can belong to a bitfield The high and low pairs of load and save registers for 24 bit counters are also treated as bitfields The interrupt control related bitfields are described below Not all bitfields referred to in section 8 4 Programming Information are listed here To locate a particular bitfield description within this manual refer to Appendix B Register Information Interrupt_A_Enable bit 11 type Write in Interrupt_Control_Register address 59 This bit enables interrupt request generation on the OUT pin selected by Interrupt_A_Output_Select 0 Disabled 1 Enabled Related bitfields Interrupt_A_Output_Select Interrupt_A_Output_Select bits lt 8 10 gt type Write in Interrupt_Control_Register address 59 This bit selects the output pin OUT O 7 for interrupt group A 0 7 IRQ lt 0 7 gt DAQ STC Technical Reference Manual 8 12 National Instruments Corporation Chapter 8 Interrupt Control Interrupt A St bit 15 type Read in AI Status 1 Register address 2 This bit indicates whether an interrupt is asserted in interrupt group A 0 No interrupts asserted 1 Atleast one interrupt asserted Interrupt B Enable bit 15 type Write in Interrupt Control Register address 59 This bit enab
297. are directly accessible from the register map If the counter is disarmed UC Load loads the counter with the value from the selected load register During normal operation the UC counter synchronously reloads from the selected load register following TC Two options AO UC Switch Load On End and AO UC Switch Load On the selected load register under various conditions DAQ STC Technical Reference Manual 3 118 National Instruments Corporation Chapter 3 Analog Output Timing Control The options to switch load registers on the next TC and switch load registers on the next UC TC The UC control circuit generates the count enable signals The UC save register latch signal asserts after a rising then a falling edge of BC SRC following a 1 being written to AO UC Save Trace The UC save register latch signal deasserts after a rising then a falling edge of BC SRC following a zero being written to AO UC Save Trace 3 8 3 4 UC Control The UC counter is controlled by a circuit whose state transitions are shown in Figure 3 38 The UC counter control circuit has two states WAIT and CNT On power up the control circuit begins and remains in the WAIT state until the counter is armed and a STARTI pulse 16 received When these two events occur the control circuit moves to the CNT state and the counter begins counting On UC the control circuit either remains in CNT or returns to the WAIT state dep
298. ase is 0 this bit determines the pulsewidth of the CONVERT and PFI2 CONV output signals If AI CONVERT Pulse Timebase is 1 and AI CONVERT Original Pulse is 0 this bit determines the maximal pulsewidth of the CONVERT PFI2 CONV signals so that the pulsewidth is equal to the shorter of this pulsewidth and the original signal pulsewidth The pulsewidths are as follows 0 1 5 2 AI OUT TIMEBASE periods 1 0 5 1 AI OUT TIMEBASE periods Related bitfields CONVERT Pulse Timebase AI CONVERT Original Pulse CONVERT Source Polarity bit 5 type Write in AI Mode 1 Register address 12 This bit selects the of active edge of the CONVERT source the signal that is selected by AI CONVERT Source Select 0 Falling edge 1 Rising edge You must set this bit to O in the internal CONVERT mode Related bitfields AI CONVERT Source Select CONVERT Source Select bits lt 11 15 gt type Write in AI Mode 1 Register address 12 This bitfield selects the CONVERT source 0 The internal signal SI2 TC inverted 1 0 PFI lt 0 9 gt 11 17 RTSI TRIGGER O 6 19 The internal signal from general purpose counter 0 31 Logic low When you set this bit to 0 the DAQ STC is in the internal CONVERT mode When you select any other signal as the CONVERT source the DAQ STC is in the external CONVERT mode Delayed START bit 9 type Write in AI Mode 3 Register address 87 This bit determines when the STARTI trigg
299. ast Sample Clock This signal is the output of the CONVERT selector after polarity selection Related bitfields AI CONVERT Source Select AI CONVERT Polarity Select DAQ STC Technical Reference Manual 2 114 National Instruments Corporation Chapter 2 Analog Input Timing Control Table 2 9 Internal Signals Continued Signal Description FSC SRC Fast Edge of SC Source This signal synchronizes signals that arrive asynchronously but need to be retimed by 5 SRC In the internal CONVERT mode FSC SRC is equal to the inactive falling edge of SI2_SRC In the external CONVERT mode FSC SRC is equal to FSCLK IN TIMEBASE2 Slow Internal Timebase This signal is derived from the IN TIMEBASE signal and is usually configured to be 100 kHz Related bitfields Slow Internal Time Divide 2 Slow Internal Timebase SC CE SC Count Enable This signal enables and disables the SC counter Refer to section 2 8 3 2 SC Control for the SC CE logic equations SC CLK SC Clock This is the actual clock signal for the SC counter and the SC counter control logic When the counter is not armed SC CLK is derived from the write strobe for AI Command 1 Register so that the counter can be loaded using the load command When the counter is armed SC is the same as SC SRC Related bitfields AI SC Load SC GATE SC Counter Gate This signal is generated by the SC control logic SC conditions th
300. at the counter can be loaded using the load command When the counter is armed CLK is the same as SRC UC DISARM UC Disarm This signal which is generated by the UC control circuit disarms the UC counter by asynchronously clearing AO UC Arm UC HOLD UC Hold This signal controls the UC save register If UC HOLD 0 the UC save register tracks the UC counter output If UC HOLD the UC save register latches the UC counter output Related bitfields AO UC Save Trace UC LOAD UC Load This signal pulses to load the value from the selected UC load register into the UC counter Related bitfields UC Load DAQ STC Technical Reference Manual 3 112 National Instruments Corporation Chapter 3 Analog Output Timing Control Table 3 6 Internal Signals Continued Signal Description UC LOAD SRC UC Load Source This signal determines which load register A or B the UC counter will use on the next reload The initial UC load source is set using AO UC Initial Load Source The UC control logic updates the UC LOAD SRC while the DAQ STC is counting Related bitfields UC Initial Load Source AO UC Next Load Source St UC TC Update Counter TC This signal indicates to the counter control logic that the programmed number of updates has been generated end of a buffer UI CE UI Count Enable This signal enables and disables the UI counter It is true w
301. ata output signal digital I O 4 serial data input signal 16 bit divide down counter DIV clock enable signal DIV clock signal DIV load signal DIV counter TC signal direct memory access end of conversion signal equivalent time sampling external multiplexer clock signal external strobe signal external strobe serial data clock signal external clock signal external DIV_TC signal external gate signal G 5 DAQ STC Technical Reference Manual Glossary EXT GATE2 F F FIFO FOUT FSCLK FSC SRC FSK G GO TC GHOST GND GOUTO GOUTI GPCT G CONTROL GATE G IN TIMEBASEI secondary external gate signal Farad first in first out frequency output signal fast sample clock fast update clock signal fast edge of SC source frequency shift keying TC signal from general purpose counter 0 ghost input signal ground OUT signal from general purpose counter 0 OUT signal from general purpose counter 1 general purpose counter timer module GPCT counter control signal GPCT gate input signal internal timebase for GPCT module G OUT GPCT output signal TBI internal signal IN TIMEBASEI G TC GPCT counter TC signal G UP DOWN GPCT up down control input signal DAQ STC Technical Reference Manual G 6 National Instruments Corporation G UP DOWNO G UP DOWNI H HW ICM ID II IL INTEL MOTO INTERRUPT INTERRUPT G OUT INT SCLK SEL IN TIMEBASE2 Ton I ol IRQ_IN
302. ate Operation sess 2 31 2 6 3 8 Trigger Signals tee eere 2 32 2 6 3 9 Number of Scans edet eee bets 2 33 2 6 3 10 Start of SCan coe aote cc eee te eet A ets 2 34 2 6 3 11 of 2 37 2 6 3 12 Convert Signal etse deae 2 38 2 6 3 13 Enable Interrupts 2 40 2 6 3 14 eroe tgo o nee tci a erede us 2 41 2 6 3 15 Starting the Acquisition 2 41 2 6 3 16 Analog Input Program 2 42 2 6 4 Single 2 42 2 6 5 Change Scan Rate during an 2 43 2 6 6 Staged Acquisition inde retenue tret Huren 2 44 2 6 7 Master Slave Operation Considerations esses 2 45 2 6 8 Analog Input Related Interrupts 2 46 2 6 9 Bitfield 2 48 27 Timing Diagrams eoe eee prn he e ES 2 84 2 7 1 Signal Definitions en 2 84 2 7 1 1 CONVERT SRC eno eei rore titii 2 84 2 1 1 2 OUT CLR erre 2 85 27 2 Basic Analog Input 2 86 2 7 3 Data FIP OSs AR ne eee E EEEE 2 88 2 7 4 Configuration 2 89 2 7 5 Maximum Rate Analog 2 91 2 7 6 External CONVERT 2 2 92 2 7 7 External Triggets secessit 2 93 2 7 8 Trigger Output enne RR OE Po ora 2 97 2 7 8 1 START and START Triggers
303. ated by the AO FIFO Mode bitfield UPDATE Interrupt Interrupts are generated on the trailing edge of UPDATE UD TC Interrupt Interrupts are generated on the trailing edge of UPDATE2 3 8 5 Error Detection The DAQ STC can detect error conditions that occur during the analog output operation There are three primary analog output errors overrun TC and BC TC trigger and one secondary analog output error UI2 TC error 3 8 5 1 Overrun Error An overrun error occurs when an UPDATE command is issued to a DAC that was not loaded with data In hardware this is detected when an UPDATE pulse occurs before all of the TMRDACWR pulses from the previous UPDATE have completed The TARDACWR pulses from the previous UPDATE may not have completed for several reasons such as interference from CPU writes to the DACs an UPDATE interval that is too short or a FIFO empty condition that delayss TMRDACWR DAQ STC Technical Reference Manual 3 122 National Instruments Corporation Chapter 3 Analog Output Timing Control 3 8 5 2 BC TC Error During waveform staging for primary analog output software loads the parameters for each MISB during the previous MISB The software must complete this programming operation before the end of the current MISB A BC TC error occurs when the parameters for the next MISB are not written in the allotted time The error detection circuit is armed on each BC TC If a software clear BC TC Interrupt
304. ation 4 4 4 Pulse Train Generation In the pulse train generation functions the counter generates a continuous stream of pulses of specified interval and duration following the software arm and an optional hardware trigger The software arm occurs when software sets the counter arm bit in the DAQ STC register map The following actions are available in pulse train generation e Specify the pulse parameters in terms of periods of SOURCE input e The G_GATE input can serve as a trigger signal to generate a stream of pulses only after the active gate edge occurs hardware provides an alternate output mode so that OUT outputs two counter TC pulses instead of a single long pulse 4 4 4 1 Continuous Pulse Train Generation This function generates a sequence of pulses with programmable delay from trigger pulse interval and pulsewidth The counter uses G SOURCE as a timebase to generate the pulses so you specify the programmable parameters in terms of periods of the G SOURCE input Pulse train generation is implemented in software by loading the pulse parameters into the counter and load resisters and by programming the counter to switch load registers on every counter TC Figure 4 16 shows the generation of three pulses with a delay from trigger of three a pulse interval of four and a pulsewidth of three DAQ STC Technical Reference Manual 4 12 National Instruments Corporation Chapter 4 General Purpose Counter Time
305. ational Instruments Corporation Chapter 2 Analog Input Timing Control 51 5 1 nod B SI Arm i si TC G SC TC H AI End On End Of Scan ALEnd On SC SUME J Al Continuous N Trigger Once P ALSI Tonce Nye sse MET T SI LOAD E SI Load SI CE AL SI Arm CNT1 n 1 SI DISARM CNT1 n WAIT1 n 1 H I Figure 2 50 51 Control Circuit State Transitions 2 8 3 5 SI2 Counter The SI2 counter is a 16 bit down counter with dual load registers The SI2 counter counts the interval between samples as well as the delay from the START signal to the first sample pulse The SI2 counter uses the same clock that is selected for the SI counter SI SRC or AI IN TIMEBASE I The counter load registers are directly accessible from the register map If the counter is disarmed 512 Load will load the counter with the value from the selected load register During normal operation the SI2 counter will synchronously reload from the selected load register following SI2 TC The SI2 Reload Mode option allows the SI2 counter to alternate load registers once after every STOP The SI2 control circuit generates the count enable signals 2 8 3 6 SI2 Control The SI2 counter is controlled by a circuit whose state transitions are shown in Figure 2 51 The SI2 counter control circuit has three states WAIT1 WAIT2 and CNT On power up the coun
306. auses the BC UC and UI counters to be disarmed at the next TC You can use this bit to stop waveform generation in the continuous mode This action is internally synchronized to the falling edge of the UC source This bitis cleared automatically Related bitfields Continuous 0 Error Interrupt Ack bit 13 type Strobe Interrupt Ack Register address 3 Setting this bit to clears Overrun St and acknowledges the Error interrupt request in either interrupt bank if the Error interrupt is enabled This bit is cleared automatically Related bitfields AO Overrun St 0 Error Interrupt Enable bit 5 type Write in Interrupt Enable Register address 75 This bit enables the Error interrupt 0 Disabled 1 Enabled The Error interrupt is generated on the detection of an overrun error condition National Instruments Corporation 3 53 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 Error Second Irq Enable bit 5 type Write in Second Irq B Enable Register address 76 This bit enables the Error interrupt in the secondary interrupt bank 0 Disabled 1 Enabled The Error interrupt is generated on the detection of an overrun error condition External Gate Enable bit 15 type Write in AO Output Control Register address 86 Setting this bit to 1 enables external gating for the primary analog output group excluding UD This bit is not supported on the f
307. ay to accomplish this The delay is implemented as an MISB section where all of the internal counters operate but the output signals are shut off A single control bit AO Mute determines whether an MISB section is muted For the case in which a single MISB is repeatedly output with a mute MISB serving as a delay software is required only to shut off the waveform generation at an appropriate time Figure 3 13 shows an example of how mute buffers can be used to introduce pauses in the analog output timing In the example a single buffer containing two points is repeated twice generating four update pulses A mute buffer is then inserted to give the desired delay This process can be repeated as many times as required Mute Mute START1 _ BC i h Figure 3 13 Mute Buffers 3 4 5 5 Master Slave Trigger Master slave triggers should be used whenever it is required for multiple DAQ STC ASICs to output data in a synchronized manner that is when multiple ASICs share the same START1 trigger In master slave triggering one DAQ STC is designated to be the master trigger ASIC sourcing the STARTI trigger to the other ASICs through the PFI lt 0 9 gt or TRIGGER O 6 interface This provides better synchronization performance than if all DAQ STC
308. ayed STARTI 5 Polarity AO UD Source Polarity AO UD Source Select AO UD Source Select AO UD Source Select AO UD Source Select AO UD Source Select STARTI Sync AO STARTI Edge STARTI Select AO STARTI Select AO STARTI Select AO STARTI Select AO STARTI Select DAQ STC Technical Reference Manual Appendix B Register Information AO UC Load A Registers Address 48 Type Write only 15 Reserved 14 Reserved 13 Reserved Reserved N Reserved Reserved Reserved Reserved AO_UC_Load_A AO_UC_Load_A AO_UC_Load_A AO_UC_Load_A AO_UC_Load_A AO_UC_Load_A AO_UC_Load_A AO_UC_Load_A AO UC Load B Registers Address 50 Type Write only 15 Reserved 14 Reserved 13 Reserved Reserved N Reserved Reserved Reserved Reserved AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B _ 1 OO DAQ STC Technical Reference Manual B 22 Address 49 ee NUR 5 HRN Address 51 9 DO NW gt tA AO UC Load A Registers Type Write only AO Load AO Load AO Load AO UC Load A AO Load A AO Load AO Load AO Load AO Load A AO Load A AO UC Load A AO Load
309. bers in parentheses refer to the number of clock periods that will occur at the minimum and maximum delays because those parameters are clock edge driven with possible additional gate delays The CONVERT signal can be programmed to be one or two OUT CLK periods refer to AI CONVERT Pulse Width The CONVERT synchronization circuit counts either two or four OUT CLK edges regardless of polarity The EOC input must be connected for the proper operation of SHIFTIN which is asserted on the active edge of EOC SHIFTIN is held for a falling clock edge and then one or two rising edges refer to AI SHIFTIN Pulse Width National Instruments Corporation 2 87 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 2 1 3 Data FIFOs In addition to the SHIFTIN signal the input signals AIFFF and AIFEF and the output signal AIFREQ are available for interfacing to a data FIFO The SHIFTIN signal is used to write the data into the FIFO and the CPU or a DMA controller will typically read those values The FIFO flags will change only after a read a write a retransmit or a FIFO reset The AIFREQ signal is based on these FIFO flags as well as on the last TC of the SC counter AIFREQ can be configured internally to generate interrupt requests refer to AI FIFO Interrupt Enable and can be used externally for such purposes as generating DMA requests The timing for these signals is shown in Figure 2 17
310. binary down counter that generates update interval timing The UI2 counter is a 16 bit binary down counter that generates a second independent update interval The UC counter is a 24 bit binary down counter that counts the number of UPDATEs The BC counter is a 24 bit binary down counter that counts the number of cycles or buffers generated that is the TC of the UC counter Notice UI2 does not have associated update or buffer repetition counters It is primarily intended to be used in an interrupt driven waveform generation where these functions are provided by software The UI counter alternate first period reload modes provide a retriggerable method for obtaining a delay between the trigger signal and the first update pulse which is different than the update interval The UL UI2 UC and BC counters each has its own control block The counter control blocks are synchronous control circuits that use the counter mode information trigger and gate signals and state of the counter to generate the count enable and load control signals Figure 3 37 shows the state diagram for the UI control block Figures 3 38 and 3 39 show the state diagrams for the UC and BC control blocks respectively 3 8 3 1 UI Counter The UI counter is a 24 bit down counter with dual load registers The UI counter typically counts the interval between UPDATES as well as the delay from the initial trigger to the first update The bitfield AO UI Source Select controls the select
311. bit 6 type Read in AO Status 1 Register address 3 This bit indicates whether the UC counter has reached TC 0 No 1 Yes To clear this bit set AO UC TC Interrupt Ack to 1 Related bitfields AO UC Interrupt Refer to Table 8 2 Interrupt Condition Summary for more information 0 UC Write Switch bit 10 type Write in AO Mode 2 Register address 39 This bit enables the write switch feature of the UC load registers Writes to UC load register A are 0 Unconditionally directed to UC load register A 1 Directed to the inactive UC load register UI Arm bit 10 type Strobe AO Command 1 Register address 9 Setting this bit to 1 arms the UI counter The counter remains armed and the bit remains set until it is disarmed either by hardware or by setting AO Disarm to 1 Related bitfields AO UI Arm AO Disarm National Instruments Corporation 3 71 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control AO UI Armed St bit 5 type Read in AO Status 2 Register address 6 This bit indicates whether the UI counter is armed 0 Disarmed 1 Armed Related bitfields UI Arm UI Count Enabled St bit 8 type Read in AO Status 2 Register address 6 If the UI counter is armed this bit indicates whether the UI counter is enabled to count 0 No 1 Yes If the counter is disarmed this bit should be ignored AO UI Initial Load Source bit 7 type Writ
312. bit is cleared automatically Related bitfields Gate Error St Gi Gate Error St 0 bit 14 type Read Status Register address 4 i l bit 15 type Read Status Register address 4 This bit indicates the detection of a general purpose counter i gate acknowledge latency error 0 No 1 Yes To clear this bit set Gi Gate Error Confirm to 1 Related bitfields Gi Gate Error Confirm DAQ STC Technical Reference Manual 4 38 National Instruments Corporation Chapter 4 General Purpose Counter Timer Gi Gate Interrupt i 0 0 15 type Strobe Interrupt_A_Ack_Register address 2 bit 15 type Strobe Interrupt Ack Register address 3 Setting this bit to 1 clears Gi Gate Interrupt St and acknowledges the gate interrupt request either interrupt bank if the gate interrupt 1s enabled This bit is cleared automatically Related bitfields Gate Interrupt St Gate Interrupt Enable i 0 0 8 type Write in Interrupt Enable Register address 73 i 1 bit 10 type Write in Interrupt_B_Enable_Register address 75 This bit enables the gate interrupt 0 Disabled 1 Enabled The relevant gate edge is Stop edge in case of level gating Active edge both start and stop in case of edge gating Related bitfields Gating Mode Gi_Gate_On_Both_Edges Gi Gate Interrupt St i 0 bit 2 type Read in AI Status 1 Register address 2 bit 2 type Read in AO Stat
313. ble 3 65 STARTI Select 3 65 AO STARTI St 3 65 STARTI Sync 3 65 STOP Interrupt Ack 3 65 STOP Interrupt Enable 3 66 AO Stop On BC TC Error 3 66 AO Stop On BC TC Trigger Error 3 66 AO Stop Overrun Error 3 66 AO STOP Second Irq Enable 3 67 AO STOP St 3 67 DAQ STC Technical Reference Manual Index AO TMRDACWR Pulse Width 3 67 TMRDACWRs In Progress St 3 67 AO Trigger Length 3 67 AO Trigger Once 3 68 AO UC Arm 3 68 AO UC Armed St 3 68 AO UC Initial Load Source 3 68 AO UC Load 3 68 AO UC Load A 3 68 AO Load B 3 69 Next Load Source St 3 69 AO UC Q St 3 69 AO UC Save St 3 69 AO UC Save Trace 3 69 AO UC Save Value 3 70 AO UC Switch Load Every BC TC 3 70 AO UC Switch Load Every TC 3 70 UC Switch Load On BC TC 3 70 AO UC Switch Load On TC 3 70 AO UC Interrupt 3 70 AO UC Interrupt Enable 3 71 AO UC TC Second Irq Enable 3 71 AO UC St 3 71 AO UC Write Switch 3 71 AO UI Arm 3 71 AO UI Armed St 3 72 AO UI Count Enabled St 3 72 AO UI Initial Load Source 3 72 AO Load 3 72 AO Load A 3 72 UI Load B 3 73 AO UI Next Load Source St 3 73 AO UI Q St 3 73 DAQ STC Technical Reference Manual I 14 AO UI Reload Mode 3 73 AO UI Save Value 3 74 AO UI Source Polarity 3 74 AO UI Source Selec
314. bled This bit is cleared automatically Related bitfields DIO HW Serial Enable National Instruments Corporation 7 13 DAQ STC Technical Reference Manual Chapter 7 Digital 1 0 DIO HW Serial Timebase bit 10 type Write in DIO Control Register address 11 This bit selects the timebase used for the EXTSTROBE SDCLK signal during hardware controlled serial digital I O 0 SERIAL TIMEBASE divided by 12 1 2 clock 1 TIMEBASE2 You need to set DIO Serial Divide By 2 to 0 if a 10 MHz oscillator is used and to 1 if a 20 oscillator is used to obtain the frequency indicated in parentheses Use DIO HW Serial Enable to enable hardware controlled serial digital I O Related bitfields DIO Serial Out Divide By 2 DIO HW Serial Enable DIO Parallel Data In St bits lt 0 7 gt type Read in DIO Parallel Input Register address 7 This bitfield is used for digital input on DIO O 7 If a DIO line is configured for output the corresponding bit in this register will reflect the output state DIO Parallel Data Out bits lt 0 7 gt type Write in DIO Output Register address 10 This bitfield is used for data to be output in parallel on DIO lt O 7 gt DIO Pins Dir bits lt 0 7 gt type Write in DIO Control Register address 11 This bitfield selects the directions of the bidirectional pins DIO lt 0 7 gt 0 Input 1 Output Use this field to configure all eight lines on a per line basis
315. by a circuit whose state transitions are shown in Figure 3 37 The UI counter control circuit has two states WAIT and CNT On power up the control circuit begins and remains in state WAIT until the counter is armed and a STARTI pulse is received The control circuit then transitions to state CNT and remains there until the count termination condition is reached For continuous output modes the UI counter control circuit can return to state WAIT based on the software strobes AO End On TC and AO End On UC Also the UI counter normally remains armed and retriggerable at the end of a scan sequence The UI counter has the option AO Trigger Once to disarm itself when returning to the WAIT state DA START1 B AO UI Arm i G BC TC H AO End On BC TC E AO UC TC E AB J AO Continuous M STOP CNT N AO Trigger Once ore e T G H LOAD AO UI Load CE CNT n 1 AO UI Arm UI DISARM CNT n WAIT n 1 I Figure 3 37 UI Control Circuit State Transitions 3 8 3 3 UC Counter The UC counter is a 24 bit down counter with dual load registers and output save latch The UC counter typically counts the number of sample updates contained in a buffer For this reason it is referred to as the update counter The UC counter uses the same clock that is selected for the BC counter SRC The counter load registers
316. by the DAQ STC is to time conversions and load the resulting data into a FIFO The primary output signals are CONVERT and SHIFTIN and the input signals are SOC and EOC The timing for these signals is shown in Figure 2 16 OUT uu X CONVERT SRC N L gt Tcconvd oconv gt Tcsoc CONVERT X Tsoc Tsoceoc SOC 3L 7 EOC gt Tclkshft Teocshft SHIFTEN Tsover gt gt Teover2 p OVER_DETECT A XB Figure 2 16 Basic Analog Input Timing Table 2 3 Basic Analog Input Timing Name Description Minimum Maximum Tcconv CONVERT SRC to CONVERT 19 58 internal convert CONVERT_SRC to CONVERT 21 65 external convert CLK to CONVERT deasserted 12 38 Toconv CONVERT width 0 5 1 5 1 2 Tsoc SOC pulsewidth 6 i Tsoceoc SOC precedes EOC 25 pulsewidth Teocshft EOC to SHIFTIN asserted 21 DAQ STC Technical Reference Manual National Instruments Corporation Chapter 2 Analog Input Timing Control Table 2 3 Basic Analog Input Timing Continued Name Description Minimum Maximum Tshft SHIFTIN pulsewidth 0 5 1 5 1 5 2 5 Tclkshft OUT_CLK to SHIFTIN deasserted 13 38 Tsover Begin overrun detection 10 1 End overrun detection mode
317. cal Reference Manual 1 12 AI START2 Second Irq Enable 2 80 AI START2 Select 2 80 AI START2 St 2 80 AI 5 2 Sync 2 80 AI STOP Edge 2 81 AI STOP Interrupt 2 81 AI STOP Interrupt Enable 2 81 AI STOP Polarity 2 81 AI STOP Pulse 2 81 AI STOP Second Irq Enable 2 82 STOP Select 2 82 AI STOP St 2 82 AI STOP Sync 2 83 AI Trigger Length 2 83 AI Trigger Once 2 83 analog output timing control 3 45 to 3 84 AO Analog Trigger Reset 3 45 AOFREQ Enable 3 46 AOFREQ Polarity 3 46 AO BC Arm 3 46 AO BC Armed St 3 46 AO BC Gate Enable 3 46 AO BC Gate St 3 47 AO BC Initial Load Source 3 47 AO BC Load 3 47 AO Load A 3 47 AO BC Load B 3 47 AO BC Next Load Source 3 48 AO BC Q St 3 48 AO BC Reload Mode 3 48 AO Save St 3 48 AO BC Save Trace 3 48 AO Save Value 3 49 AO BC Source Select 3 49 AO BC Switch Load On TC 3 49 AO BC TC Error Confirm 3 49 AO BC EHrror St 3 49 AO BC TC Interrupt 3 50 AO BC TC Interrupt Enable 3 50 National Instruments Corporation AO BC TC Second Enable 3 50 AO TC St 3 50 AO BC TC Trigger Error Confirm 3 50 AO BC TC Trigger Error St 3 51 AO BC Write Switch 3 51 AO Configuration End 3 51 AO Configuration Start 3 51 AO Continuous 3 52 AO DACi Update Mode 3 52 AO Delayed STARTI 3 52 AO Disarm 3 52 AO Control 3 53 AO End On BC TC 3 53 AO End On UC TC 3 5
318. ce 3 8 DACUPDN signal table 3 111 DACWR lt 0 1 gt signal DAC interface 3 8 decoded signal timing 3 94 to 3 95 description table 3 18 simplified analog output model 3 5 DAQ STC applications 1 2 to 1 4 analog input 1 2 to 1 3 analog output 1 3 to 1 4 block diagram 1 4 features 1 1 overview 1 1 revision history D 1 to D 2 DAQ STC and CPU conflict 3 7 DAQ STC and CPU driven analog output timing 3 90 to 3 92 DAQ STC registers See registers DAQ STC driven analog output 3 6 DAQ STC Technical Reference Manual Index DAQ STC driven analog output timing 3 86 to 3 88 signal names and clock periods table 3 87 to 3 88 signal timing figure 3 87 data FIFOs 2 88 to 2 89 configuration memory timing table 2 89 control signals 2 7 signal timing figure 2 88 data interfaces 3 8 to 3 11 FIFO data interface 3 8 to 3 10 serial link data interface 3 10 unbuffered data interface 3 11 DC characteristics specifications A 3 to A 4 decoded signal timing 3 94 to 3 95 digital I O 7 1 to 7 17 detailed description 7 17 features 7 1 overview 7 1 parallel mode 7 2 to 7 3 parallel input 7 3 parallel output 7 3 pin interface 7 6 to 7 7 programming information 7 7 to 7 15 bitfield descriptions 7 13 to 7 15 control lines 7 12 hardware controlled serial digital I O 7 10 to 7 12 parallel digital I O 7 9 programming the digital interface 7 8 to 7 9 reading status lines 7 13 software con
319. chronous 2 104 STOP Delay Asynchronous 2 104 SC TC Delay ertet er 2 105 SI ICDel ay iine ere cete RE 2 105 Delay t Ru 2 106 Interval Scanning Mode Timing eee 2 106 Free Run Gating Mode Timing Internal CONVERT 2 109 Free Run Gating Mode Timing External CONVERT 2 110 Halt Gating Mode Timing Internal CONVERT 2 111 AITM Block 2 112 START and STOP Routing Logic eee 2 120 5 and START2 Routing 2 120 EXT Routing 2 121 SC Control Circuit State Transitions 2 125 SI Control Circuit State Transitions esse 2 127 SD Control Circuit State 2 128 DIV Control Circuit State 008 2 130 AOTM Simplified 3 4 DAQ STC Driven Analog 3 6 CPU Driven Analog Output essere 3 7 DAQ STC and CPU Conflict eese 3 7 FIFO Interface eoe ede aie iet bank 3 9 Local Buffer Mode petere pitt Pe 3 10 Serial Link Data Interface 3 10 DAQ STC Technical Reference Manual xvi National Instruments Corporation Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17
320. cing the destination address of the DAC write on the CPU bus address lines The DAQ STC responds by lowering CHRDY_OUT to extend the current bus cycle When the hardware is ready the bus address lines A lt 0 3 gt pass through to the AO ADDR O 3 lines and CPUDACWR line pulses to complete the write CHRDY OUT is then released to allow the bus cycle to continue The bus cycle delay signal CHRDY operates in two software selectable modes In the slow interface mode CHRDY deasserts until the write to the DAC is complete In the fast interface mode CHRDY OUT deasserts only until the write to the DAC is initiated maximizing bus bandwidth DAQ STC Technical Reference Manual 3 6 National Instruments Corporation Chapter 3 Analog Output Timing Control Figure 3 3 shows a sequence of three consecutive CPU driven analog output operations one each to the DAC at addresses four five and six In this figure CHRDY OUT is held until the write to the DAC is complete slow interface mode CPUDACREQ CHRDY OUT CPUDACWR AO_ADDR lt 3 0 gt X5X Figure 3 3 CPU Driven Analog Output 3 4 1 3 DAQ STC and CPU Conflict The possibility exists that the CPU and DAQ STC will both attempt to write to the DACs at the same time The CPU is given priority over the DAQ STC but it can not interrupt a DAQ STC write cycle in progress If the DAQ STC is writing to the DACS
321. ck source These are only the nominal pulsewidths the actual synchronization edges and propagation delays are detailed in section 3 7 Timing Diagrams Table 3 9 Analog Output Nominal Signal Widths Signal Source Clock Output Clock UPDATE 1 1 3 UPDATE2 1 1 3 LDACO 1 1 3 LDACI 1 1 3 TMRDACWR 2 3 CPUDACWR 2 3 TMRDACREQ Asserted when data needed removed at TMRDACWR AO lt 0 3 gt Changes on trailing edge of TMRDACWR Bus address pass through during CPUDACWR CHRDY OUT From CPUDACREQ to edge of CPUDACWR DACWRO 2 3 DACWRI 2 3 AOFFRT 1 DAQ STC Technical Reference Manual 3 124 National Instruments Corporation General Purpose Counter Timer 4 1 Overview 4 2 This chapter presents information about the general purpose counter timer GPCT module of the DAQ STC The GPCT consists of two independent 24 bit up down counters each with associated load and save registers and a control structure for implementing some common counting and timing I O functions These timing functions include period measurement pulsewidth measurement event counting single pulse generation and pulse train generation with programmable frequency and duty cycle the percentage of the cycle that the pulse is high Most functions can operate using only one general purpose counter There are two modes of operation for the measurement functions single m
322. cuitry in reset to prevent glitches on the output pins during configuration You should set this bit to 1 when ending the configuration of the analog input circuitry This bit is cleared automatically Related bitfields Configuration Start Configuration Start bit 4 type Strobe Joint Reset Register address 72 This bit holds the analog input circuitry in reset to prevent glitches on the output pins during configuration The following analog input circuits are affected Output circuits Counter control circuits Trigger circuits nterrupt circuits The following circuits are also affected nterrupt Ack Register Autoacknowledge circuit for general purpose counter 0 You should set this bit to 1 when beginning the configuration of the analog input circuitry By doing this you ensure that no spurious glitches appear on the output pins and on the internal circuit components If you do not set this bit to 1 the DAQ STC may behave erroneously This bit is cleared by setting AI Configuration End to 1 Related bitfields AI Configuration End Config Memory Empty St bit 6 type Read in Joint Status 2 Register address 29 This bit indicates the state of the MUXFEF input pin after the polarity selection Related bitfields FIFO Flags Polarity AI Continuous bit 1 type Write in AI Mode 1 Register address 12 This bit determines the behavior of the SC SI SI2 and DIV counters during 5 TC 0
323. cy may be long enough to cause problems in your waveform stage If the interrupt cannot be serviced during one MISB of the waveform the DAQ STC will not be programmed properly for the next MISB To avoid this you should keep interrupt latency and workload on your computer system in mind when programming the DAQ STC for waveform staging Although the DAQ STC cannot eliminate the interrupt latency problem it can detect when an excessive delay has occurred Use this function for servicing the BC_TC interrupt during waveform staging We assume that the parameters for each stage are stored in an array defined as follows bc_new_ticks contains the number buffer iterations in each MISB uc_new_ticks contains the number of updates in each buffer of the MISB ui_new_ticks contains the number of clocks between updates in each MISB new_mute_flag indicates whether the MISB will be muted 1 indicates muting In addition the variable ac_last_load_register keeps track of which load registers should be used and the variable ao tick count to use keeps track of which parameter in the array should be used These variables were first introduced in the Counting function Function AO Staged ISR Declare variables new_bc_ticks number of buffer iterations new_uc_ticks number of updates in each buffer DAQ STC Technical Reference Manual 3 32 National Instruments Corporation Chapter 3 Analog Output Timing Control new ui
324. d National Instruments Corporation 3 51 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 Continuous bit 1 type Write in AO Mode 1 Register address 38 This bit determines the behavior of the BC UC and UI counters during TC 0 Counters will stop on BC TC 1 Counters will ignore BC The counters remain armed and generate UPDATE pulses until an AO End On BC TC or AO End On UC TC command is given until the AOTM is reset using AO Reset or until an AO Trigger Once command is issued Related bitfields AO_End_On_BC_TC AO_End_On_UC_TC AO_Reset AO Trigger Once DAC Update Mode 1 0 2 type Write in AO Command 1 Register address 9 i l bit 4 type Write in AO Command 1 Register address 9 This bit selects the update mode for the LDACi output signals 0 Immediate update mode LDACi outputs an inverted version of the DAC write signals TMRDACWR and CPUDACWR 1 Timed update mode LDACi outputs the UPDATE or UPDATE2 signal See AO Source Select Related bitfields AO LDACi Source Select Delayed START1 bit 14 type Write in AO Trigger Select Register address 67 This bit determines when the START trigger is used by the AOTM 0 Use the STARTI trigger immediately 1 Delay the START trigger by synchronizing it to the BC source Set this bit to 1 in the master ASIC during master slave trigger The slave ASIC can then synchronize to the
325. d AOFEF 0 Active low 1 Active high Related bitfields FIFO Full St AO FIFO Half Full St AO FIFO Empty St 0 FIFO Full St bit 14 type Read in AO Status 1 Register address 3 This bit reflects the state of the AOFFF input signal after the polarity selection which indicates the data FIFO status 0 Not full 1 Full Related bitfields Flags Polarity 0 FIFO Half Full St bit 13 type Read in AO Status 1 Register address 3 This bit reflects the state of the AOFHF input signal after the polarity selection which indicates the data FIFO status 0 Half full or less 1 More than half full Related bitfields Flags Polarity Note The operation of this bit is similar to AI FIFO Half Full St in the analog input section In analog input however the FIFO requires service when itis MORE than half full In analog output the FIFO requires service when it is HALF FULL OR LESS For this reason the analog input and analog output ISRs must check for opposite values when deciding on interrupt servicing 0 FIFO Interrupt Enable bit 8 type Write in Interrupt Enable Register address 75 This bit enables the FIFO interrupt 0 Disabled Enabled The FIFO interrupt is generated on the FIFO condition indicated by AO FIFO Mode Related bitfields FIFO Mode DAQ STC Technical Reference Manual 3 56 National Instruments Corporation Chapter 3 Analog
326. d refer to AI CONVERT Source Select The SI2 counter is started by the START trigger and can be programmed to count anywhere from 2 to 216 clock periods The external signal must meet the setup and pulsewidth requirements that are indicated in section 2 7 7 External Triggers in order to guarantee recognition by the AITM The external signal can be passed through the National Instruments Corporation 2 107 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control DAQ STC or can be internally conditioned The conditioning allows for a shorter CONVERT pulsewidth as the signal is latched and held for two edges of OUT CLK The pass through option passes the original external signal or truncates the external signal after two or four edges of the output clock Because a very short pulse is possible you should take extra care when allowing the signal to pass through the DAQ STC refer to AI CONVERT Pulse Timebase The STOP trigger terminates the current scan and is generated by an external signal or a software strobe refer to AI STOP Select The external signal must meet the setup and pulsewidth requirements indicated in section 2 7 7 External Triggers in order to guarantee recognition by the AITM Although the STOP trigger can be asserted a large number of clock periods before the CONVERT signal it must be held until the SOC for that CONVERT has been asserted The START trigger which is used only in pretrigger acquisitio
327. d 14 15 OxOE OxOF Generic Control Register Write 71 0x47 National Instruments Corporation B 3 DAQ STC Technical Reference Manual Appendix B Register Information Table B 1 DAQ STC Registers Continued Register Name Type Address Hex Address G Status Register Read 4 0x04 Interrupt A Ack Register Write 2 0x02 Interrupt Enable Register Write 73 0x49 Interrupt_B_Ack_Register Write 3 0x03 Interrupt_B_Enable_Register Write 75 Ox4B Interrupt Control Register Write 59 Ox3B IO Bidirection Pin Register Write 57 0x39 Joint Reset Register Write 72 0 48 Joint Status 1 Register Read 27 Ox1B Joint Status 2 Register Read 29 RTSI Board Register Write 81 0x51 RTSI Trig Output Register Write 79 4 RTSI Trig Output Register Write 80 0x50 RTSI Trig Direction Register Write 58 Ox3A Second Enable Register Write 74 Ox4A Second Enable Register Write 76 4 Window Address Register Write 0 0x00 Window Data Read Register Read 1 0 01 Window Data Write Register Write 1 0x01 Write Strobe 0 Register Write 82 0x52 Write Strobe 1 Register Write 83 0x53 Write Strobe 2 Register Write 84 0x54 Write Strobe 3 Register Write 85 0x55 DAQ STC Technical Reference Manual B 4 National Instruments Corporation Appendix B Register Information Table
328. d A DAQ STC Technical Reference Manual Appendix B Register Information AO BC Load A Registers Address 45 Type Write only 15 AO BC Load A 14 AO BC Load A 13 AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Load A AO BC Load A j N AO BC Load Registers Address 47 Type Write only 15 AO BC Load B 14 AO BC Load B 13 AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B N _ gt DAQ STC Technical Reference Manual B 18 Address 46 NUR DO 5 HN Address 18 e NW KN AO BC Load B Registers Type Write only Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Load B AO BC Save Registers Type Read only Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AO Save Value AO Save Value AO Save Value AO Save Value AO
329. d B bit 2 68 AI SI Load bit 2 68 AI SI Next Load Source St bit 2 68 AI SI Q St bit 2 69 AI SI Reload Mode bit 2 69 AI SI Save Value bit 2 69 AI SI Source Polarity bit 2 69 AI SI Source Select bit 2 70 AI SI Special Trigger Delay bit 2 70 AI SI Switch Load SC TC bit 2 70 AI SI Switch Load On Stop bit 2 70 AI SI Switch Load On TC bit 2 70 AI SI Write Switch bit 2 71 AI SI2 Arm bit 2 71 AI SI2 Armed St bit 2 71 AI SD Initial Load Source bit 2 71 AI 512 Load A bit 2 71 AI SI2 Load B bit 2 72 AI SI2 Load bit 2 71 AI SI2 Next Load Source St bit 2 72 AI SI2 St bit 2 72 AI SI2 Reload Mode bit 2 72 AI SI2 Save Value bit 2 72 AI SI2 Source Select bit 2 73 AI SOC Polarity bit 2 73 National Instruments Corporation AI SOC St bit 2 73 AI Software Gate bit 2 73 AI Source Divide By 2 bit 2 73 AI Staged ISR function 2 44 to 2 45 AI START Edge bit 2 74 AI START Interrupt bit 2 74 AI START Interrupt Enable bit 2 74 AI START Output Select bit 2 74 AI START Polarity bit 2 74 AI START Pulse bit 2 75 AI START Second Enable bit 2 75 AI START Select bit 2 75 AI START St bit 2 75 AI Start Stop bit 2 76 AI Start Stop Gate Enable bit 2 76 AI Start Stop Gate St bit 2 76 AI START Sync bit 2 76 AI Start The Acquisition function 2 41 to 2 42 AI STARTI Disable bit 2 76 AI STARTI Edge bit 2 77 AI STARTI Interrupt bit 2 77
330. d Mode AI SI Reload Mode AI SI Reload Mode AI SI Write Switch AI SC Initial Load Source AI SC Reload Mode AI SC Write Switch DAQ STC Technical Reference Manual Appendix B Address 87 15 14 13 N DO Address 77 15 14 13 N Register Information AI Mode 3 Register Type Write only AI Trigger Length AI Delay START AI Software Gate AI SI Special Trigger Delay AI SI2 Source Select AI Delayed START2 AI Delayed STARTI AI External Gate Mode AI FIFO Mode AI FIFO Mode AI External Gate Polarity AI External Gate Select AI External Gate Select AI External Gate Select AI External Gate Select AI External Gate Select AI Personal Register Type Write only AI SHIFTIN Pulse Width AI EOC Polarity AI SOC Polarity AI SHIFTIN Polarity AI CONVERT Pulse Timebase AI CONVERT Pulse Width AI CONVERT Original Pulse AI FIFO Flags Polarity AI Overrun Mode EXTMUX CLK Pulse Width AI LOCALMUX CLK Pulse Width AI AIFREQ Polarity Reserved Reserved Reserved Reserved DAQ STC Technical Reference Manual B 12 Address 60 15 14 13 N _ DO RK Address 18 eS eS 9 NW gt tA AI Output Control Register Type Write only Reserved
331. d and should be initialized to 0 Function Gi Seamless Pulse Train Change See if you can legally change the rate You cannot change the rate twice in a row before generation of at least one cycle of intermediate frequency If Gi_Bank_St equals g_bank_to_be_used then Gi_Load_A pulse interval 1 Gi_Load_B pulsewidth 1 Gi_Bank_Switch_Start 1 If g_bank_to_be_used is 0 then g_bank_to_be_used 1 Else g_bank_to_be_used 0 Else Inform user that pulse generation rate cannot be changed Two pulse train generation modes are defined for the hardware but are not supported in this programming section These are buffered static pulse train generation and buffered pulse train generation 4 6 1 11 Frequency Shift Keying FSK is an application in which a counter is used to generate a rectangular wave whose frequency is controlled by a hardware input An example is generation of a 300 kHz square wave when the controlling signal has a low logic value and a 500 kHz square wave when the controlling signal has a high logic value No errors are detected in this application National Instruments Corporation 4 31 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer Use this function to program a counter for FSK Program the Source to select the signal that you want to use as a reference clock Program the Gate to select the signal that is to be used as a hardware input to control the
332. d on internal selection Table 3 3 UI2 SRC Reference Pin Selection AO UD Source Select Reference Pin 0 The reference pin is OSC or RTSI depending on the clock mode you choose in 5 Clock mode 1 10 PFI lt 0 9 gt 11 17 RTSI lt 0 6 gt 19 UI2 source is selected to be the output of general purpose counter 0 The reference pin is determined by GO Source Select To determine delays for this case the source to output delay Tso from general purpose counter 0 must be added National Instruments Corporation 3 85 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control Table 3 3 12 SRC Reference Pin Selection Continued AO UD Source Select Reference Pin 20 The UI2 source is selected to be the output of general purpose counter The reference pin is determined by Source Select To determine delays for this case the source to output delay Tso from general purpose counter 1 must be added 21 The reference pin is OSC or RTSI OSC depending on the clock mode you choose in RTSI Clock mode 3 7 1 1 OUT CLK OUT represents the AO OUT TIMEBASE signal which can come from OSC input or the RTSI OSC input respectively depending on the clock mode you choose in RTSI Clock mode If the output clock is set for divide by two operation then each edge of OUT represents a rising edge of OSC or OSC Ot
333. d on the level of an analog waveform The test mode provides a method to quickly verify input pin connectivity 10 2 Features The DAQ STC has the following miscellaneous features e Clock distribution Two clock input pins for main clock selection with master slave capability across the RTSI bus Divide by two stage for main clock selection allows more flexible interfacing to slow and fast external components Independent clock multiplexers for selecting the input timebase and the output conditioning clock allowing selection of a fast input timebase for high timing resolution and a slow output conditioning clock to facilitate interfacing to slow components Output pin for board level use of the main clock selection e Frequency output Divides the master timebase by any integer between 1 and 16 e Analog trigger Test mode National Instruments Corporation 10 1 DAQ STC Technical Reference Manual Chapter 10 Miscellaneous Functions 10 3 Clock Distribution The DAQ STC has two timing input pins OSC and RTSI to allow for master slave clock distribution across the RTSI bus as shown in Figure 10 1 In a master slave scheme both master and slave DAQ STCs derive their timing from the RTSI OSC pin to minimize the skew between master and slave The master DAQ STC enables the output driver on its RTSI_OSC pin and the slave disables the driver on its RTSI_OSC pin The clock distribution circuit has divisors and multipl
334. de In the single wire mode one signal is used as both an external START and an external CONVERT Interval scan timing is still permitted although the number of timing parameters is quite limited Figure 2 15 shows an example of three scans of four CONVERT pulses each in single wire mode Single Wire START1 STOP CONVERT y START DAQ STC Technical Reference Manual Figure 2 15 Single Wire Mode National Instruments Corporation Chapter 2 Analog Input Timing Control 2 8 Pin Locator Interface The I O signals relevant to analog input are listed in Table 2 1 An asterisk following a pin name indicates that the default polarity for that pin is active low Pin Type Notation IU TUS O4TU O9TU Input pull up 50 kQ Input pull up 5 Output 4 mA sink 2 5 mA source tri state pull up 50 kQ Output 9 mA sink 5 mA source tri state pull up 50 kQ Table 2 1 Pin Interface Pin Name Type Description AIFEF IU Data FIFO Empty Flag This input generates the FIFO interrupt and the FIFO request signal AIFREQ based on the status of the FIFO The input polarity is selectable and the input state can be directly observed in one of the status registers Source AI data FIFO Related bitfie
335. determines the polarity of STOP trigger 0 Active high or rising edge 1 Active low or falling edge Set this bit to 0 if AI STOP Select is set to 0 You should set this bit to 1 if AI STOP Select is set to 31 STOP Pulse bit 3 type Strobe AI Command 2 Register address 4 Setting this bit to 1 sends a STOP trigger to the counters if the STOP software strobe is selected STOP Select is set to 0 This bit is cleared automatically Related bitfields AI STOP Select National Instruments Corporation 2 81 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control STOP Second Irq Enable bit 4 type Write in Second Irq A Enable Register address 74 This bit enables the STOP interrupt in the secondary interrupt bank 0 Disabled 1 Enabled The STOP interrupt is generated on valid STOP triggers recognized by the DAQ STC A valid STOP trigger is one that is received while the SC counter is enabled to count yet after a valid START Caution must use the STOP interrupt in conjunction with the START interrupt otherwise the STOP interrupt does not execute STOP Select bits lt 7 11 gt type Write in AI START STOP Select Register address 62 This bitfield selects the STOP trigger 0 The internal signal DIV TC or bitfield AI STOP Pulse 1 10 lt 0 9 gt 11 17 RTSI lt 0 gt 18 The internal signal SI2 19 Signal present on the A
336. dge of and returns to latched mode on the next SOURCE falling edge DAQ STC Technical Reference Manual 4 74 National Instruments Corporation Chapter 4 General Purpose Counter Timer Figure 4 35 shows an example of buffered cumulative event counting The dotted line indicates where the ARM occurs and the arrows indicate where the gate interrupt is generated G SOURCE ace amp 1 amp Counter Value 0 X1 X2X3X4X5 X6 X7X8a X x 10 HW Save 2 7 HW Save Register Figure 4 35 Buffered Cumulative Event Counting 4 8 11 5 Relative Position Sensing To use this function program the counter to use G UP DOWN as an up down control G UP DOWN is synchronized by the falling edge of G SOURCE to generate the up down control signal After the ARM the counter increments when up down is high and decrements when up down is low Figure 4 36 shows an example of relative position sensing The dotted line indicates where the ARM occurs G SOURCE UP DOWN Up Down Counter Value TIR G 3 Figure 4 36 Relative Position Sensing National Instruments Corporation 4 75 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 8
337. dicates the detection of an ADC overrun error 0 No error 1 Error The overrun error indicates that the ADC interval is not long enough to complete a conversion This bit can be cleared by setting Error Interrupt Ack to 1 Related bitfields AI Overrun Mode AI Error Interrupt Ack DAQ STC Technical Reference Manual 2 60 National Instruments Corporation Chapter 2 Analog Input Timing Control Pre Trigger bit 13 type Write in AI Mode 2 Register address 13 If AI Continuous is 0 this bit selects between the posttrigger acquisition mode and the pretrigger acquisition mode 0 Posttrigger acquisition mode Pretrigger acquisition mode If AI Continuous is 1 this bit is not used Refer to section 2 4 3 Acquisition Level Timing and Control for more information on the acquisition modes Related bitfields AI Continuous AI Reset bit 0 type Strobe Joint Reset Register address 72 Setting this bit to 1 resets all the resetable registers to their power on state The resetable registers are AI Command 1 Register AI Command 2 Register AI Mode 1 Register AI Mode 2 Register AI Mode 3 Register AI Output Control Register Personal Register AI START STOP Select Register AI Trigger Select Register Setting this bit to 1 also clears all the status bits and interrupts related to AI except those associated with the AI data FIFO This bit is cleared automatically Scan In Progress St
338. dles the interrupts associated with the AOTM board level interrupt input IRQ INI and interrupts associated with general purpose counter 1 The combined interrupt output of both interrupt groups can be enabled on the first two interrupt lines as well This allows pairing up to three pins externally to increase the sink current capability This is useful for buses such as the NuBus which have a single interrupt line but high current sink requirements Two additional independently controlled outputs from each of the two interrupt groups are provided to simplify the interface for hardware acceleration of specific interrupt driven tasks such as general purpose counter timer input using DMA instead of interrupts The additional independent interrupt outputs are called secondary interrupt outputs Features The ICM has the following features e Eight tri statable interrupt lines with high current output stages for direct interface to the bus e Twointerrupt groups with individual channel selections Both groups can share the same interrupt channel e Two external interrupt inputs for board level interrupts generated outside the DAQ STC e 18 internally generated interrupt sources relating to the AITM AOTM and GPCT modules e Two additional independently controlled outputs for each group allow an additional mechanism for interrupt service National Instruments Corporation 8 1 DAQ STC Technical Reference Manual Chapter 8 Interr
339. dth measurement where the pulsewidth is three G SOURCE rising edges The dotted line indicates where the ARM occurs and the arrows indicate where the gate interrupt is generated Figure 4 41 assumes that ARM occurs while G_GATE is low If ARM occurs while G_GATE is high the initial pulse will only be measured from ARM until the end of the pulse HW Save Register G SOURCE Li G GATE V E K G_CONTROL T Counter Load HWSae Counter Value 1 Figure 4 41 Buffered Pulsewidth Measurement DAQ STC Technical Reference Manual 4 80 National Instruments Corporation Chapter 4 General Purpose Counter Timer 4 8 11 11 Single Pulse Generation To use this function program the counter to reload on TC stop at the second TC and count once The counter begins decrementing after the ARM Once the counter TC is reached the counter reloads and counts down to TC again On the second counter TC the counter disarms The load select signal indicates whether the reload occurs from load register A or B Figure 4 42 shows an example of single pulse generation with a pulse delay of five and a pulsewidth of three The dotted line indicates where the ARM occurs G SOURCE Load Select Cou
340. e SOURCE rising edges G GATE G SOURCE ML PLL Counter Value 0i 1 2 3 4 5 HW Save Register 5 Figure 4 8 Single Pulsewidth Measurement 4 4 2 3 Buffered Period Measurement Buffered period measurement is similar to single period measurement except that measurements are taken for multiple periods The counter uses G_SOURCE to measure the time interval between two active edges of the signal present on the G_GATE input counting the number of rising edges that occur on G SOURCE between each pair of active edges of GATE At the completion of each period interval for the HW save register National Instruments Corporation 4 7 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer latches the counter value for software read An interrupt notifies the CPU after each period so that the interrupt software can read the value in the HW save register Figure 4 9 shows two periods of a buffered period measurement where the period is three G SOURCE rising edges G_GATE G SOURCE Counter Value 0 1 2 3 HW Save Register 3 3 Figure 4 9 Buffered Period Measurement 4 4 2 4 Buffered Semiperiod Measurement Buffered semiperiod measurement is similar to buffered period measurement except that the measurements are taken over every semiperiod The counter uses G_SOURCE to measure each half per
341. e 0 DAQ STC Technical Reference Manual 4 32 National Instruments Corporation Chapter 4 General Purpose Counter Timer 4 6 1 12 Pulse Train Generation for ETS ETS is a data acquisition operation in which data on a repetitive waveform with a frequency higher than the Nyquist frequency of the system is obtained by sampling the waveform at instants skewed in relation to the beginning of each wave pulse The DAQ STC general purpose counters can be used to generate timing for ETS No errors are detected in these applications Since the period incrementing circuitry in the DAQ STC is an adder with no overflow detection you will not be notified if overflow occurs Use this function to program a counter for pulse train generation for ETS Program the Source to select the signal that you want to use as a reference clock Program the Gate to select the trigger signal that initiates each pulse Function Pulse Train Generation For ETS Gi_Autoincrement increment value for delay from trigger Gi_Load_Source_Select 0 Gi_Load_A delay from software arm to first edge of pulse 1 Gi_Load 1 X Gi Load B pulsewidth 1 Gi Load Source Select 1 Gi Source Select 0 IN TIMEBASEI1 or 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 IN TIMEBASE2 or 19 other G TC Gi Source Polarity 0 count rising edges or 1 count falling edges Gi Gate Select 1 through 10
342. e 2 95 external UPDATE external trigger timing synchronous edge figure 3 103 synchronous level figure 3 103 primary analog output 3 12 trigger output STARTI delays synchronous mode figure 3 106 EXTMUX CLK signal configuration FIFO control and external multiplexer control 2 8 DAQ STC Technical Reference Manual configuration memory timing 2 89 to 2 91 description table 2 21 nominal pulsewidths table 2 133 simplified analog input model 2 5 EXTSTROBE signal configuration memory timing 2 89 to 2 91 nominal pulsewidths table 2 133 EXTSTROBE SDCLK signal description table 7 7 parallel mode parallel input 7 3 parallel output 7 3 serial input timing figure 7 16 serial mode hardware controlled serial digital I O 7 10 to 7 12 serial input 7 4 serial I O 7 5 serial output 7 4 to 7 5 software controlled serial digital I O 7 12 serial output timing figure 7 16 F fax and telephone support numbers E 2 Fax on Demand support E 2 FIFO configuration FIFO control 2 7 to 2 9 data FIFOs 2 7 2 88 to 2 89 data interface mode 3 8 to 3 10 FIFO mode selection 3 29 to 3 30 FIFO Request Selection function 2 30 FOUT Divider bit 10 13 FOUT Enable bit 10 14 FOUT signal description table 10 10 programming 10 12 purpose and use 10 3 National Instruments Corporation FOUT Timebase Select bit 10 14 free run gating mode theory of operation 2 17 timing for external gate external CONVE
343. e 3 81 AO UPDATE2 Pulse Width 3 81 bus interface module 9 4 to 9 5 Software Reset 9 4 Software Test 9 4 Window Address 9 5 Window Data 9 5 Write Strobe 0 9 5 Write Strobe 1 9 5 Write Strobe 2 9 5 Write Strobe 3 9 5 digital I O 7 13 to 7 15 Control 7 13 DIO HW Serial Enable 7 13 DIO HW Serial Start 7 13 DIO HW Serial Timebase 7 14 DIO Parallel Data In St 7 14 DIO Parallel Data Out 7 14 DIO Pins Dir 7 14 National Instruments Corporation 1 15 Index DIO_Serial_Data_In_St 7 14 DIO_Serial_Data_Out 7 14 DIO_Serial_IO_In_Progress_St 7 15 DIO_Serial_Out_Divide_By_2 7 15 DIO_Software_Serial_Control 7 15 Generic_Status 7 15 general purpose counter timer 4 35 to 4 52 G_Source_Divide_By_2 4 52 Gi_Analog_Trigger_Reset 4 35 Gi_Arm 4 36 Gi_Arm_Copy 4 36 Gi_Armed_St 4 36 Gi_Autoincrement 4 36 Gi_Bank_St 4 36 Gi_Bank_Switch_Enable 4 37 Gi_Bank_Switch_Mode 4 37 Gi_Bank_Switch_Start 4 37 Gi Counting Once 4 37 Gi Counting St 4 38 Disarm 4 38 Gi Disarm Copy 4 38 Gate Error Confirm 4 38 Gi Gate Error St 4 38 Gi Gate Interrupt Act 4 39 Gi Gate Interrupt Enable 4 39 Gi Gate Interrupt St 4 30 Gi Gate On Both Edges 4 39 Gi Gate Polarity 4 40 Gi Gate Second Enable 4 40 Gate Select 4 40 Gate Select Load Source 4 41 Gi St 4 41 Gi Gating Mode 4 41 Gi HW Save St 4 42 Gi HW Save Value 4 42 Gi Little Big Endian 4 42 Lo
344. e The low indication and high indication signals from the comparator are connected directly to the TRIG LO and ANALOG TRIG IN HI pins respectively When the analog trigger circuit is enabled the analog trigger signal takes over the PFIO slot in the PFI input selectors In this case the PFIO AI STARTI pin can no longer be an input although it can still output the analog input STARTI signal Many boards will also have the ability to source an analog trigger to external devices based on DAQ STC timing The output TRIG DRIVE selects the I O direction of the analog trigger signal You have direct control over DRIVE through a bit in the register map National Instruments Corporation 10 3 DAQ STC Technical Reference Manual Chapter 10 Miscellaneous Functions Figures 10 2 through 10 5 show all of the available modes and illustrations of corresponding trigger generation scenarios LOW and HI values are represented with dashed lines and the signal used for triggering is represented with a solid line In the low window mode the trigger indicates when the signal is less than the LOW value The HI value is unused LOW Value Trigger Figure 10 2 Low Window Mode In the high window mode the trigger indicates when the signal value is greater than the HI value The LOW value is unused HI Value Trigger
345. e 3 9 to 3 10 local buffer mode timing 3 96 to 3 97 serial link data interface 3 10 simplified analog output model 3 5 unbuffered data interface 3 11 unbuffered data interface timing 3 98 to 3 100 AOFFF signal DAQ STC driven analog output timing 3 86 description table 3 17 simplified analog output model 3 5 AOFFRT signal description table 3 17 local buffer mode 3 9 to 3 10 DAQ STC Technical Reference Manual Index local buffer mode timing 3 96 to 3 97 simplified analog output model 3 4 AOFHF signal DAQ STC driven analog output timing 3 86 description table 3 17 simplified analog output model 3 5 AOFREQ signal DAQ STC driven analog output timing 3 86 description table 3 17 FIFO data interface 3 8 to 3 9 simplified analog output model 3 5 AOTM See analog output timing control module arming analog input counters 2 41 general purpose counter timer module 4 18 primary analog output operation 3 30 to 3 31 secondary analog output operation 3 41 BC counter control circuitry 3 120 to 3 121 description 3 120 BC CE signal table 3 110 BC CLK signal table 3 110 BC DISARM signal table 3 110 BC HOLD signal table 3 110 BC LOAD signal table 3 110 BC LOAD SRC signal table 3 110 BC SRC signal table 3 110 BC error 3 123 BC TC signal continuous mode 3 13 to 3 14 description table 3 17 3 111 output timing figure 3 107 single buffer mode 3 13 DAQ S
346. e active low or 3 enable active high AI Configuration End 1 End critical section 2 6 3 3 Initialize Configuration Memory Output Use this function to generate a LOCALMUX_CLK pulse that accesses the first value in the configuration FIFO Function Initialize Configuration Memory Output Begin critical section AI_Configuration_Start 1 If an external MUX is present then AI External MUX Present 0 DAQ STC Technical Reference Manual 2 28 National Instruments Corporation Chapter 2 Analog Input Timing Control T AI CONVERT Pulse 1 Pause here long enough that LOCALMUX pulse generated by the CONVERT will have time to clock the configuration FIFO AI External MUX Present 1 Else AI_CONVERT_ Pulse 1 AI_Configuration_End 1 End critical section 2 6 3 4 Board Environment Setup Part of the AITM programming depends only on properties of hardware surrounding the device that the DAQ STC is on For example if you have an MIO board the external hardware can be an AMUX 64T or an SCXI device The major distinction between power up initialization and environment setup is that power up initialization is always the same for a device using the DAQ STC while the latter environmental setup may be different Function AI_Board_Environmentalize Begin critical section AI_Configuration_Start 1 If an external MUX is present then AI EXTMUX CLK
347. e the SI special trigger delay feature of the SI counter allows an extra timing parameter in the scan timing This feature allows you to enforce a minimum delay from the STARTI trigger to the first START When the SI special trigger delay is enabled the SI counter blocks external START pulses for a fixed time period after the START trigger Software can program the SI counter to count edges on the internal IN TIMEBASE signal for an absolute time delay or it can program the SI counter to count edges on the external START signal for a delay in terms of the number of START pulses blocked Figure 2 10 depicts the SI special trigger delay feature where the SI counter counts edges on the internal IN TIMEBASE signal The START1 pulse causes the SI counter to begin counting External START pulses not recognized until the SI TC This feature gives the user greater control over the external START timing External START START1 SI TC START p Figure 2 10 SI Special Trigger Delay National Instruments Corporation 2 13 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 2 4 3 Acquisition Level Timing and Control The SC counter is available to control the acquisition level timing Two trigger signals are available for acquisition level timing the STARTI trigger and the START trigger The DAQ STC has thre
348. e 1 Register address 38 Setting this bit to 1 causes the analog output timing sequence to stop on TC The BC UC and UI counters are disarmed at this time This bit is cleared automatically 0 UC Arm bit 8 type Strobe AO Command 1 Register address 9 This bit arms the UC counter The counter remains armed and the bit remains set until it is disarmed either by hardware or by setting AO Disarm to 1 Related bitfields AO UC Armed St AO Disarm 0 UC Armed St bit 14 type Read in AO Status 2 Register address 6 This bit indicates whether the UC counter is armed 0 Disarmed 1 Armed Related bitfields AO Arm 0 UC Initial Load Source bit 11 type Write in AO Mode 2 Register address 39 If the UC counter is disarmed this bit selects the initial UC load register 0 Load register 1 Load register B If the UC counter is armed writing to this bit has no effect Related bitfields AO Arm 0 UC Load bit 7 type Strobe in AO Command 1 Register address 9 If the UC counter is disarmed this bit loads the UC counter with the contents of the selected UC load register A or B If the UC counter is armed writing to this bit has no effect This bit is cleared automatically Related bitfields UC Initial Load Source 0 UC Load bits lt 0 7 gt type Write in AO UC Load A Registers address 48 bits lt 0 15 gt type Write in AO UC Load A Registers address 49 This
349. e CONVERT signal is the primary timing signal for analog input Three board level subsystems are controlled by CONVERT and the signals derived from CONVERT the ADC the data FIFO and the configuration FIFO and external multiplexer CONVERT timing is affected by your selection of internal or external CONVERT mode DAQ STC Technical Reference Manual 2 6 National Instruments Corporation Chapter 2 Analog Input Timing Control 2 4 1 1 ADC Control The basic function of the ADC control signals is to time ADC conversions and load the resulting digital data into a latch The primary output signals are CONVERT and SHIFTIN and the input signals are SOC and EOC Figure 2 3 shows these signals in a basic data acquisition sequence SOC EOC CONVERT SHIFTIN Figure 2 3 ADC Control The SOC input informs the DAQ STC when a conversion starts Similarly the EOC input notifies the DAQ STC when a conversion completes The assertion of EOC leads to the assertion of SHIFTIN which loads the acquired data into its destination An overrun condition occurs when the conversion rate is too high for the A D subsystem to maintain If a second CONVERT signal occurs before the current conversion is complete the DAQ STC flags an overrun error and generates an interrupt if programmed to do so 2 4 1 2 Data FIFO Control Many DAQ products include data FIFOs to prevent loss of data
350. e Counter Timer Programmable input and output signal polarities One shot continuous or tri state output Two banks of dual load registers that allow seamless frequency and duty cycle changes during double buffered pulse train generation A counter load register that can increment or decrement on TC which allows for equivalent time sampling ETS timing output ETS is a sampling method for repetitive waveforms where the sample point is moved within the cycle Refer to section 4 4 4 5 Pulse Generation for ETS for more information Interevent relative time stamping Two sets of save registers to save the counter value via an external control signal or via software command Current count value can be read without affecting circuit operation Bus interface support Interrupts based TC or on active gate edge rising edge falling edge or any edge Secondary interrupts to facilitate a DMA or local CPU interface for timing functions Not supported in hardware are BCD counting and time of day counting 4 3 Simplified Model The GPCT module contains two identical 24 bit binary up down counters general purpose counters 0 and 1 Figure 4 1 shows a simplified model of the counter G UP DOWN Load Registers 24 Bit Up Down Counter G SOURCE G OUT G GATE Save Registers INTERRUPT Figure 4 1 General Purpose Counter Timer Simplified Model DAQ STC Technical Refer
351. e Value GO Save Value GO Save Value GO Save Value GO Save Value GO Save Value GO Save Value GO Save Value GO Save Value GO Save Value GO Save Value GO Save Value DAQ STC Technical Reference Manual Appendix B Register Information 1 Autoincrement Register Address 69 Type Write only 15 Reserved 14 Reserved 13 Reserved Reserved N Reserved Reserved Reserved Reserved Autoincrement Autoincrement Autoincrement Autoincrement Autoincrement Autoincrement Autoincrement _ OO CO RK G1_Autoincrement G1_HW_Save_Registers Address 10 Type Read only 15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 Reserved 10 Reserved 9 Reserved 8 Reserved 7 GW Save Value 6 GW Save Value 5 GW Save Value 4 GW Save Value 3 Save Value 2 GI GW Save Value 1 GW Save Value 0 GW Save Value DAQ STC Technical Reference Manual B 30 Address 7 ee _ 95 gt 5 tA Address 11 _ NW 4 tA G1 Command Register Type Write only GO Disarm Copy GO Save Trace Copy GO Arm Copy Bank Switch Enable Bank Switch Mode Bank Switch Start GI Little Big Endian Synchronized Gate Write Switch Up Down Up Down
352. e acquisition level timing modes posttrigger mode pretrigger mode and continuous acquisition mode This section discusses the operation of the 5 and START triggers in the context of these three timing modes 2 4 3 1 Posttrigger Acquisition Mode In the posttrigger acquisition mode only one parameter is required the number of scans to complete The STARTI pulse initiates the scan sequence The SC counter counts the number of scans and terminates the acquisition upon completion of the programmed number of scans Posttrigger acquisitions can be retriggerable or nonretriggerable In the retriggerable mode additional START pulses that occur after SC initiate additional acquisition sequences In the nonretriggerable mode only one acquisition sequence is allowed Externally generated STARTI and START triggers enter the DAQ STC through one of PFI lt 0 9 gt or RTSI TRIGGER O 6 Figure 2 11 shows a single posttrigger acquisition sequence consisting of three scans START1 START STOP d ES CONVERT SC Counter 2 1 0 B T6 Figure 2 11 Posttrigger Acquisition Mode 2 4 3 2 Pretrigger Acquisition Mode In the pretrigger acquisition mode two parameters are required The first parameter gives the pretrigger count requirement that is the number of scans
353. e additional analog output operations In the nonretriggerable single buffer mode only one analog output operation is allowed and the final UPDATE pulse in the MISB is masked Therefore you need to add an extra UPDATE pulse to the first buffer in the nonretriggerable single buffer mode Figure 3 11 shows an example of the nonretriggerable single buffer mode The buffer contains five data points so the UC counter is programmed to count six UPDATE pulses in the following buffers The buffer is repeated twice so the BC counter is programmed to count two UC TC pulses The BC TC BC counter TC signal causes the MISB to terminate and masks the final UPDATE pulse Iteration 1 Iteration 2 STARTI i UPDATE LILI LN EE Figure 3 11 Single Buffer Mode 3 4 5 2 Continuous Mode In the single buffer mode the BC counter indicates when an MISB should terminate In the continuous mode however the MISB does not terminate at a predetermined time Instead the MISB continues until the hardware receives an End TC command End On BC TC command or an AO Reset The End On UC TC command causes the MISB to terminate at the next UC corresponding to the end of the current buffer The End On BC TC command causes the MISB to terminate at the next TC The AO Reset causes the MISB to terminate immediately National Instruments Corporation 3 13
354. e analog input module They can also be either edge sensitive or level sensitive When an external UPDATE source is being used the state clock will be generated by a combination of the UPDATE SRC and a delayed version of UPDATE SRC The four modes of behavior for the STARTI signal and UPDATE SRC are shown in Figures 3 23 through 3 28 The four modes are called asynchronous level sensitive asynchronous edge sensitive synchronous level sensitive and synchronous edge sensitive UPDATE SRC N Ts_strt1 lt Th lt q START1 Figure 3 23 External Trigger Asynchronous Level Ts strtl START1 N UPDATE SRC N Figure 3 24 External Trigger Asynchronous Edge DAQ STC Technical Reference Manual 3 102 National Instruments Corporation Chapter 3 Analog Output Timing Control Ts_strt1 4 ae UI Source START1 Figure 3 25 External Trigger Synchronous Level Internal UPDATE Mode UI Source N A START1 Figure 3 26 External Trigger Synchronous Edge Internal UPDATE Mode P Th strt1 lt q UPDATE_SRC START1 Figure 3 27 External Trigger Synchronous Level External UPDATE Mode Ts strt START1 N UPDATE N Figure 3 28 External Trigger Synchronous Edge External UPDATE Mode National Instruments Corporation 3 103 DAQ STC Technical Reference M
355. e and immediate update mode Select the timed update mode if you want the outputs of all of the DACs to update simultaneously Select the immediate update mode if you want the output of each DAC to update immediately after data is written In the timed update mode LDAC lt 0 1 gt follow the UPDATE signal for primary analog output or the UPDATE2 signal for secondary analog output In the immediate update mode LDAC lt 0 1 gt are inverted versions of the DAC write signals TMRDACWR and CPUDACWR Data Interfaces The DAQ STC supports several methods for transferring analog output data from computer memory to the DACs In CPU driven analog output the CPU writes the output data directly to the DACs In DAQ STC driven analog output however CPU writes are usually too inefficient to achieve high data throughput For this reason the DAQ STC supports three other modes for transferring data to the DACs In the FIFO data interface mode output data is buffered locally in the data FIFO When the data FIFO empties it can be filled using DMA or interrupts or through the FIFO retransmit in local buffer mode In the serial link data interface mode the output data comes through a serial link from another board In the unbuffered data interface mode the output data is written directly to the DACs using DMA This section discusses the three methods for transferring data to the DACs 3 4 3 1 FIFO Data Interface In the FIFO data interface mode the analog outpu
356. e external CONVERT so that CONVERT passes through only when the SC counter is enabled to count It is set by the assertion of START1 when SC ARM is true and is cleared when the SC counter returns to the WAIT state Related bitfields AI SC Gate Enable AI SC Gate St SC HOLD SC Hold This signal controls the SC save register If SC HOLD 0 then the SC save register tracks the SC counter output If SC HOLD 1 then the SC save register latches the SC counter output on the next SC CLK SCKG Sample Clock Gate In the internal CONVERT mode SCKG is 50 TC In the external CONVERT mode SCKG is 1 SCLK Sample Clock In the internal CONVERT mode SCLK is the signal 50 TC In the external CONVERT mode SCLK is the signal FSCLK after it passes through a delay gate The delay gate is provided so that signals synchronized to FSCLK have sufficient time to settle to known state before being used by SCLK National Instruments Corporation 2 115 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Table 2 9 Internal Signals Continued Signal Description SCLKG Internal Sample Clock SCLKG is the signal that appears on the CONVERT and PFI2 CONV pins The hardware generates SCLKG by passing the SCLK signal through pulsewidth and polarity selection circuitry If the CONVERT pin is configured for high impedance this signal will be ground Related bitfields AI CONVERT Output Select AI
357. e from AO IN TIMEBASEI IN TIMEBASE2 the signal from general purpose counter 0 or 1 PFI lt 0 9 gt and RTSI lt 0 6 gt Related bitfields UD Source Select UD TC Secondary Update Interval TC The UI2 TC signal is the independent secondary update interval clock 3 8 2 Trigger Selection and Conditioning The signal routing block selects the counter clocks trigger signals and gate signals from the default timebases The routing logic for the UI SRC UI2_SRC and BC SRC signals is a 20 to 1 multiplexer followed by an exclusive OR gate for polarity selection The routing logic for the trigger signal STARTI has additional controls for edge detection and synchronization as shown in Figure 3 35 When synchronization is selected STARTI is synchronized to both UI SRC and SRC DAQ STC Technical Reference Manual 3 114 National Instruments Corporation Chapter 3 Analog Output Timing Control OUT TO SLAVE SYNC 2STAGE Q zi D lt 0 9 gt 20 to 1 em EDGE E B R RTSI_TRIGGER lt 0 6 gt MUX POLARITY SEL lt 0 4 gt INT CLK 2STAGE EXT EXT TIMING NOTE Does not show all possible selections D Q INT gt R DELAY_EXT_CLK EXT_TIMING DELAY
358. e front of the board Product Name PWB Number AT MIO 16E 1 183020B 01 AT MIO 16E 2 182412D 01 AT MIO 64E 10 182642B 01 AT MIO 16DE 10 182637C 01 AT MIO 16XE 50 182542C 01 PCI MIO 16XE 50 183118C 01 DAQPad MIO 16XE 50 182951A 01 National Instruments Corporation D 1 DAQ STC Technical Reference Manual Appendix D DAQ STC Revision History Product Name PWB Number NEC MIO 16E 4 182397C 01 NEC AI 16E 4 182397C 01 NEC MIO 16XE 50 182832 01 NEC AI 16XE 50 182832A 01 SB MIO 16E 4 182467C 01 VXI MIO 64E 1 183006C 01 VXI MIO 64XE 10 183392B 01 DAQ STC Technical Reference Manual D 2 National Instruments Corporation Customer Communication For your convenience this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation When you contact us we need the information on the Technical Support Form and the configuration form if your manual contains one about your system configuration to answer your questions as quickly as possible National Instruments has technical assistance through electronic fax and telephone systems to quickly provide the information you need Our electronic services include a bulletin board service an FTP site a fax on demand system and e mail support If you have a hardware or software problem first try the electro
359. e generation of a single pulse with a pulse delay of four and a pulsewidth of three G GATE G SOURCE 1 Counter Value 3 5 2 1 0 2 1 0 Counter TC G OUT p Figure 4 13 Single Triggered Pulse Generation DAQ STC Technical Reference Manual 4 10 National Instruments Corporation Chapter 4 General Purpose Counter Timer 4 4 3 3 Retriggerable Single Pulse Generation This function is similar to single triggered pulse generation except that the counter generates a pulse on every active G_GATE edge following the software arm instead of only on the first occurrence After the counter arm every active G_GATE edge causes the counter to generate a single pulse with programmable delay and programmable pulsewidth You should specify the programmable parameters in terms of periods of the G SOURCE input Retriggerable single pulse generation is implemented in software by loading the delay value into the counter loading the pulsewidth value into the primary load register programming the counter output OUT to change states on counter TC and configuring the counter to trigger on every G GATE Figure 4 14 shows the generation of two pulses with a pulse delay of five and a pulsewidth of three G GATE H G SOURCE
360. e in AO Mode 2 Register address 39 If the UI counter is disarmed this bit selects the initial UI load register 0 Load register 1 Load register B If the UI counter is armed writing to this bit has no effect Related bitfields AO UI Arm UI Load bit 9 type Strobe in AO Command 1 Register address 9 If the UI counter is disarmed this bit loads the UI counter with the contents of the selected UI load register A or B If the UI counter is armed writing to this bit has no effect This bit is cleared automatically UI Load bits lt 0 7 gt type Write in AO UI Load A Registers address 40 bits lt 0 15 gt type Write in AO UI Load A Registers address 41 This bitfield is load register A for the UI counter If load register A is the selected UI load register the UI counter loads the value contained in this bitfield on AO Load and on UI TC The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related bitfields AO UI Next Load Source St AO UI Load DAQ STC Technical Reference Manual 3 72 National Instruments Corporation Chapter 3 Analog Output Timing Control Load B bits lt 0 7 gt type Write in AO UI Load Registers address 42 bits lt 0 15 gt type Write in AO UI Load Registers address 43 This bitfield is load register B for the UI counter If load register B is the selected UI load register the UI counter loads th
361. e low or falling edge Else AI START Select 1 through 10 PFI lt 0 9 gt or 11 through 17 lt 0 6 gt or 18 bitfield AI START Pulse or 19 the OUT signal from general purpose counter 0 AI START 5 1 AI START 1 AI START Polarity 0 active high or rising edge or active low or falling edge If SI Special Trigger Delay is used then AI SI Special Trigger Delay 1 AI SI Write Switch 0 If an internal timebase 1s used then AI SI Source Select 0 AI_LIN_TIMEBASE1 or 19 IN TIMEBASE2 AI SI Source Polarity 0 DAQ STC Technical Reference Manual 2 36 National Instruments Corporation Chapter 2 Analog Input Timing Control Else AI_SI_Source_Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI lt 0 6 gt AI SI Source Polarity 0 rising edge or 1 falling edge AI SI Load A minimum number of clocks from START to first START 1 AI SI Initial Load Source 0 AI SI Load 1 Else AI SI Special Trigger Delay 0 If staged acquisition then AI SI Load si_ticks 0 1 AI SI Reload Mode 0 AI SI Switch Load On SC 1 si last load register B Else si_last_load_register A E AI Configuration End 1 End critical section 2 6 3 11 End of Scan Use this function to select the end of scan event On a typical MIO board the end of sc
362. e physical damage to the DAQ STC the external circuitry or both 1 6 2 1 Parallel Digital 1 0 Use the following function to program the value to be output on the DIO pins configured for output Function DIO Parallel Out DIO Parallel Data ijklmnop where i j J m n o and p are all binary digits so that ijklmnop is an eight digit binary number Logic values corresponding to i j k L n o and p will appear on the DIO pins configured for output Note that i corresponds to pin DIO7 j to pin DIO6 and so on If you wish to change values on some pins and preserve values on others you have to maintain a software copy of the value you write to DIO Parallel Data Out Use the following function to read the value from the DIO pins Function DIO Parallel In Here i j k l m n o and p are all binary digits corresponding to logic values on the DIO pins 7 through 0 so that ijkImnop is an eight digit binary number Values corresponding to pins configured for input will reflect the state of the external digital signal connected to the pin Values corresponding to the pins configured for output will reflect the values being output on those pins ijklmnop DIO Parallel Data St National Instruments Corporation 7 9 DAQ STC Technical Reference Manual Chapter 7 Digital 1 0 1 6 2 2 Hardware Controlled Serial Digital 1 0 DIO line 4 can be used for serial input and DIO line 0 for se
363. e sensitive mode has only a pulsewidth requirement but in order to guarantee recognition by a specific clock edge it must also meet the setup time to the latching state clock edge The four modes resulting from the combination of the above options are shown in Figures 2 21 through 2 26 The four modes are asynchronous level sensitive asynchronous edge sensitive synchronous level sensitive and synchronous edge sensitive In synchronous mode the synchronizing edge depends on whether you select internal CONVERT or external CONVERT In the internal CONVERT mode the external signal synchronizes to the inactive edge of the SI2 source In the external CONVERT mode the external signal synchronizes to the active edge of CONVERT_SRC National Instruments Corporation 2 93 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Ts strt1 Ts strt2 Ts strt Ts stop Th strt2 Th strt Th stop CONVERT SRC START1 N START2 N START STOP ef Figure 2 21 External Trigger Timing Asynchronous Level 475 11 475 2 gt 475 E 475 stop CONVERT SRC N J NN l1f N START1 START2 N gt he 5 gt Tstop STOP N Figure 2 22 External Trigger Timing Asynchronous Edge DAQ STC Technical Reference Manual 2 94 National Instruments Corporation Chapter 2 Analog Input Tim
364. e to the ADC The DAQ STC instructs the ADC to begin the conversion and monitors the progress through status flags When the conversion is complete the DAQ STC clocks the digital data into the AI data FIFO until it can be retrieved by the system bus The DAQ STC monitors the status of the AI data FIFO so that the DAQ STC can generate an interrupt or a DMA request when the FIFO fills beyond a programmable threshold On many boards a configuration FIFO is available to provide gain control and channel selection The DAQ STC supplies a clock and a retransmit signal for the configuration FIFO and monitors the FIFO empty flag The ghost signal from the configuration FIFO inhibits the AI data FIFO clock to provide a multirate sampling capability Timing and trigger signals pass to and from the DAQ STC and the I O and RTSI connectors for external timing applications 1 1 2 Analog Output Application Figure 1 2 shows the primary components of an analog output subsystem On an analog output board the CPU typically writes the output data into the AO data FIFO and one or more D A converters DACs subsequently convert the digital data to an analog form Output Data Analog Channels Ao Data i DACs FIFO DAC Write lt iB DAC Address E Status E v 8 Retransmit Update CPU Request DAQ STC Channel Ready Analog Output Timing C
365. e value contained in this bitfield on AO Load and on UI TC The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related bitfields UI Next Load Source St AO UI Load UI Next Load Source St bit 6 type Read in AO Status 2 Register address 6 This bit indicates the next load source of the UI counter 0 Load register A 1 Load register B A0 UI Q St bit 9 type Read in AO Status 2 Register address 6 This field reflects the state of the UI control circuit 0 WAIT 1 CNT See section 3 8 Detailed Description for more information on the UI control circuit 0 UI Reload Mode bits lt 4 6 gt type Write in AO Mode 2 Register address 39 This bitfield selects the reload mode for the UI counter 0 No automatic change of the UI load register 4 Alternate first period on STOP Use this setting to make the time interval between the START trigger and the first UPDATE pulse different from the remaining update intervals 5 Switch load register on STOP Use this setting to synchronously change the update interval at each STOP 6 Alternate first period on TC Use this setting to make the time interval between the STARTI trigger and the first UPDATE pulse different from the remaining update intervals 7 Switch load register on TC Use this setting to synchronously change the update interval at each TC This is convenient for staged analog output
366. e_l first read save 2 second read Gi Save Trace 0 Y Save 1 Read two times save 1 Gi Save Registers save 2 Gi Save Registers the two values read are not equal read once more If save 1 does not equal save 2 then Inform user of the counter contents contained in save_1 save 1 Gi Save Registers 4 6 1 14 Reading the Hardware Save Registers In pulse width and period measurement applications you need to read the value in the hardware save registers The Gate Interrupt St bit will be set whenever a value is saved in the HW Save Registers This status bit indicates when it is time to read the hardware save registers DAQ STC Technical Reference Manual 4 34 National Instruments Corporation 4 6 2 Chapter 4 General Purpose Counter Timer Function Read Gi Save Registers Declare variables save 0 Read from the AI_Status_1_Register to check the GO_Gate_Interrupt_St or read from the AO_Status_1_Register to check the G1_Gate_Interrupt_St If the status bit is set read the hardware save registers 24 bit value if Gi_Gate_Interrupt_St save Gi_HW_Save_Registers 4 6 1 15 Enabling the General Purpose Counter Timer Output Pin The output pin for each general purpose counter timer must be enabled before it can be used This is required for applications such as single or contiuous pulse generation Function Enable_Gi_Out GPF
367. eached the counter reloads and counts down to TC again The load select signal indicates whether the reload occurs from load register A or B After every second counter TC the interrupt service routine programs the counter to switch load register banks The bank select signal then changes on the falling edge of the next counter TC Figure 4 46 shows an example of a buffered pulse train generation The first pulse has a delay from trigger of two a pulsewidth of five and a pulse interval of four The second pulse has a pulsewidth of three and a pulse interval of two The interrupt software programs the counter to switch load register banks at the second and fourth TC interrupts The dotted line indicates where the ARM occurs and the arrows indicate where the TC interrupt is generated G SOURCE GATE G CONTROL Bank Select Load Select fi 1 Xa X2 2 1 F1 Counter Load Counter Value Counter TC G_OUT Figure 4 46 Buffered Pulse Train Generation National Instruments Corporation 4 85 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 8 11 16 Frequency Shift Keying To use this function set G C
368. ed Enabled When the SC gate is enabled external CONVERT signals pass through the DAQ STC only when the SC counter is counting or if in pretriggered mode waiting for trigger You must disable the SC gate when internally generated CONVERT pulses are used SC Gate St bit 4 type Read in Joint Status 1 Register address 27 This bit indicates the status of the SC gate if the SC gate is enabled 0 SC gate blocks external CONVERTs 1 SC gate allows external CONVERTS to pass Related bitfields SC Gate Enable DAQ STC Technical Reference Manual 2 62 National Instruments Corporation Chapter 2 Analog Input Timing Control AI SC Initial Load Source bit 2 type Write in AI Mode 2 Register address 13 If the SC counter is disarmed this bit selects the initial SC load register 0 Load register A 1 Load register B If the SC counter is armed this bit has no effect Related bitfields AI SC Arm SC Load bit 5 type Strobe AI Command 1 Register address 8 If the SC counter is disarmed this bit loads the SC counter with the contents of the selected SC load register or B If the SC counter is armed writing to this bit has no effect This bit is cleared automatically Related bitfields SC Initial Load Source SC Load bits lt 0 7 gt type Write in AI SC Load A Registers address 18 bits lt 0 15 gt type Write in AI SC Load A Registers address 19 This bitfield is
369. ed analog input model 2 4 2 6 staged acquisition 2 16 trigger operation 2 122 trigger output 2 97 to 2 100 asynchronous mode 2 99 to 2 100 synchronous mode 2 97 to 2 99 trigger routing logic figure 2 120 START signal analog output timing control module continuous mode 3 14 DAQ STC Technical Reference Manual 1 36 description table 3 112 external trigger timing 3 102 to 3 104 external UPDATE timing 3 12 internal UPDATE timing 3 11 to 3 12 routing logic figure 3 115 simplified analog output model 3 5 single buffer mode 3 13 trigger output asynchronous mode 3 106 to 3 107 synchronous mode 3 104 to 3 106 START signal description table 2 118 external trigger timing 2 94 to 2 96 interval scanning mode 2 106 to 2 108 master slave trigger 2 16 posttrigger acquisition mode 2 14 pretrigger acquisition mode 2 14 to 2 15 trigger operation 2 122 trigger output 2 07 to 2 100 asynchronous mode 2 99 to 2 100 synchronous mode 2 97 to 2 99 trigger routing logic figure 2 120 status lines reading 7 13 STATUS lt 0 3 gt signal table 7 6 stop on error primary analog output programming 3 29 STOP signal analog input timing control module table 2 119 analog output timing control module table 3 112 external CONVERT mode 2 10 to 2 11 external trigger timing 2 94 to 2 97 internal CONVERT mode 2 9 to 2 10 interval scanning mode 2 106 2 108 simplified analog input model 2 4 to 2 6 trigger
370. ed bitfields AI SC TC Interrupt Ack Refer to Table 8 2 Interrupt Condition Summary for more information AI SC Write Switch bit 0 type Write in AI Mode 2 Register address 13 This bit enables the write switch feature of the SC load registers Writes to SC load register A are 0 Unconditionally directed to SC load register A 1 Directed to the inactive SC load register DAQ STC Technical Reference Manual 2 66 National Instruments Corporation Chapter 2 Analog Input Timing Control SHIFTIN Polarity bit 12 type Write in AI Personal Register address 77 This bit selects the polarity of the AI FIFO SHIFTIN output signal 0 Active low 1 Active high SHIFTIN Pulse Width bit 15 type Write in AI Personal Register address 77 This bit determines the pulsewidth of the SHIFTIN and AI FIFO SHIFTIN output signals 0 0 5 1 5 AI OUT TIMEBASE periods 1 1 5 2 OUT TIMEBASE periods The leading edge of the SHIFTIN and AI SHIFTIN pulses occurs immediately after the active edge of EOC AI SI Arm bit 10 type Strobe AI Command 1 Register address 8 Setting this bit to 1 arms the SI counter The counter remains armed and the bit remains set until it is disarmed either by hardware or by setting Disarm to 1 Related bitfields AI SI Armed St AI Disarm SI Armed St bit 5 type Read in AI Status 2 Register address 5 This bit indicates whether the SI counter is armed
371. ed process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment Contents About This Manual Organization of This Manual xxiii Conventions Used in This ener nne XXV National Instruments xxvi Related Documentation reo tere trier meto nete ERE PEE Ee Ee eR E EA eves xxvi Customer Communication 1 eese enne ener enne ener ense tenen xxvii Chapter 1 Introduction 1 1 DAQ STC Applications ete ree ete eee reete epe 1 2 1 1 1 Analog Input Application esses eene enne 1 2 1 1 2 Analog Output 1 3 1 2 DAQ STC Block 1 4 Chapter 2 Analog Input Timing Control 2 1 OVELVIEW 2 1 2 14 Programming the 2 1 2 2 Beat teS 2 2 2 3 Sunphfied eee tege eie 2 4 2 44 Analog Input Functions et eere tee e ett erii 2 6 2 4 1 Low Level Timing and 2 6 2 4 1 1 ADC Control sii d onde eei 2 7 2 4 1 2 Data FIFO
372. eet reete 2 121 Table 2 11 Analog Input Interrupts esee nennen 2 131 Table 2 12 Analog Input Nominal Signal 2 133 Table 3 1 Pin Interface eene ete 3 16 Table 3 2 UPDATE SRC Reference Pin Selection eee 3 85 Table 3 3 UI2_SRC Reference Pin Selection 3 00088 3 85 Table 3 4 DAQ STC Driven Analog Output 3 87 Table 3 5 External Trigger Timing eene 3 104 Table 3 6 Internal Signals 14 3 109 Table 3 7 8 ne SR a eee 3 115 Table 3 8 Analog Output Interrupts 3 122 Table 3 9 Analog Output Nominal Signal Widths 3 124 National Instruments Corporation Xix DAQ STC Technical Reference Manual Contents Table 4 1 CTRSRC Reference Pin 4 53 Table 4 2 CTRGATE Reference Pin Selection essen 4 54 Table 4 3 U D Reference Pin 4 54 Table 4 4 Internal Signal Description 2 4 62 Table 4 5 G SOURCGE Selection ici TE IRR 4 63 Table 4 6 SOURCE Conditioning eese eene 4 63 Table 4 7 G GATE ME de 4 64 Table 4 8 G GATE Conditioning 4 64 Table 4 9 G UP DOWN MlOdes wis ccd ait eroe e ree E 4 6
373. eference Manual PARALLEL READ gt EXTSTROBE SDCLK Chapter 7 Digital 1 0 SERIAL READ SHIFT IN lt gt gt M DIO4 SDIN SERIAL WRITE SHIFT OUT S lt q j PI DIO0 SDOUT 4 010 lt 1 3 gt DIO 5 7 PARALLEL WRITE gt CTRL lt 0 7 gt f4 STATUS O0 3 Figure 7 1 DIO Simplified Model The bidirectional DIO lt 0 7 gt lines provide a port for 8 bit parallel I O When parallel I O is not needed the DIO4 SDIN and DIOO SDOUT lines provide a port for 8 bit serial I O The signal EXTSTROBE SDCLK can generate periodic timing for serial I O or it can act as a software controlled handshaking signal for both parallel and serial I O The STATUS lt 0 3 gt and CTRL O 7 lines provide a board level read and write register 1 4 Overview of DIO Functions 1 4 1 The DIO module provides two modes of digital I O operation parallel mode and serial mode In parallel mode the DAQ STC transfers data eight bits at a time under software control In serial mode the DAQ STC transfers data one bit at a time under hardware control with software initiating each 8 bit serial transfer This section discusses the parallel and serial modes of operation Parallel Mode In parallel I O mode eight bits are available for interfacing with a parallel port The software outputs data asynchro
374. eference Manual 4 46 National Instruments Corporation Chapter 4 General Purpose Counter Timer Gi Save St i 0 bit 0 type Read in G_Status_Register address 4 i 1 bit 1 type Read in G_Status_Register address 4 This bit indicates the status of the general purpose counter i save register 0 Save register is tracing the counter 1 Save register is latched for later read Related bitfields Gi_Save_Trace Gi_Save_Trace i 0 bit 1 type Write in GO_Command_Register address 6 bit 1 type Write Command Register address 7 Setting this bit or Save Trace Copy to 1 places the general purpose counter i save register in the latched data state Setting both this bit and Save Trace Copy to 0 makes the save register trace the counter To latch the counter contents in the save register you must make the save register trace the counter before issuing the save command Gj Save Trace i 0 bit 14 type Write Command Register address 7 bit 14 type Write in GO Command Register address 6 Setting this bit or Gi Save Trace to 1 places the general purpose counter i save register in the latched data state Setting both this bit and Save Trace to 0 makes the save register trace the counter To latch the counter contents in the save register you must make the save register trace the counter before issuing the save command Gj Save Value i 0 bits lt 0 7 gt type Read in GO Save
375. egisters or as clear strobes for the various FIFOs Related bitfields Control DIOO SDOUT B18TU Digital I O0 Serial Data Output This bidirectional pin is one of the eight individually programmable DIO lines This pin is also the serial port data output pin The serial port implements communication with the SCXI at one of two selectable clock rates See also EXTSTROBE SDCLK Related bitfields DIO Pins Dir DIO Parallel Data In St DIO Parallel Data Out DIO Serial Data Out DIO lt 1 3 gt 18 Digital I O Lines lt 1 3 gt Individually programmable DIO lines Related bitfields DIO_Pins_Dir DIO_Parallel_Data_In_St DIO_Parallel_Data_Out DIO4 SDIN B18TU Digital I O4 Serial Data Input This bidirectional pin is one of the eight individually programmable DIO lines This pin is also the serial port data input pin The serial port implements communication with the SCXI at one of two selectable clock rates See also EXTSTROBE SDCLK Related bitfields DIO Pins Dir DIO Parallel Date In St DIO Parallel Data DIO Serial Data In St DIO lt 5 7 gt 18 Digital I O Lines lt 5 7 gt Individually programmable DIO lines Related bitfields DIO_Pins_Dir DIO_Parallel_Data_In_St DIO_Parallel_Data_Out DAQ STC Technical Reference Manual 7 6 National Instruments Corporation Chapter 7 Digital 1 0 Table 7 1 Pin Interface Continued Pin Name Type
376. elect 2 70 AI SI Special Trigger Delay 2 70 AI SI Switch Load On SC TC 2 70 AI SI Switch Load On Stop 2 70 AI SI Switch Load On TC 2 70 AI SI Write Switch 2 71 AI SI2 Arm 2 71 AI SI2 Armed St 2 71 AI SI2 Initial Load Source 2 71 AI 512 Load 2 71 AI SI2 Load A 2 71 DAQ STC Technical Reference Manual Index AI SI2 Load 2 72 AI SI2 Next Load Source St 2 72 AI SI2 Q St 2 72 AI SI2 Reload Mode 2 72 AI SI2 Save Value 2 72 AI SI2 Source Select 2 73 AI SOC Polarity 2 73 AI SOC 2 73 AI Software Gate 2 73 AI Source Divide By 2 2 73 AI START Edge 2 74 AI START Interrupt 2 74 AI START Interrupt Enable 2 74 AI START Output Select 2 74 AI START Polarity 2 74 AI START Pulse 2 75 AI START Second Enable 2 75 AI START Select 2 75 AI START St 2 75 AI Start Stop 2 76 AI Start Stop Gate Enable 2 76 AI Start Stop Gate St 2 76 AI START Sync 2 76 AI STARTI Disable 2 76 AI STARTI Edge 2 77 AI STARTI Interrupt 2 77 AI STARTI Interrupt Enable 2 77 AI STARTI Polarity 2 77 AI STARTI Pulse 2 77 AI STARTI Second Enable 2 78 AI STARTI Select 2 78 AI STARTI St 2 78 AI STARTI Sync 2 78 AI START2 Edge 2 79 AI START2 Interrupt 2 79 AI START2 Interrupt Enable 2 79 AI START2 Interrupt Polarity 2 79 AI START2 Interrupt Pulse 2 79 DAQ STC Techni
377. elect is set to 18 This bit is cleared automatically Related bitfields AI START Select START Second Enable bit 3 type Write in Second Enable Register address 74 This bit enables the START interrupt in the secondary interrupt bank 0 Disabled 1 Enabled The START interrupt is generated on valid START triggers received by the DAQ STC A valid START trigger is one that is received while the SC counter is enabled to count START Select bits lt 0 4 gt type Write in AI START STOP Select Register address 62 This bit selects the START trigger 0 The internal signal SI TC 1 10 PFI lt 0 9 gt 11 17 RTSI lt 0 6 gt 18 Bitfield AI START Pulse 19 The internal signal OUT from general purpose counter 0 31 Logic low When you set this bit to 0 the DAQ STC is in the internal START mode When you select any other signal as the START trigger the DAQ STC is in the external START mode Related bitfields AI START Pulse AI START St bit 5 type Read in AI Status 1 Register address 2 This bit indicates that a valid START trigger has been received by the AITM 0 No 1 Yes A valid START trigger is one that is received while the SC counter is enabled to count You can clear this bit by setting AI START Interrupt to 1 Refer to Table 8 2 Interrupt Condition Summary for more information National Instruments Corporation 2 75 DAQ STC Technical Reference
378. elect the polarity of signal which will be used as an external interrupt Function 5 Pass Through Polarity Pass Thru 0 Interrupt Polarity 0 active high or 1 active low Pass Thru 1 Interrupt Polarity 0 active high or 1 active low Use the following function to enable the use of an external interrupt condition on pins IRQ_IN lt 0 1 gt Function MSC_Pass_Through_Interrupt switch pass through interrupt case 0 Pass Thru 0 Interrupt Enable 0 disabled or 1 enabled break case 1 Pass Thru 1 Interrupt Enable 0 disabled or 1 enabled break DAQ STC Technical Reference Manual 8 4 National Instruments Corporation Chapter 8 Interrupt Control Use the following function to enable the use of an external secondary interrupt condition on pins lt 0 1 gt Function 5 Pass Through Second Irq switch pass through secondary interrupt case 0 Pass_Thru_0_Second_Irq_Enable 0 disabled or 1 enabled break case Pass Thru 1 Second Irq Enable 0 disabled or 1 enabled break CF Note You should set Pass Through i Interrupt Enable to 1 after selecting the interrupt polarity 8 4 2 Interrupt Handling Up to 18 events occurring within the DAQ STC and up to two events occurring outside the DAQ STC can cause the DAQ STC to assert an interrupt This section presents a programming sequence you can use to determine which of the many conditions caused
379. ellaneous Functions The RESET pin is a special case because it connects directly to the OR structure To test the RESET pin follow these steps 1 Bring TEST IN high This setting tri states all of the output pins except TEST OUT 2 Bring the RESET pin and all of the pins listed in Table 10 2 low TEST OUT will be high 3 Toggle the RESET pin and observe the change on TEST OUT Pins are tested in pairs in the in circuit test mode Table 10 2 lists the pin pairs for in circuit testing Table 10 2 Test Mode Input Pin Pairs Pin Pairs Pin Pairs INTEL MOTO CS TRIGGER4 RTSI TRIGGER5 RD WR WR DS RTSI TRIGGER6 GHOST 1 2 RTSI BRDO RTSI BRDI A3 4 RTSI BRD2 RTSI BRD3 A5 A6 EOC SOC 7 RTSI OSC IRQ INO IRQ INI DO DI AIFFF AIFEF D2 D3 AIFHF MUXFEF D4 D5 AI STOP IN TRIG IN LO D6 D7 ANALOG IN TRIG HI AOFFF D8 D9 AOFHF AOFEF D10 D11 CPUDACREQ CHRDY_IN D12 D13 DIO0 SDOUT DIOI 014 015 DIO2 DIO3 PFIO AI STARTI START2 DIO4 SDIN DIOS PFI2 CONV PFI3 G SRCI DIO6 DIO7 PFI4 G_GATE1 PFIS UPDATE STATUSO STATUSI PFI6 AO START PFI7 AI START STATUS2 STATUS3 1 DAQ STC Technical Reference Manual 10 8 National Instruments Corporation Chapter 10 Table 10 2 Test Mode Input Pin Pairs Continued Pin Pairs Pin Pairs PFI8 G SRCO PFI9 G GATEO G UP DOWNO G UP DOWNI RTSI TRIGGERO RTSI TRIGGERI RTSI TRIGG
380. ement and generate the START signal which begins the next scan The timing for the halt gating mode with an external CONVERT or with SI2 source and SI source as different signals is more complicated and is therefore omitted National Instruments Corporation 2 111 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 2 8 Detailed Description This section describes the AITM module in detail You need not read this section unless you need to understand the inner workings of the circuit This section refers to bitfields in the AITM related registers in the DAQ STC register map Refer to Appendix B Register Information for more information on the register addresses containing these bitfields Figure 2 46 shows a block diagram of the AITM module The AITM contains four special purpose counters SI SI2 SC and DIV Each of the counters except DIV has dual load registers A and B which allow the counters to handle two parameters for each timing layer as discussed in section 2 4 Analog Input Functions Apart from the counters the primary logic blocks are the counter control blocks the routing logic block the interrupt control block and the output control block SC Load A SC Load B START
381. ence Manual 4 2 National Instruments Corporation Chapter 4 General Purpose Counter Timer Each GPCT counter has a source input SOURCE a gate input GATE and an up down control input G UP DOWN When the counter is enabled to count rising edges on SOURCE input cause the counter to increment or decrement input acts as a general purpose control signal and can operate as a counter trigger signal a counter enable a save signal a reload signal an interrupt an output control signal a load register select signal and a counter disarm The G UP DOWN input determines whether the counter counts up or down The counter outputs are the signals labeled OUT and INTERRUPT OUT is a counter TC related signal which can toggle on every counter TC or can output the counter TC signal directly INTERRUPT is an interrupt signal routed inside the DAQ STC to the interrupt control module Refer to Chapter 8 Interrupt Control for more information The counter has load registers to reload the counter with new count values The save registers save the counter contents until they can be read by software 4 4 Counter Timer Functions The purpose of the GPCT is to provide counter timer functions that are improved over those available on the Am9513 based DAQ boards through NI DAQ the National Instruments software for data acquisition Examples of existing counter timer functions supported by the DAQ STC are event coun
382. end of the current MISB This bit is cleared automatically UI Switch Load On Stop bit 8 type Strobe in AO Command 2 Register address 5 Setting this bit to 1 causes the UI counter to switch load registers upon receiving a STOP trigger This action is internally synchronized to the falling edge of the This bit is cleared automatically This bitfield is currently not supported and it must be set to 0 DAQ STC Technical Reference Manual 3 74 National Instruments Corporation Chapter 3 Analog Output Timing Control AO UI Switch Load TC bit 7 type Strobe AO Command 2 Register address 5 Setting this bit to 1 causes the UI counter to switch the load registers at the next UI TC This action is internally synchronized to the falling edge of the UI CLK You can use this bit to change the update rate during waveform generation at the end of the current buffer This bit is cleared automatically AO UI Write Switch bit 3 type Write in AO Mode 2 Register address 39 This bit enables the write switch feature of the UI load registers Writes to UI load register A are 0 Unconditionally directed to the UI load register A 1 Directed to the inactive UI load register 0 2 Arm Disarm bit 12 type Write in AO Command 1 Register address 9 Setting this bit to 1 arms the UI2 counter Setting this bit to 0 disarms the UI2 counter 0 UI2 Armed St bit 11 type Read in AO Status 2 Register address
383. ending on the signals STOP AO End On BC TC AO End UC BC and AO Continuous For continuous acquisition modes the UC counter control circuit can return to the WAIT state based on the software strobes AO End On BC TC and AO End On UC Also the UC counter normally remains armed and retriggerable at the end of a scan sequence The UC counter has the option AO Trigger Once to disarm itself when returning to the WAIT state AB A DA START1 E E B AO UC Arm d i E UC TC G BC TC H AO End On BC TC EC I AO End On UC TC AD UN J AO Continuous K SCKG CNT STOP Trigger Once T UC LOAD AO UC Load UC CE BK EXT GATE INT SCLK SEL CNT n CNT n 1 DISARM H I CNT n WAIT n 1 Figure 3 38 UC Control Circuit State Transitions National Instruments Corporation 3 119 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 3 8 3 5 BC Counter The BC counter is a 24 bit down counter with dual load registers and output save latch The BC counter typically counts the number of buffers to be output The bitfield AO Source Select controls the SRC The choices for BC source are UPDATE pulses or TC pulses Normally the BC source is configured to count UC pulses The counter load registers are directly accessible from the register map If the counter is di
384. equence AO STARTI Disable 1 for the master DAQ STC AO Delayed STARTI 1 for the master DAQ STC AO Delayed STARTI 0 for all the slave DAQ STCs Perform the usual set up sequence for each DAQ STC see section 3 6 1 Programming for a Primary Analog Output Operation AO STARTI Disable 0 for the master DAQ STC 3 6 5 Primary Analog Output Group Related Interrupts The DAQ STC is designed to be used primarily with a system that supports interrupts This section contains instructions on programming the DAQ STC when it is used in an environment that supports interrupts National Instruments Corporation 3 35 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control The DAQ STC you want to program could be a part of a system in which interrupts do not exist In this case you can use programming sequences intended for ISRs directly in your application coupled with the programming technique known as polling If you use polling your application must periodically read relevant status bitfields and use the values obtained this way to decide whether to execute programming sequences equivalent to ISRs When the DAQ STC is used in a system in which interrupts can be handled but the handling 18 prohibitively slow you can use the polling technique However your system will be devoted entirely to one application Information on interrupts and polling can be found in the National Instruments Application Note
385. equency 20 MHz Min timing resolution 50 ns General Purpose Counter Timers Digital 1 0 Number onte RERO REA 2 Resolution 2 24 bits Max source frequency ss 20 Mhz Min source pulse duration 6 ns Min gate pulse duration 6ns Number of channels 8 T O Compatibility TTL in CMOS out National Instruments Corporation 1 DAQ STC Technical Reference Manual Appendix A Specifications Frequency Output Absolute Maximum Ratings Pin Capacitance Divide ratio eee 1 to 16 Power supply voltage VDD 0 5 to 46 5 V Input output voltage VV Vo 0 5 to 0 5 V Latch up current gt l A typ Output current Pin Type Value O4TU 10mA B9TU O9TU 09 20 mA B18TU OD18U 40 mA Operating temperature 40 to 85 C Storage temperature 65 to 150 C Input capacitance Output capacitance capacitance Recommended Operating Conditions Power supply voltage Ambient temperature TA Low level input voltage High level input voltage Input rise or fall time
386. er Else Inform user that rate change is impossible at this time Else If AO2_UI_Next_Load_Source_St is 1 then AO_UI2_Load_A number of clocks between updates 1 X AO UD Switch Load Next TC 1 ao2 last load register Else Inform user that rate change is impossible at this time DAQ STC Technical Reference Manual 3 44 National Instruments Corporation Chapter 3 Analog Output Timing Control To change the update rate immediately you must perform at least one update using the previous update interval before a change is possible 3 6 9 Master Slave Operation Considerations for Secondary Analog Output There are no provisions for master slave operation of secondary analog output modules on multiple DAQ STCs Shared mechanisms which may require additional external wiring may be used 3 6 10 Secondary Analog Output Related Interrupts The only interrupts related to AO timing generated by the secondary group are generated on the UI2 TC TC To enable AO UD TC Interrupt Enable To recognize AO UD TC St To acknowledge and clear AO UD TC Interrupt Ack This interrupt belongs to group B Refer to section 3 6 5 Primary Analog Output Group Related Interrupts for more information on programming group B interrupts 3 6 11 Bitfield Descriptions Bits in the register bit maps are organized into bitfields A bitfield can contain one or more bits Only bits with contiguous locations within a regis
387. er Type Write only AO UD Software Gate AO UD External Gate Polarity AO START Polarity AOFREQ Enable AO UD Extermal Gate Select AO UD Extermal Gate Select AO UD Extermal Gate Select AO UD Extermal Gate Select AO UD Extermal Gate Select AO START Sync AO START Edge AO START Select AO START Select AO START Select AO START Select AO START Select AO Status 2 Register Type Read only AO UC Next Load Source St AO UC Armed St AO UD Count Enable St AO UD Next Load Source St AO UD Armed St AO UD TC Error St AO UI Q St AO UI Count Enable St AO UC Save St AO UI Next Load Source St AO UI Armed St AO BC TC Trigger Error St AO BC St AO BC Save St AO BC Next Load Source St AO BC Armed St National Instruments Corporation Address 3 15 14 13 N Address 67 15 14 13 N _ Appendix B Register Information AO Status 1 Register Type Read only Interrupt St AO FIFO Full St AO FIFO Half Full St AO FIFO Empty St AO BC TC Error St AO START St AO Overrun St AO STARTI St AO BC TC St AO UC TC St AO UPDATE St AO UD St TC St Gl Gate Interrupt St AO FIFO Request St Pass Thru 1 Interrrupt St AO Trigger Select Register Type Write only AO UI External Gate Enable AO Del
388. er 8 RTSI Chapter 6 Reserved Chapter 10 Slow Chapter 10 Software Chapter 9 Window Chapter 9 Write Strobe Chapter 9 National Instruments Corporation B 9 DAQ STC Technical Reference Manual Appendix B Register Information Register Maps Address 8 15 14 13 N OO AI Command 1 Register Type Write only Reserved AI Analog Trigger Reset AI Disarm AI SI2 Arm AI SI2 Load AI SI Arm AI SI Load AI DIV Arm AI Load AI SC Arm AI SC Load AI SCAN IN PROG Pulse AI EXTMUX CLK Pulse AI LOCALMUX CLK Pulse AI SC TC Pulse AI CONVERT Pulse DAQ STC Technical Reference Manual B 10 Address 4 DU gt tA AI Command 2 Register Type Write only AI End On SC TC AI End On End Of Scan Reserved Reserved AI STARTI Disable AI SC Save Trace AI SI Switch Load On SC TC AI SI Switch Load STOP AI SI Switch Load On TC Reserved Reserved AI SC Switch Load On TC AI STOP Pulse AI START Pulse AI START2 Pulse AI STARTI Pulse National Instruments Corporation AI DIV Load A Register Address 64 Type Write only 15 AI DIV Load 14 AI DIV Load 13 AI DIV Load AI DIV Load A AI DIV Load A AI DIV Load A AI DIV Load A AI DIV Load A AI DIV Load A AI DIV Load A AI DIV Load A AI DIV Load A AI DIV Load A AI DI
389. er is used by the AITM 0 Use STARTI trigger immediately 1 Delay the STARTI trigger by synchronizing it to the CONVERT source Set this bit to 1 in the master ASIC during master slave trigger The slave ASIC s can then synchronize to the same clock as the master by triggering on the STARTI signal that is output from the master National Instruments Corporation 2 51 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control AI Delayed START2 bit 10 type Write in AI Mode 3 Register address 87 This bit determines when the START trigger is used by the AITM 0 Use START trigger immediately 1 Delay the START trigger by synchronizing it to the CONVERT source Set this bit to 1 in the master ASIC during master slave trigger The slave ASIC can then synchronize to the same clock as the master by triggering on the START2 signal that is output from the master Delay START bit 14 type Write in AI Mode 3 Register address 87 This bit selects the internal clock that synchronizes the START trigger when START synchronization is selected 0 START synchronizes to 512 SRC internal CONVERT or to FSCLK external CONVERT 1 START synchronizes to SC SRC Since the clock SC is internally delayed relative to 812 SRC and FSCLK setting this bit to 1 provides additional margin for the external START to reach the synchronization flip flop but allows less margin for the output of the synchronization flip f
390. erence Manual B 28 National Instruments Corporation 15 14 13 N 15 14 13 N _ G0 Load B Registers Address 31 Type Write only GO Load B GO Load B GO Load B GO Load B GO Load B GO Load B GO Load B GO Load B GO Load B GO Load B GO Load B GO Load B GO Load B GO Load B GO Load GO Load B GO Save Registers Address 12 Type Read only Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GO Save Value GO Save Value GO Save Value GO Save Value GO Save Value GO Save Value GO Save Value GO Save Value National Instruments Corporation Address 26 15 14 13 N Om Address 13 15 14 13 N _ gt Appendix B Register Information G0 Mode Register Type Write only GO Reload Source Switching GO Loading On Gate GO Gate Polarity GO Loading On TC GO Counting Once GO Counting Once GO Output Mode GO Output Mode GO Load Source Select GO Stop Mode GO Stop Mode GO Trigger Mode For Edge Gate GO Trigger Mode For Edge Gate GO Gate On Both Edges GO Gating Mode GO Gating Mode G0 Save Registers Type Read only GO Save Value GO Save Value GO Save Value GO Save Value GO Sav
391. erence Manual C 6 National Instruments Corporation Appendix C Pin List Table 6 1 DAQ STC Pins in Alphabetical Order Continued Pin Name Pin Number Buffer Type VCC 120 VCC ADDED 60 VCC ADDED 140 WR DS 66 IU WRITE STROBEO 27 O4TU WRITE STROBEI 28 O4TU WRITE STROBE2 29 O4TU WRITE_STROBE3 30 O4TU These pins are pulled down on the first revision of the DAQ STC and pulled up on the later revisions See Appendix D DAQ STC Revision History for DAQ STC revision information Table C 2 Summary of Buffer Types Resistor Nominal Name In Out Input Level Output Level Value mA mA B18TU In Out TTL CMOS 3 State 50k Up 24 13 B9TU In Out TTL CMOS 3 State 50k Up 9 5 ODISU Nch Open 50k Up 24 0 Drain O9TU Out CMOS 3 State 50k Up 9 5 09 CMOS 9 5 O4TU Out CMOS 3 State 50k Up 4 5 2 5 ID In TTL 50kDown IS In TTL Schmitt IU In TTL 50k Up IU5 In TTL 5k Up National Instruments Corporation C 7 DAQ STC Technical Reference Manual Appendix C Pin List ic Note Pull up pull down resistance values are as follows Resistance Nominal Value Minimum Typical Maximum 50 KQ 17 38 100 5kQ 2 9 13 DAQ STC Technical Reference Manual 8 National In
392. errupts 2 46 to 2 48 master slave operation considerations 2 45 to 2 46 number of scans 2 33 overview 2 25 to 2 26 register and bitfield considerations 2 24 resetting 2 26 to 2 27 sequence of functions for 2 42 single scan 2 42 to 2 43 software gate operation 2 31 staged acquisition 2 44 to 2 45 start of scan 2 34 to 2 37 starting the acquisition 2 41 to 2 42 trigger signals 2 32 to 2 33 windowing registers 2 25 analog output operation primary 3 20 to 3 32 arming 3 30 to 3 31 bitfield descriptions 3 45 to 3 84 board power up initialization 3 22 to 3 23 changing update rate 3 34 to 3 35 channel select 3 28 enable interrupts 3 30 FIFO mode 3 29 to 3 30 interrupts 3 35 to 3 37 LDAC source and UPDATE mode 3 29 master slave operation considerations 3 35 National Instruments Corporation Index number of buffers 3 24 to 3 26 general purpose counter timer overview 3 21 4 17 to 4 52 resetting 3 21 to 3 22 arming 4 18 sequence of functions in 3 31 to 3 32 bitfield descriptions 4 35 to 4 52 starting the waveform 3 30 to 3 31 buffered event counting 4 20 to 4 22 stop on error 3 29 buffered period semiperiod and trigger signals 3 23 to 3 24 pulsewidth measurement update selection 3 26 to 3 28 4 26 to 4 28 waveform staging 3 32 to 3 34 enabling general purpose analog output operation secondary counter timer output pin 4 35 3 38 to 3 42 frequency shift keying 4 31 to 4
393. erted at the same time when LOCALMUX CLK is asserted and their pulsewidths are equal Output polarity is selectable Destination External Multiplexer Options Active Low Active High Ground High Z Related bitfields AI EXTMUX CLK Output Select AI EXTMUX Pulse AI EXTMUX Pulse Width GHOST IU Ghost Input This active high input masks the AI FIFO SHIFTIN pulses associated with specific channels to allow multirate scanning The GHOST signal is produced by the configuration FIFO containing the scan list Source Configuration FIFO National Instruments Corporation 2 21 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Table 2 1 Pin Interface Continued Pin Name Type Description LOCALMUX CLK O4TU Configuration FIFO Advance Clock This output clocks the local configuration FIFO containing the scan list thereby updating the channel gain and channel configuration selections The LOCALMUX_CLK pulse is asserted on CONVERT and remains asserted based on the selected pulsewidth with the added condition that SOC must arrive before the signal is deasserted When an external multiplexer is present the LOCALMUX_CLK signal can be configured to pulse only after every n conversions where n is determined by the value in the 16 bit DIV counter This is useful when an external multiplexer is used to switch more than one active channel into a channel in the
394. es to BC load register A are 0 Unconditionally directed to BC load register A 1 Directed to the inactive BC load register 0 Configuration End bit 9 type Strobe Joint Reset Register address 72 This bit clears Configuration Start which holds the analog output circuitry in reset to prevent glitches on the output pins during configuration You should set this bit to 1 at the end of the configuration process of the analog output circuitry excluding the UI2 counter This bit is cleared automatically Related bitfields Configuration Start 0 Configuration Start bit 5 type Strobe Joint Reset Register address 72 This bit holds the analog output circuitry in reset to prevent glitches on the output pins during configuration The following analog output circuits are affected output circuits counter control circuits trigger circuits interrupt circuits The following circuits are also affected nterrupt B Register Auto acknowledge circuit for general purpose counter 1 You should set this bit to 1 at the beginning of the configuration process of the analog output circuitry excluding the UI2 counter By doing this you ensure that no spurious glitches appear on the output pins and on the internal circuit components If you do not set this bit to 1 the DAQ STC may behave erroneously You can clear this bit by setting AO Configuration End to 1 Related bitfields Configuration En
395. eserved Reserved Reserved GO Autoincrement GO Autoincrement GO Autoincrement GO Autoincrement GO Autoincrement GO Autoincrement GO Autoincrement _ DOO CO GO Autoincrement G0 HW Save Registers Address 8 Type Read only 15 Reserved 14 Reserved 13 Reserved Reserved N Reserved Reserved Reserved Reserved GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value National Instruments Corporation Address 6 15 14 13 N _ 1o0 ODODO Address 9 15 14 13 N Appendix Register Information G0 Command Register Type Write only Disarm Copy Save Trace Copy Arm Copy GO Bank Switch Enable GO Bank Switch Mode GO Bank Switch Start GO Little Big Endian GO Synchronized Gate GO Wirite Switch GO Up Down GO Up Down GO Disarm GO Analog Trigger Reset GO Load GO Save Trace GO Arm G0 HW Save Registers Type Read only GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO HW Save Value GO H
396. eserved 1 St 11 Reserved 1 St 10 Reserved 1 St 9 Reserved 1 St 8 Reserved 1 St 7 DIO Parallel Data In St 6 DIO Parallel Data In St 5 DIO Parallel Data In St 4 DIO Parallel Data In St 3 DIO Parallel Data In St 2 DIO Parallel Data In St 1 DIO Parallel Data In St O DIO Parallel Data In St DAQ STC Technical Reference Manual B 26 ee NUR DO NW KN eS eS 9 NW gt tA DIO Output Register Address 10 DIO Serial Data Out DIO Serial Data DIO Serial Data DIO Serial Data Out DIO Serial Data DIO Serial Data DIO Serial Data DIO Serial Data Out DIO Parallel Data Out DIO Parallel Data Out DIO Parallel Data Out DIO Parallel Data Out DIO Parallel Data Out DIO Parallel Data Out DIO Parallel Data DIO Parallel Data DIO Serial Input Register Address 28 Reserved 2 St Reserved 2 St Reserved 2 St Reserved 2 St Reserved 2 St Reserved 2 St Reserved 2 St Reserved 2 St DIO Serial Data In St DIO Serial Data In St DIO Serial Data In St DIO Serial Data In St DIO Serial Data In St DIO Serial Data In St DIO Serial Data In St DIO Serial Data In St National Instruments Corporation Type Write only Type Read only G0 Autoincrement Register Address 68 Type Write only 15 Reserved 14 Reserved 13 Reserved Reserved N Reserved R
397. ess 58 i 5 bit 14 type Write in RTSI Trig Direction Register address 58 i 6 bit 15 type Write in RTSI Trig Direction Register address 58 This bit selects the of the bidirectional pin RTSI TRIGGERIT 0 Input 1 Output National Instruments Corporation 6 5 DAQ STC Technical Reference Manual Chapter 6 RTSI Trigger 6 5 Detailed Description When configured as inputs the RTSI TRIGGER pins provide an interface through which your timing I O signals can be brought to the internal DAQ STC modules Each of the three main internal modules AITM and GPCT has 20 to 1 input multiplexers PFI selectors to select their relevant timing control input signals Refer to section 5 5 Detailed Description for a complete list of the PFI selectors available in each module When configured as outputs each RTSI TRIGGER pin reflects the status of a particular signal related to the timing control signals The pins will power up as inputs and will be used primarily as inputs The output capability on these pins is useful for synchronizing external circuitry to the board Table 6 2 gives a list of the internal signals that are available as outputs on the 5 TRIGGER pins Table 6 2 RTSI_TRIGGER lt 0 6 gt Output Selections RTSI Trig Output Select SIGNAL 0 The internal analog input signal ADR STARTI 1 The internal analog input signal START2 2 The internal analog input signal SC
398. etected in these applications Use this function to program a counter for single pulse generation single triggered pulse generation or retriggerable single pulse generation Program the Gi_Source to select the signal that you want to use as a reference clock For single triggered pulse generation and retriggerable single pulse generation program Gi_Gate to select the signal that you want to use as a hardware trigger DAQ STC Technical Reference Manual 4 28 National Instruments Corporation Chapter 4 General Purpose Counter Timer Function Single Pulse Generation Gi_Load_Source_Select 0 If single pulse generation then Gi_Load_A delay from software arm to first edge of pulse 1 Else Single triggered pulse generation or retriggerable single pulse generation Gi_Load_A delay from hardware trigger to first edge of pulse 1 X Gi Load 1 gt Gi Load B pulsewidth 1 Gi Load Source Select 1 Gi Source Select 0 IN TIMEBASEI1 or 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 IN TIMEBASE2 or 19 other G TC Gi Source Polarity 0 count rising edges or 1 count falling edges Gi Gate Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 AI START2 or 19 UI2 TC or 20 other TC or 21 AI START or 31 logic low Gi OR Gate 0 Gi Output Polarity 0 active low or 1 active high Gate Select Load Source
399. etical Order Continued Pin Name Pin Number Buffer Type D3 78 B9TU D4 82 B9TU D5 83 B9TU D6 84 B9TU D7 85 B9TU D8 55 B9TU D9 54 B9TU D10 52 B9TU D11 51 B9TU D12 49 B9TU D13 47 B9TU 14 45 B9TU 015 43 B9TU DACWR 0 157 O4TU DACWR 1 158 O4TU DIOO SDOUT 126 18 DIO1 124 B18TU DIO2 119 B18TU DIO3 116 B18TU DIO4 SDIN 114 B18TU 005 112 B18TU DIO6 110 18 DIO7 107 B18TU DIV_TC 117 O4TU EOC 135 IU EXTMUX_CLK 104 O9TU EXTSTROBE SDCLK 103 O9TU National Instruments Corporation C 3 DAQ STC Technical Reference Manual Appendix C Pin List Table 6 1 DAQ STC Pins in Alphabetical Order Continued Pin Name Pin Number Buffer Type FOUT 87 O9TU OUTO RTSI IO 88 B9TU OUTI DIV TC OUT 94 O9TU UP DOWNO 108 ID IU G UP DOWNI 111 ID IU GHOST 142 IU GND 21 GND 41 z GND 42 GND 79 GND 80 GND 101 GND 121 GND 122 GND 159 GND 160 INTEL MOTO 113 IU IRQ INO 73 IU INI 71 IU IRQ OUTO 72 OD18U IRQ OUTI 70 OD18U IRQ_OUT2 67 OD18U IRQ_OUT3 53 OD18U IRQ_OUT4 50 OD18U IRQ_OUTS 48 OD18U IRQ OUT6 46 OD18U IRQ_OUT7 44 OD18U DAQ STC Technical Reference Manual C 4 National Instruments Corporation Appendix C Pin List Table C 1 DAQ STC Pins in Alphabetical Order Co
400. example in a buffered period measurement function the software must be able to read the current period measurement before the hardware acquires the next period measurement Error detection circuits flag the case in which the software is unable to service the hardware within the allowed time Error bits in the status register indicate the current error conditions 4 8 10 1 Gate Acknowledge Latency Error The gate acknowledge latency error indicates that the software does not read the HW save register in time or reads it at an inappropriate time In several functions for example buffered event counting and buffered period measurement the G_GATE signal saves the counter value in the HW save register If the software read from the HW save register does not occur before another save operation is attempted via the G_GATE signal the gate acknowledge latency error Gi_Gate_Error_St is set because the read value may be erroneous The error mechanism is conservative so that an error may be present without an actual failure but the absence of an error guarantees that no failure has occurred 4 8 10 2 Stale Data Error This error indicates that the G_GATE signal is not being measured properly In several functions for example single pulsewidth measurement and single period measurement the counter uses G_SOURCE pulses to count the duration of an event on the G_GATE signal If two relevant G edges occur without an intervening G SOURCE edge
401. exers to divide IN TIMEBASE by two and select either IN TIMEBASE or IN TIMEBASE divided by two for routing to the various modules This scheme allows using either a 10 MHz or 20 MHz clock at the OSC pin without necessarily scaling the absolute timing The OUTBRD OSC pin supplies the IN TIMEBASE signal to the board either directly or divided by two OSC gt IN TIMEBASE RTSI OSC gt OUTBRD OSC lt DIV2 Figure 10 1 Clock Distribution The clock distribution circuit generates two input timebases and one output timebase for the AITM AOTM and GPCT modules The slower input timebase IN TIMEBASE2 is shared by AITM AOTM and GPCT The multiplexers allow for independent selection of the clock source for the various modules The multiplexers also provide additional flexibility when interfacing the DAQ STC to system components because the output portion of the various modules can use a different clock from the input portion of the same module Table 10 1 indicates the internal timebases derived from IN TIMEBASE Table 10 1 Timebases Derived from IN TIMEBASE Timebase Related Bitfields Divide Options IN TIMEBASE2 Slow Internal Time Divide By 2 100 200 Slow Internal Timebase AI IN TIMEBASEI AI Source Divide By 2 1 2 DAQ STC Technical Reference Manual 10 2 National Instruments Corporation Chapter 10 Miscellaneous Functions
402. f the host system If less than seven address lines are used the unused address inputs should be tied low In this case two accesses are required to read from or write to one of the indirectly addressed registers Frequently accessed registers occupy lower addresses in the address space of the DAQ STC so that they can be accessed directly Source CPU bus CHRDY IN 105 Board Level Channel Ready When CHRDY is deasserted the DAQ STC deasserts OUT requesting that the CPU bus extend the current bus cycle CHRDY OUT OD18U Channel Ready Output This is an active high signal used for bus cycle extension This signal is driven low when a bus cycle needs to be extended A bus cycle extension can occur due to a board level request CHRDY_IN or it can occur when the CPU tries to access a D A converter during a DAQ STC write to the D A converters Destination CPU bus CS IU Chip Select This is an active low signal to activate the DAQ STC to read from or write to one of the registers Source CPU bus D lt 0 15 gt B9TU Bidirectional Tri State Data Bus This signal transfers data between the DAQ STC and the CPU Source Destination CPU bus INTEL MOTO IU Intel Motorola Bus Interface Selection Intel mode uses RD and WR signals Motorola mode uses R W and DS signals DAQ STC Technical Reference Manual 9 2 National Instruments Corporation Chapter 9 Bus I
403. f then should be executed in the order shown FOUT_Enable 0 L FOUT_Timebase_Select 0 FOUT IN TIMEBASEI1 or 1 TIMEBASE2 FOUT Divider 0 for division factor 16 or 1 15 for division factor 1 15 gt FOUT Enable 1 4 6 1 1 Overview The DAQ STC contains two general purpose counters general purpose counter 0 and general purpose counter The two general purpose counters are designed to be used in various applications Each general purpose counter is equipped with two save registers and two banks of load registers Every bank of load registers contains two load registers The two banks of load registers are called bank X and bank Y The two load registers in each bank are called load register A and load register B The two save registers are used for saving the contents of the counter they are called the HW save register and the save register National Instruments Corporation 4 17 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 6 1 2 Notation In this section Gi refers to bitfields pertaining to either one of the two general purpose counters The notation will be used consistently for a single general purpose counter within each individual programming sequence Gj will be used for references to the other general purpose counter To summarize Gi can denote general purpose counter 0 or general purpose counter 1 in any programming sequence if Gi is denoting general purpose
404. ffer into the DACs i Note For the TMRDACWR pulses to be generated AO FIFO Enable must be set to 1 and the data FIFO must contain data If the analog output section is in external update mode the AO St bit be set after toggling the AO Not UPDATE bit high and low After toggling the AO Not An UPDATE bit wait for the AO TMRDACWRSs In Progress St bit to be cleared then set the AO Error Interrupt Ack to clear the St bit This bit is NOT cleared automatically 0 Number Of Channels bits lt 6 9 gt type Write in AO Output Control Register address 86 If AO Multiple Channels is set to 1 this bitfield determines the number of analog output channels that will be written 0 15 Output channels 0 through the selected number will be written If AO Multiple Channels is set to 0 this bitfield determines the number of the single analog output channel that will be written 0 15 Output channel 0 15 will be written Related bitfields Multiple Channels National Instruments Corporation 3 59 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 Number Of DAC Packages bit 14 type Write in AO Personal Register address 78 This bit selects the DAC mode 0 Dual DAC mode 1 Single DAC mode The pins DACWR lt 0 1 gt pulse on each TMRDACWR CPUDACWR In the dual DAC mode DACWRO pulses on every write and DACWRI is not used In the single D
405. first gate edge stops the next starts the counting 2 Gate edge always starts the counting unless counting is already in progress in which case the edge is ignored The valid Stop Mode settings for this selection are 1 and 2 but only the TC not the gate will stop the counting 3 Gate is used for reload save or load select only if any of those options is enabled not for stopping Selections 0 and 1 are valid only if Gi Stop Mode is set to 0 no hardware limit on this Selections 0 1 and 2 are valid only if Gi Gating Mode is set to 2 or 3 Selection 3 is valid only if Gating Mode is not set to 0 Related bitfields Gi Gating Mode Stop Mode DAQ STC Technical Reference Manual 4 50 National Instruments Corporation Chapter 4 General Purpose Counter Timer Up Down i 0 bits 5 6 type Write in GO Command Register address 6 i 1 bits lt 5 6 gt type Write in Command Register address 7 This bit selects the up down mode 0 Software selected down counting 1 Software selected up counting 2 Hardware selected up down counting controlled by the UP DOWNTI input pins Logic low Count down Logic high Count up 3 Hardware selected up down counting controlled by the internal gate value see Gating Polarity Active gate level Count up Inactive gate level Count down Selection can be changed while the counter is counting Related bitfields Gi Gating Polarity Write Acknow
406. fter the pretrigger count requirement has been satisfied That is in the pretrigger acquisition mode the first SC_TC does not generate an interrupt National Instruments Corporation Chapter 2 Analog Input Timing Control Table 2 11 summarizes the analog input interrupts and lists the condition that causes the interrupt Table 2 11 Analog Input Interrupts Interrupt Condition Error interrupt Interrupt generated on the detection of a overrun or overflow error condition START interrupt Interrupts are generated on valid START triggers received by the DAQ STC A valid START trigger is one that is received while the SC counter is enabled to count The actual interrupt signal appears on the active edge of SC CLK STOP interrupt Interrupts are generated on valid STOP triggers received by the DAQ STC A valid STOP trigger is one that is received after a valid START and while counting is enabled on the SC counter After a valid START the actual interrupt signal appears on the active edge of SC CLK Note that this interrupt must be used in conjunction with the START interrupt STARTI interrupt Interrupts are generated on valid STARTI triggers received by the DAQ STC A valid STARTI trigger is one that is received while the SC counter is armed and in the WAITI state The actual interrupt signal appears on the active edge of SC CLK START interrupt Interrupts are generated on valid START2 triggers received by the
407. function as an ISR for staged acquisitions Function AI Staged ISR If the last load was from the last load register written to it is all right to change the rate Otherwise you cannot change the rate If si last load register is O then AI_SI_Load_B si_ticks si_ticks_pointer 1 If sc_ticks sc_ticks_pointer is 0 then 1 AI SC TC Interrupt Enable 0 Else DAQ STC Technical Reference Manual 2 44 National Instruments Corporation Chapter 2 Analog Input Timing Control AI SC Load sc ticks si ticks pointer 1l AI SI Switch Load On SC 1 AI SC Switch Load 1 si_ticks_pointer l si last load register l Else AI SI Load si ticks si ticks pointer l If sc ticks sc ticks pointer is 0 then 1 AI SC Interrupt 0 Else AI sc_ticks si_ticks_pointer 1 AI SI Switch Load On SC 1 AI SC Switch Load 1 si ticks 1 1 si last load register 0 AI SC TC Interrupt Ack 1 Check for interrupt latency problems If AI SC TC Error St is 0 then AI SC TC Confirm 1 Else Inform user that an SC_TC error has occurred 2 6 7 Master Slave Operation Considerations You can use several DAQ STCs for synchronized analog input operation To do this connect the tri
408. ge of BC 0 BC TC St bit 7 type Read in AO Status 1 Register address 3 This bit indicates whether the BC counter has reached TC 0 No 1 Yes This bit is set on the trailing edge of BC You can clear this bit by setting AO BC TC Interrupt Ack to 1 Related bitfields AO BC Interrupt Ack Refer to Table 8 2 Interrupt Condition Summary for more information 0 BC TC Trigger Error Confirm bit 3 type Strobe Interrupt Ack Register address 3 Setting this bit to 1 clears AO BC TC Trigger Error St This bit is cleared automatically Related bitfields TC Trigger Error St DAQ STC Technical Reference Manual 3 50 National Instruments Corporation Chapter 3 Analog Output Timing Control 0 BC TC Trigger Error St bit 4 type Read in AO Status 2 Register address 6 This bit indicates the detection of a BC TC trigger error 0 No error 1 Error A BC TC trigger error occurs when a STARTI trigger is received after the last TC of a staged waveform but before BC TC Interrupt Ack is set to 1 This allows you to detect triggers which arrive before completion of your ISR You can clear this bit by setting AO BC Trigger Error Confirm to 1 Related bitfields BC TC Interrupt AO BC TC Trigger Error Confirm 0 BC Write Switch bit 0 type Write in AO Mode 2 Register address 39 This bit enables the write switch feature of the BC load registers Writ
409. ger modes Hardware and software triggering Support for analog triggering e Delayed trigger Interval counters have alternate first period capability for retriggerable delay from trigger Minimum delay of 1 update interval clock Maximum delay of 224 update interval clocks e Gating Hardware and software gating e Simplified interface to data FIFO Supports local buffer mode Error detection Underflow error detection flag for internal or external timing on both update groups A Additional error detection for double buffered parameter change operations e Bus interface support Interrupts based on update triggers error conditions and FIFO flags FIFO flag based request signal to simplify DMA or interrupt request logic Bus cycle extension for D A bus contention case and slow DAC write case National Instruments Corporation 3 3 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 3 9 Simplified Model The AOTM module contains the hardware necessary to generate timing and control signals for the DAC on an MIO board Figure 3 1 shows a simplified model of the AOTM module lt 0 9 gt gt RTSI lt 0 6 gt SELECT START Di UL TC UPDATE p COUNTER OSC CPUDACREQ AOFFF UC AOFHF COUNTER AOFEF I TMRDACWR AO ADDR O 3 CPUDACWR OUTP
410. ger selection 3 115 to 3 116 PFI signals CTRGATE reference pin selection table 4 54 National Instruments Corporation 1 29 Index CTRSRC reference pin selection table 4 53 external trigger timing 3 102 external UPDATE mode 3 12 master slave trigger 3 15 SCAN IN PROG deassertion 2 103 simplified analog input model 2 5 simplified analog output model 3 4 START trigger and SCAN IN PROG assertion 2 100 external CONVERT mode 2 102 internal CONVERT mode 2 101 START and START triggers asynchronous mode 2 99 to 2 100 synchronous mode 2 97 to 2 98 START trigger output 3 104 to 3 107 PFIO AI STARTI signal table 5 2 PFIO AI START signal table 5 2 PFI2 CONV signal table 5 3 PFI3 G_SRC1 signal table 5 3 PFI4 G_GATEI signal table 5 3 PFI5 UPDATE signal table 5 3 PFI6 AO 5 signal table 5 4 PFI7 AI START signal table 5 4 PFI8 G_SRCO signal table 5 5 PFI9 G_GATEO signal table 5 5 pin capacitance specifications A 2 pin interface See also signals alphabetical list of pins table C 1 to C 7 analog input timing control module table 2 19 to 2 23 analog output timing control module table 3 16 to 3 20 bus interface module table 9 1 to 9 3 digital I O table 7 6 to 7 7 general purpose counter timer table 4 16 interrupt control table 8 2 miscellaneous functions table 10 9 to 10 10 PFI module table 5 2 to 5 5 DAQ STC Technical Reference Manual Index
411. gger signal to the trigger input of the master DAQ STC You also connect the output equivalents of the triggers from the master DAQ STC to the slave DAQ STCs You may use the RTSI connector to do this Note You must perform the programming sequence described in section 10 8 1 Programming Clock Distribution before you execute the sequence given here National Instruments Corporation 2 45 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Use the following programming sequence AI STARTI Disable 1 for the master DAQ STC AI Delayed STARTI 1 for the master DAQ STC AI Delayed STARTI 0 for all the slave DAQ STCs If pretriggered AT then AI_Delayed_START2 1 for the master DAQ STC AI_Delayed_START2 0 for all the slave DAQ STCs Perform the usual set up sequence for each DAQ STC See programming sequence in Analog Input Program AI STARTI Disable 0 for the master DAQ STC 2 6 8 Analog Input Related Interrupts The DAQ STC is designed to be used primarily with a system that supports interrupts This section contains instructions on programming the DAQ STC when it is used in an environment that supports interrupts If the DAQ STC you want to program is part of a system in which interrupts do not exist you can use programming sequences intended for ISRs directly in your application coupled with the programming technique known as polling If you use polling your application must
412. gister address 23 This bitfield reflects the contents of the UI2 counter Reading from this bitfield while the UI2 counter is counting may result in an erroneous value National Instruments Corporation 3 77 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 UI2 Software Gate bit 15 type Write in AO START Select Register address 66 Setting this bitto 1 stops the UI2 counter immediately Setting this bit to 0 allows the UI2 counter to count 0 UI2 Source Polarity bit 12 type Write in AO Trigger Select Register address 67 This bit selects the active edge of the UD2 source the signal that is selected by AO UD Source Select 0 Rising edge Falling edge Related bitfields UI2 Source Select 0 2 Source Select bits lt 7 11 gt type Write in AO Trigger Select Register address 67 This bit selects the UI2 source 0 The internal signal AO IN TIMBASEI 1 10 PFI lt 0 9 gt 11 17 RTSI_TRIGGER lt 0 6 gt 18 The internal TC signal from general purpose counter 0 19 The internal TC signal from general purpose counter 1 20 The internal signal IN TIMEBASE2 31 Logic low 0 UI2 Switch Load Next TC bit 13 type Strobe AO Mode 3 Register address 70 Setting this bitto 1 causes the UI2 counter to switch load registers at the next UI2 TC This bit is cleared automatically 0 UI2 TC Error Confirm bit 5 type Strobe in Interrupt Reg
413. gister address 6 i l bit 8 type Write Command Register address 7 This bit enables gate synchronization to the source 0 Disabled 1 Enabled You should normally set this bitto 1 You can set this bit to O if you know that the gate signal is synchronized to the source signal Gi TC Error Confirm i 0 6 type Strobe Interrupt Ack Register address 2 bit 2 type Strobe Interrupt Ack Register address 3 Setting this bit to 1 clears Error St This bit is cleared automatically Related bitfields TC Error St Gi TC Error St i 0 0 12 type Read Status Register address 4 i 1 bit 13 type Read in G_Status_Register address 4 This bit indicates the detection of a TC latency error 0 No 1 Yes A TC latency error is detected if Gi_TC_Interrupt_Ack is not set between two counter TCs This allows you to detect large interrupt latencies and potential problems associated with them To clear this bit set Gi_TC_Error_Confirm to 1 Related bitfields Gi_TC_Interrupt_Ack Gi_TC_Error_Confirm Gi_TC_Interrupt_Ack i 0 1 14 type Strobe Interrupt_A_Ack_Register address 2 i l bit 14 type Strobe Interrupt Ack Register address 3 Setting this bit to 1 clears Gi TC St and acknowledges the TC interrupt request in either interrupt bank if the TC interrupt is enabled This bit is cleared automatically Related bitfields St National Instrume
414. gital 1 0 7 8 Detailed Description Two periodic timebases are available for timing the serial output a 1 2 clock and a 10 us clock The clock is selected according to Table 7 2 Table 7 2 Serial Output Source Select DIO HW Serial Timebase Description 0 1 2 us clock 1 10 us clock The DIO lt 0 7 gt directionality control is provided by DIO Pins Dir Each of the eight digital lines can be individually configured using this bitfield Two way digital communication can be accomplished on the DIO lines by programming some of the lines for input and some for output In parallel I O mode the bits in the read register that correspond to pins configured for output should be ignored Similarly the bits in the write register that correspond to pins configured for input are ignored by the hardware National Instruments Corporation 7 17 DAQ STC Technical Reference Manual Interrupt Control 8 1 Overview 8 2 This chapter describes the interrupt control module ICM its features and the conditions that cause interrupts The ICM consists of two interrupt banks that can be routed to any two of the eight open drain interrupt output lines The ICM allows using one or two interrupt channel interfaces to the CPU Interrupt group A handles the interrupts associated with the AITM the board level interrupt input INO and interrupts associated with general purpose counter 0 Interrupt group B han
415. gnized on a falling edge of the output clock before TMRDACWR is asserted In this case the CPU driven write will occur immediately while the DAQ STC driven write will be delayed as shown in Figure 3 17 The shaded region of the signal TMRDACWR indicates where the TMRDACWR signal would have been asserted had there been no contention Notice that the two write pulses are again separated by one clock period The timing parameters are identical to those for the first conflict case out ek X 2 A S _ _ _ _ p Tctwrd Tctwr Twr o CPUDACREQ Treqchrdy N TMRDACWR Tewrcrdy CHRDY_OUT CPUDACWR Figure 3 17 Analog Output Contention Timing Case B DAQ STC Technical Reference Manual 3 92 National Instruments Corporation Chapter 3 Analog Output Timing Control 3 7 5 Secondary Analog Output Timing The DAQ STC supports a limited secondary group for analog output An on chip 16 bit counter timer is connected to the UPDATE2 pin which can provide periodic update pulses This counter timer can also generate an interrupt to coincide with each update pulse which can be used for a straightforward interrupt driven analog output With appropriate external circuitry DMA operations could be performed as well Figure 3 18 shows the timing for this signal OUT CLK AA NS N 2
416. gt gt SELECT STOP SI TC gt CONVERT AL STOP IN S SI 52252 COUNTER gt LOCALMUX ion 24 gt LOCALMUX AIFFF gt SI TC I EXTMUX FIFO SHIFTIN ADER CONTROL DIV TC OUTPUT gt SHIFTIN AIFREQ SCAN PROG pv COUNTER START FP 5 86 COUNTER SC TC Figure 2 2 AITM Simplified Model One of the primary features of the AITM is that a wide variety of signals can be selected as timing and control sources The simplified model depicts this as a select circuit which chooses between the 10 PFI signals PFI lt 0 9 gt the seven RTSI signals RTSI_TRIGGER lt 0 6 gt and the dedicated STOP input signal STOP IN Many of the signals required for the ADC can come from external sources routed through the selector The DAQ STC can also generate the timing sources internally The simplified model in Figure 2 2 shows that the source for the CONVERT pulse may come from the SI2 counter internal CONVERT source or the select circuit external CONVERT source SOC start of conversion and EOC end of conversion are status signals generated by the ADC SOC indicates that a conversion has begun and indicates that a conversion is complete Using CONVERT as a reference the output circuit generates several ancillary signals used on the board The LOCALMUX
417. gured for input it will be in the pull up high impedance state 1 The signal from the OSC pin will be used as internal timebase The RTSI OSC pin will be configured for output it will propagate the signal coming from the OSC pin In this mode the signal from the OSC pin is used as the internal timebase directly in other words not after passing through the RTSI OSC pin buffers 2 Slave clock The signal from the OSC pin will be ignored The RTSI OSC pin will be configured for input The signal from the RTSI OSC pin will be used as the internal timebase 3 Master clock The signal from the OSC pin will be used as the internal timebase The RTSI OSC pin will be configured for output it will propagate the signal coming from the OSC pin The signal from the OSC pin will pass through two buffers provided for use with the RTSI OSC pin before becoming the internal timebase this design provides the best master slave clock synchronization DAQ STC Technical Reference Manual 6 4 National Instruments Corporation Chapter 6 RTSI Trigger RTSI Sub Selection 1 bit 15 type Write in RTSI Trig B Output Register address 80 This bit determines the signal propagated when any of the RTSI Trig Output Select bitfields is set to 7 to select the internal signal RGOUTO 0 The G OUT signal from general purpose counter 0 1 The signal present on the OUTO RTSI IO pin RTSI Trig Output Select i 0 bits 0 3 type Write in RTSI Trig A Out
418. hat is specific to the bus interface For general information about programming the DAQ STC see section 2 6 Programming Information National Instruments Corporation 9 3 DAQ STC Technical Reference Manual Chapter 9 Bus Interface 9 4 1 Programming the Write Strobes Use the following function to pulse the write strobe signals WRITE 5 lt 0 3 gt Function MSC Write Strobe switch strobe number case 0 Write_Strobe_0 1 break case 1 Write_Strobe_1 1 break case 2 Write_Strobe_2 1 break case 3 Write_Strobe_3 1 break i Note These are generic strobe lines Refer to the hardware manual for your DAQ board or device for information on how these lines are used 9 4 2 Bitfield Descriptions Bits in the register bit maps are organized into bitfields A bitfield can contain one or more bits Only bits with contiguous locations within a register can belong to a bitfield The high and low pairs of load and save registers for 24 bit counters are also treated as bitfields The bus interface related bitfields are described below Not all bitfields referred to in section 9 4 Programming Information are listed here To locate a particular bitfield description within this manual refer to Appendix B Register Information Software_Reset bit 11 type Write in Joint_Reset_Register address 72 Setting this bit to 1 resets the DAQ STC and is equivalent to pulsing the RESET pin Setting th
419. he DAQ STC National Instruments Corporation 3 5 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 3 4 1 1 DAQ STC Driven Analog Output In DAQ STC driven analog output the primary output signals are UPDATE TMRDACWR and ADDR O 3 The UPDATE signal serves to transfer the data to the outputs of all of the DACs simultaneously Following the UPDATE the DAQ STC writes the next data point to each DAC sequentially using the write pulse TMRDACWR The AO_ADDR lt 0 3 gt signals indicate which DAC is to be the destination of the current write pulse The TMRDACWR signal actually performs the write and you should decode the AO_ADDR lt 0 3 gt lines to determine which DAC to select Figure 3 2 shows two DAQ STC driven analog output operations on a board configured for four analog output channels After each update the TMRDACWR signal pulses four times to reload the DACs AO_ADDR 0 gt 01 2 0 TMRDACWR EBEN UPDATE X1X2X3 X_0 Figure 3 2 DAQ STC Driven Analog Output 3 4 1 2 CPU Driven Analog Output The DAQ STC also provides circuitry that allows the CPU to write directly to the output channels The primary signals for CPU driven analog output are CPUDACREQ CHRDY_OUT and CPUDACWR The CHRDY_OUT signal is discussed in Chapter 9 Bus Interface The CPU initiates an analog output by asserting CPUDACREQ and pla
420. he WRITE STROBEI pin Write Strobe 2 bit 0 type Strobe Write Strobe 2 Register address 84 Writing to this register pulses the WRITE STROBE2 pin Write Strobe 3 bit 0 type Strobe Write Strobe 3 Register address 85 Writing to this register pulses the WRITE STROBES pin 9 5 Timing Diagrams The DAQ STC is statically configurable for Intel or Motorola style bus interfaces which are adaptable to many others There are seven address lines for accessing up to 128 read write registers which are 16 bits wide The read timing for the Intel style bus interface is shown in Figure 9 1 and the write timing is shown in Figure 9 2 The read timing for the Motorola style bus interface is shown in Figure 9 3 and the write timing is shown in Figure 9 4 National Instruments Corporation 9 5 DAQ STC Technical Reference Manual Chapter 9 Bus Interface CS d 7 RD Tads ar Tcs rd gt Tadh gt CS RD N lt 1 7 gt 8850 Tdv Tdi gt D lt 0 15 gt SEEK Figure 9 1 Intel Bus Interface Read Timing CS j WR CS WR lt 1 7 gt D lt 0 15 gt Figure 9 2 Intel Bus Interface Write Timing Table 9 2 Intel Bus Interface Timing Name Description Minimum Maximum Tcs rd CS RD pulsewidth 45 50 Tcs wr CS WR pulsewidth 40 m Tads Address setup time Tadh Address
421. hen the UI counter is active UI control state CNT and false when the UI counter is idle UI control state WAIT UI CLK UI Clock The UI clock signal is the actual clock for the UI counter and the UI control logic When the counter is not armed UI CLK is derived from the write strobe for AO Command 1 Register so that the counter can be loaded using the load command When the counter is armed UI CLK is the same as UI SRC UI DISARM UI Disarm This signal which is generated by the UI control circuit disarms the UI counter by asynchronously clearing AO UI Arm UI LOAD UI Load This signal pulses to load the value from the selected UI load register into the UI counter Related Bitfields Load UI LOAD SRC UI Load Source This signal determines which load register A or B the UI counter will use on the next reload The initial UI load source is set using AO UI Initial Load Source The UI control logic updates UI LOAD SRC while the DAQ STC is counting The current load source depends on the counter state and the selected reload mode Related bitfields UI Initial Load Source AO UI Next Load Source St AO UI Reload Mode UI SRC UI Source The UI source is the timebase for the UI counter It is software selectable from AO IN TIMEBASEI IN TIMEBASE2 PFI lt 0 9 gt and 5 TRIGGER O 6 Related bitfields AO UI Source Select UI TC Update Interval C
422. herwise OUT and OSC or RTSI_OSC are identical 3 7 2 DAQ STC Driven Analog Output Timing The basic analog output functionality provided by the DAQ STC can control the timed updating of up to 16 independent double buffered DACS fed by a single FIFO The primary output signals are UPDATE TMRDACWR lt 0 3 gt TMRDACREQ and AOFREQ and the input signals are AOFFF and AOFEF Figure 3 14 shows the timing for these signals in a basic analog output sequence There are two UPDATE signals shown UPDATE SRC and UPDATE OUT The UPDATE signal can be operated from either the source or output clocks and both are included in the timing diagram When there is data in the FIFO the TMRDACREQ signal is removed and TMRDACWR is asserted The delay will be in clock period increments and an internally synchronized version of the AOFEF enables or disables the generation of the TMRDACWR The UPDATE signal simultaneously transfers the written data to the outputs of all of the DACs DAQ STC Technical Reference Manual 3 86 National Instruments Corporation Chapter 3 Analog Output Timing Control 4 Te set gt Tefhold Pur N f X AX V XC SN XP NX NX NV VN Tcp Toup UPDATE OUT Tsup UPDATE SRC P Tctwr Tetwr P Tctwr Tupwr Tupwr Twr Twr Twr gt TMRDACWR _ Taddr Taddr N Taddr AO ADDR O 3 X X X Tctreq E Treqneg TMRDACREQ
423. hip The only possible error condition is rollover Rollover occurs when the counter attempts to count below 0 underflow or above OxFFFFFF hex overflow When rollover occurs the counter continues counting with the wrap around counter value which is defined to be OxFFFFFF hex for underflow and 0 for overflow The rollover condition can be checked but you can not tell how many rollovers have occurred If your application requires counting that exceeds the capabilities of a single general purpose counter you may decide to use one general purpose counter for normal counting and the other general purpose counter for counting the first counter TC Alternatively you can enable the TC interrupt and use the corresponding interrupt service program to expand the counter width in software You can use the error detection mechanism associated with this interrupt to check for any interrupts not being serviced in time that is the DAQ STC will let you know if your system is unable to keep up with the counting Use the following function to program a counter for simple event counting Program the Source to select the signal on which you want to count events Program the Gate to select the gating signal for simple gated event counting or logic low Function Gi Simple Event Counting Gi_Load_Source_Select 0 Gi_Load_A initial counter value Gi_Load 1 X Gi Source Select 0 IN or 1 through 10 PF
424. his function will be used later in the functions for waveform staging AO Staged ISR and changing the update rate during an output operation AO Rate Change For waveform staging operation we assume that the parameters for each stage are stored in an array defined as follows bc new ticks contains the number buffer iterations in each MISB uc new ticks contains the number of updates in each buffer of the MISB new mute flag indicates whether the MISB will be muted 1 indicates muting Function Counting Begin critical section AO_Configuration_Start 1 Declare variables DAQ STC Technical Reference Manual 3 24 National Instruments Corporation Chapter 3 Analog Output Timing Control last load register indicates which load register was used previously ao tick count to use indicates which parameter in the array should be used If waveform staging then AO_Continuous 1 AO_Mute_A new_mute_flag 0 AO BC Initial Load Source 0 AO Load A bc new ticks 0 1 L AO_BC_Load 1 L AO UC Initial Load Source 0 AO UC Load A new ticks 0 Y AO UC Load 1 L AO Load A uc new ticks 0 1 AO Mute B new mute flag l AO BC Load B new ticks l AO UC Load B new ticks l AO BC Reload Mode 1 AO UC Switch Load Every BC 1 ao tick count to 2 last load register 1
425. his bitfield on BC Load and on BC TC The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related Bitfields BC Next Load Source St AO BC Load National Instruments Corporation 3 47 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 BC Next Load Source St bit 1 type Read in AO Status 2 Register address 6 This bit indicates the next load source of the BC counter 0 Load register 1 Load register B i Note This bit is updated on counter reload 0 BC Q St bit 3 type Read in AO Status 2 Register address 6 This field reflects the state of the BC control circuit 0 WAIT 1 CNT See section 3 8 Detailed Description for more information on the BC control circuit 0 BC Reload Mode bit 1 type Write in AO Mode 2 Register address 39 This bit selects the reload mode for the BC counter 0 No automatic change of the BC load register 1 The BC counter will switch load registers on BC You can use setting 1 in waveform staging to obtain a new buffer repetition count for each MISB 0 BC Save St bit 2 type Read in AO Status 2 Register address 6 This bit indicates the status of the BC save register 0 BC save register is tracing the counter 1 BC save register is latched for later read Related bitfields BC Save Trace 0 BC Save Trace bit 10 type Write in AO Command 2 Register address 5 Se
426. hold time Data valid 12 44 49 Tdi Data invalid 3 10 DAQ STC Technical Reference Manual 9 6 National Instruments Corporation Chapter 9 Table 9 2 Intel Bus Interface Timing Continued Bus Interface Name Description Minimum Maximum Tds Data setup time 25 Tdh Data hold time 0 All timing values are in nanoseconds The numbers in parentheses indicate a 100 pF load all other numbers indicate 15 pF The DAQ STC generates an internal read or write signal based upon the read write and chip select signals at the pins The internal signal will be asserted only when both chip select and the appropriate strobe are asserted shown in these figures as CS RD and CS WR The timing parameters are all relative to the combined signal CS DS CS DS RD WR lt 1 7 gt D lt 0 15 gt N Tads Tadh Trws Tcs ds Trwh lt gt gt E Tdv Tdi i p Figure 9 3 Motorola Bus Interface Read Timing National Instruments Corporation 9 7 DAQ STC Technical Reference Manual Chapter 9 Bus Interface CS N DS Trwh Tads Tcs ds Tdh Tds Trws 4 4 pd gt osos iid RD WR N lt 1 7 gt D lt 0 15 gt Figure 9 4 Motorola Bus Interface Write Timing
427. how to program the RTSI interface The RTM eliminates the need for a RTSI ASIC on the board by providing the equivalent functionality The RTM consists of seven 12 to 1 multiplexers that drive seven RTSI trigger bus signals and four 8 to 1 multiplexers that drive the four RTSI board signals Any of the seven RTSI trigger bus signals can be driven by eight internally generated timing signals and the four RTSI board signals Similarly the four RTSI board signals can be driven by any of the RTSI trigger bus signals 6 2 Features The RTM has the following features e RTSI ASIC cross bar switch type routing capability obviates the need for a RTSI ASIC Eight internal signals can drive any of the seven RTSI trigger lines RTSI trigger bus signals can drive any of the internal trigger or timing signals Four additional bidirectional pins for communication between the RTSI trigger bus and board signals 6 3 Pin Interface The RTSI signals are listed in the following table Pin Type Notation B9TU Bidirectional 9 mA sink 5 mA source tri state pull up 50 National Instruments Corporation 6 1 DAQ STC Technical Reference Manual Chapter 6 RTSI Trigger Table 6 1 Pin Interface Pin Name Type Description RTSI lt 0 6 gt B9TU RTSI Trigger As an input these pins the seven RTSI trigger lines As an output these pins can be driven from 12 signal sources ADR STARTI ADR
428. i Source Select 0 IN 5 or through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 IN TIMEBASE2 or 19 other G TC Gi Source Polarity 0 count rising edges or 1 count falling edges Gi Gate Select 1 through 10 PFI 0 9 or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 AI START2 or 19 UI2 TC or 20 other G TC or 21 AI STARTI or 31 logic low OR Gate 0 Gi Output Polarity 0 active low or 1 active high Gate Select Load Source 0 Gi Gate Polarity 0 disable inversion or 1 enable inversion Gi Output Mode one clock cycle output or 2 toggle on TC or 3 toggle on TC or gate Gi Reload Source Switching 1 Gi Loading On Gate 0 Gi Loading On 1 Gi Gating Mode 2 Gi Gate On Both Edges 0 Gi Trigger Mode For Edge Gate 2 DAQ STC Technical Reference Manual 4 30 National Instruments Corporation Chapter 4 General Purpose Counter Timer Gi Stop Mode 0 Gi Counting Once 0 Gi Up Down 0 Gi Bank Switch Enable 0 disable bank switching or 1 enable bank switching Gi Bank Switch Mode 0 Gi TC Interrupt Enable 0 Gi Gate Interrupt Enable 0 If you set Gi Bank Switch Enable to 1 in the function Continuous Pulse Train Generation you can use this function to change the pulse generation rate while the pulse train is in progress The variable g bank to be used indicates the bank to be use
429. ich selects between UPDATE and UPDATE2 This allows the DAC group to be driven by either the primary or secondary analog output circuitry The output signals DACWRO DACWRI are decoded versions of TMRDACWR and CPUDACWR based on the AO ADDRO line The appropriate DACWRI is driven active during either TMRDACWR or CPUDACWR cycle The DACWRO signal can be configured to ignore the ADDRO line for use with a single DAC package In this option the DACWRO signal will be asserted on every TMRDACWR and CPUDACWR cycle DAQ STC Technical Reference Manual 3 94 National Instruments Corporation Chapter 3 Analog Output Timing Control JU X GE NF AV AV V AV NC NCC INS NU e Xe SN UPDATE LDACO coal Twrld TwrldN Twrld TwrldN Di LDAC1 X Iu LZ x d Ok uf TMRDACWR ZI J N Tascpu gt CPUDACWR Taddr gt Tahcpu ADDRO N N N Tckwr Fu DACWRO X N Tckwr gt TckwrN DACWR1 N N Name Description Minimum Maximum Tupld UPDATE to LDACi asserted 4 TupldN UPDATE to LDACi deasserted 1 5 Twrld CPU TMRDACWR to LDACi asserted 4 0 TwrldN CPU TMRDACWR to LDACi deasserted 4 2 Tckwr OUT CLK to asserted 15 47 TckwrN OUT CLK to DACWRi deasserted 12 37 Taddr TMRDACWR to da addr change 3 10 Tascpu AO ADDR setup to CPUDACWR 3 9
430. idth AO UPDATE Source Select 0 UPDATE Output Select bits lt 0 1 gt type Write in AO_Output_Control_Register address 86 This bitfield enables and selects the polarity of the UPDATE output signal 0 High 7 1 Ground 2 Enable active low 3 Enable active high This bitfield also selects the polarity of the PFIS UPDATE output signal if enabled for output 0 Active low 1 Ground 2 Active low 3 Active high Related bitfields BD_5_Pin_Dir AO_UPDATE_Pulse bit 0 type Strobe in AO Command 1 Register address 9 Setting this bit to 1 produces a pulse on the UPDATE and PFIS UPDATE output signals if the signals are enabled for output and if UPDATE pulses are not blocked UPDATE pulses can be blocked by the external gate or by AO Software Gate The pulsewidth of the output signals is determined by AO UPDATE Pulse Width This bit is cleared automatically Related bitfields UPDATE Output Select AO Software Gate AO UPDATE Pulse Width DAQ STC Technical Reference Manual 3 82 National Instruments Corporation Chapter 3 Analog Output Timing Control UPDATE Pulse Timebase bit 6 type Write in AO Personal Register address 78 This bit determines how the pulsewidth of the UPDATE and PFIS UPDATE signal is selected 0 Selected by AO UPDATE Pulse Width 1 Selected by AO UPDATE Original Pulse Related bitfields AO UPDATE Pulse Width AO UPDATE Original Pulse 0 UPDATE Pulse Width
431. idth Measurement function 4 26 to 4 27 buffered period measurement 4 7 to 4 8 buffered pulse train generation 4 14 buffered pulsewidth measurement 4 9 buffered retriggerable single pulse generation 4 11 to 4 12 buffered semiperiod measurement 4 8 buffered static pulse train generation 4 13 buffers number of primary analog output operation 3 24 to 3 26 bulletin board support E 1 bus interface module 9 1 to 9 8 features 9 1 overview 9 1 pin interface 9 1 to 9 3 programming information 9 3 to 9 5 bitfield descriptions 9 4 to 9 5 write strobes 9 4 timing diagrams 9 5 to 9 8 Intel bus interface read timing figure 9 6 National Instruments Corporation 1 17 Index Intel bus interface timing table 9 6 to 9 7 Intel bus interface write timing figure 9 6 Motorola bus interface read timing figure 9 7 Motorola bus interface timing table 9 8 Motorola bus interface write timing figure 9 8 C channel selection primary analog output operation 3 28 CHRDY IN signal table 9 2 CHRDY OUT signal bus interface table 9 2 CPU driven analog output 3 6 to 3 7 CPU driven analog output timing 3 88 to 3 89 unbuffered data interface timing 3 98 to 3 100 clock distribution 10 2 to 10 3 master slave distribution across RTSI bus figure 10 2 programming 10 10 to 10 11 timebases derived from IN TIMEBASE table 10 2 to 10 3 Clock To Board bit 10 13 Clock To Board Divide 2 bit 10 1
432. idths 2 133 overflow error 2 132 overview 2 1 pin locator interface table 2 19 to 2 23 programming information 2 24 to 2 83 arming 2 41 bitfield descriptions 2 48 to 2 83 board environment setup 2 29 to 2 30 board power up initialization 2 27 to 2 28 changing scan rate during acquisition 2 43 to 2 44 convert signal 2 38 to 2 40 enable interrupts 2 40 to 2 41 end of scan 2 37 to 2 38 FIFO request 2 30 hardware gate programming 2 30 to 2 31 initialize configuration memory output 2 28 to 2 29 interrupts 2 46 to 2 48 master slave operation considerations 2 45 to 2 46 number of scans 2 33 overview 2 25 to 2 26 register and bitfield considerations 2 24 resetting 2 26 to 2 27 sequence of functions for 2 42 single scan 2 42 to 2 43 software gate operation 2 31 staged acquisition 2 44 to 2 45 start of scan 2 34 to 2 37 starting the acquisition 2 41 to 2 42 trigger signals 2 32 to 2 33 windowing registers 2 25 simplified model 2 4 to 2 6 specifications A 1 National Instruments Corporation timing diagrams 2 84 to 2 111 basic analog input timing 2 86 to 2 87 configuration memory 2 89 to 2 01 CONVERT SRC signal 2 84 to 2 85 data FIFOs 2 88 external CONVERT source 2 92 to 2 93 external triggers 2 03 to 2 97 maximum rate analog input 2 9 to 2 92 OUT signal 2 85 SCAN IN PROG deassertion 2 103 signal definitions 2 84 to 2 85 START trigger and SCAN assertion 2
433. ield in this document Register and Bitfield Programming Considerations Several write only registers on the DAQ STC contain bitfields that control a number of functionally independent parts of the chip To follow the instructions for assigning values to bitfields you must set or clear bits without changing the current state of the remaining bits in the register However writing to these registers affects all register bits You cannot read these registers to determine which bits have been set or cleared in the past therefore you should maintain a software copy of the write only registers You can then use this software copy to determine the status of write only registers Because some bitfields get cleared automatically you should keep your software copies current To change the state of a single bitfield without disturbing the remaining bits perform the following steps 1 Make a secondary copy of the software copy 2 Clear the bitfield in the secondary copy 3 Place the new bitfield value in the secondary copy 4 Write the value of the secondary to the register 5 If the bitfield is not cleared automatically update the software copy by replacing it with secondary copy Bitfields that get cleared automatically are called strobe bits To change the state of a bitfield that spans over two registers you need to write to both registers DAQ STC Technical Reference Manual 2 24 National Instruments Corporation Chapter 2 A
434. if Stale Data St was set at any time during an interrupt driven noncumulative event counting or period measurement operation This is useful for after the fact error detection G Read Acknowledges i 0 bit 0 type Write in GO Input Select Register address 36 i 1 bit 0 type Write in G1 Input Select Register address 37 Setting this bit to 1 causes hardware save register accesses to clear Gate Interrupt St and to reset the associated interrupt latency error detection circuitry To select between the high low save register use Little Big Endian Do not set this bit to 1 if Gi Write Acknowledges Irq is set to 1 Related bitfields Gate Interrupt St Gi Little Big Endian Gj Reload Source Switching 0 bit 15 type Write in GO Mode Register address 26 bit 15 type Write in G1 Mode Register address 27 If Gi Gate Select Load Source is set to 0 this bit enables load register selection in the following manner 0 Always use the same load register 1 Alternate between the two load registers Related bitfields Gi Gate Select Load Source Gi Reset i 0 bit 2 type Strobe Joint Reset Register address 72 i 1 bit 3 type Strobe Joint_Reset_Register address 72 Setting this bit to 1 resets the counter clears Gi_Arm and Gi_Arm_Copy clears the GO Mode Register and clears the appropriate bits of the G_Input_Select_Register This bit is cleared automatically DAQ STC Technical R
435. ignal table 9 3 Read Gi HW Save Registers function 4 35 reading counter contents 4 34 hardware save registers 4 34 to 4 35 status lines digital I O 7 13 recommended operating conditions A 2 to A 3 registers B 1 to B 38 address order table B 5 to B 8 alphabetical list table B 1 to B 4 bitfield location guide table B 9 programming considerations 2 24 register maps B 10 to B 38 relative position sensing description 4 6 programming 4 23 to 4 24 Relative Position Sensing function 4 23 to 4 24 Reserved One bit 10 14 RESET signal description table 9 3 testing 10 8 resetting operation analog input timing control module 2 26 to 2 27 analog output timing control module primary analog output operation 3 21 to 3 22 secondary analog output operation 3 38 general purpose counter timer module 4 18 retriggerable single pulse generation 4 11 revision history for DAQ STC D 1 to D 2 RTSI Board Output Select bit 6 4 National Instruments Corporation RTSI Board Pin Dir bit 6 4 RTSI lt 0 3 gt signals table 6 2 RTSI Clock Mode bit 6 4 RTSI OSC signal table 6 2 RTSI Sub Selection 1 bit 6 5 RTSI Trig Output Select bit 6 5 RTSI Trig i Pin Dir bit 6 5 RTSI lt 0 6 gt signals table 6 2 RTSI signals CTRGATE reference pin selection table 4 54 CTRSRC reference pin selection 4 53 external trigger timing 3 102 external UPDATE mode 3 12 master slave trigger 3
436. in AI Personal Register address 77 This bit selects the pulsewidth and assertion time of the EXTMUX output signal 0 Pulsewidth is 4 5 AI OUT TIMEBASE periods EXTMUX trails the LOCALMUX CLK pulse by 0 5 1 5 AI OUT TIMEBASE periods 1 Pulsewidth is equal to the pulsewidth of the LOCALMUX read pulse selected by AI LOCALMUX Pulse Width EXTMUX and LOCALMUX are asserted at the same time Related bitfields AI LOCALMUX CLK Pulse Width DAQ STC Technical Reference Manual 2 56 National Instruments Corporation Chapter 2 Analog Input Timing Control FIFO Empty St bit 12 type Read in AI Status 1 Register address 2 This bit reflects the state of the AIFEF pin after the polarity selection which indicates the AI data FIFO status 0 Notempty 1 Empty Related bitfields FIFO Flags Polarity AI FIFO Flags Polarity bit 8 type Write in AI Personal Register address 77 This bit selects the polarity of the AI data FIFO flags input signals AIFFF AIFHF AIFEF MUXFEF 0 Active low 1 Active high Related bitfields Empty St Full St FIFO Half Full St AI Config Memory Empty St FIFO Full St bit 14 type Read in AI Status 1 Register address 2 This bit reflects the state of the AIFFF pin after the polarity selection which indicates the AI data FIFO status 0 Not full 1 Full Related bitfields FIFO Flag
437. in the buffer If all the points have been written into the buffer then Gi_Disarm 1 buffer done l Gi_Gate_Interrupt_Ack 1 If Gi_Gate_Error_St is 1 then gate acknowledge latency error hardware saves are too fast Inform user that a gate acknowledge latency error has occurred Gi_Gate_Error_Confirm 1 If Gi_TC_St is 1 then rollover error counter value is not correct Inform user that a rollover error has occurred Gi TC Interrupt 1 DAQ STC Technical Reference Manual 4 22 National Instruments Corporation Chapter 4 General Purpose Counter Timer 4 6 1 7 Relative Position Sensing Relative Position Sensing is an application in which a general purpose counter counts the edges of its source signal and the counting direction is controlled by a hardware input or by software The only possible error condition is rollover Rollover occurs when the counter attempts to count below 0 underflow or above OxFFFFFF hex overflow When rollover occurs the counter continues counting with the wrap around counter value which is defined to be OxFFFFFF hex for underflow and 0 for overflow The rollover condition can be checked but you can not tell whether the rollover was caused by underflow or overflow Use this function to program a counter for relative position sensing Program the Source to select the signal on which you want to count events For relative position sensing controlled by
438. in the mute MISB 1 AO_UI_Reload_Mode 7 Else if UPDATE source is the GOUTI signal from general purpose counter 1 then National Instruments Corporation 3 27 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control AO Gate Enable 1 AO UPDATE Source Select 20 AO UPDATE Source Polarity 0 Else external UPDATE mode AO_BC_Gate_Enable 1 AO UPDATE Source Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt AO UPDATE Source Polarity 0 rising edge or 1 falling edge AO_Configuration_End 1 End critical section Another feature provided by the DAQ STC in the external UPDATE mode is the BC_GATE BC Counter Gate The BC_GATE provides a mechanism for blocking the external UPDATE pulses If AO_BC_Gate_Enable is set to 1 the BC_GATE enables the external UPDATE pulses whenever the BC counter is enabled to count and blocks the external UPDATE pulses whenever the BC counter is not enabled to count The BC_GATE must be disabled when internally generated UPDATE pulses are used 3 6 1 7 Channel Select This function lets you update one or more analog output channels If you choose single channel analog output select the channel number If you choose multiple channel analog output you may select how many but channel numbers must be ascending continuously from 0 Function AO_Channels Begin critical section AO Configuration Start
439. in the register bit maps are organized into bitfields A bitfield can contain one or more bits Only bits with contiguous locations within a register can belong to a bitfield The high and low pairs of load and save registers for 24 bit counters are also treated as bitfields The AITM related bitfields are described below Not all bitfields referred to in section 2 6 Programming Information are listed here To locate a particular bitfield description within this manual refer to Appendix B Register Information AI AIFREQ Polarity bit 4 type Write in AI Personal Register address 77 This bit selects the polarity of the AIFREQ output signal 0 Active high 1 Active low AI Analog Trigger Reset bit 14 type Strobe AI Command 1 Register address 8 This bit clears the hysteresis registers in the analog trigger circuit Set this bit to 1 at the time you arm the analog input counters if you want to use analog triggering in hysteresis mode for any analog input signal Before setting this bit to 1 make sure that the analog trigger is not being used by any other part of the DAQ STC You should not set this bit to 1 in any other case This bit is cleared automatically DAQ STC Technical Reference Manual 2 48 National Instruments Corporation Chapter 2 Analog Input Timing Control Configuration End bit 8 type Strobe Joint Reset Register address 72 This bit clears AI Configuration Start which holds the analog input cir
440. ing Control Ts strt1 Ts strt2 Ts strt Ts stop Th 5141 Th strt2 Th strt Th stop SI2 Source N N N START1 N START2 START STOP N Figure 2 23 External Trigger Timing Synchronous Level Internal CONVERT Mode 475 52 475 stop 512 Source Th START1 e Th stri2 Le START2 gt START Th stop g STOP N Figure 2 24 External Trigger Timing Synchronous Edge Internal CONVERT Mode National Instruments Corporation 2 95 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Ts strt1 Ts strt2 Ts stop Th Th stop CONVERT SRC US RE START1 START2 START STOP fe Figure 2 25 External Trigger Timing Synchronous Level External CONVERT Mode 1 siti ii Ts 2 gt 475 qe 1 stop 512 Source VL Tstrt1 lt n START1 eb START2 Tstrt lt gt START p STOP Figure 2 26 External Trigger Timing Synchronous Edge External CONVERT Mode Table 2 5 External Analog Input Timing Name Description Minimum Maximum Ts strtl STARTI setup to CONVERT SRC 33 36 Tstrtl STARTI pulsewidth edge mode 6 Th strt1 STARTI hold from CONVE
441. iod of the signal present on the G_GATE input counting the number of rising edges that occur on G_LSOURCE while G_GATE remains in an active and in an inactive state At the completion of each semiperiod interval for G_GATE the HW save register latches the count value for software read An interrupt notifies the CPU after each semiperiod so that the interrupt software can read the value in the HW save register Figure 4 10 shows three semiperiods of a buffered semiperiod measurement where the first semiperiod is three SOURCE rising edges the second semiperiod is one SOURCE rising edge and the final semiperiod is two SOURCE rising edges Notice that you do not know whether the first value is saved on a rising edge or a falling edge act Lo G SOURCE Counter Value 0 1 2 3 HW Save Register 3 1 2 Figure 4 10 Buffered Semiperiod Measurement DAQ STC Technical Reference Manual 4 8 National Instruments Corporation 4 4 3 Chapter 4 General Purpose Counter Timer 4 4 2 5 Buffered Pulsewidth Measurement Buffered pulsewidth measurement is similar to single pulsewidth measurement except that the measurements are taken over multiple pulses The counter uses G SOURCE to measure the pulsewidth of the signal present on the G_GATE input counting the number of rising edges that occur on SOURCE while G_GATE remains in an active state At the completion of each pulse
442. ion 2 85 analog output timing control module 3 86 OUTBRD OSC signal table 10 10 output control analog output timing control module 3 123 to 3 124 output pin for general purpose counter timer enabling 4 35 OVER DETECT signal 2 86 to 2 87 overrun error analog input timing control module 2 132 analog output timing control module 3 122 National Instruments Corporation P parallel mode digital I O 7 2 to 7 3 parallel input 7 3 parallel output 7 3 programming 7 9 Pass Thru Interrupt Enable bit 8 14 Pass Thru Interrupt Polarity bit 8 14 Pass Thru Interrupt St bit 8 14 Pass Thru Second Irq Enable bit 8 14 pass through interrupt 8 4 to 8 5 Period And Semi Period And Pulse Width Measurement ISR function 4 27 to 4 28 period measurement buffered period measurement 4 7 to 4 8 buffered semiperiod measurement 4 8 CTRSRC minimum period and minimum pulsewidth figure 4 55 programming buffered period semiperiod and pulsewidth measurement 4 26 to 4 28 single period measurement 4 24 to 4 25 PFI module 5 1 to 5 9 bitfield descriptions 5 6 to 5 7 features 5 1 overview 5 1 PFI 0 9 input selections table 5 7 to 5 8 PFI lt 0 9 gt output selections table 5 8 to 5 9 pin interface table 5 2 to 5 5 programming information 5 5 to 5 6 simplified analog input model 2 5 PFI selectors for trigger signals table analog input trigger selection 2 121 analog output trig
443. ion of the UI source clock UI The choices for UI source AO IN TIMEBASEI PFI lt 0 9 gt RTSI lt 0 gt TIMEBASE2 The bitfield AO UI Source Polarity selects the polarity of the source clock The counter load registers are directly accessible from the register map If the counter is disarmed AO UI Load loads the counter with the value from the selected load register During normal operation the UI counter synchronously reloads from the selected load register following TC Several options AO Reload Mode AO UI Switch Load On End AO UI Switch Load On Stop and AO UI Switch Load On TC exist for the UI counter to change the selected load register under various conditions The options are to alternate load registers once after each STOP switch load registers on every STOP alternate load registers once after each switch load registers on every BC TC switch load registers on the next TC switch load registers on the next STOP and switch load registers on the next 1 TC The term alternate load registers refers to the action of having one load from the secondary load register and the remaining loads from the primary load register The UI control circuit generates the count enable signals National Instruments Corporation 3 117 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 3 8 3 2 UI Control The counter is controlled
444. ion presents programming information specific to the GPCT module For general information about programming the DAQ STC see section 2 6 Programming Information Programming for a GPCT Operation This section will give programming sequences you should perform if you want to use the features of the DAQ STC general purpose counters The programming sequences will be developed in a bottom up fashion so that reading this section from the beginning to the end will give you overview of the full functionality of the DAQ STC general purpose counters If you are interested in a specific application you should feel free to skip over parts of the text that you find irrelevant Most of the programming sequences presented here must be executed exactly as shown Bitfield assignment is a pseudocode instruction of the form bitfield name gt value Pseudocode sequences enclosed in braces that contain only bitfield assignments can normally be executed in any order or simultaneously if possible If the sequence must be executed in the exact order the character marks the boundary between two groups of assignments that have to be executed sequentially For example in the following pseudo code the first bitfield assignment must be performed first the second and third assignments may then be executed in any order but the fourth bitfield assignment must be executed after the second and the third bitfield assignments Other programming constructs such as i
445. ird sequence into the unused load registers Switching between load registers occurs at the end of each sequence that is at SC TC This arrangement allows the software a maximum latency of up to the duration of the sequence in progress to finish writing the set of values for the next sequence into the alternate load register set Error detection is provided in case the next parameter set is not written in the allotted time The error detection circuit is armed on each SC TC If a software clear does not occur before the next SC TC error detection circuit latches an SC TC error condition 2 4 3 5 Master Slave Trigger Use master slave triggers whenever you need DAQ devices with multiple DAQ STC ASICs to acquire data in a synchronized manner that is when multiple ASICs share the same STARTI and START triggers With master slave triggering one DAQ STC is designated to be the master trigger ASIC sourcing the STARTI and START triggers to the other ASICs through the PFI lt 0 9 gt or RTSI_TRIGGER lt 0 6 gt interface This arrangement provides better synchronization than if all DAQ STC ASICs receive the same STARTI and START triggers independently because different ASICs may synchronize differently In master slave triggering all DAQ STC AITMs timed from a common source The master ASIC delays recognition of the 5 and 5 2 triggers by one source period to allow the slave ASICs adequate time to receive the triggers
446. irst revision of the DAQ STC and must be set to 0 See Appendix D DAQ STC Revision History for DAQ STC revision information 0 External Gate Polarity bit 3 type Write in AO Output Control Register address 86 This bit selects the polarity of the primary analog output external gate signal 0 Active high high enables operation 1 Active low low enables operation This bit is not supported on the first revision of the DAQ STC and must be set to 0 See Appendix D DAQ STC Revision History for DAQ STC revision information 0 External Gate Select bits lt 10 14 gt type Write in AO Output Control Register address 86 This bit enables and selects the external gate 0 External gate disabled 1 10 PFI lt 0 9 gt 11 17 RTSI lt 0 gt 31 Logic low This bit is not supported on the first revision of the DAQ STC and must be set to 0 See Appendix D DAQ STC Revision History for DAQ STC revision information DAQ STC Technical Reference Manual 3 54 National Instruments Corporation Chapter 3 Analog Output Timing Control 0 External Gate St bit 11 type Read in Joint Status 1 Register address 27 This bit indicates whether the external gate and software gate are set to enable waveform generation 0 Pause analog output operation 1 Enable analog output operation This bit is not supported on the first revision of the DAQ STC See Appendix D DAQ STC Revision History for DAQ ST
447. is bit to 0 clears the bit and takes the DAQ STC out of reset This bit cannot be cleared using windowed mode accesses Software_Test bit 5 type Strobe Analog Trigger Etc Register address 61 Setting this bitto 1 enables the hardware test mode which tri states all the output signals Setting this bit to 1 is equivalent to bringing the TEXT IN pin low DAQ STC Technical Reference Manual 9 4 National Instruments Corporation Chapter 9 Bus Interface Window Address bits lt 0 15 gt type Write in Window Address Register address 0 This bitfield contains the register address for windowed mode accesses To access a register in windowed mode write the address of the register you want to access into this bitfield The register whose address you wrote will be mirrored in the Window Data Read and Window Data Write bitfields Related bitfields Window Data Read Window Data Write Window Data bits lt 0 15 gt type Read in Window Data Register address 1 bits lt 0 15 gt type Write in Window Data Register address 1 Use these bitfields to read or write the value contained in the register whose address is in the Window Address bitfield Related bitfield Window Address Write Strobe 0 bit 0 type Strobe Write Strobe 0 Register address 82 Writing to this register pulses the WRITE STROBEO pin Write Strobe 1 bit 0 type Strobe Write Strobe 1 Register address 83 Writing to this register pulses t
448. is section indicate that OSC is the reference pin with RTSI OSC included in parentheses This indicates that you can use the RTSI Clock Mode to choose between OSC and RTSI_OSC as the reference pin CTRSRC represents the signal that causes the counter to increment or decrement Table 4 1 indicates the pin represented by CTRSRC based on internal selection Table 4 1 CTRSRC Reference Pin Selection Gi Source Select Reference Pin 0 OSC or RTSI OSC 1 10 PFI lt 0 9 gt 11 17 RTSI lt 0 6 gt 18 OSC or RTSI OSC 19 The counter source is selected to be the output of the other general purpose counter The reference is determined by the Source Select bitfield of the other counter To determine delays for this case the source to output delay Tso from the other counter must be added When OSC or 5 OSC is the selected reference the counter is in the internal timing mode In this mode GTRGATE and U D are synchronized to the inactive edge of CTRSRC while the counter changes state on the active edge of CTRSRC When any other pin is the selected reference the counter is in the external timing mode In this mode CTRGATE and are synchronized to the active edge of CTRSRC before it enters a delay gate while the counter changes state on the active edge of CTRSRC after it passes through the delay gate The delay gate is provided so that the signals synchronized t
449. ister address 3 Setting this bit to 1 clears AO UI2 TC Error St This bit is cleared automatically Related bitfields AO UI2 Error St DAQ STC Technical Reference Manual 3 78 National Instruments Corporation Chapter 3 Analog Output Timing Control 0 UI2 TC Error St bit 10 type Read in AO Status 2 Register address 6 This bit indicates the detection of a UI2 TC error 0 No error 1 Error 2 error occurs if AO UI2 TC Interrupt is not set between two UI2 TCs This allows you to detect interrupt latencies and potential problems associated with them To clear this bit set UI2 TC Error Confirm to 1 Related bitfields AO UD TC Interrupt Ack AO UI2 TC Error Confirm 0 12 TC Interrupt Ack bit 6 type Strobe Interrupt Ack Register address 3 Setting this bit to 1 clears AO UI2 TC St and acknowledges the UI2 TC interrupt request in either interrupt bank if the UI2 TC interrupt is enabled This bit is cleared automatically Related bitfields AO UI2 TC St 0 2 TC Interrupt Enable bit 7 type Write in Interrupt Enable Register address 75 This bit enables the UI2 TC interrupt 0 Disabled 1 Enabled UI2 TC interrupts are generated on the trailing edge of UPDATE2 0 2 TC Second Enable bit 7 type Write in Second Enable Register address 76 This bit enables the UI2 TC interrupt in the secondary interrupt bank 0 Disabled 1 Enabled
450. it 11 type Write in Interrupt Enable Register address 75 This bit enables the pass through i interrupt 0 Disabled Enabled Related bitfields Pass Thru Interrupt Polarity Pass Thru Interrupt Polarity 1 0 bit 3 type Write in Interrupt Control Register address 59 bit 2 type Write in Interrupt Control Register address 59 This bit selects the polarity of the IRQ IN input signal 0 Active high 1 Active low Pass Thru Interrupt St i 0 bit 0 type Read in AI Status 1 Register address 2 i i bit 0 type Read in AO Status 1 Register address 3 This bit indicates whether a pass through i interrupt is asserted 0 Interrupt not asserted 1 Interrupt asserted Pass Thru j Second Irq Enable i 0 0 9 type Write in Second A Enable Register address 74 i 1 bit 11 type Write in Second_Irq_B_Enable_Register address 76 This bit enables the pass through i interrupt in the secondary interrupt bank 0 Disabled Enabled Related bitfields Pass Thru Interrupt Polarity DAQ STC Technical Reference Manual 8 14 National Instruments Corporation Chapter 8 Interrupt Control 8 5 Interrupt Conditions Table 8 2 summarizes the DAQ STC interrupts and indicates the condition that causes each interrupt when the interrupt is enabled Table 8 2 Interrupt Condition Summary Interrupt Condition AI FIFO Interrupt Interrupts are generated on the FIFO condition indicated by A
451. its lt 7 11 gt type Write in GO Input Select Register i 1 bits lt 7 11 gt type Write in Input Select Register This bitfield selects the GATE source for general purpose counter i 1 10 PFI lt 0 9 gt 11 17 RTSI lt 0 6 gt 18 The internal analog input signal START2 address 26 address 27 address 74 address 76 address 36 address 37 19 The internal analog output signal 12 TC See UPDATE2 Output Toggle 20 The G TC signal from the other general purpose counter 2 The internal analog input signal STARTI 31 Logic low Related bitfields UPDATE2 Output Toggle DAQ STC Technical Reference Manual 4 40 National Instruments Corporation Chapter 4 General Purpose Counter Timer Gj Gate Select Load Source i 0 01 12 type Write in GO_Input_Select_Register address 36 i 1 bit 12 type Write in Input Select Register address 37 This bit enables the selection of the load register by the counter gate 0 Disabled 1 Enabled When this bit is set to 1 an active gate level selects load register and an inactive gate level selects load register B Also Reload Source Switching is ignored This feature can be used only in conjunction with level gating Related bitfields Gating Mode Gi Reload Source Switching Gi Gate St i 0 bit 2 type Read in Joint Status 1 Register address 27 bit 3 type Read in Joint Status 1 Register address 27
452. iven analog output timing 3 88 to 3 89 DAQ STC driven analog output 3 6 3 86 to 3 88 description table 3 16 local buffer mode timing 3 97 to 3 97 simplified analog output model 3 4 unbuffered data interface 3 11 unbuffered data interface timing 3 08 to 3 100 AO Analog Trigger Reset bit 3 45 AO Enable bit 3 46 Polarity bit 3 46 AO Arming function 3 30 to 3 31 AO BC Arm bit 3 46 AO BC Armed St bit 3 46 AO BC Gate Enable bit 3 46 AO BC Gate St bit 3 47 AO BC Initial Load Source bit 3 47 AO BC Load A bit 3 47 AO BC Load B bit 3 47 AO BC Load bit 3 47 AO Next Load Source bit 3 48 AO BC Q St bit 3 48 AO BC Reload Mode bit 3 48 AO BC Save St bit 3 48 AO Save Trace bit 3 48 AO Save Value bit 3 49 AO Source Select bit 3 49 AO BC Switch Load On TC bit 3 49 AO BC TC Error Confirm bit 3 49 AO BC St bit 3 49 AO TC Interrupt Ack bit 3 50 AO BC TC Interrupt Enable bit 3 50 National Instruments Corporation I 7 Index AO BC TC Second Irq Enable bit 3 50 AO BC TC St bit 3 50 AO BC TC Trigger Error Confirm bit 3 50 AO BC TC Trigger Error St bit 3 51 AO BC Write Switch bit 3 51 AO Board Personalize function 3 23 AO Channels function 3 28 AO Configuration End bit 3 51 AO Configuration Start bit 3 51 AO Continuous bit 3 52 AO Counting function 3 24 to 3 26 AO DACi Update Mode bit 3 52 Delayed
453. l Service the AI START interrupt To clear this interrupt set AI START Interrupt Ack 1 To enable this interrupt set AI START Interrupt Enable 1 DAQ STC Technical Reference Manual 8 8 National Instruments Corporation Chapter 8 Interrupt Control Else done 1 8 4 2 3 Interrupt Group B Interrupt group B contains the following interrupts Analog output error STOP START STARTI BC TC UC TC and FIFO conditions e General purpose counter 1 TC and Gate e Pass through interrupt Pass Through interrupt 1 The following function should be used to service an interrupt generated by group B The same sequence can be applied if the two groups share the interrupt level and the function Shared Level Service is used and if the interrupt level is dedicated to group B Function Service Group B Declare variable done_b done_b 0 While done b is 0 do If Soft Copy AO FIFO Interrupt Enable is 1 then If AO FIFO Request St is 1 then AO FIFO caused the interrupt Service AO FIFO interrupt You cannot explicitly acknowledge a FIFO interrupt You must perform an action external to the DAQ STC in order to clear this interrupt condition Else if Soft Copy Pass Thru 1 Interrupt Enable is 1 then If Pass Thru 1 Interrupt St is 1 then The interrupt was caused by a signal entering the DAQ STC through the IRQ INI pin Service the external interrupt 0 You canno
454. l Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation CVI DAQ STC NI DAQ and RTSI are trademarks of National Instruments Corporation Product and company names mentioned herein are trademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of establish
455. l I O 7 4 to 7 5 hardware controlled serial digital I O 7 10 to 7 12 serial input 7 4 DAQ STC Technical Reference Manual 1 34 serial I O 7 5 serial output 7 4 to 7 5 serial output timing figure 7 16 Service Group A function 8 6 to 8 9 Service Group B function 8 9 to 8 12 Shared Level Service function 8 6 SHIFTIN signal ADC control 2 7 basic analog input timing 2 86 to 2 87 data FIFO control 2 7 data FIFO timing 2 88 description table 2 23 nominal pulsewidths table 2 133 simplified analog input model 2 5 SI counter control circuitry 2 126 to 2 127 description 2 126 SI CE signal description table 2 117 SI counter operation 2 126 SI CLK signal table 2 117 SI DISARM signal 2 126 SI HOLD signal table 2 117 SI LOAD signal description table 2 117 SI counter operation 2 126 SI LOAD SRC signal table 2 117 SI SRC signal table 2 117 SI STARTI signal table 2 117 SI TC signal counter outputs figure 2 105 description table 2 118 external START mode 2 13 internal START mode 2 11 pin interface description table 2 23 SI2 counter control circuitry 2 127 to 2 128 description 2 127 National Instruments Corporation SD CE signal description table 2 116 SD counter operation 2 128 SD CLK signal table 2 116 SD DISARM signal 2 128 50 LOAD signal description table 2 116 SD counter operation 2 128 50 LOAD SRC signal table 2 117 SD SRC signal table 2 117
456. l clock distribution 10 10 to 10 11 FOUT 10 12 windowed mode register access PFI module 5 5 to 5 6 example 7 7 to 7 8 pulse generation for ETS 4 15 National Instruments Corporation 1 31 DAQ STC Technical Reference Manual Index pulse generation functions 4 9 to 4 12 buffered retriggerable single pulse generation 4 11 to 4 12 programming 4 28 to 4 31 retriggerable single pulse generation 4 11 single pulse generation 4 9 to 4 10 single triggered pulse generation 4 10 Pulse Train Generation For ETS function 4 33 to 4 34 pulse train generation functions 4 12 to 4 15 buffered pulse train generation 4 14 buffered static pulse train generation 4 13 continuous pulse train generation 4 12 to 4 13 frequency shifting keying FSK 4 14 to 4 15 programming frequency shifting keying 4 31 to 4 32 pulse and continuous pulse train generation 4 28 to 4 31 pulse generation for ETS 4 33 to 4 34 pulse generation for ETS 4 15 pulsewidth measurement buffered pulsewidth measurement 4 9 CTRSRC minimum period and minimum pulsewidth figure 4 55 G_GATE minimum pulsewidth 4 56 programming buffered period semiperiod and pulsewidth measurement 4 26 to 4 28 single period measurement 4 24 to 4 25 single pulsewidth measurement 4 7 pulsewidths nominal analog input timing control module table 2 133 DAQ STC Technical Reference Manual 1 32 analog output timing control module table 3 124 R RD WR s
457. l is the stop trigger used by the SC counter in the pretrigger mode START2 is software selectable from either polarity of the programmable function inputs and software strobe It can be programmed to be edge or level sensitive and can be synchronized to FSC SRC 5 2 is selected using START2 Select Related bitfields AI START2 Select AI START2 Pulse AI START2 Edge AI START2 Sync DAQ STC Technical Reference Manual 2 118 National Instruments Corporation Chapter 2 Analog Input Timing Control Table 2 9 Internal Signals Continued Signal Description STOP Stop This signal performs two functions In the start stop mode it halts CONVERT generation until the next START This is accomplished by stopping the SI2 counter at the next sample pulse if an internal CONVERT is used or by clearing the STST at the next sample pulse if an external CONVERT is used The STOP signal also serves as an end of scan last channel signal and is used by the SC counter to count scans Related bitfields AI STOP Select AI STOP Pulse AI STOP Edge AI STOP Sync STST GATE Start Stop Gate This signal is used for conditioning the external CONVERT so that CONVERT passes through only between the assertion of START and the assertion of STOP STST_GATE is set by the assertion of START after the SC counter has been armed and triggered and is cleared by the assertion of STOP or when the SC counter retu
458. lated signals in order for their recognition to be valid Notice that this does not take into account the setup or synchronization time for the external signals as covered in section 2 7 7 External Triggers The External Control column is applicable when the signal is originating outside the DAQ STC The DAQ STC minimum and maximum columns apply to the internally generated signals The STARTI trigger is the only trigger in the posttrigger mode and is the first trigger in the pretrigger mode It triggers the acquisition sequence and can be generated by software or by an external pulse refer to AI STARTI Select The software trigger which is caused by setting AI STARTI to 1 generates the correct pulsewidth automatically The external pulse must meet the latch and recognition time parameters that are indicated in section 2 7 7 External Triggers for its selected mode of operation The START trigger enables a particular scan and is generated by either an external signal or the internal signal SI TC refer to AI START Select The SI counter is started by the START trigger and be programmed to count anywhere from 2 to 224 clock periods The external signal must meet the setup and pulsewidth requirements indicated in section 2 7 7 External Triggers in order to guarantee recognition by the AITM The CONVERT output signal causes an actual conversion to occur and can be caused either by an external signal or the internal signal 512 TC inverte
459. lated bitfields DIV Load DIV LOAD DIV Load This signal pulses to load the value from the DIV load register into the DIV counter Related bitfields DIV Load DIV TC Divide Down Counter TC When an external multiplexer is used AI External MUX Present 1 this signal indicates that the desired number of sample pulses for the current channel in the onboard mux gain list has been generated so that LOCALMUX can be asserted to switch to the next channel When an external multiplexer is not being used External MUX Present 0 TC can be used as an internally generated STOP trigger Related bitfields AI External MUX Present EXT DIVTC External Version of DIV_TC This signal is provided as a pulse stretched version of the LOCALMUX CLK signal for use with an external multiplexer The hardware generates EXT DIVTC by synchronizing a delayed version of DIV TC with an internal version of CONVERT EXT GATE External Gate This signal can asynchronously combinatorially gate the CONVERT output on a per scan basis The final scan in a scan sequence cannot be individually gated off The hardware generates GATE by passing the output of the External Gate selector through a circuit that guarantees that the signal does not interrupt a scan in progress Related bitfields External Gate Mode AI External Gate Select AI External Gate St AI Software Gate FSCLK F
460. lds AI FIFO Flags Polarity AI_FIFO_Empty_St AIFFFE IU Data FIFO Full Flag This input is used to generate the FIFO interrupt and the FIFO request signal AIFREQ based on the status of the FIFO The input polarity is selectable and the input state can be directly observed in one of the status registers Source AI data FIFO Related bitfields AI FIFO Flags Polarity AI FIFO Full St AIFHF IU Data FIFO Half full Flag This input generates the FIFO interrupt and the FIFO request signal AIFREQ based on the status of the FIFO The input polarity is selectable and the input state can be directly observed in one of the status registers Source AI data FIFO Related bitfields AI FIFO Flags Polarity AI FIFO Half Full St AI FIFO SHIFTIN O9TU Data FIFO Write Clock This output shifts the ADC data from the ADC into the data FIFO at the end of conversion The AI_FIFO_SHIFTIN pulse is asserted on EOC and remains asserted based on the selected pulsewidth The AI_FIFO_SHIFTIN pulse is inhibited for the conversions that occur when the GHOST signal is active Output polarity is selectable Destination AI data FIFO Options Active Low Active High Related bitfields AI_SHIFTIN_Polarity AI SHIFTIN Pulse Width National Instruments Corporation 2 19 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Table 2 1 Pin Interface Continued Pin Name Type
461. le 4 17 Reload G CONTROL Selections GATE Trigger Loading CONTROL Mode for On Gate Conditioning Edge Gate Selected Reload Mode 0 X X CONTROL does not cause counter reload 1 Level gating X Counter reload occurs G CONTROL transition to ACTIVE state DAQ STC Technical Reference Manual 4 68 National Instruments Corporation Chapter 4 General Purpose Counter Timer Table 4 17 Reload on G CONTROL Selections Continued GATE Trigger Loading CONTROL Mode for On Gate Conditioning Edge Gate Selected Reload Mode 1 Edge gating 0 1 or2 Counter reload occurs on G CONTROL transition to ACTIVE state 1 Edge gating 3 Counter reload occurs on every G CONTROL transition 4 8 7 4 UP DOWN on G CONTROL When Up Downis set to 3 the UP DOWN control is controlled by CONTROL When CONTROLis ACTIVE the counter counts up When CONTROLis INACTIVE the counter counts down 4 8 7 5 Generate Interrupt on G_GATE When Gate Interrupt Enable is set to 1 interrupts are generated based on the following table Interrupts are generated only when a counter is armed Table 4 18 Gate Interrupts CONTROL Gate on Conditioning Both Edges Gate Interrupt Level 0 Interrupt on GATE transition to INACTIVE state Edge gating 0 Interrupt on every G GATE transition to active state Edge gating double edge 1 Interrupt on every G tr
462. ledges Irq i 0 type Write in GO Input Select Register address 36 bit 1 type Write in G1 Input Select Register address 37 Setting this bit to 1 causes load register write accesses to clear Gi St and to reset the associated interrupt latency error detection circuitry To select between the high low load register use Little Big Endian Do not set this bit to 1 if Read Acknowledge is set to 1 Related bitfields St Gi Little Big Endian Gi Write Switch i 0 7 type Write in GO Command Register address 6 bit 7 type Write Command Register address 7 This bit enables the write switch feature of the general purpose counter i load registers Writes to load register A are 0 Unconditionally directed to load register A 1 Directed to the inactive load register GPFO 0 Output Enable bit 14 type Write in Analog Trigger Etc Register address 61 This bit configures OUTO RTSI IO bidirectional pin 0 Input Use this pin to route an external signal to the RTSI TRIGGER bus See RTSI Trig Output Select 1 Output Use GPFO 0 Output Select to select the output signal Related bitfields RTSI Trig Output Select GPFO 0 Output Select National Instruments Corporation 4 51 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer GPFO 0 Output Select bits lt 11 13 gt type Write in Analog Trigger Etc Register address 61 This bit
463. les interrupts request generation on the IRQ OUT pin selected by Interrupt Output Select 0 Disabled 1 Enabled Related bitfields Interrupt Output Select Interrupt B Output Select bit lt 12 14 gt type Write in Interrupt Control Register address 59 This bit selects the output pin OUT O 7 for interrupt group B 0 7 IRQ lt 0 7 gt Interrupt B St bit 15 type Read in AO Status 1 Register address 3 This bit indicates whether an interrupt is asserted in interrupt group B 0 No interrupt asserted 1 At least one interrupt asserted Interrupt Output On 3 Pins bit 1 type Write in Interrupt Control Register address 59 This bit enables output on OUT lines 0 and 1 in addition to the OUT lines specified by Interrupt A Output Select and Interrupt B Output Select when an interrupt request is generated in either group This is useful because of the NuBus interrupt line current drive requirements Additional output on OUTO and pins is 0 Disabled 1 Enabled Interrupt Output Polarity bit 0 type Write in Interrupt Control Register address 59 This bit selects the polarity of the lt 0 7 gt output signals 0 Active high 1 Active low National Instruments Corporation 6 13 DAQ STC Technical Reference Manual Chapter 8 Interrupt Control Pass Thru Interrupt Enable i 0 0 9 type Write in Interrupt Enable Register address 73 i l b
464. lock Diagram An asterisk following a pin name indicates that the default polarity for that pin is active low Refer to Table C 1 for a description of the buffer types Table C 1 DAQ STC Pins in Alphabetical Order Pin Name Pin Number Buffer Type 1 64 ID A2 63 ID A3 62 ID 4 59 ID 5 58 ID A6 57 ID 7 56 ID AI SHIFTIN 132 O9TU AI STOP IN 138 IU5 AI STOP OUT 109 O4TU AIFEF 131 IU AIFFF 129 IU AIFHF 130 IU AIFREQ 13 O4TU ANALOG_TRIG_DRIVE 115 O4TU ANALOG_TRIG_IN_HI 128 IU ANALOG_TRIG_IN_LO 127 IU National Instruments Corporation C 1 DAQ STC Technical Reference Manual Appendix C Pin List Table C 1 DAQ STC Pins in Alphabetical Order Continued Pin Name Pin Number Buffer Type AO ADDRO 148 O4TU AO ADDRI 149 O4TU AO_ADDR2 150 O4TU AO_ADDR3 151 O4TU AOFEF 152 IU AOFFF 154 IU AOFFRT 155 O4TU AOFHF 153 IU AOFREQ 14 O9TU BC TC 105 O4TU CHRDY_IN 39 IU5 CHRDY OUT 74 OD18U CONVERT 141 O9TU CPUDACREQ 17 IU CPUDACWR 147 O4TU CS 68 IU CTRLO 31 O4TU CTRLI 32 O4TU CTRL2 33 O4TU CTRL3 34 O4TU CTRL4 35 O4TU CTRLS 36 O4TU CTRL6 37 O4TU CTRL7 38 O4TU DO 75 B9TU DI 76 B9TU D2 77 9 0 DAQ STC Technical Reference Manual C 2 National Instruments Corporation Appendix C Pin List Table C 1 DAQ STC Pins in Alphab
465. log Trigger Etc Register address 61 This bit enables the DIV TC SC TC SI TC UC TC and BC TC output signals 0 Disabled 1 Enabled Reserved bit 2 type Write in AI Mode 1 Register address 12 This bit is reserved and always has to be set to 1 Slow Internal Time Divide By 2 bit 12 type Write in Clock and FOUT Register address 56 This bit determines whether to divide the IN TIMEBASE2 clock obtained by dividing the IN TIMEBASE clock by 100 by 2 0 No 1 Yes DAQ STC Technical Reference Manual 10 14 National Instruments Corporation Chapter 10 Miscellaneous Functions Slow Internal Timebase bit 11 type Write in Clock and FOUT Register address 56 This bit enables the slow internal clock IN TIMEBASE2 and the clocks used for serial digital output for communication with SCXI SERIAL TIMEBASEB 0 Disabled 1 Enabled National Instruments Corporation 10 15 DAQ STC Technical Reference Manual Specifications Analog Input Analog Output This appendix lists the specifications for the DAQ STC These specifications are typical at 25 Celsius unless otherwise noted Max sampling 10 MS s single channel Max timebase frequency 20 MHz Min timing resolution 50 ns Number of channels Up to 16 Max update 4 MS s single channel Max timebase fr
466. lop to reach the counter control circuits You should normally set this bit to 0 Related bitfields AI START Sync Disarm bit 13 type Strobe AI Command 1 Register address 8 Setting this bitto 1 asynchronously disarms the SC SI SI2 and DIV counters This command should only be used to disarm idle counters To disarm non idle counters use AI Software Reset This bit is cleared automatically Related bitfields Software Reset AI DIV Arm bit 8 type Strobe AI Command 1 Register address 8 This bit arms the DIV counter The counter remains armed and the bit remains set until it is disarmed either by hardware or by setting Disarm to 1 Related bitfields AI DIV Armed St AI Disarm DAQ STC Technical Reference Manual 2 52 National Instruments Corporation Chapter 2 Analog Input Timing Control AI DIV Armed St bit 14 type Read in AI Status 2 Register address 5 This bit indicates whether the DIV counter is armed 0 Disarmed 1 Armed Related bitfields AI DIV Arm AI DIV Load bit 7 type Strobe AI Command 1 Register address 8 If the DIV counter is disarmed this bit loads the DIV counter with the contents of the DIV load register If the DIV counter is armed writing to this bit has no effect This bit is cleared automatically DIV Load A bits lt 0 15 gt type Write in AI DIV Load A Register address 64 This bitfield is the load register for the DIV counter
467. lt 0 1 gt IRQ_OUT lt 0 7 gt ISA ISR National Instruments Corporation Glossary dedicated up down control for the GPCTs dedicated up down control for the GPCTs hardware Hertz interrupt control module TTL input pin pull down 50 kQ input clamp voltage input leakage current Intel Motorola bus interface selection signal interrupt signal GPCT counter T related signal internal update indicator signal slow internal timebase signal input output high level output current low level output current individually programmable polarity general purpose interrupt input signal programmable polarity interrupt output signal Industry Standard Architecture interrupt service program G 7 DAQ STC Technical Reference Manual Glossary L LDAC O 1 LOCALMUX CLK LOCALMUX FFRT LSB MAX MB MHz MIN MIO MISB MSB Mux MUXFEF 0 OSC OUTBRD OSC OUT CLK P PFI DAQ STC Technical Reference Manual G 8 DAC load 0 through 1 configuration FIFI advance clock signal configuration FIFO retransmit signal least significant bit maximum megabytes of memory megahertz minimum multifunction input output Multiple Iterations of a Single Buffer most significant bit multiplexer configuration FIFO empty flag signal oscillator source signal oscillator source signal for output to the board AI OUT TIMEBASE signal programmable function input National Instruments Corporation PFI lt 0
468. lue AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value Appendix B AI SI Save Registers Address 64 15 14 13 N NUR DO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value AI SD Load A Register Address 23 15 14 13 mi N 2 OO AI 512 Load AI 512 Load AI SD Load A AI SI2 Load A AI 512 Load A AI 512 Load AI SI2 Load A AI 512 Load AI 512 Load AI SI2 Load A AI SI2 Load A AI SI2 Load A AI SI2 Load AI SI2 Load A AI SD Load A AI SI2 Load A DAQ STC Technical Reference Manual Register Information Type Read only Type Write only Appendix B Register Information AI SD Load B Register Address 25 Type Write only 15 AI SD Load 14 AI SI2 Load B 13 AI SI2 Load B AI SI2 Load AI SI2 Load B AI 512 Load AI 512 Load AI 512 Load AI SI2 Load B AI 512 Load AI 512 Load AI 512 Load AI SD Load AI SI2 Load B AI SI2 Load AI SI2 Load B N NUR AI START STOP Select Register Address 62 Type Write only 15 AI START Polarity
469. m general purpose counter 1 SW Software strobe TB2 The internal signal IN TIMEBASE2 Cz Note When the analog trigger circuit is enabled the analog trigger signal takes over the PFIO0 slot in the PFI selectors 3 8 2 1 Using Edge Detection Use edge detection whenever a one bit pulse is required but the pulsewidth of the trigger signal cannot be guaranteed Internally generated triggers are automatically the correct width and need not be edge detected Software strobes do not have the correct width and should always be edge detected Edge detection of external signals can usually be performed without affecting the circuit operation 3 8 2 2 Using Synchronization Use synchronization whenever the trigger to clock timing relationship cannot be guaranteed Internally generated triggers automatically have the correct timing and need not be synchronized Software strobes do not have the correct timing and should always be synchronized Synchronization of external signals results in a one half bit synchronization delay 3 8 2 3 Trigger Signals START is the trigger for the waveform generation initiating the output sequence It can be generated by software or by an external pulse STARTI can also be internally conditioned to provide enhanced master slave operation DAQ STC Technical Reference Manual 3 116 National Instruments Corporation Chapter 3 Analog Output Timing Control 3 8 3 Analog Output Counters The UI counter is a 24 bit
470. ments or to comment on our products and manuals The Glossary contains an alphabetical list and description of terms used in this manual including abbreviations acronyms metric prefixes mnemonics and symbols The ndex contains an alphabetical list of key terms and topics in this manual including the page where you can find each one xxiv National Instruments Corporation About This Manual Conventions Used in This Manual lt gt bold bold italic device italic module monospace The following conventions are used in this manual Angle brackets containing numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example lt 0 7 gt stands for ACHO through ACH7 This icon to the left of bold italicized text denotes a note which alerts you to important information This icon to the left of bold italicized text denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash This icon to the left of bold italicized text denotes a warning which advises you of precautions to take to avoid being electrically shocked Bold text denotes the names of menu items or dialog box buttons or options Bold italic text denotes a note caution or warning Device refers to any hardware that contains DAQ STC Italic text denotes emphasis a cross reference or an introduction to a key concept Module refers to
471. ming Clock Distribution to set up your timebase Call 02 Reset 11 National Instruments Corporation 3 41 DAQ STC Technical Reference Manual Chapter 3 3 6 7 Analog Output Timing Control Call 402 Board Personalize Call A02 Hardware Gating Call A02 Counting Call A02 Updating Call A02 Arming Waveform Staging for Secondary Analog Output You can use waveform staging to generate timing for a waveform stage consisting of multiple updates each with a unique update interval The DAQ STC has dual load registers for the UI2 counter so that software can load the parameters for the next update interval during the current update interval To accomplish this program the UI2 TC interrupt to call the AO2 Staged ISR ISR To enable the 12 TC interrupt you must make sure that an interrupt level is dedicated to interrupt group B and that interrupt group is enabled You can program 12 TC Interrupt and interrupt group B as follows Interrupt_B_Output_Select 0 through 7 Interrupt_B_Enable 1 AO_UI2_TC_Interrupt_Enable 1 Interrupts can normally be serviced after some delay commonly referred to as interrupt latency In some cases the interrupt latency may be long enough to cause problems in your waveform stage If the interrupt cannot be serviced during one update interval the DAQ STC will not be programmed properly for the next update interval To avoid this you should keep interrupt latency a
472. mum Tpfi Source to PFI output 9 37 Trtsi Source to RTSI output 11 43 Tbrd Source to BRD output 16 60 timing values are in nanoseconds Figure 3 29 START1 Delays Synchronous Mode Internal UPDATE National Instruments Corporation 3 105 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control In the external UPDATE mode the active edge of UPDATE 5 that recognizes the external trigger generates the output Figure 3 30 shows the propagation delays for STARTI START1 UPDATE SRC 55 c PF16 AO START1 34 Trtsi RTSI TRIGGER O 6 Tbrd RTSI_BRD lt 0 3 gt Name Description Minimum Maximum Tpfi Source to PFI output 9 37 Trtsi Source to RTSI output 11 43 Tbrd Source to BRD output 16 60 AII timing values are in nanoseconds Figure 3 30 START1 Delays Synchronous Mode External UPDATE Asynchronous Mode When you select asynchronous mode for STARTI the external trigger itself generates the rising edge of the output Figure 3 31 shows the propagation delays for STARTI DAQ STC Technical Reference Manual 3 106 National Instruments Corporation Chapter 3 Analog Output Timing Control START1 PF16 AO START RTSI TRIGGER O 6 RTSI_BRD lt 0 3 gt Name Description Minimum Maximum Tpfi Trigger to PFI output 9 34 Trtsi Trigger to RTSI output 11 4
473. n 4 12 to 4 13 frequency shifting keying FSK 4 14 to 4 15 pulse generation for ETS 4 15 time measurement 4 6 to 4 9 buffered period measurement 4 7 to 4 8 buffered pulsewidth measurement 4 9 buffered semiperiod measurement 4 8 single period measurement 4 6 to 4 7 single pulsewidth measurement 4 7 CPUDACREQ signal CPU driven analog output 3 6 to 3 7 CPU driven analog output timing 3 88 to 3 90 DAQ STC and CPU driven analog output timing 3 91 to 3 92 description table 3 17 simplified analog output model 3 4 unbuffered data interface timing 3 98 to 3 100 CPUDACWR signal CPU driven analog output 3 6 to 3 7 CPU driven analog output timing 3 88 to 3 90 description table 3 18 maximum update rate timing 3 101 simplified analog output model 3 4 unbuffered data interface 3 11 National Instruments Corporation 1 19 Index unbuffered data interface timing 3 98 to 3 100 CPU driven analog output 3 6 to 3 7 CPU driven analog output timing 3 88 to 3 90 CS signal table 9 2 U D reference pin selection table 4 54 CTRGATE reference pin selection table 4 54 CTRL O 7 signal table 7 6 CTRSRC signal CTRSRC to CTROUT delay 4 55 to 4 56 minimum period and minimum pulsewidth figure 4 55 reference pin selection table 4 53 customer communication xxvii E 1 to E 2 D D lt 0 15 gt signal table 9 2 DA STIED signal table 3 111 STARTI signal table 3 111 DAC interfa
474. n 2 33 to 2 34 AI OUT TIMEBASE signal table 2 114 AI Output Divide By 2 bit 2 60 AI Overflow St bit 2 60 AI Overrun Mode bit 2 60 AI Overrun St bit 2 60 AI Pre Trigger bit 2 61 AI Reset function 2 26 to 2 27 AI Reset bit 2 61 AI SC Arm bit 2 62 AI SC Armed St bit 2 62 AI SC Gate Enable bit 2 62 AI SC Gate St bit 2 62 AI SC Initial Load Source bit 2 63 AI SC Load A bit 2 63 AI SC Load B bit 2 63 AI SC Load bit 2 63 AI SC Next Load Source St bit 2 63 AI SC Q St bit 2 64 AI SC Reload Mode bit 2 64 AI SC Save St bit 2 64 AI SC Save Trace bit 2 64 AI SC Save Value bit 2 64 AI SC Switch Load TC bit 2 65 AI SC TC Error Confirm bit 2 65 AI SC TC Error St bit 2 65 AI SC TC Interrupt bit 2 65 AI SC TC Interrupt Enable bit 2 65 AI SC TC Output Select bit 2 66 AI SC TC Pulse bit 2 66 AI SC TC Second Enable bit 2 66 DAQ STC Technical Reference Manual 2 AI SC TC St bit 2 66 AI SC Wirite Switch bit 2 66 AI Scan End function 2 37 to 2 38 AI SCAN IN PROG Output Select bit 2 61 AI SCAN IN PROG Pulse bit 2 62 AI Scan In Progress St bit 2 61 AI Scan Start function analog input programming 2 34 to 2 37 single scan programming 2 42 to 2 43 AI SHIFTIN Polarity bit 2 67 AI SHIFTIN Pulse Width bit 2 67 AI SI Armed St bit 2 67 AI SI Count Enabled St bit 2 67 AI SI Initial Load Source bit 2 68 AI SI Load A bit 2 68 AI SI Loa
475. n and end on any two of the GATE edges active inactive or either e HW save register can save the counter value upon the completion of the measurement 4 4 2 1 Single Period Measurement In single period measurement the counter uses G SOURCE to measure the period of the signal present on GATE input The counter counts the number of rising edges that occur on SOURCE between two active edges of G GATE At the completion of the period interval for the HW save register latches the counter value for software read DAQ STC Technical Reference Manual 4 6 National Instruments Corporation Chapter 4 General Purpose Counter Timer Figure 4 7 shows a single period measurement where the period of G_GATE is five SOURCE rising edges GATE SOURCE Counter Value 0 HW Save Register Figure 4 7 Single Period Measurement 4 4 2 2 Single Pulsewidth Measurement In single pulsewidth measurement the counter uses G SOURCE to measure the pulsewidth of the signal present on the G_GATE input The counter counts the number of rising edges that occur on SOURCE while the signal remains in an active state At the completion of the pulsewidth interval for G_GATE the HW save register latches the counter value for software read Figure 4 8 shows a single pulsewidth measurement where the pulsewidth of G_GATE is fiv
476. n mode operates similarly to STARTI trigger The START trigger is ignored until the proper number of pretrigger data points has been taken as indicated by the SC TC signal It is recognized by the current scan if it occurs before the STOP trigger Otherwise the following scan will be the first posttrigger point Therefore all of the scans in the pretrigger buffer will have completed before the assertion of the START2 signal DAQ STC Technical Reference Manual 2 108 National Instruments Corporation Chapter 2 Analog Input Timing Control 2 1 11 External Gating The DAQ STC provides two modes of gating free run and halt gating modes Halt gating mode provides the shortest guaranteed delay from the assertion of the gate to the next CONVERT pulse while free run mode provides deterministic timing for a scan regardless of how many scans were masked off prior to the current scan Gating is controlled by either an external gate signal or a software strobe Timing for the external gate depends on whether you select internal CONVERT or external CONVERT using AI CONVERT Source Select In internal CONVERT mode the external gate is synchronized to the inactive edge of the SD source Figure 2 42 shows the timing for free run gating mode with an internal CONVERT 82 START CONVERT 559 55597 Ses External Ga
477. n of the serial DIO In this case you should program eight instances of this value in the DIO Serial Data Out field before the serial DIO operation begins 1 6 2 3 Software Controlled Serial Digital 1 0 If hardware controlled serial digital I O is not used the EXTSTROBE SDCLK pin be used as a digital output line This enables you to select the direction of the eight DIO lt 0 7 gt pins and the EXTSTROBE SDCLK pin for creating simple digital communication protocols For example you can configure pin DIOO for output and pin DIO4 for input and perform operations similar to the one described in section 7 6 2 2 Hardware Controlled Serial Digital I O To use EXTSTROBE SDCLK pin it this way you must disable hardware control of it by setting the following bitfield DIO HW Serial Enable 0 Use the following function to control the value on the EXTSTROBE SDCLK pin Function DIO Clock Out DIO Software Serial Control 0 for logic low or 1 for logic high 1 6 2 4 Programming the Control Lines Use the following function to set the generic control lines Function 5 Generic Control Control output value Note These are generic control lines Refer to the user manual for your DAQ board or device for information on how these lines are used DAQ STC Technical Reference Manual 7 12 National Instruments Corporation Chapter 7 Digital 1 0 1 6 2 5 Reading the Status Lines Use the following function to
478. n selection table 4 53 CTRSRC to CTROUT delay 4 55 to 4 56 U D reference pin selection table 4 54 minimum pulsewidth 4 56 National Instruments Corporation Generic Status bit 7 15 GHOST signal description table 2 21 simplified analog input model 2 6 Gi Analog Trigger Reset bit 4 35 Arm function 4 18 Gi Arm bit 4 36 Gi Arm Copy bit 4 36 Armed St bit 4 36 Gi Autoincrement bit 4 36 Gi Bank St bit 4 36 Gi Bank Switch Enable bit 4 37 Gi Bank Switch Mode bit 4 37 Gi Bank Switch Start bit 4 37 Gi Buffered Event Counting function 4 21 to 4 22 Gi Counting Once bit 4 37 Gi Counting St bit 4 38 Disarm bit 4 38 Gi Disarm Copy bit 4 38 Gi Gate Error Confirm bit 4 38 Gi Gate Error St bit 4 38 Gi Gate Interrupt Act bit 4 39 Gi Gate Interrupt Enable bit 4 39 Gi Gate Interrupt St bit 4 39 Gi Gate On Both Edges bit 4 39 Gi Gate Polarity bit 4 40 Gi Gate Second Irq Enable bit 4 40 Gate Select bit 4 40 Gate Select Load Source bit 4 41 Gate St bit 4 41 Gi Gating Mode bit 4 41 Gi HW Save St bit 4 42 Gi HW Save Value bit 4 42 Gi Little Big Endian bit 4 42 Load A bit 4 43 Gi Load B bit 4 43 Load bit 4 42 Load Source Select bit 4 43 Gi Loading On Gate bit 4 44 Gi Loading On TC bit 4 44 National Instruments Corporation 1 25 Index Gi_Next_Load_Source_St bit 4 44 Gi_No_Load_Between_Gates_St bit
479. nal CONVERT mode SCAN_IN_PROG is asserted on the first CONVERT of each scan The signal remains asserted until SOC occurs while the internal STOP is active Output polarity is selectable Destination Sample and hold circuit Options Active Low Active High Ground High Z Related bitfields AI SCAN PROG Output Select AI SCAN IN PROG Pulse SC TC O9TU SC Counter TC This signal indicates the end of a data acquisition operation Output polarity is active high Related bitfields Misc Counter TCs Output Enable SHIFTIN O9TU Data Shift Pulse This output sends ADC data over the serial link The serial link transfers data serially across the RTSI bus but is not currently supported The signal is similar to AI_FIFO_SHIFTIN except that its generation is not inhibited by the GHOST signal The SHIFTIN pulse is asserted on EOC and remains asserted based on the selected pulsewidth Output polarity is active low Destination Serial Data Link Related bitfields AI SHIFTIN Pulse Width SI TC O4TU SI Counter TC Signal Output polarity is active high Related bitfields Misc Counter TCs Output Enable SOC IU Start of Conversion This input indicates that a conversion has begun Internally the SOC signal allows the trailing edge of LOCALMUX to occur enables the overrun error detection circuitry to start the overrun detection interval and terminates the SCAN PROG signal when STOP is asserted The inp
480. nal pulsewidth The UPDATE2 signal pulsewidth is 0 3 3 5 AO OUT TIMEBASE periods 1 1 1 5 AO OUT TIMEBASE periods Related bitfields UI2 Pulse Timebase AO UD2 Original Pulse UPDATE Interrupt bit 10 type Strobe Interrupt Ack Register address 3 Setting this bit to 1 clears AO UPDATE St and acknowledges the UPDATE interrupt request in either interrupt bank if the UPDATE interrupt is enable This bit is cleared automatically Related bitfields AO UPDATE St 0 UPDATE Interrupt Enable bit 2 type Write in Interrupt Enable Register address 75 This bit enables the UPDATE interrupt 0 Disabled 1 Enabled UPDATE interrupts are generated on the trailing edge of UPDATE National Instruments Corporation 3 81 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 UPDATE Original Pulse bit 7 type Write in AO Personal Register address 78 If AO UPDATE Pulse Timebase is 1 this bit determines the pulsewidth of the UPDATE signal The pulsewidth of the UPDATE signal is 0 Equal to the pulsewidth of the signal used to generate the UPDATE signal with the maximum pulsewidth determined by UPDATE Pulse Width 1 Equal to the pulsewidth of the signal used to generate the UPDATE signal If you set this bit to 1 external gating for the analog output circuitry except the UI2 counter will not work Related bitfields AO UPDATE Pulse Timebase AO UPDATE Pulse W
481. nalog Input Timing Control 2 6 2 Windowing Registers of the write only and read only registers on the DAQ STC can be addressed in two modes direct mode and windowed mode A particular implementation on a board may use either or both of these modes Direct mode allows direct access to all of the DAQ STC registers The register addresses are calculated by adding the register offset to the base address assigned to the DAQ STC on the particular board The Register Maps section of Appendix B Register Information lists the register offsets Windowed mode allows a smaller address space requirement for the DAQ STC at the expense of requiring more accesses to perform the same task In this mode all DAQ STC register accesses use the Window Address Register and Window Data Register Refer to the 7 6 1 Windowed Mode Register Access Example section of Chapter 7 Digital I O for more information on windowing mode and for an example program Caution When using windowed mode accesses from an interruptable process your application may not function properly if an interrupt occurs between the time that the address is loaded into the Window Address Register and the time that an access is made from the Window Data Register Make sure that the interrupt does not disturb the Window Address Register during this sensitive period disable interrupts during windowed mode accesses or write the interrupt routines so that they do not disturb the contents
482. ncremental delay parameter is 8 bits wide On every other counter TC the counter reloads with the sum of the load register and the 8 bit incremental delay parameter The counter then stops and waits for the next active edge This continues until the software issues a disarm command After each recognized edge of GATE the counter ignores further edges on G GATE until the second counter TC Figure 4 20 shows an example of pulse generation for ETS In this figure the delay from the trigger to the pulse increases after each subsequent G_GATE active edge START G GATE FL U io gu PL i Counter TC 1 1 1 1 1 1 1 1 1 t 1 t 1 i 1 1 1 1 1 1 1 1 1 G OUT D1 D2 D1 AD D3 D1 2AD Figure 4 20 Pulse Generation for ETS National Instruments Corporation 4 15 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 5 Pin Interface The I O pins relevant to the counter timer are listed in the following table Although the PFI lt 0 9 gt and RTSI TRIGGER O 6 pins can be used to input and source GPCT related signals these pins are discussed in Chapter 5 Programmable Function Inputs and Chapter 6 RTSI Trigger and are not listed in this table Pin Type Notation IU TTL input pull down 50 IU TTL input pull up 50 B9TU Bidirectional 9 mA sink 5 mA source tri state pull up 50 O9TU Output 9 mA sink
483. nctionality and their operation differs here The primary output signals are UPDATE TMRDACWR CHRDY OUT CPUDACWR and ADDR O 3 Primary input signals are AOFEF and CPUDACREQ Figure 3 21 shows the timing for this mode DAQ STC Technical Reference Manual 3 98 National Instruments Corporation Chapter 3 Analog Output Timing Control UPDATE OU y XP XU Uf UE XU NC Ne NUNG RP XS XC NS XL Xo Tcupd a UPDATE OUT N SN Tetwr Tlwrd TMRDACWR RT AOFEF CPUDACREQ 5 Treqrdy lp Treqrdy lp CHRDY OUT Treqrdy Twrrdy Twrrdy gt Twrrdy gt Tecwr Tewr Tecwr gt CPUDACWR E N AO ADDR 0 3 X X X X Name Description Minimum Maximum Toup UPDATE OUT pulsewidth 1 3 1 5 3 5 Tcupd OUT CLK to UPDATE OUT deasserted 12 38 Tctwr OUT_CLK to TMRDACWR asserted 11 34 Tlwrd last CPUDACWR to TMRDACWR 2 6 deasserted Treqrdy AOFEF to CHRDY OUT asserted 4 12 Twrrdy CPUDACWR to CHRDY OUT deasserted 4 2 11 5 OUT CLK to CPUDACWR asserted 14 15 43 47 Tcwr CPUDACWR pulsewidth 2 3 2 3 All timing values are in nanoseconds Figure 3 21 Unbuffered Data Interface Timing The numbers in parentheses for DACWR lt 0 1 gt National Instruments Corporation 3 99 DAQ STC Technical Reference Manual Chapter 3 Analog Outpu
484. nd general purpose counting are self contained and independent and can therefore be understood without discussing any specific implementation Analog Input Application Figure 1 1 shows the primary components of an analog input subsystem On an analog input board a sample hold circuit samples the analog value of one or more input channels and an A D converter ADC converts the analog value to a digital value A FIFO then holds the digital data until it can be transferred to the host system memory Analog Channels L ape ocessing Ai aps Sample Hold i pP Mux eae Clock olarity SE diff Hold A Select 5 Clock 5 Retransmit Conii i Convert onfiguration E S FIFO E g S 2 7 host Status Y E DAQ STC Timing Trigger gt Analog Input Timing Control FIFO Status Timing Trigger RTSI Connector Figure 1 1 Analog Input Application The analog channels enter the board through the I O connector as shown at the left of the figure The DAQ STC supplies a hold command to latch the analog values at the sample hold device On boards with multiple input channels a multiplexer selects each channel one at a DAQ STC Technical Reference Manual 1 2 National Instruments Corporation Chapter 1 Introduction time and applies its voltag
485. nd in the WAITI state START1 Polarity bit 15 type Write in AI Trigger Select Register address 63 This bit determines the polarity of the START trigger 0 Active high or rising edge 1 Active low or falling edge You should set this bit to 0 if AI STARTI Select is set to 0 Related bitfields AI STARTI Select START1 Pulse bit 0 type Strobe AI Command 2 Register address 4 Setting this bitto 1 sends a STARTI trigger to the counters if the STARTI software strobe is selected AI STARTI Select is set to 0 This bit is cleared automatically Related bitfields AI STARTI Select National Instruments Corporation 2 77 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control START1 Second Enable bit 1 type Write in Second A Enable Register address 74 This bit enables the STARTI interrupt in the secondary interrupt bank 0 Disabled 1 Enabled The START interrupt is generated on valid STARTI triggers received by the DAQ STC valid START trigger is one that is received while the SC counter is armed and in the WAIT1 state 1 Select bits lt 0 4 gt type Write in AI Trigger Select Register address 63 This bitfield selects the STARTI trigger 0 Bitfield AI STARTI Pulse 1 10 lt 0 9 gt 11 17 RTSI lt 0 gt 18 The internal signal OUT from general purpose counter 0 31 Logic low Related bitfields AI
486. nd workload on your computer system in mind when programming the DAQ STC for waveform staging Although the DAQ STC cannot eliminate the interrupt latency problem it can detect when an excessive delay has occurred Use the following function for servicing the UI2_TC interrupt during waveform staging It is assumed that the parameters for each stage are stored in an array defined as follows ui2_ticks contains the number of clocks between updates In addition the variable ac2_last_load_register keeps track of which load registers should be used and the variable ao2_t ick_count_to_use keeps track of which parameter in the array should be used These variables were first introduced in the AO2_Counting and AO2 Updating functions Function AO2 Staged ISR Declare variable DAQ STC Technical Reference Manual 3 42 National Instruments Corporation Chapter 3 Analog Output Timing Control new ticks Holds the number of clocks between updates ao2 shut down isr Indicates the last UI2 TC in the sequence and the next to the last UI2 TC in the sequence as follows 2 the last UI2 TC 1 the next to the last 2 TC 0 otherwise If 402 shut down isr is 2 then AO UD Arm Disarm 0 Else new ticks 112 ticks ao2 tick count to use If new ticks is 0 ao2 shut down isr ao2 shut down 15 1 Else 2 tick count to use ao2 tick count to 1 If 02 1oad register is A then
487. nerate the FIFO interrupt and the FIFO request signal AOFREQ based on the status of the FIFO The input polarity is selectable and the input state can be directly observed in one of the status registers Source AO data FIFO Related bitfields AO FIFO Flags Polarity AO FIFO Half Full St AOFFRT O4TU Data FIFO Retransmit This active low output instructs the data FIFO to retransmit its contents It is used primarily in the local buffer mode When enabled AOFFRT pulses each time AOFEF indicates a FIFO empty condition Destination AO data FIFO Related bitfields AO_FIFO_Retransmit_Enable AOFREQ O9TU Data FIFO Request This output is a FIFO request signal that indicates that the data FIFO needs to be loaded with output data The AOFREQ signal is generated directly from the data FIFO status flags AOFEF AOFHF and AOFFF The generation conditions are assert on empty FIFO assert on half full or less FIFO assert on less than full FIFO assert on half full or less FIFO deassert on full FIFO Output polarity is selectable Destination DMA Controller or CPU Related bitfields AO_AOFREQ Polarity AO_AOFREQ Enable AO_FIFO_Mode BC_TC O4TU The BC Counter Terminal Count Signal Output polarity is active high Related bitfields Misc_Counter_TCs_Output_Enable National Instruments Corporation 3 17 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control Table 3 1 Pin
488. ng Since many of the timing parameters are defined based on internal signals and the internal signals can be selected from a variety of sources it is convenient to define some global signals that can refer to any one of a number of pins depending on the internal signal selection Some of the tables in this section indicate that OSC is the reference pin with RTSI OSC included in parentheses This indicates that you can use RTSI Clock Mode to choose between OSC and 5 OSC as the reference pin DAQ STC Technical Reference Manual 3 84 National Instruments Corporation Chapter 3 Analog Output Timing Control 3 7 1 1 UPDATE SRC UPDATE SRC represents the signal that causes an UPDATE to be generated Table 3 2 indicates the pin represented by UPDATE SRC based on internal selection Table 3 2 UPDATE SRC Reference Pin Selection AO UPDATE Source Select Reference Pin 0 The UPDATE source is selected to be UI TC The reference pin is determined by AI UI Source Select 1 10 PFI lt 0 9 gt 11 17 lt 0 6 gt 19 The UPDATE source is selected to be the output of general purpose counter 1 The reference pin is determined by Source Select To determine delays for this case the source to output delay Tso from general purpose counter 1 must be added 3 7 1 1 UI2 SRC UI2_SRC represents the signal that clocks the UI2 counter Table 3 3 indicates the represented by UI2 SRC base
489. ng written to AI SC Save The SC save register latch signal deasserts after a rising and then a falling edge of SC SRC following a 0 being written to AI SC Save 2 8 3 2 SC Control The SC counter is controlled by a circuit whose state transitions are shown in Figure 2 49 The SC counter control circuit has four states WAIT1 PCNT WAIT2 and CNT The bitfield AI Pre Trigger determines the sequence of the control circuit When AI Pre Trigger is low the counter simply counts until the scan requirement is fulfilled When AI Pre Trigger is high the counter first satisfies the pretrigger scan requirement before fulfilling the posttrigger scan requirement On power up the counter begins in WAIT1 and remains there until the counter is armed and a STARTI pulse is received If AI Pre Trigger is low the counter moves directly to CNT state If AI Pre Trigger is high the counter moves to PCNT and remains counting until reaching SC fulfilling the pretrigger requirement The control circuit then transitions to WAIT to wait for the START2 signal When START is received the control circuit transitions to CNT and the counter continues to count scans until SC TC When the counting is complete 5 causes the control circuit to return to WAITI The internal signal SCKG affects the count operation of the SC counter When the internal timebase is selected for the SC source AI CONVERT Source Select is set to 0 SCKG becomes the sample interval
490. nic support systems If the information available on these systems does not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers updates and example programs For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information call 512 795 6990 You can access these services at United States 512 794 5422 Up to 14 400 baud 8 data bits 1 stop bit no parity United Kingdom 01635 551422 Up to 9 600 baud 8 data bits 1 stop bit no parity France 01 48 65 15 59 Up to 9 600 baud 8 data bits 1 stop bit no parity Support To access our FTP site log on to our Internet host ftp natinst com aS anonymous and use your Internet address such as joesmith anywhere com as your password The support files and documents are located in the support directories National Instruments Corporation E 1 DAQ STC Technical Reference Manual Fax on Demand Support Fax on Demand is a 24 hour information retrieval system containing a library of documents on a wide range of technical information You can access Fax on Demand from a touch tone telephone a
491. nless the pretrigger acquisition mode is selected In the pretrigger acquisition mode the first SC TC falling edge does not generate an interrupt but subsequent SC TC falling edges do National Instruments Corporation 2 65 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Al SC TC Output Select bits lt 2 3 gt type Write in AI Output Control Register address 60 This bitfield enables and selects polarity for the SC TC output signal 0 HighZ 1 Ground 2 Enable active low 3 Enable active high SC TC Pulse bit 1 type Write in AI Command 1 Register address 8 Set this bit to 1 to begin a pulse on the SC TC output signal if the output is enabled Set this bit to to end the pulse Related bitfields AI SC TC Output Select SC TC Second Irq Enable bit 0 type Write in Second Irq A Enable Register address 74 This bit enables the SC TC interrupt in the secondary interrupt bank 0 Disabled 1 Enabled SC TC interrupts are generated on every SC TC falling edge unless the pretrigger acquisition mode is selected In the pretrigger acquisition mode the first SC TC falling edge does not generate an interrupt but subsequent SC falling edges SC TC St bit 6 type Read in AI Status 1 Register address 2 This bit indicates whether the SC counter has reached TC 0 No 1 Yes You can clear this bit by setting AI SC TC Interrupt to 1 Relat
492. noncumulative mode and cumulative mode In noncumulative mode the counter is reloaded every time its contents are saved due to the gate action In cumulative mode the counter s contents are saved by the gate but the counter keeps counting Noncumulative mode is useful if you are interested in the number of events between two controlling events Cumulative mode is useful if you are interested in monitoring progress in terms of events One interesting application is periodic event count monitoring For example you may be interested in the number of events that happened every second You can do this by programming Gi for buffered event counting and Gj for pulse generation and then using the Gj output as the Gi gate Possible error conditions are rollover gate acknowledge latency error and stale data error in noncumulative mode Rollover is explained in section 4 4 1 1 Simple Event Counting The gate acknowledge latency error occurs if the interrupt service program ISR does not manage to read the value in the HW save register before the next hardware save In noncumulative mode the stale data error occurs if there are two gate edges without an intervening source edge indicating that the gave event was too quick to be measured In cumulative mode the stale data error is ignored because the gate actions do not affect the counter contents so that the HW save register always contains the correct value DAQ STC Technical Reference Manual 4 20
493. nously to the DIO port by writing the output data to the parallel output register The software inputs data asynchronously from the DIO port by reading from the parallel input register Software must perform handshaking to ensure that the data is read and written safely The EXTSTROBE SDCLK output is available for simple handshaking operations DAQ STC Technical Reference Manual 7 2 National Instruments Corporation Chapter 7 Digital 1 0 1 4 1 1 Parallel Input In parallel input mode an external device transfers 8 bit parallel data to the DAQ STC through the DIO lines Typically software configures the external device to place a new data byte on the DIO lines based on EXTSTROBE SDCLK which is under software control The DAQ STC then reads the data lines after each EXTSTROBE SDCLK pulse Figure 7 2 shows a parallel input operation where the external device sends a new data byte on each EXTSTROBE SDCLK falling edge The DAQ STC reads the data bytes 0x55 and Ox AA hex EXTSTROBE SDCLK DIO lt 7 0 gt 0x55 SW READ SW READ Figure 7 2 Parallel Input 1 4 1 2 Parallel Output In parallel output mode the DAQ STC transfers 8 bit parallel data to an external device through the DIO lines Typically the software configures the external device to read a new data byte based on EXTSTROBE SDCLK which is under software control The software then updates the DIO lines between each EXTSTROBE SD
494. nput Timing Control STOP is used to end the conversion pulse sequence when the number of channels has been reached For low end applications the DIV counter generates STOP For high end applications the configuration FIFO provides STOP AI STOP Sync AI STOP Edge and AI STOP Polarity are the options for selection of STOP synchronization edge detection and polarity When externally generated STOP should be synchronized unless it is sourced from another DAQ STC operating from the same source clock and timing can be guaranteed STOP is used by the SC counter and is therefore synchronized to SC SRC Analog Input Counters The SI counter is a 24 bit binary down counter that generates scan interval timing START pulses when you select internal START When you select external START the SI counter can enforce a minimum delay from START to the first recognized START SI2 counter is a 16 bit binary down counter that generates sample interval timing CONVERT pulses when you select internal CONVERT When you select external CONVERT the SI2 counter is unused The SC counter is a 24 bit binary down counter that counts scans when a predetermined number of scans is to be generated The SI counter alternate first period reload modes provide a retriggerable method to obtain a delay between STARTI and START that is different from the scan interval Software stores the scan interval in SI load register B and the delay from START in SI load register
495. nt Counting 4 74 4 8 11 4 Buffered Cumulative Event Counting 4 74 4 8 11 5 Relative Position Sensing esee 4 75 4 8 11 6 Single Period Measurement 4 76 4 8 11 7 Single Pulsewidth Measurement 4 77 4 8 11 8 Buffered Period Measurement sess 4 78 4 8 11 9 Buffered Semiperiod Measurement 4 79 4 8 11 10 Buffered Pulsewidth Measurement 4 80 48 11 11 Single Pulse Generation eee 4 81 4 8 11 12 Single Triggered Pulse Generation 4 82 4 8 11 13 Retriggerable Single Pulse Generation 4 83 4 8 11 14 Continuous Pulse Train Generation 4 84 4 8 11 15 Buffered Pulse Train Generation 4 85 4 8 11 16 Frequency Shift 4 86 4 8 11 17 Pulse Generation for ETS see 4 87 Chapter 5 Programmable Function Inputs 31 OyervieWwiuc sss neei opponi i Ania sing nb 5 1 52 Features C EE 5 1 5 3 Pinlnterface eere 5 2 5 4 Programming Information 5 5 5 4 1 Programming the PFI Pins 2 0 5 5 5 4 2 4 sienien eisite ieee 5 6 9 5 Detailed Description eise oie nee pe tei tp HE 5 7 Chapter 6 RTSI Trigger 6 1 LOTES 6 1 6
496. nter Load X3X2 X1 XoX2X XoX 4 Counter Value 4 Counter TC G OUT Figure 4 42 Single Pulse Generation National Instruments Corporation 4 81 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 8 11 12 Single Triggered Pulse Generation To use this function set G CONTROL conditioning to edge gating and program the counter to reload on TC stop at the second TC and count once The rising edge of GATE is synchronized by the falling edge of G SOURCE to generate a G CONTROL pulse The counter begins decrementing after the CONTROL pulse Once the counter TC is reached the counter reloads and counts down to TC again On the second counter TC the counter disarms The load select signal indicates whether the reload occurs from load register A or B Figure 4 43 shows an example of single triggered pulse generation with a pulse delay of five and a pulsewidth of three The dotted line indicates where the ARM occurs G SOURCE G GATE G CONTROL Load Select Counter Load Counter Value Counter TC G OUT A EN o Figure 4 43 Single Triggered Pulse Generation DAQ STC Technical Reference Manual 4 82 National Instruments Corporation Chapter 4 General Purpose Counter Timer 4 8 11
497. nterface Table 9 1 Pin Interface Continued Pin Name Type Description RD WR IU In Intel mode RD WR RD This is an active low input p signal indicating a read bus cycle from the host system so that the DAQ STC will drive the data bus In Motorola mode RD WR R W This is a read write input signal indicating that the current bus cycle is a read high or write low cycle The mode is set using the INTEL MOTO pin Source CPU bus RESET IU Reset This is an active low signal that resets the DAQ STC during initialization Related bitfields Software_Reset WR DS IU In Intel mode WR DS WR This is an active low input signal that indicates that the current bus cycle is a write cycle and that the CPU has placed valid data on the data bus In Motorola mode WR DS DS This is an active low input signal that indicates that the DAQ STC should drive the data bus during a read cycle and that the CPU has placed valid data on the data bus during a write cycle Source CPU bus The mode is set using the INTEL MOTO pin WRITE_STROBE lt 0 3 gt 04TU Write Strobe These pins serve as general purpose write strobes These could be used to simplify adding board level control registers or as clear strobes for the various FIFOs Related bitfields Write Strobe 0 Write Strobe 1 Write Strobe 2 Write Strobe 3 9 4 Programming Information This section presents programming information t
498. nterrupt Group A SEC IRQ OUT BANKI OD18U Secondary Interrupt Output for Interrupt Group B DAQ STC Technical Reference Manual 8 2 National Instruments Corporation Chapter 8 Interrupt Control 8 4 Programming Information This section presents programming information that is specific to the ICM For general information about programming the DAQ STC see section 2 6 Programming Information 8 4 1 Programming the Interrupt Interface This section contains detailed programming information for users who need to do bit level programming of the interrupt interface for specialized applications The DAQ STC can be used as an interrupt management device The DAQ STC can generate interrupts on up to 18 internal conditions and can propagate two externally generated interrupts Ten pins are provided for the interrupt interface pins IRQ_OUT lt 0 7 gt can be used for interrupt assertion and pins IRQ_IN lt 0 1 gt can be used for interrupt propagation Interrupts on the DAQ STC are divided into groups A and B Details are provided in section 8 4 2 Interrupt Handling 8 4 1 1 Interrupt Output Polarity Use the following function to select the logic level that will indicate an interrupt condition on the IRQ OUT pins and to indicate whether you want the selected interrupt to be duplicated on IRQ_OUT lt 0 1 gt pins Function MSC IRQ Personality Interrupt_Output_Polarity 0 for active high or 1 for active low
499. nting The hardware control signals UP DOWN O 1 are ignored 1 Software elected up counting The hardware control signals G_UP_DOWN lt 0 1 gt are ignored 2 The UP DOWNi pin controls the direction of counting Down counting on low level and up counting on high level 3 signal controls the direction GATE is ACTIVE count up G GATE is INACTIVE count down 4 8 5 G OUT Conditioning and Routing Table 4 10 lists the conditioning available for the counter output signal OUT Table 4 10 G OUT Mode Gi Output Mode Description 1 TC Mode The actual counter TC signal appears G OUT 2 Toggle Output on TC Mode OUT changes state on the trailing edge of counter TC 3 Toggle Output on TC or Gate Mode OUT changes state on the trailing edge of counter TC and on GATE transitions to ACTIVE The Gi Output Polarity bits further condition the output signal OUT as shown in Table 4 11 Table 4 11 G OUT Polarity Gi Output Polarity Description 0 Active high Output is normally low 1 Active low Output is normally high National Instruments Corporation 4 65 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer The TC related output signal OUT routing is not symmetrical for the two counters Both counter outputs are available on PFI lt 0 9 gt The output of only one counter counte
500. ntinued Pin Name Pin Number Buffer Type LDAC 0 123 O4TU LDAC 1 125 O4TU LOCALMUX_CLK 136 O4TU LOCALMUX_FFRT 133 O9TU MUXFEF 137 IU OSC 19 IS OUTBRD_OSC 22 O9TU PFIO AI STARTI 99 B9TU START2 98 B9TU PFI2 CONV 97 B9TU PFI3 G_SRC1 96 B9TU PFI4 G GATEI 95 B9TU PFIS UPDATE 93 B9TU PFI6 AO_START1 92 B9TU PFI7 AI START 9 B9TU PFI8 G_SRCO 90 B9TU PFI9 G GATEO 89 B9TU RD WR 65 IU RESET 61 IU RTSI BRDO 9 B9TU RTSI BRDI 10 B9TU RTSI BRD2 11 B9TU RTSI BRD3 12 B9TU RTSI OSC 18 B9TU RTSI TRIGGERO 2 B9TU RTSI TRIGGERI 3 B9TU RTSI TRIGGER2 4 B9TU National Instruments Corporation C 5 DAQ STC Technical Reference Manual Appendix C Pin List Table C 1 DAQ STC Pins in Alphabetical Order Continued Pin Name Pin Number Buffer Type RTSI TRIGGER3 5 B9TU RTSI_TRIGGER4 6 B9TU RTSI TRIGGER5 7 9 0 RTSI TRIGGER6 8 B9TU SC TC 86 O9TU SCAN IN PROG 139 04TU SEC IRQ OUT BANKO 15 OD18U SEC IRQ OUT BANKI 16 OD18U SHIFTIN 143 O9TU SI TC 118 O4TU SOC 134 IU STATUSO 23 ID STATUS1 24 ID STATUS2 25 ID STATUS3 26 ID TEST_IN 102 IU5 TEST OUT 69 09 TMRDACREQ 156 O9TU TMRDACWR 146 O4TU UC_TC 106 O4TU UPDATE 144 O9TU UPDATE2 145 O9TU VCC 1 VCC 20 VCC 40 VCC 81 VCC 100 DAQ STC Technical Ref
501. nts Corporation 4 49 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer G TC Interrupt Enable i 0 6 type Write in Interrupt Enable Register address 73 i l bit 9 type Write in Interrupt Enable Register address 75 This bit enables the TC interrupt 0 Disabled 1 Enabled The TC interrupt occurs on the rising edge of the counter TC Gj TC Second Irq Enable i 0 bit 6 type Write in Second Enable Register address 74 i l bit 9 type Write in Second Irq B Enable Register address 76 This bit enables the TC interrupt in the secondary interrupt bank 0 Disabled Enabled The TC interrupt occurs on the rising edge of the counter TC Gi TC St 1 0 bit 3 type Read in AI Status 1 Register address 2 i l bit 3 type Read in AO Status 1 Register address 3 This bit indicates whether general purpose counter i has reached TC 0 No 1 Yes You can use this bit for overflow detection in some applications This bit is cleared by setting Gi TC Interrupt to 1 Related bitfields TC Interrupt Refer to Table 8 2 Interrupt Condition Summary for more information Gi Trigger Mode For Edge Gate i 0 bits 3 4 type Write in GO Mode Register address 26 i l bits lt 3 4 gt type Write in G1 Mode Register address 27 This bit selects the triggering mode if gating is not disabled 0 The first gate edge starts the next stops the counting The
502. o the early version of CTRSRC have sufficient time to settle to a known state before being used by the counter National Instruments Corporation 4 58 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer CTRGATE represents the signal that gates the counting operation of the counter Table 4 2 indicates the pin represented by CTRGATE based on internal selection Table 4 2 CTRGATE Reference Pin Selection Gi Gate Select Reference Pin PFI lt 0 9 gt lt 0 6 gt The counter gate is selected to be AI 5 2 The reference is determined by AO START2 Select To determine delays for this case the source to AO START2 delay must be added 19 The counter gate is selected to be UI2 TC The reference pin is determined by AO UD Source Select To determine delays for this case the UI2 source to TC delay must be added 20 The counter gate is selected to be the output of the other general purpose counter The reference pin is determined by the Source Select bitfield of the other counter To determine delays for this case the source to output delay Tso from the other counter must be added 21 The counter gate is selected to be AI STARTI The reference pin is determined by STARTI Select To determine delays for this case the source to AO STARTI delay must be added U D represents the signal that causes the counter to co
503. o 1 this bit selects whether IN TIMEBASE as selected by the RTSI Clock Mode bitfield will be divided by 2 when it is fed to the board through the OUTBRD OSC pin 0 Do not divide by 2 1 Divide by 2 FOUT Divider bits lt 0 3 gt type Write in Clock and FOUT Register address 56 This bit selects the divide ratio for the FOUT output signal 0 Divide by 16 FOUT FOUT TIMEBASE divided by 16 1 15 Divide by 1 15 FOUT TIMEBASE divided by 1 15 Related bitfields FOUT Timebase Select FOUT Enable National Instruments Corporation 10 13 DAQ STC Technical Reference Manual Chapter 10 Miscellaneous Functions FOUT Enable bit 15 type Write in Clock and FOUT Register address 56 Setting this bit to 1 enables and starts frequency output 0 Disabled 1 Enabled To change the frequency divider value first clear this bit then change FOUT Divider and set this bit again If this bit is clear FOUT is disabled and output is in the high impedance state FOUT Timebase Select bit 14 type Write in Clock and FOUT Register address 56 This bit selects the timebase used for FOUT that is FOUT_TIMEBASE 0 FOUT TIMEBASE IN TIMEBASE if Slow Internal Time Divide By 2150 FOUT TIMEBASE IN 2 if Slow Internal Time Divide By 2 is 1 1 FOUT TIMEBASE IN TIMEBASE2 Related bitfield Slow Internal Time Divide By 2 Misc Counter TCs Output Enable bit 6 type Write in Ana
504. o 1 clears AO START St and acknowledges the START interrupt in either interrupt bank if the START interrupt is enabled This bit is cleared automatically This bitfield is not currently supported National Instruments Corporation 3 61 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 START Interrupt Enable bit 3 type Write in Interrupt Enable Register address 75 This bit enables the START interrupt 0 Disabled Enabled This bit is currently not supported and it must be set to 0 0 START Polarity bit 13 type Write in AO START Select Register address 66 This bit determines the polarity of the START trigger 0 Active high or rising edge 1 Active low or falling edge This bit is currently not supported and it must be set to 0 0 START Pulse bit 14 type Strobe AO Command 1 Register address 9 Setting this bit to 1 sends a START trigger to the counters if the START software strobe is selected START Select is set to 0 This bit is cleared automatically This bitfield is currently not supported and it must be set to 0 Related bitfields AO START Select 0 START Second Irq Enable bit 3 type Write in Second Enable Register address 76 This bit enables the START interrupt in the secondary interrupt bank 0 Disabled 1 Enabled This bit is currently not supported and it must be set to 0 0 START Select bits lt 0 4 gt type Write in
505. o enable and configure the serial I O This function needs to be called only once Function DIO HW Serial Configure DIO_Serial_Out_Divide_By_2 0 do not divide by 2 or 1 divide by 2 DIO HW Serial Timebase 0 1 2 us clock or 1 10 ps clock DIO HW Serial Enable 1 Use the following function to initiate a serial transfer Function DIO HW Serial Initialize If DIO Serial IO In Progress St is 1 then DAQ STC Technical Reference Manual 7 10 National Instruments Corporation Chapter 7 Digital 1 0 Serial I O is already in progress Cannot start now Notify user that serial I O is already in progress Else DIO_Serial_IO_In_Progress_St indicates when the first seven bits of serial I O is in progress A timed delay is necessary to allow the last bit to be transferred Delay DIO HW Serial Start 1 Use the following function to read the data that has been input on the serial digital input Use DIO Serial IO In Progress St and a delay to verify that the transfer is complete Function DIO Serial In 4 s t v and x are all binary digits corresponding to logic values input on the DIO4 pin so that grstuvwx is an eight digit binary number The logic value q will correspond to the first bit and x will correspond to the last bit input on pin DIO4 qrstuvwx DIO Serial Data In St Function Serial DIO Serial DIO Output Call DIO_Serial_Data_Out
506. o take place simultaneously on separate lines In serial I O mode the DAQ STC inputs data on the DIO4 SDIN line and outputs data on the DIO0 SDOUT line Software configures the external device that is sending data as described in section 7 4 2 1 Serial Input and configures the external device that is receiving data as described in section 7 4 2 2 Serial Output Each 8 bit transfer is initiated under software control Figure 7 6 shows a serial I O operation where the DAQ STC simultaneously reads the data byte 0x4B hex and outputs the data byte 0x97 hex SW START EXTSTROBE SDCLK DIO4 SDIN Read Locations R R R R R R R R DIO0 SDOUT Figure 7 6 Serial 1 0 National Instruments Corporation 7 5 DAQ STC Technical Reference Manual Chapter 7 Digital 1 0 7 5 Pin Interface The I O signals relevant to the DIO module are listed in the following table Pin Type Notation ID O4TU B18TU O9TU TTL input pull down 50 Output 4 mA sink 2 5 mA source tri state pull up 50 kQ Bidirectional 24 mA sink 13 mA source tri state pull up 50 kQ Output 9 mA sink 5 mA source tri state pull up 50 kQ Table 7 1 Pin Interface Pin Name Type Description CTRL lt 0 7 gt O4TU Control lt 0 7 gt These pins serve as general purpose write strobes These could be used to simplify adding board level control r
507. oad A AI SI Load A AI SI Load A AI SI Load A AI SI Load A DAQ STC Technical Reference Manual B 14 NUR 5 HN 9 NW gt tA AI SI Load Registers Address 14 Type Write only Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AI SI Load A AI SI Load A AI SI Load A AI SI Load A AI SI Load A AI SI Load A AI SI Load A AI SI Load A AI SI Load B Registers Address 16 Type Write only Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B National Instruments Corporation AI SI Load B Registers Address 17 15 14 13 N Type Write only AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Load B AI SI Save Registers Address 65 15 14 13 N _ National Instruments Corporation Type Read only AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Value AI SI Save Va
508. ocalMuxClk or 5 SCAN IN PROG From START to last SOC EXTSTROBE Eight cyles of 1 2 us or 10 us software toggle LOCALMUX FFRT 1 National Instruments Corporation 2 133 DAQ STC Technical Reference Manual Analog Output Timing Control 3 1 Overview This chapter describes the analog output timing control module AOTM which generates timing for the DACs and controls signals for the associated circuitry such as the data FIFO buffers Two independent update groups primary and secondary are supported The primary update group is fully supported by hardware and the secondary update group is supported through interrupt software The primary update group contains a 24 bit update interval counter UD a 24 bit update counter UC a 24 bit buffer repetition counter BC and a 4 bit channel address counter CHADDR The UI counter determines the update interval The UC counter counts the primary UPDATE pulses controlling the size of the buffer output The BC counter controls the number of times a buffer is generated The CHADDR counter generates successive DAC addresses in multiple channel update mode It also controls the number of DAC writes generated in an update cycle The secondary update group contains a 16 bit secondary update interval counter UI2 which generates an independent update interval clock The secondary update group does not have additional counters such as the update and buffer repetition coun
509. ode using AI STOP Sync National Instruments Corporation 2 103 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Synchronous Mode In synchronous mode the STOP outputs change on the CONVERT source edge following a change in the external trigger Figure 2 36 shows the behavior of the STOP output in synchronous mode STOP wiw o CONVERT sRC __ Tstop Tstop AI STOP OUT Tbrd Tbrd RTSI_BRD lt 0 1 gt Name Description Minimum Maximum Tstop CONVERT_SRC to AI STOP OUT 12 44 Tbrd CONVERT SRC to BRD output 12 45 timing values are in nanoseconds Figure 2 36 STOP Delay Synchronous Mode Asynchronous Mode In asynchronous mode the STOP outputs follow the external trigger Figure 2 37 shows the behavior of the STOP outputs in asynchronous mode stop 11 N Tstst Tstst STOP OUT Tbrd Tbrd RTSI BRD O 1 Name Description Minimum Maximum Tstst STOP to AI STOP OUT 9 3 Tbrd STOP to BRD output 10 33 timing values are in nanoseconds Figure 2 37 STOP Delay Asynchronous Mode DAQ STC Technical Reference Manual 2 104 National Instruments Corporation Chapter 2 Analog Input Timing Control 2 7 9 Counter Outputs You can output the internal counter TC signals to the board This section presents the output timing for
510. ode and buffered mode In single mode the functions obtain only one measurement In buffered mode the functions obtain a series of consecutive gap free measurements You can select the GPCT input signals from any of the 17 external timing I O pins on the DAQ STC Ten of these PFI lines are user programmable I O pins and are available on the I O connector of the MIO E Series boards The remaining seven of the external timing I O pins connect to the RTSI bus Refer to Chapter 5 Programmable Function Inputs and Chapter 6 RTSI Trigger for more information on the timing I O pins The two counters are identical except for the internal routing of the counter outputs Refer to section 4 8 Detailed Description for more information on the routing of the counter outputs Programming the GPCT To program the GPCT module of the DAQ STC read sections 4 2 Features through 4 6 Programming Information As you read the Programming Information section you will need to refer to section 4 7 Timing Diagrams You will also need to consult the register level programmer manual for the hardware containing the DAQ STC Features The GPCT module has the following features e Two independent 24 bit binary up down counters e Count up count down control via hardware or software e Programmable counter source and gate selection from 17 signal sources National Instruments Corporation 4 1 DAQ STC Technical Reference Manual Chapter 4 General Purpos
511. of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products DAQ hardware revision Interrupt level of hardware DMA channels of hardware Base I O address of hardware Programming choice HiQ NI DAQ LabVIEW or LabWindows version Other boards in system Base I O address of other boards DMA channels of other boards Interrupt level of other boards Other Products Computer make and model Microprocessor Clock frequency or speed Type of video board installed Operating system version Operating system mode Programming language Programming language version Other boards in system Base I O address of other boards DMA channels of other boards Interrupt level of other boards Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title DAQ STC Technical Reference Manual Edition Date January 1999 Part Number 340934B 01 Please comment on the completeness clarity and organization of the manual
512. of the Window Address Register 2 6 3 Programming for an Analog Input Operation This section contains detailed programming information for bit level programming of the AITM for specialized applications The programs are presented in a bottom up fashion This section lists functions that can be used to configure the AITM for various operations The functions are then assembled into a complete program in section 2 6 3 16 Analog Input Program Most of the programming sequences presented here must be executed exactly as shown Bitfield assignments are defined as pseudocode instructions of the form lt bitfield name value Pseudocode sequences enclosed in braces that contain only bitfield assignments can normally be executed in any order or simultaneously if possible If the sequence must be executed in exact order the character marks the boundary between two groups of assignments that have to be executed sequentially For example in the following pseudocode the first bitfield assignment must be performed first the second and third assignments may then be executed in any order but the fourth bitfield assignment must be executed after the second and third bitfield assignments Other programming constructs such as if then should be executed in the order shown National Instruments Corporation 2 25 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control FOUT Enable 0 L FOUT_Timebase_Select 0 FOUT_IN_T
513. ognition of the STARTI trigger 0 Enabled 1 Disabled You should use this bit if you want the same STARTI trigger to start several activities First disable STARTI by setting this bit to 1 do the necessary programming on all DAQ STCs then enable STARTI by setting this bit to 0 National Instruments Corporation 3 63 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control START1 Edge bit 5 type Write in AO Trigger Select Register address 67 This bit enables edge detection of the STARTI trigger 0 Disabled 1 Enabled This bit should normally be set to 1 Set this bit to 1 if AO STARTI Select is O Set this bit to 0 if the ASIC is a STARTI slave to another DAQ STC START1 Interrupt bit 9 type Strobe Interrupt Register address 3 Setting this bitto 1 clears AO STARTI St and acknowledges the STARTI interrupt request in either interrupt bank if the STARTI interrupt is enabled This bit is cleared automatically Released bitfields AO STARTI St START1 Interrupt Enable bit 1 type Write in Interrupt Enable Register address 75 This bit enables the STARTI interrupt 0 Disabled Enabled The STARTI interrupt is generated on valid STARTI triggers received by the DAQ STC A valid START trigger is one that is received while the BC counter is armed and in the WAIT state START1 Polarity bit 13 type Write in AO Trigger Select Registe
514. olarity 8 14 Pass Thru Interrupt St 8 14 Pass Thru Second Enable 8 14 miscellaneous functions 10 12 to 10 15 Analog Trigger Drive 10 12 Analog Trigger Enable 10 13 Analog Trigger Mode 10 13 Clock To Board 10 13 Clock To Board Divide By 2 10 13 FOUT Divider 10 13 FOUT Enable 10 14 FOUT Timebase Select 10 14 Misc Counter TCs Output Enable 10 14 Reserved One 10 14 Slow Internal Time Divide By 2 10 14 Slow Internal Timebase 10 15 PFI module 5 6 to 5 7 BD i Pin Dir 5 7 RTSI trigger module 6 3 to 6 5 RTSI Board Output Select 6 4 RTSI Board Pin Dir 6 4 RTSI Clock Mode 6 4 RTSI Sub Selection 1 6 5 RTSI Trig Output Select 6 5 RTSI Trig Pin Dir 6 5 bitfields analog input programming considerations 2 24 guide to location in manual table B 9 block diagram for DAQ STC 1 4 National Instruments Corporation board environment setup analog input programming 2 29 to 2 30 board power up initialization analog input programming 2 27 to 2 28 primary analog output operation 3 22 to 3 23 secondary analog output operation 3 39 buffer timing and control for primary analog output 3 12 to 3 16 continuous mode 3 13 to 3 14 master slave trigger 3 15 to 3 16 mute buffers 3 15 single buffer mode 3 13 waveform staging 3 14 to 3 15 buffered event counting cumulative 4 5 noncumulative 4 4 to 4 5 programming 4 20 to 4 22 Buffered Period And Semi Period And Pu W
515. ommand 1 Register AO Command 2 Register AO Interrupt Control Register AO Mode 1 Register AO Mode 2 Register DAQ STC Technical Reference Manual 3 60 National Instruments Corporation Chapter 3 Analog Output Timing Control AO Mode 3 Register AO Output Control Register AO Personal Register AO START Select Register AO Trigger Select Register Setting this bit to 1 also clears all of the status bits and interrupts related to analog output except those associated with the data FIFO This bit is cleared automatically 0 Software Gate bit 1 type Write in AO Mode 3 Register address 70 This bit controls the software gate which you can use to pause an analog output operation 0 Enable operation Pause operation This bit is not supported on the first revision of the DAQ STC and must be set to 0 See Appendix D DAQ STC Revision History for DAQ STC revision information 0 Source Divide 2 bit 4 type Write in Clock and FOUT Register address 56 This bit determines the frequency of the internal timebase AO IN TIMEBASEI 0 Same as IN TIMEBASE 1 IN TIMEBASE divided by two 0 START Edge bit 5 type Write AO START Select Register address 66 This bit enables edge detection of the START trigger 0 Disabled 1 Enabled This bit is currently not supported and it must be set to 0 START Interrupt bit 11 type Strobe Interrupt Ack Register address 3 Setting this bit t
516. on 3 8 6 Output Control The AOTM also contains hardware for generating the necessary output signals This hardware performs the following operations e Generates the update signals UPDATE and UPDATE2 and controls their width and polarity e Generates the DAQ STC writes to DAC signals TMRDACWR DACWR lt 1 0 gt LDAC lt 1 0 gt e Conditions the CPU writes to DAC signal CPUDACWR e Arbitrates the DAQ STC and CPU write signals to prevent local bus conflict e Generates the bus extend request signal to the CPU CHRDY OUT National Instruments Corporation 3 123 DAQ STC Technical Reference Manual Chapter 3 3 8 7 Analog Output Timing Control e Generates the DAC address up to 16 DAC channels Generates the AOFFRT signal e Generates the AOFREQ signal The bitfield AO UPDATE Output Select controls the output UPDATE The output can be one of high impedance ground output enabled or output enabled and inverted When enabled the signal pulses to update the DAC The bitfield AO_UPDATE2_Output_Select controls the output UPDATE2 The output can be one of high impedance ground output enabled or output enabled and inverted When enabled the signal also pulses to update the DAC Nominal Signal Pulsewidths Table 3 9 lists the nominal pulsewidths for the signals associated with analog input Notice that only the UPDATE and UPDATE2 signals can use either the source or output clocks all of the others must use the indicated clo
517. on in combination with the GPCT module or directly in software Scan count 24 bit scan down counter Trigger up to 224 scans or generate scans continuously DAQ STC Technical Reference Manual 2 2 National Instruments Corporation Chapter 2 Analog Input Timing Control Trigger modes Hardware and software triggering Support for versatile analog triggering e Delayed trigger nterval counters have alternate first period capability for retriggerable delay from trigger Minimum delay of one SI source clock Maximum delay of 27 SI source clocks e Pretrigger Count pretrigger scans and ignore START triggers until the pretrigger count has been satisfied Synchronize multiple DAQ STCS in the pretrigger mode e Gating Hardware and software gating e Seamless interface to the configuration FIFO and the data FIFO Error detection Overrun and overflow error detection flags for internal or external timing Error detection for excessive interrupt latency during staged analog input e Bus interface support Interrupts based on triggers error conditions and FIFO flags FIFO flag based request signal to simplify DMA request logic e Seamless interface to external analog input accessories Multiplexer 16 bit counter can generate internal multiplexer clock by dividing down the external multiplexer clock Provides a clock for the external multiplexer Simultaneous sample and
518. on Minimum Maximum Tpfi 512 Source to PFI output START 14 56 Tbrd 512 Source to BRD output START 15 60 Tscan SI2 Source to SCAN IN PROG 16 56 Tspfi SI2 Source to PFI output 16 56 SCAN PROG Tsbrd SI2 Source to BRD output 17 61 SCAN PROG timing values are in nanoseconds Figure 2 33 START Delays Internal CONVERT National Instruments Corporation 2 101 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control External CONVERT Mode In the external CONVERT mode the START and SCAN IN PROG outputs are generated by the active edge of the CONVERT source that recognizes START If you set AI Trigger Length to 0 both edges of the START pulse are generated by the same edge of the CONVERT source If you set AI Trigger Length to 1 the START pulse is stretched Figure 2 34 shows the propagation delays for START and SCAN IN PROG in the external CONVERT mode The deassertion delay for 7 START is indicated for the case where AI Trigger Length is set to O START N CONVERT SRC Tpfin Tpfi PFI7 AI START START Tbrd RTSI BRD 2 3 START Tscan SCAN_IN_PROG Tspfi PFI7 Al_START SCAN_IN_PROG Tsbrd RTSI BRD 2 3 SCAN IN PROG Name Description Minimum Maximum Tpfi CONVERT SRC to PFI output START 14 48 Tpfin CONVERT SRC to PFI output START 23 77 deassert Tbrd CONV
519. ons to set up your timebase Before beginning the programming sequence you may want to program the Configuration FIFO and flush the AI data FIFO if this is appropriate for your DAQ device Call AI_Reset_All Call Board Personalize Call AI Initialize Configuration Memory Output Call Board Environmentalize Call AI FIFO Request Selection Call AI Hardware Gating Call AI Trigger Signals Call Number Of Scans Call AI Scan Start Call Scan End Call CONVERT Signal You may want to clear the AI data FIFO if applicable If you are using an external multiplexer such as the AMUX 64T you must program it here f you are using an external track and hold module that requires the presence of the SCAN PROG signal on PFIT you must program it here Call Interrupt Enable Call Arming Call Start The Acquisition 2 6 4 Single Scan To acquire exactly one scan of input a special programming sequence is required as follows Use the programming sequence from section 2 6 3 16 Analog Input Program In the function AI_Scan_Start set AI START Select 31 ground AI START Polarity 0 DAQ STC Technical Reference Manual 2 42 National Instruments Corporation Chapter 2 Analog Input Timing Control After the programming sequence is complete issue the following commands AI START Polarity 1 E AI START Polarity 0 2 6 5 Ch
520. ontrol Timing Trigger Timing Trigger RTSI Connector National Instruments Corporation Figure 1 2 Analog Output Application DAQ STC Technical Reference Manual Chapter 1 Introduction The DAQ STC monitors the status of the AO data FIFO so that it can generate an interrupt or a DMA request when the FIFO empties beyond a programmable threshold The DAQ STC can also supply a retransmit signal to the AO data FIFO if the FIFO is large enough to hold the entire buffer When the output data is needed at the converters the DAQ STC clocks the data from the FIFO into the DACs using the DAC write and DAC address signals An update signal allows all of the DACs to update their outputs simultaneously The CPU can also write directly to the DACs using the CPU request signal to request that the DAQ STC allow access The DAQ STC arbitrates between itself and the CPU notifying the CPU that the write has completed using the channel ready signal Timing and trigger signals pass to and from the DAQ STC and the I O and RTSI connectors for external timing applications 1 2 DAQ STC Block Diagram Figure 1 3 shows a block diagram of the DAQ STC The diagram shows all of the I O signals as well as the direction of the signal input output or bidirectional Each chapter of this manual discusses one of the modules depicted in this block diagram lt 1 7 gt CS RD WR WR DS RESET D 0 15 CH
521. ontrol signals The state diagrams for the control circuits are discussed below National Instruments Corporation 2 123 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 2 8 3 1 SC Counter The SC counter is a 24 bit down counter with dual load registers and output save latch The SC counter is used to count scans When you select internal CONVERT the SC counter source is equal to 51 SRC In this mode the SC counter increments on 512 TC AND STOP When you select external CONVERT the SC counter source is SCLK In this mode the SC counter increments on every STOP The counter load registers are directly accessible in write mode from the register map If the counter is disarmed AI SC Load will load the counter with the value from the selected load register The AI SC Write Switch option allows the load register writes to be directed to the inactive load register During normal operation the SC counter will synchronously reload from the selected load register following SC Several options allow the SC counter to change the selected load register under various conditions The options are to switch load registers on every SC TC AI SC Reload Mode and to switch load registers on the next SC TC SC Switch Load On TC The SC control circuit discussed below generates the count enable signals The SC save register latch signal asserts after a rising and then a falling edge of SC SRC following a 1 bei
522. operation National Instruments Corporation 3 73 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control UI Save Value bits lt 0 7 gt type Read in AO UI Save Registers address 16 bits lt 0 15 gt type Read in AO UI Save Registers address 17 This bitfield reflects the contents of the UI counter Reading from this bitfield while the UI counter is counting may result in an erroneous value The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address 0 UI Source Polarity bit 3 type Write in AO Mode 1 Register address 38 This bit selects the active edge of the UI source the signal that is selected by AO UI Source Select 0 Rising edge Falling edge Related bitfields UI Source Select 0 UI Source Select bits lt 6 10 gt type Write in AO Mode 1 Register address 38 This bitfields selects the UI source 0 The internal signal AO IN TIMEBASEI 1 10 lt 0 9 gt 11 17 RTSI TRIGGER O 6 19 The internal signal IN TIMEBASE2 31 Logic low Related bitfields UI Source Polarity UI Switch Load On BC TC bit 9 type Strobe in AO Command 2 Register address 5 Setting this bit to 1 causes the UI counter to switch load registers at the next This action is internally synchronized to the falling edge of the UI CLK You can use this bit to change the update rate during waveform generation at the
523. or AO_Configuration_End 1 End critical section 3 6 1 10 FIFO Mode Use this function to select the data FIFO condition on which interrupt or DMA requests will be generated if you want the DAQ STC to generate them You can also use this function to program FIFO control for local buffer mode with or without pauses National Instruments Corporation 3 29 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control Function AO FIFO Begin critical section AO Configuration Start 1 AO FIFO Mode 0 generate on empty FIFO or 1 generate on less than half full FIFO or 2 generate on less than full FIFO or 3 generate on less than half full FIFO but keep asserted until FIFO is full AO Retransmit Enable 0 disable local buffer mode or 1 enable local buffer mode AO Configuration End 1 End critical section 3 6 1 11 Enable Interrupts Use this function to enable the AOTM to generate interrupts Function AO Interrupt Install Begin critical section AO_UPDATE_Interrupt_Enable 0 no interrupt or generate interrupt AO BC TC Interrupt Enable 0 no interrupt or 1 generate interrupt AO UC Interrupt Enable 0 no interrupt or 1 generate interrupt AO STARTI Interrupt Enable 0 no interrupt 1 generate interrupt AO Interrupt Enable 0 no interrupt or 1 generate interrupt AO START Interrupt Enable 0 no interrupt or 1 gene
524. ounter TC The UI TC signal is primarily used as the internal UPDATE National Instruments Corporation 3 113 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control Table 3 6 Internal Signals Continued Signal Description UD CE UI2 Count Enable This signal enables and disables the UI2 counter Refer to section 3 8 3 8 UI2 Control for the UI2 CE equations UD CLK UD Clock The 012 clock signal is the actual clock for UI2 counter and the UI2 control logic When the counter is not armed UI2_CLK is the write strobe for Command 1 Register so that the counter can be loaded using the load command When the counter is armed UI2 CLK is the same as UI2_SRC 012 LOAD UI2 LOAD SRC UI2 Load This signal pulses to load the value from the selected UI2 load register into UI2 counter Related bitfields 012 Load UI2 Load Source This signal determines which load register A or B the UI2 counter will use on the next reload The initial UI2 load source is set using AO UD Initial Load Source The UI2 control logic updates 012 LOAD SRC while the DAQ STC is counting The current load source depends on the counter state and the selected reload mode Related bitfields UI2 Initial Load Source AO UD Next Load Source St UI2 Reload Mode UD SRC UI2 Source The UI2 source is the timebase for the UI2 counter It is software selectabl
525. ounter disarms when CONTROL returns low The HW save register switches to transparent mode on the rising edge of G_GATE and returns to latched mode on the next G SOURCE falling edge Interrupts if enabled are generated on GATE falling edge Figure 4 38 shows an example of a single pulsewidth measurement where the pulsewidth of is four SOURCE rising edges The dotted line indicates where the ARM occurs and the arrows indicate where the gate interrupt is generated Figure 4 38 assumes that ARM occurs while is low If ARM occurs while G_GATE is high the pulse will only be measured from ARM until the end of the pulse G SOURCE Fond G_CONTROL Counter Value 0 X 2 X 3 X 4 X HW Save HW Save Register Figure 4 38 Single Pulsewidth Measurement National Instruments Corporation 4 77 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 8 11 8 Buffered Period Measurement To use this function set G CONTROL conditioning to edge gating and program the counter to reload CONTROL and generate interrupts on The counter increments on every SOURCE rising edge following the ARM The rising edge of GATE 15 synchronized by the falling edge of G SOURCE to generate a G CONTROL pulse On the SOURCE rising edge following
526. ounter value gt Gi_Load 1 Y DAQ STC Technical Reference Manual 4 24 National Instruments Corporation Chapter 4 General Purpose Counter Timer Gi Source Select 0 IN TIMEBASEI1 or 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt 18 IN TIMEBASE2 or 19 other G TC Gi Source Polarity 0 count rising edges or 1 count falling edges Gi Gate Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 AI START2 19 UD or 20 other TC or 21 AI STARTI or 31 logic low Gi OR Gate 0 Gi Output Polarity 0 active low or 1 active high Gate Select Load Source 0 Gi Gate Polarity 0 disable inversion or 1 enable inversion Gi Output Mode 1 one clock cycle output or 2 toggle on TC or 3 toggle on TC or gate If single period measurement then Gi Reload Source Switching 1 Gi Loading On Gate 0 Gi Loading On TC 0 Gi Gating Mode 2 Gi Gate On Both Edges 0 Gi Trigger Mode For Edge Gate 0 Gi Stop Mode 0 Gi Counting Once 2 Gi Up 1 Else Single pulsewidth measurement Gi Reload Source Switching 0 Gi Loading Gate 1 Gi Loading On TC 0 Gi Gating Mode 1 Gi Gate On Both Edges 0 Gi Trigger Mode For Edge Gate 2 Gi Stop Mode 0 Gi Counting Once 2 Gi Up 1 Gi_Bank_Switch_Enable 0 Gi_Bank_Switch_Mode 0 Gi_TC_Inter
527. output signal CTROUT If the CTRSRC is selected to be the output of the other general purpose counter then you must add the Tso delays from each counter to determine the total source to output delay For example if general purpose counter 0 selects OSC for its source and general purpose counter 1 selects the output of general purpose 0 for its source then the total delay OSC to the CTROUT of general purpose counter 1 will be 18 27 45 MIN and 55 80 135 National Instruments Corporation 4 55 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer CTRSRC H Tso Tso CTROUT _ ul Name Description Minimum Maximum Tso Internal timing mode 18 55 Tso External timing mode 27 80 timing values are in nanoseconds Figure 4 22 CTRSRC to CTROUT Timing 4 7 3 G_GATE Minimum Pulsewidth Figure 4 23 and the accompanying table indicate the minimum pulsewidth for the general purpose counter gate signal CTRGATE Tgatepw CTRGATE Tgatepw Name Description Minimum Maximum Tgatepw CTRGATE minimum pulsewidth 6 timing values are in nanoseconds Figure 4 23 G_GATE Minimum Pulsewidth DAQ STC Technical Reference Manual 4 56 National Instruments Corporation Chapter 4 General Purpose Counter Timer 4 7 4 CTRGATE to CTROUT Delay When Gi Out
528. p_Gate_St 6 AO_BC_Gate_St 5 AI_Start_Stop_Gate_St 4 AI SC Gate St 3 Gate St 2 GO Gate St 1 Bank St 0 GO Bank St RTSI Board Register Address 81 Type Write only 15 RTSI Board 3 Pin Dir 14 13 N 1 RTSI Board 2 Pin Dir RTSI Board 1 Pin Dir RTSI Board 0 Pin Dir RTSI Board 3 Output Select 5 Board RTSI Board Output Select Output Select RTSI Board 3 Output Select RTSI Board 3 Output Select RTSI Board 2 Output Select RTSI Board 2 Output Select RTSI Board 2 Output Select RTSI Board 1 Output Select RTSI Board 1 Output Select RTSI Board 1 Output Select RTSI Board 0 Output Select 0 0 DAQ STC Technical Reference Manual Appendix B Register Information RTSI Trig A Output Register Address 79 Type Write only 15 RTSI Trig 3 Output Select 14 RTSI Trig 3 Output Select 13 RTSI Trig 3 Output Select RTSI Trig 3 Output Select RTSI Trig 2 Output Select RTSI Trig 2 Output Select RTSI Trig 2 Output Select RTSI Trig 2 Output Select RTSI Trig 1 Output Select RTSI Trig 1 Output Select RTSI Trig 1 Output Select RTSI Trig 1 Output Select RTSI Trig 0 Output Select RTSI Trig 0 Output Select RTSI Trig 0 Output Select RTSI Trig 0 Output Select N NUR CO Trig Direction Register Address 58 Type Write only 15 RT
529. pe Strobe AI Command 2 Register address 4 Setting this bit to 1 causes the SC counter to switch load registers at the next SC TC You can use this bit for staged analog input This bit is cleared automatically SC TC Error Confirm bit 7 type Strobe Interrupt Ack Register address 2 Setting this bit to 1 clears AI 5 TC Error St This bit is cleared automatically Related bitfields AI SC Error St AI SC TC Error St bit 9 type Read in AI Status 1 Register address 2 This bit indicates the detection of an SC TC error 0 No error 1 Error An SC error is detected if AI SC TC Interrupt Ack is not set between two SC TCs This allows you to detect large interrupt latencies and potential problems associated with them To clear this bit set SC Error Confirm to 1 Related bitfields AI SC TC Interrupt AI SC TC Error Confirm SC TC Interrupt Ack bit 8 type Strobe Interrupt Ack Register address 2 Setting this bitto 1 clears AI Last Shiftin St AI SC TC St and the SC TC interrupt request in either interrupt bank if the SC TC interrupt is enabled This bit is cleared automatically Related bitfields AI Last Shiftin St AI SC TC St SC TC Interrupt Enable bit 0 ype Write in Interrupt_A_Enable_Register address 73 This bit enables the SC_TC interrupt 0 Disabled 1 Enabled SC interrupts are generated on every SC falling edge u
530. pe Write in Interrupt Enable Register address 73 This bit enables the START interrupt 0 Disabled Enabled The START interrupt is generated on valid START triggers received by the DAQ STC A valid START trigger is one that is received while the SC counter is enabled to count AI START Output Select bit 10 type Write in AI Output Control Register address 60 This bit selects the output source for the bidirectional pin 7 START Pulse if the pin is configured for output 0 If AI Trigger Length is set to 0 the pin will reflect the internal signal START If AI Trigger Length is set to 1 the pin will reflect the internal signal AD START after it has been pulse stretched to be 1 2 AI OUT TIMEBASE periods long The pin will output the same signal as SCAN IN PROG If SCAN IN PROG is configured for high impedance the pin will output ground Related bitfields 7 Pin Dir AI Trigger Length START Polarity bit 15 type Write AI START STOP Select Register address 62 This bit determines the polarity of START trigger 0 Active high or rising edge 1 Active low or falling edge DAQ STC Technical Reference Manual 2 74 National Instruments Corporation Chapter 2 Analog Input Timing Control START Pulse bit 2 type Strobe AI Command 2 Register address 4 Setting this bitto 1 sends a START trigger to the counters if the START software strobe is selected START S
531. periodically read relevant status bitfields and use the values obtained to decide whether to execute a programming sequence equivalent to the ISRs When the DAQ STC is used in a system in which interrupts can be handled but the handling is prohibitively slow you can use the polling technique However your system will be devoted entirely to one application For more detailed discussion of interrupts and polling refer to any introductory computer architecture textbook Information on interrupts and polling can also be found in National Instruments Application Note 010 Programming Interrupts for Data Acquisition on 80 86 Computers Interrupts related to analog input can be generated on the following analog input conditions Error overrun or overflow e START e STOP e STARTI e START2 DAQ STC Technical Reference Manual 2 46 National Instruments Corporation e SC e FIFO condition Chapter 2 Analog Input Timing Control Basic actions required to enable detect and acknowledge the analog input related interrupts follow Error To enable To recognize To acknowledge and clear START To enable To recognize To acknowledge and clear STOP To enable To recognize To acknowledge and clear START1 To enable To recognize To acknowledge and clear START2 To enable To recognize To acknowledge and clear SC TC To enable To recognize To acknowledge and
532. polarity selection edge detection and synchronization synchronized to the falling edge of SI SRC National Instruments Corporation 2 117 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Table 2 9 Internal Signals Continued Signal Description SI TC Scan Interval TC This signal is the internal START signal START Start This signal is used when the AITM is in the start stop mode AI Start Stop 1 Asserting the START trigger after the timer has been armed and triggered STARTI asserted starts CONVERT generation If an internal CONVERT is used the START trigger starts the SI2 counter If an external CONVERT is used the START trigger sets the STST_GATE to allow the CONVERTS to pass The START signal is software selectable from either polarity of the programmable function inputs SI TC and software strobe It can be programmed to be level or edge sensitive and can be synchronized to FSC 5 Related bitfields AI START Select AI START Pulse AI START Edge AI START Sync STARTI Start 1 This signal is the start trigger signal for the SC SI SI2 and DIV counters STARTI is software selectable from either polarity of the programmable function inputs and software strobe It can be programmed to be edge or level sensitive and can be synchronized to FSC SRC Related bitfields AI STARTI1 Select AI STARTI Pulse AI STARTI Edge AI STARTI Sync START2 Start 2 This signa
533. programming of the RTSI interface for specialized applications DAQ STC Technical Reference Manual 6 2 National Instruments Corporation Chapter 6 RTSI Trigger Use the following function to program the RTSI interface Function MSC RTSI Pin Configure switch pin class case RTSI Trigger switch pin number case i RTSI Trig i Pin Dir 0 input or 1 output RTSI Trig i Output Select 0 ADR 1 ADR START2 or 2 SCLKG or 3 DACUPDN or 4 STARTI or 5 G_SRC 0 or 6 GATE 0 or 7 RGOUTO or 8 through 11 RTSI_BRD lt 0 3 gt case RTSI Board switch pin number case i RTSI Board i Pin Dir 0 input or 1 output RTSI Board i Output Select 0 through 6 5 TRIGGER O 6 or 7 AI STOP case RTSI Subselection switch pin number case 1 RTSI Sub Selection 1 0 general purpose counter 0 TC or 1 same as OUT RTSI IO pin break 6 4 2 Bitfield Descriptions Bits in the register bit maps are organized into bitfields A bitfield can contain one or more bits Only bits with contiguous locations within a register can belong to a bitfield The high and low pairs of load and save registers for 24 bit counters are also treated as bitfields The RTSI trigger related bitfields are described below Not all bitfields referred to in section 6 4 Programming Information are listed here To locate a particular bitfield description within this manual refer to
534. pt Control Register 60 AI Output Control Register 61 Analog Trigger Etc Register 62 AI START STOP Select Register 63 AI Trigger Select Register 64 AI DIV Load A Register 66 AO START Select Register 67 AO Trigger Select Register 68 GO Autoincrement Register 69 Autoincrement Register 70 AO Mode 3 Register National Instruments Corporation B 6 DAQ STC Technical Reference Manual Appendix B Register Information Table B 2 Registers in Order of Address Continued Address Register Name 71 Generic Control Register 72 Joint Reset Register 73 Interrupt Enable Register 74 Second Enable Register 75 Interrupt B Enable Register 76 Second Irq Enable Register 77 AI Personal Register 78 AO Personal Register 79 RTSI Trig A Output Register 80 RTSI Trig B Output Register 81 RTSI Board Register 82 Write Strobe 0 Register 83 Write Strobe 1 Register 84 Write Strobe 2 Register 85 Write Strobe 3 Register 86 AO Output Control Register 87 AI Mode 3 Register 1 Window Data Read Register 2 Status 1 Register 3 AO Status 1 Register 4 G Status Register 5 AI Status 2 Register 6 AO Status 2 Register 7 DIO Parallel Input Register 8 9 GO HW Save Registers 10 11 G1 HW Save Registers National Instruments Corporation B 7 DAQ STC Technical Reference Manual Appendix B Register Information Registers in Order of Address Continued
535. pt control 3 122 bitfield descriptions 8 12 to 8 14 features 8 1 interrupt condition summary table 8 15 to 8 16 interrupt handling programming 8 5 to 8 12 Interrupt Group A 8 6 to 8 9 Interrupt Group B 8 9 to 8 12 interrupt program 8 6 interrupt interface programming 8 3 to 8 5 interrupt output polarity 8 3 interrupt output select and enable 8 3 to 8 4 pass through interrupt 8 4 to 8 5 overview 8 1 pin interface table 8 2 interrupt latency 3 32 3 42 Interrupt_Output_On_3_Pins bit 8 13 National Instruments Corporation Interrupt Output Polarity bit 8 13 interrupts enabling analog input timing control 2 40 to 2 41 primary analog output operation 3 30 programming analog input related interrupts 2 46 to 2 48 primary analog output 3 35 to 3 37 secondary analog output 3 45 servicing for waveform staging 3 32 3 42 interval scanning mode timing 2 106 to 2 108 clock periods table 2 107 signals for figure 2 106 IRQ IN O 1 signal table 8 2 IRQ OUT O 7 signal table 8 2 L LDAC lt 0 1 gt signals DAC interface 3 8 decoded signal timing 3 94 to 3 95 description table 3 18 setting source and update mode primary analog output operation 3 29 simplified analog output model 3 5 local buffer mode FIFO data interface 3 9 to 3 10 timing 3 96 to 3 97 LOCALMUX CLK signal configuration FIFO control and external multiplexer control 2 8 configuration memory timing 2 89 to
536. pts are generated on the leading edge of the G_TC signal from general purpose counter 1 G1 Gate Interrupt Interrupts are generated on the CONTROL signal from general purpose counter 1 Refer to section 4 8 7 Gate Actions for a complete description Pass Through Interrupt 0 Interrupts are generated when the IRQ INO pin is asserted Pass Through Interrupt 1 Interrupts are generated when the IRQ INI pin is asserted DAQ STC Technical Reference Manual National Instruments Corporation Bus Interface 9 1 Overview This chapter describes the features of the bus interface module gives programming instructions and presents the timing diagrams for the bus interface The bus interface module implements a flexible window address mapping scheme to access the internal registers of the DAQ STC The entire address space of the DAQ STC is always indirectly accessible via two window registers address and data Two accesses to the DAQ STC are required for each access to an internal register via the window registers This allows the DAQ STC to be used in systems with address space limitations such as the ISA The entire address space is also directly accessible for systems where address space is not a problem A mixed mode implementation of the address space such as eight registers accessed directly and the remaining registers accessed in windowed mode is desirable for the ISA bus The frequently used regi
537. put Mode is set to 3 the counter output CTROUT is asynchronously controlled by the counter gate CTRGATE Figure 4 24 and the accompanying table indicate the delay from CTRGATE to CTROUT when the output is being controlled by the gate CTRGATE Tgateo Tgateo CTROUT Name Description Minimum Maximum Tgateo CTRGATE to CTROUT 14 44 timing values are in nanoseconds Figure 4 24 CTRGATE to CTROUT Timing 4 7 5 CTRGATE to INTERRUPT When Gi Gate Interrupt Enable is set to 1 interrupts are generated based on CTRGATE The deassertion of INTERRUPT occurs when software clears the register bit causing the interrupt Figure 4 21 and the accompanying table indicate the delay from CTRGATE to INTERRUPT when the counter gate generates an interrupt CTRGATE Tgatei INTERRUPT Name Description Minimum Maximum Tgatei CTRGATE to INTERRUPT 11 37 timing values are in nanoseconds Figure 4 25 CTRGATE to INTERRUPT Timing National Instruments Corporation 4 57 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 7 6 CTRGATE Setup In many GPCT functions for example simple gated event counting the gate signal causes the counter to start and stop counting In these functions CTRGATE is usually synchronized to the falling edge of CTRSRC before being used by the counter In order for CTRGATE to be recognized
538. put Register address 79 i 1 bits lt 4 7 gt Write in RTSI Trig A Output Register address 79 bits lt 8 11 gt type Write in RTSI Trig A Output Register address 79 bits lt 12 15 gt type Write in RTSI Trig A Output Register address 79 bits lt 0 3 gt Write in RTSI Trig B Output Register address 80 i bits lt 4 7 gt Write in RTSI Trig B Output Register address 80 i 6 bits lt 8 11 gt type Write in RTSI Trig B Output Register address 80 This bitfield selects the signal appearing on RTSI TRIGGERI pin if the pin is configured for output Internal analog input signal ADR STARTI Internal analog input signal START2 Internal analog input signal SCLKG Internal analog output signal DACUPDN Internal analog output signal STARTI The SRC signal from general purpose counter 0 The GATE signal from general purpose counter 0 RGOUTO see 5 Sub Selection 1 8 11 Signal present at the RTSI BRD pin 0 3 Related bitfields RTSI Trig Dir i 1 Il A WN QU eS RTSI Trig j Pin Dir i 0 bit 9 type Write in RTSI Trig Direction Register address 58 i 1 bit 10 type Write RTSI Trig Direction Register address 58 i 2 bhit ll type Write in RTSI Trig Direction Register address 58 i 3 bit 12 type Write in RTSI Trig Direction Register address 58 i 4 bit 13 type Write in RTSI Trig Direction Register addr
539. r G GATE Counter Value 2 2 2 1 027 OS 270 2 109 9 2 1 9 2 1 G SOURCE Counter TC 4 p G OUT Figure 4 16 Continuous Pulse Train Generation 4 4 4 2 Buffered Static Pulse Train Generation This function is similar to continuous pulse train generation except that the software maintains a software count of the number of pulses that have been generated and stops the pulse generation after a predetermined number of pulses G_GATE active edge causes the counter to generate a sequence of pulses with programmable delay from trigger pulse interval and pulsewidth The counter uses G SOURCE as a timebase to generate the pulses so you specify the programmable parameters in terms of periods of the G SOURCE input After each pulse an interrupt notifies the CPU so that the interrupt software can increment the software pulse counter After the desired number of pulses have been output the software terminates the pulse generation Figure 4 17 shows the generation of three pulses with a delay from trigger of three a pulse interval of four and a pulsewidth of three G GATE G SOURCE Counter Value 2 2 2 1 021 032 102 10321021 Counter TO GOUT
540. r 4 8 Detailed Description This section provides a detailed description of the GPCT The discussion refers to bitfields in the DAQ STC register map You can find the register level information for these bitfields in section 4 6 Programming Information The GPCT module contains two identical 24 bit binary up down counters Figure 4 30 shows a model of the counter G UP DOWN 24 Bit Load Registers Bank X Bank Y Ll 8 Bit autoinc a G SOURCE G OUT 24 Bit Up Down Counter G GATE HW Save Register SW Save Register INTERRUPT Figure 4 30 General Purpose Counter Timer Model The two counters are identical except in the routing of their output signal G_OUT Refer to section 4 8 5 G_OUT Conditioning and Routing for more information Each counter has two banks of load registers designated bank X and bank Y Each bank contains two 24 bit load registers designated load register A and load register B The load registers allow a seamless change of counter load parameters in the pulse generation functions for example in buffered pulse train generation Load register A in bank X has a special autoincrement feature that is used in pulse train generation for ETS Each time the counter reloads from the load register the autoincrement circuit adds a constant fixed value National In
541. r 0 is available on RTSI TRIGGER O 6 The counter output pins are OUTO RTSI IO and OUTI DIV TC OUT As the pin names reflect these pins have multiplexers on the outputs Table 4 12 indicates how the bitfield GPFO 0 Output Select controls OUTO RTSI IO pin Table 4 12 OUTO RTSI 10 Selection GPFO 0 Output Select Selection 0 OUT signal from general purpose counter 0 1 7 RTSI lt 0 6 gt Table 4 13 indicates how the bitfield 1 Output Select controls G OUTI DIV TC OUT pin Table 4 13 G OUT1 DIV TC OUT Selection GPFO 1 Output Select Selection 0 OUTI signal from general purpose counter 0 1 Internal analog input signal EXT DIVTC EXT DIVTC is the AITM DIV counter output The multiplexed functionality on the G OUTI DIV TC OUT is utilized by the SCXI systems GPFO 0 Output Enable and GPFO 1 Output Enable control the output enables for these pins To facilitate the use of the timing output capability of the GPCT counters the outputs connect internally to the other DAQ STC modules The general purpose counter 0 output G OUT connects to the AITM of the DAQ STC The general purpose counter 1 output G OUT connects to the AOTM of the DAQ STC Refer to the appropriate module description for more details DAQ STC Technical Reference Manual 4 66 National Instruments Corporation 4 8 6 G CONTROL Conditioning Chapter 4 General Purpose Counte
542. r 5 Programmable Function Inputs 5 3 Pin Interface The 10 PFI signals are listed in the following table An asterisk following a pin name indicates that the default polarity for that pin is active low Pin Type Notation B9TU Bidirectional 9 mA sink 5 mA source tri state pull up 50 Table 5 1 Pin Interface Pin Name Type Description PFIO AI STARTI B9TU PFIO STARTI Trigger from Analog Input As an input this pin provides a signal path to the PFI selectors As an output this pin reflects the state of the active high internal AI START signal The hardware generates PFIO AI STARTI as follows If AI Trigger Length is 0 this pin reflects the internal Alsignal ADR STARTI If AI Trigger Length is 1 this pin reflects the internal Alsignal AD STARTI after it has been pulse stretched to be 1 2 AI OUT TIMEBASE periods long Source Destination This pin is appropriate for use as a bidirectional signal Related bitfields BD 0 Pin Dir AI Trigger Length Analog Trigger Enable START2 B9TU PFI1 START2 Trigger from Analog Input As an input this pin provides a signal path to the PFI selectors As an output this pin reflects the state of the active high internal AI START signal The hardware generates START2 as follows If AI Trigger Length is 0 this pin reflects the internal AI signal ADR START2 If AI Trigger Length is
543. r Timer The CONTROL signal derives from the GATE signal and controls the counter operation CONTROL has two states ACTIVE and INACTIVE Table 4 14 indicates the input conditioning available for G CONTROL Table 4 14 G CONTROL Conditioning Gi Gating Mode Gi Gate On Both Edges CONTROL Conditioning 0 0 No gating G CONTROL always INACTIVE 1 0 Level gating G CONTROL just follows the GATE signal 2 0 Edge gating CONTROL pulses on GATE transition to ACTIVE 3 1 Edge gating Double Edge G CONTROL pulses on both edges of 4 8 7 Gate Actions Table 4 15 lists the gating actions that are available when gating is enabled Table 4 15 Gate Actions Gate Action Related Bitfields START STOP on G CONTROL Gi Trigger Mode For Edge Gate Gi Stop Mode Save CONTROL None Reload CONTROL Gi Loading On Gate Gi Trigger Mode For Edge Gate UP DOWN on CONTROL Gi Up Down Generate interrupt on Gi Gate Interrupt Enable Change output polarity on Gi Output Mode Select load Register on CONTROL Gi Gate Select Load Source Disarm Counter on G CONTROL Gi Counting Once Switch load bank selection CONTROL Gi Bank Switch Enable Gi Bank Switch Mode Gi Bank Switch Start National Instruments Corporation DAQ STC Technical Reference Manu
544. r address 67 This bit determines the polarity of STARTI trigger 0 Active high or rising edge 1 Active low or falling edge Set this bit to 0 if AO STARTI Select is set to 0 START1 Pulse bit 0 type Strobe AO Command 2 Register address 5 Setting this bit to 1 sends a STARTI trigger to the BC UC and UI counters if the STARTI software strobe is selected 5 Select is set to 0 This bit is cleared automatically Related bitfields AO STARTI Select DAQ STC Technical Reference Manual 3 64 National Instruments Corporation Chapter 3 Analog Output Timing Control START1 Second Enable bit 1 type Write in Second Enable Register address 76 This bit enables the STARTI interrupt in the secondary interrupt bank 0 Disabled 1 Enabled The STARTI interrupt is generated on valid STARTI triggers received by the DAQ STC A valid STARTI trigger is one that is received while the BC counter is armed and in the WAIT state START Select bits lt 0 4 gt type Write in AO Trigger Select Register address 67 This bitfield selects the STARTI trigger 0 Bitfield AO STARTI Pulse 1 10 PFI lt 0 9 gt 11 17 RTSI TRIGGER O 6 19 The internal analog input signal STARTI 31 Logic low Related bitfields AO STARTI Pulse 0 5 1 St bit 8 type Read in AO Status 1 Register address 3 This bit indicates that a valid STARTI trigger has been received by the DAQ
545. rate interrupt AO FIFO Interrupt Enable 0 no interrupt or 1 generate interrupt End critical section generate interrupts you must also program the interrupt control module Refer to Chapter 8 Interrupt Control for more information on programming the interrupt control module To use interrupts refer to section 3 6 5 Primary Analog Output Group Related Interrupts 3 6 1 12 Arming Use this function to arm the analog output counters and to preload the DACS with the first analog output value Function AO Arming Begin critical section AO Not An UPDATE 1 DAQ STC Technical Reference Manual 3 30 National Instruments Corporation Chapter 3 Analog Output Timing Control AO Not UPDATE 0 While AO_TMRDACWRs In Progress St 1 do No op AO Ul Amrn 1 Y ou must set these three bitfields in a single write AO UC 1 AO BC _ 1 End critical section 3 6 1 13 Starting the Waveform Use the following function to initiate an analog output operation if you have selected software trigger If you do not select software trigger this function does not do anything Function AO Start The Generation Begin critical section If software trigger then AO_START1_Pulse 1 End critical section 3 6 1 14 Primary Analog Output Program Use the following sequence of functions to program the AOTM for any primary analog output operation If you have data FIFO on yo
546. read the generic status lines Function MSC Generic Status return Generic_Status Note These are generic status lines Refer to the hardware manual for your DAQ board or device for information on how these lines are used 7 6 3 Bitfield Descriptions Bits in the register bit maps are organized into bitfields A bitfield can contain one or more bits Only bits with contiguous locations within a register can belong to a bitfield The high and low pairs of load and save registers for 24 bit counters are also treated as bitfields The digital I O related bitfields are described below Not all bitfields referred to in section 7 6 Programming Information are listed here To locate a particular bitfield description within this manual refer to Appendix B Register Information Control bits lt 8 15 gt type Write in Generic_Control_Register address 71 This bitfield determines the value on CTRL O 7 pins Refer to your board user manual for a description of the function of these pins DIO HW Serial Enable bit 9 type Write in DIO Control Register address 11 This bit enables hardware controlled serial digital I O 0 Disabled Use DIO Software Serial Control bit to toggle EXTSTROBE SDCLK pin 1 Enabled EXTSTROBE SDCLK pin is controlled by serial hardware DIO HW Serial Start bit 8 type Strobe DIO Control Register address 11 Setting this bitto 1 starts the hardware controlled serial digital I O if ena
547. related signals while the BC counter is using load register A as the active load register You can use the mute operation to obtain a pause between two real waveforms You must set the AO Mute bit to the correct value before the BC counter begins using load register A DAQ STC Technical Reference Manual 3 58 National Instruments Corporation Chapter 3 Analog Output Timing Control 0 Mute B bit 3 type Write in AO Command 2 Register address 5 This bit determines whether the programmed load register buffer is a mute buffer 0 Normal buffer 1 Mute buffer Set this bitto O if you want UPDATE and related signals to be generated while the BC counter is using load register as the active load register Set this bit to 1 if you want DAQ STC to suppress UPDATE and related signals while the BC counter is using load register B as the active load register You can use the mute operation to obtain a pause between two real waveforms You must set the AO Mute B bit to the correct value before the BC counter begins using load register B 0 Not An UPDATE bit 2 type Write in AO Mode 3 Register address 70 Setting and then clearing this bit causes the generation of an appropriate number of TMRDACWR pulses without generating any UPDATE pulses DAC address lines AO ADDR O 3 will also be affected if appropriate You should use this bit during the AO configuration phase in the programming sequence to load the first point of the bu
548. rial digital I O 7 10 to 7 12 IN TIMEBASE signal clock distribution figure 2 13 external START mode 2 13 timebases derived from table 10 2 to 10 3 IN TIMEBASE 2 signal analog input timing control table 2 115 analog output timing control table 3 111 initialization power up See board power up initialization initializing configuration memory output 2 28 to 2 29 INT SCLK SEL signal table 3 111 Intel bus See bus interface module INTEL MOTO signal table 9 2 internal CONVERT mode CONVERT timing 2 9 to 2 10 free run gating mode timing internal CONVERT figure 2 109 halt gating mode timing internal CONVERT figure 2 111 START and SCAN PROG trigger output 2 101 START trigger output 2 101 START and START triggers in synchronous mode 2 97 to 2 98 DAQ STC Technical Reference Manual 1 26 internal START mode scan level timing and control 2 11 to 2 12 internal UPDATE external trigger timing synchronous edge figure 3 103 synchronous level figure 3 103 primary analog output 3 11 to 3 12 trigger output START delays synchronous mode figure 3 105 Interrupt_A_Enable bit 8 12 Interrupt_A_Output_Select bit 8 12 Interrupt_A_St bit 8 13 Interrupt_B_Enable bit 8 13 Interrupt_B_Output_Select bit 8 13 Interrupt_B_St bit 8 13 interrupt control 8 1 to 8 16 analog input interrupt control 2 130 to 2 131 description 2 130 interrupts and their causes table 2 131 analog output interru
549. rial output Pin EXTSTROBE SDCLK clocks the data by generating active low pulses at the times digital data on line O is valid If you want the DAQ STC to input data synchronously to the mentioned clock circuitry connected to the DIO line 4 must have valid and stable data at those times Pulse generation on the EXTSTROBE SDCLK pin can be controlled by hardware or by software This section presents the programming sequence for hardware controlled pulse generation on the EXTSTROBE SDCLK pin To perform 8 bit hardware controlled serial output on pin 0 you must program pin DIOO for output see the function DIO Pin Configure To perform 8 bit hard ware controlled serial input on pin 4 you must program pin DIO4 for input see the function DIO Pin Configure Also in either case you must enable the serial timebase using Slow Internal Timebase see the function Msc Clock Configure in Chapter 10 Use the following function to write data to be output on the serial digital output Use the function DIO HW Serial Initialize to initiate the transfer Function DIO Serial Data Out DIO Serial Data Out ijklmnop Here i j l m n o and p are all binary digits so that ijklmnop is an eight digit binary number Logic values corresponding to i j 1 m n o and p will appear on DIOO pin Data will be output starting with i and ending with p in other words output starts with the MSB and ends with the LSB Use the following function t
550. rigger mode status signal channels 0 through 3 stop scan signal that terminates the buffer in progress start stop gate signal software G 11 DAQ STC Technical Reference Manual Glossary TC TA TC TEST IN TEST OUT TTL typ U UC UC UC CE UC CLK UC HOLD UC LOAD UC LOAD SRC UC TC UI UI2 UI2 CE UD CLK UD LOAD UI2 LOAD SRC DAQ STC Technical Reference Manual G 12 terminal count ambient temperature terminal count signal test input signal test output signal transistor transistor logic typical 24 bit update counter update counter UC count enable signal UC clock signal UC hold signal UC load signal UC load source signal UC terminal count signal update interval signal secondary update interval counter UI2 count enable signal t 012 clock signal and the UI2 control logic UD load signal 012 load source signal National Instruments Corporation UI2 SRC UI2 TC UI CE UI CLK U JI DISARM UI LOAD UI LOAD SRC UI SRC UI TC UPDATE UPDATE2 WR DS WRITE 5 lt 0 3 gt National Instruments Corporation Glossary UD source secondary update interval terminal count signal UI count enable signal UI clock signal UI disarm signal Ul load signal Ul load source signal UI source UI counter terminal count signal update clock signal secondary update signal volt power supply voltage voltage in voltage out in Intel mode
551. rns to the WAIT state Related bitfields AI Start Stop Gate Enable AI Start Stop Gate St 2 8 2 Trigger Selec tion and Conditioning The signal routing block selects the counter clocks trigger signals and gate signals from the default timebases IN TIMEBASEI and 2 internal counter outputs software strobes and the programmable function timing inputs The routing logic for the SI SRC and SCLK signals is a 20 to 1 multiplexer followed by an exclusive OR gate for polarity selection The routing logic for the trigger signals START and STOP has additional controls for edge detection and synchronization as shown in Figure 2 46 National Instruments Corporation 2 119 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control OUT SYNC 2STAGE EOUT a Q PFI 0 9 MOUT E 20 to 1 MOUT R RTSI TRIGGER 0 6 MUX POLARITY INT CLK SEL lt 0 4 gt EXT_CLK 2STAGE EXT_TIMING D Q INT_CLK R NOTE Does not show all possible selections DELAY_EXT_CLK DELAY EXT_TIMING ACK Figure 2 46 START and STOP Routing Logic Figure 2 47 depicts the control for START1 and START2 OUT SYNC n 2STAGE EOUT D 9 D Q vpp4D Q
552. roduced in this function will be used later in the functions for changing the scan rate during an acquisition Scan Rate Change staged acquisition AI Staged ISR Function Scan Start Begin critical section Declare variable si_last_load_register AI_Configuration_Start 1 DAQ STC Technical Reference Manual 2 34 National Instruments Corporation Chapter 2 Analog Input Timing Control If internal START mode is selected then AI SI Special Trigger Delay 0 AI START Select 0 the internal signal 51 TC AI START 1 AI START 5 1 AI START Polarity 0 If SI counter will use an internal timebase then AI SI Source Select 0 AI IN 85 or 19 IN TIMEBASE2 AI SI Source Polarity 0 Else AI_SI_Source_Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt AI SI Source Polarity 0 rising edge or 1 falling edge If acquisition is retriggerable then You can specify a special delay from the START trigger to the first start of scan by preloading SI AI SI Load A number of clocks from STARTI to first START 1 AI SI Initial Load Source 0 AI SI 1 L AI SI Load A number of clocks between each START 1 AI SI Reload Mode 0 Else if you will not change the scan rate during the acquisition then You can specify a special delay from the START trigger to the first start of
553. rogrammer manual for the same board The register level programmer manual refers to some of the sections in this manual When you are familiar with the material in the register level programmer manual you can refer directly to the DAQ STC Technical Reference Manual Programmers should have to read only the Programming Information section of each chapter in order to program the DAQ STC Hardware engineers may need to read further for more detailed information about hardware operation Organization of This Manual The DAQ STC Technical Reference Manual is organized as follows e Chapter 1 Introduction describes the data acquisition system timing controller DAQ STC an application specific integrated circuit ASIC for the system timing requirements of a general purpose A D and D A system such as a system containing the National Instruments multifunction I O boards e Chapter 2 Analog Input Timing Control describes the analog input timing control module AITM which generates timing for the ADC and controls signals for the associated circuitry e Chapter 3 Analog Output Timing Control describes the analog output timing control module AOTM which generates timing for the DACs and controls signals for the associated circuitry such as the data FIFO buffers National Instruments Corporation xxiii DAQ STC Technical Reference Manual About This Manual DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter
554. rogramming the Control Lines 222222 1 7 12 7 6 2 5 Reading the Status 7 13 7 6 3 Bitfield Descriptions ete oie teet er e nonet 7 13 7 7 Timne Diagrams eee ete ee He Rr ette 7 15 7 7 1 Serial Input Timing eee reete rites 7 15 7 1 2 Serial Output eee eee retener nennen 7 16 7 8 Detad d Description teo ceste 7 17 Chapter 8 Interrupt Control 81 OVENI W iced fedet ptite eet reed etae ade ates 8 1 8 2 t Features cione enn US a aware ea 8 1 83 pinIntetf ce oem gene leid eique 8 2 84 Programming 2 22 04 8 3 8 4 1 Programming the Interrupt Interface eee 8 3 8 4 1 1 Interrupt Output Polarity eese 8 3 National Instruments Corporation xiij DAQ STC Technical Reference Manual Contents 8 4 1 2 Interrupt Output Select and Enable 8 3 8 4 1 3 Pass Through Interrupt esee 8 4 8 4 2 Interrupt Handling eese 8 5 8 4 2 1 Interrupt Program 2 8 6 8 4 2 2 Interrupt 8 6 8 4 2 3 Interrupt Group 8 9 8 4 3 Bitfield Descriptions 8 12 85 Interrupt Conditions iei etre rp baptiste ipe 8 15 Chapter 9 Bus Interface PME Ou EE 9 1 92 RBeat res REOR RO DER PESO DRE DRE 9 1 9
555. ronous Mode Table 2 7 START1 and START2 Timing Asynchronous Mode Name Description Minimum Maximum Tpfi Trigger to PFI output 8 31 Trtsi Trigger to RTSI output 10 36 Tbrd Trigger to BRD output 16 53 All timing values are in nanoseconds 2 7 8 2 START Trigger and SCAN_IN_PROG Assertion You can output the START trigger on the PFI output PFI7 AI_START or on the RTSI_BRD lt 2 3 gt outputs You can output SCAN_IN_PROG on the SCAN_IN_PROG pin PFI7 AI_START or on the RTSI BRD 2 3 outputs The timing for START and SCAN_IN_PROG depends on whether you select internal CONVERT or external CONVERT using AI CONVERT Source Select This section assumes Delay Start is set to 0 DAQ STC Technical Reference Manual 2 100 National Instruments Corporation Chapter 2 Analog Input Timing Control Internal CONVERT Mode In the internal CONVERT mode the START and SCAN IN PROG outputs are generated by the inactive edge of the SI2 source that recognizes START You can select the pulsewidth of the START pulse using AI Trigger Length Figure 2 33 shows the propagation delays for START and SCAN IN PROG in the internal CONVERT mode START N SI2 Source fC VL S Tpfi PFI7 AI START START Tbrd RTSI BRD 2 3 START N Tscan SCAN_IN_PROG PFI7 AI START SCAN IN PROG Tsbrd RTSI BRD 2 3 SCAN IN PROG Name Descripti
556. rporation 3 111 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control Table 3 6 Internal Signals Continued Signal Description SCKG Internal UPDATE This signal is 1 in the external UPDATE mode and is equal to UI in the internal UPDATE mode SCLK Internal Update Clock In the internal UPDATE mode SCLK is the signal UI TC In the external UPDATE mode SCLK is the signal FSCLK after it passes through a delay gate The delay gate is provided so that signals synchronized to FSCLK have sufficient time to settle to a known state before being used by SCLK STARTI Start Trigger for the UI UC and BC Counters The start trigger is software selectable from the either polarity of the PFI lt 0 9 gt RTSI lt 6 gt software strobe AI STARTI It can be programmed to be edge or level sensitive and can be synchronized to the SRC Related bitfields AO STARTI Source Select Edge STARTI Sync AO 5 Polarity STOP Stop This signal terminates the buffer in progress It is the same signal as UC TC UC CE UC Count Enable This signal enables and disables the UC counter Refer to Figure 3 38 for the UC CE logic equations UC CLK UC Clock The UC clock signal is the actual clock signal for the UC counter and the UC counter control logic When the counter is not armed UC CLK is the write strobe for AO Command 1 Register so th
557. rq Enable 2 59 AI Last Shiftin St 2 59 AI LOCALMUX CLK Output _ Select 2 59 AI LOCALMUX Pulse 2 59 AI LOCALMUX CLK Pulse 5 Width 2 59 to 2 60 AI Output Divide 2 2 60 AI Overflow St 2 60 AI Overrun Mode 2 60 AI St 2 60 AI Pre Trigger 2 61 AI Reset 2 61 AI SC Arm 2 62 AI SC Armed St 2 62 AI SC Gate Enable 2 62 AI SC Gate St 2 62 AI SC Initial Load Source 2 63 AI SC Load 2 63 AI 5 Load A 2 63 AI SC Load B 2 63 AI SC Next Load Source St 2 63 AI SC Q St 2 64 AI SC Reload Mode 2 64 AI SC Save St 2 64 AI SC Save Trace 2 64 National Instruments Corporation 1 11 Index AI SC Save Value 2 64 AI SC Switch Load On TC 2 65 AI SC TC Error Confirm 2 65 SC TC St 2 65 AI SC TC Interrupt 2 65 AI SC TC Interrupt Enable 2 65 AI SC TC Output Select 2 66 AI SC TC Pulse 2 66 AI SC TC Second Enable 2 66 AI SC TC 65 2 66 AI SC Wirite Switch 2 66 AI SCAN IN PROG Output Select 2 61 AI SCAN Pulse 2 62 AI Scan In Progress St 2 61 AI SHIFTIN Polarity 2 67 AI SHIFTIN Pulse Width 2 67 AI SI Armed St 2 67 AI SI Count Enabled St 2 67 AI SI Initial Load Source 2 68 AI SI Load 2 68 AI SI Load A 2 68 AI SI Load B 2 68 AI SI Next Load Source St 2 68 AI SI Q St 2 69 AI SI Reload Mode 2 69 AI SI Save Value 2 69 AI SI Source Polarity 2 69 AI SI Source S
558. rrupt level your service program should test all the possible causes of interrupt and react to each one of them You can use the following function Function Shared Level Servic Declare variable done done 0 While done is 0 do If Interrupt St is 1 then Call Service Group A Else if Interrupt St is 1 then Call Service Group B Else done 1 8 4 2 2 Interrupt Group A Group contains the following interrupts e Analog input Error START STOP START1 START2 SC TC and FIFO conditions e General purpose counter 0 GO TC and GO Gate e Pass through interrupt Pass Through interrupt 0 Use the following function to service an interrupt generated by group A The same sequence can be applied if the two groups share the interrupt level and the function Shared_Level_Service is used and if the interrupt level is dedicated to group A Function Service_Group_A Declare variable done done 0 While done a is 0 do If Soft Copy AI FIFO Interrupt Enable is 1 then If AI FIFO Request St is 1 then AI FIFO caused the interrupt Service AI FIFO interrupt You cannot explicitly acknowledge a FIFO interrupt You must perform an action external DAQ STC Technical Reference Manual 8 6 National Instruments Corporation Chapter 8 Interrupt Control to the DAQ STC in order to clear this interrupt condition Else if Soft Copy Pass Thru 0 Interrupt Enable is 1 then
559. rupt_Enable 0 Gi Gate Interrupt Enable 0 National Instruments Corporation 4 25 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 6 1 9 Buffered Period Semiperiod and Pulsewidth Measurement Buffered period measurement buffered semiperiod measurement and buffered pulsewidth measurement are applications in which a general purpose counter counts the edges of its source signal normally a clock over multiple counting intervals Progress of counting is observed by monitoring the counter contents at points of interest that is on a specified gate event This is achieved by using the HW save register and interrupts In buffered period measurement source edges are counted between successive pairs of active gate edges In buffered semiperiod measurement source edges are counted between each gate transition In buffered pulsewidth measurement source edges are counted between the time the gate signal reaches the active level and the time the gate signal reaches the inactive level Possible error conditions are rollover gate acknowledge latency error and stale data error Rollover is explained in section 4 4 1 1 Simple Event Counting The gate acknowledge latency and stale data errors are explained in section 4 6 1 6 Buffered Event Counting Use this function to program a counter for a buffered period measurement buffered semiperiod measurement or buffered pulsewidth measurement Program the Source
560. s AO Source Divide By 2 AO OUT TIMEBASE AO Output Clock This signal times the output circuitry for analog output Related bitfields AO OUTPUT Divide 2 BC CE BC Count Enable This signal enables and disables the BC counter Refer to Figure 3 39 for the BC CE logic equations BC CLK BC Clock The BC clock signal is the actual clock for the BC counter and the BC control logic When the counter is not armed BC CLK is the write strobe for AO Command 1 Register so that the counter can be loaded using the load command When the counter is armed BC CLK is the same as BC SRC BC DISARM BC Disarm This signal which is generated by the BC control circuit disarms the BC counter by asynchronously clearing AO BC Arm BC HOLD BC Hold This signal controls the BC save register If BC HOLD 0 the BC save register tracks the BC counter output If BC HOLD 1 the BC save register latches the BC counter output Related bitfields Save Trace BC LOAD BC Load This signal pulses to load the value from the selected BC load register into the BC counter Related bitfields Load BC LOAD SRC BC Load Source This signal determines which load register A or B the BC counter will use on the next reload The initial BC load source is set using AO BC Initial Load Source The BC control logic updates BC LOAD SRC while the DAQ STC is counting The current load source depends on the counter state
561. s Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix E Customer Communication at the end of this manual National Instruments Corporation xxvii DAQ STC Technical Reference Manual Introduction This chapter describes the data acquisition system timing controller DAQ STC an application specific integrated circuit ASIC for the system timing requirements of a general purpose A D and D A system such as a system containing the National Instruments multifunction I O MIO boards The DAQ STC contains nine modules or function groups These function groups include the analog input timing control module analog output timing control module general purpose counter timer module programmable function inputs module RTSI trigger module digital I O module interrupt control module bus interface module and the miscellaneous functions module The counters and support logic within the analog input timing control and analog output timing control modules supply timing and control signals to independent A D and D A subsystems Two counters in the general purpose counter timer module implement event counting time measurement
562. s e To pause analog input AI Software Gate 1 e To resume analog input after pause AI Software Gate 0 Notes Software and external gating share the gating mode that is AI External Gate Mode determines the mode of operation for both hardware and software gating Software and hardware gating can be used simultaneously without any special setup The analog input operation proceeds when neither hardware nor software gate is in the pause state National Instruments Corporation 2 31 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 2 6 3 8 Trigger Signals Use this function to enable or disable retriggering and to select the START and START2 signals if applicable Function AT Trigger Signals Begin critical section AI_Configuration_Start 1 If retriggerable acquisition then AI Trigger Once 0 Else AI Trigger 1 If pretriggered acquisition then Trigger Selection AI STARTI Select 0 bitfield AI STARTI Pulse or 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 the G_OUT signal from general purpose counter 0 If AI STARTI Select is 0 then AI_START1_Polarity 0 AI_START1_Edge 1 AI STARTI Syncz 1 Else AI 5 Polarity 0 active high or rising edge or active low or falling edge AI STARTI 1 AI STARTI Syncz 1 Second Trigger Selection AI STARTO2 Select 0 bitfield AI START2 P
563. s Corporation Chapter 4 General Purpose Counter Timer 4 8 11 17 Pulse Generation for ETS To use this function set G CONTROL conditioning to edge gating program the counter to reload on TC and stop at the second TC and program load register A to autoincrement after every reload The rising edge of GATE is synchronized by the falling edge of G SOURCE to generate a G CONTROL pulse The counter begins decrementing after CONTROL pulse Once the counter TC is reached the counter reloads and counts down to TC again On the second counter TC the counter stops to wait for another gate On the next rising edge the whole process begins again The load select signal indicates whether the reload occurs from load register A or B Each time the counter reloads from load register A the value in load register increments by a fixed amount Figure 4 48 shows an example of pulse generation for ETS with an initial pulse delay of three and a pulsewidth of two The pulse delay for each subsequent pulse is one larger than the pulse delay of the previous pulse The dotted line indicates where the ARM occurs G SOURCE B G GATE G CONTROL 2 X2X1XOXIXOX 4 X9X2X1X0X1X0X5 Load Select
564. s Polarity FIFO Half Full St bit 13 type Read in AI Status 1 Register address 2 This bit reflects the state of the AIFHF pin after the polarity selection which indicates the AI data FIFO status 0 Half full or less 1 More than half full Related bitfields FIFO Flags Polarity National Instruments Corporation 2 57 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control AI FIFO Interrupt Enable bit 7 type Write in Interrupt Enable Register address 73 This bit enables the FIFO interrupt 0 Disabled Enabled The FIFO interrupt is generated on the FIFO condition indicated by AI FIFO Mode Related bitfields AI FIFO Mode AI FIFO Mode bits lt 6 7 gt type Write in AI Mode 3 Register address 87 This bit selects the AI data FIFO condition on which to generate the DMA request output signal AIFREQ and the FIFO interrupt if the FIFO interrupt is enabled 0 Generate DMA request and FIFO interrupt on FIFO not empty Keep the request and interrupt asserted while the FIFO is not empty 1 Generate DMA request and FIFO interrupt on FIFO more than half full Keep the request and interrupt asserted while the FIFO is half full 2 Generate DMA request and FIFO interrupt on FIFO full Keep the request and interrupt asserted while the FIFO is full 3 Generate DMA request and FIFO interrupt on FIFO more than half full Keep the request and interrupt asserted while the FIFO is
565. s general purpose counter i The counter remains armed and the bit remains set until it is disarmed either by hardware or by setting Gi Disarm to 1 Related bitfields Disarm Gj Arm Copy i 0 0 13 type Strobe Command Register address 7 i i bit 13 type Strobe GO Command Register address 6 Setting this bit to 1 arms general purpose counter i The counter remains armed and the bit remains set until it is disarmed either by hardware or by setting Gi Disarm to 1 Related bitfields Disarm Gi Armed St 1 0 8 type Read Status Register address 4 i 1 bit 9 type Read in G_Status_Register address 4 This bit indicates whether general purpose counter i is armed 0 Not armed 1 Armed Related bitfields Gi_Arm Gi_Arm_Copy Gi Autoincrement 1 0 01 0 7 type Write in 0 Autoincrement Register address 68 i l bits 0 75 type Write in Register address 69 This 8 bit register holds a fixed value that is added to the contents of load register A after each counter reload so that on the next reload the counter will load the incremented value You should use the autoincrement feature in pulse train generation for ETS to automatically increase the pulse delay after each trigger Gi Bank St 0 bit 0 type Read in Joint Status 1 Register address 27 i 1 bit 1 type Read in Joint_Status_1_Register address 27 This bit indicates the load register bank u
566. s on The options include polarity and pulsewidth of commonly used signals You must execute this function every time after you invoke the A02 Reset A11 function and before you perform any analog output operation using the DAQ STC If you are programming a DAQ STC that is a part of a data acquisition system refer to the register level programming manual for information about the proper selections to make in this function Function 02 Board Personalize Begin critical section AO UPDATE2 Pulse Timebase 0 selected by AO UPDATE2 Pulse Width or 1 selected by AO UPDATEA Original Pulse AO UPDATE2 Pulse Width 2 0 3 3 5 AO OUT TIMEBASE periods or 1 1 1 5 AO OUT TIMEBASE periods AO UPDATE2 Original Pulse 0 equal to the pulsewidth of UI2 TC with a maximum pulsewidth determined by AO UPDATE2 Pulse Width or 1 equal to pulsewidth of UI2 TC AO UPDATE2 Output Select 0 high Z or 1 ground or 2 enable active low or 3 enable active high End critical section 3 6 6 4 Hardware Gate Programming Use this function to enable or disable hardware and software gating If you enable hardware gating you also select the signal that will control the gate the gate polarity and the gating mode Function AO2 Hardware Gating Begin critical section If external gating is desired then AO_UI2_External_Gate_Enable 1 AO_UI2_External_Gate_Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI TRIGGER O 6 AO U
567. s one counter Counters in the first group are UI UC and BC The second group consists of the UI2 counter Since the two groups are almost independent the programming examples are separate This section discusses programming for the primary group Refer to section 3 6 6 Programming for a Secondary Analog Output Group Operation for a discussion of the secondary group 3 6 1 2 Resetting Assume the primary analog output section of the DAQ STC was set up to perform an unknown operation The object is to stop any activities in progress Function AO_Reset_All Begin critical section AO_Configuration_Start 1 AO_ Disarm 1 AO Personal Register 0 AO Command 1 Register 0 National Instruments Corporation 3 21 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control AO Command 2 Register 0 AO Mode 1 Register 0 AO Mode 2 Register 0 AO Output Control Register 0 AO Mode 3 Register 0 AO START Select Register 0 AO Trigger Select Register 0 gt AO BC Interrupt Enable 0 AO 5 Interrupt Enable 0 AO UPDATE Interrupt Enable 0 AO START Interrupt Enable 0 AO STOP Interrupt Enable 0 AO Error Interrupt Enable 0 AO UC Interrupt Enable 0 AO FIFO Interrupt Enable 0 L AO_BC_Source_Select 1 AO BC TC Trigger Error Confirm 1 AO BC TC Error Confirm 1 AO UC Interrupt Ack 1 AO BC TC Interrupt 1 AO START
568. same clock as the master by triggering on the STARTI signal that is output from the master 0 Disarm bit 13 type Strobe in AO Command 1 Register address 9 Setting this bit to 1 asynchronously disarms the BC UC and UI counters This command should be used only to disarm idle counters To disarm non idle counters use AO Software Reset This bit is cleared automatically DAQ STC Technical Reference Manual 3 52 National Instruments Corporation Chapter 3 Analog Output Timing Control 0 DMA PIO Control bit 8 type Write in AO Personal Register address 78 This bit selects the data interface mode 0 FIFO data interface mode 1 Unbuffered data interface mode You should set this bit to 0 on a board with an AO data FIFO Set this bit to 1 on a board without an AO data FIFO Refer to section 3 4 3 Data Interfaces for more information on the data interface modes 0 End On BC TC bit 15 type 5 AO Command 2 Register address 5 Setting this bit to 1 causes the BC UC and UI counters to be stopped but not disarmed at the next TC You can use this bit to stop waveform generation in the continuous mode so that the AOTM will end up in a retriggerable state This action is internally synchronized to the falling edge of the UC source This bit is cleared automatically Related bitfields Continuous 0 End On UC TC bit 14 type Strobe AO Command 2 Register address 5 Setting this bit to 1 c
569. sarmed BC Load loads the counter with the value from the selected load register During normal operation the BC counter will synchronously reload from the selected load register following TC Two options AO BC Reload Mode and AO BC Switch Load On TC change the selected load register under various conditions The options are to switch load registers on every BC TC and to switch load registers on the next TC The BC control circuit generates the count enable signals The BC save register latch signal asserts after a rising and then a falling edge of SRC following a 1 being written to AO BC Save Trace The BC save register latch signal deasserts after a rising then a falling edge of SRC following a zero being written to AO Save Trace 3 8 3 6 BC Control The BC counter is controlled by a circuit whose state transitions are shown in Figure 3 39 The BC counter control circuit has two states WAIT and CNT On power up the control circuit begins and remains in the WAIT state until the counter is armed and a STARTI pulse is received The control circuit then transitions to the CNT state and remains there until the count termination condition is reached The BC counter normally remains armed and retriggerable at the end of a waveform generation sequence The BC counter has the option AO Trigger Once to disarm itself after the first TC At the end of a nonretriggerable waveform generation sequence the T
570. scan list Output polarity is selectable Destination Configuration FIFO Options Active Low Active High Ground High Z Related bitfields AI LOCALMUX CLK Output Select AI LOCALMUX CLK Pulse AI LOCALMUX Pulse Width LOCALMUX FFRT O9TU Configuration FIFO Retransmit This output indicates that the configuration FIFO should repeat the scan list When MUXFEF is active the LOCALMUX FFRT signal is asserted on the trailing edge of LOCALMUX CLK and remains asserted based on the selected pulsewidth Output polarity is active low Destination Configuration FIFO Related bitfields AI LOCALMUX CLK Pulse Width MUXFEF IU Configuration FIFO Empty Flag This input indicates that the configuration FIFO is empty The MUXFEF signalis used to generate the configuration FIFO retransmit signal LOCALMUX FFRT The input polarity is selectable Source Configuration FIFO Related bitfields AI FIFO Flags Polarity DAQ STC Technical Reference Manual 2 22 National Instruments Corporation Chapter 2 Analog Input Timing Control Table 2 1 Pin Interface Continued Pin Name Type Description SCAN PROG O4TU Scan in Progress This output indicates that a scan is in progress It is useful for generating track hold signals for on board track and hold systems in a simultaneous sampling environment In the internal CONVERT mode SCAN_IN_PROG is asserted when START is recognized In the exter
571. se until the AO data FIFO can be refilled Timing for TMRDACWR is based on AO OUT TIMEBASE The signal can also be used as a DMA request on a board without an data FIFO in the unbuffered data interface mode The output polarity is active low and the pulsewidth is selectable Destination DACs Related bitfields AO PIO Control AO FIFO Enable AO Not An UPDATE AO TMRDACWR Pulse Width TMRDACWRs In Progress St UC TC P4TU The UC Counter Terminal Count Signal Output polarity is active high Related bitfields Misc Counter TCs Output Enable National Instruments Corporation 3 19 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control Table 3 1 Pin Interface Continued Pin Name Type Description UPDATE O9TU Primary Update This output is used to update the DACs The hardware generates UPDATE by passing the output of the UPDATE selector SCLK through pulsewidth and polarity selection circuitry Output polarity is selectable Destination DACs Options Active Low Active High Ground High Z Related bitfields AO_UPDATE_Output_Select AO_UPDATE_Pulse AO_UPDATE_Original_Pulse AO UPDATE Pulse Timebase AO UPDATE Pulse Width UPDATE2 O9TU Secondary Update This output is the secondary update signal to the DACs The hardware generates UPDATE2 by passing the internal UI2_TC UI2 counter TC signal through pulsewidth and polarity selection circuitry Output polari
572. sed by general purpose counter i 0 Bank X 1 Bank Y DAQ STC Technical Reference Manual 4 36 National Instruments Corporation Chapter 4 General Purpose Counter Timer Bank Switch Enable i 0 12 type Write in GO Command Register address 6 bit 12 type Write in Command Register address 7 If the general purpose counter i is not armed this bit selects the bank to which you can write 0 Bank X 1 Bank Y If the general purpose counter i is armed this bit enables bank switching 0 Disabled 1 Enabled Bank Switch Mode 0 bit 11 type Write in GO Command Register address 6 bit 11 type Write in Command Register address 7 This bit selects the source that controls general purpose counter i load register bank switching if bank switching is enabled 0 Gate 1 Software Related bitfields Gi Bank Switch Enable Gi Bank Switch Start Gi Bank Switch Start 0 bit 10 type Strobe GO Command Register address 6 bit 10 type Strobe Command Register address 7 Setting this bit to 1 indicates load register bank switching on the condition selected by Gi Bank Switch Mode You will typically use this bit in an interrupt service program This bit is cleared automatically Related bitfields Bank Switch Start Gi Counting Once i 0 bits 10 11 type Write in GO Mode Register address 26 i 1 bits lt 10 11 gt type Write in
573. set in either case Related bitfields TC Error St 0 Stop On BC TC Trigger Error bit 4 type Write in AO Mode 3 Register address 70 This bit determines whether analog output timing will stop when a BC TC trigger error occurs 0 Continue on BC_TC trigger error 1 Stop on BC TC trigger error AO BC TC Trigger Error St will be set in either case Related bitfields AO BC TC Trigger Error St 0 Stop On Overrun Error bit 5 type Write in AO Mode 3 Register address 70 This bit determines whether analog output timing will stop when an overrun error occurs If this bit is set and an overrun error is detected the update pulses will be masked off until the overrun error is cleared by the AO Error Interrupt Ack bit 0 Continue on overrun error 1 Stop on overrun error AO Owverrun St will be set in either case Related bitfields Overrun St Note In the case of maximum rate timing where the last IMRDACWR is being deasserted at the same time that the next UPDATE is being asserted the UPDATE pulse may be masked off Although this is not an error condition and the AO St bit will not be set that specific UPDATE pulse may be blocked DAQ STC Technical Reference Manual 3 66 National Instruments Corporation Chapter 3 Analog Output Timing Control STOP Second Enable bit 4 type Write in Second B Enable Register address 76 This bit enables the STOP interrupt in
574. signal from the other general purpose counter 31 Logic low Gi Stale Data St i 0 bit 6 type Read Status Register address 4 bit 7 type Read Status Register address 4 This bit indicates that no source edge was detected between two adjacent relevant gate edges This bit is used for noncumulative event counting and period measurement Gj Stop Mode 1 0 015 5 665 type Write in GO Mode Register address 26 i l bits lt 5 6 gt type Write in G1 Mode Register address 27 This bit selects the condition on which the counter will stop 0 Stop on gate condition 1 Stop on gate condition or at the first TC whichever comes first 2 Stop by gate condition or at the second TC whichever comes first 3 Reserved Notice that regardless of this bitfield setting you can always use the software disarm command Gi Disarm to stop the counter The gate condition that stops the counter is determined by Gating Mode in case of level gating or by a combination of Gi Gating Mode and Trigger Mode For Edge Gate in case of edge gating Selections 1 and 2 are valid only if Gi Trigger Mode For Edge Gate is set to 2 no hardware limit on this Related bitfields Gi Disarm Gating Mode Gi Trigger Mode For Edge Gate DAQ STC Technical Reference Manual 4 48 National Instruments Corporation Chapter 4 General Purpose Counter Timer Synchronized Gate i 0 0 8 type Write in GO_Command_Re
575. ssive CONVERT pulses in Figure 2 7 are equidistant they could follow any other timing 2 4 2 Scan Level Timing and Control As discussed in section 2 3 Simplified Model sequences of CONVERT pulses are organized into scans Each scan begins with a START pulse The START pulse may come from either the SI counter internal START mode or the PFI selector external START mode 2 4 2 1 Internal START Mode In the internal START mode the SI TC SI counter TC signal becomes the START pulse The STARTI trigger causes the SI counter to generate the START pulses which continue until the acquisition sequence is complete Refer to section 2 4 3 Acquisition Level Timing and Control for more information on the STARTI trigger The SI counter has dual load registers that allow for two timing parameters at the START timing level The first parameter A gives the delay from START to the first START The second parameter B gives the delay between START pulses National Instruments Corporation 2 11 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Figure 2 8 shows three scans of four CONVERT pulses each to indicate the timing parameters that are available Timing Parameter 1 A START1 START SI TC stop 02 2 Ooo TLO TL CONVERT Figure 2 8 Internal START 2 4 2 2 External START Mode In the e
576. ster address 87 This bit determines the gating mode if gating is enabled 0 Free run gating mode 1 Halt gating mode Refer to section 2 4 4 Gating for more information on gating modes Related bitfields AI External Gate Select AI Software Gate External Gate Polarity bit 5 type Write in AI Mode 3 Register address 87 This bit selects the polarity of the external gate signal 0 Active high high enables operation 1 Active low low enables operation External Gate Select bits lt 0 4 gt type Write in AI Mode 3 Register address 87 This bitfield enables and selects the external gate 0 External gate disabled 1 10 PFI lt 0 9 gt 11 17 RTSI lt 0 6 gt 31 Logic low You can use the external gate to pause an analog input operation in progress Refer to section 2 4 4 Gating for more information on external gating Related bitfields AI External Gate Polarity External Gate St bit 10 type Read in Joint Status 1 Register address 27 This bit indicates whether the external gate and the software gate are set to enable analog input operation 0 Pause analog input operation 1 Enable analog input operation Related bitfields External Gate Select AI Software Gate National Instruments Corporation 2 55 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control External Present bit 12 type Write in AI Mode 2 Register address 13
577. sters have lower addresses to allow direct access to these registers in this mixed mode implementation 9 2 Features The DAQ STC bus interface has the following features e ntel or Motorola type bus interface selection e Flexible windowed address space Requires minimum of two words of address space Scalable address space to suit host system Direct addressing is possible 9 3 Pin Interface The I O signals relevant to the Bus Interface are listed in the following table An asterisk following a pin name indicates that the default polarity for that pin is active low Pin Type Notation ID TTL input pull down 50 IU Input pull up 50 National Instruments Corporation 9 1 DAQ STC Technical Reference Manual Chapter 9 Bus Interface 105 O4TU OD18U B9TU Input pull up 5 Output 4 mA sink 2 5 mA source tri state pull up 50 Output open drain 24 mA sink pull up 50 Bidirectional 9 mA sink 5 mA source tri state pull up 50 Table 9 1 Pin Interface Pin Name Type Description lt 1 7 gt ID Address This active high address signal selects the register during a read or write operation The entire address space is always accessible via two word locations the address register A lt 1 7 gt 0 and the data register A lt 1 7 gt 1 This provides a flexible window interface The DAQ STC can occupy 2 128 words in the address space o
578. struments Corporation DAQ STC Revision History This appendix lists the differences between the first two revisions of the DAQ STC and identifies those boards containing the first revision of the DAQ STC The first revision of the DAQ STC is packaged in a 160 pin quad flat pack QFP It was revised to use a smaller lower profile 160 pin package for PCMCIA applications At that time three circuit modifications were made two of which may affect user applications and one which reduced board cost e The analog output section now supports hardware and software gating e The up down pin for each general purpose counter time is now pulled up instead of pulled down dat bus is latched during a read from the general purpose counter timer hardware save registers which removes the need for an external latch All but the earliest shipments of the first and second revision DAQ STCs contain a part number printed on the chip package The first revision of the DAQ STC contains the number 702088 01 The second revision contains the number 690286 01 The following table lists the products that used the first revision of the DAQ STC It includes product name and latest PWB revision A PWB with an earlier revision than listed such as A instead of B also uses the first revision of the DAQ STC The PWB revision is printed on the back side of each board It is not the same as the CCA number typically printed on a label and located on th
579. struments Corporation Chapter 5 Programmable Function Inputs BD ij Pin Dir 0 9 bit i type Write in IO Bidirection Pin Register address 57 This bit selects the direction of the bidirectional pin PFIi 0 Input 1 Output 9 9 Detailed Description When configured as inputs the PFI lt 0 9 gt pins provide an interface through which your timing I O signals can be brought to the internal DAQ STC modules Each of the three main internal modules AITM AOTM and GPCT has 20 to 1 input multiplexers PFI selectors to select their relevant timing control input signals Two of the inputs to the PFI selectors are generally used by internal signal sources such as software strobes and internal timebases The remaining available inputs are used for 17 timing I O pins 10 PFI pins and seven RTSI_TRIGGER pins Table 5 2 indicates the input selections available for each of the PFI multiplexers Table 5 2 PFI 0 9 Input Selections Mux 0 1 10 11 17 18 19 20 21 31 AI 5 Source SW PFI lt 0 9 gt RTSI lt 0 6 gt GOUTO GND AI START2 Source SW PFI lt 0 9 gt RTSI lt 0 6 gt GND AI SI Source AI TBI PFI lt 0 9 gt RTSI lt 0 6 gt TB2 GND AI CONVERT Source 512 TC PFI lt 0 9 gt RTSI lt 0 6 gt GOUTO GND AI START Source SI TC PFI lt 0 9 gt RTSI lt 0 6 gt SW GOUTO GND AI STOP Source DIV TC PFI lt 0 9 gt RTSI lt 0 6 gt SI2_TC AI STP GND SW AI External Gate PFI lt
580. struments Corporation 4 61 DAQ STC Technical Reference Manual Chapter 4 4 8 1 General Purpose Counter Timer to the load register so that on the next reload the counter will load the incremented value Refer to Autoincrement for more information Each counter also has two 24 bit save registers designated the hardware save register HW Save Register and the software save register SW Save Register The GATE signal latches the counter contents into the HW Save Register Thus the hardware determines the time that the counter contents are saved hence the name HW Save Register The HW Save Register makes possible buffer oriented interrupt driven period and pulsewidth measurements The DAQ STC provides error detection mechanisms for cases where gap free readings are not possible due to the interrupt latency of the system The software save register provides the ability to peek at the counter contents any time without disturbing any buffer oriented measurements The software save registers enable the software to monitor the counter contents for status reporting Internal Signals and Operation Table 4 4 lists internal signals used in the GPCT hardware description and their relationship to the external signals Table 4 4 Internal Signal Description Signal Description CONTROL Counter Control The hardware generates G CONTROL by passing through the CONTROL conditioning circuit Co
581. suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable contro
582. t 512 418 1111 E Mail Support Currently USA Only You can submit technical support questions to the applications engineering team through e mail at the Internet address listed below Remember to include your name address and phone number so we can contact you with solutions and suggestions support natinst com Telephone and Fax Support National Instruments has branch offices all over the world Use the list below to find the technical support number for your country If there is no National Instruments office in your country contact the source from which you purchased your software to obtain support Country Australia Austria Belgium Brazil Canada Ontario Canada Qu bec Denmark Finland France Germany Hong Kong Israel Italy Japan Korea Mexico Netherlands Norway Singapore Spain Sweden Switzerland Taiwan United Kingdom United States DAQ STC Technical Reference Manual Telephone 03 9879 5166 0662 45 79 90 0 02 757 00 20 011 288 3336 905 785 0085 514 694 8521 45 76 26 00 09 725 725 11 01 48 14 24 24 089 741 31 30 2645 3186 03 6120092 02 413091 03 5472 2970 02 596 7456 5 520 2635 0348 433466 32 84 84 00 2265886 9 640 0085 08 730 49 70 056 200 51 51 02 377 1200 01635 523545 512 795 8248 E 2 Fax 03 9879 6277 0662 45 79 90 19 02 757 03 11 011 288 8528 905 785 0086 514 694 4399 45 76 26 02 09 725 725 55 01 48 14 24 14 089 714 60 35 2686 8505 03 6120095 02 41309
583. t 3 74 AO UI Switch Load On TC 3 74 AO UI Switch Load On Stop 3 74 AO UI Switch Load On TC 3 75 AO UI Wirite Switch 3 75 AO UD Arm Disarm 3 75 AO UD Armed St 3 75 AO UD Configuration End 3 75 AO UD Configuration Start 3 75 AO UD Count Enabled St 3 76 AO UID External Gate Enable 3 76 AO UD External Gate Polarity 3 76 AO UD External Gate Select 3 76 AO UD Gate St 3 76 AO UD Initial Load Source 3 76 AO UD Load 3 77 AO UD Load A 3 77 AO UD Load B 3 77 AO UD Next Load Source St 3 TT AO UD Reload Mode 3 77 AO UD Save Value 3 77 AO UD Software Gate 3 78 AO UD Source Polarity 3 78 AO UD Source Select 3 78 AO UD Switch Load Next 3 78 AO UD TC Error Confirm 3 78 AO UD Error St 3 79 AO UD Ack 3 79 AO UD Interrupt Enable 3 79 AO UD TC Second Irq Enable 3 79 National Instruments Corporation AO UD TC St 3 79 AO UPDATE Interrupt 3 81 AO UPDATE Interrupt Enable 3 81 AO UPDATE Original Pulse 3 82 AO UPDATE Output Select 3 82 AO UPDATE Pulse 3 82 AO UPDATE Pulse Timebase 3 83 AO UPDATE Pulse Width 3 83 AO UPDATE Second Irq Enable 3 83 AO UPDATE Source Polarity 3 83 AO UPDATE Source Select 3 84 AO UPDATE St 3 84 AO UPDATE2 Original Pulse 3 80 AO UPDATE2 Output Select 3 80 AO UPDATE2 Output Toggle 3 80 UPDATE2 Pulse 3 80 AO UPDATE2 Pulse Timebas
584. t This bit is cleared automatically Related bitfields TC Error St 0 BC TC Error St bit 11 type Read in AO Status 1 Register address 3 This bit indicates the detection of a TC error 0 No error 1 Error A BC error occurs BC TC Interrupt Ack is not set between two BC TCs This allows you to detect large interrupt latencies and potential problems associated with them To clear this bit set AO BC TC Error Confirm to 1 Related bitfields AO BC TC AO BC TC Error Confirm National Instruments Corporation 3 49 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 BC TC Interrupt Ack bit 8 type Strobe Interrupt Register address 3 Setting this bit to 1 clears BC TC St and acknowledges the interrupt request in either interrupt bank if the TC interrupt is enabled This bit is cleared automatically Related bitfields AO TC St 0 BC TC Interrupt Enable bit 0 type Write in Interrupt Enable Register address 75 This bit enables the TC interrupt 0 Disabled 1 Enabled BC interrupts are generated on the trailing edge of BC BC TC Second Enable bit 0 type Write in Second Irq B Enable Register address 76 This bit enables the BC TC interrupt in the secondary interrupt bank 0 Disabled 1 Enabled BC interrupts are generated on the trailing ed
585. t Timing Control The numbers in square brackets indicate the number of clock periods that occur at the minimum and maximum delays because those parameters are clock edge driven with possible additional gate delays The UPDATE signal still performs the updating of the DACs as before The TMRDACWR signal is now used as a DMA request indicating that new data is needed for the analog output The CPUDACWR signal is used to actually write the DMA data to the DACs The TMRDACWR signal will remain asserted until the completion of the last CPUDACWR The AOFFF input is the DMA acknowledge indicating that the DMA data is ready for the write The CPUDACREQ input is still used to provide CPU access to DACs The CHRDY OUT signal acts as before and extends the bus cycle to the appropriate length during both of CPU DMA accesses The AO ADDR O 3 lines still indicate the destination DAC but change on the CPUDACWR signal instead of the TMRDACWR signal as before The bus address lines A lt 0 3 gt will still pass through to the AO ADDR O 3 lines during a CPU access DAQ STC Technical Reference Manual 3 100 National Instruments Corporation Chapter 3 Analog Output Timing Control 3 7 9 Maximum Update Rate Timing The maximum analog output rates that the DAQ STC obtains depend upon the number of channels selected for output Every output sequence consists of an UPDATE pulse followed by the appropriate number of TMRDACWR or CPUDACWR pulses Only
586. t also determines the length of the signal appearing on the bidirectional pin PFI7 AI START when the pin is configured to output the internal signal AD START 0 Output the normal internal version of the signal 1 Pulse stretch the internal signal to be 1 2 AI OUT TIMEBASE periods long Use the bitfield AI START Output Select to select the signal appearing on the pin PFI AI START Refer to section 5 3 Pin Interface for a description of the internal signal appearing on each bidirectional PFI pin Related bitfields AI START Output Select Trigger Once bit 0 type Write in AI Mode 1 Register address 12 This bit controls the retriggerability of the SC SI SI2 and DIV counters 0 The counters remain armed and retriggerable after generating a timing sequence 1 The counters are disarmed after one analog input timing sequence Set this bit to 1 only if Continuous is set to 0 Set this bit to 0 fora single finite pretrigger infinite posttrigger analog input operation Related bitfields AI Continuous Note If the operation is halted by AI End On End Of Scan or AI End On SC TC the counters are disarmed regardless of the state of this bit National Instruments Corporation 2 83 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 2 7 Timing Diagrams 2 1 1 The DAQ STC is primarily a synchronous device and requires careful inspection of the timing parameters when you are designing
587. t data is buffered locally in the data FIFO The data FIFO reports its status to the DAQ STC through the inputs AOFFF AOFHF and AOFEF which are the data FIFO full half full and empty flags respectively The DAQ STC uses the FIFO status to generate a DMA request or FIFO interrupt notifying the system that the FIFO requires data The DMA request appears on the output signal AOFREQ and the FIFO interrupt appears on one of the interrupt lines OUT O0 7 The DAQ STC generates the DMA request or FIFO interrupt on one of four different FIFO flag conditions including assert on FIFO empty assert on FIFO less than half full assert on FIFO not full and assert on FIFO less than half full and deassert on FIFO full DAQ STC Technical Reference Manual 3 8 National Instruments Corporation Chapter 3 Analog Output Timing Control If the data FIFO empties while a data sequence is being written to the DACs the TMRDACWR pulses pause until the data FIFO has an opportunity to refill Figure 3 5 shows an example of the FIFO data interface mode using AOFREQ asserting on FIFO empty The UPDATE signal causes the TARDACWR signal to begin writing the next output data values After TMRDACWR writes data to three channels the data FIFO empties causing AOFEF and to assert instructs the DMA controller to refill the data FIFO When the FIFO refills AOFEF deasserts allowing the remaining three channels to be written UPD
588. t explicitly acknowledge a pass through interrupt You must perform an action external to the DAQ STC in order to clear this interrupt condition Normally board hardware should be designed so that you can cause this action To enable this interrupt set AI Pass Thru 1 Interrupt Enable 1 National Instruments Corporation 8 9 DAQ STC Technical Reference Manual Chapter 8 Interrupt Control Else if Soft_Copy AO_UI2_TC_Interrupt_Enable is 1 then If AO_UI2_TC_Interrupt_St is 1 then The interrupt was caused by AO UI2_TC that is the UPDATE2 signal Service the AO UI2_TC interrupt To clear this interrupt set AI_UI2_TC_Interrupt_Ack 1 To enable this interrupt set AI UI2 TC Interrupt Enable 1 Else if SoftCopy G1_TC_Interrupt_Enable is 1 then If TC Stis 1 then The interrupt was caused by general purpose counter 0 TC Service the general purpose counter 0 TC interrupt To clear this interrupt set G1_TC_Interrupt_Ack 1 To enable this interrupt set G1_TC_Interrupt_Enable 1 Else if G1_Gate_Interrupt_St is 1 then The interrupt was caused by an appropriate event that occurred on the gate of general purpose counter 0 Service the general purpose counter 0 gate interrupt To clear this interrupt set G1_Gate_Interrupt_Ack 1 To enable this interrupt set G1_Gate_Interrupt_Enable 1 Else if Soft_Copy AO_BC_TC_Interrupt_Enable is 1 then
589. t function properly if an interrupt occurs between the time that the address is loaded into the Window Address Register and the time that an access is made from the Window Data Register Make sure that the interrupt does not disturb the Window Address Register during this sensitive period To do this disable interrupts during windowed mode accesses or write the interrupt routines so that they do not disturb the contents of the Window Address Register 1 6 2 Programming the Digital Interface The DAQ STC has eight DIO lines corresponding to pins DIO lt 0 7 gt and a digital output line EXTSTROBE SDCLK The eight DIO lines can be configured for input or output on an individual basis DIO4 can be used for 8 bit serial digital input and line DIOO can be used for 8 bit serial digital output To program the eight DIO pins for input or output use the following function DAQ STC Technical Reference Manual 7 6 National Instruments Corporation Chapter 7 Digital 1 0 Function DIO Pin Configure DIO Pins Dir ijkImnop where i j J m n o and p are all binary digits so that ijklmnop is an eight digit binary number Use 0 to program a line for input and 1 to program it for output Note that i corresponds to pin DIO7 j to pin DIO6 and so on Warning You must be very careful when programming bidirectional pins for output If an external signal is driving a bidirectional pin and you configure the pin for output you may caus
590. t mode to verify connectivity between the board traces and the package pins Each of the input bidirectional pins is connected to an internal gate tree The output of the tree appears on the pin TEST OUT The internal gate tree consists of multiple two input AND gates connected to an OR structure Figure 10 7 shows the structure of the internal gate tree DAQ STC Technical Reference Manual 10 6 National Instruments Corporation Chapter 10 Miscellaneous Functions RESET cS RD WR JU WR DS 2 TEST_OUT STATUS2 STATUS3 G_UP_DOWNO G_UP_DOWN1 JG Figure 10 7 Test Mode Internal Gate Tree To check input pin connectivity using the in circuit test mode use the following procedure 1 Bring TEST_IN high This setting tri states all of the output pins except TEST_OUT 2 Bring the RESET pin and all of the pins listed in Table 10 2 low TEST OUT will be high 3 Foreach pin pair listed in Table 10 2 perform the following steps Bring both members of the pair high TEST OUT will be low b Toggle the first member of the pair low then high Observe the change on TEST OUT c Toggle the second member of the pair low then high Observe the change on TEST OUT d Bring both members of the pair low TEST OUT will be high National Instruments Corporation 10 7 DAQ STC Technical Reference Manual Chapter 10 Misc
591. t the end of the current MISB then AO_UI_Switch_Load_On_BC_TC 1 ao_last_load_register Else Inform user that rate change is impossible at this time Else DAQ STC Technical Reference Manual 3 34 National Instruments Corporation Chapter 3 Analog Output Timing Control If Next Load Source St is 1 then AO UI Load A number of clocks between updates 1 If change update rate immediately then AO UI Switch Load On 1 Else if change update rate at the end of the current MISB then AO UI Switch Load On 1 ao last load register Else Inform user that rate change is impossible at this time End critical section To change the update rate immediately you must perform at least one update using the previous update interval before a change is possible The other option is to change the update rate at the end of the current MISB 3 6 4 Master Slave Operation Considerations for Primary Analog Output Group You can use several DAQ STCs for synchronized analog output operation To do this use the RTSI connection to connect the trigger signal to the trigger input of the master DAQ STC Also connect the output equivalent of the trigger from the master DAQ STC to the slave DAQ STCs You must perform the programming sequence described in section 10 8 1 Programming Clock Distribution before you execute the sequence given here Use this programming s
592. te Name Description Minimum Maximum Tgtclki External gate to SI2_Source setup internal 0 Tgtclke External gate to CONVERT_SRC setup 5 external All timing values are in nanoseconds Figure 2 42 Free Run Gating Mode Timing Internal CONVERT National Instruments Corporation 2 109 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control In external CONVERT mode the external gate is synchronized to the active edge of CONVERT SRC Figure 2 43 shows the timing for free run gating mode with an external CONVERT 4 Tgiclke 4 CONVERT START STOP CONVERT E External Gate Name Description Minimum Maximum Tgtclki External gate to SI2_Source setup internal 0 Tgtclke External gate to CONVERT_SRC setup 5 external timing values are in nanoseconds Figure 2 43 Free Run Gating Mode Timing External CONVERT The shaded areas in Figures 2 42 and 2 43 indicate where those signals would be asserted had they not been gated off The recognition of the external gate signal in the free run gating mode is relative to the START signal DAQ STC Technical Reference Manual 2 110 National Instruments Corporation Chap
593. te to the DAC are associated with CPU driven analog output The CPU asserts CPUDACREQ to request a write to one of the output channels and CPUDACWR is the actual write signal AOFFRT AO data FIFO retransmit retransmits the analog output FIFO DAQ STC Technical Reference Manual 3 4 National Instruments Corporation Chapter 3 Analog Output Timing Control contents in the local buffer mode TMRDACREQ DAQ STC data request indicates that there is no data available for the timer initiated write to the DAC The signals DACWR O 1 DAC write strobe serve as write strobes for the DACs combining the timer and CPU initiated writes The signals LDAC lt 0 1 gt DAC Load serve as DAC updates in the two DAC board case and can be configured to output primary or secondary UPDATE The AO data FIFO request output is used to generate a DMA request based on the analog output FIFO flags AOFEF AO data FIFO empty flag AOFHF AO data FIFO half full flag and AOFFF AO data FIFO full flag Sequences of UPDATE pulses are organized into buffers The value in the UC counter indicates the number of data points contained in each buffer and the value in the BC counter indicates the number of buffers to be generated The UI2 counter realizes an independent secondary analog output function generating UPDATE2 secondary update pulses based on software programming The STARTI trigger signal begins the primary and secondary analog output sequence
594. ted in your computer Use these manuals for hardware installation and configuration instructions specification information about your DAQ hardware and application hints Software manuals Examples of software manuals you may have are the LabVIEW and LabWindows CVI manual sets and the NI DAQ manuals After you set up your hardware system use either the application software LabVIEW or LabWindows CVI manuals or the NI DAQ manuals to help you write your application If you have a large and complicated system it is worthwhile to look through the software manuals before you configure your hardware Accessory manuals If you are using accessory products read the terminal block and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you are making your connections SCXI chassis manuals If you are using SCXI read these manuals for maintenance information on the chassis and installation instructions Related Documentation The following National Instruments documents contain general information and operating instructions for the DAQ STC DAQ STC Technical Reference Manual The AT E Series Register Level Programmer Manual The AT E Series User Manual xxvi National Instruments Corporation About This Manual e PCIE Series Register Level Programmer Manual e Application Note 010 Programming Interrupts for Data Acquisition on 80x66 Based Computer
595. ter 2 Analog Input Timing Control Figure 2 44 shows the timing for the halt gating mode with an internal CONVERT where the SD source and SI source are the same signal 4 rock 4 rock sesoee J LI LI LIII LJ LI LI LI I 4 P SI CNT 2 1 1 1 1 0 N N 1 N 2 N 3 START CONVERT External Gate Name Description Minimum Maximum Tgtclk External gate to SI2_Source setup internal 0 Tgtoff Gate off a scan 0 Tgton Gate on a scan 0 timing values are nanoseconds The numbers in parentheses refer to the number of clock periods because those parameters are clock edge driven Figure 2 44 Halt Gating Mode Timing Internal CONVERT The gate signal is always latched and recognized in the level sensitive synchronous mode and is qualified by the SCAN IN PROG signal A change in the GATE signal is not used internally while the SCAN PROG signal is asserted The recognition of the external gate signal in halt gating mode is relative to the source clock and the SI counter The external gate signal is latched on the falling edge and used on the rising edge but it must be recognized prior to or at the same source clock edge as the SI counter counting down to zero The SI counter stops at one and remains there until the external gate signal is deasserted At that point the SI counter will decr
596. ter begins in state WAITI and remains there until the counter is armed and a STARTI pulse is received When these two events occur the counter transitions to state WATT2 to wait for START to be asserted Once START is received the counter transitions to state CNT and begins counting When STOP is received the counter returns to the WAIT2 state to wait for another START National Instruments Corporation 2 127 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control The SI2 load signal SI2 LOAD enables the SI2 counter to reload from the selected load register on the next clock 512 LOAD is asserted when 512 TC is reached or is asserted by software The 512 count enable signal SI2 CE allows 512 counter to count 512 CE is asserted on any transition terminating at the CNT state provided that the SI2 counter is armed The 512 disarm signal 512 DISARM clears the SI2 Arm bit in the register map SI2 DISARM is asserted on the transition from the CNT state to the WAITI state when AI End On End Of Scan AI End On SC TC or AI Trigger Once is high AB DA 9 opp WAIT1 77 7777 51 5 1 ALSI2 Arm qe 5 ABE E SI2 TC c i F START S Y WAIT2 mad G SC TC End On End Of Scan On SC TC EMT J Continuous GARDE a STOP gt N Al_Trigger_Once gt T GH HTJ 512
597. ter can belong to a bitfield The high and low pairs of load and save registers for 24 bit counters are also treated as bitfields The AOTM related bitfields are described below Not all bitfields referred to in section 3 6 Programming Information are listed here To locate a particular bitfield description within this manual refer to Appendix B Register Information 0 Analog Trigger Reset bit 15 type Strobe AO Command 1 Register address 9 This bit clears the hysteresis registers in the analog trigger circuit Set this bit to 1 at the time you arm the analog output counters if you want to use analog triggering in hysteresis mode for any analog output signal Before setting this bit to 1 make sure that the analog trigger is not being used by some other part of the DAQ STC This bit should not be set to 1 in any other case This bit is cleared automatically National Instruments Corporation 3 45 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 AOFREQ Enable bit 12 type Write in AO START Select Register address 66 This bit enables the AOFREQ output signal 0 Disabled The signal is forced to the inactive value determined by AO AOFREQ Polarity 1 Enabled Related bitfields AOFREQ Polarity AOFREQ Polarity bit 9 type Write in AO Personal Register address 78 This bit selects the polarity of the AOFREQ output signal 0 Active high 1 Active low 0 BC Arm bit
598. ternal START source Similarly the STOP pulse may come from the DIV counter internal STOP source or the PFI selector external STOP source The SCAN IN PROG output indicates that a scan is in progress by asserting on START and deasserting on STOP The SC counter is available to count the number of scans that have occurred This is useful for generating a specific number of scans in an acquisition The START trigger signal begins the acquisition sequence and may come from one of several sources PFI RTSI software or general purpose counter 0 2 4 Analog Input Functions 2 4 1 The AITM is a highly flexible circuit that can accommodate a variety of timing scenarios The most useful of these is the interval scanning mode For this reason the functional description will present interval scanning as the primary analog input mode For the purpose of discussion the analog input functions can be divided into three groups low level timing and control scan level timing and control and acquisition level timing and control Low level timing and control refers to the timing signals related to and derived from CONVERT Scan level timing and control refers to the timing signals necessary to organize the CONVERT pulses into scans Acquisition level timing and control refers to the timing signals that govern the generation of scan sequences Low Level Timing and Control This section discusses CONVERT and the signals derived from CONVERT Th
599. terrupt_Enable 15 1 then National Instruments Corporation 8 7 DAQ STC Technical Reference Manual Chapter 8 Interrupt Control If AI STARTI Stis 1 then The interrupt was caused by AI START signal Service the AI START interrupt To clear this interrupt set AI_START1_Interrupt_Ack 1 To enable this interrupt set AI STARTI Interrupt Enable 1 Else if Soft_Copy AI_START2_Interrupt_Enable is 1 then If AI_START2_St is 1 then The interrupt was caused by AI START2 signal Service the AI START2 interrupt To clear this interrupt set AI_START2_Interrupt_Ack 1 To enable this interrupt set AI_START2_Interrupt_Enable 1 Else if Soft Copy AI Error Interrupt Enable is 1 then If Overrun Stis 1 or AI Overflow St is 1 then The interrupt was caused by one or both errors Service the AI error interrupt To clear this interrupt set Error Interrupt 1 To enable this interrupt set Error Interrupt Enable 1 Else if Soft Copy AI STOP Interrupt Enable is 1 then If AI STOP St is 1 then The interrupt was caused by AI STOP signal Service the AI STOP interrupt To clear this interrupt set AI STOP Interrupt Ack 1 To enable this interrupt set AI STOP Interrupt Enable 1 Else if Soft Copy AI START Interrupt Enable is 1 then If AI START Stis 1 then The interrupt was caused by AI START signa
600. ters associated with it Instead these functions will be carried out by software The UI2 counter can select either general purpose counter output as the source clock and the UI2 counter s toggled output can gate either of the two general purpose counters There are five timing and control signals associated with the analog output These signals are STARTI the update clock UPDATE the update interval clock UI source the secondary update interval clock UI2 source and the secondary external gate The AOTM contains independent multiplexers and conditioning circuits to derive these timing and control signals from any of 10 PFI signals seven RTSI trigger signals or other internal signals For more information about devices with which the AOTM can work read section 1 1 2 Analog Output Application in Chapter 1 Introduction National Instruments Corporation 3 1 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 3 1 1 Programming the AOTM To program the AOTM module of the DAQ STC read section Analog Output Application and read this chapter through section 3 6 Programming Information 3 2 As you read section 3 6 Programming Information you will need to refer to section 3 7 Timing Diagrams You will also need to consult the register level programmer manual for the device containing the DAQ STC You should not have to read section 3 8 Detailed Description Features The AOTM has the following
601. th measurement Gi Gating Mode 1 Gi_Gate_On_Both_Edges 0 Gi_Trigger_Mode_For_Edge_Gate 3 Gi_Stop_Mode 0 Gi Counting Once 0 Gi Up 1 Gi Bank Switch Enable 0 Gi Bank Switch Mode 0 Gi TC Interrupt Enable 0 Gi Gate Interrupt Enable 1 The gate interrupt notifies the CPU after each counting interval so that the ISR can read the results from the HW save register The ISR first checks for a stale data error indicating that the gate action was too quick to be measured by the source clock In this case the ISR ignores the counter value and writes O into the buffer The ISR then checks for a rollover error and a gate acknowledge latency error Use this function as an ISR for buffered period semiperiod and pulsewidth measurement Function Period And Semi Period And Pulse Width Measurement ISR Declare variables save 1 holds the save register value g_buffer_done indicates whether the measurement is complete save 1 Gi HW Save Register If Gi Stale Data St is 1 then stale data no source transitions between two relevant gate edges save_1 0 If buffer done is 0 AND buffer is not full then National Instruments Corporation 4 27 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer Write save 1 into the current position in the buffer Increment the pointer to the current position in the buffer If all the poin
602. th the START interrupt GO TC Interrupt Interrupts are generated on the leading edge of the G_TC signal from general purpose counter 0 GO Gate Interrupt Interrupts are generated on the G CONTROL signal from general purpose counter 0 Refer to section 4 8 7 Gate Actions for a complete description National Instruments Corporation 8 15 DAQ STC Technical Reference Manual Chapter 8 Interrupt Control Table 8 2 Interrupt Condition Summary Continued Interrupt Condition AO FIFO Interrupt Interrupts are generated on the analog output FIFO condition indicated by FIFO Mode bitfield AO Error Interrupt Interrupts are genInterrupts are generated on the analog output FIFO condition indicated by AO FIFO Mode bitfield erated on the detection of an analog output overrun error condition AO UD TC Interrupt Interrupts are generated on the trailing edge of the internal AO signal UPDATE2 AO UC TC Interrupt Interrupts are generated on the leading edge of the internal AO signal UC TC AO BC Interrupt Interrupts are generated on the trailing edge of the internal AO signal BC TC AO UPDATE Interrupt Interrupts are generated on the trailing edge of the internal AO signal UPDATE AO START Interrupt Interrupts are generated on AO STARTI pulses recognized by the AOTM AO START is recognized on the active edge of the internal AO signal BC_CLK G1 TC Interrupt Interru
603. that must occur before START2 can be recognized The second parameter gives the posttrigger count requirement that is the number of scans that will occur after 5 2 is recognized DAQ STC Technical Reference Manual 2 14 National Instruments Corporation Chapter 2 Analog Input Timing Control The 5 pulse initiates the scan sequence After the pretrigger count requirement has been satisfied the DAQ STC looks for the 5 2 trigger while continuing to generate scans When the START trigger has been received the hardware generates a specific number of additional scans according to the posttrigger count requirement Pretrigger acquisitions can be retriggerable or nonretriggerable In the retriggerable mode additional pulses initiate additional acquisition sequences In the nonretriggerable mode only one acquisition sequence is allowed Alternatively STARTI can come from general purpose counter 0 Figure 2 12 shows a single pretrigger acquisition sequence with a pretrigger count requirement of four scans and a posttrigger scan requirement of three scans The total number of scans acquired before START2 occurs is six because the START trigger occurs after the sixth scan but before the start of the second scan The vertical lines indicate where the SC counter transitions occur START1 START2 Don t Care START
604. the interrupt You will find suggestions for interrupt servicing programs in the other chapters of this manual Keep a record of interrupts that you enable so that you can determine which condition caused the interrupt You should have software copies of all the relevant write only registers It is assumed that you want to service every condition that can cause an interrupt For instructions on programming the physical interrupt interface circuitry see section 8 4 1 Programming the Interrupt Interface For information on how your system uses the DAQ STC interrupts consult your hardware and computer manuals Conditions that can cause interrupts are divided into group A and group B Group contains conditions generated by or related to analog input control and timing circuitry general purpose counter 0 and pass through interrupt 0 Group B contains conditions generated by or related to analog output control and timing circuitry general purpose counter 1 and pass through interrupt 1 You can enable the two groups independently and you can choose any of the eight interrupt levels for each group or the two groups can share an interrupt level The following sections present the functions that should be executed when an appropriate interrupt is asserted National Instruments Corporation 8 5 DAQ STC Technical Reference Manual Chapter 8 Interrupt Control 8 4 2 1 Interrupt Program If both groups are enabled and share the same inte
605. the master board to use the OSC pin as the clock input and to output the clock on the RTSI OSC pin If boards are to be used in master slave mode they should use the OUTBRD OSC pin as their local clock source When programming the RTSI OSC pins on several DAQ STCs you must program the slave DAQ STCs before the master DAQ STC If the DAQ STC is supplied with an IN TIMEBASE signal you can use an additional slower internal timebase IN TIMEBASE2 This timebase is obtained by dividing the IN TIMEBASE frequency by 100 or 200 If the slow internal timebase is disabled and you select slow internal timebase IN_TIMEBASE2 for any purpose you will get a unchanging signal instead of a timebase You cannot perform hardware controlled serial digital I O if the slow internal timebase is disabled Use the following function to select the various timebase options Function MSC Clock Configure Slow_Internal_Timebase 0 disable IN TIMEBASE2 and SERIAL TIMEBASE or 1 enable IN TIMEBASE2 and SERIAL TIMEBASE Slow Internal Time Divide By 2 0 do not divide by two or 1 divide by two Clock Board 0 disable OUTBRD pin or 1 enable OUTBRD pin Clock To Board Divide 2 0 do not divide by two or 1 divide by two RTSI Clock Mode 0 OSC is input or 1 OSC is input RTSI_OSC is output or 2 slave clock or 3 master clock A Warning You must be very careful when programming bidirectional pins for o
606. the AOTM The AOTM contains four special purpose counters the BC UI UI2 and UC counters Each counter has dual load registers A and B to handle two parameters for each timing layer In addition to the counters the primary logic blocks are the counter control blocks the trigger block the interrupt control block and the output control block DAQ STC Technical Reference Manual 3 108 National Instruments Corporation Chapter 3 Analog Output Timing Control BC Load A BC Load B I I LOAD SRC Y Y STARTI STARTI gt B sccE MUX 4 STOP STOP Conal a BC TC IRQ_OUT lt 0 7 gt 4 BC Counter p e Interrupt BC BC HOLD Control BC_SRC gt BC Save Ul Load A UI Load B I START Ul LOAD SRC DE I Trg Src SEL EXT_GATE Ul CE UL TC ULSRC Control UI CLK UI Counter ecr r gt Losic gt Uu Tc gt STARTI AO IN TIMEBASE UNE IN TIMEBASE2 gt Routing gt niece UC Load A UC Load B PFI lt 0 9 gt gt Logic SRG START Y RTSI TRI LOAD SRC TRIGGER lt 0 6 gt gt gt EXT GAT S BC TC UC CE MUX EXT GATE Control GK TC BG SRC Logic UC Counter
607. the CPU bus cycle will be extended to the next write slot Figure 3 4 shows a DAQ STC driven analog output sequence a board configured with eight channels interrupted by a CPU driven analog output to DAC number 9 UPDATE TMRDACWR AO_ADDR lt 3 0 gt 0 X1xXx2X3X9X4X5X6X7X CPUDACREQ CHRDY OUT CPUDACWR Figure 3 4 DAQ STC and CPU Conflict National Instruments Corporation 3 7 DAQ STC Technical Reference Manual Chapter 3 3 4 2 3 4 3 Analog Output Timing Control DAC Interface In addition to TMRDACWR and ADDR O 3 the DAQ STC provides four other pins that can be used to interface to the DACs The DACWR O 1 pins serve as DAC write strobes by pulsing on each TMRDACWR pulse and on each CPUDACWR pulse Two modes are available for the DACWR lt 0 1 gt signals single DAC mode and dual DAC mode The single DAC mode supports two distinct DACs In the single DAC mode DACWRO pulses on every write to an even channel and DACWRI pulses on every write to an odd channel The dual DAC mode supports two DACs that are contained in a single package In the dual DAC mode DACWRO pulses on every write and DACWR1 is not used The LDAC O 1 pins serve as DAC updates when the DACs are configured for double buffered output Two update modes are available for the LDAC lt 0 1 gt signals timed update mod
608. the secondary interrupt bank 0 Disabled 1 Enabled This bit is currently not supported and it must be set to 0 0 STOP St bit 2 type Read in Joint Status 2 Register address 29 This bit indicates that a valid STOP trigger has been received by the AOTM 0 No 1 Yes This bit is currently not supported and its setting is undefined TMRDACWRSs In Progress St bit 5 type Read in Joint Status 2 Register address 29 This bit indicates whether the TMRDACWR sequence initiated by an UPDATE or by setting AO Not An UPDATE to 1 has completed 0 Completed 1 n progress You can poll this bit if you want to wait on the DAC loading before arming the analog output counters 0 TMRDACWR Pulse Width bit 12 type Write in AO Personal Register address 78 This bit selects the pulsewidth of the TMRDACWR CPUDACWR and DACWR O 1 signals 0 3AO OUT TIMEBASE periods 1 2 TIMEBASE periods 0 Trigger Length bit 11 type Write in AO Mode 3 Register address 70 This bit selects the signal appearing on the bidirectional pin PFI6 AO_START1 when the pin is configured for output 0 Output the internal signal STARTI 1 Output the internal signal STIED after it has been pulse stretched to be 1 2 AO OUT TIMEBASE periods long National Instruments Corporation 3 67 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control 0 Trigger Once bit 0 type Write in AO Mod
609. then the stale data error Gi Stale Data St is set because the GATE event was too quick to be measured by the SOURCE timebase 4 8 10 3 Permanent Stale Data Error The permanent stale data error indicates that GATE signal was not measured properly at some point in a sequence of measurements In several functions for example buffered pulsewidth measurement and buffered period measurement the counter uses the SOURCE pulses to count the duration of a repetitive event on the G_GATE signal The stale data error indicates an error at a particular G_GATE edge but may be cleared later while the permanent stale data error detects this situation If the stale data error is set at any point in arepetitive measurement then the permanent stale data error Permanent Stale Data St is set to indicate that a measurement error occurred at some point in the sequence National Instruments Corporation 4 71 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 8 10 4 TC Latency Error This error indicates that some programming action related to the TC was not performed in time In several functions for example buffered pulse train generation with software programming the software performs some action on the counter while the counter is running and the action must complete before the counter TC is reached If the counter TC is reached before the software is able to confirm the programming see TC Interr
610. ticks number of clocks between updates new mute indicates whether the MISB will be muted ao shut down isr indicates the last TC in the stage and the next to the last BC TC in the stage as follows 2 The last BC TC 1 The next to the last BC_TC 0 Otherwise old_stage_uc_ticks the number up updates in the previous buffer If ao_shut_down_isr is 2 then ao shut down isr 0 If ao shut down isr is 1 then ao shut down isr 2 new bc ticks bc new ticks ao tick count to use If new ticks is 0 then ao shut down isr l If ao shut down 15 is 1 then AO_End_On_BC_TC 1 ao_tick_count_to_use 0 new bc ticks new ticks ao tick count to use new ticks uc new ticks ao tick count to use new ui ticks new ticks ao tick count to use new mute new mute flag ao tick count to use If ao shut down isr is 1 then new uc ticks new uc 1 1 If ao shut down isr is 2 then old stage uc ticks new ticks ao tick count to use l If ao 1oad register is A then AO BC Load B new ticks l AO UC Load B new uc ticks l AO UI Load B new ui ticks 1 AO Mute B new mute If ao shut down isr is 2 then AO UC Load oid stage uc ticks l ao last load register Else AO_BC_Load_A new bc ticks 1l AO UC Load new uc ticks l AO UI Load new ui ticks l AO Mute A new
611. ting period measurement pulsewidth measurement pulse generation and pulse train generation Enhancements to the existing counter timer functions include ETS timing output relative time stamping and the ability to perform buffered mode operations 4 4 1 Event Counting In event counting functions the counter counts events on SOURCE input following the software arm The software arm occurs when software sets the counter arm bit in the DAQ STC register map The following actions are available in event counting SOURCE increments or decrements the counter e indicates when to start and stop counting intervals or when to save the counter contents in the save register software either reads the counter value asynchronously or reads the save register each time the hardware latches the counter value In the latter case interrupts notify the software that a save has occurred G UP DOWN controls the direction of the counting National Instruments Corporation 4 8 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 4 1 1 Simple Event Counting In simple event counting the counter counts the number of pulses that occur on the SOURCE signal after the software arm Software can read the counter contents at any time without disturbing the counting process Figure 4 2 shows an example of simple event counting where the counter counts five events on G SOURCE
612. tion Summary esee 8 15 Table 9 1 DTT N eS A dutem tende 9 2 Table 9 2 Intel Bus Interface Timing 9 6 Table 9 3 Intel Bus Interface 9 8 Table 10 1 Timebases Derived from IN_TIMEBASE Hm 10 2 Table 10 2 Test Mode Input Pin Pairs 2 10 8 Table 10 3 Pin Interface 10 9 DAQ STC Technical Reference Manual XX National Instruments Corporation Contents Table B 1 DAQ STC Registers 1 ecce tete heiter re Retina B 1 Table B 2 Registers in Order of B 5 Table B 3 Bitfield Description Guide sese B 9 Table C 1 DAQ STC Pins in Alphabetical Order sees C 1 Table C 2 Summary of Buffer Types ecce eee ciet eite C 7 National Instruments Corporation DAQ STC Technical Reference Manual About This Manual The DAQ STC is an application specific integrated circuit ASIC designed by National Instruments The DAQ STC Technical Reference Manual describes the programmable features of the DAQ STC and is intended for programmers who need to program the DAQ STC on an existing data acquisition DAQ board and for hardware engineers who want to design a board using the DAQ STC Before using this manual to program the DAQ STC on an existing board you should be familiar with the board that contains your DAQ STC You should begin by reading the user manual for the board containing the DAQ STC Next read the register level p
613. tion has occurred The bit is set on the SHIFTIN following the SC TC trailing edge It is cleared by setting AI SC TC Interrupt Ack to 1 Related bitfields AI SC TC Interrupt Ack CF Note If the SC CLK is slow with respect to the conversion period the trailing edge of SC TC may miss the SHIFTIN pulse This can happen in the internal CONVERT mode if you select IN as the SI2 source For this reason you must not rely on this bit as an end of acquisition indicator LOCALMUX Output Select bits lt 4 5 gt type Write in AI Output Control Register address 60 The bitfield enables and selects the polarity of the LOCALMUX output signal 0 HighZ 1 Ground 2 Enable active low 3 Enable active high LOCALMUX Pulse bit 2 type Strobe AI Command 1 Register address 8 Setting this bit to 1 produces a pulse on the LOCALMUX output signal if the output is enabled The pulsewidth of the output signal is determined by AI LOCALMUX CLK Pulse Width LOCALMUX must also be cleared by an SOC This bit is cleared automatically Related bitfields AI LOCALMUX Output Select AI LOCALMUX CLK Pulse Width LOCALMUX CLK Pulse Width bit 5 type Write in AI Personal Register address 77 This bit selects the pulsewidth of the LOCALMUX FFRT output signal and the minimum pulsewidth of the LOCALMUX CLK output signal 0 LOCALMUX FFRT is 0 5 1 AI OUT TIMEBASE periods and
614. tion of the third scan had it not been gated off START1 External Gate STARTS blocked START STOP CONVERT RRRA Figure 2 13 Free Run Gating Mode 2 4 4 2 Halt Gating Mode Halt gating mode is available only when the START signal is generated internally In the halt gating mode the delay from the assertion of the external gate to the next CONVERT is minimized The SI counter counts down normally until it reaches a count value of one At this point the behavior of the SI counter depends upon the external gate If the external gate is deasserted the SI counter pauses so that no START pulses are generated When the external gate asserts the START occurs immediately with jitter of up to one SI source clock period The external gate works as a pseudotrigger for a scan in this mode National Instruments Corporation 2 17 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control Figure 2 14 shows three scans where the second scan has been delayed by the action of the external gate START is asserted immediately upon the assertion of the external gate START1 External Gate START SI TC SI Counter Paused STOP CONVERT Figure 2 14 Halt Gating Mode 2 4 5 Single Wire Mo
615. tive This can happen when FIFO read rate does not keep pace with the FIFO write rate If the overflow error occurs at least one point of data has been lost 2 8 5 3 SC TC Error During staged analog input the software loads the parameters for each posttrigger acquisition sequence during the previous acquisition sequence The software must complete this programming operation before the end of the current acquisition sequence An SC TC error occurs when the parameters for the next sequence are not written in the allotted time The error detection circuit is armed on each SC TC If a software clear AI SC TC Interrupt Ack does not occur before the next 5 the error detection circuit latches an error condition DAQ STC Technical Reference Manual 2 132 National Instruments Corporation 2 8 6 Nominal Signal Pulsewidths Table 2 12 lists the nominal pulsewidths for the signals associated with analog input Note that only the CONVERT signal can use either the source or output clocks all of the others must use the indicated clock source These are only the nominal pulsewidths the actual synchronization edges and propagation delays are detailed in section 2 7 Timing Diagrams Chapter 2 Analog Input Timing Control Table 2 12 Analog Input Nominal Signal Widths Signal Source Clock Output Clock CONVERT 1 1 2 5 1 2 SC TC 1 LOCALMUX CLK 1 or 2 to SOC EXTMUX CLK L
616. tive Low Active High Ground High Z Related bitfields AI CONVERT Output Select AI CONVERT Pulse AI CONVERT Original Pulse AI CONVERT Pulse Timebase AI CONVERT Pulse Width DIV TC O4TU DIV Counter TC Signal Output polarity is active high Related bitfields Misc_Counter_TCs_Output_Enable DAQ STC Technical Reference Manual 2 20 National Instruments Corporation Chapter 2 Analog Input Timing Control Table 2 1 Pin Interface Continued Pin Name Type Description EOC IU End of Conversion This input indicates that a conversion is complete Internally the EOC signal causes the SHIFTIN pulse to be generated and causes the overrun error detection circuitry to end the overrun detection interval in overrun mode 0 The input polarity is selectable and the input state can be directly observed in one of the status registers Source ADC Related bitfields Polarity 51 AI Overrun Mode EXTMUX CLK 09 0 External Multiplexer Clock This output pulses after each CONVERT to clock an external multiplexer such as the AMUX 64 causing the multiplexer to switch to the next entry in the external scan list Two output modes are available for the EXTMUX_CLK output In the first mode EXTMUX_CLK trails the LOCALMUX_CLK pulse by 0 5 1 5 AI OUT TIMEBASE periods and has a pulsewidth of 4 5 AI OUT TIMEBASE periods In the second mode EXTMUX CLK and LOCALMUX CLK are ass
617. to select the signal that you want to use as a reference clock Program the Gi Gate to select the signal on which you want to measure the period semiperiod or pulsewidth Function Bu fered Period And Semi Period And Pulse Width Measurement Gi_Load_Source_Select 0 Gi_Load_A initial counter value Load 1 L Gi Source Select 0 or through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 IN_TIMEBASE2 or 19 other G_TC Gi_Source_Polarity 0 count rising edges or 1 count falling edges Gi_Gate_Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 AI START2 or 19 UI2_TC or 20 other G TC or 21 AI START or 31 Logic low OR Gate 0 Gi Output Polarity 0 active low or 1 active high Gi Gate Select Load Source 0 Gi Gate Polarity 0 disable inversion or 1 enable inversion Gi Output Mode 1 one clock cycle output or 2 toggle on TC or 3 toggle on TC or gate Gi Reload Source Switching 0 Gi Loading On Gate 1 Gi Loading On TC 20 DAQ STC Technical Reference Manual 4 26 National Instruments Corporation Chapter 4 General Purpose Counter Timer If buffered period measurement then Gi Gating Mode 2 Gi Gate On Both Edges 0 Else if buffered semiperiod measurement then Gi Gating Mode 3 Gi Gate On Both Edges 1 Else Buffered pulsewid
618. to 2 85 START trigger and SCAN IN PROG assertion 2 100 to 2 103 START and START triggers 2 97 to 2 100 STOP trigger 2 103 to 2 104 trigger output 2 97 to 2 104 analog output timing control module 3 84 to 3 108 counter outputs 3 107 to 3 108 CPU driven analog output timing 3 88 DAQ STC and CPU driven analog output timing 3 90 to 3 02 DAQ STC driven analog output timing 3 86 to 3 88 decoded signal timing 3 94 to 3 95 external trigger timing 3 102 to 3 104 local buffer mode timing 3 96 to 3 97 maximum update rate timing 3 101 to 3 102 secondary analog output timing 3 93 signal definitions 3 84 to 3 86 trigger output 3 104 to 3 107 unbuffered data interface timing 3 98 to 3 100 bus interface module 9 5 to 9 8 Intel bus interface read timing figure 9 6 Intel bus interface timing table 9 6 to 9 7 Intel bus interface write timing figure 9 6 Motorola bus interface read timing figure 9 7 DAQ STC Technical Reference Manual Index Motorola bus interface timing unbuffered data interface 3 11 table 9 8 unbuffered data interface timing Motorola bus interface write timing 3 98 to 3 100 figure 9 8 trigger analog See analog trigger circuit digital I O 7 15 to 7 16 trigger output analog input timing control serial input timing 7 15 to 7 16 2 97 to 2 102 serial output timing 7 16 SCAN IN PROG deassertion 2 103 general purpose counter timer START trigger and SCAN IN PROG
619. to 3 22 AO Reset bit 3 60 to 3 61 Software Gate bit 3 61 AO Source Divide By 2 bit 3 61 AO Start Generation function 3 31 AO START Edge bit 3 61 START Interrupt bit 3 61 START Interrupt Enable bit 3 62 START Polarity bit 3 62 AO START Pulse bit 3 62 AO START Second Irq Enable bit 3 62 AO START Select bit 3 62 AO START St bit 3 63 AO START Stop Gate Enable bit 3 63 AO START Stop Gate St bit 3 63 AO START Sync bit 3 63 STARTI Disable bit 3 63 AO STARTI Edge bit 3 64 STARTI Interrupt bit 3 64 STARTI Interrupt Enable bit 3 64 STARTI Polarity bit 3 64 AO STARTI Pulse bit 3 64 AO STARTI Second Enable bit 3 65 AO STARTI Select bit 3 65 St bit 3 65 STARTI Sync bit 3 65 DAQ STC Technical Reference Manual 1 8 STOP Interrupt Ack bit 3 65 STOP Interrupt Enable bit 3 66 AO Stop On BC TC Error bit 3 66 AO Stop On BC TC Trigger Error bit 3 66 AO Stop On Error bit 3 66 AO STOP Second Irq Enable bit 3 67 STOP St bit 3 67 AO TMRDACWR Pulse Width bit 3 67 TMRDACWRs In Progress St bit 3 67 AO Trigger Length bit 3 67 AO Trigger Once bit 3 68 AO riggering function 3 23 to 3 24 AO UC Amm bit 3 68 AO UC Armed St bit 3 68 AO UC Initial Load Source bit 3 68 AO Load A bit 3 68 AO Load B bit 3 69 AO UC Load bit 3 68 AO UC Ne
620. to section 2 7 Timing Diagrams You will also need to consult the register level programmer manual for the hardware containing the DAQ STC If you need additional help programming the AITM read section 2 8 Detailed Description National Instruments Corporation 2 1 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 2 2 Features The AITM has the following features Scan interval timing 24 bit scan interval down counter Maximum frequency of 20 MHz yields 50 ns resolution with a maximum interval of 0 83 s Divide by two timebase yields 100 ns resolution with a maximum interval of 1 67 s Divide by 200 timebase yields 10 us resolution with a maximum interval of 167 s Sample interval counter 16 bit sample interval down counter Maximum sample rate of 10 MS s Maximum interval of 3 3 ms between channels with 50 ns resolution External timing for the following signals START STARTI START2 CONVERT SI source with special considerations for SI2 source STOP External gate Bidirectional external timing pins Input timing and control signals from PFI lt 0 9 gt and RTSI lt 0 6 gt A Output the most important internally generated timing and control signals to the board Programmable polarities for clock sources trigger inputs and the most important timing outputs Ability to change the scan rate during an acquisiti
621. to section 2 8 3 4 SI Control for the SI CE logic equations SI CLK SI Clock This is the actual clock for the SI counter and the SI control logic When the counter is not armed 51 CLK is derived from the write strobe for AI Command 1 Register so that the counter can be loaded using the load command When the counter is armed 51 is the same as SI SRC Related bitfields SI Load SI HOLD SI Hold This signal controls the SI save register If SI HOLD 0 then the SI save register tracks the SI counter output If SI HOLD 1 then the SI save register latches the SI counter output on the next SI CLK SI LOAD SI Load This signal pulses to load the value from the selected SI load register into the SI counter Related bitfields SI Load SI LOAD SRC SI Load Source This signal determines which load register or B the SI counter will use on the next reload The initial SI load source is set using AI SI Initial Load Source The SI control logic updates the load source while the DAQ STC is counting The current load source depends on the counter state and the selected reload mode Related bitfields AI SI Initial Load Source SI SRC SI Source This signal is the timebase for the SI counter Related bitfields SI Source Select SI STARTI STARTI Synchronized to SI SRC This signal is generated by the hardware by passing the output of the AI STARTI selector through
622. trigger signals 2 122 to 2 123 local buffer mode timing 3 96 to 3 97 analog output timing control module maximum update rate timing 3 101 3 114 to 3 116 serial link data interface 3 10 edge detection 3 116 simplified analog output model 3 4 DAQ STC Technical Reference Manual 1 38 National Instruments Corporation EXT GATE and EXT GATE2 routing logic figure 3 115 PFI selectors table 3 115 to 3 116 STARTI routing logic figure 3 115 synchronization 3 116 trigger signals 3 116 trigger signals programming analog input timing control module 2 32 to 2 33 primary analog output timing control module 3 23 to 3 24 triggers external See external trigger timing external triggers U UC counter control circuitry 3 119 description 3 118 to 3 119 UC CE signal table 3 112 UC signal table 3 112 UC DISARM signal table 3 112 UC HOLD signal table 3 112 UC LOAD signal table 3 112 UC LOAD 5 signal table 3 113 UC TC signal continuous mode 3 13 to 3 14 description table 3 113 local buffer mode 3 9 to 3 10 output timing figure 3 108 pin interface table 3 19 single buffer mode 3 13 UI counter control circuitry 3 118 description 3 117 internal UPDATE timing 3 11 to 3 12 UI CE signal table 3 113 UI CLK signal table 3 113 UI DISARM signal table 3 113 UI LOAD signal table 3 113 UI LOAD signal table 3 113 National Instruments Corporation Index UI
623. trolled serial digital I O 7 12 windowed mode register access example 7 7 to 7 8 serial mode 7 4 to 7 5 serial input 7 4 serial I O 7 5 serial output 7 4 to 7 5 DAQ STC Technical Reference Manual 1 20 serial output source select table 7 17 simplified model 7 1 to 7 2 specifications A 1 timing diagrams 7 15 to 7 16 serial input timing 7 15 to 7 16 serial output timing 7 16 DIO lt 1 3 gt signal table 7 6 DIO lt 5 7 gt signal table 7 6 DIO Clock Out function 7 12 DIO HW Serial Enable bit 7 13 DIO HW Serial Initialize function 7 10 to 7 11 DIO HW Serial Start bit 7 13 DIO HW Serial Timebase bit description 7 14 serial output source select table 7 17 DIO Parallel Data In St bit 7 14 DIO Parallel Data Out bit 7 14 DIO Parallel Out function 7 2 DIO Pin Configure function 7 9 DIO Pins Dir bit 7 14 DIO Serial Data In St bit 7 14 DIO Serial Data Out bit 7 14 DIO Serial Data Out function 7 10 DIO Serial In function 7 11 DIO Serial IO In Progress St bit 7 15 DIO Serial Divide 2 bit 7 15 DIO Software Serial Control bit 7 15 DIOO SDOUT signal table 7 6 DIO4 SDIN signal table 7 6 DIV counter control circuitry 2 129 to 2 130 description 2 128 DIV CE signal description table 2 114 DIV counter operation 2 129 DIV CLK signal table 2 114 DIV DISARM signal DIV counter operation 2 129 National Instruments Corporation DIV LOAD signal description table
624. truments Corporation Chapter 3 Analog Output Timing Control 3 4 3 3 Unbuffered Data Interface In the unbuffered data interface mode the DMA controller writes data directly to the DACs This mode is primarily used in low cost data acquisition boards that do not have a data FIFO The UPDATE signal performs the updating of the DACs as before The TMRDACWR signal becomes the DMA request indicating that new data is needed for the analog output The AOFEF input becomes the DMA acknowledge indicating that the DMA data is ready for the write The CPUDACWR signal pulses each time AOFEF asserts to write the DMA data to the DACs The TMRDACWR signal remains asserted until the completion of the last CPUDACWR Figure 3 8 shows an example of the unbuffered data interface mode where the DAQ STC writes output data to the first three DACs UPDATE 1 TMRDACWR 1 CPUDACWR 1 I AO_ADDR lt 3 0 gt g X1 X2 Figure 3 8 Unbuffered Data Interface 3 4 4 Update Timing for Primary Group Analog Output In DAQ STC driven analog output the UPDATE signal allows DACs for multiple channels to be updated simultaneously As discussed in section 3 3 Simplified Model of this chapter the UPDATE signal can be generated internally or externally This section discusses the internal and external UPDATE sources and the timing parameters associated with each source 3 4 4 1
625. ts have been written into the buffer then Gi_Disarm 1 buffer 1 Gi Gate Interrupt 1 If Gi Gate Error St is 1 then gate acknowledge latency error hardware saves are too fast Inform user that a gate acknowledge latency error has occurred Gate Error Confirm 1 If Gi_TC_St is 1 then rollover error counter value is not correct Inform user that a rollover has occurred Gi_TC_Interrupt_Ack 1 4 6 1 10 Pulse and Continuous Pulse Train Generation In pulse generation a counter generates a single pulse of specified duration and specified delay In continuous pulse train generation a counter generates a rectangular waveform of specified frequency and duty cycle Three modes of operation are defined for pulse generation single pulse generation single triggered pulse generation and retriggerable single pulse generation In single pulse generation the pulse is generated based on the software arm signal In single triggered pulse generation the pulse is generated based on a hardware trigger In retriggerable single pulse generation a pulse is generated on each hardware trigger active edge A fourth mode of operation buffered retriggerable single pulse generation is defined for the hardware but is not supported in this programming section Note Pulse and continuous pulse train generation mimic the behavior of the NI DAQ functions for the Am9513 counter chip No errors are d
626. ts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are
627. tting this bitto 1 causes the BC save register to latch the BC counter value at the next BC CLK falling edge Setting this bitto 0 causes the BC save register to trace the BC counter DAQ STC Technical Reference Manual 3 48 National Instruments Corporation Chapter 3 Analog Output Timing Control 0 BC Save Value bits lt 0 7 gt type Read in AO BC Save Registers address 18 bits lt 0 15 gt type Read in AO BC Save Registers address 19 When AO Save Trace is 0 this bitfield reflects the contents of the BC counter When you set AO BC Save Trace to 1 this bitfield synchronously latches the contents of the BC counter using the BC source The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related bitfields Save Trace 0 BC Source Select bit 4 type Write in AO Personal Register address 78 This bit selects the BC counter source 0 UPDATE 1 The internal signal UC TC You should normally set this bit to 1 Setting 0 is not currently supported 0 BC Switch Load On TC bit 4 type Strobe AO Command 2 Register address 5 Setting this bit to 1 causes the BC counter to switch load registers at the next TC This action is internally synchronized to the falling edge of the BC CLK This bit is cleared automatically 0 BC TC Error Confirm bit 4 type Strobe Interrupt Ack Register address 3 Setting this bit to 1 clears AO BC TC Error S
628. ty is selectable Destination DACs Options Active Low Active High Ground High Z Related bitfields AO_UPDATE2_Output_Select AO_UPDATE2_Output_Toggle AO_UPDATE2_Pulse AO UPDATE2 Original Pulse AO UPDATE2 Pulse Timebase AO UPDATE2 Pulse Width 3 6 Programming Information This section presents programming information that is specific to the AOTM For general information about programming the DAQ STC see section 2 6 Programming Information 3 6 1 Programming for a Primary Analog Output Operation This section contains detailed programming information for bit level programming of the primary AOTM for specialized applications The programs are presented in a bottom up fashion This section lists functions that can be used to configure the primary AOTM for various operations The functions are then assembled into a complete program in section 3 6 1 14 Primary Analog Output Program Most of the programming sequences presented here must be executed exactly as shown Bitfield assignment is a pseudocode instruction of the form bitfield name value Pseudocode sequences enclosed in braces that contain only bitfield assignments can normally be executed in any order or simultaneously if possible If the sequence must be executed in exact order the character marks the boundary between two groups of assignments that have to be executed sequentially For example in the following pseudocode the first bitfield
629. ui_new_ticks contains the number of clocks between updates in each MISB Function AO_Updating Begin critical section AO_Configuration_Start 1 If internal UPDATE mode then AO_BC_Gate_Enable 0 AO UPDATE Source Select 0 AO UPDATE Source Polarity 0 If UI source is AO TIMEBASEI1 then AO UI Source Select 0 AO UI Source Polarity 0 Else if UI source is IN TIMEBASE2 then DAQ STC Technical Reference Manual 3 26 National Instruments Corporation Chapter 3 Analog Output Timing Control AO Source Select 20 AO UI Source Polarity 0 Else AO UI Source Select 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI lt 0 6 gt AO UI Source Polarity 0 rising edge or 1 falling edge If waveform staging then AO_UI_Initial_Load_Source 0 AO UI Load A ui new ticks 0 1 gt AO UI Load 1 L AO UI Load B ui new ticks 1 1 AO UI Mode 7 Else AO Initial Load Source 0 AO UI Reload Mode 0 If there is no special delay from STARTI to first update then AO_UI_Load_A number of clocks between each update 1 AO UI Load 1 Else AO UI Load A number of clocks between START and first update 1 AO UI 1 AO UI Load A number of clocks between each update 1 If local buffer mode with pauses then AO_UI_Load_B number of clocks between each update
630. ulse or 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI lt 0 6 gt If AI START2 Select is 0 then AI START2 Polarity 0 AI START2 Edge 1 AI START2 Syncz 1 Else AI START2 Polarity 0 active high or rising edge or active low or falling edge AI START2 1 AI START2 Syncz 1 DAQ STC Technical Reference Manual 2 32 National Instruments Corporation Chapter 2 Analog Input Timing Control Else Trigger Selection AI STARTI Select 0 bitfield AI STARTI Pulse or 1 through 10 PFI lt 0 9 gt or 11 through 17 RTSI_TRIGGER lt 0 6 gt or 18 the OUT signal from general purpose counter 0 If AI STARTI Select is 0 then AI STARTI Polarity 0 AI 5 1 AI STARTI 5 1 Else AI STARTI Polarity 0 active high or rising edge or active low or falling edge AI STARTI 1 AI STARTI Syncz 1 AI Configuration End 1 End critical section 2 6 3 9 Number of Scans Use this function to select the number of scans to be acquired In a staged acquisition the number of scans to be executed in each stage is contained an array named sc ticks If the acquisition is staged this function will load the initial value of sc ticks into the SC load register to initialize the first stage The additional values in the array are written as needed by the interrupt routine see AI Staged ISR Function AT Number Of Scans
631. ulse Width The synchronization for UPDATE OUT counts a total of either three or seven output clock edges regardless of polarity The TMRDACWR signal can be set to two or three output clock periods which is an exact number see UPDATE Pulse Width There is no synchronization involved with this write signal The ADDR O 3 will change to the appropriate values upon the trailing edge of TMRDACWR CPU Driven Analog Output Timing The DAQ STC provides arbitration circuitry to prevent simultaneous access to the DAC data bus by both the CPU and the DAQ STC as well as timing signals for the actual write The primary output signals CHRDY OUT CPUDACWR and ADDR O 3 and the input signals are CPUDACREQ and the bus addresses A lt 1 4 gt The CPUDACREQ signal notifies the DAQ STC that a CPU write to a DAC is being requested CHRDY OUT is deasserted to delay the bus cycle and operates in two software selectable modes see AO Fast CPU In mode 0 OUT is asserted until the end of CPUDACWR In mode 1 CHRDY OUT is asserted only until the start of CPUDACWR which maximizes bus bandwidth In mode 1 if another request is made before the initial write is completed CHRDY is reasserted and held until the second write is started The bus address lines A lt 1 4 gt are passed through to the AO ADDR O 3 lines during the actual CPUDACWR This allows the board to only decode one set of address lines when both TMR
632. unt up or down Table 4 3 indicates the pin represented by U D based on internal selection Table 4 3 U D Reference Pin Selection Gi Up Down Mode Reference Pin 2 G UP DOWNi 3 Same reference pin as selected by CTRGATE Reference Pin Selection CTROUT refers to following pins e OUTO RTSI OUT e OUTI DIV TC OUT INTERRUPT refers to the following pins e IRQ OUT lt 0 7 gt e SEC_IRQ OUT lt 0 1 gt DAQ STC Technical Reference Manual 4 54 National Instruments Corporation Chapter 4 General Purpose Counter Timer 4 7 1 CTRSRC Minimum Period and Minimum Pulsewidth Figure 4 21 and the accompanying table indicate the minimum period and minimum pulsewidth for the general purpose counter source signal CTRSRC Tctrp Tctrpw CTRSRC Tctrpw Name Description Minimum Maximum Tctrp CTRSRC minimum period 50 Tctrpw CTRSRC minimum pulsewidth 6 timing values are in nanoseconds Figure 4 21 CTRSRC Minimum Period and Minimum Pulsewidth Note If simple loop counting is the only functionality required for the counter then the frequency of operation may be increased For simple loop counting the counter has been shown to function at CTRSRC periods as small as 33 ns 4 7 2 CTRSRC to CTROUT Delay Figure 4 22 and the accompanying table indicate the delay from the counter source signal CTRSRC to the counter
633. unter Gate G can come from two sources If OR Gate is set to 0 the hardware generates GATE by passing the output of the Gi Gate selector through polarity selection If OR Gate is set to 1 the hardware generates GATE by passing the output of the Gate selector through polarity selection and OR ing the result with the output of the other general purpose counter IN TIMEBASEI Internal Timebase G IN TIMEBASEI is the internal timebase for the general purpose counter timer module IN TIMEBASEI can be the same as IN TIMEBASE or it can be IN TIMEBASE divided by two Related bitfields Source Divide By 2 G SOURCE Counter Source The hardware generates SOURCE by passing the output of the Gi Source selector through polarity selection Related bitfields Source Select G TC Counter TC G is the actual general purpose counter TC signal G OUT Counter Output G OUT is the TC signal after output and polarity selection Related bitfields Output Mode Output Polarity DAQ STC Technical Reference Manual 4 62 National Instruments Corporation Chapter 4 General Purpose Counter Timer Table 4 4 Internal Signal Description Continued Signal Description IN TIMEBASE2 Slow Internal Timebase This timebase is derived from the IN TIMEBASE input and is usually configured to be 100 kHz Related bitfields Slow Internal Time Di
634. update timing for primary group 3 11 to 3 12 external UPDATE 3 12 internal UPDATE 3 11 to 3 12 UPDATE2 signal description table 3 20 secondary analog output timing 3 93 simplified analog output model 3 5 W waveform starting primary analog output operation 3 30 to 3 31 waveform staging buffer timing and control for primary analog output 3 14 to 3 15 primary analog output 3 32 to 3 34 secondary analog output 3 42 to 3 44 counting 3 40 windowed mode register access analog input programming considerations 2 25 digital I O programming example 7 7 to 7 8 WR DS signal table 9 3 WRITE 5 lt 0 3 gt signal description table 9 3 programming 9 4 DAQ STC Technical Reference Manual 1 40 National Instruments Corporation
635. upt Ack then the TC latency error is set 4 8 11 Detailed Operation by Application This section discusses the detailed operation of the counter for the GPCT applications Each description begins with a summary of how you program the counter to implement the application A short paragraph then describes the operation of the internal signals Finally a figure shows the explicit relationship between applied signals and internal signals for the application The G SOURCE signal is generated differently depending on whether you select internal timing or external timing When you select internal timing G SOURCE is simply the internal source clock When you select external timing the active edge of the external source generates both edges of G_SOURCE first the falling edge then the rising edge A delay gate determines the width of the G SOURCE negative pulse Figure 4 31 shows the relationship between SOURCE and the source clock for internal and external timing Internal Internal Source G SOURCE External External Source G SOURCE 1 Figure 4 31 G SOURCE Generation 4 8 11 1 Simple Event Counting In simple event counting the counter increments on every SOURCE rising edge following the ARM To read the counter contents use the save register DAQ STC Technical Reference Manual 4 72 National Instruments Corporation Chapter 4 General
636. upt Control 8 3 Pin Interface Table 8 1 lists the I O signals relevant to the ICM Pin Type Notation ID TTL input pull down 50 OD18U Output open drain 24 mA sink pull up 50 kQ Table 8 1 Pin Interface Pin Name Type Description lt 0 1 gt ID Individually Programmable Polarity General Purpose Interrupt Inputs lt 0 1 gt to the DAQ STC These inputs are enabled disabled via registers in the DAQ STC and passed on to the two interrupt groups in the DAQ STC Related bitfields Pass Thru Interrupt Enable Pass Thru Second Enable Pass Thru Interrupt Polarity lt 0 7 gt OD18U Programmable Polarity Interrupt Outputs lt 0 7 gt from the DAQ STC Two IRQ_OUT lines can be asserted simultaneously by the two interrupt groups in the DAQ STC when an unmasked interrupt condition is true Both interrupt groups can also share the same IRQ_OUT line in which case only one IRQ_OUT line will be asserted In addition OUTO and IRQ_OUTI can be enabled to be driven whenever any unmasked interrupt condition is true These two outputs can be tied together to increase the current sink capability as required by NuBus Destination CPU bus Related bitfields Interrupt_A_Output_Select Interrupt_A_Output_Enable Interrupt_B_Output_Select Interrupt_B_Output_Enable Interrupt_Output_Polarity Interrupt_Output_On_3_Pins SEC IRQ OUT BANKO OD18U Secondary Interrupt Output for I
637. ur board you should transfer data into that FIFO Refer to section 10 8 1 Programming Clock Distribution to set up your timebase Call AO Reset A11 Call AO Board Personalize Call AO Hardware Gating Call AO Triggering Call AO Counting Call AO Updating Call AO Channels Call AO LDAC Source And Update Mode Call AO Errors To Stop Call AO FIFO Call AO Interrupt Install National Instruments Corporation 3 31 DAQ STC Technical Reference Manual Chapter 3 3 6 2 Analog Output Timing Control Call AO Arming Call AO Start The Generation Waveform Staging for Primary Analog Output Waveform staging can be used to generate timing for a waveform stage consisting of many MISBs The DAQ STC has dual load registers for each analog output counter so that the software can load the parameters for the next MISB while the current MISB is still being output To accomplish this program the TC interrupt to call the AO Staged ISR ISR enable the BC TC interrupt you must make sure that an interrupt level is dedicated to the interrupt group and that interrupt group B is enabled Program the BC interrupt and interrupt group B as follows Interrupt_B_Output_Select 0 through 7 Interrupt_B_Enable 1 AO_BC_TC_Interrupt_Enable 1 Interrupts can normally be serviced after some delay commonly referred to as interrupt latency In some cases the interrupt laten
638. us 1 Register address 3 This bit indicates whether a gate interrupt has occurred in general purpose counter i 0 No interrupt Interrupt request generated This bit can be cleared by setting Gate Interrupt Ack to 1 Related bitfields Gi Gate Interrupt Refer to Table 8 2 Interrupt Condition Summary for more information Gij Gate On Both Edges i 0 2 type Write in GO Mode Register address 26 bit 2 type Write in Mode Register address 27 This bit enables you to use both gate edges to generate the gate interrupt and or to control counter operation 0 Disabled 1 Enabled This bit also affects where interrupts are generated National Instruments Corporation 4 39 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer G Gate Polarity i 0 0 13 type Write GO Mode Register i i bit 13 type Write in G1 Mode Register This bit selects the polarity of the GATE input signal 0 Active high 1 Active low Gj Gate Second Enable i 0 bit 8 type Write in Second Enable Register bit 10 type Write in Second Enable Register This bit enables the gate interrupt in the secondary interrupt bank 0 Disabled 1 Enabled The relevant gate edge is Stop edge in case of level gating Active edge both start and stop in case of edge gating Related bitfields Gating Mode Gate On Both Edges Gj Gate Select i 0 b
639. using AI 5 Sync and START2 Sync Synchronous Mode When you select synchronous mode for START1 or 5 2 the timing depends on whether you select internal CONVERT or external CONVERT using AI CONVERT Source Select In the internal CONVERT mode the inactive edge of the SI2 source that recognizes the external trigger generates the output Figure 2 27 shows the propagation delays for STARTI Figure 2 28 shows the propagation delays for START2 National Instruments Corporation 2 97 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control START1 SI2 Source N Tpfi PFIO Al_ START1 Trtsi RTSI TRIGGER 0 6 X RTSI_BRD lt 0 3 gt Figure 2 27 START1 Delays Synchronous Mode Internal CONVERT START2 SI2 Source PFI1 Al_START2 RTSI_TRIGGER lt 0 6 gt RTSI_BRD lt 0 3 gt zo Tpfi Tttsi _jTbrd Figure 2 28 START2 Delays Synchronous Mode Internal CONVERT In the external CONVERT mode the active edge of CONVERT_SRC that recognizes the external trigger generates the output Figure 2 29 shows the propagation delays for START 1 Figure 2 30 shows the propagation delays for START2 START1 CONVERT SRC UX PFIO AI START1 RTSI lt 0 6 gt RTSI BRD O0 3 Tpfi L 4 Trtsi L
640. ut counters Function AI Arming Declare variable arm si arm 512 If single scan then AI Arm 1 AI On End Of 1 If internal START mode SI special trigger delay will be used then arm 51 1 Else arm 0 If internal CONVERT mode then arm si2 21 Else arm 2 0 AI SC 1 You must set these four bitfields in a single write AI SI Arn arm si AI SD Arm arm 512 AI DIV 1 2 6 3 15 Starting the Acquisition Use this function to initiate an analog input operation if you have selected software pretrigger for pretriggered operation or software posttrigger for non pretriggered operation This function does not do anything unless you have selected software pretrigger or posttrigger Function AI Start The Acquisition If acquisition is pretriggered then If software pretrigger then AI STARTI Pulse 1 Else National Instruments Corporation 2 41 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control If software posttrigger then AI STARTI Pulse 1 2 6 3 16 Analog Input Program The previous sections listed functions that you can use to configure the AITM This section shows how to organize these functions to implement a general analog input operation You can use the following sequence of functions to program the AITM for any analog input operation Refer to Chapter 10 Miscellaneous Functi
641. ut polarity is selectable and the input state can be directly observed in one of the status registers Source ADC Related bitfields SOC Polarity AI SOC St National Instruments Corporation 2 23 DAQ STC Technical Reference Manual Chapter 2 Analog Input Timing Control 2 6 Programming Information 2 6 1 Programming the DAQ STC involves writing to and reading from the registers on the chip The programming instructions are language independent that is they instruct you to write a value to a given bitfield or register or to detect the state of a bitfield or a register without presenting the actual code This section presents the functions required to implement some common analog input applications which are described in pseudocode that refers to the various bitfields Bitfield descriptions relevant to the AITM modules are also included The bitfield descriptions are intended to be used as a reference See Appendix B Register Information for the DAQ STC register map and to locate specific bitfield descriptions in this manual A bitfield is a bit in a register a group of functionally related bits in one register or a pair of registers that jointly perform a function If a bitfield consists of several bits within one register the locations of the bits must be contiguous Pairs of 16 bit registers are needed for loading and saving the 24 bit counter contents Each pair of registers is treated as a single bitf
642. ut timing control module analog input application 1 2 to 1 3 analog input functions 2 1 to 2 18 acquisition level timing and control 2 14 to 2 16 continuous acquisition mode 2 15 master slave trigger 2 16 posttrigger acquisition mode 2 14 pretrigger acquisition mode 2 14 to 2 15 staged acquisition 2 16 DAQ STC Technical Reference Manual Index gating 2 16 to 2 18 free run gating mode 2 17 halt gating mode 2 17 to 2 18 low level timing and control 2 6 to 2 11 ADC control 2 7 configuration FIFO and external multiplexer control 2 7 to 2 9 CONVERT timing 2 9 to 2 11 Data FIFO control 2 7 scan level timing and control 2 11 to 2 13 external START mode 2 12 to 2 13 internal START mode 2 11 to 2 12 single wire mode 2 18 analog input timing control module 2 1 to 2 133 block diagram 2 112 counter outputs 2 105 to 2 106 DIV TC 2 106 SC TC 2 105 SI TC 2 105 counters 2 123 to 2 130 DIV control 2 129 to 2 130 DIV counter 2 128 SC control 2 123 to 2 125 SC counter 2 123 SI control 2 126 to 2 127 SI counter 2 126 SI2 control 2 127 to 2 128 SI2 counter 2 127 error detection 2 132 overflow error 2 132 overrun error 2 132 SC TC error 2 132 external gating 2 109 to 2 111 features 2 2 to 2 3 internal signals and operation table 2 113 to 2 119 interrupt control 2 130 to 2 131 macro level analog input timing 2 106 to 2 108 DAQ STC Technical Reference Manual 4 nominal signal pulsew
643. utput If an external signal is driving a bidirectional pin and you configure the pin for output you may cause physical damage to the DAQ STC the external circuitry or both You must enable the slow internal timebase IN TIMEBASE2 if you want to use it National Instruments Corporation 10 11 DAQ STC Technical Reference Manual Chapter 10 Miscellaneous Functions 10 8 2 Programming FOUT The following function can be used to configure FOUT Function MSC FOUT Configure If enable FOUT then FOUT_Timebase_Select 0 fast timebase or 1 slow timebase FOUT Divider 0 divide by 16 or 1 through 15 divide by 1 through 15 FOUT Enable 1 10 8 3 Programming Analog Trigger The following function enables or disables analog triggering and if enabled selects the analog trigger mode and the source of the analog trigger Function Analog Trigger Control Analog Trigger Mode 0 low window or 1 high window or 2 middle window or 3 high hysteresis or 6 low hysteresis Analog Trigger Drive 0 or 1 Analog Trigger Enable 0 not enabled or 1 enabled 10 8 4 Bitfield Descriptions Bits in the register bit maps are organized into bitfields A bitfield can contain one or more bits Only bits with contiguous locations within a register can belong to a bitfield The high and low pairs of load and save registers for 24 bit counters are also treated as bitfields This section describes the bitfields related
644. utput version of START signal analog input error signal AI data FIFO empty flag AI data FIFO full flag AI data FIFO half full flag AI FIFO request signal AI data FIFO request analog input timing control module data FIFO write clock signal internal timebase signal for the analog input module output timebase signal internal analog input signal STARTI internal analog input signal STARTI dedicated stop input signal dedicated stop output signal internal analog input signal AI IN TIMEBASEI analog trigger drive signal analog trigger input high voltage reference analog input trigger low voltage reference analog output AO start signal DAQ STC Technical Reference Manual G 2 National Instruments Corporation AO UPDATE AOFEF AOFFF AOFFRT AOFHF AOFREQ AOTM AO ADDR Q 3 ENDI END2 TIMEBASEI OUT TIMEBASE AO TBI ASIC BC BC CE BC CLK BCD BC DISARM BC HOLD BC LOAD BC LOAD SRC National Instruments Corporation Glossary AO update signal AO FIFO empty flag AO FIFO full flag data FIFO retransmit AO FIFO half full flag data FIFO request signal analog output timing control module AO address signal channels 0 through 3 end on UC TC signal end on BC TC signal internal timebase for analog output module AO output clock signal AO timebase 1 signal application specific integrated circuit 24 bit buffer repetition counter BC count enable signal
645. utputs analog input timing control module DIV TC signal figure 2 106 SC TC signal figure 2 105 SI TC signal figure 2 105 DAQ STC Technical Reference Manual 18 analog output timing control module 3 107 to 3 108 BC TC signal figure 3 107 UC TC signal figure 3 108 counters analog input timing control module 2 123 to 2 130 DIV control 2 129 to 2 130 DIV counter 2 128 SC control 2 123 to 2 125 SC counter 2 123 SI control 2 126 to 2 127 SI counter 2 126 SI2 control 2 127 to 2 128 SI2 counter 2 127 analog output timing control module 3 117 to 3 121 BC control 3 120 to 3 121 BC counter 3 120 UC control 3 119 UC counter 3 118 to 3 119 UI control 3 118 UI counter 3 117 UI2 control 3 121 UI2 counter 3 121 counter timer See general purpose counter timer counter timer functions 4 3 to 4 15 event counting 4 3 to 4 6 buffered cumulative event counting 4 5 buffered noncumulative event counting 4 4 to 4 5 relative position sensing 4 6 simple event counting 4 4 simple gated event counting 4 4 pulse generation 4 9 to 4 12 buffered retriggerable single pulse generation 4 11 to 4 12 retriggerable single pulse generation 4 11 National Instruments Corporation single pulse generation 4 9 to 4 10 single triggered pulse generation 4 10 pulse train generation 4 12 to 4 15 buffered pulse train generation 4 14 buffered static pulse train generation 4 13 continuous pulse train generatio
646. ve TMRDACWR The next UPDATE pulse can be asserted at the same output clock edge on which the last TMRDACWR signal is deasserted Therefore the shortest cycle time for the case above is four output clock periods for one channel plus three output clock periods for 3 101 DAQ STC Technical Reference Manual Chapter 3 Analog Output Timing Control each additional active channel This example uses three channels so the period for the entire cycle is 10 output clock periods With a 10 MHz source and output clock this corresponds to 1 us or a per channel rate of 1 MHz 3 7 10 External Trigger Timing The external control of the analog output is very similar to the AITM but with fewer signals to control The primary analog output module consists of the UI UC and BC counters This circuitry provides extensive hardware support for waveform generation and is intended as the main source of analog output control on the DAQ STC The signals to be controlled externally are START and UPDATE The PFI lt 0 9 gt and RTSI TRIGGER O 6 signals are used for the external interface along with software strobes The secondary analog output module consists of the single counter UI2 This 16 bit counter begins counting immediately after it is armed by software Software can also strobe the UPDATE2 pin for non timed applications These signals are latched and recognized for use by the analog output control circuit in the same fashion as the external signals in th
647. verview The DAQ STC has two groups of counters dedicated to analog output timing and control the primary group and the secondary group This section discusses programming for the secondary group Refer to section 3 6 1 Programming for a Primary Analog Output Operation for a discussion of the primary group 3 6 6 2 Resetting Assume the secondary AO module of the DAQ STC was set up to perform an unknown operation The object is to stop any activities in progress Function 2 Reset A11 Begin critical section AO_UI2_Arm_Disarm 0 AO UD TC Interrupt Enable 0 AO 12 Source Select 0 AO UD Source Polarity 0 AO UD External Gate Enable 0 AO UD External Gate Select 0 AO UD External Gate Polarity 0 AO UD Software Gate 0 AO UD TC Interrupt Ack 1 AO UD TC Error Confirm 1 AO UD Initial Load Source 0 End critical section You need to perform the A02 Board Personalize programming function in order to bring secondary analog output module of the DAQ STC into a known state You can then program the secondary analog output module for any desired operation DAQ STC Technical Reference Manual 3 38 National Instruments Corporation Chapter 3 Analog Output Timing Control 3 6 6 3 Board Power up Initialization Use this function to program software selectable options in the secondary analog output module of the DAQ STC that depend on the personality of the board or device the DAQ STC i
648. vide 2 Slow Internal Timebase RGOUTO RTSI Counter Output RGOUTO can come from two sources If RTSI Sub Selection 1 is 0 RGOUTO is OUT signal from general purpose counter 0 If Sub Selection 1 is 1 RGOUTO is the signal appearing on the OUTO RTSI IO pin 4 8 2 G SOURCE Selection and Conditioning The hardware can route any of the PFI or the RTSI TRIGGER pins to the input G SOURCE In addition G SOURCE can come from a few internal signals The user can select the active edge polarity rising edge active or falling edge active Table 4 5 shows a comprehensive list of the signal sources available for G SOURCE Table 4 5 G SOURCE Selection Gi Source Select Source Internal signal IN TIMEBASEI PFI lt 0 9 gt RTSI lt 0 6 gt Internal signal IN TIMEBASE2 TC signal from the other general purpose counter Note On the AT MIO E Series boards the OSC pin is tied to 20 MHz IN has possible values of 20 MHz and 10 MHz and IN TIMEBASE2 is 100 kHz Table 4 6 shows the conditioning available for G SOURCE Table 4 6 G SOURCE Conditioning Gi Source Polarity Polarity 0 Rising edge active 1 Falling edge active National Instruments Corporation 4 63 DAQ STC Technical Reference Manual Chapter 4 General Purpose Counter Timer 4 8 3 G GATE Selection and Conditioning
649. vided by two AO Output Divide By 2 0 OUT TIMEBASE is the same as IN TIMEBASE or 1 AO OUT TIMEBASE is IN TIMEBASE divided by two AO UPDATE Pulse Timebase 0 selected by AO UPDATE Pulse Width or 1 selected by AO UPDATE Original Pulse AO UPDATE Pulse Width 2 0 3 3 5 AO OUT TIMEBASE periods or 1 1 1 5 AO OUT TIMEBASE periods AO UPDATE Output Select 0 high Z or 1 ground or 2 enable active low or 3 enable active high AO DMA PIO Control 0 FIFO data interface mode or unbuffered data interface mode AO Enable 0 disabled or 1 enabled AO AOFREQ Polarity 0 active high or 1 active low AO TMRDACWR Pulse Width 0 3 AO OUT TIMEBASE periods or 1 2 AO OUT TIMEBASE periods AO FIFO Enable 0 TMRDACWR signal is disabled or 1 TMRDACWR signal is enabled AO FIFO Flags Polarity 0 active low or 1 active high AO Number Of DAC Packages 0 dual DAC mode or 1 single DAC mode AO Configuration End 1 End critical section 3 6 1 4 Trigger Signals Use this function to select the signal that will trigger the analog output operation and to program the DAQ STC AOTM to recognize single or multiple trigger signals Function AO Triggering Begin critical section AO_Configuration_Start 1 If docal buffer mode with pauses OR continuous mode OR waveform staging then AO_Trigger_Once 0 Else AO_Trigger_Once 1 If software triggered then AO STARTI Select 0
650. viii National Instruments Corporation Contents Figure 7 5 Serial Output e eee tte tenet ra 7 5 Figure 7 6 Rd rH 7 5 Figure 7 7 Serial Input Timing eoe eere 7 16 Figure 7 8 Serial Output 7 16 Figure 9 1 Intel Bus Interface Read Timing 2 9 6 Figure 9 2 Intel Bus Interface Write 9 6 Figure 9 3 Motorola Bus Interface Read 9 7 Figure 9 4 Motorola Bus Interface Write 9 8 Figure 10 1 Clock Distribution 10 2 Figure 10 2 Low Window enne 10 4 Figure 10 3 High Window 10 4 Figure 10 4 Middle Window 10 5 Figure 10 5 High Hysteresis 10 5 Figure 10 6 Low Hysteresis 10 6 Figure 10 7 Test Mode Internal Gate 10 7 Tables Table 2 1 od Interface M 2 19 Table 2 2 CONVERT SRC Reference Pin Selection 2 84 Table 2 3 Basic Analog Input Timing 2 86 Table 2 4 Configuration Memory 2 90 Table 2 5 External Analog Input Timing eene 2 96 Table 2 6 5 and START2 Timing Synchronous Mode 2 99 Table 2 7 STARTI and START2 Timing Asynchronous Mode 2 100 Table 2 8 Interval Scanning Mode Timing 2 107 Table 2 9 Internal Signals eee ire et ie beo opc 2 113 Table 2 10 PELSelectors eere t
651. width interval for G_GATE the HW save register latches the counter value for software read An interrupt notifies the CPU after each period so that the interrupt software can read the value in the HW save register Figure 4 11 shows two pulsewidths of a buffered pulsewidth measurement where the first pulsewidth is three G SOURCE rising edges and the second pulsewidth is two SOURCE rising edges ace _ 1 2 3 3 G SOURCE Counter Value 0 HW Save Register Figure 4 11 Buffered Pulsewidth Measurement Pulse Generation In the pulse generation functions the counter generates a single pulse of specified duration following the software arm The software arm occurs when software sets the counter arm bit in the DAQ STC register map The following actions are available in pulse generation e The counter uses SOURCE as a timebase to generate the pulse e user specifies the pulse parameters terms of periods of the SOURCE input e G_GATE can serve as a trigger signal to generate a pulse after the first active gate edge or after each active gate edge e An alternate output mode is provided so that G OUT outputs two counter TC pulses instead of a single long pulse 4 4 3 1 Single Pulse Generation The single pulse generation function generates a single pulse with programmable delay and programmable pulsewidth following the software arm The counter uses
652. xt Load Source St AI SI Load SI Load B bits lt 0 7 gt type Write in AI SI Load B Registers address 16 bits lt 0 15 gt type Write in AI SI Load B Registers address 17 This bitfield is load register B for the SI counter If load register B is the selected SI load register the SI counter loads the value contained in this bitfield on SI Load and on SI TC The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address Related Bitfields SI Next Load Source St AI SI Load SI Next Load Source St bit 6 type Read in AI Status 2 Register address 5 This bit indicates the next load source of the SI counter 0 Load register A 1 Load register B DAQ STC Technical Reference Manual 2 66 National Instruments Corporation Chapter 2 Analog Input Timing Control SI Q St bits lt 9 10 gt type Read in AI Status 2 Register address 5 This bitfield reflects the state of the SI control circuit 0 WAIT 1 1 CNT 1 See section 2 8 Detailed Description for more information on the SI control circuit SI Reload Mode bits lt 4 6 gt type Write in AI Mode 2 Register address 13 This bitfield selects the reload mode for the SI counter 0 No automatic change of the SI load register 4 Alternate first period on every STOP Use this setting to make the time interval between the START trigger and the first sample pulse different from the remaining
653. xt Load Source St bit 3 69 AO UC Q St bit 3 69 AO UC Save St bit 3 69 AO UC Save Trace bit 3 69 AO UC Save Value bit 3 70 AO UC Switch Load Every BC TC bit 3 70 AO UC Switch Load Every TC bit 3 70 AO UC Switch Load On BC bit 3 70 AO UC Switch Load TC bit 3 70 AO UC bit 3 70 AO UC Interrupt Enable bit 3 71 AO UC TC Second Enable bit 3 71 AO UC TC St bit 3 71 AO UC Write Switch bit 3 71 AO UI Arm bit 3 71 AO UI Armed St bit 3 72 AO UI Count Enabled St bit 3 72 AO UI Initial Load Source bit 3 72 AO Load A bit 3 72 AO Load B bit 3 73 AO UI Load bit 3 72 National Instruments Corporation AO UI Next Load Source St bit 3 73 AO UI Q St bit 3 73 AO UI Reload Mode bit 3 73 AO UI Save Value bit 3 74 AO UI Source Polarity bit 3 74 AO Source Select bit 3 74 AO UI Switch Load On bit 3 74 AO UI Switch Load On Stop bit 3 74 AO UI Switch Load On bit 3 75 AO UI Wirite Switch bit 3 75 AO UD Arm Disarm bit 3 75 AO UD Armed St bit 3 75 AO UD Configuration End bit 3 75 AO UD Configuration Start bit 3 75 AO Count Enabled St bit 3 76 AO UD External Gate Enable bit 3 76 AO UD External Gate Polarity bit 3 76 AO UD External Gate Select bit 3 76 AO UD Gate St bit 3 76 AO UD Initial Load Source bit 3 76 AO UI2 Load A bit 3 77 AO UD Load B bit 3 77 AO 012 Load bit 3 77 AO U
654. xternal START mode the externally generated START pulses enter the DAQ STC through one of the PFI lt 0 9 gt or RTSI lt 0 6 gt inputs or from general purpose counter 0 When the counters are armed and a START pulse is received the DAQ STC is ready to recognize external START pulses Each external START initiates a scan causing the DAQ STC to generate CONVERT pulses until a STOP is received If the external START pulses occur at a rate higher than the DAQ STC can maintain the extra external START pulses are ignored The timing for the external START can be arbitrarily complex depending on the behavior of the signal you select as the external START source Typically though you will select a periodic signal in which case the only timing parameter available is the delay between START pulses The delay from START to the first START depends on the relationship between the START trigger and the external START and can vary DAQ STC Technical Reference Manual 2 12 National Instruments Corporation Chapter 2 Analog Input Timing Control Figure 2 9 shows three scans of four CONVERT pulses each where the scans are initiated by an external START External START START1 START STOP CONVERT Figure 2 9 External START In the external START mod
655. you set AI Start Stop Gate Enable to 0 in the external CONVERT section of the Convert Signal function the SC GATE is selected The SC enables the external CONVERT pulses whenever the SC counter is enabled to count and blocks the external CONVERT pulses whenever the SC counter is not enabled to count 2 6 3 13 Enable Interrupts Use this function to enable the AITM to generate interrupts Function AI_Interrupt_Enable AI_FIFO_Interrupt_Enable 0 disabled or 1 enabled AI START Interrupt Enable 0 disabled or 1 enabled START interrupt must be enabled in order for the STOP interrupt to operate If AI START Interrupt Enable is 1 then AI STOP Interrupt Enable 0 disabled or 1 enabled Else AI STOP Interrupt Enable 0 disabled AI_SC_TC_Interrupt_Enable 0 disabled or 1 enabled AI_START1_Interrupt_Enable 0 disabled or 1 enabled AI_START2_Interrupt_Enable 0 disabled or 1 enabled AI_Error_Interrupt_Enable 0 disabled or 1 enabled DAQ STC Technical Reference Manual 2 40 National Instruments Corporation Chapter 2 Analog Input Timing Control To generate interrupts you must also program the interrupt control module Refer to Chapter 8 Interrupt Control for more information on programming the interrupt control module To use interrupts refer also to section 2 6 8 Analog Input Related Interrupts 2 6 3 14 Arming Use this function to arm the analog inp

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