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User Manual (Meerkat SoM)

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1. Max frequency data rate 750 1500 MHz Mbps per data lane Number of loads 1 load Max loading per pin 10 pF Reference plane GND or PWR If PWR 10 decoupling cap required for return current Breakout region 90 diff 45 55 single 15 impedance ended Max PCB breakout delay 48 ps Trace impedance 90 diff pair 45 55 sin Q gle ended Via proximity signal to 3 8 24 mm ps reference Trace spacing 2x microstrip stripline dielectric Max trace delay 1620 ps PCB routing delays for Max trace delays and max trace delay skew parame ters Max within 1 ps PCB routing delays for pair skew Max trace delays and max trace delay skew parame ters Max inter pair pair pair 10 ps PCB routing delays for skew Max trace delays and max trace delay skew parame ters Table 26 CSI interface delays CSI 46 109 5 155 5 CSI A CLK P 46 109 5 155 5 CSI DO 81 73 8 154 8 CSI A DO P 81 73 8 154 8 CSI A DI 61 94 155 1 CSLA DI 62 93 0 155 0 CSI B 78 76 4 154 4 Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 infoG avionic design de www avionic design de Section 4 Interfaces of the COM 32 CSI B DO P 79 75 5 154 5 CSI B 66 88 0 154 0 CSI B DI P 67 87 1 154 1 CSI E CLK N 67 87 4 154 4 CSI E CLK P 68 86 4 154 4 CSI
2. 29 458 MIBECSLD ol hae th et ha Noire ie 29 48 1 Signals 22222222524 eu 30 4 8 2 Example schematic 31 4 8 3 Necessary layout properties 31 49 JMIPLIDSI xxm 84 by a PP be CA ER ee Rp RE E So 32 Sienals ee Rx M ome ele PNE ek ee Sa 33 4 9 2 33 4 9 3 Necessary layout properties 33 Section Contents 4 10 PCIe 4 10 1 4 10 2 4 10 3 4 11 SATA 4 11 1 4 11 2 4 11 3 Signals kb sexe Rem RUP do AUR des acd P UR AGE Aa Example schematic Necessary layout properties SIGNALS owe oe oe Oe Be Example Necessary layout properties 4 12 SD MMC SDIO 4 12 1 4 12 2 4 12 3 4 13 S PDIF 4 13 1 4 13 2 4 13 3 4 14 SPI 4 15 UART 4 15 3 SIONS uo ko Spore wm dea ROW dum ba Ie Rod e dus e RE VR Aes Example schematic Necessary layout properties
3. van SY e RW e has SA EA 19 4 2 2 Example schematic 20 4 2 3 Necessary layout properties 20 43 EDP 21 Signals 2 624 omm oem SAP Rege og RUP Se d eds 21 4 3 2 Exampleschematic s 22 4 3 3 Necessary layout properties 22 Bde a ee ee a Be 23 Signals cache ego band ede Oe ERS De eee UR Re Hake de US 23 442 Example 24 445 Necessary layout properties 24 45 HDMI hs eae eh ee ed ee ae oe ele ad 25 49 1 Signals 25 4 5 2 Example schematic 11 s 26 4 5 3 Necessary layout properties 26 0G oc Dd 27 46 1 Signals 4 4 2 o dc BA Gee Uum eh a ea D e SE 28 4 6 2 Example schematic 28 4 6 3 Necessary layout properties 28 d diss d dod ed te a ee EY ee 29 A Ll Signals uox so oet Re ome aer x RR Re ee 29 4 7 3 Exampleschematic 29 4 7 3 Necessary layout properties
4. OUT P i vddio pex ctl 0 3 3V oo oo 2 X4 1 Ground ao SE X42 GPIO PK3 GPIO3 GPIO R2 SDMMC2A_DAT4 tracectl z vddio_gmi pu 1 8V Re X43 GPIO3 PK 01 GPIO R3 SDMMC2A traceclk 5 vddio gmi pd es 1 8 ze SA z X4 4 GPIO_PIS GPIO3 05 GPIO 5 U7 SDMMC2A DATI vddio_gmi pu oo T 1 8 77 X4 5 GPIO_PI7 GPIO3 PL07 tracedata7 DTV ERR PSYNC vddio gmi pu E 1 8 X4 6 GPIO PH6 GPIO3 PH 06 PH6 U8 SDMMC2A_DAT3 wacedata3 DTV DATA vddio gmi pu 5 E 18V ER GPIO 5 GPIO3 PH 05 GPIO 5 R4 SDMMC2A_DAT2 3 E vddio gmi pd B ks 1 8 2 5 8 5 X4 8 GPIO PK2 GPIO3 PK 02 PK2 YI vddio gmi pu 1 8 3 X4 9 BL_EN GPIO3_PH 04 GPIO_PH4 R5 SDMMC2A DATO s vddio 8 5 1 8 amp gd 5 X410 GPIO PJO GPIO3 00 GPIO PJO U6 vddio gmi pu 5 3 1 8V 8 X4 11 BL PWM 2 GPIO_PH2 AAA PM3 PWM2 vddio gmi pd lt lt lt 1 8 o X4 12 FAN GPIO3 PH 00 PHO Y6 PM3 PWMO tracedata2 DTV VALID vddio pd 1 8 93 X413 Ground E X414 GPIO GPIO3 PK 00 AAL soc_therm_oc3_n vddio_gmi pu 1 8 X415 ITAG H6 JTAG TCK vddio sys 2 1 8 4 16 Ground X4
5. OWR is not supported by NVIDIA add X3 42 GPIO update the pinmux table reference is the customer pinmux table from the Jetson reference board e NVIDIA does not officially support SPI2D and SPI3C Rev00 26 01 2015 Draft release Initial Release Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Contents 1 Document Change History 2 2 Introduction 9 2 1 Purpose of this manual 9 2 2 Designated use of the 9 3 Properties of the COM 10 3 1 Structure of the COM 2 s e EO 10 3 1 Generaloverview 10 3 1 2 Function block diagram 12 3 2 Mechanical properties ofthe COM 12 3 3 Operation parameters 14 3 4 Power management ofthe COM 15 3 4 1 Powersequence 15 4 Interfaces of the COM 16 4 1 processor module special functions 16 41 1 Signal descriptions 17 MAP TE Siig SR dC YR SE dU eee KI da 18 42 Signals Low soe ee
6. X4 5 GPIO PI7 X4 6 GPIO PH6 X4 7 GPIO PH5 X4 8 PK2 X4 9 BL EN X4 10 GPIO_PJO 4 11 BL PWM X4 12 FAN PWM X4 14 X4 18 SPI4C_nCS1 X4 20 GPIO PH3 X4 22 PK4 X4 24 2 X4 35 UART4_DEBUG_nCTS X4 36 GPIO PJ2 X4 37 UART4_DEBUG_TXD X4 39 UART4 DEBUG nRTS X4 41 DEBUG RXD X4 43 2 2 X4 52 VDD 5 10 DISABLE X5 13 GPIO POI X5 18 GPIO X5 19 GPIO PO2 X5 21 nIRQ X5 23 GPIO PO3 X5 27 GPIO PO4 X5 45 MISO X5 47 50 X5 49 5 SCK X5 51 X5 53 SPIAC 50 X5 55 SPIAC MOSI X5 57 MISO X5 59 SCK e Add possible PCIe configurations e Define default PCIe configuration e Define GEN2 as default mini PCIe socket I2C bus Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section Document Change History e PCB Changes for Meerkat Rev02 add nWAKEUP POWER pull up 100 add WAKEUP 11 pull down 10k add pull down resistor for 100k use LDO4 of the PMIC for AVDD LVDS to support LVDS and eDP replace OWR with
7. EXT 6 3 OR 5 5 4 5 SLGS9M30I VTR Usp vpus 0580 VBUS USB VBUS Das x 1 j 115 USBO D L SA 6 USB CLIENT VBUS 5 1E CUSBU CLIENT 7 VEHI USB CLIENTD Y Y d P 1 m USBO DL P 23 LL TENT De Net Class ACM20I2 900 2P 1 4234 76 ClassName USB CLIENT n 2 R221 Net Class ClassName 90Ohms Diff USB ID M 26 MicroUSB upp 5V GND G Figure 4 6 USB Client schematic example 4 16 3 Necessary layout properties Table 52 USB 2 0 interface signal routing requirements Max frequency High 480 2083 240 Mbps ns MHz Speed Max loading High Speed 107 150 600 pF Full Speed Low Speed Reference plane GND Breakout region min width spacing impedance Trace impedance 90 diff pair 50 single Q 15 ended Via proximity Signal to 3 8 24 mm ps Up to 4 signal vias can reference share a single GND return via Max trace delay 1280 microstrip 1150 ps stripline Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 5 Max intra pair between USBx D P amp USBx D N skew 7 5 ps PCB routing delays for Max trace delays and max trace delay skew parame ters Table 53 USB 3 0 interface signal routing require
8. 45 SPI2D signals 1 8V level 45 SPI3E signals 1 8V level 45 SPI4C signals 1 8V level 45 UARTI signals 1 8V 47 UART2 signals 1 8V 47 UARTS3 signals 1 8V 1 47 UART4 DEBUG signals 1 8V 47 USB signals bch GOA wae eee Row oe be AR be OR ee 49 Section List of Tables 52 USB 2 0 interface signal routing requirements 53 USB 3 0 interface signal routing requirements 54 USB 2 0 interface delays Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 2 Introduction 9 2 Introduction Tegra processor module is a platform by Avionic Design that is based on NVIDIA Tegra technology It defines the form factor the pinout and the function set Please read all the information in this manual carefully If you have any questions about the Tegra R processor module please contact Avionic Design 2 1 Purpose of this manual This manual will give you information about the abilities and the interfaces of the processor module COM You
9. HDMI DDC SCL X1 4 HDMII2C clock HDMI DDC SDA 1 2 HDMI I2C data HDMI INT 1 8 interrupt Used for Hot Plug detection X1 1 Transmit clock negative P 1 3 Transmit clock positive HDMI TXDO N 1 7 Datalane negative HDMI TXDO X1 9 Data lane positive HDMI TXD1 X1 13 Data lane negative X1 15 Data lane positive HDMI TXD2 N X1 19 Data lane negative HDMI TXD2 P X1 21 Data lane positive HDMI VDD EN X4 52 HDMI power enable 010 001 0 01 09 9 310 Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Figure 4 2 HDMI schematic example 4 5 3 Necessary layout properties t m GND H INANC GND c Table 16 HDMI interface signal routing requirements Max frequency 297 MHz Data rate is ten times larger than the pixel fre quency Topology Point to Point Termination 50 At Receiver 500 To 3 3V at receiver To on board GND near connector Reference plane GND Max Breakout length de 7 62 52 5 mm ps lay Trace impedance 90 diff
10. SDMMC3 VDD EN X5 25 SDMMC power enable SDMMC3 X1 30 SDMMC clock SDMMC3 LB IN X1 26 SDMMC clock loop back input SD I MMC3 CLK LB IN connects to SD MMC3 CLK LB OUT Total trance length is the length of a round trip from Tegra to connector and back SDMMC3 CLK LB OUT X1 28 SDMMC clock loop back output SDMMC3 CMD X1 18 SDMMC command IO SDMMC3 DATO X1 22 SDMMC data I O SDMMC3 DATI X1 16 SDMMC data I O SDMMC3 DAT2 X1 20 SDMMC data I O SDMMC3 DAT3 X1 14 SDMMC data I O SDMMC3 nCD X1 32 SDMMC card detect O low active SDMMC3 nWP X1 34 SDMMC write protect O active Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 42 4 12 2 Example schematic Length Constraint Min Length Length 100mm Matched Net Lengths Tolerance 2mm DAD NOTE customer might want to add TVS if exposed externally X16 SD Card Socket Jes lu 10 PCB Rule Net Class i SDMMC DAT3 RIO oR t SDMMC DAT3 SDMMC CMD R RIO UR SDMMC_CMD Fi 5 43V3 SD RUM mp 08 SDMMC CLK 7 SDMMC DATOR OR SERRE C SDMNIC3 5 48 SDMMC DATT R RI R 9 Uk DUMC DAR EG _ 2 lass RUR
11. 1 1 4mm E ae EM 3 2 2 Alb e Figure 3 4 Mechanical properties of the COM bottom view Hole Positions and Exemplary Cooling from Top Chip Die center Hole center ARR M 2 H B i TT AS gt 805mm K E 35 9 mm Figure 3 5 Mechanical properties of COM heatsink mounting points Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 infoG avionic design de www avionic design de Section 3 Properties of the COM 14 In the table below you can find a list of the mechanical properties of the Tegra processor module Table 2 Mechanical properties of the COM Parameter Properties Size of the COM 70 x 50 mm Size of the NVIDIA Tegra 3 SoC 23 x 23 mm Total PCB height 5 70 mm Maximum stacking height top 2mm Maximum stacking height bottom 2 3 Weight 18g connector type DF12 3 0 60DP 0 5V 86 Total pin count 360 3 3 Operation parameters In this section you can find a list of the maximum operation conditions for the Tegra processor module The module can operate under those conditions for a short time If these operation conditions continue for an extended time they could damage the module You can find recommended operation conditions
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13. device it is a request that the system power be restored No interrupt or other con sequences result from USB3_RX0_N X3 9 PCIe receive data laneO negative Shared I with USB3 0 USB3 RXO P X3 7 PCIe receive data laneO positive Shared I with USB3 0 USB3 X3 1 PCIe transmit data laneO negative Shared O with USB3 0 0583 TXO P X3 3 PCIe transmit data laneO positive Shared with USB3 0 PEX USB3 N X3 19 PCIe receive data lanel negative Shared I with USB3 0 PEX USB3 P X3 21 PCIe receive data lanel positive Shared I with USB3 0 USB3 X3 13 PCIe transmit data lanel negative Shared with USB3 0 USB3 P X3 15 PCIe transmit data lanel positive Shared with USB3 0 2 X3 31 PCIe receive data lane2 negative I PEX RX2 P X3 33 PCIe receive data lane2 positive I 2 X3 25 PCIe transmit data lane2 negative O PEX TX2 P X3 27 PCIe transmit data lane2 positive O PEX RX3 N X3 45 PCIe receive data lane3 negative I PEX RX3 P X3 43 PCIe receive data lane3 positive I PEX TX3 N X3 37 PCIe transmit data lane3 negative O PEX_TX3_P X3 39 PCIe transmit data lane3 positive O PEX_RX4_N X3 49 PCIe receive data lane4 negative I PEX RX4 X3 51 PCIe receive data lane4 positive I PEX X3 57 PCIe transmit data lane4 negative O TX4 X3 55 PCIe transmit dat
14. vddio audio pu 1 8V X5 9 UART1_RXD GPIO3_PS 02 KB_ROW10 AA31 UA3_RXD vddio_sys 1 8V pd X5 10 W_DISABLE GPIO3_PX 07 GPIO_X7_AUD P28 vddio audio pd 1 8V 5 11 UARTI TXD GPIO3 PS 01 KB ROW9 AA28 UA3 TXD vddio sys 1 8V pd X5 12 GPIO PX6 GPIO3 PX 06 GPIO X6 AUD N31 audio pu 1 8 X5 13 GPIO POI GPIO3 01 DATAO 5 SPI3E_DOUT vddio bb 1 8V pu X5 14 GENI 2 nIRQ GPIO3 PX 05 GPIO X5 AUD R31 vddio_audio pu 1 8V 5 15 Ground 5 16 5 GPIO3 PR 05 KB ROWS Y31 vddio_sys 1 8V pd X5 17 EN_LVDS_EDP GPIO4 AS3722 Pin B3 X5 18 PP2 GPIO3 PP 02 DAP3 DOUT 7 1252 SDATA OUT vddio bb 1 8V pd X5 19 GPIO PO2 GPIO3 PO 02 DATAI 5 SPI3E DIN 1 vddio bb 1 8V pu X5 20 GPIO3 PR 04 KB 4 Y29 vddio sys 1 8V pd X521 GPIO3 PP 01 DAP3 DIN 7 1252 SDATA IN vddio bb 1 8V pd X522 HEAD DET GPIO3 PR 07 KB ROW7 Y30 vddio_sys 1 8V pd X5 23 03 DATA2 7 SPI3E_SCK 1 vddio bb 1 8V pu X524 Ground X5 25 SDMMC3 VDD EN GPIO3 PR 00 KB ROWO W31 vddio sys 1 8V pd X5 26 unconnected X527 GPIO PO4 GPIO3 PO 04 ULPI_DATA3 AJIS SPI3E_CS1 1 vddio_bb 1 8V pu 187121004 9 uonoog L9 op ugTsop oruorA OJU 0 1
15. Table 8 DAP DS interface signal routing requirements Configuration Device 1 load Organization Max loading 8 pF Topology Point to Point Reference plane GND Breakout region Min width spacing impedance Trace impedance 50 Q 20 Via proximity signal to lt 3 8 24 mm ps Up to 4 signal vias can reference shared a single GND re turn via Trace spacing Microstrip 2x 2x dielectric Stripline Max trace delay 3600 555 ps mm Include Package amp PCB routing delays for max trace delays parameter Max trace delay skew 250 38 ps mm Include Package amp PCB between SCLK amp routing delays for max SDATA_OUT IN trace delay skew parame ter Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces the COM 21 Table 9 DAP I2S interface delays DAP2 DIN 69 169 5 238 5 DAP2 DOUT 61 158 9 219 9 DAP2 FS 78 200 3 278 3 DAP2 SCLK 64 110 0 174 0 DIN 66 348 2 414 2 DOUT 61 360 9 421 9 FS 72 336 1 408 1 SCLK 71 245 4 316 4 43 eDP The Tegra supports up to a 4 lane Embedded Display Port eDP interface The maximum resolution supported with eDP is 3840x2160 60fps e Embedded Display Port mode interface will take in a clock frequency of 2
16. our Universal Bootloader U Boot per default the configuration 1 If you require a different setup please contact us The mapping of the control signals are the following Table 31 PCIe Clock and control signal mapping 0 LO nCLKREQ PEX LO nRST PCle 1 PEX CLK2 PEX LI nCLKREQ PEX L1 nRST 4 10 1 Signals Table 32 PCIe signals X3 58 PCIe clock negative O P X3 60 PCIe clock positive O PEX CLK2 N X3 24 PCIe clock negative O PEX_CLK2_P X3 22 PCIe clock positive O PEX_LO_nCLKREQ X3 44 PCIe clock request I 10 nRST X3 46 PCIe reset This signal provides a reset sig nal to all the PCIe links It must be asserted 100 ms after power to the PCIe slots has sta bilized PEX nCLKREQ X3 48 PCIe clock request I Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM PEX nRST X3 50 PCIe reset This signal provides a reset sig nal to all the PCIe links It must be asserted 100 ms after power to the PCIe slots has sta bilized PEX nWAKE X3 52 PCIe Wake This signal is used as the PCIe I defined WAKE signal When asserted by a
17. low active low active UART4_DEBUG_nCTS X4 35 UART Clear to send UART4_DEBUG_nRTS X4 39 Request to send UART4_DEBUG_RXD X4 41 UART receive UARTA4 DEBUG TXD X4 37 UART transmit 4 15 2 Example schematic No special schematics are required 4 15 3 Necessary layout properties no necessary layout properties Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 48 4 16 USB HSIC The USB complex provides a mechanism to communicate with a PC and or USB2 0 peripherals such as keyboard mouse and card readers USB3 0 peripherals such as camera and storage devices as a host using regular USB 3 0 ports and to an ob board baseband controller using ether USB HSIC or HSI interfaces The USB complex consists of a single USB 3 0 controller and three USB 2 0 controllers The USB 3 0 controller supports up to 2 regular USB 3 0 ports and their companion regular USB 2 0 ports The USB 2 0 controllers support up to 2x regular USB ports 2x HSIC interfaces On the K1 Meerkat SoM is only on HSIC interface HSIC1 routed which is shared with USB1 USB 2 0 Tegra USB interfaces are compliant with the following USB specifications e Universal Serial Bus Specification Revision 3 0 e Universal Serial Bus Specification Revision 2 0 plus the followin
18. sials ed RO Sedes b dee eoe m oe aan ai 28 CSI signals oa e ose oe Ry X RS YU oos 30 CSI interface signal routing requirements 31 CSI interface delays o ei uo pose xD dem 31 MIPIDSIsignals 33 DSI interface signal routing requirements 34 DSIinterface delays gt or oue Re 34 Possible PCIe Configurations 35 PCIe Clock and control signal mapping 35 PCle sign l 2 4 Barbed eue Sk bade bee ee es 35 PCIe interface signal routing requirements 37 PCleinterfacedelays 38 SATA Signals 4o gom eA DRE XR RUE YOUR 39 SATA interface signal routing requirements 40 PCIe interface delays 40 SDMMCI1 SDIO signals 41 SDMMCS3 signals 22 255 eee Rome a eos 41 SDMMC3 1 interface signal routing requirements 42 SDMMC3 1 interface delays 43 S PDIF signals xx le a oe ae 44 SPILA signals 1 8V level
19. trace delay skew parame ters Table 41 SDMMC3 I interface delays SDMMCI CLK 97 91 1 188 1 SDMMC1_CMD 86 95 8 181 8 SDMMC1_DATO 68 103 3 171 3 SDMMC1_DAT1 68 104 1 172 1 SDMMC1_DAT2 69 103 5 172 5 SDMMCI DAT3 90 101 2 191 2 SDMMC3 CLK 63 81 4 144 4 SDMMC3 CMD 76 69 0 145 0 SDMMC3 DATO 74 70 1 144 1 SDMMC3 DATI 89 73 5 162 5 SDMMC3 DAT2 77 76 5 153 5 SDMMC3 DAT3 72 81 4 153 4 SDMMC3 LB IN 72 70 0 142 0 SDMMC3 CLK LB OUT 73 76 1 146 1 4 13 S PDIF The Sony Philips Digital Interconnect Format SPDIF interface supports both professional and consumer applications When used in a professional application the interface is primarily intended to carry mono phonic or stereophonic programs at a 48 kHz sampling frequency and with a resolution of up to 24 bits per sample it may alternatively be used to carry signals sampled at 32 kHz or 44 1 kHz When used in a consumer application the interface is primarily stereophonic programs with a resolution of up to 20 bits per sample The Interface normally carries audio data coded as other than linear PCM coded audio samples The inter face may also carry data related to computer software or signals coded using non linear PCM Features e Fire data formats 16 bit 20 bit 24 bit RAW and 16 bit packed e Supprted sample rates 32 44 1 48 88 2 96 176 4 and 192 kHz Avionic Design GmbH Wragekamp 10 22397 Ha
20. 5 DI P avdd dsi csi 1 2V X2 34 DSI DO DSL A DO P ALII DSL DO P avdd dsi csi 1 2V X2 35 CSI DI CSI A DI AE9 CSI A DI avdd dsi csi 1 2V X2 36 Ground X2 37 Ground X2 38 DSLA D2P DSLA 5 5 2 avdd dsi csi 1 2 X2 39 CSI CLK P CSI A CLK P ADII CSI A CLK P avdd dsi csi 1 2V X2 40 DSI A D2 N DSLA D2 N ALI5 DSI A D2 avdd dsi csi 1 2V X2 41 CSI CSI CSI A avdd dsi csi 1 2V X2 42 Ground X2 43 Ground X2 44 DSI A CLK P DSI P AH14 DSI_A_CLK_P avdd_dsi_csi 1 2V Isr noud 9 uonoog 09 op ugTsop oruorA OJU 0 1 81 88 0 0 67 410 281 88 L Awun S1nquieH 6 cc 01 durexoserA usIsaq oruortAV X2 45 HSICI DATA HSICI DATA HSICI DATA vddio_hsic 1 2V X2 46 DSI A CLK DSI A DSI A CLK avdd dsi csi 1 2V X2 47 HSIC1_STROBE HSIC1_STROBE 8 HSIC1_STROBE vddio_hsic 1 2V X2 48 Ground X2 49 Ground X2 50 DSL P DSLA D3 P AFIA DSL A P avdd dsi csi 1 2V X2 51 FORCE nRECOVERY GPIO3_PI 01 GPIO_PI1 AA6 vddio_gmi pu Pull Up on SoM 1 8V against 3 3 V X2 52 DSI A D3 DSL A D3 14 DSI D3 avdd dsi csi 1 2V X2 53 USBO D N USBO DN AH20 0580 DN avdd u
21. 7 Reference documents 8 Contact Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de 53 53 53 53 54 54 59 55 55 56 56 56 72 73 List of Figures 3 1 3 2 3 3 3 4 3 5 3 6 4 1 4 2 4 3 4 4 4 5 4 6 8 1 Top view of the Tegra processor module 11 Function block diagram of COM 12 Mechanical properties of the top view 13 Mechanical properties of the COM bottom view 13 Mechanical properties of the COM heatsink mounting points 13 Powersequence ede 16 DAP2schematicexample 20 HDMI schematic example 26 PCI Express schematic example 37 Mini PCI Express socket schematic example 37 SDMMC schematic example 42 USB Client schematic example 50 head office Duvenstedt Germany 73 List of Tables gt RRP Rr rR Rr ew 5 5 6 Document Cha
22. 81 88 0 0 67 410 281 88 L Awun S1nquieH 6 cc 01 durexoserA usIsaq oruortAV X5 28 unconnected X5 29 GPIO_PR6 GPIO3_PR 06 KB_ROW6 DCA LSPII vddio sys 1 8V pd X5 30 unconnected X5 31 SOC_ALIVE GPIO3_PT 00 KB_ROW16 AA26 vddio_sys 1 8V pd X5 32 unconnected X5 33 Ground X5 34 unconnected X5 35 unconnected X5 36 SPDD nIRQ GPIO3 PX 03 GPIO X3 AUD M30 vddio audio pu 1 8V X5 37 Ground X5 38 AUDIO EN GPIO3 PR 02 KB ROW2 AF30 vddio sys 1 8V pd X5 39 SATA PWR EN GPIO3 PEE 02 DAP MCLKI REQ SATA DEV SLP vddio_audio pd 1 8V X5 40 Ground 5 41 SATA LED GPIO3 PN 02 DOUT L28 1250 SDATA OUT vddio audio pd 1 8V X5 42 DAP MCLKI GPIO3 PW 04 DAP MCLKI L29 extperiphl clk vddio audio pd 1 8V X5 43 GPIO PW3 GPIO3 PW 03 GPIO W3 AUD J30 vddio audio pu 1 8V X5 44 DAP2 FS GPIO3 PA 02 DAP2 FS R30 1251 LRCK vddio audio pd 1 8V X5 45 SPILA_MISO GPIO3_PY 01 ULPI_DIR ALIS DIN vddio bb 1 8V 2 5 46 DAP2 DIN GPIO3 PA 04 DAP2 DIN L30 1251 SDATA IN vddio audio pd 1 8V 5 47 5 50 03 5 ALI6 SPIIA CSO vddio bb 1 8V 2 X5 48 DAP2 DOUT GPIO3 PA 05 DAP2 DOUT J29 I281 SDATA OUT vddio audio pd 1 8V X5 49 SCK GPIO3 PY 02 ULPI NXT 5 SCK vddio_bb 1 8V
23. Awun S1nquieH 6 cc 01 durexoserA usIsaq oruortAV 16 SDMMC3 DATI GPIO3 PB 06 SDMMC3 DATI SDMMC3 DATI vddio_sdmmc3 1 8V 3 3V 17 Ground 18 SDMMC3 CMD GPIO3 PA 07 SDMMC3 CMD F2 SDMMC3 CMD vddio_sdmmc3 pu 1 8V 3 3V 19 HDMI TXD2 HDMI TXD2N AD2 HDMI TXD2N avdd hdmi 3 3V X1 20 SDMMC3 DAT2 GPIO3 PB 05 SDMMC3 DAT2 F1 SDMMC3_DAT2 vddio_sdmmc3 pu 1 8V 3 3V X121 HDMI TXD2 P HDMI TXD2P ADI HDMI TXD2P avdd hdmi 3 3V X122 SDMMC3 DATO GPIO3 PB 07 SDMMC3 DATO H2 SDMMC3 DATO vddio_sdmmc3 pu 1 8V 3 3V X1 23 Ground X1 24 Ground X1 25 DP AUX P DP AUX CHO P AC6 I2C6 CLK vddio hv 3 3V 2 X1 26 SDMMC3 CLK LB IN GPIO3 PEE 05 SDMMC3 CLK LB IN F3 SDMMC3 CLK LB IN vddio_sdmmc3 pd 1 8V 3 3V 1 27 DP AUX DP AUX CHO N ACS I2C6 DAT vddio hv 3 3V 2 X1 28 SDMMC3 CLK LB OUT GPIO3 PEE 04 SDMMC3 LB OUT F4 SDMMC3 CLK LB OUT vddio_sdmmc3 2 1 8V 3 3V 1 29 Ground X1 30 SDMMC3_CLK GPIO3_PA 06 SDMMC3_CLK F5 SDMMC3 CLK vddio_sdmmc3 pd 1 8V 3 3V 31 eDP3 P LVDSO_TXD4P LVDSO TXD4P avdd 1 450 1 05V X1 32 SDMMC3_nCD GPIO3 PV 02 SDMMC3 CD N V24 SDMMC3_CD_N vddio_sys 1 8V pu 33 eDP3 LVDSO_TXD4N AF3 LVDSO_TXD4N avdd 1 450 io 1 05V 1 34 SDMMC3 GPIO3 PQ 04 KB_COL4 AF28 SDMMC3_WP_N vddio_sys 1 8V pu 1 35 Ground X1 36 Ground 1 37
24. I low active nRESET PERIPH X6 39 periphery reset signal O low active VBAT_BKUP X6 40 PMU backup battery input 2 5V 3 6V Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 17 nONKEY X6 41 Power button I nWAKEUP POWER X6 43 power wakeup signal I low active WAKEUP LID X6 45 LID wakeup signal I high active FORCE nRECOVERY X2 51 Force to recovery mode I low active PMU GPIOA X6 47 PMU GPIO T O PMU_GPIOB X6 49 PMU GPIO T O 4 1 1 Signal descriptions e 2V5_AON_RTC This voltage rise after the PMU will be powered by the 5V_SYS The 5V_SYS will be loaded after the nPOWER_GOOD signal will be set low active This voltage should be used to pull the nWAKEUP_POWER pin 0580 TBD e 1 8 VDDIO The signal 1V8_VDDIO is a power source which is powered by PMU The maximum current is 600 mA e nRESET COM This signal reset the PMU It is pulled on the SoM against 2V5 AON 100k e nPOWER GOOD The power good signal low active indicate that the voltages 5 SYS and 43V3 SYS are okay This signal can be connect to the power good outputs of the power supplies Or it can also be connect to ground This signal is pulled against 5V_SYS 100k e nRESET PERIPH This output is pulled agai
25. POWER event The signal is pulled on the SoM with 10k against ground FORCE_nRECOVERY If this signal is low at the power up the Tegra will starts in recovery mode e PMU_GPIOA Free usable GPIO from the PMU PMU_GPIOB Free usable GPIO from the PMU 4 2 DAP PS The processor module support up to two 125 interfaces DAP2 and DAP4 The 125 Controller transports streaming audio data between system memory and an audio codec The controller supports 125 format Left justified Mode format Right justified Mode format and DSP mode format as defined in the Philips inter IC sound I2S bus specification The I2S and PCM master and slave modes interfaces support clock rates up to 24 576 MHz The 125 controller supports point to point P2P serial interfaces for the 125 digital audio streams I2S compatible products such as compact disc players digital audio tape devices digital sound processors and those with digital TV sound may be directly connected to the I2S controller The controller also supports the PCM and telephony mode of data transfer Pulse Code Modulation PCM is a standard method used to digitize audio particularly voice patterns for transmission over digital communication channels The Telephony mode is used to transmit and receive data to and from an external mono CODEC in a slot based scheme of time division multiplexing The I2S controller supports bidirectional audio streams and can operate in half duplex or full dup
26. Signals yan ei pr ds arn ee SR ae ae antes a Her ee Be Example schematiC p e uuo Bd a Le Y X eoo 4 Necessary layout properties Signals ee a ae eo ee Example Necessary layout properties OIL ee a dee ok ele ee Se aed le aed de Example Necessary layout properties 4 16 USB HSIC SG ew eH 4 16 1 4 16 2 4 16 3 5 Software 51 BCT SIGNALS Bk ba Eh bee ae Example Necessary layout properties 5 2 Bootloadet dua oos a ROM 5 3 Using tegra uboot flasher scripts 5 3 1 3 3 2 5 3 3 5 3 4 5 3 5 6 Pinout List Build cross compiling toolchain Checkout required sources and utilities Build required utilities Build U DOOt m we we XD ES d dg 3 Flash u boot to System 6 1 6 2 Connector pinout and pin muxing
27. compiles clear text BCT configuration files into BCT files 5 2 Bootloader Once the Tegra has read the BCT it jumps to the initial load address from which it should load a bootloader There are two bootloaders available for the Tegra K1 fastboot deprecated Fastboot is a minimalistic bootloader which is available in a special nvidia version supporting the Tegra This was the default for early software releases but shall not be used for new projects anymore u boot The u boot bootloader is the default bootloader for Tegra K1 running a mainline or LAT linux system u boot is an open source project http www denx de wiki U Boot and widely used as bootloader on embedded systems especially on ARM processors Avionic Design has added support for the Meerkat processor module as well as the Avionic Design Evaluation Carrier to u boot and provides the source code on github 5 3 Using tegra uboot flasher scripts The tegra uboot flasher scripts can be used to build a u boot image generate the BCT file and flash them to a Avionic Design Evaluation Carrier equipped with a Meerkat processor module The following steps show how to use tegra uboot flasher scripts for an Avionic Design Evaluation Carrier Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 5 Software 54 5 3 1 Build cross compiling toolchain In order to
28. gR 1 ClassName SDMMC3 T Eau CERCEBIOUTA SDMMC3 5138 GND SDMMC3 53 NOTE SDMMC3 LB OUT 33 924mm Average DATx 34 022mm 67 95mm Figure 4 5 SDMMC schematic example 4 12 3 Necessary layout properties Table 40 SDMMC3 1 interface signal routing requirements Max frequency 3 3V DS 25 12 5 MB s Actual frequencies my be 50 25 slightly different due to HS 55 12 5 clock source divider limi 1 8 SDRI2 50 25 tations SDR25 100 50 SDR50 208 104 SDR104 50 50 DDR50 Topology Point to Point Max loading per pin 10 pF Reference plane GND or PWR Breakout region impedance 45 50 Q 15 Trace impedance 45 50 Q 15 Max trace delay 1100 745 ps Include Package amp PCB routing delays for max SDR12 SDR25 SDR50 trace delays and max trace SDR104 delay skew parameters Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM LB OUT to LB IN length Average of DAT 3 0 Max trace delay skew in be 100 20 ps PCB routing delays for tween CLK amp CMD DAT Max trace delays and max trace delay skew parame SDR12 SDR25 SDR50 ters SDR104 Loopback clock routing 150 ps PCB routing delays for Max trace delays and max
29. in Table 4 Please note e Stress above the ranges listed in Table 3 can permanently damage the Tegra R processor module e Operate the Tegra R K1 processor module only under the recommended operation conditions see Table 4 Absolute maximum operation conditions Table 3 Absolute maximum operation conditions Parameter Explanation Min Max Unit Vmax 3V3_SYS Main 3 3 V power supply 0 5 V 3 63 V Vmax 5V_SYS Main 5 V power supply 0 5 7 0 V Vmax VBAT BKUP backup battery voltage OV 5 V Vmax PIN Voltage applied to powered I O pins 0 5 3 63 V Vmax USB VBUS USB supply voltage 0 5 V 6 0 enabled V 0 5 not enabled Operating temperature Measured by a thermal diode 25 105 C Storage temperature 40 125 C Storage humidity Relative humidity in a sealed bag less then 90 In the next table you will find the recommended operation parameters It is safe to operate the module under these conditions Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section Properties of the COM 15 Recommended operation conditions Table 4 Recommended operation conditions Parameter Explanation Typical Unit 3V3_SYS Main 3 3 V power supply 3 3 V 45V SYS Main 5 V power supply 5 V Vmax PIN Voltage applied to powered I O pins 3 3 or 1 8 V BKUP RTC backup battery volt
30. pair 45 60 sin Q 15 gle ended Trace spacing 4x microstrip 3x dielectric Mircostrip routing is rec stripline ommended for HDMI due to limited eye height and has longer MAX length Max Trunk delay 297 114 675 Microstrip mm ps Include package amp PCB MHz Stripline routing delays for Max trace delays and max trace delay skew parameters Max Trunk delay 225 204 1400 Microstrip mm ps Include package amp PCB MHz Stripline routing delays for Max trace delays and max trace delay skew parameters Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de 4 h i 5 2 Example schematic ps GS EXT HDMI INING em 1202 1 5 Len 100k FAUT Tpaegov H ins L RON TPSISSSDBV PIS 5 ina GND H GND 212 GND GND ClassName 990hms Ditt TVSRClmpUS Net CI a Maximum Via Count Constraint Max Count 2 1002 I Length Constraint Min Length mm Length 90mm 1 TDMS D2 SHIELD N TDMS D2 ii 25 TDMS rows pi seruo ADM TDMS Di EXT 3 HDME_TXD9_ P rio
31. 1 05V X3 16 USB2DP USB2 DP AD20 USB2 DP avdd usb 3 3V X3 17 Ground X3 18 USB2_D_N USB2_DN AE20 USB2_DN avdd_usb 3 3V X3 19 PEX_USB3_RX1_N PEX USB3 RXIN AL23 PEX USB3 RXIN dvddio pex 1 05V X320 Ground X321 PEX USB3 P PEX USB3 RXIP AK23 PEX USB3 RXIP dvddio pex 1 05V X322 PEX CLK2 P PEX CLK2P AC26 PEX CLK OUT 2 P vddio pex ctl 3 3V X3 23 Ground X3 24 PEX CLK2 N PEX CLK2N AC27 PEX CLK OUT 2 N vddio pex ctl 3 3V X325 PEX TX2 N PEX TX2N AJ23 PEX TX2N dvddio pex 1 05V X3 26 Ground X3 27 PEX_TX2_P PEX_TX2P AH23 PEX_TX2P dvddio pex 1 05V 3 28 USBI D USBI DN AF20 0581 DN avdd usb 3 3V X3 29 Ground X3 30 USBI D P USBI DP AG20 USBI1 DP avdd usb 3 3V 3 31 2 RX2N 21 PEX RX2N dvddio_pex 1 05V X3 32 Ground Isr noud 9 uonoog 9 op ugTsop oruorA OJU 0 1 81 88 0 0 67 410 281 88 L Awun S1nquieH 6 cc 01 durexoserA usIsaq oruortAV X3 33 PEX RX2 P PEX RX2P PEX RX2P dvddio pex 1 05V X3 34 USB VBUS ENI nOC GPIO3 PN 05 USB VBUS ACI usb vbus enl vddio hv 3 3V X3 35 Ground X3 36 USB VBUS ENO nOC GPIO3 PN 04 USB VBUS ABI usb vbus 0 vddio hv 3 3V X3 37 PEX TX3 N PEX TX3N AG23 PEX_TX3N dvddio pex 1 05V X3 38 Ground X3 39 PEX TX3 P PEX TX3P AF23 PE
32. 1 62 RBR Min UI 185 HBR2 370 ps HBR 617 Number of loads 1 load Topology Point to Point Differen tial unidirectional Termination 100 Q on die at TX RX Max breakout PCB length 7 63 mm Trace impedance Diff Single 90 45 60 Q 15 Stripline Routing for Main Trunk Max trace length from Tegra TX pin 215 RBR HBR mm Max trace delays amp max to connector 165 HBR2 trace delays skew match ing must include substrate pin delays unless other wise specified Max propagation delay HBR2 1137 ps Max number of signal vias 4 RBR HBR 2 HBR2 one more test via HBR2 right after AC cap OK PCB pair to pair spacing 3x dielectric height 3x of the thinner of above and below PCB main link to AUX spacing 3x dielectric height 3x of the thinner of above and below Max stub length on the vias allowed Rout below core to mini mize stub length Microstrip routing for main trunk Max trace length from Tegra TX pin to 215 RBR HBR mm Max Trace Delay amp Max connector 127 152 4 HBR2 Trace Delay Skew match 5x 7x spacing ing must include substrate pin delays Max propagation delay HBR2 7x 750 900 ps 150 ps inch delay as spacing sumption for microstrip Max number of signal vias 4 RBR HBR 2 HBR2 one more test via HBR2 right after AC cap OK PCB pair to pair spacing 4x RBR HBR dielectric height 5x 7x HBR2 PCB main link to AUX spacing 5x dielectric height Signal skews Stripline or Mircolin
33. 1 8V GPIOs signals GPIO_PC7 X4 43 I O GEN2_I2C_IRQ GPIO PEE2 X5 39 I O SATA PWR EN GPIO PHO X4 12 I O FAN PWM GPIO 4 52 HDMI VDD EN GPIO PH2 X4 11 I O BL PWM PH3 X4 20 I O GPIO PHA 4 9 I O BL EN GPIO PH5 X4 7 I O PH6 X4 6 I O GPIO PD X4 24 GPIO X4 18 SPI4C_nCS1 GPIO 5 X4 4 4 5 Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 infoG avionic design de www avionic design de Section 4 Interfaces of the COM GPIO PJO X4 10 GPIO PJ2 X4 36 GPIO 4 14 I O GPIO X4 3 2 X4 8 GPIO 4 2 GPIO X4 22 GPIO 2 X5 41 SATA LED X5 13 SPIBE MOSI GPIO PO2 X5 19 SPI3E_MISO GPIO X5 23 I O SPBE SCK GPIO 4 X5 27 SPI3E_nCS1 X5 54 GPIO 5 21 5 X5 18 GPIO X5 25 I O SDMMC3 VDD EN GPIO PR2 X5 38 I O AUDIO EN GPIO PRA X5 20 GPIO PR5 5 16 GPIO 5 29 GPIO PR7 5 22 HEAD DET GPIO PTO X5 31 I O SOC ALIVE X4 48 SDM
34. 1 Signals Table 19 IC GENI 1V8 signals GENI DC SCL 5 2 GENI DC clock GENI DC SDA X5 4 GENI data VO Table 20 IC GEN2 3V3 signals GEN2 DC SCL X4 45 GEN2 DC clock O GEN2 2 SDA X4 47 GEN2D2C data I O Table 21 IC CAM 1V8 signals DC SCL 1 56 Camera DC clock CAM DC SDA X1 58 Camera I2C data Table 22 HDMI DDC signals SCL X1 4 HDMI DDC clock SDA X1 2 HDMI DDC data 4 6 2 Example schematic No special schematics are required 4 6 3 Necessary layout properties The I2C bus lines are pulled already on the SoM Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 29 47 JTAG series processors have an optional JTAG interface that can be used for SCAN testing or for communica tion with either integrated CPU 4 7 A Signals JTAG signals JTAG nTRST X4 21 Test reset I Normal operation Pull down only Do connect to TRST pin of connector Scan test mode Connect to TRST N pin of the connector pulled with 10k to GND on the SoM RTCK X4 23 Return Test reset JTAG_TCK X4 15 Test clock JTAG_TDI X4 19 Test data In JTAG_TDO X4 25 Test data Out JT
35. 17 TMS JTAG TMS 15 JTAG TMS vddio sys 2 pu 1 8 v9 op ugTsop oruorA OJU 0 1 81 88 0 0 67 410 281 88 L Awun S1nquieH 6 cc 01 durexoserA usIsaq oruortAV X4 18 SPI4C_nCS1 GPIO3_PI 04 GPIO_PI4 SPI4C CSI tracedata6 vddio a 8V X4 19 JTAG TDI JTAG TDI H5 TDI vddio sys 2 pu 1 8V X4 20 GPIO_PH3 GPIO3 PH 03 GPIO PH3 V8 PM3_PWM3 vddio_gmi pd 1 8V X421 JTAG_nTRST JTAG_TRST_N H4 JTAG_TRST_N vddio_sys_2 pd 1 8V X4 22 GPIO_PK4 GPIO3_PK 04 GPIO_PK4 TI SDMMC2A 5 vddio_gmi pu 1 8V X4 23 JTAG_RTCK JTAG_RTCK JTAG_RTCK vddio_sys_2 pu 1 8V X4 24 2 GPIO3 PL02 GPIO PI2 SDMMC2A tracedata5 vddio_gmi pu 1 8V X4 25 JTAG_TDO JTAG_TDO JTAG TDO vddio sys 2 0 1 8V X4 26 Ground X4 27 unconnected X4 28 UART2_RXD GPIO3_PC 03 UART2_RXD L9 IR3 RXD vddio_uart pu 1 8V X4 29 Ground X4 30 UART2 TXD GPIO3 02 UART2 TXD M8 IR3_TXD vddio_uart pu 1 8V X4 31 unconnected X4 32 UART2_nRTS GPIO3 PJ 06 UART2 RTS N P4 UB3 RTS vddio_uart pu 1 8V X4 33 Ground X4 34 UART2 nCTS GPIO3 PJ 05 UART2 CTS N MI UB3 CTS vddio pu 1 8V X4 35 UART4 DEBUG nCTS GPIO3 PB 01 GPIO PBI v9 UD3 CTS vddio_gmi 2 1 8V X4 36 G
36. 2 5 50 DAP2 SCLK GPIO3 PA 03 DAP2 SCLK M29 1251 SCLK vddio audio pd 1 8V 5 51 5 MOSI GPIO3 PY 00 ULPI CLK 7 DOUT vddio bb 1 8V 2 5 52 Ground Isr noud 9 uonoog 89 op ugTsop oruorA OJU 0 1 81 88 0 0 67 410 281 88 L Awun S1nquieH 6 cc 01 durexoserA usIsaq oruortAV X5 53 SPI4C nCSO GPIO3 03 SPI4C CSO vddio a 8V X5 54 GPIO3 PP 00 DAP3 FS 5 1252 LRCK vddio bb 1 8V pd X5 55 SPI4C MOSI GPIO3 PG 06 GPIO PG6 Y8 SPI4C DOUT vddio_gmi 2 1 8V X5 56 SPDIF OUT GPIO3 PK 05 SPDIF OUT ACA SPDIF OUT vddio hv 3 3V pu X5 57 SPI4C_MISO GPIO3_PG 07 GPIO_PG7 V3 SPI4C_DIN vddio_gmi 2 1 8V X5 58 SPDIF IN GPIO3 PK 06 SPDIF IN AA8 SPDIF_IN vddio hv 3 3V pd X5 59 SPI4C SCK GPIO3 PG 05 5 AA3 SPI4C SCK vddio 2 1 8 X5 60 CODEC nIRQ GPIO3 PU 05 5 M4 vddio_uart 2 1 8V X6 1 Ground X6 2 Ground X6 3 Ground X6 4 Ground X6 5 Ground X6 6 Ground X6 7 Ground X6 8 Ground X6 9 Ground X6 10 Ground X6 11 5V_SYS X6 12 5V_SYS X6 13 45V SYS X6 14 45V SYS X6 15 45V SYS X6 16 45V SYS X6 17 45V SYS X6 18 45V SYS X6 19 45V SYS X6 20 45V SYS Isr noud 9 uonoog
37. 69 op ugTsop oruorA OJU 0 1 81 88 0 0 67 A 10 281 88 L Awun S1nquieH 6 cc 01 durexoserA usIsaq oruotAV X6 21 45V SYS X6 22 45V SYS X6 23 5V_SYS X6 24 45V SYS X6 25 45V SYS X6 26 2 5 AON AS3722 PMU H2 X6 27 Ground X6 28 Ground X6 29 Ground X6 30 Ground X6 31 Ground X6 32 Ground X6 33 0580 ID AS3722 PMU Bll X6 34 unconnected X6 35 1V8_VDDIO X6 36 1V8_VDDIO X6 37 nRESET COM Pull Up on SoM against 2 5 V X6 38 nPOWER GOOD Pull Up on SoM against 5V X6 39 nRESET PERIPH Pull UP on SoM against 1 8V X6 40 VBAT_BKUP RTC Batterie Voltage X6 41 nONKEY Pull Up on SoM against 2 5V X6 42 3V3_SYS X6 43 nWAKEUP POWER pull up required on carrier against 2V5_AON_RTC X6 44 3V3_SYS X6 45 WAKEUP LID pull down re quired on carrier X6 46 3V3_SYS Isr noud 9 uonoog OL op ugTsop oruorA OJU 0 1 81 88 0 0 67 A 10 281 88 L S1nquieH 6 cc 01 dureyases ustsoq X6 47 PMU GPIOA AS3722 PMU GPIO X6 48 43V3 SYS X6 49 PMU GPIOB AS3722 PMU GPIO X6 50 43V3 SYS X6 51 Ground X6 52 Ground X6 53 Ground X6 54
38. 70 Mht i e it will generate 6x 10x and 20x high frequency clock 1 6 GHz for RBR 2 7 GHz for HBR and 5 4 GHz for HBR2 4 3 1 Signals Table 10 embedded DisplayPort eDP signals eDP HPD X1 10 eDP Hot Plug detect I O eDPO N X1 39 eDP data lane negative O eDPO P X1 37 eDP data lane positive O eDP1 X1 45 eDP data lane negative O eDP1 P X1 43 eDP data lane positive O eDP2 N X1 55 eDP data lane negative O eDP2 P X1 57 eDP data lane positive O eDP3_N X1 33 eDP data lane negative O eDP3_P X1 31 eDP data lane positive O LVDS_TXD3_N X1 49 LVDS lane 3 negative O LVDS is not supported LVDS_TXD3_P X1 51 LVDS lane 3 positive O LVDS is not supported DP AUX CHO N eDP Auxiliary Channel Connect to AUX on the display connector DP AUX CHO P eDP Auxiliary Channel Connect to AUX on the display connector EN LVDS EDP X5 17 eDP enable signal Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 4 3 2 Example schematic Schematics follow soon 4 3 3 Necessary layout properties 22 Table 11 eDP HBR2 main link signal routing requirements Max data rate per data lane 54 HBR2 Gbps 27 HBR
39. 9 0583 26 147 4 173 4 0583 26 147 4 173 4 RX2 39 159 2 198 2 RX2 38 160 2 198 2 PEX TX2 N 37 142 9 179 9 PEX TX2 P 36 143 6 179 6 PEX RX3 N 45 147 2 192 2 PEX RX3 P 45 147 2 192 2 PEX TX3 N 29 165 4 194 4 PEX TX3 P 28 166 3 194 3 PEX RX4 49 145 3 194 3 PEX RX4 P 48 146 4 194 4 PEX TX4 N 39 168 6 207 6 PEX TX4 P 39 168 6 207 6 4 11 SATA The Serial ATA SATA controller enables a control path from the Tegra processor to an external SATA device A SSD HDD ODD drive can be connected Controller can support the maximum troughput of a Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 infoG avionic design de www avionic design de Section 4 Interfaces of the COM 39 GEN 2 drive Features e SATA specification rev 3 1 and AHCI specification rev 1 3 1 compliant Including all errata ENC and TP except DHU direct head unload e Device sleep feature support Software initialed device sleep from slumber state only Software initialed device sleep from any link states active partial slumber Hardware initialed aggressive device sleep management e Port multiplier support Command based switching CBS FIS based switching FBS e Supported Cables and connectors Standard internal connector Internal micro connector Internal slimline connector mSATA connector BGA SSD in
40. A nCSO X5 53 Chip Select SPI4_SCK 5 59 Serial Clock NOTE SPI2 and SPI3 are not officially supported from NVIDIA You can use them on your own risk The SPI3 interface pins will be used as GPIOs per default Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 46 4 14 2 Example schematic No special schematics are required 4 14 3 Necessary layout properties no necessary layout properties 4 15 UART The Universal Asynchronous Receiver Transmitter UART controller provides serial data synchronization and data conversion parallel to serial and serial to parallel for both receiver and transmitter sections Syn chronization for serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character Data integrity is accomplished by attaching a parity bit to the data character The parity bit can be checked by the receiver for any transmission bit errors Features Synchronization for the serial data stream with start and stop bits to transmit data and form a data character Supports both 16450 and 16550 compatible modes Default mode is 16450 Device clock up to 200 MHz baudrate of 12 5 Mbits second Data integrity by attaching parity bit to the data character Support for word lengths from five to ei
41. AG_TMS X4 17 Test mode select O 4 7 2 Example schematic No special schematics are required 4 7 3 Necessary layout properties no necessary layout properties 4 8 MIPI CSI The Camera Serial Interface CSI is based on MIPI CSI 2 0 specification and implements the CSI receiver which receives data from an external camera module with a CSI transmitter It consists of two CSI receiver interfaces so it can receive serial transmissions from two cameras Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 30 e MIPI CSI 2 0 receiver e Support for 3 camera sensors any 2 can be active at the same time 1 x4 single camera with 4 lane sensor 1 x4 1 x1 one high resolution camera nad antoher front facing low resolution camera 2 x4 dual cameras for stereo with 4 lanes for each camera e Supported input data formats RGB RGB888 RGB666 RGB565 RGB555 RGB444 YUV YUV422 8b YUV420 8b legacy 420 8 YUV444 8b RAW RAW6 RAW7 RAW8 RAWIO RAW12 RAW14 DPCM user defined User defined JPEG8 Embedded Embedded control information e Supports single shot mode e D PHY Modes of Operation High Speed Mode High speed differential signaling up to 1 5 Gbps burst transmission for low power Low Power Control Single ended 1 2 V CMOS
42. AJ8 CSI E CLK N avdd dsi csi 1 2V X2 12 Ground X2 13 Ground X2 14 DSI DO DSI B DO P AJ12 DSI B avdd dsi csi 1 2V X2 15 DI DI P AH9 5 B DI avdd dsi csi 1 2 2 16 DSI B DSI B 2 DSI B DO avdd dsi csi 1 2V X2 17 B DI 5 B DI 9 5 avdd dsi csi 1 2V X2 18 Ground X2 19 Ground X2 20 DSI B CLK N DSI B DSI B avdd dsi csi 1 2V X2 21 CSI_B_DO_N CSI_B_DO_N AK8 CSI_B_DO_N avdd_dsi_csi 1 2 Isr noud 9 uonoog 65 op ugTsop oruorA OJU 0 1 81 88 0 0 67 410 281 88 L Awun S1nquieH 6 cc 01 durexoserA usIsaq oruortAV 2 22 DSI B CLK P DSI B CLK P DSI B CLK P avdd dsi csi 1 2V X2 23 CSLB DO CSI B DO P ALS CSI B avdd dsi csi 1 2V X2 24 Ground X2 25 Ground X2 26 DSI B D2 DSI B D2 ALI2 DSI B D2 avdd dsi csi 1 2V X2 27 CSI CSI AK9 CSI avdd dsi csi 1 2V X2 28 DSI B D2 P DSL B D2 AKI2 DSI B D2 P avdd dsi csi 1 2V X2 29 CSI A DO P CSI A DO AL9 5 DO avdd dsi csi 1 2V X2 30 Ground 2 31 Ground X2 32 DSI A DO DSI A AKII DSI A avdd dsi csi 1 2V X2 33 CSLA DI P 5 DI P AD9
43. CMD vddio sd mmc1 pu 1 8V X1 53 Ground 1 54 2 MCLK GPIO3 PBB 00 GPIO PBBO 5 2 alt3 vddio cam pd 1 8V 1 55 eDP2 LVDSO_TXDON AJ2 LVDSO TXDON avdd lvdsO 1 05V X1 56 I2C SCL GPIO3 01 CAM DC SCL AF8 I2C3 vddio cam 2 1 8V 1 57 eDP2 LVDSO_TXDOP AJ3 LVDSO TXDOP avdd lvdsO 1 05V 1 58 2 SDA 02 SDA AG8 12C3_DAT vddio_cam 2 1 8V X1 59 Ground Isr noud 9 uonoog 85 op ugTsop oruorA OJU 0 1 81 88 0 0 67 410 281 88 L Awun S1nquieH 6 cc 01 durexoserA usIsaq oruortAV X1 60 MCLK GPIO3 00 CAM MCLK vimclk alt3 vddio cam 1 8V X2 Ground X2 2 DSI_B_D1_P DSL B DI P ADI2 DSL B DI avdd dsi csi 1 2V X2 3 CSI E CSI E AF9 CSI_LE_DO_N avdd_dsi_csi 1 2V X2 4 DSI B DI DSI B DI N AE12 DSI_B_D1_N avdd_dsi_csi 1 2V X2 5 CSI E DO P CSI E DO P AG9 CSI E DO P avdd dsi csi 1 2V X2 6 Ground X2 7 Ground X2 8 DSI_B_D3_P DSI_B_D3_P AGI2 DSI B D3 P avdd dsi csi 1 2V X2 9 5 CLK P CSI E CLK P AH8 CSI E CLK P avdd dsi csi 1 2V X2 10 DSI B D3 N DSI B D3 N AFI2 DSI D3 avdd dsi csi 1 2V X2 11 CSI E CLK N CSI E CLK N
44. DMI TXD2 N 49 182 6 231 6 HDMI TXD2 P 50 182 6 232 6 27 Inter Chip Communication I2C controller implements I2C master and slave controller The controller supports multiple masters and slaves in Standard mode up to 100Kbit s Fast mode up to 400Kbit s Fast mode plus FM up to IMbit s and High speed mode up to 3 4Mbit s of operations A general purpose I2C controller allows system expansion for I2C based devices such as AM FM radio remote LCD display serial ADC DAC and serial EPROMs as defined in the NXP Inter IC bus I2C speci fication The I2C bus supports serial device communications to multiple devices The I2C controller handles bus mastership with arbitration clock source negotiation speed negotiation for standard and fast devices and 7 bit and 10 bit slave address support according to the 12 protocol and supports master and slave mode of operation The following table shows the our default U Boot and Kernel bus number assignment Table 18 bus number assignment i2c0 GENI DC 1 8V I2C bus i2cl GEN2 DC 3 3V D2C bus 12 2 CAM DC 1 8V I2C bus Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 1223 HDMI DDC 5V tolerant I2C bus 1224 PWR 2 1 8V I2C bus only on the SoM 4 6
45. E 57 97 5 154 5 CSI E 58 96 5 154 5 4 9 MIPI DSI The MIPI Display Serial Interface DSI us a serial bit stream replacement for the parallel MIPI DPI and DBI display interface standards DSI reduces package pin count and I O power consumption DSI support enables both display controllers to connect to an external display s with a MIPI DSI receiver The DSI transfers pixel data from the internal display controller to an external third party LCD module Features e Phy Layer Start End of transmission Other out of band signaling Per DSI interface 1 Clock Lane up to 4 data lanes Supports link configuration 1x4 2x4 Supports Dual link operation in 2x4 configurations for asymmetrical symmetrical split in both left right side or odd even group split schemes Maximum link rate 1 5 Gbps as D PHY 1 1v version Maximum 10 MHz LP receive rate e Maximum resolution supported Dual link 2x4 3840x1920 60Hz 24 bpp at 1 5 Gbps per lane Single link 1x4 2560x1440 60Hz 24 bpp at 1 5 Gbps per lane e Lange Managment Layer with Distributor e Protocol Layer with Packet Constructor e Supports MIPI DSI 1 0 1v version mandatory features e Command Mode one shot with host and or display controller as master e Clocks Bit clock Serial data stream bit rate clock Byte clock Lane management layer byte rate clock Application clock Protocol layer byte rate clock e
46. Error Detection Correction ECC generation for packet Headers Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 infoG avionic design de www avionic design de Section 4 Interfaces of the COM Checksum generation for Long Packets e Error recovery e High speed transmit timer e Low power receive timer e Turnaround acknowledge Timeout 4 9 1 Signals Table 27 MIPI DSI signals DSI A X2 46 DSI clock negative O DSI CLK P 2 44 DSI clock positive O DSI X2 32 DSI bidirectional data lanes negative DSI A DO P X2 34 DSI bidirectional data lane positive DSI DI X2 56 DSI bidirectional data lane negative I O DSI ADI P X2 58 DSI bidirectional data lane positive I O DSI 2 X2 40 DSI bidirectional data lane negative DSI A D2 P X2 38 DSI bidirectional data lane positive I O DSI D3 X2 52 DSI bidirectional data lane negative DSI A D3 P X2 50 DSI bidirectional data lane positive I O DSI B CLK N X2 20 DSIclock negative O shared with CSI C D DSI B 2 22 DSIclock positive O shared with CSI C D DSI B X2 16 DSI bidirectional data lane negative I O shared with CSI C D DSI B DO X2 14 DSI bidirectional data lane positive I O shared with C
47. GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 16 The processor module COM requires the below external sequencing 45V SYS 3V3 SYS 2V5_AON_RTC 1V8_VDDIO nPOWER_GOOD nONKEY nWAKEUP POWER nRST in x ea Figure 3 6 Power sequence 4 Interfaces of the COM In this chapter you will find information that will help you develop a carrier board for the Tegra R processor module The COM has a larger number of interfaces and some of these have specified layout properties When you develop your own carrier you need to obey these properties This chapter will give you examples of schematics for the interfaces and it will list the signals of the inter faces Please note e Read all the information in this chapter carefully when you develop a carrier board If you have any questions on how to develop your own carrier board please contact Avionic Design 41 processor module special functions Table 5 Meerkat special functions 2V5 AON X6 26 Pull up voltage P USBO ID PMU X6 33 TBD I 1V8_VDDIO X6 35 1 8V power source P 1V8_VDDIO X6 36 1 8V power source P nRESET_COM X6 37 SoM reset signal I low active nPOWER_GOOD X6 38 power good signal
48. Ground X6 55 Ground X6 56 Ground X6 57 Ground X6 58 Ground X6 59 Ground X6 60 Ground NVIDIA does not officially support these interfaces You can use them on your on risk moug 9 uonoog IL Section 7 Reference documents 72 7 Reference documents In the following chapter you can find a list of documents that will provide you with more information on the processor module and the carrier You can find information about the Tegra R K1 SoC on their website https developer nvidia com Technical Reference Manual for Tegra processor module Please note To access the TRM you need to follow these steps 1 Be registered on the NVIDIA Developer website 2 Apply for the Tegra Registered Developer Program through your account settings Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 8 Contact 8 Contact Figure 8 1 head office in Duvenstedt Germany If you have any questions about the Tegra R processor module you can contact us at Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany Fon 49 40 88187 0 Fax 49 40 88187 150 E Mail info avionic design de www avionic design de Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de
49. MCI EN GPIO PU5 X5 60 CODEC nIRQ GPIO PW2 X5 8 I O GPIO PW3 X5 43 I O GPIO PX3 X5 36 SPDD nIRQ GPIO PX5 5 14 GENI DC nIRQ GPIO PX6 X5 12 I O GPIO PX7 X5 10 I O Table 14 3 3V GPIOs signals GPIO 5 X5 56 I O SPDIF OUT GPIO PK6 X5 58 I O SPDIF IN 4 4 Example schematic No special schematics are required 4 4 3 Necessary layout properties It is necessary that all Inputs are not powered unit the Tegra is running Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 25 4 5 HDMI High Definition Multimedia Interface HDMI support provides a unified method of transferring both audio and video data over a TMDS compatible physical link to an audio visual device The HDMI block receives video from either display controller and audio from a separate high definition audio HDA controller it combines and transmits them as appropriate Features e High definition Multimedia Interface HDMI specification 1 4b e High bandwidth Digital Content Protection HDCP system specification 1 4 e On Chip HDCP key storage no external SecureROM required e TMDS Transition Minimized Differential Signaling PHY I F 4 5 1 Signals Table 15 HDMI signals HDMI CEC X1 6 HDMI Consumer Electronics Control
50. PIO_PJ2 GPIO3 PJ 02 2 WI soc therm oc4 n vddio_gmi pu 1 8V X4 37 UART4 DEBUG TXD GPIO3 PJ 07 7 V4 UD3 TXD vddio_gmi 2 1 8V X4 38 UART3 RXD GPIO3 PW 07 UART3_RXD M3 UC3_RXD vddio_uart pu 1 8V X4 39 UART4_DEBUG_nRTS GPIO3_PK 07 GPIO_PK7 V5 UD3_RTS vddio_gmi 2 1 8 Isr noud 9 uonoog 59 op ugTsop oruorA OJU 0 1 81 88 0 0 67 410 281 88 L Awun S1nquieH 6 cc 01 durexoserA usIsaq oruortAV X4 40 UART3 TXD GPIO3 PW 06 UART3 TXD UC3 TXD vddio a 8V X441 UART4_DEBUG_RXD GPIO3 PB 00 GPIO PBO 04 UD3 RXD vddio_gmi 2 1 8V X4 42 UART3 nRTS GPIO3 00 UART3 RTS N R9 UC3 RTS vddio_uart pu 1 8V X4 43 GEN2 2 nIRQ GPIO3 PC 07 UL vddio_gmi pu 1 8V X4 44 UART3_nCTS GPIO3_PA 01 UART3_CTS_N 8 UC3 CTS vddio_uart pu 1 8V X4 45 GEN2 DC SCL GPIO3 PT 05 GEN2 DC SCL 2 I2C2 vddio 2 3 3 4 46 Ground 4 47 GEN2 1 2 SDA GPIO3 PT 06 GEN2 DC SDA AA2 I2C2 DAT vddio_gmi 2 3 3V X4 48 SDMMCI EN GPIO3 01 P2 UA3 RXD vddio 2 1 8 X4 49 Ground X4 50 CLK3 OUT GPIO3 PEE 00 CLK3 OUT P7 extperiph3 clk vddio_uart 2 1 8 X4 51 DAP4_SCLK GPIO3_PP 07 DAP4_SCLK 1253 SCLK vddio_uart pd 1 8V X4 52 HDMI_
51. Peripheral 3 Clock Connect to MCLK pin of the audio device if reference clock is required Conntect to MCLK if DIN X4 55 Data In DAP pins support I2S PCM audio Interface can be master or slave DOUT X4 57 Data Out DAP pins support I2S PCM audio Interface can be master or slave FS X4 53 Frame Sync Word Select DAP pins support I2S PCM audio Interface can be master or slave T O DAP4_SCLK X4 51 Serial Clock Bit Clock DAP pins support I2S PCM audio Interface can be master or slave T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany 19 Section 4 Interfaces of the COM 20 4 2 2 Example schematic 1V8 EXT place close to Pin 10 place close to Pin 24 place close to Pin 40 z z 2 N place close to Pin 39 Ii 52 ClassName GENI Net Class GNP GND 9 a 4u7_6V3 4u7_6V3 100n_16V J 202 16V GEN SDA GEN SCL DAP DIN LINE OUT 259 lu 6 4E C GENI DC HPOUTL 1 6 4 DAP2 LINE OUT L C60 1u 10V 1 Net Class ClassName DAP2 MBIAS TPISTPI9TP20TP21 C61 C62 Audio Codec WM8903 THEE GND GND Figure 4 1 DAP2 schematic example 4 2 3 Necessary layout properties
52. Point to Point Unidirectional differen tial Configuration Device or 1 load ganization Max loading per pin N A pF see return loss spec in PCIe 2 0 spec Termination 50 Q To GND single ended for P amp N Reference plane GND Breakout region Width 4 mils line spacing Breakout region pair 10 mils Maximum pair spacing of spacing 500 mils Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 38 Trace impedance 90 diff pair 45 55 sin gle ended Pair to Pair Trace Spacing 3x stripline 4x mi dielectric crostrip Max trace length delay 254 1700 mm ps Max intra pair within 1 ps PCB routing delays for pair skew Max trace delays and max trace delay skew parame ters Max inter pair pair pair 600 ps PCB routing delays for RX TX skew Max trace delays and max trace delay skew parame ters Table 34 PCIe interface delays PEX CLK1 N 73 149 8 222 8 PEX P 72 150 5 222 5 PEX CLK2 N 67 147 2 214 2 PEX CLK2 P 64 149 8 213 8 USB3 43 145 7 188 7 0583 43 145 5 188 5 0583 36 146 4 182 4 0583 35 147 6 182 6 0583 46 136 6 182 6 0583 46 136 9 182
53. SI C D DSI X2 4 DSI bidirectional data lane negative I O shared with CSI C D DSI B DI P X2 2 DSI bidirectional data lane positive I O shared with CSI C D DSI B D2 X2 26 DSI bidirectional data lane negative I O shared with CSI C D DSI B D2 P X2 28 DSI bidirectional data lane positive I O shared with CSI C D DSI X2 10 DSI bidirectional data lane negative I O shared with CSI C D DSI B D3 P X2 8 DSI bidirectional data lane positive I O shared with CSI C D 4 9 2 Example schematic No special schematics are required 4 9 3 Necessary layout properties Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de 33 Section 4 Interfaces of the COM Table 28 DSI interface signal routing requirements Max frequency data rate 750 1500 MHz Mbps per data lane Number of loads 1 load Max loading per pin 10 pF Reference plane GND or PWR If PWR 10nF decoupling cap required for return current Breakout region 90 diff 45 55 single Q 15 impedance ended Max PCB breakout delay 48 ps Trace impedance 90 diff pair 45 55 sin Q gle ended Via proximity signal to lt 3 8 24 mm ps reference Trace spacing 2x microstrip stripline dielectric Max trace
54. User Manual Embedded Tegra K1 processor module avionic design Product information Product Embedded Tegra K1 processor module Product number 1477 110 000 Manufacturer Avionic Design GmbH Wragekamp 10 22397 Hamburg In cooperation with NVIDIA C Year 2014 Revision history Document number Date Version Remarks 1477 011 315 01 23 06 2015 01 first release 1477 011 315 00 26 01 2015 00 Preliminary release Copyright All the rights to this manual provided through this service revert to AVIONIC DESIGN GmbH Any and all reproduction modification or publication of the guides and or manuals either in part or their entirety without the permission of AVIONIC DESIGN GmbH is prohibited under copyright laws NVIDIA the NVIDIA logo and TEGRA are trademarks and or registered trademarks of NVIDIA Corpora tion Other company and product names may be trademarks of the respective companies with which they are associated The Embedded Tegra K1 products are subject to change Please check www avionic design de for updates Section Document Change History 1 Document Change History 01 23 06 2015 Table 1 Document Change History Meerkat Rev02 changes e Define X5 10 as Disable e Change the VDDIO GMI and VDDIO BB voltage from 3 3V to 1 8V like on Jetson The level of the following pins are affected X4 2 PK3 X4 2 GPIO PK3 X4 3 GPIO PK1 X4 4
55. VDD_EN GPIO3_PH 01 GPIO PHI U3 PM3 PWMI vddio pd 1 8V X4 53 FS GPIO3 PP 04 FS PI 1253 LRCK vddio_uart pd 1 8V X4 54 CAM1_PWDN GPIO3_PBB 05 GPIO 5 5 VGP5 vddio_cam pd 1 8V X4 55 DAP4_DIN GPIO3_PP 05 DAP4_DIN P3 12S3_SDATA_IN vddio_uart pd 1 8V X4 56 CAM_nRST GPIO3_PBB 03 GPIO_PBB3 AK6 VGP3 vddio_cam pd 1 8V X4 57 DAP4_DOUT GPIO3 PP 06 DAP4 DOUT P5 1253 SDATA OUT vddio pd 1 8V X4 58 CAM2 PWDN GPIO3 PBB 06 GPIO PBB6 AL6 vddio cam pd 1 8V X4 59 Ground X4 60 BOOT SEC Pull Down on SoM against GND Isr noud 9 uonoog 99 op ugTsop oruorA OJU 0 1 81 88 0 0 67 410 281 88 L Awun S1nquieH 6 cc 01 durexoserA usIsaq oruortAV SPI2D_nCSO GPIO3_PS 05 KB ROWI3 SPI2D 0 vddio_sys 1 8 X52 GENI DC SCL GPIO3 PC 04 GENI DC SCL P6 vddio_uart 2 1 8 5 3 SPI2D MOSI GPIO3 PQ 00 KB COLO AD30 SPDD DOUT vddio sys 1 8 pu X5 GENI 2 SDA GPIO3 PC 05 GENI DC SDA M6 2 DAT vddio_uart 2 1 8 5 5 SPI2D_SCK GPIO3_PS 06 KB_ROW14 AC30 SPI2D_SCK vddio sys 1 8V pd X5 6 Ground X517 SPI2D_MISO GPIO3_PQ 01 KB COLI AC28 SPDD DIN 1 vddio sys 1 8 pu X5 8 GPIO PW2 GPIO3 PW 02 GPIO W2 AUD M28
56. VIDIA cbootimage git git clone https github com N VIDIA tegrarcm git git clone https git kernel org pub scm utils dtc dtc git 4 Checkout configuration repositories git clone https github com avionic design cbootimage configs git 5 Checkout u boot git clone branch tk1 master https github com avionic design u boot git Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 5 Software 55 5 3 3 Build required utilities cd BUILD_DIR tegra uboot flasher scripts build tools 5 3 4 Build u boot Make sure that the environment variable CROSS COMPILE is correctly set cd BUILD_DIR tegra uboot flasher scripts build boards kein baseboard build 5 3 5 Flash u boot to System 1 Connect the USB debug port of the baseboard to your host PC 2 Put the carrier into recovery mode 3 Make sure that the carrier was detected on the USB host by running lsusb grep NVidia Output should look like this Bus 001 Device 011 ID 0955 7140 NVidia Corp Bus number and device may be different on your system 4 Flash u boot onto the system sudo tegra uboot flasher flash kein baseboard Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de op ugTsop or
57. X TX3P dvddio pex 1 05V X3 40 unconnected X3 41 Ground X3 42 GPIO_PBB4 GPIO3_PBB 04 GPIO_PBB4 AH6 vddio cam 1 8V X3 43 PEX RX3 P PEX RX3P AL24 PEX RX3P dvddio pex 1 05V X3 44 PEX L0 nCLKREQ GPIO3 PDD 02 PEX 10 CLKREQ AK29 peO clkreq 1 vddio pex ctl 3 3V X3 45 RX3 PEX RX3N AK24 PEX RX3N dvddio_pex 1 05V X3 46 PEX LO nRST GPIO3 PDD 01 PEX 10 RST AJ29 rst 1 vddio pex ctl 3 3V 3 47 Ground X3 48 PEX L1 nCLKREQ GPIO3 PDD 06 CLKREQ AJ30 pel clkreq vddio pex ctl 3 3V X3 49 PEX RX4 N PEX_RX4N AL26 PEX_RX4N dvddio_pex 1 05V X3 50 PEX L1 nRST GPIO3 PDD 05 PEX RST AJ31 pel_rst_l vddio_pex_ctl 3 3V X3 51 PEX_RX4_P PEX_RX4P AK26 PEX_RX4P dvddio_pex 1 05V X3 52 PEX nWAKE GPIO3 PDD 03 PEX WAKE N AG28 pe wake vddio pex ctl 3 3V X3 53 Ground X3 54 USB VBUS EN2 nOC GPIO3 USB VBUS EN2 AG29 usb vbus en2 vddio pex ctl 3 3V X3 55 PEX TX4 P PEX TX4P AJ26 PEX TX4P dvddio pex 1 05V 187121004 9 uonoog 9 Nn 5 3 56 Ground 3 57 PEX_TX4N AH26 PEX_TX4N 5 dvddio_pex 1 05V X3 58 CLKIN AG26 PEX CLK OUT vddio pex ctl 0 E 3 3V X3 59 Ground 20 3 60 PEX_CLKI_P 8 AF26
58. a lane4 positive O Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de 36 Section 4 Interfaces of the COM 37 4 10 2 Example schematic ClassName PCIE ClassName 9 Ohms Diff Net Class Net Class N SSS SUF EX ean T TE 816 10 PEX LI aRST Figure 4 3 PCI Express schematic example 3V3 1 5 mPCIE Socket H 32 273 H thar P 74 Ics ND Maximum Vis Count Constraint Max Count 111281 5367 mn Ma Langh Rule 530 EXT EET Net Class ClaseName mPCIE Maximum Via Count Constraint Max Count Legit Constant Min Length mm Legi 250mm ClassName 90Ohme Ditr PCB Rule Net Class 7 Nb ClassName GEN2_12C CGENZ EC 111584 1928 810 USB P CD Class Nane cooks D Net Class ClassName mPCIE Figure 4 4 Mini PCI Express socket schematic example 4 10 3 Necessary layout properties Table 33 PCIe interface signal routing requirements Max frequency UI pe 5 0 200 Gbps ps 2 5 GHz half rate archi riod tecture Topology
59. age 3 max 3 6 USB VBUS USB supply voltage 3 V Power dissipation TBD Operating temperature Measured by thermal diode TBD C 3 4 Power management of the COM The Tegra R processor module has efficient solutions for the power management The power up process of the module is specified and it is necessary for the carrier board to follow these specifications so the module can power up correctly 3 4 1 Power sequence To start the power sequence of the Tegra R processor module the carrier board has to supply the 5V_SYS and 3V3_SYS If both voltage are Okay the GOOD must pulled low pull up agains 5V_SYS on the SoM The Tegra can started by pull low the nONKEY Power But ton pull up on the SoM agains 2 5 AON or by pull low WAKEUP nPOWER After a fix delay the Tegra will release the nRESET PERIPH signal this indicates that the power for the external periphery can be powered see power sequencing It is necessary that the external periphery is not powered before the nRESET PERIPH signal will be released Otherwise the Tegra R can be back driven which will produce unwanted behaviors To autoboot the SoM see section 4 1 1 It is not necessary which power 5V_SYS or 43V3 5 5 will be powered first The best is that both voltages will powered at the same time After the power sequence is complete the boot ROM passes control to the system dependent software Avionic Design
60. ble 54 USB 2 0 interface delays USBO D N 73 75 5 148 5 USBO D P 72 75 5 147 5 0581 D 67 156 8 223 8 USBI D 64 157 4 221 4 USB2 D N 43 125 9 168 9 0582 D P 43 126 1 169 1 For the USB 3 0 interface delays take a look on table 34 PCIe interface delays Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 5 Software 53 5 Software This chapter contains information about the BCT and the Bootloader 5 1 BCT The BCT is a nvidia specific format which contains initialisation data for the Tegra processor Most im portantly it includes the initial configuration for the memory controller which is required to set timings matching the connected DDR memory modules As those timings depend on chip characteristics as well as PCB layout data they differ between boards Avionic Design provides a BCT file for the Meerkat processor module that is independent of the carrier board and which can to be used for flashing the Meerkat modules The BCT files are flashed onto the processor along with the bootloader files using the nvidia tegrarcm tool Nvidia provides a set of helper utilities called tegra uboot flasher scripts which ease the process of building BCT and bootloader and flashing them onto the module BCT is a binary format which is generated using the nvidia tool called cbootimage which
61. build the bootloader you need a cross compilation toolchain for armv71 as a prerequisite If you already have a toolchain for the target you can just set the environment variable CROSS COMPILE and skip this step Otherwise you may build a toolchain using the buildroot based BSP for Meerkat from Avionic Design The BSP has the form of a buildroot external Get the BSP sources by running git clone https github com avionic design buildroot external ad git Then follow the instructions in the file buildroot external ad README to build the toolchain Then point the environment variable CROSS COMPILE to that toolchain Assuming your buildroot root directory is BR_ROOT insert absolute path here and you have built the BSP resp the BSP toolchain there using the commandline make O build meerkat rootfs toolchain as described in the buildroot external ad README then do export CROSS COMPILE S BR ROOT build meerkat rootfs host usr bin arm buildroot linux gnueabihf If you have chosen a different directory for Oz when building the BSP adapt accordingly 5 3 2 Checkout required sources and utilities 1 Enter working directory mkdir p dev tegra linux export BUILD DIR dev tegra linux cd DIR 2 Checkout tegra uboot flasher scripts from github git clone branch tk1 master https github com avionic design tegra uboot flasher scripts git 3 Checkout helper repositories git clone https github com N
62. delay 1620 ps PCB routing delays for Max trace delays and max trace delay skew parame ters Max intra pair within 1 ps PCB routing delays for pair skew Max trace delays and max trace delay skew parame ters Max inter pair pair pair 10 ps PCB routing delays for skew Max trace delays and max trace delay skew parame ters Table 29 DSI interface delays DSI_A_CLK_N 66 85 9 151 9 DSI A CLK P 66 86 0 152 0 DSI A DO N 76 76 3 152 3 DSI DO 75 76 5 151 5 DSL DI N 50 102 0 152 0 DSI A DI P 51 101 6 152 6 DSI A D2 N 75 71 5 152 5 5 75 77 5 152 5 DSI D3 N 56 97 6 153 6 DSL A 57 96 5 153 5 DSI B CLK N 68 84 9 152 9 DSI B CLK P 67 85 8 152 8 DSI B DO 67 85 9 152 9 DSI B DO P 67 85 9 152 9 DSI B DI N 47 105 7 152 7 DSI B DI P 48 104 7 152 7 Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de 34 Section 4 Interfaces of the COM 35 DSI B D2 N 74 78 3 152 3 DSI B D2 P 73 79 3 152 3 DSI B D3 N 55 97 8 152 8 DSI B D3 P 55 97 0 152 8 4 10 PCIe series processors integrate a x4 lane bridge to enable a control path from the Tegra chip to external PCIe devices Two PCIe Gen2 controllers 5 0 GT s supports up to 5 PCIe lanes two interfaces Table 30 Possible PCIe Configurations Jetson TKI 1 2 3 4 We use
63. e Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 23 Max intra pair within pair skew 1 ps Max inter pair pair pair skew 150 ps Table 12 eDP LVDS interface delays eDPO N LVDS2 TXON 30 137 2 167 2 eDPO P LVDS2 TXOP 30 137 2 167 2 N LVDSI1 44 134 5 178 5 eDP1_P LVDS1_TXOP 45 134 5 179 5 eDP2 N LVDSO TXON 50 134 8 184 8 eDP2 P LVDSO TXOP 51 134 8 185 8 eDP3_N LVDS4_TXON 38 134 9 172 9 eDP3 P LVDS4 TXOP 38 134 9 172 9 LVDS3 TXON 46 134 5 180 5 LVDS3 TXOP 47 134 5 181 5 4 4 GPIO The Tegra processor GPIO controller provides the tools for configuring each MPIO for use as software controlled GPIO Each GPIO is individually configurable as Output Input Interrupt sources with level edge controls The GPIO controller is divided into 8 banks Each bank handles the GPIO functionality for up to 32 MPIOs Within a bank GPIOs are arranged as four ports of 8 bits each The ports are labeled consecutively from A through Z and the AA through FF Ports A through D are in bank 0 Ports E through H are in bank 1 There 183 available GPIOs but not all GPIOs are routed to the connectors See the list below which GPIOs are available 4 4 1 Signals Table 13
64. eDPO P LVDSO TXD2P AG6 LVDSO TXD2P avdd 1 450 io 1 05V X1 38 SDMMCI nIRQ GPIO3 PCC 05 CLK2 REQ 14 vddio sdmmcl 2 8V Isr noud 9 uonoog LS op ugTsop oruorA OJU 0 1 81 88 0 0 67 410 281 88 L Awun S1nquieH 6 cc 01 durexoserA usIsaq oruortAV X1 39 LVDSO_TXD2N LVDSO TXD2N avdd lvdsO 1 05V X1 40 SDMMCI DAT2 GPIO3 PY 05 SDMMCI DAT2 11 SDMMCI DAT2 vddio sd mmc1 pu 1 8V X1 41 Ground X1 42 SDMMCI DATO GPIO3 PY 07 SDMMCI DATO L2 SDMMCI DATO vddio sd mmc1 pu 1 8V X1 43 eDPI 50 TXDIP AG4 LVDSO TXDIP avdd 1 450 io 1 05V X1 44 SDMMCI DATI GPIO3 PY 06 SDMMCI DATI L3 SDMMCI DATI vddio sd mmc1 pu 1 8V X1 45 eDPI LVDSO TXDIN AG3 LVDSO TXDIN avdd lvdsO 1 05V X1 46 SDMMCI nWP GPIO3 PV 03 SDMMCI WP N L5 SDMMCI WP vddio sdmmcl1 pu 1 8V 1 47 Ground 1 48 SDMMCI DAT3 GPIO3 PY 04 SDMMCI DAT3 J8 SDMMCI DAT3 vddio sd mmc1 pu 1 8V X1 49 LVDS TXD3 N LVDSO_TXD3N AGI LVDSO TXD3N avdd lvdsO 1 05V X1 50 SDMMCI GPIO3 PZ 00 SDMMCI CLK L7 SDMMCI vddio sd mmc1 pd 1 8V 51 LVDS TXD3 P 50 TXD3P AG2 LVDSO TXD3P avdd lvdsO io 1 05V 1 52 SDMMCI CMD GPIO3 PZ 01 SDMMC1_CMD L8 SDMMCI
65. ed to be controlled by software or it can be generated automatically by the hardware on packet boundaries Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 45 e Receive compare mode controller listens for a specified pattern on the incoming data before receiving the data in the FIFO e Simultaneous receive and transmit supported e Supports Master and Slave modes of operation 4 14 1 Signals Table 43 SPI1A signals 1 8V level 5 MISO X5 45 Master In Slave Out 5 MOSI X5 51 Master Out Slave In 5 nCSO X5 47 Chip Select 5 X5 49 Serial Clock 5 nIRQ X5 43 Interrupt request Table 44 SPI2D signals 1 8V level SPI2D_MISO X5 7 Master In Slave Out SPI2D MOSI X5 3 Master Out Slave In SPI2D nCSO X5 1 Chip Select SPI2D_SCK X5 5 Serial Clock SPI2D nIRQ X5 36 Interrupt request _ Table 45 SPI3E signals 1 8V level SPI2D MISO X5 19 Master In Slave Out SPI2D MOSI X5 13 Master Out Slave In SPI2D nCS1 5 27 Chip Select SPI2D SCK X5 23 Serial Clock Table 46 SPIAC signals 1 8V level SPI4_MISO X5 57 Master In Slave Out SPI4_MOSI X5 55 Master Out Slave In SPI
66. g USB Battery Charging Specification version 1 0 Including Data Contract Detect protocol Modes Host and Device Speeds low Full and High e Enhanced Host Controller Interface Specification for Universal Serial Bus revision 1 0 USB 3 0 controller The USB 3 0 controller XUSB USB 3 0 ports only operate in USB 3 0 Super Speed SS mode USB 3 0 ports share one Super Speed Bus Instance 5Gb s bandwidth is distributed across these ports The XUSB controller supports e xHCI programming model for scheduling transactions and interface management as a host that na tively support USB 3 0 USB 2 0 and USB 1 1 transactions through USB 3 0 and USB 2 0 interfaces e Remote wakeup wake on connect wake on disconnect and wake on overcurrent in all Tegra power states including deep sleep mode USB 2 0 controller USB 2 0 controllers support e USB hast controller registers and data structures are compliant to Intel specification The max packet size supported on any endpoint is 1024 bytes in high speed mode for both device and host modes e USB legacy USB 1 1 Full and Low speed devices without a companion USB 1 1 host controller or host controller driver software using EHCI standard data structures USB 2 0 Controller 1 Supports both USB 2 0 device and USB 2 0 host operations USB recovery is supported only with USB 2 0 0580 CLIENT USB controller 1 only connects to USB 2 0 port 0 which is the
67. ght bits an optional parity bit and one or two stop bits Support for modem control inputs DMA capability for both TX and RX 8 bit x 36 deep TX FIFO 11 bit x 36 deep RX FIFO 3 bits of 11 bits per entry will log the RX errors in FIFO mode break framing and parity errors as bits 10 9 8 of fifo entry Auto sense baud detection Timeout interrupts to indicate if the incoming stream stopped Priority interrupts mechanism Flow control support on RTS and CTS Internal loopback SIR encoding decoding 3 16 or 4 16 baud pulse widths to transmit bit zero Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 47 4 15 1 Signals Table 47 UARTI signals 1 8V level UARTI RXD X5 9 UART receive I UARTI TXD X5 11 UART transmit Table 48 UART2 signals 1 8V level low active low active UART2 nCTS X4 34 UART Clear to send UART2_nRTS X4 32 UART Request to send UART2_RXD X4 28 UART receive UART2_TXD X4 30 UART transmit Table 49 UART3 signals 1 8V level low active low active UART3 nCTS X4 44 UART Clear to send UART3_nRTS X4 42 UART Request to send UART3 RXD X4 38 UART receive UART3 TXD X4 40 UART transmit Table 50 UART4 DEBUG signals 1 8V level
68. imedia platform for embedded avionic and industrial operation It has a very high graphic performance but it consumes little power see Section 2 6 The hardware of the Processor Module has a NVIDIA Tegra SoC as its core component The main properties of the CPU are e NVIDIA Tegra R quad core ARM Cortex A15 r3 with NVIDIA 4 Plus 1 ARM NEON 11 cache 32 KB instruction cache for each core 32 KB data cache for each core L2 cache 2 MB shared by all cores Operation frequency up to 2 2 GHz The properties of the COM memory are e 2GB DDR3L 64 Bit 16 GB eMMC eMMCS5 0 The Tegra Processor Module has a larger number of GPIOs and interfaces e 2 GB DDR3 eMMC 16 GB 5 0 e up to 2 4 CSI e up to 2 x4 MIPI DSI e Ix eDP e up to 5 PCIe lanes Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 3 Properties of the COM 2x standard USB 2 0 hosts 1x HSIC shared with USB1 1x standard USB 2 0 client configurable as host up to 2x USB 3 0 hosts 1x standard SATA 1x standard SDMMC 4 bit 1x standard SDMMC SDIO 4 bit 2x DAP I2S PCM 1x Debug UART 3x UART 2x standard I2C 1x 3 3 V and 1x 1 8 V 4x SPI 8x 1 8V GPIOs 22x 3 3V GPIOs 1x JTAG 1x S PDIF In Out 1x standard HDMI 1 4b 11 The following figure wil
69. l give you overview of the Tegra Processor Module and its components f art UP th yz Lnd m CD575M A1 Figure 3 1 Top view of the Tegra processor module n Hu 10 arm E wa Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de FETS 7 Section Properties of the COM 12 Explanation to 1 DDR3L 2 PMU 3 Temperature sensor 4 eMMC 5 NVIDIA Tegra amp SoC 3 1 2 Function block diagram Below you can find a function block diagram of the processor module SV max 15 3V3 1A PWRsource 1 840 2 5 49 a 2 Optional Boot R 1 WAKEUP LD Audio 2x I2S DA Figure 3 2 Function block diagram of the COM 3 2 Mechanical properties of the COM In this section you can find information about the mechanical properties of the Tegra R processor mod ule The diagram below shows the general layout of the processor board Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 3 13 Properties of the COM 70mm 22mm 1 mu 2 Figure 3 3 Mechanical properties of the top view NT
70. level Low speed signaling for handshaking Low speed signaling for data used for escape command entry only 20 Mbps 4 8 Signals Table 24 MIPI CSI signals CAM_nRST X4 56 CAM reset O X1 60 master clock CAMI PWDN X4 54 power down O O O I I 2 X1 54 CAM2 master clock CAM2_PWDN X4 58 power down CSI A X241 CSI clock negative CSI A CLK P X2 39 CSIclock positive CSI DO X2 27 CSI data negative I O CSI A DO P X2 29 CSI data positive I O CSI A DI X2 35 CSI data negative I O CSI A DI P X2 33 CSI data positive I O CSI B DO N 2 21 CSI data negative I O CSI B DO P X2 23 CSI data positive I O CSI B D1 X2 17 CSI data negative I O CSI B DI P X2 15 CSI data positive I O CSI E X2 11 CSIclock negative I CSI E P X29 CSI clock positive I CSI E DO N X2 3 CSI data negative I O CSI E DO P X2 5 CSI data positive I O Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 4 8 2 Example schematic No special schematics are required 4 8 3 Necessary layout properties Table 25 CSI interface signal routing requirements
71. lex mode Features Basic 125 modes to be supported 125 RJM LJM and DSP in both Master and Slave modes e PCM mode with short one bit clock wide and long fsync two bit clocks wide in both master and slave modes e NW mode with independent slot selection for both TX and RX e TDM mode with flexibility in number of slots and slot s selection Capability to drive out a High z outside the prescribed slot for transmission Flow control for the external input output stream Support for u Law and A Law compression decompression Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de 4 21 Signals DAP MCLKI X5 42 Section 4 Interfaces of the COM Table 6 DAP2 signals DAP master clock 1 External Peripheral 1 Clock Connect to MCLK pin of the audio device if reference clock is required DAP2 DIN X5 46 Data In DAP pins support I2S PCM audio Interface can be master or slave DAP2 DOUT X5 48 Data Out DAP pins support I2S PCM audio Interface can be master or slave DAP2 FS X5 44 Frame Sync Word Select DAP pins support I2S PCM audio Interface can be master or slave DAP2 SCLK X5 50 Serial Clock Bit Clock DAP pins support I2S PCM audio Interface can be master or slave CLK3 OUT X4 50 Table 7 signals Clock 3 out External
72. mburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 infoG avionic design de www avionic design de Section 4 Interfaces of the COM 44 e Flexible clock divisor for use to generate different spdifout data rate e SPDIFOUT TX 16 word data FIFO for storage of outgoing audio data 4 word user FIFO for storage of outgoing user data 6 word page buffer for storage of outgoing channel status 4 13 1 Signals Table 42 S PDIF signals SPDIF IN X5 58 Data In SDPIF OUT X5 56 Data Out 4 13 2 Example schematic No special schematics are required 4 13 3 Necessary layout properties no necessary layout properties 414 SPI The Serial Peripheral Interface SPI controller supports master slave operations up to 50 MHz 50 Mbps maximal data rate It allows a duplex synchronous serial communication between the controller and external peripheral devices It consists of 4 signals nCS chip select SCK clock MOSI master data out and Slave data in and MISO master data in and Slave data out The data 15 transferred on MOSI or MISO based on the data transfer direction on every SCK edge The receiver always receives the data on the other edge of SCK Features e Independent RX FIFO and RX FIFO e Software controlled bit length supports packet sizes of 1 to 32 bits e Packed mode support for bit length of 7 8 bit packet size and 15 16 bit packet size e 5 can be select
73. ments Data rate UI period 5 0 200 Gbps ps Max number of loads 1 load Termination 90 differential Q On die termination TX amp RX Reference plane GND Breakout region Max length 7 62 mm 4x dielectric spacing pre ferred Trace impedance dielectric 4 Microstrip Stripline 5x 3x To Ref plane amp capacitor pad 5x 4x To unrelated high speed signals Max trace length 152 mm Include Package amp PCB routing delays for max trace delays and max trace delay skew parameters Max PCB Via distance from 7 62 mm BGA ball Max intra pair skew RX TX_N 1 0 15 ps mm PCB routing delays for to RX TX_P Max trace delays and max trace delay skew parame ters Max intra pair matching be 1 0 15 ps mm Recommended trace tween subsequent discontinu length matching to 1 ities ps before Vias or any discontinuity to min imize common mode conversion Via placement GND via dis Diff via pitch Recommended trace tance length matching to ps before Vias or any discontinuity to min imize common mode conversion Max number of vias 4 Via stub length lt 0 4 mm AC coupling capacitor 100 nF Discrete 0402 AC coupling capacitor location lt 8 53 mm ps Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM Ta
74. n x ie Case HOMEL TADO N T sHieLD ET ALE FB9 Dt TOMS CLK 5 a pipes Scie HDMI DDC SCL_FBIO_gaggtit2 o Clearance Constraint Clearance 0 1 0v osi HDMI DDC SDA BI MIDDC SDA FE TE PCB Rule 3 paa fo g 1 HEC Datat 4n HDMI TYPA RUE ro 0 sov Hmi mm H MNO sd T viso IN rH INANC NNC H GND INKNC TVS Section 4 Interfaces of the COM 4 6 Max Trunk delay 16 254 1500 Microstrip mm ps Include package amp PCB MHz Stripline routing delays for Max trace delays and max trace delay skew parameters Max distance from ESD 12 7 87 mm ps to connector Max distance from signal 6 35 37 5 mm ps Keep stub connecting line to ESD pad ESD to signal trace very short or overlay pad on signal trace Max intra pair within 1 ps pair skew Max inter pair pair pair 150 ps skew Table 17 HDMI interface delays HDMI TXC N 29 182 2 211 2 HDMI TXC P 29 182 2 211 2 HDMI TXD0 29 182 8 211 8 HDMI P 29 182 8 211 8 HDMI TXD1 38 182 4 220 4 HDMI TXDI 39 182 4 221 4 H
75. negative Shared with PCIe USB3 RX0 P X3 7 USB 3 0 receive data lane I positive Shared with PCle 0583 X3 1 USB 3 0 transmit data O lane negative Shared with PCIe USB3 3 3 USB 3 0 transmit data O lane positive Shared with PCIe USB3 X3 19 USB 3 0 receive data lane I negative Shared with PCIe PEX USB3 X3 21 USB 3 0 receive datalane I positive Shared with PCIe PEX USB3 X3 13 USB 3 0 transmit data O lane negative Shared with PCIe PEX USB3 P X3 15 USB 3 0 transmit data O lane positive Shared with PCIe Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 50 4 16 2 Example schematic The following figure shows a schematic example of a OTG capable USB Client port USB Client 5V EXT 024 bl 3V3 EXT 3 9 ClassName POWER 1C38 NetClass 2 R211 2 6 10k 2 a l USB VBUS 5 Net Class 3 3 R213 ClassName POWER FETS FDN337N G USB CLIENT ID 5 D FETII GND G FDN337N 5 5V EXT di GND Gup C2 C213 100 16V L 100 50 1039 vo H R219 CAP 2
76. nge History 2 Mechanical properties ofthe COM 14 Absolute maximum operation conditions 14 Recommended operation conditions 15 Meerkat special 16 DAP2 Signals ee GE ae ums 19 DAPA signals 4 2 ha 43 92 bi XU 19 DAP DS interface signal routing requirements 20 DAP I2S intertac delays koe oo RR Ry 21 embedded DisplayPort eDP signals 21 eDP HBR2 main link signal routing requirements 22 eDP LVDS interface delays 23 1 8V GPIOs signal 4 esee o Romo Rue d UR RU RR 23 3 3V GPIOssignals 24 HDMI signals 2 020002 24 so Rom o oe ORO RS 25 HDMI interface signal routing requirements 26 HDMI interface delays 27 bus number 27 PCOGENI 1V8 signals 28 PC 2 3V3 44 amp a a 28 1 8 Dunne eumd a es 28 HDMI DDC
77. nst 1 8 VDDIO 10k and indicate if the Tegra is powered The signal should be used to unload all device which are connected to the SoM otherwise reverse supply can happen e VBAT_BKUP This pin can be used for a RTC battery but it can also be opened The RTC backup battery can be loaded by the internal battery charger of the PMU to 2 5 V or to 3 0 V In the power off mode the current should below 10 uA supplier specification e nONKEY This input can be used to start the PMU The signal is low active and pulled on the SoM against 2V5_AON_RTC 220k e nWAKEUP_POWER This signal can also be used to start the PMU The signal is low active and is pulled on the SoM with 100k against 2V5_AON_RTC Autoboot if no Power Off Mode will be required this signal can be connected to ground In this case the PMU will be reseted instead of powered off when a long press event is detected at the nONKEY signal Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 18 otherwise a reset chip should be used to generate the power on event In this case the reset chip must generate a low level until the nPOWERGOOD is high plus minimum 210 ms WAKEUP LID This signal is high active and can be used to leave the suspend mode when the input is configured The suspend mode can also be leaved by the nWAKEUP
78. primary USB 2 0 port on the Tegra devices This controller shares the same USB 2 0 port 0 pins with the XUSB controller USB 2 0 Controller 2 Can be configured to use regular USB 2 0 port 1 USB1 or can be configured to use an HSIC interfaces that allows connection of an on board peripheral supporting an HSIC interface to the Tegra processor This controller shares the same USB 2 0 port 1 pins with the XUSB controller Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 infoG avionic design de www avionic design de Section 4 Interfaces of the COM 49 USB 2 0 Controller 3 Can be configured to use regular USB 2 0 port 2 USB2 This controller shares the same USB 2 0 port 2 pins with the XUSB controller 4 16 1 Signals Table 51 USB signals USBO D N X2 53 05 0 OTG data USBO D P X2 55 05 0 data USBO ID X2 57 USBO OTG ID I USBO VBUS X2 59 USBO OTG VBUS P USB VBUS nOC X3 36 USBO enable overcurrent I requires pull up against 3 3V USBI D X3 28 USBI data USBI D P X3 30 USBI data USB VBUS nOC X3 34 USB1 enable overcurrent I requires pull up against 3 3V USB2 D N X3 18 USB2 data USB2 DP X3 16 USB2 data USB VBUS EN2 nOC X3 54 0582 enable overcurrent I requires pull up against 3 3V USB3 X3 9 USB 3 0 receive data lane I
79. sb 3 3V X2 54 Ground X2 55 USBODP USBO DP AJ20 USBO DP avdd usb 3 3V X2 56 5 A DI DSLA DI N ADI4 DSL A DI avdd dsi csi 1 2V X2 57 USBO ID USBO ID AK20 USBO ID avdd usb 3 3V X2 58 DSLA DI P DSL ADI P AEI4 DSLA DI P avdd dsi csi 127 X2 59 USBO VBUS USBO VBUS AL20 0580 VBUS avdd usb 3 3V X2 60 Ground X3 USB3 USB3 TXON AJ21 USB3 TXON dvddio pex 1 05V X32 Ground X3 3 0583 0583 AH21 0583 dvddio pex 1 05V X3 SATA 10 TX P SATA 10 TXP AL27 SATA 10 TXP vddio sata 1 05V X3 5 Ground X3 6 SATA 10 TX SATA 10 TXN AK27 SATA 10 TXN vddio sata 1 05V X3 7 USB3_RX0_P 0583 AK21 USB3 dvddio pex 1 05V X3 8 Ground Isr noud 9 uonoog 19 op ugTsop oruorA OJU 0 1 81 88 0 0 67 410 281 88 L Awun S1nquieH 6 cc 01 durexoserA usIsaq oruortAV USB3 RXO N USB3 RXON USB3 RXON dvddio pex 1 05V X3 10 SATA 10 SATA 10 RXN AH27 SATA 10 RXN vddio sata 1 05V X3 11 Ground 3 12 SATA 10 P SATA 10 AJ27 SATA 10 RXP vddio_sata 1 05V X3 13 USB3 PEX USB3 TXIN AG21 PEX USB3 TXIN dvddio pex 1 05V X3 14 Ground X3 15 PEX USB3 TXI P PEX USB3 TXIP AF21 PEX USB3 TXIP dvddio pex
80. terface Not supported External connector eS ATA USM Internal LIF SATA 4 11 1 Signals Table 35 SATA signals table sata SATA LO X3 10 receive data lane negative SATA LO RX P X3 12 receive data lane positive SATA LO TX N X3 6 transmit data lane negative SATA LO TX P 3 4 transmit data lane positive SATA LED X5 41 SATA status LED SATA_PWR_EN X5 39 SATA power enable oO ocoo 4 11 2 Example schematic No special schematics are required Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 4 11 3 Necessary layout properties Table 36 SATA interface signal routing requirements Max frequency UI pe 3 0 333 3 Gbps ps 1 5 GHz riod Topology Point to Point Unidirectional differen tial Configuration Device or 1 load ganization Max loading per pin 0 5 pF Termination 100 Q On die termination Reference plane GND Breakout region Width 4 mils line spacing Trace impedance 90 diff pair 55 single Q ended Pair to Pair Trace Spacing 3x stripline 3x mi dielectric crostrip Max trace length delay 203 1330 mm ps Include Package amp PCB routing delays for max trace delays and max trace delay skew parameters Max intra pair
81. uorA OJU 0 1 81 88 0 0 67 410 281 88 L Awun S1nquieH 6 cc 01 durexoserA usarse oruotAV 6 Pinout List Tn this section you will find a list of pinouts for all the connectors of the Tegra R K1 processor module towards a carrier board 6 1 Connector overview 6 2 Connector pinout and pin muxing HDMI TXC HDMI TXCN AFS HDMI TXCN avdd hdmi 3 3V X1 2 HDMI_DDC_SDA GPIO3_PV 05 DDC_SDA AC8 I2C4 DAT vddio hv 3 3V 2 3 HDMI TXCP AF6 TXCP avdd hdmi 3 3V X1 4 HDMI_DDC_SCL GPIO3_PV 04 DDC_SCL 7 2 4 vddio hv 3 3V 2 5 Ground 6 HDMI CEC GPIO3 PEE 03 HDMI CEC AD7 CEC vddio_hv 3 3V 2 7 HDMI TXDO HDMI TXDON ADS HDMI TXDON avdd hdmi 3 3V 8 HDMI INT GPIO3 07 HDMI INT AC3 vddio_hv 3 3V pd X1 9 HDMI_TXD0_P HDMI AD6 HDMI_TXDOP avdd_hdmi 3 3V 10 eDP HPD GPIO3_PFF 00 DP_HPD AC2 DP_HPD vddio_hv 3 3V 2 X1 11 Ground X1 12 Ground X1 13 HDMI TXD1 HDMI TXDIN AD4 HDMI TXDIN avdd hdmi 3 3V X1 14 SDMMC3_DAT3 GPIO3 PB 04 SDMMC3 DAT3 GI SDMMC3 DAT3 vddio_sdmmc3 pu 1 8V 3 3V 15 HDMI TXDI HDMI TXDIP AD3 HDMI TXDIP avdd hdmi 3 3V jsr inouid 9 uonoog 96 op ugTsop oruorA OJU 0 1 81 88 0 0 67 410 281 88 L
82. will read about the production parameters and the operating conditions of Tegra B processor module so you will be able to operate it safely This manual will enable you to develop a carrier that obeys the COM parameters This document includes an overview of the Tegra processor module its main components and the pinout of the board connectors You will also get information about the power management of the Tegra R processor module You will read about the interfaces of the Tegra processor module and the properties of those interfaces 2 2 Designated use of the COM Tegra processor module is a multimedia platform for embedded avionic and industrial operation Its core component is the NVIDIA Tegra processor The COM supports various interfaces like DSI CSI eDP USB3 0 SATA GEN2 and HDMI Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section Properties of the COM 10 3 Properties of the COM This chapter will give you information about the different properties of the Tegra R processor module as well as its compliance requirements and operating parameters 3 1 Structure the COM In this section you will receive an overview of the Tegra amp processor module and its main components 3 11 General overview The Tegra processor module is a mult
83. within 1 ps PCB routing delays for pair skew Max trace delays and max trace delay skew parame ters Table 37 PCle interface delays SATA_LO_RX_N 44 65 7 109 7 SATA LO RX P 44 65 7 109 7 SATA LO TX N 50 61 9 111 9 SATA LO TX P 49 62 9 111 9 40 4 12 SD MMC SDIO The Tegra has four SD MMC controllers The Meerkat uses SDMMC3 for an SD Card interface and SDMMC4 to interface to an eMMC device primary boot option SDMMC1 is available to use as SDIO SDMMC72 is not routed on the Meerkat SoM For the SD Card SDIO interfaces SDMMC3 and SDMMC1 support up to UHS 1 For eMMC SD supports up to HS200 Avionic Design GmbH Wragekamp 10 22397 Hamburg Germany T 49 0 40 88 187 0 F 49 0 40 88 187 150 info avionic design de www avionic design de Section 4 Interfaces of the COM 4 12 1 Signals Table 38 SDMMCI SDIO signals SDMMCI EN X4 48 SDMMCI power enable SDMMCI CLK 1 50 SDMMC SDIO clock SDMMCI CMD X1 52 SDMMC SDIO command T O SDMMCI DATO X1 42 SDMMC SDIO data I O SDMMCI DATI X1 44 SDMMC SDIO data I O SDMMC1_DAT2 X1 40 SDMMC SDIO data I O SDMMC1_DAT3 X1 48 SDMMC SDIO data I O SDMMCI nIRQ X1 38 SDMMC SDIO interrupt request low active SDMMC1_nWP X1 46 SDMMC SDIO write protect O low active Table 39 SDMMC3 signals

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