1785-6.5.9-RN1, PLC-5/VME VMEbus Programmable Controllers
Contents
1. e Jamaica e Japan e Jordan e Korea e Kuwait e Lebanon e Malaysia e Mexico e Netherlands e New Zealand e Norway e Pakistan e Peru e Philippines e Poland e Portugal e Puerto Rico e Qatar e Romania e Russia CIS e Saudi Arabia e Singapore e Slovakia e Slovenia e South Africa Republic e Spain e Sweden e Switzerland e Taiwan Thailand e Turkey e United Arab Emirates e United Kingdom e United States e Uruguay Venezuela e Yugoslavia Allen Bradley Headquarters 1201 South Second Street Milwaukee WI 53204 USA Tel 1 414 382 2000 Fax 1 414 382 4444 Publication 1785 6 5 9 RN1 December 1996 PN955127 63 Supersedes Publication 1785 6 5 9 RN1 May 1995 Copyright 1996 Allen Bradley Company Inc Printed in USA2. Introduction Release Note PLC 5 VME VMEbus Programmable Controllers Cat No 1785 V30B V40B V40L and V80B Use these release notes with the following processors Processor Series Revision PLC 5 V30 C K PLC 5 V40 PLC 5 V40L B PLC 5 V80 These release notes supersede publication 1785 6 5 9 RN1 May 1995 For information about See page Using VME interrupts Making VME self references in post tests Avoiding multiple watchdog faults Inserting ladder rungs at the 56K word limit Recovering from possible memory alteration Examining fault codes Avoiding run time errors when executing FBC and DDT instructions oa Sy gt A AI CO Cy Cy nro Processor specifications Publication 1785 6 5 9 RN1 December 1996 2 PLC 5 VME VMEbus Programmable Controllers Using VME Interrupts If you e set the NOCV bit to 1 AND e use the VME interrupt receive bits in the VME status file then you should implement ladder logic similar to the following example to avoid missing interrupts interupt received bit B3 0 0 xic OTL Me may need to ae the value B3 0 0 TON of the TON timer for each unique r 4 be application 1xic inc Base or Acc 0 interupt received bit interupt received bit m xci T4 0 DN OTU Clear Status ID Set Update Status File Bit RES T4 0 OTU B3 0 0 XIC Clear Sta
3. LED lights PLC 5 V30 5 V40 5 V80 60 C 180 days 360 days 6 days 801A 25 C 290 days 580 days 9 days 50uA The battery indicator BATT warns you when the battery is low These durations are based on the battery supplying the only power to the processor power to the chassis is off once the LED first lights Publication 1785 6 5 9 RN1 December 1996 PLC 5 VME VMEbus Programmable Controllers PLC and PLC 5 PLC 5 VME PLC 5 V30 PLC 5 V40 PLC 5 V40L and PLC 5 V80 DH Data Highway Plus SLC 500 are trademarks of Allen Bradley Company Inc oN Rockwell Automation Allen Bradley a Rockwell Automation Business has been helping its customers improve SS productivity and quality for more than 90 years We design manufacture and support a broad Allen Bradley range of automation products worldwide They include logic processors power and motion control devices operator interfaces sensors and a variety of software Rockwell is one of the world s leading technology companies i Worldwide representation PA E x Argentina e Australia e Austria e Bahrain e Belgium e Brazil e Bulgaria e Canada e Chile e China PRC e Colombia e Costa Rica e Croatia e Cyprus e Czech Republic e Denmark e Ecuador e Egypt e El Salvador e Finland e France e Germany e Greece e Guatemala e Honduras e Hong Kong Hungary Iceland e India e Indonesia e Ireland Israel e Italy
4. function charts SFCs and the jump to subroutine JSR instruction Publication 1785 6 5 9 RN1 December 1996 Recovering from Possible Memory Alteration Examining Fault Codes Avoiding Run time Errors when Executing FBC and DDT Instructions Publication 1785 6 5 9 RN1 December 1996 PLC 5 VME VMEbus Programmable Controllers If you cannot segment your program file save the file often while editing it If you encounter the error Memory Unavailable for Attempted Operation while performing online edits then use your programming software package to clear memory and restore the last saved version of your program ATTENTION Processor memory could become altered if you lose power while performing any of the following online editing operations creating a rung assembling online edits creating and or deleting data table space If you lose power while editing your program use your programming software package to clear potentially altered memory and restore the last saved version of your program Fault routines execute when a PLC 5 processor encounters a run time error major fault during program execution For information about fault codes see e PLC 5 VME VMEbus Programmable Controllers User Manual publication 1785 6 5 9 e Enhanced and Ethernet PLC 5 Programmable Controllers User Manual publication 1785 6 5 12 To avoid encountering a possible run time error when executing FBC and DDT instruction
5. s add a ladder rung that clears S 24 indexed addressing offset immediately before a FBC or DDT instruction PLC 5 VME VMEbus Programmable Controllers 5 PLC 5 VME PLC 5 V30 PLC 5 V40 PLC 5 V40L PLC 5 V80 Processor Specifications 1785 V30B 1785 V40B 1785 V40L 1785 V80B Maximum User Memory Words 32 K 48KO 100 K Maximum Any Mix 896 1920 2944 Total I O Complementary 896 in and 896 out 1920 in and 1920 out 2944 in and 2944 out Maximum Analog I O 896 1920 2944 Program Scan Time 2 d e cn 0 5 ms extended local IO Scan Time a tren 3 ms per rack 230 kbps 57 6 kbps Remote I O Transmission Rate 115 2 kbps 230 kbps Maximum Number of MCPs 16 Number of Data Highway Plus DH D 4 9 4 or Remote I O Ports Adapter or Scanner Number of Extended Local I O Ports N A N A 1 N A Maximum Number of I O Racks 7 15 23 Maximum Number Extended Local N A N A 16 N A of I O Chassis Remote 28 60 92 Number of RS 232 Ports 1 Backplane Maximum 3 0A 3 3 A 3 5A 3 3A Current Load Typical 2 4 A 2 7 A 29A 27A Weight 0 56 kg 1 25 Ibs 0 67 kg 1 5 lbs The PLC 5 V40 5 V40L and 5 V80 processors have a limit of 32K words per data table file PLC 5 VME Battery Specifications 1770 WV A Worst case Battery Life Estimates Battery used in this processor Atthis temperature Power off 100 Power off50 Battery Duration after the
6. s of how you set SW2 positions 1 3 If you encounter a hardware error or watchdog major fault it may be because multiple watchdog faults occurred while the processor was busy servicing a ladder related major fault The hardware error occurs when the fault queue which stores a maximum of six faults becomes full and cannot store the next fault When you encounter a hardware error or multiple watchdog faults take the following steps before calling a service representative If you encountera Then watchdog error Extend the watchdog timer so that the real run time error is not masked and a fault bit Check your major fault bits ignore the watchdog faults and use any remaining fault bits to help indicate the source of the processor fault for more information see the Enhanced and Ethernet PLC 5 Programmable Controllers User Manual publication 1785 6 5 12 hardware error 1 Power down then power up the processor 2 Reload the program 3 Set the watchdog timer to a value 10 x current setting 4 Runthe program again Performing run time or program mode editing of ladder files that approach the maximum program file size of 57 344 words could e prevent the rung from being inserted cause suspension of the operation by 6200 Series PLC 5 Programming Software release 4 3 and later To avoid this problem segment your program file by using modular programming design practices such as main control programs MCPs sequential
7. tus ID Set Update Status File Bit RES T4 0 OTU B3 0 0 MSG Programmable Controllers User Manual publication 1785 6 5 9 Publication 1785 6 5 9 RN1 December 1996 CSF For a complete explanation of using VME interrupts see page 4 5 of the PLC 5 VME MG10 0 Making VME Self references in POST Tests Avoiding Multiple Watchdog Faults If you continue to encounter the hardware error call your Ss Allen Bradley representative Inserting Ladder Rungs at the 56K Word Limit This consideration applies to PLC 5 V80 processors when you are editing a program file that approaches the maximum file limit of 57 344 words PLC 5 VME VMEbus Programmable Controllers 3 SW2 position 7 now controls whether the PLC 5 processor makes a VME self reference in its POST test If you set SW2 position 7 to OFF up position then the PLC 5 VME processor will make self references as it did prior to the series D B and C K releases If you set SW2 position 7 to ON down position then the POST test will skip all VME self references causing the following effects e The PLC 5 processor cannot test its bus master hardware e The PLC 5 processor cannot determine its own unique logical address and assumes that its ULA is F0H regardless of how you set SW2 positions 1 3 e The VME status file ULA field word 1 bits 13 15 will always contain 000 regardles
Download Pdf Manuals
Related Search