Home

User Manual

Contents

1. HY PE PO POT PS CO PST POT CO CO CO CO GO CO CO BH HB HY co CO SH AB HY Figure 2 2 DN5000k10 Stuffing Option Comparison 2 4 The DINI Group Flip Flops and LUTs LAB Carry In addnsub Carry In1 Carry InO data1 data2 data3 data4 labelr1 Chip Wide Reset Clock amp Clock Enable Select labclk1 labclk2 labclkena1 labclkena2 DN5000k10 User s Manual DN5000k10 Features Overview and General Description Figure 2 3 shows what Altera calls a Logic Element or LE Each LE contains a flip flop and a 4x1 look up table LUT LEs are arranged in groups of 10 called Logic Array Blocks LAB The EP1S80 is an array of LABs with 91 rows and 101 columns but there are 9 RAM blocks which appear in place of 13 row by 11 column sections of the grid leaving a total of 7904 LABs and 19040 LEs Other blocks such as DSP multiplier blocks and smaller RAM are arranged in entire columns squeezed between two LAB columns Each LUT can implement any Boolean function of four inputs An LUT can also be configured as a two input adder subtractor with a carry chain coming from the adjacent LE and going to the next LE In order to reduce delays caused by long carry chains each set of 5 LEs computes two adder results simultaneously then uses the carry result from the previous set of 5 to select which result i
2. lt DATA 30 y lt _ SDRAM DATA 31 4 SDRAM DATA 32 4 SDRAM DATA 33 4 M SDRAM DATA 34 4 SDRAM DATA 85 4 SDRAM DATA 86 gt lt P SDRAM DATA 37 gt gt 4 50 DATA 38 lt 0 DATA 39 lt Vn c SDRAM DATA 40 o 4 spRAN paTa4 gt Nn P Q lt SDRAM DATA 42 gt lt lt SDRAM DATA 43 i SDRAM DATA 44 9 DATA 45
3. 0 1 CSN O0 n CSN 1 lt M CSN 2 CSN 3 0 BA 1 lt lt CASN lt RASN 0 0 lt ADDI lt ADD 2 lt p ADD 3 lt lt ADD 4 lt ADD 5 lt ADD 6 lt lt ADD 7 lt n ADDI 8 lt _ addy lt ADD 10 _ ADD 11 lt a ADD 12 lt ADD 13 0 DQNB 1 lt 2 DQNBI 3 4 5 DOQNBI 6 DQNBI 7 scL 4 SDA lt SA 0 lt R SA 1 lt IY SAI 2 R263 spram CKE 0 R50 SDRAM CKE 1 gt R42 SDRAM CSN 0 R37 SDRAM CSN 1 R266 SDRAM CSN 2 R39 SDRAM CSN 3 gt R270 SDRAM BAD R264 SDRAM BAH R260 SDRAM R262 SDRAM_CASN R268 SDRAM_RASN soram ADD 0 gt R49 SDRAM ADD 1 R46 SDRAM ADD 2 R47 SDRAM ADD 3 R45 SDRAM_ADD 4 gt R271 SDRAM_ADD 5 gt R43 SDRAM ADD 6 R44 SDRAM ADD 7 R41 SDRAM ADD 8 R272 SDRAM_ADD 9 R38 AAA sbRAM ADD 10
4. 0 29 lt AD 30 4 0131 lt 0 32 lt AD 39 AD 40 aom D lt 0 42 lt AD 43 gt AD 44 AD 45 lt AD 46 AD 47 AD 48 AD 49 lt AD 50 AD 51 lt 0 52 AD 53 _ gt lt 0 54 lt AD 55 lt AD 56 AD 57 lt AD 58 AD 59 c AD 60 AD 61 AD 62 _ gt AD 63 gt AD 64 _ gt AD 65 lt 0166 gt lt 0 67 AD 68 y AD 69 lt T AD 70 lt AD 71 lt AD 72 lt AD 73 0 74 U Suld J0431u02 01 02 Ld 5 5 D anji ADI e ADI 3 AD 4 P AD 5 O AD 6
5. Figure 5 11 SDRAM J19 Bus Signals Page 1 of 2 DN5000k10 User s Manual Memories SDRAM J19 CKEO CKE1 S0 S1 S2 S3 BA0 BA1 WE CAS RAS gt gt N o SS ppV suld 3 DQMB1 DQMB 2 DQMB 3 DQMBIA DQMB 5 DQMB 6 DQMB 7 L eg DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 o o ejeq 5 11 Memories FPGA D U20 E18 F18 C18 A23 C23 F23 E23 B24 D24 B27 A26 D27 C27 B36 A28 B29 C19 SDRAM On Continued lt SDRAM DATA 21 4 SDRAM DATA 22 4 SDRAM DATA 23 4 LLC SDRAM DATA 24 lt SDRAM DATA 25 4 SDRAM DATA 26 4 SDRAM DATA 27 4 SDRAM DATA 28 J 4 SDRAM DATA 29
6. 4 aB 32 AB 33 lt AB 34 gt AB 35 lt AB 36 lt AB 37 gt lt M 38 lt 39 4 AB 40 41 lt AB 42 lt AB 56 57 AB 58 lt 59 lt AB 60 gt lt AB 61 AB 62 gt y lt AB 63 gt lt AB 64 lt AB 65 T lt AB 66 67 AB 68 Figure 5 4 SSRAM AB U21 Bus Signals DN5000k10 User s Manual Memories FPGA B U19 AV4 AU4 AW5 AV5 AU5 AW6 AV6 AU6 AW7 AV7 AU7 AW8 AV8 AU8 AW9 AV9 AUS AW10 AV10 AU28 AU10 AW11 AV11 AU11 AW12 AV12 AU12 AV13 AU13 AW14 AV14 AU14 AV15 AU15 AW16 AV16 AU16 AW17 AV17 AU17 AV37 AV18 AU18 AU36 AV19 AU19 AW20 AV20 AU20 AW21 AV21 AU21 AW22 AT36 AU22 AW23 AV23 AU23 AW24 AV24 AU24 AV25 AU25 AW26 AV26 AU26 AV27 AU27 AW28 Memories FPGA E U15 A18 D23 C18 A17 B17 ED ED 2 lt ED 3 T lt ED 4 nyh EDS ED 6
7. ED 35 0 36 EDI37 ED 38 ED 39 lt 0 40 ED 41 0 42 TD ED 43 0 44 0 45 0 46 ED 47 ED 48 0 49 0 50 0 51 0 52 4 ED 53 lt Oh ED 54 0 55 lt ED 56 lt o ED 57 0 58 0 59 4 ED 60 ED 61 ED 62 ED 63 ED 64 lt ED 65 s ED 66 EDI 67 lt P ED 68 gt FPGA D U20 E39 E38 F39 F38 F37 G39 G38 G37 H39 H38 H37 E27 E26 J37 K39 K38 K37 L39 L38 J34 L37 M39 M38 M37 N38 N37 P39 P38 G32 R38 R37 T39 T38 T37 U37 v39 V38 D35 D36 D34 AB39 AB38 AB37 AC39 AAC38 AC37 AD39 AD38 AD37 AF39 AF38 AG25 AG38 AG37 AH39 AH38 AH37 AJ39 AJ38 AJ37 AK39 AK38 AK37 AT36 AR37 AL37 AM39 AM38 AM37 The DINI Group Memories Pin 14 of each SSRAM may be pulled high pulled low or left unconnected Table 5 1describes which 0 ohm resistors must be used for each type of SSRAM to function correctly Table 5 1 Requirements for Non Standard SSRAMs ZBT Pipeline Install Install Install Install R290 R293
8. s Pcl_AD 21 lt F FN Eryri 0 22 lt v n o s a v F h n c ADI23 lt T V CU 0 24 lt ot x xcl l Ab 25 AA PCI AD 26 lt PCI AD 27 AAA PCI AD 28 lt PCI AD 29 i P CI AD 30 I _ 31 lt T CELO lt C BE 1 4 l 2 lt CREL lt a FRAME i m PCI AD 32 lt YOUFr AD 33 lt A n TOFrhc r AD 34 lt D F l AD 35 lt F Tp cI AD 36 lt n PocI AD 37 lt gt N c AD 38 lt r D IG I AD 39 lt amp P8CI AD 40 lt CI aja I _ PCI AD 42 i PeCI AD 43 I M PCI AD A4 i PeCI 0 45 PCI AD 48 i M ci AD 49 lt PCI AD 5O lC PCI AD 51 I PCI AD 52 PCI AD 53 I L PCI AD 54 i PCI AD 55 lt PCI AD 56 amp
9. gt AD 59 AD 60 n AD 61 AD 62 lt P AD 63 gt lt AD 64 lt AD 65 AD 66 FO AD 67 AD 68 lt 0 69 lt AD 70 gt AD 71 AD 72 mr lt AD 73 lt AD 74 Figure 5 3 SSRAM AD U23 Bus Signals FPGA D U20 The DINI Group FPGA A U12 AW36 AV36 AW35 AV35 AU35 AW34 AV34 AU34 AW33 AV33 AU33 AW32 AV32 AU32 AW31 AV31 AU31 AW30 AV30 AU12 1 lt 2 lt 3 4 lt 5 6 lt N 7 ABs 9 AB 10 AB 11 AB 12 AB 13 AB 14 AB 15 16 AB 17 lt 18 19 o 70 AU30 AW29 AV29 AU29 AW28 AV28 AU28 AV27 AU27 AW26 AV26 AU26 AV25 20 21 22 lt hn 23 lt 24 lt 25 lt PA AB 26 lt 27 lt R 28 29 lt AB 30 lt AB 31 lt
10. ED 7 0 8 gt gt lt ED 9 m ED 10 ED 11 lt ED 12 ED 13 ED 14 ED 15 ED 16 lt ED 17 ED 18 0 19 lt ED 83 ED 20 E En ED 23 ED 24 0125 4 0126 lt ED 27 4 ED 28 ED 29 4 EDB lt ED 31 lt ED 32 lt ED 33 lt ED 34 D ED 35 lt 0 36 lt ED 37 lt o ED 38 0 39 ED 40 lt ED 41 0 42 4 ED 43 lt ED a4 T V lt ED 45 lt 0 46 lt ED 47 lt ED 48 M ED 49 0 50 _ gt ED 51 b gt lt ED 52 ED 53 n
11. 8 7 DN5000k10AETEST Startup Screen DN5000k10 Recognized 9 4 AETEST Startup Screen No PCI Peripheral Recognized 9 5 AETEST Main Screen 9 6 AETEST PCI Men IRI ee eae ee 9 7 AETEST Memory 9 9 AETEST Write to Memory Test 9 10 AETEST Read Memory 9 10 AETEST Write Read Test 9 11 AETEST Memory Fill 9 11 AETEST Memory Display 9 12 AETEST Write Memory Byte 9 12 AETEST Read Memory 9 13 AETEST Write Read Memory Byte 9 13 Berg 91403 003 Datasheet Page 1 of 2 A 2 Berg 91403 003 Datasheet Page20f2 A 3 Berg 91294 003 Datasheet Page 1 of 3 4 Berg 91294 003 Datasheet Page20f3 A 5 Berg 91294 003 Datasheet Page30f3 A 6 The DINI Group List of Tables TABLE DN5000k10 User s Manual 2 1 2 2 2 3 2 4 3 1 3 2 3 3 3 4 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 1 5 2 6 1 6 2 7 1 7 2 TITLE Signals and Connections to 4 FPGA Serial JTAG Configuration Header J2 Configuration Jumper Settings Stratix FPGA Approximate File Sizes Present Signal Definitions M66EN Jumper Descriptions
12. J R269 A V CL sDRAM ADD 11 gt R40 SDRAM ADD 12 R231 SDRAM ADD 13 gt R52 M sbRAM DQMB 0 R51 R261 R36 R53 R273 R35 R232 R239 R233 SDRAM CB 0 SDRAM CB 1 SDRAM CB 2 SDRAM CB 3 SDRAM CB 4 SDRAM CB 5 SDRAM CB 6 SDRAM CBI7 SDRAM DATA O SDRAM DATA 1 SDRAM DATA 2 SDRAM DATA 3 SDRAM_DATA 4 SDRAM DATA 5 SDRAM DATA 6 SDRAM DATA 7 SDRAM DATA 8 SDRAM DATA 9 SDRAM DATA 10 DRAM DQMB 1 9 DRAM DQMB 2 9 DRAM DQMB s 9 DRAM DQMB 4 9 DRAM DQMB 5 9 R259 A L sDRAM DQMB 6 AN s DRAM DQMB 7 9 R243 WA somam sce lt SDRAM_SDA gt SDRAM SA 0 2 soram SAH gt AN SDRAM SA 4 50 DATA 11 lt _ _ 0 DATA 12 lt y lt SDRAM DATA 13 gt v n no lt A SDRAM DATA 14 gt _ SDRAM DATA 15 lt SsDRAM DATA 16 lt SDRAM DATA 17 4 spRAMN DATA 18 n h lt spRAN DATA 19 m lt sDRAM DATA 20
13. PCI AD 57 amp PCI AD 58 AD 59 EA 5 TR 6 lt CENT A58 B58 A57 B56 A55 B55 A54 B53 B52 A49 B48 A47 B47 A46 B45 A44 A32 B32 A31 B30 A29 B29 A28 B27 A25 B24 A23 B23 A22 B21 A20 B20 A52 B44 B33 B26 A34 B35 B16 A36 B37 A38 A26 B18 A60 B60 A67 A6 B40 B42 A15 B39 A43 A17 A91 B90 A89 B89 A88 B87 A86 B86 A85 B84 A83 B83 A82 B81 A80 B80 79 78 77 B77 76 75 74 B74 A73 B72 A71 B71 A70 B69 A68 B68 B66 A65 B65 A64 PCI Pin P2 Figure 3 1 FPGA Pin Connections for PCI Signals The DINI Group 45V 12V 412V 45V Q Q Q Q PCI_TDIO INTA PRSNT1 INTD__ AG S PRSNT1 VIO 1 PRSNT2 RSVD _ PRSNT2 3 3VAUX PCI_RST PCI CLK VIO REQ VIO 2 PME AD PCI_AD30 PCI AD28 PCI AD27 PCI AD26 P AD PCI AD24 C BE3 D P AD PCI AD22 PCI AD21 PCI AD20 PC ADIS PCI_AD18 PCI AD17 PCT ADTG FRAME IRDY TRDY DEVSEL GND STOP 3 3V Q A39 Q LOCK x m AA 546 SERR 72 23 37 4 Y PAR C BE1 4 ad 015 4 4 3V A46 PCI_AD13 PCI_AD12 4 Y PCLAD ADTO 48 A48 VIGGEN 9 P PCI AD9 PCI AD8 GND E C BE0 D A av pci ans PCI AD5 AD PCI AD2 PCI AD1 PCI AD0 VIO VIO ROCKO HEGO64 B6 C BE7 C BE6 BE4 B66 VIO
14. SDRAM DATA 46 lt SDRAM DATA 47 lt SDRAM_DATA 48 lt SDRAM DATA 49 4 SDRAM DATA 50 4 SDRAM DATA 51 4 SDRAM DATA 52 SDRAM 53 gt lt SDRAM DATA 54 y SDRAM DATA 55 lt lt SDRAM DATA 56 4 SDRAM DATA 57 gt lt SDRAM DATA 58 fn11Gs lt 50 DATA 59 4 sDRAM DATA 60
15. 4 6 NOTE C375 C393 C396 and C400 are stuffed with 0 ohm resistors Note that the schematic shows capacitors in positions C375 C393 C396 and C400 The DN5000k10 has 0 ohm resistors in these capacitor positions The termination resistors R182 R183 R190 R191 R197 198 and R200 R201 are not stuffed The DN5000k10 gives the user a simple means to bring off board clocks onto the board The user can attach 10 pin ribbon cable to rows B and C of the Clock Grid J13 B consists of an input to 3807 1 and differential pair inputs to both RoboclocklI s J13 C consists of ground pins for signal integrity These signals are described in Table 4 1 on page 4 3 BUFINA is a standard 3 3 V TTL input Both differential pairs provide some flexibility The user can provide a single 3 3 V TTL input It can be attached to either input However the other input must be left open The user can provide a differential clock input to the pair The differential clock inputs must obey the electrical specifications listed in Table 4 8 on page 4 13 The DINI Group Clocks and Clock Distribution While attaching a ribbon cable the user can jumper oscillator signal CLOCKB to BUFINB 3807 2 on J24 This results in full use of all of the timing devices on the DN5000k10 See Figure 4 5 WITHOUT 10 PIN RIBBON CABLE CLKOUT J13 7 CLOCKA J13 13 CLOCKB J13 1 Option goes to goes to goes to Notes Roboclock 2 may 1 PLL1A J13
16. 7 4 o R2 aan mr 8 Jd HH T LI U3 LILILI U2 OR vi H co C16 C19 C21 2 R6 uw ka e o o IDT74FST163245 chips are used as bus switches in the passive mode and the IDT74LVC16245A chips are used as bus transceivers in the active mode The DN3000k10SD has separate enable direction signals for each driver NOTE Availability of these I O signals depends on the location of the daughter card with respect to the development board The LEDs act as visual indicators representing the active power sources e D1 LED indicating 43 3 V present e D2 LED indicating 5 0 V present e D3 LED indicating 12 V present Under normal operating conditions all LEDs should be on A linear power supply U4 is present to provide level shift translation functions when the board is populated with bus switches The DINI Group Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors Options Resistors R10 and R11 can be used to select different voltage sources 5 V or 43 3 V respectively When used U4 must be removed in order to prevent contention NOTE Never populate R10 R11 simultaneously this will result in a shorted power supply Power Rating 5 V power supply is rated for 1 A 3 3 V power supply is rated for 1 A 1 5 V power supply is rated for 1 A 12 V power supply is rated for 0 5 A 12 V power supply is rated for 0 5 A
17. Programming Header N ss UAWAWAW uP_LED 3 0 Figure 2 7 DN5000k10Block Diagram of ATmega128L DN5000k10 Interfaces sections that follow Figure 2 7 is a block diagram of the ATmega128L and its various interfaces on the DN5000k10 J6 Unused HP 36 contains connections to the ATmega128L that were not used else Connections Where These ten connections can be used for external TTL connections to the pP externally generated interrupts or any other function that the ATmega128L supports on these pins Remember that the ATmega128L is not 5 V tolerant so if you attach external TTL signals to these pins the voltage level of these signals must not exceed 43 3 V DN5000k10 User s Manual 2 11 DN5000k10 Features Overview and General Description The J6 schematic is shown in Figure 2 8 uP GPIO J6 Figure 2 8 J6 Unused uP Connections uP JTAG 3 3V 3 3V PFO ADCO PF1 ADC1 PF2 ADC2 PF3 ADC3 Aie PF4 ADC4 PF5 ADC5 PF6 ADC6 PF7 ADC7 PWRRSTn Figure 2 9 J5 JTAG Interface ATmega128L ATmega128L processor has JTAG interface that can be used for on JTAG Interface hip debugging real time emulation and programming of FLASH EEPROM fuses and Lock Bits In order to take advantage of the JTAG inter face you must have the Atmel AVR JTAG ICE kit part number ATAVR JTAGICE and AVR studio software that Atmel provides free at www atmel com The JTAG interface for the ATmega128L c
18. ADI7 OV ADI8 Andy 4 10 sh AD 11 sv lt AD 12 AD 13 _ gt lt AD 14 AD 15 sM gt n AD 16 AD 17 lt o r AD 18 lt AD 19 lt N AD 38 a mM A AD 20 gt lt anz 4 022 4 23 lt ana 4 aa som lt 0126 K lt 0 27 YV YP 4 AD 28 4 0 29 lt Ap 30 4 031 4 ap a32 AD 39 lt AD 40 AD 41 lt gt lt n 0 42 lt 043 O lt AD 44 gt lt n AD 45 a 4 AD 46 gt AD 47 4 Ol AD 48 gt AD 49 lt M AD 50 AD 51 lt AD 52 gt lt AD 53 lt 0 54 p AD 55 _ gt lt AD 56 AD 57 v v lt AD 58
19. Connector J8 Table 7 1 shows the connections of J8 Table 7 1 Connector J8 Pins External Power Function i Function 2 3 4 5 6 7 8 9 DN5000k10 User s Manual 7 5 Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors LVDS Connector J2 Unbuffered I O Connectors J3 JA Connector J5 J6 J7 7 6 Low voltage differential signaling LVDS is a signaling method used for high speed transmission of binary data over copper It is well recognized that the benefits of balanced data transmission begin to outweigh the costs over single ended techniques when the signal transmission times approach 10 ns This represents signaling rates of about 30 Mbps or clock rates of 60 MHz in single edge clocking systems and above LVDS is defined in the TIA EIA 644 standards NOTE Not available on the DN5000k10 ASIC prototyping board This is a Mini D Ribbon MDR connector 50 pin manufactured by 3M used specifically for high speed LVDS signaling The connector mates with a standard off the shelf 3M cable assembly P N 14150 EZBB XXX 0LC where XXX is 050 0 5 m 150 1 5 300 3 0 m 500 5 0 m Please contact 3M for further details http www1 3m com The DN3000k10SD Daughter Card provides 66 unbuffered I O signals including 5 single ended clock signals The function of these signals is position dependent NOTE Si
20. 3 3V and 1 5V Standalone operation via separate power connector 43 3V not needed on backplane e 6low skew clocks distributed to all FPGA and test connectors 2CY7B993 4 Roboclockll PLLs 2 socketed oscillators PCI Clock 1dividable clock via CPLD e Direct support for Synplicity s Certify TDM interconnect multiplexing e Robust observation debug with 488 connections for logic analyzer observability or for pattern generator stimulus e Status LEDs DN5000k10 User s Manual 2 1 DN5000k10 Features Overview and General Description e User designed daughter PWB for custom circuitry and interfaces e SignalTap and Identify from Synplicity fully supported via JTAG interface Figure 2 1 shows a block diagram of the DN5000k10 DN5000k10 Description The DN5000k10 is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions The DN5000k10 can be hosted in a 32 64 bit PCI PCI X slot or can be used as a stand alone device A single DN5000k10 stuffed with five EP1S80s can emulate up to 3 5 million gates of logic as measured by LSI High 1508 pin flip chip BGA pack ages are employed The F1508 package has 1203 I Os which allows for abundant connections to daughter connectors and external memories A total of 488 test pins are provided on the top of the PWB via high density c
21. F Set PCI Function Number D Display all Configured PCI Devices 1 Display Vendor and Device ID for PCI device function 7f 0 2 Loop on PCI device fun 7f 0 and Display Vendor and Device ID 3 Loop on PCI device fun 7f 0 and Don t Display Vendor and Device ID 4 Loop on all PCI device numbers and Display Device Vendor ID s 5 Display all PCI information for PCI device function 7f 0 6 Write config dword 7 Read config dword C Configure BAR s from File V Save BAR Configuration to File M Main Menu Q Quit PCI BASE ADDRESS 0 d800000 1 e0000000 2 00000000 3 00000000 4 00000000 5 00000000 Please select option Figure 9 4 AETEST PCI Menu Set PCI Device Number sets a PCI device number of your choice as the active device hex input This option lists the available Device Numbers to help you match up your device IDDevice ID and Vendor ID with the device number Set PCI Function Number sets a PCI function number of your choice as the active function of a multi function device hex input This option lists the Device ID and Vendor ID of each function within the active device number to help you to choose the desired function Display all Configured PCI Devices Displays the PCI Device Numbers and corresponding Device ID and Vendor ID of all devices seen on the bus This does not display device numbers with a Device ID and Vendor ID of all ones OxFFFF Display Vendor and Device ID for PCI device f
22. N32 N31 P32 P31 R32 R31 T32 T31 U32 U31 V32 V31 W31 AF31 AD32 J30 AB32 AB31 AC32 AC31 AD31 AE32 AE31 AF33 AG32 AF32 AH32 AG31 AH31 K33 J29 K29 T29 U29 M30 N33 N30 P34 P30 R33 R30 V29 T30 W29 u30 v30 w30 AB30 AC30 AD30 AE33 AE30 AF35 AF30 AB29 AG30 AC29 AH30 AD29 AD26 AE26 AU38 AK29 AL30 AL29 SSRAM AD U23 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 expansion AD 1 ADI 2 AD 3 0 4 ADI5 AD 6 ADIT apis ADI9 lt AD 10 0 11 AD 12 I AD 13 m 4 AD i4 AD 15 gt r lt 0 16 lt 17 AD 18 ol m gt lt O AD 19 gt gt lt AD 38 s a j ADV ADSP ADSC BWA BWB BWC BWD BWE GW MODE CE OE zz mM AD 20 gt 0121 22 4 0123 lt AD 24 99 lt 0125 lt 0126 lt 27 4 28 lt
23. PCI_AD63 Bes AD6 PCT A Beo VIO PCI AD60 B71 PCI AD58 E B72 573 PCI AD56 PCI AD55 PCT AD54 PCI AD B75 VIO B76 LA PCI AD51 B77 50 AD49 B78 VIO B79 PCI AD48 _AD4 B80 PCI AD46 KDA PCI AD44 PCI AD4 PCI AD42 5 VIO 6 ATO PCI AD39 AD38 VIO 6 PCI AD36 AD PCT AD34 AD PCI AD32 PCI64M EDGE Figure 3 2 PCIIPCI X Edge Connector DN5000k10 User s Manual PCI 3 3 PCI 3 4 7 75 196 7 mm r s _ 13 25 in 336 2 a ma AB BUS SRAM gcc Eod 1 M mimrmmmarnanamamannami marmanamanaananmmaqcnru 4 i m g FB BUS SRAM ID Giesiiee TPS pg 2 DN5000K10 ASSY NO 502 0105 COPYRIGHT C 2002 THE DIN GROUP LA JOLLA INC MADE IN USA ED BUS SRAM e e LN TIT MS Figure 3 3
24. TO 80 HGT IS 47 01 APPLYS TO VERT THRU amp SURFACE MT STYLES 4 THE SOLDER TAILS ON THIS PRODUCT ARE DESIGNED TO BE COMPLIANT IN ORDER TO ACCOMMODATE PRINTED CIRCUIT BOARD DIMENSIONAL VARIATIONS THEREFORE HOLDOOWN HARDWARE 15 REQUIRED TO SECURE THE CONNECTOR TO THE PRINTED CIRCUIT BOARO FOR MOST TYPES OF SOLDER REFLOW OPERATIONS FOR FURTHER APPLICATION DATA INCLUDING HOLE SIZES FOR VARIOUS TYPES OF HARDWARE SEE TA 932 DO NOT REMOVE PROCESSING CAP UNTIL SOLDERING 15 COMPLETED EXAMPLE XXXXX XXXH HOLD DOWN __ lineor XXX amp 005 projection title _ xxx 2 0020 EJ 4d ongles o i2 form no 7530 001 103 BY ADDING LETTER HT TO TABULATED P N THE OPTIONAL MOLD DOWNS WILL BE SUPPLIED INTEGRAL W CONNECTOR ELECTRONICS MICROPAX 025M SMT PLUG DOUBLE MODULE product fomil MICROPAX or 3 4 93 INCH MM eng wnan 3 4 93 size dug no chr unan 3 4 93 scole 91294 www 5 1 1 cage code 22526 Figure A 5 Berg 91294 003 Datasheet Page 3 of 3 The DINI Group A 6 Glossary and Acronyms pP BAR BGA BIOS CMOS CPLD CSF DSP EEPROM EIA ESD FAQ FAT FPGA FT HDL VO IP LED LSI LVCMOS microprocessor Base Address Register ball grid array Basic Input Output Services complementary metal oxide semiconductor Complex Programmable Logic Device Configuration Settings File d
25. lt S DRAM DATA 61 P lt 0 DATA 62 lt e T n V s lt SDRAM DATA 63 4 SDRAM REGE See REGE below Figure 5 12 SDRAM J19 Bus Signals Page 2 of 2 SDRAM J19 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 p nunuoo sulg eea R189 and R193 are connected to the WP Write Protect input of the Board Options 5 12 SDRAM EEPROM Stuffing a 0 ohm resistor in R193 will keep the WP signal high whereas stuffing it in R189 drives the signal low The default config uration is RS193 stuffed NEVER stuff both resistors at the same time The EEPROM holds data describing the size configuration and timing characteristics of the SDRAM The data is write protected when the WP signal is high There should be little or no reason to want to overwrite the EEPROM data Some SDRAM manufacturers simply connect the WP pin of the EEPROM chip to the power supply of the SDRAM in which case the WP resistors have no effect whatsoever Header J17 is connected to the REGE Register Enable input of the SDRAM and to ground A pull up resistor keeps the REGE signal high
26. 0 J13 ACLK 8 0 BCLK 9 0 X3 stuffed at factory with 33 MHz X2 stuffed at factory with 14 318 MHz ACLK BCLK CCLK DCLK ECLK ACLK BCLK CCLK PCI CLK DCLK ECLK PCI Connector Figure 4 1 Clock Distribution Block Diagram ACLK BCLK CCLK ACLK BCLK CCLK DCLK ECLK ACLK BCLK CCLK DCLK ECLK The DINI Group Clock Grid Orientation and Description DN5000k10 User s Manual Clocks and Clock Distribution frequency Phase adjustments can be made in 625 ps or 1300 ps steps up to 10 4 ns All adjustments are jumper selectable The clock grid J13 gives the user the ability to customize the clock scheme on the DN5000k10 A brief description of each pin is given in Table 4 1 The physical orientation of the pins is diagrammed in Figure 4 2 Table 4 1 Clock Grid Signal Descriptions Signal Description CLKOUT Clock signal from CPLD Typically 12 MHz PLL1A Input to Roboclockll 1 CLOCKA Clock signal of oscillator 1 X1 BUFINB Clock input to 3807 2 CLOCKB Clock signal of oscillator 2 X2 PLL2B PRE Secondary clock input to Roboclockll Il 2 Differential pair with PLL2BN PRE PLL2BN PRE Secondary clock input to Roboclockll Il 2 Differential pair with PLL2B PRE BUFINA Clock input to 3807 1 PLL1BN PRE Secondary clock input to Roboclockll 1 Differential pair with PLL1B PRE PLL1B PRE Secondary clock input to Robo
27. 10 BUFINA J13 14 BUFINB J13 4 be driven by Roboclock 1 Roboclock 2 may 2 BUFINB J13 4 BUFINA J13 14 PLL1BN J13 2 be driven by Roboclock 1 BUFINA J13 14 PLL1BN J13 2 3 PLL2BN J13 8 Buffer B is undriven PLL1A J13 10 BUFINB J13 4 PLL2B J13 11 4 BUFINB J13 4 requires wire wrap PLL1BN J13 2 Buffer A is undriven BUFINA Buffer A gt BUFFINB gt Buffer B gt BCLK PLL1A Roboclock gt CCLK DCLK PLLSEL1 low PLL1B Roboclocki gt CCLK DCLK PLLSEL1 high PLL2B gt Roboclock2 PLLSEL2 high Roboclock1 Roboclock2 with PLLSEL2 low J27 installed and FCKLOUT unused WITH 10 PIN RIBBON CABLE Option Connected to J21 and J22 3 external PLL1B PLL2B and BUFINA are driven from cable BUFINB can be clocks jumpered to CLKOUT or CLOCKB or left undriven 2 external PLL2B and BUFINA are driven from cable with PLL1A jumpered to clocks CLKOUT or CLOCKA Same options as above for BUFINB PECL The board can be set up for PECL inputs in PLL1B and PLL1BN and in clocks PLL2B and PLL2BN PECL ready boards cannot function without the cable except as in options 3 and 4 above Figure 4 5 External Ribbon Cable Connections Roboclock PLL Clock Buffers Figure 4 6 is a functional diagram of Roboclock 1 and Roboclock 2 Jumper Desc
28. 3 0 amps Most of the signals are TTL or some low current variation such as LVDS so you can reasonably expect to get up to 3 amps per power pin through this connector Remember that the 3 3V and 1 5V power supplies are limited to 5 amps total the memories the FPGA and the clock circuitry on the DN5000k10 consume 3 3V The FPGA only consumes 1 5V If you use the DN5000k10 stand alone meaning that it is not plugged into a PCI slot the auxiliary power connector has 5V and 12V but does not have 12V So unless you provide 12V to the DN5000k10 via another connection 12V will not be available for use by a daughter card NOTE 12V is not required by the DN5000k10 The DN5000k10 will operate normally without 12V power supply Some of the interconnect with the 200 pin connectors is shared with the memories See Figure 5 1 on page 5 2 to see which signals are shared The 200 pin connectors are shown in Figure 8 5 Notes e The signal labeled HDR_CLKOUT on J9 is connected to a Roboclock input and may be used to supply a clock to the FPGAs The same pin on J10 and J16 is connected to a Roboclock output so if a daughtercard is built to supply a clock output to HDR CLKOUT it should not be put on J10 or J16 All other clock data and power pin locations are the same on each header so a daughtercard designed for J10 can be put on J16 instead with no problems Cards designed for J9 may be built with a jumper between their
29. 4 General LE Diagram 2 5 Dual Port Data Flows 2 6 DSP Block Diagram 2 7 Multiplier Sub Component Block Diagram 2 8 DN5000k10Block Diagram of ATmega128L and DN5000k10 Inter llc ue Cpu egy aw ky a W Saw Q AI 2 11 J6 Unused pP Connections 2 12 J5 JTAG Interface 2 12 J2 Schematic nfl ree arene 2 13 Location of J4 on the DN5000k10 2 16 J3 Serial Port Locations 2 19 Delkin 32 MB 3 3 V Smart Media Card 2 25 FPGA Pin Connections for PCI Signals 3 2 PCI PCI X Edge 3 3 DN5000k10 Dimensions 3 4 JP1 PCI X Present Header 3 5 PCI X Capability Header 3 6 Clock Distribution Block Diagram 4 2 Clock Grid 26 u y er USER ENSE qes 4 4 Common Clock Configurations 4 5 PECL Clock Input and Termination 4 6 External Ribbon Cable Connections 4 7 Functional Diagram of Roboclock 1 and 2 4 8 Header Layout uyu lll Lll 4 9 Clock OE Pin Jumper Settings 4 15 PCI PLL Circuit 4 17 FPGA Interconnect Bl
30. 43 3 V CMOS version is needed with a tolerance of 50 ppm The part number for an acceptable oscillator from this family would be SG 8002DC PCB ND package SG 531 output enable 3 3V CMOS 50ppm If the order is placed via the web page the requested frequency to two decimal places is placed in the Web Order Notes The datasheet is on the CD ROM for this oscillator The file name is SG8002DC pdf The DINI Group Clocks and Clock Distribution Any polarity of output enable for each oscillator on pin 1 is acceptable Make sure that you have the proper jumper settings at positions 9 and10 of J14 J15 and J16 See Figure 4 8 and Figure 4 9 for a description 3 3V LJ FBFO01 HEADER 10x3 HEADER 10x3 HEADER 10x3 Figure 4 8 Clock OE Pin Jumper Settings Table 4 9 Clock OE Pin Jumper Settings Clock OE Jumper Settings Active High OE for X1 Jumper J11 26 to J11 27 Active Low OE for X1 Jumper J11 26 to J11 25 Active High OE for X2 Jumper J11 29 to J11 30 Active Low OE for X2 Jumper J11 29 to J11 28 DN5000k10 User s Manual 4 15 Clocks and Clock Distribution DN5000k10 PCI Operation PCI CLK Details 4 16 The DN5000k10 ASIC emulation board has the ability to run all FPGAs all SRAMs and all the SDRAM off of PCI CLK PCI single destination clock which is routed to FPGA F U11 from the PCI connector The user can input PCI one of the Stratix Enhanced PLLs in F
31. 8 The DINI Group Clocks and Clock Distribution Figure 4 7 Header Layout Table 4 2 Header Classification Controls Header Group 2 PLL1 Divider Control Group 3 PLL2 Divider Control Group 4 Feedback and fyoy Control The input pins are either LVTTL or 3 level input pins The LVTTL pins need to be jumpered HIGH or LOW which is achieved by connecting the input pin to the neighboring 43 3 V or GND pin using a jumper The 3 level input pins can be in a HIGH MID or LOW state The HIGH and LOW states are achieved in the same way as the LVTTL pins The MID state is reached by leaving the input pin unjumpered The Roboclockll s have internal circuitry to bring the pin to 1 5 V when left open The Jumper Definitions are shown in Table 4 3 DN5000k10 User s Manual 4 9 Clocks and Clock Distribution Table 4 3 Jumper Definitions Name Type Default Description PLLSEL2 1 Input Clock Select If LOW U16 DCLK 7 or FCLKOUT U14 PLL1A or HDR_CLKOUT is selected as the input clock If HIGH the U16 PLL2B U14 PLL1B_N pair is selected as the input clock MODE 2 1 Output Mode If HIGH clock outputs disable to high Z state If LOW clock outputs disable to HOLD OFF mode If MID clock outputs disable to factory test mode INV2 1 Invert Mode When HIGH clocks CCLK 3 0 ECLK 3 0 are inverted When MID these clock outputs are non inverting When LOW the pairs CCLK 1 0 and CCLK 3 2 ECLK 1 0
32. ED 54 lt ED 55 ED 56 lt ED 57 ED 58 ED 59 A lt ED 60 ED 61 _ gt ED 62 lt ED 63 ED 64 ED 65 lt ED 66 AUh lt ED 67 lt ED 68 Figure 5 5 SSRAMI ED U18 Bus Signals SSRAM ED U18 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 expansion Lo Suld SseJppy ADV ADSP ADSC BWA BWB BWC BWD BWE GW MODE CE OE 22 10 D0 D1 D2 D3 lt EDI1 lt EDI 2 x EDI3 EDI4 lt EDI5 lt EDIS lt M ED 7 lt EDI8 0 9 ED 10 ED 11 n ED 12 ED 13 ED 14 ED 15 m 0 16 0 17 ED 18 0 19 lt ED 83 lt ED 20 lt EpI 21 lt ED 22 lt ED 23 lt ED 24 lt N ED 25 lt TY ED 26 lt 0 27 ED 28 lt 0 29 lt 0 30 lt 0 31 lt ED 32 ED 33 0 34
33. ED 83 SSRAM ED U18 Figure 5 1 FPGA Interconnect Block Diagram 5 2 The DINI Group FPGAF U11 L32 K25 M32 M31 N32 N31 P32 P31 R32 R31 T32 T31 U32 U31 v32 V31 W31 AA36 AA27 P24 AB32 AB31 AC32 AC31 AD31 AE32 AE31 AF32 AF31 AG32 AG31 AH32 AH31 K32 G30 K29 J28 M30 N33 N30 N24 P30 R33 R30 U29 T30 T29 U30 V30 W30 AB30 AC30 AD30 AD29 AE30 AF33 AF30 AC29 AG30 AB29 AH30 AJ33 AR35 AR36 AT36 AK29 AL30 AL29 AV37 FB 1 FB 2 FB 3 FB 4 FB 5 FB 6 FB 7 FB 8 FB 9 FB 10 11 lt rB 12 rFB 13 lt FB 14 on F 15 lt 16 lt O FB 17 gt 18 19 129 v s lt FB 20 lt FB 1 lt 22 lt LT 23 lt nTrFEBI 24 lt 25 lt FB 26 lt IIIZIIP I lt 28 lt 29 lt rB 30 lt 31 lt FB 32 40 41 42 43 FB 44 gt 45 46 47 48 49 lt 50 51 52 FB 53 5
34. Ground Not Capable Connected Ground Pull down PCI X 66 MHz Not Pull down PCI X 66 MHz Connected Ground Not PCI X 133 MHz Connected Not Not PCI X 133 MHz Connected Connected 3 7 DN5000k10 User s Manual PCI 3 8 The DINI Group Clocks and Clock Distribution Chapter 4 Clocks and Clock Distribution Functional Overview The DN5000k10 ASIC emulation board has a flexible and configurable clock scheme Figure 4 1 is a block diagram showing the clocking resources and connections The clocking structures for the DN5000k10 include the following features e 2 user selectable socketed oscillators X2 X3 148 MHz oscillator X1 e 2 CY7B993 or CY7B994 RoboclocklI Multi Phase PLL Clock Buffers e 2FCT3807 Low Skew Clock Buffers The Clock Grid J13 a 5X3 0 1 in header distributes clock signals to two FCT3807 clock buffers and two RoboclocklI PLL clock buffers CY7B993 or CY7B994 The clock outputs from the buffers are dispersed throughout the board Two 3 3 V half can oscillator sockets X2 and X3 and the signal CLKOUT from the CPLD provide on board input clock solutions The DN5000k10 is shipped with both a 14 318 MHz X2 and a 33 MHz X3 oscillator Neither X2 nor X3 are used by the configuration circuitry so the user is free to stuff any standard 3 3 V half can oscillator in the X2 and X3 positions more detail later in Customizing the Oscillators on page 4 14 The Clock Grid
35. JP2 Me6EN 66MHz Enable 3 5 TP7 PME Power Management Enable 3 6 PCI PCI X Capability 3 6 JP3 PGIXGCADPD t U sos Si ac ERR Ia ERIS 3 6 Chapter 4 Clocks and Clock Distribution Functional OverviewW 4 1 Clock Grid 4 3 Orientation and Description 4 3 Jumper Control for the Most Common Applications 4 4 Ribbon Cable Providing an Off Board Clock to the 5000 10 4 6 Roboclock PLL Clock Buffers 4 7 Jumper Descriptions 4 7 General Control 4 11 Feedback and Clock Multiplication 4 11 Clock Division 4 11 Clock Skew 2 0 sick sate ion Che Bed 4 12 Differential Clocks 4 13 Useful Notes and Hints 4 14 Customizing the Oscillators 4 14 DN5000k10 PCI CLK Operation 4 16 PCI CEK Details 4 16 BCLKOUT FCLKOUT 4 17 Header 4 17 DCLK 7 R 4 17 Chapter5 Memories SSRAMS okies ey bee malo Mak eek 5 1 SSRAM Notes 5 1 Pipeline Flowthrough
36. R286 R219 R291 R294 R287 R220 R296 R298 R288 R221 ZBT Install Install Install Install Flowthrough R289 R292 R284 R219 R291 R294 R285 R222 R295 R297 R288 R223 Syncburst Flowthrough No Extra Resistors or Pipeline DN5000k10 User s Manual 5 7 Memories Pipeline Syncburst FT Flowthrough Figure 5 6 is the most straightforward type Flowthrough of SSRAM available for the DN5000k10 Write data may be accepted on the same clock cycle as the activation signal and address and read data is ZBT returned one clock cycle after it is requested Syncburst is designed to allow two controllers to access the same SSRAM using two activation signals ADSC and ADSP an activation with ADSP requires data and byte enables one clock cycle after the address and activation Syncburst PL Pipelined Figure 5 7 is identical except for registered outputs which delay read data an additional clock cycle but may be necessary for high speed designs Zero Bus Turnaround ZBT SSRAMs are designed to eliminate wait states between reads and writes by synchronizing data Thus ZBT FT SSRAMs Write Control Logic 18 2 E Burst a Control 1 0 Memory Address Block Register Output Buffers Read Control Logic Figure 5 6 Syncburst FT Write Control Logic Memory Block Address Register Read Control Logic Figure 5 7 Syncburst PL 5 8 The DINI Group Memories Figure 5 8 accept a
37. ZBT 5 8 SDRAM ct eit eee REN faces 5 10 SDRAM On Board Options 5 12 iv The DINI Group Chapter 6 Power Supplies and Power Distribution POW eM 6 2 T1 5 V POWSE ee owed Ein 6 2 Stand Alone Operation 6 3 Chapter 7 Daughter Connections to DN3000k10SD Obser vation Daughter Card for 200 pin Connectors DTE 7 1 F alileS dosis ua des e od cose qa eee ee 7 1 Daughter Card LEDs 7 4 Power Supply 7 4 ODNONS puyuy ee eee PELO ENT 7 5 Power 7 5 Connector J8 7 5 LVDS clc Zi l usa uuu SY Al s a us a SS uu ee 7 6 Connector 222222 Sens Sherer eee 7 6 Unbuffered lO u pu gsl 7 6 Connectors J3 J4 7 6 Connector J5 J6 J7 7 6 Buttered De xXx ERE 7 7 Active Se Sanh et mua Q u vM 7 7 ECL CU 7 7 Test Interface 7 7 Connector JT a us s ae 7 7 Daughter Card I O Connections 7 8 Chapter8 Reset Schemes LEDs Bus Bars and 200 Pin Connectors Reset Schemes ie s sov edie bite eed REPE ded 8 1 LEDS ie dere Clete Z Psy BU eee Iu 8 3 Bus Bars suse una a a aa
38. and release it quickly you probably won t see LED5 since the 200 ms reset pulse is not strong long enough for the eye to observe Depressing the push button S1 causes the following sequence of events 1 Reset of the CPLD and uP 2 FPGA configuration is cleared 3 If the switches on S2 are set for Fast Passive Parallel and there is a valid SmartMedia card inserted into the socket then the FPGA will be configured A SmartMedia card is valid if it complies with the SSFDC specification and contains a file named main txt in the root directory If the card is invalid or there is no card present then the FPGA will not be configured 4 The Main Menu will appear The identical sequence of events occurs at power up DN5000k10 User s Manual 8 1 Reset Schemes LEDs Bus Bars and 200 Pin Connectors 3 3 V Reset Button Reset Control LT1326 Power 3 3 V Supply LED S1 1 5V Monitor ATmega128 P a U8 Programming Header Figure 8 1 Reset Functionality 8 2 The DINI Group Reset Schemes LEDs Bus Bars and 200 Pin Connectors LEDs The DN5000k10 has eight LEDs that are used to visually communicate the status of circuitry Figure 8 2 Figure 8 2 DN5000k10 LEDs From left to right the LEDs are labeled CPLD_LEDO CPLD LED1 CPLD LED2 CPLD LED3 UP LEDO UP LED1 UP LED2 UP LED3 see Figure 8 3 DS1 DS2 CPLD LED1 CPLD LED3 UP LED1 UP LED3 CPLD LEDO CPLD LED2 UP LEDO UP L
39. clock source and the HDR_ CLKOUT pin in which case they can be put on J10 or J16 if the jumper is disconnected 8 6 The DINI Group J16 GND 84 1 5V AB174 3 3V 16 DCLK5 GND AB173 9 GND 0 GND 8 G 0 T ee o o d Dee o z o 034 0 60 6 GND GND 6g AB 7 dd RET 0 Cf o CoH zz Cd iz 0 BTY A B20 N B GND B con200 DN5000k10 User s Manual Reset Schemes LEDs Bus Bars and 200 Pin Connectors J10 GND 12V 5 ND GND 4 MIB154 5V 4 3 3V BCLK 6 DCLK6 5V 6 GND CCLK7 GND B 1 5V 3 3V GND 9 9 GND 3 3V 9 9 GND 0 0 HDR_CLKOUT10 0 GND GND AD ADT49 7 D 8 AD59 D AD60 ADT150 ADo 5 G D 6 ADG DO ADO 8 8 8 GND 0 0 AD 0 0 ADO AD AD66 GND AD6 AD AD68 E AD109 AD69 A AD108 AD70 APA 6 6 6 6 AD B AD106 AD 5 8 8 AD10 8 AD B 9 9 ADT04 9 9 GND 0 0 AD10 0 0 AD 7 4 526 AD10 AD 524 AD10 AD GND GND AD AD100 4 AD 6 r AD z 6 6 6 AD14 520 AD14 519 8 8 8 AD B 9 9 Q ADT40 40 40 40 0 GND 4 4 AD1T39 4 AD 8 B14 A AD T 44 4 AD 6 T 4 T AD tO 46 b 6 AD 4 AD36 18 48 8 8 AD 8 8 AD 8 2 9 9 AD78 Q Q 60 60 AD 7o 60 60 6 6 AD 6 6 6 6 AD 6 6 D 6 6 AD 6 6 6 6 AD 65 6 0 66 66 GND 66 66 E 6 6 AD 6 6 E a n AD56 3 n 0 0 0 0 GND dodddddslddddddddddeidddddddddosidddudaa dut FEE 80 80 8
40. configuration process will begin as long as there is a valid SmartMedia card inserted properly in the socket If there is not a valid SmartMedia card in the socket then UP LED 3 0 will flash see Figure 8 2 on page 8 3 for LED descriptions and the Main Menu will appear from the serial port A SmartMedia card is determined to be invalid if either the format of the card does not follow the SSFDC specifications or if it does not contain a file named main txt in the root directory If the configuration was successful a message stating so will appear and the Main Menu will come up Otherwise an error message will appear The LEDs on DS1 and DS2 give feedback during and after the configura tion process see LEDs on page 8 3 for further details After the FPGA has been configured the following Main Menu will appear on the serial port Configure FPGA s using main txt Interactive FPGA configuration menu Check Configuration status Select file to use in place of main txt List files on SmartMedia a gt w N Select FPGA to program via JTAG Description of Main Menu Options 1 Configure FPGAS Using main txt as the Configuration File By selecting this option the FPGA will configure in Fast Passive Parallel mode You can also press the reset button S1 to reconfigure the FPGA in Fast Passive Parallel mode 2 Interactive FPGA configuration menu This option takes you to a menu titled Interactive Configu
41. has four mounting holes two screw holes at each end and two alignment holes between pins 50 51 and after pin 100 see Figure 8 4 These mounting holes are part of the metal shell of the The DINI Group The Signals DN5000k10 User s Manual Reset Schemes LEDs Bus Bars and 200 Pin Connectors Mounting Holes Figure 8 4 91294 003 Pin Numbering connector and make an important connection to the mating connector All four of these mounting holes are connected to digital ground on the DN5000k10 therefore the shell of the connector is grounded We used the pin numbering shown in Figure 8 4 for the 200 pin 91294 003 connectors Each of the three 200 pin connectors has the following e 162 signals connected to the FPGA 162 are connected to the FPGA A subset of the 162 are also connected to the memories 7 clocks The following power rails 12V 1 pin Reset Schemes LEDs Bus Bars and 200 Pin Connectors 12V 1 pin 5V 2 pins 43 3V 2 pins 41 5V 2 pins GND 23 pins case Regarding the amount of current that the power pins can carry the following text is lifted directly from the specification for the Micropax family of connectors 6 1 Current Rating Current rating shall be evaluated in still air at 25 ambient temperature Under the following conditions the temperature rise shall be no greater than 30 All contacts powered at 0 5 amp One contact powered at
42. like the memories RTL description of your multipliers is all that is necessary unless you are synthesizing with Quartus Make sure to check the report files multipliers that are implemented using logic blocks as opposed to the embedded memory blocks take huge amounts of FPGA resources The DINI Group DN5000k10 Features Overview and General Description 4 Clocks are the biggest problem when converting ASIC code to FPGA code FPGAs only have a limited number of clock arrays This is far too complicated to describe here so get the Stratix Data Sheet and read about the clocks DN5000k10 User s Manual 2 27 DN5000k10 Features Overview and General Description 2 28 The DINI Group PCI Chapter 3 PCI Overview The DN5000k10 can be hosted in a 32 bit or 64 bit PCI slot PCI X is also supported Stand alone operation is described in Stand Alone Opera tion on page 6 3 An EP1580 7 with care should be able to support a 64 bit 66 MHz PCI or PCI X controller We have not tested the PWB at PCI X speeds of 100 MHz and 133 MHz We suspect but won t guarantee that the DN5000k10 can support these high frequencies provided the speed grade of the FPGA is adequate Figure 3 1 shows the FPGA pin connections for the PCI signals This data is provided on the CD ROM in a CSF file titled pins F csf for your convenience The edge connector is shown in Figure 3 2 Stratix parts cannot tolerate 5 V TTL signaling so th
43. select the hardware from a list and press Next gt 6 Choose Other Devices from Hardware Types list and press Next 7 Click on Have Disk The DINI Group Utilities 8 In Copy Manufacturer s Files From window find the directory where qldriver sys is located then press OK 9 You should see dn2000k10 driver under Models click on Next 10 Press Next and then Finish 11 Run aetestnt exe Installation Instructions for LINUX This has been tested on Red Hat Linux 7 2 kernel version 2 4 x Note that all the text files including the scripts are DOS text format with an extra carriage return character after every new line so you need to convert them 1 You must be root to start the driver and the program dndev load and dndev unload are scripts that load and unload the driver dndev o is the driver file Load the driver type sh dndev load Unload the driver type sh dndev unload After driver is loaded run the utility aetest linux Pw Note You might need to run chmod on aetest linux to make it executable type chmod u x aetest linux Installation Instructions for Solaris The utility and driver are tested on Solaris 7 0 Sparc with the 32 bit kernel Note that all the text files including the scripts are DOS text format with an extra carriage return character after every new line so you need to convert them 1 To install the driver go to the
44. the line is missing or the character after the is not y or n then the sanity check will be enabled For each FPGA that the user wants to configure there should be exactly one entry in the main txt file with the following format FPGA F example rbf In the above format the F following FPGA is to signal that this entry is for FPGA F and FPGA F would then be configured with the bit file example rbf The DN5000k10 has one to five FPGAs which are FPGA A B D E and F The example has only one FPGA which is FPGA F There can be any number of spaces between the and the configuration file name but they need to be on the same line 2 21 DN5000k10 Features Overview and General Description 2 22 Comments are allowed with the following rules 1 All comments must start at the beginning of the line 2 All comments must begin with 3 If a comment spans multiple lines then each line must start with Commented lines will be ignored during configuration and are only for the user s purpose e The file main txt is NOT case sensitive IMPORTANT All configuration file names have a maximum length of eight 8 characters with an additional three 3 for the extension Do not name your configuration files with long file names In addition all file names should be located in the root directory of the Smart Media card no subdirectories or folders are allowed Since the main txt file controls which file is used to co
45. until at least the 2004 time frame Figure 2 2 shows the stuffing options for the DN5000k10 What happened to C we struggled with the layout for many months which gave the buffoons in marketing time to rethink what they asked for As is normally the case with marketing after a few drinks they decided to change the requirements The FPGA that originally was in the C position was eliminated and replaced with the four SSRAMs and a SDRAM DIMM So much work had been done to that point that those of us in engi neering didn t think it wise to re label the FPGAs That is why no FPGA C exists The following is a very brief overview of the Stratix family More informa tion can be gleaned from the Stratix Datasheet ds stx pdf This file is on the CD ROM supplied with the DN5000k10 but you are better off getting the latest version from the Altera Web page http www altera com Make sure to get the latest errata sheet also DN5000k10 User s Manual 2 3 DN5000k10 Features Overview and General Description DN5000K10 STUFFING OPTION COMPARISON Non Header Memory Access Total Chip to Non Memory Non Memory TOTAL Single FPGA Single Stuffed Chip Chip to Chip Chip to Chip Header Header FPGA FPGAs PCI SDRAM SSRAMs Connections Connections Connections Connections Connections SSRAMs ABDEF YES 4 1867 1591 1367 488 0 ABDE ABDF ABEF ADEF BDEF ABD ABE ABF ADE ADF AEF BDE BDF BEF DEF AB AD AE AF BD BE
46. when the header is unconnected adding a jumper between the two pins drives the signal low The default configuration is no jumper REGE is also connected The DINI Group DN5000k10 User s Manual Memories to FPGA D intended as an input so that the design can check the status of REGE Do NOT drive this signal high when J17 is jumpered On some SDRAMs the REGE input may be used to select Registered or Non Registered behavior If REGE is high the control signals will go through registers before being sent to the individual DRAMs delaying access by one clock cycle but improving fanout if it is low the signals will be passed directly to the DRAMs 5 13 Memories 5 14 The DINI Group Power Supplies and Power Distribution Chapter 6 Power Supplies and Power Distribution The DN5000k10 can be hosted in a 43 3 V PCI slot or it can be used stand alone Figure 6 1 shows the various supplies used on the DN5000k10 and the connections of these supplies on the circuit board The supply 5 V from the PCI connector or P1 supplies the basic power to the DN5000k10 The 43 3 V power from the PCI connector is not used nor is it connected to any circuitry on the DN5000k10 P1 J9 5 5 V 3 3 V 41 5 V 12 V 12V Molex J10 5 V 3 3 V 41 5 V 12 V 12V 200 pin Micropax Connectors P2 3 J16 5 V 3 3 V 41 5 V 12 V 12 V PCI X Connector SSRAM FB SSRAM AD SSRAM AB Figure 6
47. 0 00000000 00000000 00000000 00000000 18 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 TG 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Figure 9 10 AETEST Memory Display f forward pages the screen forward in memory b back pages the screen backwards in memory j jump jump to a specific location in hex 0 goto jump back to the original address location specified at the beginning d delay and display loop display wait for a second and dis play again Loop until a key is struck Write Memory Byte write a specific number of bytes to a single memory address Figure 9 11 Input address byte to write byte to write Please select Numbers of long words to write l Display 2 Display 3 Don t display result and loop indefinitely 5000000 in decimal 2 hex hex ff aa in in result result and loop indefinitely 9 12 Figure 9 11 AETEST Write Memory Byte You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be accessed A minimum of 1 to a maximum of 1024 bytes will be written in sequ
48. 0 80 44 8 8 AD 8 B 8 8 AD 8 B 8 B AD 8 B 8 8 84 B D 8 8 ADSS 8 8 40 86 86 AD35 86 86 540 8 AD 8 8 GNI 88 GND 88 B 6 AD B 90 90 AD 90 90 9 9 A 9 9 0 B Q Q 8 AD 9 Q Q 1 5 V 9 9 AF39 1 5 V 9 9 A B 94 04 A ADT3U 94 94 A E 9 9 GND AD 9 GND B 96 o AF83 AD126 96 Q AF4 BTTS AF80 AD 9 5120 98 AF82 AD128 98 8 GND 99 99 GND 99 12V 00 00 AF81 12V 00 00 8 con200 con200 Figure 8 5 200 Pin Connectors Signal Connections Reset Schemes LEDs Bus Bars and 200 Pin Connectors 8 8 The DINI Group Chapter 9 Utilities PCI Debug General Pontificating Debugging of PCI based hardware can be troublesome so it is best to do so with a tiered approach The following sequence of events needs to occur for PCI based peripheral to start working 1 The hardware must boot itself at power up in the case of the DN5000k10 a The pP must boot b Recognize the SmartMedia card Configure the FPGA Hopefully all this occurs before RST on the PCI bus is deasserted 2 The PCI BIOS executes the PNP routines and configures the BARs on all PCI peripherals The operating system driver initializes the card 4 The application initiates communication with the driver and the application executes The steps are dependant Each of the steps must start and execute flaw lessly before the next step occurs When you get a PCI card for the first time it is necessary to debug each step bef
49. 00k10 User s Manual A 1 Berg Connector Datasheets All rights striclly reserved Reproduction or issue to third porties in any form Tous droits strictement reserves Reproduction ou communicolion a des tiers interdite wholever is not permitted without written outhority from the proprietor Coss SA sous queique forme que ce soit sons autorisotion ecrite du propeelore Property of C BERG ELECTRONICS Copyright BERG ELECTRONICS INC Propriete de BERG ELECTRONICS Droits de reproduction BERG ELECTRONICS INC w gt 0i 100 0 S4 OU SS3N OIML LOVINOD E sco oio o 1 01 2705 06 03110 NOUD3S 0 0 et0 e i00 a 2 N gt 661 evo x zo i ovo 2 0 asimsayjo sSajun S 3U0J O 025 6 8 t kd i uonoefcud R AdO9 YINOLSND es cio V ou lazis 193934 6 ie ooi 1WS WSZO XVdOSOIN JINON 319NIS F L Figure A 1 Berg 91403 003 Datasheet Page 1 of 2 A 2 The DINI Group Berg Connector Datasheets All rights strictly reserved Reproduction or issue to third parties in any form Tous droits strictement reserves Reproduction ou communication a des tiers interdite whatever is not permitted without wrilten authority from the proprietor BERG sous quelque forme que ce soit sons oulorisotion ecrite du propietoire Property of BERG ELECTRONICS Copyright BERG ELECTRONICS INC Propriete ELECTRONICS Droits de repro
50. 05 U19 AT10 PAN 10 AD 38 U20 W14 FB 41 U11 G30 AB 104 U19 AP9 7 10 The DINI Group Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors Table 7 2 DN3000k10SD Daughter Card I O Interconnects DN5000k10 I O Connector Daughter Card Connections Header J9 Header J10 Header J16 AD 133 U20 W14 FB 40 U11 K32 AB 103 U19 AR9 GND GND GND AD 134 U20 G5 FB 39 U11 K33 AB 102 U19 AT9 3 AD 131 U20 V14 FB 38 U11 G31 AB 101 U19 AP8 PAN 2 AD 132 U20 F5 FB 37 U11 J32 AB 100 U19 AR8 PANX 11 AD 129 U20 U14 FB 123 U11 F34 AB 99 U19 AT8 1 5 V 1 5 V 1 5 V 1 PANX 10 AD 130 U20 E3 FB 124 U11 F35 AB U19 AP7 PANX 7 AD 125 U20 R14 FB 121 U11 M25 AB U19 AR7 PANX 6 AD 126 U20 D2 FB 122 U11 N26 AB U19 AT7 PANX 5 AD 127 U20 T14 FB 119 U11 H27 AB U19 AT6 PANX 4 AD 128 U20 C2 FB 120 U11 M26 AB U19 AT5 MB 156 U11 AV8 AD 84 U19 AV33 1 5 V 1 5 V MB 154 U11 AW6 AB 174 U19 AP33 3 3 V 3 3 V DCLK 6 DCLK 5 GND GND ECLK 1 i vI N e e e e MB 153 U11 AW5 AB 173 U19 AR33 e 2 e e e P2N 5 AD 57 U20 V10 FB 149 U11 AH25 U19 AU33 P2N 4 AD 58 U20 AA10 FB 148 U11 AH26 U19 AW32 P2NX 11 AD 59 U20 AB10 FB 147 U11 AG25 U19 AV32 P2NX 10 AD 60 U20 AC10 FB 146 U11 AG26 U19 AU32 P2NX 9 AD 61 U20 AD10 FB 145 U11 AF25 U19 A
51. 1 DN5000k10 Power Distribution The DN5000k10 when plugged into a PCI slot has the following different power rails e 45V 433V DN5000k10 User s Manual 6 1 Power Supplies and Power Distribution 3 3 V Power 41 5 V Power 6 2 15 V 12V 412V The power rails 3 3 V and 1 5 V are created using a switching regulator with 5 V as the input 3 3 V from the PCI fingers is not used U7 is for 3 3 V and is for 41 5 V Heat is not an issue with this style of switching regulator Each regulator should be able to supply the minimum 10 A of current without strain The most demanding application of the DN5000k10 should fit within the 10 A budget on these two power rails The specification for the 3 3 V power is shown in Table 6 1 The 43 3 V supply is used by the following components on the DN5000k10 Stratix FPGA I O 011 U12 U15 U19 020 Roboclocks U14 U16 2 Clock buffers U13 U17 CPLD U9 Microprocessor U8 Microprocessor SRAM U1 4 SSRAMs U18 U21 U22 U23 SDRAM DIMM J19 3 Oscillators X1 X2 We do run 43 3 V a little hot At worst case for all components the 3 3 V power supply should never fall below 3 30 V Table 6 1 Specification for 3 3 V Power Voltage Current The specification for the 1 5 V power is shown in Table 6 2 The 41 5 V supply is used by the following component on the DN5000k10 Stratix FPGA V amp 4INT U11 U12 U15 U19 U20 We also ru
52. 1 to 2 2 PCI 3 1 to 3 7 bus 3 1 bux 2 9 capability 3 6 capability header 3 6 connector 3 1 4 16 6 1 6 4 DN5000k10 User s Manual Index controller 3 1 debug 9 1 edge connector 3 3 fingers 6 2 6 4 FPGA pin connections 3 2 JTAG Signals 3 4 present signals 3 5 slot 2 2 3 1 6 1 6 3 specification 3 1 3 4 6 4 Specifications 1 2 specifications 3 1 target design 2 2 PCI Clock 2 1 PCI Menu 9 6 to 9 7 PCI CLK 4 16 to 4 17 PCI X 3 1 capability 3 6 to 3 7 capability header 3 6 component interface 2 9 controller 3 1 edge connector 3 3 present signals 3 5 slot 2 2 Specifications 1 2 PCIXCAP 3 6 to 3 7 PCLK See PCI CLK PECL 4 6 4 13 PLL 4 1 4 7 4 11 4 16 to 4 17 PLL1A 4 3 to 4 4 4 10 4 17 PLL1B 4 13 PLL1B_N 4 10 PLL1B_PRE 4 3 PLL1BN 4 13 PLL1BN PRE 4 3 to 4 4 PLL2B 4 13 to 4 14 PLL2B N 4 10 PLL2B PRE 4 3 PLL2BN 4 4 4 13 to 4 14 PLL2BN PRE 4 3 to 4 4 PLLSEL2 4 10 PME polarity 4 15 power 2 13 2 22 2 24 3 1 3 4 to 3 5 6 1 7 4 9 1 power connector 2 1 power distribution 6 1 to 6 4 power management 1 2 Power Management Enable See PME power rails 6 1 to 6 4 power rating 7 5 power supply 5 12 6 1 to 6 4 7 4 to 7 5 8 1 power switch 9 9 I 3 Index Index Continued power up 8 1 9 1 prototyping boards 7 1 PWB 1 1 2 1 to 2 3 2 17 2 25 3 1 Q Quartus 2 20 R R W 5 10 RB C F F 4 10 4 13 reference design 2 18 2 22 9 6 regulator 2 1 3 1 6 2 reset 2 5 2 14 8 1 to 8 2 res
53. 11 AP19 AB 159 U19 AP28 P3N 68 AD 92 U20 U12 FB 28 U11 AF31 AB 158 U19 AR28 P3N 67 AD 97 U20 AC12 FB 29 U11 AG32 AB 157 U19 AT28 P3N 66 AD 91 U20 T13 FB 27 U11 AF32 AB 156 U19 AP27 P3N 63 AD 96 U20 AB13 FB 25 U11 AE32 AB 155 U19 AR27 P3N 62 AD 90 020 712 26 U11 AE31 AB 154 U19 AT27 P3N 57 AD 95 U20 W13 FB 24 U11 AD31 AB 153 U19 AP26 GND GND GND GND P3N 56 AD 94 U20 V13 FB 13 U11 U32 AB 142 U19 AT23 P3N 55 AD 89 U20 R13 FB 12 011 731 141 U19 AP22 P3N 54 AD 87 U20 P13 FB 11 011 732 140 U19 AR22 P3N 49 AD 88 U20 R12 FB 10 U11 R31 AB 139 U19 AN22 P3N 48 AD 86 U20 P12 FB U11 R32 AB 138 U19 AT21 P3N 47 AD 85 U20 N13 FB U11 P31 AB 137 U19 AN18 P3N 46 AD 84 U20 N12 FB U11 P32 AB 136 U12 AT19 ul N P3N 43 vI N AD 83 U20 M13 FB U11 N31 AB 135 U19 AT20 UJ P3N 42 R M ui Ww ui ui AD 82 U20 M12 wW U11 N32 AB 134 U19 AP19 P3N39 AD 81 U20 K16 U11 M31 AB 133 U12 AT20 e e e a a P3N 38 AD 79 U20 K13 U11 M32 AB 132 U12 AT21 DN5000k10 User s Manual 7 9 Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors Table 7 2 DN3000k10SD Daughter Card I O Interconnects DN5000k10 I O Connector Daughter Card Connections Header J9 Header J10 Header J16 P3N 35 AD 80
54. 3 Flip Flops and 2 5 Embedded 2 6 Multipliers u kus si 2 6 VO ISSUES ke eee es 2 9 Bitstream Encryptions 2 9 pP and FPGA Configuration 2 10 The uP Some Details 2 10 J6 Unused pP Connections 2 11 ATmega128L JTAG Interface 2 12 Programming the ATmega128L U8 2 13 Detailed Instructions 2 13 CPLD EPM3256A 2 15 Some Miscellaneous Notes on the CPLD 2 17 Notes on Header J7 2 17 Fast Passive Parallel Configuration Instructions 2 18 Creating RBF Files for Fast Passive Parallel 2 18 Setting up the Serial Port 03 RS232 Port 2 19 Creating Main Configuration File main txt 2 20 Starting Fast Passive Parallel Configuration 2 22 Description of Main Menu Options 2 23 SmartMedia 2 24 Synthesis and Emulation Issues 2 26 Synthesis 2 26 DN5000k10 User s Manual iii Chapter3 PCI eua Mov 3 1 PCI Mechanical Specifications 3 1 Some Notes on the DN5000k10 and PCI PCI X 3 1 JP1 Present Signals for PCI PCI X 3 5
55. 34 mim mia O89 3 mum C40 C42 s Figure 2 11 Location of J4 on the DN5000k10 The DINI Group DN5000k10 User s Manual DN5000k10 Features Overview and General Description Table 2 1 Signals and Connections to J4 JTAG Cable J4 Signal Name VCC 3 3 V GND JTAG CPLD TCK JTAG_CPLD_TDO JTAG_CPLD_TDI JTAG CPLD TMS Some Miscellaneous Notes on the CPLD X1 is a 48 MHz oscillator This part is soldered down to the PWB and is not intended to be user configurable The 48 MHz is divided down to 8 MHz in the CPLD to provide the clock for the ATmega128L uP The processor clock signal is labeled CPUCLK and BCPUCLK on the schematic The 48 MHz is used directly for the state machines in the CPLD for control ling the interface to the SmartMedia card The frequency of 48 MHz is interesting because it is the closest frequency to 50 MHz that can be divided by an integer to get 8 MHz The frequency 50 MHz is the fastest that the Altera Stratix parts can be configured with SelectMap without wait states So FPGA configuration using Fast Passive Parallel occurs at very nearly the fastest theoretical speed Serial and JTAG configuration of the Stratix FPGA are back off positions only that is why those signals are connected to the CPLD Fast Passive Parallel is the quickest configuration method but we wanted to provide the user as many options as possible If you want to use 100 of the CPLD and uP for your own purposes y
56. 4 lt 55 56 57 58 59 lt T 60 61 62 63 C FB 63 65 4 FB 66 n FB 67 FB 68 lt lt 69 70 71 h FBI 72 73 74 FB 75 SSRAM FB U22 SAO SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 expansion Suld SsoJppy ADV ADSP ADSC BWA BWB BWC BWD BWE GW MODE CE OE ZZ 10 S 5 5 a EE FB 1 FB 2 FB 3 FB 4 FB 5 FB 6 FB 7 FB 8 FB 9 FB 10 FB 11 12 o FB 13 FB 14 FB 15 16 FB 17 FB 18 FB 19 lt s FB 129 h 4 20 lt 21 lt FB 22 lt FB 23 lt 24 lt 25 lt 26 lt T FB 27 lt 28 lt T 29 lt 32 40 Figure 5 2 SSRAM FB U22 Bus Signals DN5000k10 User s Manual Memories FPGA B U19 Memories FPGA A U12 L32 K32 M32 M31
57. 4 9 1 9 6 9 13 to 9 14 configuration 2 1 2 3 2 10 2 14 to 2 15 2 17 to 2 18 2 20 to 2 24 3 4 8 1 interconnect block diagram 5 2 FPGA A 2 21 8 4 FPGA B 2 21 8 4 FPGA C 2 3 FPGA D 2 15 2 21 5 13 8 4 FPGA E 2 21 8 4 FPGA F 2 21 to 2 22 3 4 4 16 to 4 17 8 4 9 14 FPGA C 2 3 frequency select 4 10 FS 4 10 to 4 12 4 14 G GW 5 10 H HyperTerminal 2 14 2 20 impedance 2 9 input clock select 4 10 interconnect 2 1 5 2 7 8 9 2 INV1 4 14 INV2 4 10 4 14 J JTAG 2 2 2 10 2 12 to 2 13 2 17 to 2 18 2 24 3 4 configuration 2 17 to 2 18 interface 2 2 2 12 to 2 13 jumper settings 2 17 programming 2 18 2 24 signals 3 4 The DINI Group Index Continued L LD 5 10 LED 2 23 7 4 8 3 logic analyzer 2 1 to 2 2 2 18 LTC1326 8 1 LUT 2 5 LVCMOS33 2 9 LVDS 7 1 7 6 LVPECL 4 1 4 13 M M66EN 3 5 3 7 main configuration file 2 20 main configuration file See main txt main txt 2 18 2 20 to 2 24 8 1 MDR 7 6 memories 2 2 2 26 5 1 to 5 13 9 13 to 9 14 microprocessor 2 1 2 3 2 10 2 15 6 2 MODE 4 10 multiplexing 2 1 5 10 multiplication 4 11 multiplier 2 1 2 5 to 2 6 2 26 4 11 9 2 9 6 multiplier blocks 2 5 multiplier logic 2 8 O oscillator 2 1 2 17 4 1 4 3 to 4 4 4 7 4 11 4 14 to 4 15 6 2 oscilloscope 7 1 9 8 9 10 9 13 to 9 14 output divider function 4 10 4 12 output mode 4 10 output phase function 4 10 output enable 7 7 P pattern generator 2
58. 6 AB 168 U19 AP31 2 5 ADIO U20 AL14 FB 137 U11 AR34 AB 167 U19 AR31 P2NX 4 AD 115 U20 AM12 FB 136 U11 AP34 AB 166 U19 AT31 P2NX 1 AD 114 U20 AL13 FB 36 U11 AV36 AB 165 U19 AP30 P2NX 0 AD 112 U20 AK13 FB 35 U11 AU38 AB 164 U19 AR30 P3NX 9 AD 111 U20 AK12 FB 34 U11 AK32 AB 163 U19 AT30 GND GND GND GND P3NX 8 AD 110 U20 AA13 AF 252 U11 AR19 AB 162 U19 AP29 P3NX 5 AD 109 U20 AA12 FB 33 U11 AJ32 AB 161 U19 AR29 P3NX 4 AD 108 U20 AH13 AF 161 U11 AT19 AB 160 U19 AT29 P3N 89 AD 107 U20 AH12 AF 40 U11 AP19 AB 159 U19 AP28 7 8 The DINI Group Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors Table 7 2 DN3000k10SD Daughter Card I O Interconnects DN5000k10 I O Connector Daughter Card Connections Header J9 Header J10 Header J16 P3N 88 AD 106 U20 AG13 FB 28 U11 AF31 AB 158 U19 AR28 P3N 87 AD 105 U20 AG12 FB 29 U11 AG32 AB 157 U19 AT28 P3N 86 AD 104 U20 AF13 FB 27 U11 AF32 AB 156 U19 AP27 P3N 83 AD 103 U20 AF12 FB 25 U11 A32 AB 155 U19 AR27 P3N 82 AD 102 U20 AE13 FB 26 U11 AE31 AB 154 U19 AT27 P3N 77 AD 101 U20 AE12 FB 24 U11 AD31 AB 153 U19 AP26 GND GND GND GND P3N 76 AD 100 U20 AD13 AF 252 U11 AR19 AB 162 U19 AP29 P3N 75 AD 99 U20 AD12 FB 33 U11 AJ32 AB 161 U19 AR29 P3N 74 AD 93 U20 U13 AF 161 U11 AT19 AB 160 U19 AT29 P3N 69 AD 98 U20 AC13 AF 40 U
59. 8 if a card is not installed WARNING Do NOT format a SmartMedia card using the default Windows format program All Smart Media cards come preformatted from the factory and files can be deleted from the card when they are no longer needed If for some reason you absolutely need to format a SmartMedia card you must use the format program that is included in the FlashPath Smart Media floppy adapter software DN5000k10 User s Manual 2 25 DN5000k10 Features Overview and General Description Synthesis and Emulation Issues 2 26 Synthesis Notes The QuartusllTM software from Altera is able to synthesize directly from Verilog or VHDL code However third party synthesis tools provide an advantage to create a memory block or multiplier all you need to do is describe them functionally and the tool will infer the appropriate DSP and RAM megafunctions for Quartus to place and route On the other hand if you are using Quartus to synthesize and you try to infer an M RAM block using a functional description Quartus will attempt to route 200 000 LEs as a memory array So if you don t have any other synthesis tool you will need to become familiar with Quartus megafunctions We have tried the following tools for synthesis Synplicity Synplify http www synplicity com Synopsys FPGA Express http www synopsys com Synopsys FPGA Compiler II Exemplar LeonardoSpectrum http www exemplar com products leonardospectrum htm
60. A AB 32 lt AB 33 34 v 35 AB 36 AB 37 AB 38 39 40 41 42 43 AB 44 AB 45 46 lt 47 48 49 50 51 52 lt 53 54 55 56 57 AB 58 59 lt AB 60 lt 61 lt 62 lt 63 lt r 64 lt AB 65 lt AB 66 lt M 67 lt AB 68 AU25 AW24 AV24 AU24 AW23 AV23 AU23 AW22 AT2 AU22 AW21 AV21 AU21 AW20 AV20 AU20 AT3 AV19 AU19 ATA AV18 AU18 AW17 AV17 AU17 AW16 AV16 AU16 AV15 AU15 AW14 AV14 AU14 AV13 AU13 AW12 SSRAM AB U21 SAO SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 expansion Lo ssoippy ADV ADSP ADSC BWA BWB BWC BWD BWE GW MODE CE OE ZZ JO3u023 D1 D2 suld ejeq EE a S lt y AB 70 lt aB 20 D aB 21 lt aB 22 4 AB 23 U lt 24
61. AB9 FB 133 U11 V29 U19 AW16 P3N 21 AD 21 U20 AB8 FB 132 U11 V26 AB U19 AV16 P3N 20 AD 20 U20 AA9 FB 131 U11 P26 AB U19 AU16 P3N 17 AD 19 U20 V11 FB 96 U11 AC28 AB U19 AU15 P3N 16 AD 18 U20 V9 FB 95 U11 AB27 AB U19 AW14 P3N 13 AD 17 U20 V8 FB 94 U11 AB28 AB 176 U19 AT35 P3N 12 AD 16 U20 U9 FB 93 U11 W27 AB 175 U19 AT34 P3N 11 AD 15 U20 U8 FB 92 U11 V27 AB U19 AV13 P3N 10 AD 14 U20 T9 FB 91 U11 V28 AB U19 AU13 P3N 5 AD 13 U20 T8 FB 90 U11 U27 U19 AW12 D GND GND AD 12 FB 89 U11 U28 U19 AV12 AD 11 FB 88 U11 T27 U19 AU12 AD 10 FB 87 011 728 U19 AW11 DN5000k10 User s Manual 7 13 Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors Table 7 2 DN3000k10SD Daughter Card I O Interconnects DN5000k10 I O Connector Daughter Card Connections Header J9 Header J10 Header J16 PAN 25 AD 8 U20 N9 FB 86 U11 R27 U19 AV11 PAN 24 AD 7 U20 N8 FB 85 U11 R28 U19 AU11 P4N23 AD 45 U20 M4 FB 84 U11 P27 U19 AW10 PAN 22 AD 44 U20 M6 FB 83 U11 P28 U19 AV10 PAN 17 AD 43 U20 K11 FB 82 U11 N27 U19 AU10 PAN 16 AD 42 U20 K8 FB 81 U11 N28 U19 AW9 PAN 15 AD 41 U20 11 FB 80 U11 M27 U19 AV9 GND GND GND PAN 14 AD 40 U20 J10 FB 79 U11 M28 U19 AU9 PAN 9 AD 123 U20 P14 FB 78 U11 K27 U19 AW8 PAN 8 AD 124 U20 P15 FB 77 U11 L34 U19 AV8 P4N AD 121 U20 N14 FB 76 U11 K28 U19 AU8 P4N AD 122 U20 N15 FB 116 U11 J26
62. AD 140 U20 AD14 FB 152 U11 AK26 U19 AW23 ul GND GND GND e 2 P3N 64 AD 139 U20 AP6 FB 115 U11 AM27 gt U19 AV23 P3N 61 AD 138 U20 AC14 FB 114 U11 AM28 gt U19 AU23 P3N 60 AD 137 U20 AN6 FB 113 U11 AL27 U19 AW22 P3N 59 AD 136 U20 AB14 FB 112 U11 AL28 U12 AV18 P3N 58 AD 135 U20 AA14 FB 111 U11 AK27 U19 AU22 P3N 53 AD 37 U20 AM9 FB 110 U11 AK28 U19 AU22 7 12 The DINI Group Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors Table 7 2 DN3000k10SD Daughter Card I O Interconnects DN5000k10 I O Connector Daughter Card Connections Header J9 Header J10 Header J16 P3N 52 AD 36 U20 AK7 FB 109 U11 AK25 U19 AV21 P3N 51 AD 35 U20 AL8 FB 108 U11 AJ24 U19 AU21 P3N 50 AF 77 U11 F36 FB 107 U11 AH27 U19 AW20 P3N 45 AD 34 U20 AK8 FB 106 U11 AH28 U19 AV20 e GND GND GND P3N 44 AD 33 U20 AA11 FB 105 U11 AG27 U19 AU20 P3N 41 AF 78 U11 G36 FB 104 U11 AG28 U12 AW21 P3N 40 AF 79 U11 H36 FB 103 U11 AF27 U19 AV19 P3N 37 AD 28 U20 AG8 FB 102 U11 AF28 U19 AU19 P3N 36 AD 29 U20 AG9 FB 101 U11 AE27 U12 AW22 P3N 33 AD 27 U20 AF9 FB 100 U11 AE28 U19 AV18 P3N 32 AD 26 U20 AD9 FB 99 U11 AD27 U12 AU22 P3N 31 AD 25 U20 AD8 FB 98 U11 AD28 U19 AW17 P3N 30 AD 24 U20 AC9 FB 97 U11 AC27 U19 AV17 P3N 25 AD 23 U20 AC3 FB 134 U11 W26 U19 AU17 GND GND GND P3N 24 AD 22 U20
63. AM 7 1 9 13 to 9 14 board termination voltage 2 9 Bridges2silicon 2 18 BUFINA 4 3 to 4 4 4 6 BUFINB 4 3 to 4 4 4 7 bus bars 8 1 8 4 BWE 5 10 BWx 5 10 C carry chains 2 5 CCLK 4 10 4 13 to 4 14 4 17 7 8 CE 5 10 CE2 5 10 Certify TDM 2 1 CLKOUT 4 1 4 3 to 4 4 clock 2 9 4 1 4 11 clock buffer 4 1 4 7 4 13 6 2 clock distribution 4 1 to 4 2 4 4 clock divider function 4 11 clock division 4 11 DN5000k10 User s Manual Index clock enable 2 5 clock frequency 3 1 4 1 clock frequency multipliers 4 11 clock grid 2 16 4 1 4 3 to 4 4 4 6 4 13 clock inputs 4 3 to 4 4 4 6 4 13 to 4 14 4 16 clock menu 9 6 clock multiplication 4 11 clock multiplication mechanism 4 11 clock output 2 9 4 1 4 10 to 4 11 4 16 to 4 17 clock signals 2 17 4 1 4 3 4 13 to 4 14 4 16 to 4 17 7 6 clock skew 4 11 to 4 13 CLOCKA 4 3 to 4 4 CLOCKB 4 3 to 4 4 4 7 configuration uP 2 10 uP and FPGA 2 10 clock grid 4 4 4 16 FPGA 2 1 2 3 2 10 2 17 2 23 3 4 8 1 2 17 to 2 18 SDRAM 5 12 serial 2 17 SmartMedia 2 1 2 3 2 20 2 24 8 3 stand alone 6 3 via Fast Passive Parallel 2 17 to 2 18 2 22 via Fast passive Parallel 2 1 configuration space 9 2 9 5 9 8 to 9 9 CPLD 2 1 2 3 2 9 to 2 10 2 13 2 15 2 17 2 24 4 1 4 3 to 4 4 6 2 8 1 CPLD TCK 2 17 CPLD TDI 2 17 CPLD TDO 2 17 CPLD TMS 2 17 CPUCLK 2 17 CSF 2 9 2 19 3 1 custom daughter cards 2 2 CY7B993V 4 1 4 11 to 4 12 4 14 D daughter 2 2 dau
64. DN5000k10 Dimensions the PCI Specification The pull up is 1M which should not adversely impact PCI functionality in any way The PCI JTAG signals TDI TDO TCK TMS TRSTZ are not used TDI and TDO are connected together per the PCI Specification to maintain JTAG chain integrity on the motherboard The signals TMS TCK and TRST are left unconnected The Stratix FPGAs are not 5 V tolerant so you must plug the DN5000k10 into a 3 3 V PCI slot Do NOT modify the connector to get the board to fit If you need 5 V to 43 3 V PCI voltage translation get one of our extenders The link is http www dinigroup com products pciextender html The FPGA is volatile meaning it loses its brains when power is off The SmartMedia method takes about 1 second to configure an EP1580 after power is stable It takes about 5 seconds to configure five EP1580s It is likely that FPGA F will finish the configuration process before RST is deas serted If your system has an unusually fast RST it is possible that the FPGA will not be configured when RST deasserts A RST that deasserts before the FPGA has finished cannot properly configure the PCI PCI X mode latch The signal 3 3Vaux is not connected The signals INTBZ INTCZ and INTD are not connected The DINI Group PCI JP1 Present Signals for PCI PCI X The present signals indicate to the system board whether an add in card is physically present in the slot and if one is present the t
65. E IN USA E J 3 FPGA JTAG 115 DATAO TOI b iu IS FPGA F FPOA_TDF FPGA_TDIA FPGA_TDIB FPGA_TDID FPGA_TDIE PCKCAP E Sy m jl VARI e TP amp SMART MEDIA mum RID CM mm E 3 Figure 2 12 J3 Serial Port Locations DN5000k10 User s Manual 2 19 DN5000k10 Features Overview and General Description A female to female RS232 cable is provided with the DN5000k10 This cable will attach directly to the RS232 port of a PC We get our cables from Jameco http www jameco com The part number is 132345 Male to female extension cables are part number 25700 The RS232 port is configured with the following parameters Bits per second 9600 Data bits 8 Parity None Stop Bits 1 FLow control None Terminal Emulation VT100 We use the Windows based program HyperTerminal Hypertrm exe The configuration file DN5000k10 ht is supplied on the CD ROM or can be downloaded from our web page Users have the option of connecting the serial port if they wish to see any messages during the configuration process NOTE It is NOT mandatory to have the serial port connection in order to configure the FPGA in SelectMAP mode However if an error occurs during the configuration then without a serial port connection the user will not be able to see any error messages In addition without a serial port connection a user cannot select any Main Me
66. ED2 Figure 8 3 DN5000k10 LED Diagram The LEDs have the following functions UP LED3 Lights when the configuration process from the SmartMedia was successful UP LED 2 O These three LEDs have multiple meanings e When all 3 LEDs are blinking then the pP has been repro grammed and is waiting for the user to enter FPGA stuffing DN5000k10 User s Manual 8 3 Reset Schemes LEDs Bus Bars and 200 Pin Connectors Bus Bars information via serial port or there is not a valid SmartMe dia card present and the FPGA has been configured During configuration the combination of LEDs lit tells the user which FPGA is currently being configured UP LED2 UP LED1 UP LEDO off off on FPGA F off on off FPGA A off on on FPGA E on off off FPGA B on off on FPGA D CPLD_LED3 lights when any of the FPGAs are NOT configured CPLD_LED2 lights when reset is asserted PWRRST CPLD LED1 lights when the PLL in Roboclockll 1 is LOCKED CPLD LEDO lights when the PLL in Roboclockll 2 is LOCKED You are free to reprogram the CPLD and or microprocessor to use any or all of the LEDs for your own purposes The two bus bars B1 and B2 are installed to prevent flexing of the PWB and serve no other purpose They are connected quite solidly into the ground plane of the DN5000k10 at every hole and you can use the metal bars to ground test equipment such as oscilloscopes and pattern genera tors Be careful not to sho
67. I Controller Driver v8 Read FPGA revision PCI Menu Memory Menu Flash Menu Clock Menu Dedicated Multiplier Test OO N Q Quit PCI BASE ADDRESS 0 da800000 1 e0000000 2 00000000 3 00000000 4 00000000 5 00000000 Please select option Figure 9 3 AETEST Main Screen Options Read FPGA Revision Display the revision ID of the FPGA We will update the revision ID of the FPGA every time we change the reference design PCI Menu Display the PCI utilities menu Memory Menu Display the Memory Menu Flash Menu Display the Flash Utilities Menu DN2000k10 series only Clock Menu Display the Clock Utilities Menu Dedicated Multiplier Test Execute the multiplier test Q Quit and return to the DOS prompt The selections are sometimes case sensitive so be aware of the status of the CAPS LOCK on your keyboard The base addresses for each of the configured BARs is displayed on all screens You will need these addresses if you want to manually read and write to address locations within the PCI reference design In this example Figure 9 3 above BARO is configured to OxFD800000 and BART is configured to 0xE0000000 BAR 5 2 are not configured so they show up as 0x0 9 6 The DINI Group Utilities PCI Menu AETEST PCI menu is shown in Figure 9 4 ASIC Emulator PCI Controller Driver v8 PCI Device Function Num Ox7F 0x00 S Set PCI Device Number
68. L All VCCO pins are connected to 3 3 V The VREF pins are connected to 1 5 V so the DN5000k10 does not support I O standards that require other values of VREF So the I O standards supported are LVTTL Low Voltage TTL The low voltage TTL or LVTTL standard is a general purpose EIA JESDSA standard for 3 3 V applications that use the LVTTL input buffer and a Push Pull output buffer The standard requires a 3 3 V input and output source voltage Vcco but does not require the use of a reference voltage Vggp or a termination voltage LVCMOS33 3 3 Volt Low Voltage CMOS This standard is an extension of the LVCMOS standard JESD8 5 It is used in general purpose 3 3 V applications The standard requires a 3 3 V input output source voltage Vcco but does not require the use of a refer ence voltage or a termination voltage V77 PCI X Peripheral Component Interface The PCI standard specifies support for 33 MHz 66 MHz and 133 MHz PCI bus applications It uses a LVTTL input buffer and a Push Pull output buffer This standard does not require the use of a reference voltage or a board termination voltage Vr4 however it does require 3 3 V input output source voltage Vcco SSTL 3 class and II SSTL 3 uses a series termination resistor on output signals and a parallel termination resistor on input signals Stratix devices use a VREF of 1 5V to enable the appropriate resistors internally Because
69. LK 9 6 and the SDRAM ECLK 13 10 receive signals To complete this setup a feedback signal must be connected to the PLL in FPGA F Roboclock 2 sends ECLK 15 to the feedback input of FPGA F ECLK 15 needs to be connected to the bin input signal of the PLL Using ECLK 15 as feedback allows the PLL to properly synchronize the DN5000k10 PCI CLK network which completes the setup see Figure 4 9 for a diagram of the PCI PLL circuit The DN5000k10 can be run off any single ended TTL clock signal which is sent to the Roboclocks The ECLK distribution provides the DN5000k10 this flexibility PCI CLK has special implications for DN300k10 PCI operation The DINI Group BCLKOUT and FCLKOUT Header Clocks DCLK 7 R DN5000k10 User s Manual Clocks and Clock Distribution p d ECLK 15 Figure 4 9 PCI CLK PLL Circuit FCLKOUT is assigned to a dedicated clock output pin in the Stratix architec ture and can be used to drive Roboclock 2 see the section DN5000k10 PCI CLK Operation on page 4 16 for details The DN5000K10 differs from previous Dini Group emulator boards because the Stratix architec ture assigns each PLL to specific clock pins In the case of FCLKOUT the only possible source is from PLL5 which has only one possible input PCI CLK So the sole purpose of FCLKOUT is to provide the means to run the whole board with PCI CLK Each header receives a c
70. OW 1tu 1t COL1 COL1 MID MID Oty Oty Oty Oty MID HIGH 1ty 1ty COL2 COL2 HIGH LOW 2ty 2ty 6ty 6ty HIGH MID 3ty 3ty 7ty 7ty HIGH HIGH 4ty 4ty 8ty 8ty The clock skew is equivalent to the skew on DCLK 3 0 or ECLK 11 8 The clock skew is equivalent to the skew on DCLK 7 4 or ECLK 15 12 Differential In addition to LVTTL clock signals the Roboclockll clock buffers can handle LV Differential LVPECL clocks The user can cable in an acceptable differ ential signal to PLL1B and PLL1BN or PLL2B and PLL2BN through the clock grid J13 The signals must obey the specifications given in Table 4 8 Onboard circuitry is available to center the signals about the proper voltage if needed Clocks Table 4 8 LVPECL Input Specifications Description Differential Voltage Highest HIGH Voltage Lowest LOW Voltage Common Mode range crossing voltage The clock input of the Roboclockll can accept a superset of PECL PECL involves a 1 V swing about Vcc 2 The Roboclockll clock input can accept a swing of up to 3 3 V about Vcdu 2 which gives the user another dimension of flexibility DN5000k10 User s Manual 4 13 Clocks and Clock Distribution Useful Notes and Hints The CY7B993V 4V can output LVTTL complementary differential signals too Setting INV1 INV2 LOW wil
71. PCIXCAP Jumpers M66EN and PCIXCAP Encoding Clock Grid Signal Descriptions Header Classification Jumper Definitions Frequency Range Settings Output Divider Settings Time Unit N factor Clock Skew Settings LVPECL Input Specifications Clock OE Pin Jumper Settings Requirements for Non Standard SSRAMs Syncburst and ZBT SSRAM Timing Specification for 43 3 V Power Specification for 41 5 V Power Connector J8 Pins External Power DN3000k10SD Daughter Card I O Interconnects List of Tables The DINI Group Chapter 1 Getting Started The DN5000k10 is sensitive to static electricity so treat the PWB accord ingly The target market for this product is engineers that are familiar with FPGAs and circuit boards so a lecture in ESD really isn t appropriate and wouldn t be read anyway However we have sold some of these units to people who are not as familiar with this issue The following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda org basics part1 cfm The DINI Group Technical Support The following means of technical support are available 1 The DN5000k10 User s Manual This is t
72. PGA F The resulting PLL output can be sent to the Roboclocks via the signal FCLKOUT All of the aforementioned devices receive one of the ECLK clock outputs from Roboclock 2 Consequentially the DN5000k10 can be clocked exclusively by PCI CLK PCI CLK is connected to one of FPGA F s global clock inputs from the PCI connector Then a PLL must be instantiated The PLL will require a minimum of three connections For further information on Stratix PLL operation see the Altera website at http www altera com The Stratix Datasheet ds stx pdf which can be found on the DN5000k10 CD ROM also provide useful information on PLLs PCI CLK must be connected to the INCLK 0 input of the DCM The DCM output EXTCLK 0 will be connected to the output signal FCLKOUT One more connection must be made to the PLL This will come up later in this section The FCLKOUT signal is connected to one of the four input pins on Roboclock 2 FCLKOUT s complementary input is DCLK 7 R FCLKOUT and DCLK 7 R are both single ended TTL inputs When either of them is being used the other one must be left open For complete PCI CLK operation jumper J14 must be unstuffed leaving DCLK 7 R open If set to the default configuration Roboclock 2 will drive a one to one PCI CLK derived clock on its outputs See Roboclock PLL Clock Buffers on page 4 7 for more information Roboclock 2 has 16 clock outputs ECLK 15 0 Each FPGA 4 0 each SSRAM EC
73. S Droits de reproduction BERG ELECTRONICS INC gt ELECTRONICS whatever is not permitted without written authority from the proprietor Property of BERG ELECTRONICS Copyright BERG ELECTRONICS INC All rights strictly reserved or kaba payo ria sof 200 2 930 74 42 1 530 33 78 e 00 160 12 450 61 72 1 080 27 43 975 24 76 2 050 52 07 2 650 67 3 2 290 58 16 1 215 30 86 30 GXT 3 2 950 74 42 1 330 33 78 1 225 31 12 2 550 64 77 3 150 80 01 2 790 70 87 1 465 37 21 1225 31 12 2 550 64 77 3 150 80 01 2 790 70 87 1465 3721 Gxt 404 iso 2430 6172 1 080 27 43 975 24 76 2050 5207 2 650 67 31 2 290 58 16 1 215 30 86 2 420 61 72 1 080 27 43 975 24 76 2 050 52 07 2 650 67 31 2 290 58 16 1 215 30 86 1 225 31 12 2 550 64 77 3 150 80 01 E I BRI cp lx 1 3 CAPS INSTALLED ON CONNECTOR CAPS INSTALLED ON CONNECTOR 965 24 51 30 GXT SUPPLIED LOOSE PIECE 2 790 70 87 1 465 37 21 NOTES 1 uatERILS DIELECTRIC LCP CONTACTS PHOS BRONZE FRAME ZINC ALLOY 3 3 Putine SOLDER TAILS 150 u 3 81um Sa Pb FRAME 150u 3 8tum BRIGHT TIN CONTACTS 30u 76um OVER 50u 1 27um Ni OR 60u 1 52um OVER 75u 1 90um Ni S WHEN CONNECTOR 15 MATED WITH OPPOSITE HALF THE PARALLEL BO
74. SSTL 3 requires parallel termination it is only available on banks 3 4 7 and 8 and on clock output signals CTT CTT uses a parallel termination resistor on input signals with no termina tion resistors on output signals Stratix devices use a VREF of 1 5V to enable the appropriate resistors internally Because CTT requires parallel termination it is only available on I O banks 3 4 7 and 8 and on clock output signals Differential Termination Standards Stratix devices provide several differential I O standards available only in banks 1 2 5 and 6 and on differential clock output signals However the DN5000k10 is not routed for differential signaling so these features are not likely to be very useful Bitstream stratix devices have no special bitstream encryption function The Dini Encryptions Group may be able to assist with scrambling bitfiles to protect IP on the SmartMedia card which would then be descrambled in the programming CPLD Users should be aware however that the bitstream would be DN5000k10 User s Manual 2 9 DN5000k10 Features Overview and General Description unprotected between the CPLD and FPGA so they could still be examined and reverse engineered Our DN3000k10 products use Xilinx FPGAs which can be used to decrypt the bitstream inside the FPGA providing complete design protection If you are interested in this feature please be aware that there are some issues with the Xilinx encryption featur
75. TA 31 0 A vertical or horizontal ellipsis indicates repetitive material that has been omitted X Y Z The use of fn SIGl SIGn in HDL pseudocode frag ment should be interpreted as combinational function of signals SIG1 through SIGn SUM fn A B Cin The prefix 0x or the suffix h indicate hexadecimal notation A read of address 0x00110373 returned 45524943h Fa A t an n an n or a means the signal is active low INT is active low fpga inta nis active low SRAMCS is active low FPGA_GRSTn is active low The DINI Group DN5000k10 Features Overview and General Description Chapter 2 DN5000k10 Features Overview and General Description DN5000k10 Features The DN5000k10 features include 32 64 bit 3 3V PCI PCI X based PWB with up to five Altera Stratix FPGAs FBGA1508 Device availability EP1S80 EP1S60 to follow with slightly reduced features 3 5 million ASIC gates per PWB with EP1S80 LSI standard Embedded Memory Device WO Flip Flops 18 x 18 Multipliers M512 RAM M4K RAM M RAM ener penne L L Fast Easy FPGA configuration via standard SmartMedia FLASH card Microprocessor controlled ATmega128L RS232 port for configuration operation status and control Fastest possible configuration speed via Passive Parallel method e 10 on board linear regulator for
76. U19 AW7 PAN 1 AD 119 U20 M14 FB 117 U11 K26 U19 AV7 PAN O AD 120 U20 M15 FB 118 U11 H34 U19 AU7 PANX 13 AF 1 U11 E39 AF 38 U11 AN30 U19 AW6 PANX 12 AF 2 U11 E38 AF 39 U11 AN24 U19 AV6 P4NX AF 3 U11 F39 AF 37 U11 AM31 U19 AU6 GND GND AF 4 U11 F38 AF 83 U11 34 U19 AW5 AF 5 U11 F37 AF 80 U11 H35 U19 AV5 AF 6 U11 G39 AF 82 U11 J35 U19 AU5 AF 7 U11 G38 AB 1 U19 AV4 AF 8 U11 G37 AF 81 U11 J36 U19 AU4 7 14 The DINI Group Reset Schemes LEDs Bus Bars and 200 Pin Connectors Chapter 8 Reset Schemes LEDs Bus Bars and 200 Pin Connectors Reset Schemes A LTC1326 chip from Linear Technology controls reset functionality for the DN5000k10 Figure 8 1 shows the distribution of the reset signal PWRRST In addition to controlling the reset the power supplies rails 5 V 3 3 V and 41 5 V are threshold detected by the LTC1326 Undervoltage condi tions will case the assertion of the reset signal The LTC1326 has a push button Momentarily depressing this button causes a 200 ms reset pulse on the signal PWRRST If the push button is depressed for 2 seconds and held PWRRST is asserted continuously LED5 when lit means that reset is asserted so if you press and hold S1 you should see LED5 illuminate after a few seconds If LED5 illuminates for any reason during normal operation this indicates that PWRRST is active and that something is wrong Note that if you press S1
77. U20 K15 FB 2 U11 K25 AB 131 U19 AP18 P3N 34 AD 77 U20 13 FB 1 011 132 130 U19 AR18 P3N 29 AD 78 U20 K12 FB 129 U11 P24 AB 129 U19 AT18 P3N 28 AD 76 U20 J12 FB 130 U11 U26 AB 128 U19 AM18 P3N 27 AD 55 U20 T11 FB 127 U11 J27 AB 127 U19 AR17 P3N 26 AD 75 U20 H12 FB 128 011 726 126 U19 AT17 P3N 23 AD 54 U20 T10 FB 125 U11 J29 AB 125 U19 AP16 P3N 22 AD 116 U20 K14 FB 126 U11 R26 AB 124 U19 AR16 P3N 19 AD 53 U20 N16 FB 60 U11 AD29 AB 123 U19 AT16 GND GND GND GND P3N 18 AD 52 U20 R10 FB 59 U11 AD30 AB 122 U19 AP15 P3N 15 AD 56 U20 U10 FB 58 U11 AC30 AB 121 U19 AR15 P3N 14 AD 51 U20 R7 FB 57 U11 AB30 AB 120 U19 AT15 P3N 9 AD 117 U20 G7 FB 56 U11 W30 AB 119 U19 AP14 P3N 8 AD 50 U20 P10 FB 55 U11 V30 AB 118 U19 AR14 P3N AD 118 U20 G6 FB 54 U11 U30 AB 117 U19 AT14 P3N AD 49 U20 P7 FB 53 011 729 116 U19 AP13 P3N AD 48 U20 N10 FB 52 U11 T30 AB 115 U19 AR13 P3N 2 AD 9 U20 P8 FB 51 U11 U29 AB 114 U19 AT13 P4N27 AD 47 U20 N7 FB 50 U11 R30 AB 113 U19 AP12 GND GND GND GND PAN 26 AD 46 U20 M10 FB 49 U11 R33 AB 112 U19 AR12 PAN 21 AD U20 M9 FB 48 U11 P30 AB 111 U19 AT12 PAN 20 AD U20 H13 FB 47 U11 N24 AB 110 U19 AP11 PAN 19 AD U20 M8 FB 46 U11 N30 AB 109 U19 AR11 PAN 18 AD U20 L8 FB 45 U11 N33 AB 108 U19 AT11 PAN 13 AD U20 J8 FB 44 U11 M30 AB 107 U19 AP10 PAN 12 AD U20 H9 FB 43 U11 28 AB 106 U19 AR10 PAN 11 AD 39 U20 H11 FB 42 U11 K29 AB 1
78. VERSION 0 61 October 8 2003 The DINI Group Ihe TUNE Group DN5000k10 User s Manual Version 0 61 October 8 2003 The DINI Group DN5000k10 User s Manual The UNI Group The information contained within this manual and the accompanying software program are protected by copyright all rights are reserved by the DINI Group Therewith the DINI group reserves a the right to make periodic modifications to this project without obligation to notify any person or entity of such revision Copying duplicating selling or otherwise distributing any part of this product without the prior written consent of an authorized representative of the DINI Group is prohibited DN5000K10 DN3000k10SD and DNPCIEXT S3 are trademarks of the DINI Group 1010 Pearl Street Suite 6 La Jolla CA 92037 5165 www dinigroup com info dinigroup com 858 454 3419 FAX 858 454 1728 Copyright 2003 The DINI Group All Rights Reserved The DINI Group Table of Contents Chapter 1 Getting Started The DINI Group Technical Support 1 1 Relevant Information 1 1 Conventions IM 1 3 Chapter 2 DN5000k10 Features Overview and General De scription DN5000k10 Features 2 1 DN5000k10 Description 2 2 Easy Configuration via SmartMedia 2 3 FPGA Stratix U11 U12 U15 U19 U20 F A E B D 2
79. W31 P2NX 8 AD 62 U20 AD11 FB 144 U11 AF26 U19 AV31 DN5000k10 User s Manual 7 11 Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors Table 7 2 DN3000k10SD Daughter Card I O Interconnects DN5000k10 I O Connector Daughter Card Connections Header J9 Header J10 Header J16 P2NX 3 AD 63 U20 AE8 FB 143 U11 AE26 U19 AU31 gt N GND GND GND e P2NX 2 AD 64 U20 AE10 FB 142 U11 AD26 gt U19 AW30 P3NX 11 AD 65 U20 AF8 FB 75 U11 AV37 U19 AV30 P3NX 10 AD 66 U20 AF10 FB 74 U11 AL29 U19 AU30 P3NX AD 67 U20 AG10 FB 73 U11 AL30 U19 AW29 P3NX AD 68 U20 AC11 FB 72 U11 AK29 U19 AV29 P3NX AD 69 U20 AH10 FB 71 U11 AT36 U19 AU29 P3NX AD 70 U20 AB11 FB 70 U11 AR36 U19 AW28 P3NX AD 71 U20 AE14 FB 69 U11 AR35 U19 AV28 P3NX AD 72 U20 AG16 FB 68 U11 AJ33 U19 AU28 P3N 85 AD 73 U20 AK11 FB 67 U11 AH30 U19 AV27 GND GND GND P3N 84 AD 74 U20 AL12 FB 66 U11 AB29 U19 AU27 P3N 81 AD 113 U20 AM13 FB 65 U11 AG30 U19 AW26 P3N 80 AD 144 U20 AF14 FB 64 U11 AC29 U19 AV26 P3N 79 AD 145 U20 AF15 FB 63 U11 AF30 U19 AU26 P3N 78 AD 146 U20 AG14 FB 62 U11 AF33 U19 AV25 P3N 73 AD 147 U20 AG15 FB 61 U11 AE30 U19 AU25 P3N 72 AD 143 U20 AR5 FB 151 U11 AM25 U19 AW24 P3N 71 AD 142 U20 AR4 FB 150 U11 AL25 U19 AV24 P3N 70 AD 141 U20 AR6 FB 0 U11 AL26 gt U19 AU24 P3N 65
80. ach FPGA location that contains an FPGA If you enter the wrong number of FPGAs or the wrong types or locations you will need to reprogram the processor and follow these steps again If you enter the same location twice you ll probably need to start again also The processor and the CPLD are now ready to configure the FPGA s Please see the section titled Starting Fast Passive Parallel Configura tion on page 2 22 for further instructions Some non volatile logic is needed to handle the counters and state machines associated with the high speed interface to the SmartMedia card We used an EPM3256A CPLD from Altera for this function The datasheet is the CD ROM and is titled epm3256a pdf Approximately 90 of the resources of this device are utilized so 10 are available for your own purposes The Verilog source for the CPLD is provided on the CD ROM The file name is CPLD V The CPLD performs the following functions e Interface to ATmega128L uP and SRAM Clock Output to pP Data Lower Address UPAD 7 0 Upper Address UPPADDR 15 8 Control Signals UP ALE UP RDn UP WRn SRAM Select SRAM CSn e Data Retrieval from SmartMedia Card Data Bus SM D 7 0 Control SM CLE SM ALE SM WEn SM WPn SM CEn SM REn SM RDYBUSYn e Configuration and Clock Status Reporting CPLD LED 3 0 ROBO LOCK1 ROBO LOCK2 e Control of FPGA Parallel Configuration names with the letter X indicate one signa
81. an be accessed through header J5 of the DN5000k10 see Figure 2 9 2 12 The DINI Group Programming the ATmega128L U8 DN5000k10 User s Manual DN5000k10 Features Overview and General Description A cable used to reprogram the ATmega128L is shipped with the DN5000k10 You will need to reprogram the ATmega128L if we update the code or you intend to use the processor for your own application J2 is used for this purpose Figure 2 10 illustrates J2 3 3V PWRRSTn Figure 2 10 J2 Schematic Detailed Instructions 1 Download the latest update for the processor and CPLD at www dini group com fileuP CPLD zip 2 You will first need to reprogram the CPLD Please see CPLD EPM3256A page 2 15 for instructions use the file DNk10S CPLD jed that can be found in the downloaded zip file 3 Next you will program the processor ATmetga128L Connect the AVR cable that was shipped with the DN5000k10 to header J2 with the red purple wire on the cable connected to pin 1 and connect the other end to the serial port of your PC 4 In order to program the processor you will need to install AVR Studio that is included on the Atmel CD that was shipped with the DN5000k10 This software can also be downloaded at www atmel com 5 From the Windows START menu choose PROGRAMS gt Atmel AVR Stu dio x xx where x xx is the version number 6 Once AVR Studio is open select TOOLS gt STK500 AVRISP JTAG ICE and a new window
82. and ECLK 3 2 will be complementary FBDIS 2 1 Feedback Disable When HIGH feedback is disabled When LOW feedback is enabled RB C F F 1 0 3 Level Output Phase Function Each pair controls the phase function of the respective group of outputs See Clock Skew on page 4 12 for more information C F DS 1 0 3 Level Output Divider Function Each pair controls the divider function of the respective group of outputs See Clock Division on page 4 11 for more information FS 2 1 Frequency Select The input specifies the operating range of the nominal frequency from See General Control on page 4 11 for more information FBF0 2 1 Feedback Output Phase Function The input controls the phase function of the feedback outputs See Feedback and Clock Multiplication on page 4 11 for more information FBDS 1 0 2 1 Feedback Output Divider Function Each pair controls the divider function of the feedback outputs See Feedback and Clock Multiplication on page 4 11 for more information 4 10 The DINI Group Clocks and Clock Distribution General FS 2 1 is a 3 Level input which determines the allowable range for the Control frequency fyoy of the device Depending on the chip grade the PLL can operate between 12 100 MHz or 24 200 MHz The actual fyow frequency can be determined by setting all jumpers to their defaults Thus will be seen on all of the divide by one
83. can also accept a 5X2 ribbon cable This cable can provide input clocks to both of the Roboclockil s and one of the 3807 buffers The FCT3807 clock buffer provides a high speed 1 to 10 buffer with low skew 0 35 ns allowing clocks A ACLK 9 0 and B BCLK 9 0 to be distributed point to point The two Roboclockll PLL clock buffers U14 and U16 offer functional control of clock frequency and skew among other things They are configured via header arrays J11 J12 J15 and J18 The DN5000k10 comes from the factory stuffed with CY7B994V which can operate at frequencies from 24 MHz to 200 MHz They can also be stuffed with CY7B993V which operate from 12 MHz to 100 MHz Note Output frequency can be as low as 1 MHz depending on the operating frequency see below for details Each chip has 16 output clocks along with 2 feedback output clocks Two sets of eight output clocks are jumper selectable for each chip The feedback clocks are controlled separately The PLL clock buffers can accept either 3 3 V LVTTL or LV Differential LVPECL reference inputs The devices can operate at up to 12x the input frequency while the output clocks can be divided up to 12x the operating DN5000k10 User s Manual 4 1 Clocks and Clock Distribution ACLK 8 BCLK 8 ACLK BCLK CCLK DCLK ECLK ACLK BCLK CCLK DCLK ECLK 4 2 CLOCKB CCLK 7 0 Roboclock1 CLOCKA U14 DCLK 7 0 Clock Selection Grid Roboclock2 ECLK 15
84. clock outputs The user can set FS accordingly The Frequency Range Settings are shown in Table 4 4 Table 4 4 Frequency Range Settings CY7B993V CY7B994V from MHz from MHz MIN MAX MIN MAX Feedback and First of all FBDIS 2 1 must be set LOW enabling feedback The feed Clock back output is looped back to the feedback input When a divided output 3 is applied to the feedback input the VCO voltage controlled oscillator of Multiplication the PLL aligns the feedback input with the original input clock Thus with a 10 MHz input clock and the feedback outputs set to divide by 2 must be 20 MHz Consequently 10 MHz is seen on the feedback output clocks and can be aligned with the input clocks The feedback clock divider function actually serves as a clock multiplication mechanism for the oper ating frequency The divider function and the clock skew function are set in the same manner for the feedback and the normal clock outputs See Clock Division on page 4 11 and Clock Skew on page 4 12 respectively Clock Division rThethree pairs of DS inputs per chip are used to control the two groups of clock outputs and the feedback outputs of each PLL The user can simply follow the Divider Function Table to acquire the desired output frequency There are two things to remember First F5 2 1 must be set properly according to fNOM Second the FBDS feedback inputs act as operating clock frequen
85. clockll 1 Differential pair with PLL1BN_ PRE GND Ground signals to provide signal integrity for ribbon cables 4 3 Clocks and Clock Distribution Jumper Control for the Most Common 4 4 Applications J13 A J13 B J13 C Figure 4 2 Clock Gri Three main configurations are the most common First the grid may be jumpered as follows Configuration 41 CLKOUT lt gt PLL1A CLOCKA lt gt BUFINA and CLOCKB lt gt BUFINB Both 3807s receive their inputs from the oscillators Roboclockll 1 receives a clock input from the CPLD Also Roboclockll 2 can use DCLK 7 from Roboclockll 1 as an input This is explained in Roboclock PLL Clock Buffers on page 4 7 The common clock configurations are diagrammed in Figure 4 3 Second the input clock distribution can be configured as Configuration 2 CLKOUT PLL2BN PRE CLOCKA lt gt PLL1A and CLOCKB lt gt BUFINB In this configuration a 3807 2 receives an oscillator input Roboclockll 1 receives an oscillator input while Roboclockll 2 receives the CPLD output clock signal 3807 1 is unused Finally the grid may be configured as Configuration 43 CLKOUT lt gt BUFINB CLOCKA BUFINA and CLOCKB lt gt PLL1BN PRE The 3807 1 receives an oscillator input and the 3807 2 receives a CPLD input Meanwhile Roboclockll 1 receives the other oscillator input The user can wire wrap a clock to the unused driver s as needed This
86. cy multipliers The Output Divider Settings are shown in Table 4 5 DN5000k10 User s Manual 4 11 Clocks and Clock Distribution Table 4 5 Output Divider Settings Input Signals Output Divider Function C fF DS1 and FBDS1 2 1 C F DSO and FBDSO 2 1 Feedback Output Signals Output Signals Clock Skew 4 12 Clock skew is controlled by the F inputs The clock skew may be any integer value from 0 to 8 times the Roboclockll time unit ty The time unit value is derived from the operating frequency and the FS 2 1 setting The following equation yields the time unit tu _ 1 The possible values for are given in Table 4 6 The available skew for each Roboclockll derived clock is given in Table 4 7 Based on the following information the user will be able to adjust the skew for any of the Roboclockll outputs ty Table 4 6 Time Unit N factor CY7B993V CY7B994V at which at which ty 1ns ty 1 5 The DINI Group RB C F F1 LOW RB C F FO and FBFO 2 1 LOW Clocks and Clock Distribution Table 4 7 Clock Skew Settings Input Signals DCLK 3 0 or ECLK 11 8 4tu Output Skew Function DCLK 7 4 or ECLK 15 12 4ty CCLK 3 0 or ECLK 3 0 Bty CCLK 7 4 or ECLK 7 4 8tu Feedback Output Signals LOW MID 3tu 3tu 7tu Tty LOW HIGH 2ty 2ty 6ty 6ty MID L
87. d idea the system powers up as the board is installed PME is connected to TP7 This test pin allows the user to connect external circuitry to PME if this functionality is desired JP3 PCI PCI X Capability Figure 3 5 shows the PCI X Capabilities Header Add in PCI X boards tell the system what speed they are capable of running by the correct setting of this header JP3 PCIXCAP R93 C141 10K T Figure 3 5 PCI X Capability Header Add in cards indicate at which frequency they support PCI X using a pin called PCIXCAP If the card s maximum frequency is 133 MHz this pin is left unconnected except for a decoupling capacitor C141 If the card s maximum frequency is 66 MHz it connects PCIXCAP to ground through a resistor R93 and decoupling capacitor C141 Conventional PCI cards connect this pin to ground JP3 PCIXCAP For PCI only not PCI X capable jumper between pins 5 and 6 For PCI X 133 MHz capable jumper between pins 3 and 4 For PCI X 66 MHz capable jumper between pins 1 and 2 and pins 3 and 4 The PCIXCAP jumpers are detailed in Table 3 3 Table 3 3 PCIXCAP Jumpers PCIXCAP Jumper s Installed PCI Only PCI X 133 MHz 3 4 PCI X 66 MHz 1 2 3 4 The DINI Group PCI The M66EN and PCIXCAP Encodings are shown in Table 3 4 Table 3 4 M66EN and PCIXCAP Encoding Conventional PCI X Device PCIXCAP E oodd Frequency a y Capability Capability Ground Ground Not Capable Not
88. d memory is dual ported and can be used to construct almost any type of memory FIFOs dual port RAMS single port RAMs etc The two largest blocks M RAM and RAM are fully dual ported memory with read and write functions available on two separately clocked ports M512 RAM is a simple dual port memory meaning that one port is write only and the other is read only Any of the memory blocks can be configured as simple dual port or single port memory See Figure 2 4 for a diagram of the memory Stratix devices feature a large number of multipliers grouped into what Altera calls DSP blocks see Figure 2 5 The EP1S80 contains 22 DSP blocks each of which can provide one 36x36 bit multiplier four 18x18 bit multi pliers or eight 9x9 bit multipliers Each block also contains adder subtractor accumulator registers which can be configured to provide many common DSP functions such as FIR or IIR filters FFT or DCT without the use of LAB resources The Stratix datasheet available at ALTQPRAM rdaddress a rden a outclock a outclocken a data a wraddress a wren a inclock a inclocken a rdaddress b rden b outclock b outclocken b data b wraddress b wren b inclock b inclocken b inst Figure 2 4 Dual Port Data Flows The DINI Group Optional Serial Shift Register Inputs from Previous DSP Block Optional Serial Shift Register Outputs
89. driver directory make sure the driver file dndev is in the sparc sub directory and run sh dndev uninstall sh 2 Touninstall the driver run sh dndev uninstall sh 3 Torun the test utility run aetest solaris asroot after the driver is loaded The driver is compiled with the gcc compiler aetest solaris is compiled with gmake You can download it from the GNU website The make from the Solaris installation does not work with our makefile format You may need to make aetest solaris executable run chmod u x aetest solaris DN5000k10 User s Manual 9 3 Utilities 9 4 AETEST Options Description and Definitions Installation Instructions for Windows 98 ME There are two ways to run AETEST You can run the DOS version aetestdj exe directly or you can run AETEST with a device driver To run AETEST with a device driver follow the steps below 1 Choose a default PCI driver for the device When Windows first starts with the device plugged in it should ask for a device driver Select Specify the location of the driver Select Display a list of the drivers in a specific location Select Other devices Under Manufacturers tab select unknown device Under Models select unsupported device 9x ur Re Lo NJ The driver file pcifg vxd and aetest98 exe must be in the same directory Run aetest98 exe NOTE To re compile the driver file pcicfg vxd you need the VtoolsD compiler fr
90. du propietaire gt ELECTRONICS Property of BERG ELECTRONICS Copyright BERG ELECTRONICS INC NI rights strictly reserved Reproduction or issue to third porties in form whatever is not permitted without written authority from the proprietor PRODUCT NO SEE TABLE 0 062 1 57 DRAIN AREA 0 015 0 38 HGT INTACT 0 008 0 20 55 721222222 SECTION ROTATED COUNTERCLOCKWISE 90 SCALE 10 1 VLLLILLLLLLLLLLD 0 104 2 64 REF 2X RO 052 1 32 REF 2X PROCESSING CAP 375 9 52 OUTSIOE PROFILE SHOWN ONLY NOTE 5 FRAME 04 1 0 SOLDER TAILS NOTE 4 ip ma 16 41 LI 055 1 40 VIEW A pm OPTIONAL HOLD DOWN BOTH ENDS FOR 096 003 2 45 08 PCB HOLE 2X SEE NOTE 6 form no 7530 001 103 0 040 X 0 047 OVAL REF 0 044 1 12 0 220 5 59 2x R 110 R2 79 A 2x 025 0 64 pw c 2X mat code v51287 10 20 95 chr J E70095 sam 07 22 97 sheet index sheet 112 3 270 6 86 SEE NOTE 3 tolerances unless otherwise specified CUSTOMER His Wwe ELECTRONICS 2 005 projection 0020 d e MICRORAN SMT Eu r5 PLUG DOUBLE MODULE MICROPAX size dwg no 91204 B Figure A 3 Berg 91294 003 Datasheet Page 1 of 3 The DINI Group A 4 Berg Connector Datasheets droits strictement reserves R
91. duction BERG ELECTRONICS INC w gt 01 100 0 S4 OU RISIB s s coo ri ie evooe i oo xo 09 izzc ssv sswo oocz voos osvc 2cv9 osez oc izzc sori eses oozz woos osre zcv9 ossz ziis szz Paijioads asimsayjo S 2U0J9 O lrororr ouvi 9275 jonpoid 1d3934 03 Lv Si ou 6 V1 335 NNMQNYM 30 SJAAL SNORIVA 503 53215 310M ONIOMON VIVO NOlvOnddv W3Hin4 NO4 SNOUYN3dO M01338 N3O 0S 30 S3dAl ISON NOs OMYOS 109812 JHL Ol NOIJ3NNOO JHL 38n03S 04 O3inO3 5 3uYMQNYH NMOGTION 3804331 SNOUVIMYA TVNOISN3NIO QuYOG NIYII Q31NRid 31Y00NMO2OY OL 83080 INvidmO2 38 OL 03896530 Jav 1900039 SIM NO Sii 30105 3M v cOvI6 XVdOYDIN JINGOW 319NIS HIM O3IVM SI YOLD3NNOD N3HM 08 OL O8 3TWWYd JHL 3050990 531415 um 32vsuns AWHL 133A Ol SAlddV JSON TN310d 1N3A3Hd THM dY2 O3131dmOCO 51 05 WINN dY2 9NISS3OONd MONIY 10N 00 S S2 NOWA122313 5532044 9NR3010S dl HIH 393ld IAS WSZO XVdOWOIMW po 8 a Y Figure A 2 Berg 91403 003 Datasheet Page 2 of 2 DN3000k10 User s Manual A 3 Berg Connector Datasheets Propriete de c BERG ELECTRONICS Droits de reproduction BERG ELECTRONICS INC Tous droits strictement reserves Reproduction ou communication a des tiers interdite sous quelque forme que sons outorisation ecrite
92. e described in the DN3000k10 FAQ on our website and FPGA Configuration The pP Some Details The DN5000k10 has an ATmega128L microprocessor uP that is used to control the configuration process U8 The amount of internal SRAM 4 Kbytes was not large enough to hold the FAT needed for SmartMedia so an external 32 k x 8 SRAM was added The address latching function is done via an LVT373 U3 The microprocessor has the following responsibilities e Reading the SmartMedia card e Configuring the Stratix FPGA e Executing DN5000k10 self tests Other than FPGA configuration the uP has no responsibilities Less than 2596 of the 128 Kbytes of FLASH is used for FPGA configuration and utili ties so you are welcome to use the rest of the resources of the pP for your own purposes Instructions for customizing the pP are contained in the file Custom ATmegal28L pdf This file is on the CD ROM or it can be down loaded from the DINI Group web page REMEMBER You can use the microprocessor for your own purposes We ship a programming cable for the ATmega128L with the DN5000k10 Updates to the code will be posted on our web site If you wish to do your own development you will need the compiler which we do not ship with the product The compiler is available from IAR http www iar com The part number is EWA90PCUBLV 150 Note that if you are willing to program the FPGA with the JTAG or serial cable the and the uP
93. e DN5000k10 must be plugged into a 43 3 V PCI slot PCI X by definition is 3 3 V signaling The PWB is keyed so that it is not possible to mistakenly plug the board into a 5 V PCI slot Do NOT grind out the key in the PCI host slot and Do NOT modify the DN5000k10 to get it to fit into the slot If you need a 43 3 V PCI slot the DNPCIEXT S3 Extender card can do this function The link is http www dinigroup com products pciextender html This extender also has the capability to slow the clock frequency of the PCI bus by a factor of two a function that is very useful when prototyping ASICs NOTE 5 V Signaling on Stratix parts causes them to smoke This is quite BAD Do NOT Modify the DN5000k10 board to fit into your pci slot PCI Mechanical DN5000k10 is not a standard sized PCI card it is too tall and slightly Specifications too long This is sometimes an issue in servers that have a bracket installed over the top of the PCI cards If you need to close the case on a DN5000k10 some tower configurations may work Figure 3 3 shows the exact dimen sions of the DN5000k10 Some Notes 33v power is not needed on the host PCI connector 43 3 V power is on the derived from 5 V using an on board 10 A switching regulator Power DN5000k10 distribution for the DN5000k10 is described in Power Supplies and Power Distribution on page 6 1 and PCI PCI X LOCK has a pull up This is technically a violation of the PCI specificatio
94. e Programming Files tab turn on Raw Binary File rbf and turn off all other options Note the sof file for JTAG programming will also be created The DINI Group DN5000k10 Features Overview and General Description The easy way to assign pins is to create your project then open the csf file created in a text editor If your pinlist is formatted correctly you can copy it and paste it into the csf file in the section labeled CHIP design name Sample files on the software CD provided found in the folder labeled Verilog show how to format the information and provide the correct pinlist for the signal names used on the board Setting up the Serial Port J3 RS232 Port J3 is for an RS232 connection to a terminal An ICL3221 U2 provides voltage translation to RS232 levels A cable that converts the 10 pin header to a DBO9 is shipped with the DN5000k10 This cable comes pack aged with a bracket attached Remove the bracket to eliminate the possi bility of it falling on the DN5000k10 which could short signals and damage the board After you have removed the bracket plug the cable into J3 J3 is not keyed so make sure you get the orientation correct Pin 1 is identified with the number 1 and a dot Figure 2 12 is a cutout from the assembly drawing and shows the location of J3 and Pin 1 ROBOCLOCK 00000000 1 y Beg DN5000K10 E ASSY NO 502 0105 COPYRIGHT C 2002 THE DINI GROUP LA JOLLA INC MAD
95. enables full use of the timing devices on the DN5000k10 Also the destination of the output clocks might dictate some other configuration This manual and other documentation should provide more than enough information to satisfy the user s needs See Figure 4 4 The DINI Group Clocks and Clock Distribution FCLKOUT PCLK ECLK 15 0 ACLK 1 FPGA A U12 RoboClock 2 U16 ACLK 2 FPGA E U15 ACLK 3 FPGA CCLK 6 0 RoboClock 1 ACLK 4 U14 a E E cera fT perky U20 HDR CLKOUT ECLK 12 9 J19 ECLK 5 FB ECLK 7 AB ECLK 8 ED ACLK 6 CCLK 6 6 CON2 ECLK 14 J10 ACLK 7 BCLK 7 CCLK 7 HDR CLKOUT CON J9 ACLK 5 BCLKIS I DCLK 5 pied ECLK 13 J16 DN5000k10 Clock Distribution Rev 3 11 03 Figure 4 3 Common Clock Configurations DN5000k10 User s Manual 4 5 Clocks and Clock Distribution PLL2B PRE C375 PLL2BN PRE 393 PLL1B_PRE C396 PLL1BN PRE 33V 43 3V 33V 43 3V LJ LJ LJ LJ R197 amp R201 R182 amp R190 82 82 82 lt 82 O 1uF PLL2B 0 1uF PLL2BN U DEED LEES PLLIB 0 1uF PLLIBN LL O 1uF R183 amp R191 R198 amp R200 130 S 130 130 amp 130 Figure 4 4 PECL Clock Input and Termination Ribbon Cable Providing an Off Board Clock to the DN5000k10
96. ential order to the same address A looping option is available if you want to use The DINI Group Utilities an oscilloscope If you are in a scope loop any keypress will terminate the loop and return you to the main menu Read Memory Byte Read a single byte from a specific PCI memory location Figure 9 12 Input address fb000000 b000000 Please select 1 Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely Figure 9 12 AETEST Read Memory Byte You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be read Three options are available 1 Read once and display 2 Read indefinitely and display 3 Read indefinitely and don t display Write Read Memory Byte write and read a single DWORD from a specific PCI memory location After entering a memory address hex 32 bits you specify how many DWORDS you want written and read back and the data Then you choose from the 3 options as above The menu option does not perform any data checking Figure 9 13 Numbers of long words to write in decimal 2 byte to write in hex 88888888 byte to write in hex 99999999 Please select l Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely Figure 9 13 AETEST WritelRead Memory Byte Memory test on SSRAM1 Tests one of the SSRAM chips
97. eproduction ou communication a des tiers quelque forme que ce sot sons autorisation ecrite du propietaire Propriete de c BERG ELECTRONICS Droits de reproduction BERG ELECTRONICS INC Tous ELECTRONICS All rights strictly reserved Reproduction or issue to third porties in form B whatever is not permitted without written authority from the proprietor Property of BERG ELECTRONICS Copyright BERG ELECTRONICS INC gt PRODUCT NO SEE TABLE esp 0 050 91 27 0 0 110 2 79 REF 2X 0 220 5 58 REF 2x FRAME TO BOARO CONTACT AREA 0 075 1 91 REF 2x 0 160 4 06 REF 0 052 1 33 2X REF form no 7530 001 103 003 0 08 0 045 e1 14 1000 0 0 100 2 54 160 4 06 090 2 29 410 10 41 025 0 64 050 1 27 J 015 0 38 002 05 2x 005 15 GJ tole specified Se Xxx 005 proton lle MICROPAX 025M SMT 4 t PLUG DOUBLE MODULE Fo 35 wcu ww esit Tom Tenge unas 3 4 93 size dwg no Jem uras 3 4 93 scale 91294 1 j jo uras s 4 3 1 1 2 of Figure A 4 Berg 91294 003 Datasheet Page 2 of 3 A 5 DN3000k10 User s Manual Berg Connector Datasheets Tous droits striclement reserves Reproduction ou communication a des liers interdite sous quelque forme que ce soit sons autorisation ecrite du propietaire Propriete de BERG ELECTRONIC
98. et button 2 23 to 2 24 Roboclock 4 7 to 4 8 4 16 to 4 17 Roboclockll 2 1 4 1 4 3 to 4 4 4 6 4 9 4 12 to 4 14 4 17 to 4 18 5 10 RST 3 4 9 1 S SDRAM 2 3 4 16 5 1 5 10 to 5 13 6 2 6 4 9 2 9 13 Selectl O 7 1 Serial Port 2 19 serial port 2 13 to 2 14 2 20 to 2 23 8 4 Signals ACLK 4 1 7 8 ADSC 5 8 5 10 ADSP 5 8 5 10 ADV 5 10 BCLK 4 1 7 8 BCLKOUT 4 17 BCPUCLK 2 17 BUFINA 4 3 to 4 4 4 6 BUFINB 4 3 to 4 4 4 7 BWE 5 10 BWx 5 10 CCLK 4 10 4 13 to 4 14 4 17 7 8 CE 5 10 CE2 5 10 CLKOUT 4 1 4 3 to 4 4 Clock Signals ACLK 4 1 7 8 1 4 BCLK 4 1 7 8 BCLKOUT 4 17 BUFINA 4 3 to 4 4 4 6 BUFINB 4 3 to 4 4 4 7 CCLK 4 10 4 13 to 4 14 4 17 7 8 CLKOUT 4 1 4 3 to 4 4 CLOCKA 4 3 to 4 4 CLOCKB 4 3 to 4 4 4 7 CPUCLK 2 17 DCLK 4 4 4 10 4 13 4 16 to 4 18 7 11 ECLK 4 10 4 13 to 4 14 4 16 to 4 17 5 1 5 10 7 8 7 11 FCLKOUT 4 10 4 16 to 4 18 MODE 4 10 CLOCKA 4 3 to 4 4 CLOCKB 4 3 to 4 4 4 7 CPLD TCK 2 17 CPLD TDI 2 17 CPLD TDO 2 17 CPLD TMS 2 17 CPUCLK 2 17 DCLK 4 4 4 10 4 13 4 16 to 4 18 7 11 ECLK 4 10 4 13 to 4 14 4 16 to 4 17 5 1 5 10 7 8 7 11 FBDIS 4 10 to 4 11 FBDS 4 10 to 4 11 FBFO 4 10 4 13 FCLKOUT 4 10 4 16 to 4 18 FS 4 10 to 4 12 4 14 GW 5 10 INV1 4 14 INV2 4 10 4 14 JTAG TCK 2 17 to 2 18 3 4 TDI 2 17 to 2 18 3 4 TDO 2 17 3 4 TMS 2 17 3 4 TRST 3 4 LD 5 10 MODE 4 10 PCI RST 3 4 9 1 PCI Signals CE 5 10 CE2 5 10 PCI_CLK 4 16
99. formation The program is looking for a Vendor and Device ID that it recognizes and finds vendor abcd and device 1240 which is a DN5000k10 stuffed with a 2V60000 The lines after Configuration space show whatis in the configuration space and how the BARs are configured If AETEST does not see a PCI peripheral it recognizes you will see the following Figure 9 2 vendor id 5045 vendor id abcd vendor id abcd vendor id abcd vendor id abcd vendor id abcd vendor id 1234 vendor id 1234 vendor id 11e3 vendor id 1010 vendor id 71f3 vendor id 507 vendor id bc92 vendor id e125 vendor id e62c vendor id 448b vendor id 1243 vendor id 5143 vendor id dead vendor id 10b5 device id 1 device id 1234 device id 1235 device id 1236 device id 1237 device id 1240 device id 5678 device id 5679 device id 6 device id 5064 device id 2454 device id 2367 device id 2e6c device id c38c device id ca76 device id e6a device id 4321 device id 2 device id beef device id 9610 Hit a key to continue interface test VENDOR ID 1234 PowerPC bridge VENDOR ID 11e3 old VID DID VENDOR ID 1010 DEVICE ID 5064 DEVICE ID 2454 DEVICE ID 2367 DEVICE ID 2e6c DEVICE ID c38c DEVICE ID ca76 DEVICE 8051 VENDOR ID 1243 DEVICE ID 4321 searching for Quad Sharc VENDOR ID 5045 searching for DN2000K10 Asic Emulator VENDOR ID abcd searching for DN2000K10 Asic Emulator search
100. ghter cards 2 2 6 4 to 7 4 7 6 to 7 14 DCLK 4 4 4 10 4 13 4 16 to 4 18 7 11 debug 2 1 to 2 3 2 12 5 1 9 1 to 9 14 analyzer based 2 1 to 2 3 2 12 9 1 to 9 14 Device ID 2 21 9 5 9 7 differential LVDS pairs 7 1 DIMM 2 3 5 1 5 10 6 2 divider function 4 11 to 4 12 Index Index Continued DLL 7 1 DN3000k10 2 24 DN3000k10S 2 24 DN3000k10SD 2 2 7 1 to 7 4 7 6 to 7 8 DN5000k10 1 1 block diagram 2 2 description 2 2 to 2 3 features 2 1 to 2 2 frequently asked questions 1 1 technical support 1 1 DNPCIEXT S3 3 1 DOS 9 1 to 9 4 9 6 DOS extender 9 2 DOS extenders 9 1 drive 6 3 drive power connector 6 3 DSP 2 6 2 8 dual port 2 6 E ECLK 4 10 4 13 to 4 14 4 16 to 4 17 5 1 5 10 7 8 7 11 EEPROM 2 12 5 12 embedded memory 2 1 2 6 2 26 EP1S60 2 1 2 3 EP1S80 2 1 2 3 2 5 to 2 6 2 24 EPM3256A 2 15 ESD 1 1 esd 1 1 extender card 3 1 external 2 2 5 1 external memories 2 2 5 1 F Fast Passive Parallel 2 17 to 2 18 2 20 2 22 to 2 23 8 1 FBDIS 4 10 to 4 11 FBDS 4 10 to 4 11 FBFO 4 10 4 13 FCLKOUT 4 10 4 16 to 4 18 feedback disable 4 10 feedback output divider function 4 10 feedback output phase function 4 10 FIFO 2 6 FLASH 2 1 2 3 2 10 2 12 2 14 2 22 2 24 to 2 25 1 2 9 6 FlashPath 2 22 2 24 to 2 25 FPGA 1 1 2 1 2 3 2 10 2 14 to 2 15 2 17 to 2 18 2 20 to 2 21 2 24 2 26 3 1 to 3 2 3 4 3 6 4 16 to 4 17 5 1 to 5 2 5 10 6 2 to 6 3 7 8 8 1 8 3 to 8
101. gnals P4NX7 and P4NX6 are also used for direction select and output enable on U2 and U3 respectively J3 JA Buffered Interface header IDC headers 50 pin providing 48 buffered I O signals See Table 7 2 on page 7 8 J5 J6 J7 Unbuffered Interface Header IDC headers 50 pin providing 66 buffered I O signals See Table 7 2 on page 7 8 The DINI Group Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors Buffered I O Test Interface Connector J1 DN5000k10 User s Manual The DN3000k10SD Daughter Card provides 48 buffered I O signals The function of these signals is position dependent U1 U2 and U3 allow for different populating options and devices can be active or passive Active The LCV162245A is used for asynchronous communication between data buses It allows data transmission from the A to the B or from the B to the A bus depending on the logic level at the direction control DIR input The output enable OE input can be used to disable the device so that the busses are effectively isolated Passive The FST163245 bus switches are used to connect or isolate two ports without providing any current sink or source capabilities Thus they generate little or no noise of their own while providing a low resistance path for an external driver The output enable OE input can be used to disable the device so that the busses are effectively isolated The DN3000k10SD Daughte
102. gure 9 6 AETEST Write to Memory Test You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be accessed A minimum of 1 to a maximum of 1024 long words can be written in sequential order to the same address A looping option is available if you want to use an oscilloscope If you are in a scope loop any keypress will terminate the loop and return you to the main menu Read Memory Test Read a single long word from a specific PCI memory location Figure 9 7 b000000 Please s Puedes eene Input address f5000000 l Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely elect 9 10 Figure 9 7 AETEST Read Memory Test You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be read Three options are available 1 Read once and display 2 Read indefinitely and display 3 Read indefinitely and don t display The DINI Group Utilities Write Read Test write a long word to a specific PCI memory location and immediately read what was written Repeat for a selected number of long words Figure 9 8 Input address fb000000 long word to write in hex 000 long word to write in hex aaa l Display result Please select Numbers of long words to write in decimal 2 2 Display result and loop indefinitely 3 Don t displa
103. have no function In this case you can use all of the resources of the for your own purposes The ATmega128L is gross overkill for the FPGA configuration function The datasheet and user s manual are on the CD ROM that was shipped with the DN5000k10 The file names are ATmega128 UM pdf and ATmegal28 DS pdf Butif you intend to use the uP for your own purposes you should check the Atmel web page to get a copy of the latest user s manual datasheet and erratas The Atmel web page is http www eu atmel com atmel The ATmega128L is under the section called Flash Microcontroller AVR 8 Bit RISC Most of the features are unused A variety of test headers allow for possible use of these features Each header and the various possible functions are described in the The DINI Group DN5000k10 Features Overview and General Description CSF AID Inputs or FWaTSM aner up _ Genera poves FPGA aN avcc JTAG Purpose I O I ENI F J5 15 011 J2 FPGA A Atmel AVR ATmega128L Translator H P T RS232 gt 128kbytes FLASH Connector D 4kbytes SRAM 4kbytes EEPROM cs 1CL3221 U8 we 4 Media DAPA Card Inserted E FPGA Programming Su m U4 E DE 415v Reset amp Power U15 Threshold Detection DS1 LED 3 0 4 DOUTBSYA U12 FPGA B U19 FPGA D U20 Reset Switch 1 J4 S1
104. he main source of technical information We strive to produce excellent documentation and this manual should contain most of the answers to your questions 2 The DINI Group Web Page The web page will contain the latest manual application notes FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com index php product 5000k10 3 E Mail to support dinigroup com You may direct questions and feedback to The DINI Group using this e mail address 4 Phone Support We are happy to help Call us at 858 454 3419 during the hours of 8 00 A M to 5 00 P M Pacific Time Some of us get in early and stay late so you might try us outside of these hours also 5 Frequently Asked Questions In the downloads section of our web page you can find a document called DN5000k10 S Frequently Asked Questions FAQ We will update this document occasionally with information that may not be in the User s Manual Relevant Information DN5000k10 User s Manual Information about PCI can be obtained from the following sources The PCI Special Interest Group has a web page that has lots of good stuff Copies of the latest PCI specification may be ordered here http www pcisig com PCI Special Interest Group 2575 NE Kathryn St 17 Hillsboro OR 97124 FAX 503 693 8344 1 1 Getting Started As of October 2001 the most current versions of the PCI Specifications are PCI Local Bus Specificatio
105. huwa Ga Bo a as 8 4 The 200 Pin Connectors J9 J10 J16 8 4 Ihe Signals 2222 yeeurevevie bier ewe seeded 8 5 DN5000k10 User s Manual V Chapter9 Utilities PCI Debug General Pontificating 9 1 PC Based AETEST EXE 9 1 AETEST Utility Installation Instructions 9 2 Installation Instructions for DOS 9 2 Installation Instructions for Windows NT 9 2 Installation Instructions for Windows 2000 9 2 Installation Instructions for LINUX 9 3 Installation Instructions for Solaris 9 3 Installation Instructions for Windows 98 ME 9 4 AETEST Options Description and Definitions 9 4 esed ne Dae orte t EI Ra mers 9 4 AETEST Main 9 6 Options cade pals ahaa eh tachuman us RA 9 6 PCI Men dan hee Se ved 9 7 Memory Menu 9 9 Chapter A Berg Connector Datasheets vi The DINI Group List of Figures FIGURE DN5000k10 User s Manual 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 3 1 3 2 3 3 3 4 3 5 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 List of Figures TITLE PAGE DN5000k10 Block Diagram 2 2 DN5000k10 Stuffing Option Comparison 2
106. icroprocessor controls the FPGA configuration process Visibility into the configuration via process is enhanced with an RS232 port Sanity checks are performed auto SmartMedia matically on the configuration bit files helping to avoid the time consuming process of debugging the configuration process FPGA config uration runs quickly at 48 MHz Eight LEDs provide instant status and oper ational feedback Four of these LEDs are connected to the CPLD and can be user configured FPGA Stratix U11 U12 U15 U19 U20 F A E B D The DN5000k10 contains two to five Stratix FPGAs They are called A B D E and F The package is a flip chip fine pitch BGA with 1508 pins F1508 The pitch on the pins is 1 mm This isn t important but this pin density makes the PWB a bitch to layout Keep that in mind if you try to make one of these at home Most of the 1203 I O pins are utilized on the F1508 package The DN5000k10 can be stuffed with EP1S80 devices any combination of locations The EP1S60 does come in an F1508 but since it has fewer I O pins it should not be used The standard speed grade we stuff is 7 We can use the 6 speed grade but don t fall out of your chair when you get the price Note that Altera seems to have cancelled plans for the 15120 Although this part appears in some Altera literature we haven t seen any scheduled release date or other documentation for it Don t expect to see anything larger than the EP1S80
107. id Data Valid Data Read Phase To continue a burst ADV LD is low to load a new address high to continue bust For write access only Writes to all four bytes The DN5000k10 has a socket for a 43 3 V 168 pin SDRAM DIMM Either registered or unbuffered modules fit in the socket U7 The same PC100 PC133 SDRAM modules that you put into your PC are used here Your DN5000k10 will be stuffed and tested with a 1 Gbyte PC133 SDRAM DIMM unless otherwise requested All DIMM pins are connected to the FPGA and the pins are shown in Figure 5 11 and Figure 5 12 We aren t quite sure what the largest size SDRAM DIMM is that will work in the DN5000k10 but here is the math as best we understand it 14 Address lines A 13 0 multiplexed between RAS and CAS address 10 not used for CAS 27 2 bank address BA 1 0 2 4 chip selects S 3 0 used in pairs 1 So we think that there are 29 address bits 27 2 and 2 possible chips selects which add one more address bit This totals 30 address bits 1 G of 72 bit long words which is 8 Gbytes Please tell us if this math is wrong SDRAM modules require 4 clocks CK 3 0 These clocks are driven by the Roboclockll 2 and the signal names The CD ROM has a datasheet of an acceptable 1 Gbyte SDRAM module from Micron The file name is SDF36C64 127x72G B pdf The DINI Group FPGA D U20 G17 A8 B14 A22 D16 A16 D13 H16 G18 H17 E15
108. igital signal processing Electrically Erasable PROM Electronic Industries Association Electro Static Discharge frequently asked questions file allocation table field programmable gate array flowthrough Hardware Description Language input output intellectual property light emitting diode large scale integration low voltage complementary metal oxide semiconductor DN5000k10 User s Manual LVDS LVTTL MDR PCI PCI X PL PLL PNP PWB RBF RISC SDRAM SRAM SSRAM TTL VHDL VREF ZBT Glossary and Acronyms Low Voltage Differential Signaling low voltage transistor transistor logic Mini D Ribbon peripheral component interconnect peripheral component interconnect extended pipelined phase lock loop plug and play printed wire board Raw Binary File reduced instruction set computer synchronous dynamic random access memory shadow random access memory synchronous static random access memory transistor transistor logic VHSIC Hardware Description Language reference voltage zero bus turnaround The DINI Group Index Symbols C F DS 4 10 4 12 uP Seemicroprocessor A ACLK 4 1 7 8 ADSC 5 8 5 10 ADSP 5 8 5 10 ADV 5 10 AETEST 9 1 to 9 14 ASIC 2 1 to 2 2 2 26 to 2 27 4 1 4 16 5 1 7 1 7 6 to 7 7 ATmega128L 2 1 2 10 to 2 11 2 15 BCLK 4 1 7 8 BCLKOUT 4 17 BCPUCLK 2 17 Berg A 1 to A 6 Berg connectors A 1 to A 6 BIOS 9 1 9 9 BIockR
109. ing for DN2000K10 Asic Emulator searching for DN2000K10 Asic Emulator searching for DN3000K10S Asic Emulator searching for 415064 searching for q15064 64MB dram LFSR VENDOR ID searching for q15064 searching for q15064 PowerPC bridge searching for q15064 AntiFuse test 1 searching for q15064 AntiFuse test 2 searching for q15064 AntiFuse test 3 searching for q15064 AntiFuse test 4 searching for q15064 AntiFuse test 5 searching for q15064 AntiFuse test 6 searching for q15064 Emulated with searching for Greg s PCI Device VENDOR ID 5143 searching for Cohu s PCI Device searching for LYNX 9610 VENDOR ID 10b5 DEVICE 6000 VENDOR ID abcd 1234 VENDOR ID 71f3 VENDOR ID 507 VENDOR ID bc92 VENDOR ID e125 VENDOR ID e62c VENDOR ID 448b DEVICE ID DEVICE ID 9610 Didn t find known device in the following list DEVICE ID 1234 2000E VENDOR ID abcd 1000E VENDOR ID abcd 1600E VENDOR ID abcd DEVICE ID 1235 DEVICE ID 1236 DEVICE ID 1237 DEVICE ID 1240 DEVICE ID 5678 DEVICE ID 5679 DEVICE sensor board VENDOR ID dead DEVICE ID beef Figure 9 2 AETEST Startup Screen No PCI Peripheral Recognized AETEST will still run but many DINI product specific options will not be available DN5000k10 User s Manual Utilities AETEST Main The AETEST Main Screen is shown in Figure 9 3 Screen ASIC Emulator PC
110. ions to DN3000k10SD Observation Daughter Card for 200 pin Connectors DIFFERENTIAL ACLK1 CONNECTOR BCLK1 CCLK1 ECLK1 is MBCK6 J3 J4 J5 J6 J7 50 PIN IDC HEADER UNBUFFERED VO 0 17 CUERO U J2 DIFF PAIR A0 A15 J6 UNBUFFERED I O 0 23 50 PIN MINI D RIBBON CABLE CONNECTOR J7 UNBUFFERED I O 0 23 LINEAR REGULATOR 12VDC TO 3 3V 3 9VDC BUFFERED I O 0 15 3 3V 5 0 12 0V BUFFERED I O 0 7 J1 POWER INDICATORS U1 UNBUFFERED I O 0 15 O O O POWER k U2 UNBUFFERED I O 0 15 HEADER 1 5V 3 3V J4 5 0V 12 0V J6 U3 UNBUFFERED I O 0 15 12 0V GND 20 PIN IDC 74LVC16245APA 200 PIN MICROPAX HEADER 74FST163245PA BOTTOM OF PWB U1 U2 U3 BUFFERS OR LEVEL TRANSLATORS Figure 7 1 DN3000k10SD Daughter Card Block Diagram 7 2 The DINI Group Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors eM LS Sa ee b m x w oa LE b 5 TILLLETIEIJI Bald LIN irm iem DR E a r gt mr T 2 T oF i 777 DT 9002403 LEE Qua DIXODQtMB e Figure 7 2 DN3000k10SD Daughter Card DN5000k10 User s Manual Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors MADE IN USA DN3000K10 DAUGHTER BOARD THE DINI GROUP 2001 Figure 7 3 Daughter Card LEDs Power Supply
111. l Of the four listed here we find that Synplicity offers the best perfor mance followed by Exemplar The Synopsys products are not the easiest products to use and probably should be avoided until Synopsys decides that they want to be in this market It is generally not worth your time to preserve your Synopsys ASIC compiler directives and scripts by using the FPGA synthesis products from Synopsys The time you save using Snopsys products is offset by other hassles 1 The FPGAs used on your DN5000k10 are EP1S80s in an F1508 package EP1S60s available on request Unless you paid for a faster speed grade the 6 is what you will be getting 2 Assuming you have a synthesis tool other than Quartusll memories are best implemented by describing them behaviorally in your RTL All four synthesis products are sophisticated enough to map your behav ioral descriptions into the memory blocks It is NOT necessary to instantiate memories manually unless you are synthesizing with Quartus Make sure however to check the report files to make sure that your memories were implemented in memory blocks if this is possible If input and output registers in your RTL don t match the behavior of the embedded memory blocks the synthesis program may not recognize what you intended and give you arrays of LEs instead 3 Much to our surprise the synthesis programs recognized RTL multi plier code and used the embedded multipliers without any trouble So
112. l for each FPGA for example FPGA CSnA FPGA CSnB FPGA CSnD etc Clock FPGA DCLK Chip Select FPGA CSnX FPGA CEnX Control FPGA_nCONFX FPGA CDONEX FPGA IODONEX FPGA RDYnBUSYX Data Bus FPGA_D 7 1 Mode Selector Switches FPGA_MSEL 2 0 DIP1_0 e Pass Through of Serial JTAG Cable Signals Cable DCLK TCK CONF DONE TDO nCONFIG TMS nSTA TUS DATAO TDI DN5000k10 Features Overview and General Description Gw alan t R2 IE D4 mum SMART MEDIA e FPGA Chain CPLD TMS CPLD CPLD TDI CPLD TCK CPLD TRST e Support for Clocking Schemes CPLD Clock Input CLK 48 Inputs from Clock Buffers ACLK 8 BCLK 8 Output to Clock Grid BCPLD CLKOUT e Interface to Reset Schemes FPGA GRSTn PWR RSTn We may periodically update the CPLD The CPLD can be reprogrammed using the Altera JTAG cable supplied with the DN5000k10 The connec tions are on header JA The relevant signals and the connections to J4 are listed in Table 2 1 Figure 2 10 shows the location of J4 2 C24 m m m FPGA JTAG J15 3 DATAO T01 7 NSTATUS 5 NCONFIG TUS 3 CONF D NE TOO 1 DCLK TCK 2 FPGA TDIF FPGA_TDIA FPGA_TDIB FPGA_TOID FPGA_TDIE 2907 KEAR 1 SP SIS Ph a Pu wu uu 75227 e nuu ROBOCLOCK DN5000K10 ASSY NO 502 0105 COPYRIGHT C 2002 THE DINI GROUP LA JOLLA INC MADE IN USA 639 See u e o a 765 521 REV 1 0 GND C
113. l result in clocks CCLK 1 0 and CCLK 3 2 ECLK 1 0 and ECLK 3 2 becoming complementary pairs A network of series and parallel resistors could be used to reduce the nominal swing of the clock signals The CYB993V consistently outputs 32 5 MHz signals in cases of improper settings or unacceptable clock inputs This was observed when CY7B993V part was operating at a nominal frequency fyom of 36 4 MHz with FS set LOW e Identical clocks were sent to PLL2B and PLL2BN For the CY7B994V part the operating frequency can reach up to 200 MHz However the maximum output frequency is 185 MHz This means when 185 MHz fyom 200 MHz the output divider must be set to at least 2 Otherwise the Roboclockll s will output garbage Customizing the Oscillators The user can customize the frequency of the clock networks by stuffing oscillators in X2 and X3 The DN5000k10 is shipped with a 14 318 MHz oscillator in location X2 and a 100 MHz oscillator in X2 The Roboclockll s are not 5 V tolerant so 43 3 V oscillators are necessary NOTE If you stuff your own oscillators 3 3 V CMOS outputs are neces sary since the Roboclockll s are not 5 V signalling tolerant We get our oscillators from Digi Key http www digikey com Of note is an Epson line of oscillators called the SG 8002 Programmable Oscilla tors Any frequency between 1 00 MHz 106 25 MHz can be procured in the normal Digi Key shipping time of 24 hours A half can
114. lock signal from each of the five clock groups except that J9 does not receive DCLK or ECLK The last available DCLK signal was needed to drive Roboclock 2 and the last ECLK signal was needed to drive the feedback loop for the PCI CLK function Instead J9 has a signal HDR CLKOUT which connects to an input of Roboclock 1 providing another way to drive CCLK and DCLK from an off board source This can be used for systems where additional hardware on a daughter card needs to communicate with the FPGAs on the DN5000K10 Note that HDR CLKOUT and PLL1A are connected to a differential pair of inputs on Roboclock 1 so if HDR_CLKOUT is being used pin 10 on J13 must not be connected to anything so that there is no interfering signal The signal DCLK 7 is routed from one of the Roboclock 1 outputs to one of the Roboclock 2 inputs Jumper J14 lies along this connection route J14 must be installed in order to utilize DCLK 7 R DCLK 7 R and FCLKOUT are complementary input on Roboclock 2 and are both single ended TTL inputs When either of them is being used the other one must be left open Thus FCLKOUT must be undriven on FPGA F for DCLK 7 R to operate DCLK 7 R provides two useful results First any clock signal or some derivation sent to Roboclock 1 can be driven onto Roboclockll 2 for full distribution Second running a clock through Roboclock 1 to Roboclock 2 gives the user more divide and multiply options for the clock freque
115. mpted for the starting address in hex Input starting address hex and 32 bit aligned The following screen is displayed Figure 9 10 0 000000 000020 000040 000060 000080 0000a0 0000c0 000060 000100 000120 000140 000160 000180 0001a0 0001c0 0001e0 000200 000220 000240 000260 orward 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 b ack 4 8 G 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 j ump goto 0 q uit 10 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 14 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0000000
116. n but we have seen systems from SUN that have the LOCK pin floating Remember that the function of this pin was deleted in the 2 2 version of DN5000k10 User s Manual 3 1 PCI 3 2 FPGA F U22 C24 A20 D25 B21 C25 A21 D26 A22 A23 D27 B24 C27 B25 D28 B26 C28 C30 A30 D31 B31 C31 A32 D32 B33 D33 B34 C33 A34 D34 B35 C34 A35 C26 A26 B30 A33 D30 G18 B22 E21 A29 C29 C32 C36 D24 B20 D23 C35 B28 B27 w29 A28 D29 D35 c8 B10 c11 A10 C12 B11 C13 11 D13 B12 C14 A12 D14 B13 C15 B14 D15 A14 D16 B15 D17 C16 E18 B16 C19 A16 D20 B17 C20 A17 D21 C18 A18 C22 A19 C23 E PCI a0 PCI AD 1 lt PCI ADI lt PCI AD 3 i 0 4 i PCI AD 5 PCI ADI6 PCI AD 7 lt gt PCI ADI8 4 _ 0 9 lt gt Pmr PCI AD 10 lt NPC AD 11 lt r V VM rP n 0 12 lt _ si 0 13 lt p OQ CLAD lt PCI AD 15 i O sp PCI AD 16 lt PCI AD 17 lt PCI AD 18 lt y PCI AD 19 i PCI AD 20 lt
117. n 1 5 V a little hot At worst case for all components the 1 5 V power supply should never fall below 1 50 V Table 6 2 Specification for 1 5 V Power ans Manum Voltage Current The DINI Group Power Supplies and Power Distribution If you use the DN5000k10 in a lab environment the Stratix FPGA will never see worst case power and temperature so you can use typical commer cial timing NOTE In a lab environment the FPGA never sees the worst case temper ature and power You can use typical commercial timing Stand Alone Operation The DN5000k10 can be used stand alone meaning it doesn t have to be plugged into a PCI slot Connector P1 is used to provide power to the DN5000k10 in this configuration P1 is a Molex drive power connector and will connect to any standard ATX power supply see Figure 6 2 The power supply that we used is shown in Figure 6 3 but any ATX or AT style power supply will work We use a 250 watt ATX supply Since the DN5000k10 does not draw enough current to meet the minimums required by the supply we plug an old disk drive into another one of the Molex connectors The current drawn by the disk drive sinks enough current to make the switchers in the power supply happy The P1 connector is rated to 13 A far more current than the DN5000k10 can use The DN5000k10 when used stand alone has the following different power rails 5 3 3 V 1 5 V 12 V NOTE If
118. n Revision 2 2 PCI Hot Plug Specification Revision 1 0 PCI Power Management Interface Specification Revision 1 1 PCI X Addendum to the PCI Local Bus Specification Revision 1 0a Other recommended specifications include PCIMG 2 0 Compact PCI Specification Revision 2 1 or greater PCI Industrial Computer Manufacturers Group PICMG 401 Edgewater Place Suite 500 Wakefield MA 01880 USA TEL 781 224 1100 FAX 781 224 1239 http www picmg org The best book to get if you need an introduction to PCI is PCI System Architecture Fourth Edition MindShare Inc Tom Shanley and Don Anderson Ignore some of the ignorant statements made in the Customer Review section at http www amazon com This is an excellent book for PCI and well worth the money The best book to get if you need an introduction to PCI X is PCI X System Architecture MindShare Inc Tom Shanely and Karen Gettman You are going to need to know Verilog or VHDL to use the Stratix FPGA If you need a reference we recommend the following book for Verilog Verilog HDL A Guide to Digital Design and Synthesis Samir Palnitkar ISBN 0 13 451675 3 If you are one of those people that actually like VHDL we feel sorry for you The following books may be helpful Essential VHDL RTL Synthesis Done Right Sundar Rajan The IQ Booster Improve Your IQ Performance Dramatically Edwin Breecher 1 2 The DINI Group Conventions DN5000k10 User s Manual Get
119. ncies Here is an Clocks and Clock Distribution example If you have a 40MHz input clock the user cannot output a 30MHz clock with a single Roboclockll s multiply and divide options However the user can input a 40MHz to Roboclockll 1 and divide it by 4 By installing the J27 jumper a 10MHz clock will be driven onto Roboclockll 42 Setting Roboclockll 42 s feedback outputs to divide by 3 the operating frequency will become 30MHz Thus a 30MHz could be driven onto the Roboclockll 2 output signals NOTE The signal FCLKOUT must be left open in order to utilize DCLK 7 R 4 18 The DINI Group Memories SSRAMIs SSRAM Notes DN5000k10 User s Manual Memories Chapter 5 The DN5000k10 has five external memories four 36 bit SSRAMs and one 72 bit SDRAM DIMM The four SSRAMS are referred to as SSRAM FB U22 SSRAM AD U23 SSRAM AB 021 and SSRAM ED 018 The SSRAMs can be stuffed with ZBT non ZBT pipeline or flowthrough parts We believe we have anticipated the additional address lines for the 1 M x 36 and 2 M x 36 parts when they are available The DN5000k10 is stuffed at the factory with 512 K x 36 bit Synchronous Pipeline Burst SRAM Samsung K7A163600M QC1400 are probably the parts you will have stuffed into your DN5000k10 The datasheet is on the CD ROM in the file DS K7A1636 18 00M pdf The SSRAMs are tested at 100 MHz All SSRAMs use ECLK for their clock SSRAMs FB AB and AD share most of their I Os wi
120. nd return data one clock cycle after the address phase and ZBT PL SSRAMs Figure 5 9 accept and return data two clock cycles after the address phase This allows the user to begin a write burst immediately after the last word of a read burst because read data will be returned before the first write data is required The timing is illustrated in Figure 5 10 and Table 5 2 Write Control amp Data Coherency Memory Block Figure 5 8 Syncburst ZBT FT Write Control amp Data Coherency Input K 1 lt Memory Block J Output 3 Buffers Read Control Figure 5 9 Syncburst ZBT PL 18 2 Address Register Burst Control ead E Buueeis write wee gt 1 gt Reg 2 18 2 Burst C ontrol 11 0 epa J Address gt Register Buueeis Setup i Hold Address Phase Write pen ADSP ZBT PL Phase ZBT FT T I I I Read i Flowthrough Pi elined Phase ee d I I Figure 5 10 Syncburst and ZBT SSRAMI Timing DN5000k10 User s Manual 5 9 Memories SDRAM Table 5 2 Syncburst and ZBT SSRAM Timing Address Phase Syncburst CE CE2 CE ADSC or ADSP address or apv CE CE2 CE R W LDZ2 BWx address or ADV BWx4 Write Phase BWE BWx GwZ4 data data Val
121. nd verification purposes so don t be concerned if the screens that you see aren t exactly replicated here In a nutshell AETEST lets you do the following Determine if PCI recognizes the DN5000k10 Read write loop any memory location Read write loop configuration space Display all configured PCI devices Display memory setting from any locations Fill memory with various patterns Run various tests on the DN5000k10 SSRAM Test Multiplier Test SDRAM Test Interconnect Test Daughter Card Test Installation Instructions for DOS 1 The files aetestdj exe and cwsdpmi exe the DOS extender need to be in the same directory 2 Run aetestdj exe Installation Instructions for Windows NT 1 Install the device driver install exe and qldriver sys must be in the same directory 2 Type install 3 After the driver is installed start the driver by selecting Control Panel gt Devices gt find QLDriver gt click Start 4 Runaetestnt exe Installation Instructions for Windows 2000 1 Install the device driver q1driver2000 inf and the driver file qldriver sys should be in the same directory 2 Open Control Panel click on Add Remove Hardware and then go to Next gt 3 Choose Add Troubleshoot a device the default option and click on Next 4 Wait until it finishes new hardware device searching choose Add a new device and click on Next 5 Choose No want to
122. nfigure the FPGA the Smart Media card can contain other files Example of nain txt start of file main txt Verbose level 2 Sanity check y FPGA F fpgaF rbf the line above configures FPGA F a file fpgaF rbf end of main txt Given the above example file e Verbose level is set to 2 e A sanity check on the bit files will be performed e FPGA F will be configured with file fpgaF rbf Starting Fast Passive Parallel Configuration If using the reference design SmartMedia card that came with the DN5000k10 then no files need to be copied to the card Otherwise copy your RBF file and main txt to the root directory of the SmartMedia card using the FlashPath floppy adapter Make sure the switches on S2 are set for Fast Passive Parallel as shown in Table 2 3 Table 2 3 J2 Configuration Jumper Settings Switch 0 Switch 1 Switch 2 MSEL 2 MSEL 1 MSEL 0 Configuration Mode Fast Passive Parallel Passive Serial Set up the serial port connection as described above in Setting up the Serial Port J3 RS232 Port on page 2 19 Next place the SmartMedia card in the SmartMedia socket on the DN5000k10 and turn on the power NOTE the card can only go in one way The SmartMedia card is hot The DINI Group DN5000k10 User s Manual DN5000k10 Features Overview and General Description swappable and can be taken out or put into the socket even when the power is on Once the power has been turned on the
123. nu options after the config uration process is complete Creating Main Configuration File main txt To control which bit file on the Smart Media card is used to configure the FPGA in SelectMAP mode a file named main txt must be created and copied to the root directory of the Smart Media card The configuration process cannot be performed without this file Below is a description of the options that can be set in the file a description of the format this file needs to follow and an example of a main txt file Options Verbose Level During the configuration process there are three different verbose levels that can be selected for the serial port messages Level 0 Fatal error messages Sanity Check errors e g RBF file was created for the wrong part RBF file was created with wrong version of Altera tools or Quartus options are set incorrectly Initializing message will appear before configuration single message will appear once the FPGA is configured 1 messages that Level 0 displays Displays configuration type should be Fast Passive Parallel Displays current FPGA being configured if the configuration type is set to Fast Passive Parallel Displays a message at the completion of configuration for each FPGA configured 2 20 The DINI Group DN5000k10 User s Manual DN5000k10 Features Overview and General Description Level 2 A All messages that Level 1 displays Options tha
124. ock Diagram 5 2 SSRAM FB U22 Bus Signals 5 3 SSRAM AD U23 Bus Signals 5 4 SSRAM AB U21 Bus Signals 5 5 SSRAM ED U18 Bus Signals 5 6 Syncburst FT cuc riu REY ee eere ace e leis 5 8 Syncburst ees Ae hee tx 5 8 Syncburst ZBT 5 9 Syncburst ZBT 5 9 vii List of Figures List of Figures Continued viii FIGURE 5 10 5 11 5 12 6 1 6 2 6 3 7 1 7 2 7 3 8 1 8 2 8 3 8 4 8 5 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 9 10 9 11 9 12 9 13 A 1 A 2 A 3 4 5 TITLE PAGE Syncburst and ZBT SSRAM Timing 5 9 SDRAM J19 Bus Signals Page 1 of 2 5 11 SDRAM J19 Bus Signals Page 2 of 2 5 12 DN5000k10 Power Distribution 6 1 Molex Connector P1 Auxiliary Power 6 3 Example ATX Power Supply 6 4 DN3000k10SD Daughter Card Block Diagram 7 2 DN3000k10SD Daughter Card 7 3 DN3000k10SD Daughter Card Assembly Drawing 7 4 Reset 8 2 DN5000k10 8 3 DN5000k10 LED Diagram 8 3 91294 003 Pin Numbering 8 5 200 Pin Connectors Signal Connections
125. om www numega com Startup When AETEST is first started it tries to find a device that it recognizes We have arbitrarily defined the DN5000k10 with a DEVICE IDOof0x1250 or 0x1251 and a VENDOR ID of 0x17DF We have arbitrarily defined the DN5000k10S with a DEVICE ID of 0x1240 and a VENDOR ID of OxABCD or 0x17DF The DN2000k10 series has a DEVICE ID of 0x1234 0x1235 0x1236 or 0x1237 and VENDOR ID of OxABCD You should see the following screen if AETEST recognizes a DN5000k10 Figure 9 1 searching for DN2000K10 Asic Emulator 1000E VENDOR ID abcd DEVICE ID 1236 searching for DN2000K10 Asic Emulator 1600E VENDOR ID abcd DEVICE ID 1237 searching for DN3000K10S Asic Emulator 6000 VENDOR ID abcd DEVICE ID 1240 found device vabcd d1240 name DN3000K10S Asic Emulator 6000 Configuration space 00 1240abcd 04 0000001f 08 ff000047 0c 00000000 10 fd800000 14 e0000000 18 00000000 1c 00000000 20 00000000 24 00000000 28 00000000 2c 90ab5678 30 00000000 34 00000000 38 00000000 3c 00000000 BARO base Oxfd800000 size 0x00800000 BAR1 base 0xe0000000 size 0x10000000 BAR2 base 0x00000000 size 0x00000000 BAR3 base 0x00000000 size 0x00000000 BAR4 base 0x00000000 size 0x00000000 BAR5 base 0x00000000 size 0x00000000 press any key Figure 9 1 DN5000k10AETEST Startup Screen DN5000k10 Recognized The DINI Group Utilities Most of this initial display is debug in
126. on the DN5000k10 Memory test on SSRAM2 Tests one of the SSRAM chips on the DN5000k10 Memory test on SSRAMS Tests one of the SSRAM chips on the DN5000k10 Memory test on SDRAM Tests the SDRAM chip on the DN5000k10 Full Memory Test Including BlockRAM Tests all of the memo ries This includes the SSRAM chips the SDRAM and the BIockRAM internal to the FPGA DN5000k10 User s Manual 9 13 Utilities Memory test on FPGA block memory Tests the BlockRAM inside the FPGA On the DN2000k10 the BlockRAM is only in FPGA F BAR memory range test Generic memory test that prompts the user for BAR number starting address offset DWORD count and number of iterations The user is also prompted if the program should stop if error occurs or if the program should display any errors that occur This allows for maximum flexibility when debugging a design with an oscilloscope or debugging any memories or memory locations on your PCI bus The memory test is very complete performing a write then a read to every location a read from every location and then a read write read test to every location All other memory test options listed in the memory menu are based on this generic memory test function 9 14 The DINI Group Appendix A Berg Connector Datasheets Figure A 1 and Figure A 2 contain the schematics for the Berg 91403 003 Connector Figure A 3 through Figure A 5 contain the schematics for the Berg 91294 003 connector DN30
127. on to view the entire configuration space Write config uration DWORD Allows write to configuration space The following text will appear to remind you what is in configuration space for a PCI device PCI CS VENDOR ID 0x00 PCI CS DEVICE ID 0x02 PCI CS COMMAND 0x04 PCI CS STATUS 0x06 PCI CS REVISION ID 0x08 PCI CS CLASS CODE 0x09 PCI CS CACHE LINE SIZE 0x0c PCI_CS MASTER LATENCY 0x0d PCI_CS HEADER TYPE 0x0e PCI CS BIST Ox0f PCI CS BASE ADDRESS 0 0x10 PCI CS BASE ADDRESS 1 0x14 PCI CS BASE ADDRESS 2 0x18 PCI CS BASE ADDRESS 3 0 1 PCI CS BASE ADDRESS 4 0x20 PCI CS BASE ADDRESS 5 0x24 PCI CS EXPANSION ROM 0x30 PCI CS INTERRUPT LINE 0x3c PCI CS INTERRUPT PIN 0x3d PCI CS MIN GNT 0x3e PCI CS MAX LAT 0x3f Input config offset hex 0x00 0xff word to write in hex Loop indefinitely y or n If looping was selected any keypress will stop the loop 9 8 The DINI Group Memory Menu Utilities Read config uration DWORD Allows read from configuration space Has options for single read loop read with display and loop read without display Configure BARs from File Reloads the PCI configuration of the active device from a file It writes Ox001F to the command register and writes the 6 bars with the values from the file This is useful for hot swap ping devices power switch still required on extender or reinitializing a device when its configuration has been altered WARNING Because the PCI BIOS is not as
128. onfiguration Header Name on Cable Name on Schematic Serial Mode JTAG Mode DCLK TCK CONF DONE TDO CONF DONE DATAO TDI DATAO nCONFIG TMS nCONFIG nSTATUS nSTATUS GND GND vec VCC The FPGA on the DN5000k10 can be configured in Fast Passive Parallel mode using a Smart Media card Fast Passive Parallel configuration is the easiest and quickest way to configure the FPGA The DN5000k10 is shipped with two 32 MB Smart Media cards One of these Smart Media cards contains reference design bit files produced for Fast Passive Parallel configuration and files main txt and iotst txt that sets options for the configuration process for description of options see Creating Main Configuration File main txt on page 2 20 This Smart Media card has been labeled with a sticker marked reference design The other Smart Media card is empty and is for use with your own designs To configure the FPGA with the reference design please skip to Starting Fast Passive Parallel Configuration on page 2 22 Creating RBF Files for Fast Passive Parallel To create an RBF file with Quartusll software Go to Assignments menu and drag down to Settings Click on Device under Compiler Settings on the left then click the Device amp Pin Options button on the right Go to the Configuration tab select Configuration Scheme Fast Passive Parallel and disable the option to Use Configura tion Device Go to th
129. onnectors for logic analyzer based debugging or for pattern generator stimulus Custom daughter cards such as the DN3000k10SD can be mounted to these connectors as a means of interfacing the DN5000k10 to application specific circuits A reference 32 bit PCI target design and test bench is provided in Verilog at no additional cost A Smart Media EPM3256A FPGA Switching 3 3V 10A 16 32 64 Mbyte A n 45V 16 3264 Mbyte 32kx8 SRAM CPLD Configuration Power m storage ATmega103L Supply 10A Flash based uP FPGA Configuration Controller 190 69 AB FlowThrough Pipelined d ECLK SSRAM 512k x 36 FPGA FPGA A vU B U19 EP1S80 EP1S80 FF1508 FF1508 28 E ae eg 256 AD FlowThrough Pipelined lt SSRAM 512k x 36 FB FlowThrough lt Pipelined SSRAM 512k x 36 ECLK F PG BCLK D U20 CCLK EP1S80 EP1S80 EP1S80 1508 1508 1508 lt lt oclock LL 1 Roboclock ECLK PLL 2 SDRAM 168 pin DIMM Up to 1GB x 64 FlowThrough Pipelines b SSRAM 512k x 36 32 64 Bit PCI PCI X DN5000k10 REV 10 8 03 DE 2 2 Figure 2 1 DN5000k10 Block Diagram The DINI Group DN5000k10 Features Overview and General Description Easy The configuration bit files for the FPGA are copied onto a 32 megabyte Configuration SmartMedia FLASH card provided and an on board m
130. ore attempting to go to the next We provide utilities to help with each step Steps 1 and 2 are best done without an operating system in place Windows NT based systems take minutes to reboot after a crash the BLUE screen of death and an NT driver won t work unless the hardware is debugged Since crashing is a regular occurrence in a PCI hardware debug environment we find it easiest to do our debug and manufacturing test in the old DOS environment Virtually all PCI peripherals get configured with addresses beyond the IM boundary On a PC C programs cannot access memory locations beyond IM unless special programs called DOS extenders are used Several freeware DOS extenders are available We use a free DOS extender called DJGPP More information can be found at http www delorie com DJGPP PC Based AETEST EXE A utility program called AETEST is provided with the DN5000k10 AETEST can be run under DOS Windows 98 ME Windows NT 2000 or LINUX When used under DOS you must boot your PC with a DOS disk We ship one with the DN5000k10 in case you don t know how to make one on your own All features work in the native mode of AETEST which is DOS DN5000k10 User s Manual 9 1 Utilities AETEST Utility 9 2 Installation Instructions All source code for AETEST is provided so you are welcome to customize the program to your own applications AETEST is not a stable program We add and subtract features when we need to for debug a
131. otal power requirements of the add in card The JP1 PCI X Present Header is shown in Figure 3 4 JP1 Figure 3 4 JP1 PCI X Present Header Table 3 1 shows the Present Signal Definitions for PCI PCI X Table 3 1 Present Signal Definitions PRSNT1 PRSNT2 Expansion Configuration Open Open No expansion board present Ground Open Expansion board present 25W maximum Open Ground Expansion board present 15W maximum Ground Ground Expansion board present 7 5W maximum We have never seen the present signals used anywhere but we have heard of systems that will not PNP Plug and Play configure a PCI board if both the present pins are left open We recommend installing a jumper in location 1 2 for PRSNT1 or 3 A for PRSNT2 or both JP2 M66EN 66MHz Enable The 66MHz ENABLE pin M66EN indicates to the host whether the device can operate at 66 MHz or 33 MHz Section 7 5 1 in the PCI Specification 2 2 provides the gory details For 33 MHz only FPGA designs install a jumper between pins 3 and 4 For 66 MHz capable designs install a jumper between pins 1 and 2 instead Table 3 2 shows the jumper descriptions for M66EN Table 3 2 M66EN Jumper Descriptions meer Busen Pins 3 4 Pins 1 2 DN5000k10 User s Manual 3 5 PCI 3 6 TP7 PME Power Management Enable This board does not have built in support for PME power management enable Connecting PME to an FPGA that is not powered is a ba
132. ou can configure the FPGA using the JTAG cable The 48 MHz clock can be divided down in the CPLD and used to drive the PWB clock network See Chapter 4 for a more detailed description of this option Notes on Header J7 Fast Passive Parallel using the SmartMedia card is the best way to configure the FPGA Two other options exists if for some reason the SmartMedia card method is not applicable 1 Serial Programming Using the Cable Header J7 has the 5 serial con nections that are used to configure the FPGA using the serial method Table 2 2 has the pinouts Note that this is a back off position to SmartMedia and JTAG and should only be used in dire circumstances Note also that the switches on J2 will need to change to reflect slave serial configuration DN5000k10 Features Overview and General Description Fast Passive Parallel Configuration 2 18 Instructions 2 JTAG Programming The JTAG connection can be used to configure the FPGA and can also be used to connect the SignalTap Logic Analyzer See Application Note 175 at www altera com literature lit qts html or other solu tions such as the Bridges2silicon system which was recently acquired by Synplicity see www bridges2silicon com The JTAG method of configuration should be used if the SmartMedia method isn t work ing Remember that programming a Stratix part through JTAG uses a sof file nota rbf file Table 2 2 has the pinouts Table 2 2 FPGA Serial JTAG C
133. ptional as shown by Figure 2 6 which is a detailed view of a single 18x18 bit or 9x9 bit multiplier Any or all of the registers may be used to pipeline the multiplier logic and improve the clock speed or the alternate path may be used to bypass the register Figure 2 6 also shows more detail about the optional shift register path which makes FIR or IIR filters easy to implement Most synthesis tools will accept Verilog or VHDL descriptions of multpliers and infer a DSP block with the appropriate configuration For those that don t Altera provides a megafunction generator to help with direct instantiation of the hardware resources See Synthesis and Emulation Issues on page 2 26 for more detail sign a 1 sign b 1 aclr 3 0 clock 3 0 ena 3 0 shiftin B shiftin A Result D D Q to Adder lena blocks I Optional Multiply Accumulate and Multiply Add Pipeline gt CLRN Q shiftout A Figure 2 6 Multiplier Sub Component Block Diagram The DINI Group DN5000k10 Features Overview and General Description I O Issues Terminator technology is supported on all pins The resistors used for RDN and RUP should be 250 ohms for series termination or impedance matching I O standards Parallel termination requires 1000 ohm resistors for RDN and RUP Terminator technology is a very nice feature and we recommend you use it on all I O signals The default IO STANDARD attribute for the CSF file is LVTL
134. r Card provides a 200 pin connector to inter face to one of three test connectors on the DN5000k10 ASIC prototyping board J9 J10 and J16 J1 Test Interface Connector Micropax connector 200 pin used as a standard interface to all the DINI Group development boards This connector has a specified current rating of 0 5 amps per contact See Table 7 2 on page 7 8 Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors Daughter Card I O Connections Table 7 2 shows the DN3000k10SD Daughter Card I O Interconnects to connectors J25 J26 and J28 Table 7 2 DN3000k10SD Daughter Card I O Interconnects Daughter Card DN5000k10 I O Connector Connections Header J9 Header J10 Header J16 J9 J10 or J16 Signal Pin No Signal FPGA FPGA Pin i FPGA Pin i Signal Pin Signal 12 V 12 V 12 V GND GND GND 1 ACLK 7 ACLK 6 ACLK 5 45V 45V 45V 45V BCLK 1 BCLK 7 BCLK 6 BCLK 5 45V 45V 45V 45V CCLK 1 CCLK 7 CCLK 6 CCLK 5 GND GND GND GND 3 3 V 3 3 V 3 3 V 3 3 V P2N 3 HDR ECLK 14 ECLK 13 CLKOUT GND GND GND GND P2N 2 AD 149 U20 AH15 FB 135 U11 AN27 AB 172 U19 AT33 P2N 1 AD 148 U20 AH14 FB 141 U11 AH22 AB 171 U19 AP32 P2N 0 AD 151 U20 AM15 FB 140 U11 AF21 AB 170 U19 AR32 P2NX 7 AD 150 U20 AL15 FB 139 U11 AC26 AB 169 U19 AT32 P2NX 6 AD 152 U20 AK14 FB 138 U11 AB2
135. ramming FLASH using block mode 100 OK Leaving programming mode OK After programming the processor close all AVR Studio windows and setup the serial port according to the section titled Setting up the Serial Port J3 RS232 Port on page 2 19 Please note that in this situation connecting the serial port is mandatory and the FPGA can not be configured via the SmartMedia card until you have completed all the instructions in this section Reset the DN5000k10 by pressing S1 After about 5 seconds you should see the following in the HyperTerminal window k k NEERD FPGA STUFFING INFORMATION Enter number of FPGAs on Board 1 6 Using the keyboard enter the number of FPGAs on the board should be between 1 and 5 for the DN5000k10 After you have entered this you should see the following query Please select the FPGA on the board F A E B or D Enter one of the FPGA locations on your board that contains an FPGA and you should see the following menu 1 Virtex II 1000 FG456 2 Virtex II 6000 FF1152 3 Virtex II 4000 FF1152 4 Virtex II 3000 FG676 5 Virtex II 8000 FF1152 The DINI Group CPLD EPM3256A DN5000k10 User s Manual 10 DN5000k10 Features Overview and General Description 6 Altera Apex II 2A40 7 Altera Apex II 2A70 8 Altera Stratix EP1S80F1508C7 Please enter selection 1 6 for FPGA D Enter option 8 for Stratix FPGAs Then repeat these two steps for e
136. ration Menu and allows the FPGA to be configured through a set of menu options instead of using the main txt file The menu options are described below Description of Interactive Configuration Menu options 1 Select a bit file to configure FPGA s This menu option allows the user to select a file from a list of files found on the SmartMedia card to use to configure the FPGA 2 Set verbose level current level 2 This menu option allows the user to change the verbose level from the current setting Please note if the user goes back to the main menu and configures the FPGA s using main txt the verbose level will be set to whatever setting is specified in main txt 3 Disable Enable sanity check for bit files This menu option either allows the user to disable or enable the sanity check depending on what the current setting is Please note if the user goes back to the main menu and configures the FPGA s 2 23 DN5000k10 Features Overview and General Description SmartMedia 2 24 using main txt the sanity check will be set to whatever setting is specified in main txt M Main menu This menu option takes the user back to the Main Menu described above Check Configuration status This option checks the status of the DONE pin and prints out whether or not the FPGA s have been config ured along with the file name that was used for configuration Select file to use in place of main txt By default the p
137. resenting a substantial investment of time and money Prototype boards from manufacturers can meet this demand for experi mentation while eliminating the expense and time involved with custom PC boards Additionally such prototype boards facilitate the under standing and advantages of new device features Purpose The DN3000k10SD daughter card allows external connection to the signals present on the DN5000k10 series ASIC prototyping boards The DN5000k10 allows logic emulation with Stratix devices prior to commit ting to using them for specific applications It allows designers to try Stratix features such as BlockRAM DLLs and Selectl O resource with an off the shelf resource Features The DN3000k10SD Daughter Card has the following features e Buffered I O Passive and Active Bus Drivers e Unbuffered I O e Differential LVDS pairs Note Not available on DN5000k10 ASIC prototyping board e Headers for Test Points The daughter card contains headers that may be useful with certain types of oscilloscope probes or when wiring pins to prototype areas Figure 7 1 is a block diagram of the DN3000k10SD Daughter Card The DN3000k10SD Daughter Card is pictured in Figure 7 2 Figure 7 3 shows the assembly drawing of the DN3000k10SD Daughter Card The DN3000k10SD Daughter Card provides 16 differential pairs 48 buff ered passive active I O and 66 unbuffered I O signals The DN5000k10 User s Manual 7 1 Daughter Connect
138. riptions Headers J11 J12 J15 and J18 are used to control the PLLs Each header consists of GND pins in row A various PLL inputs in row B and 3 3 V pins in row C The layout of the headers is shown in Figure 4 7 The Header Classifications are shown in Table 4 2 Table 4 2 Header Classification Group I General Control DN5000k10 User s Manual 4 7 Clocks and Clock Distribution Clock A i I ROBOCLOCK1 Control Logic I Detector Generator Selection I I I I I I Clock Frequency Divide and Phase Matrix I I L Divide and Phase select Matrix Divide and Phase select Matrix Divide and Phase select Matrix Divide and Phase select Matrix Divide and Phase select Matrix ROBOCLOCK2 PLLSEL2 MODE1 Duplicate of Clock A Divide and arno See details above Phase select Matrix 5 or J11 B 1051 xi c Bie au gunun INR lt Divide an FBEDI 1 EKI 4DS0 gt Phase select i H 4ps143 gt Matrix FBDS01 FBDS11 d E A sri Divide and FS2 q 3DS0 gt Phase select 8ps143 Matrix I 3 INV3 I i el gt 2Fo 35 I 2F1 ES Divide and i NIS ao E Phase select l sei gt Matrix gt 1F0 I 1F1 ES Divide and i lt 1080 Phase select pi Matrix i Figure 4 6 Functional Diagram of Roboclock 1 and Roboclock 2 4
139. rocessor uses the file main txt to get the names of the files to be used for configuration as well as options for the configuration process How ever a user can put several files that follow the format for main txt on the SmartMedia card that contain different options for the config uration process By selecting the main menu option 4 the user can select a txt file from a list of files that should be used in place of main txt After selecting a new file to use in place of main txt the user should select Main Menu option 1 to configure the FPGA S according to this new file If the power is turned off or the reset but ton S1 is pressed the configuration file is changed back to the default main txt List files on SmartMedia This option prints out a list of all the files found on the SmartMedia card Select FPGA to Program with JTAG This option must be set to enable an FPGA before it can be programmed through JTAG The configuration file for the FPGA is copied to a SmartMedia card using the SmartDisk FlashPath Floppy Disk Adapter The approximate file size for each possible Stratix FPGA is shown below in Table 2 4 Note that several files can be put on a 32 megabyte card We supply two 32 mega byte SmartMedia cards with the DN5000k10 SmartMedia is a standard so you can get more SmartMedia cards if you want The DN5000k10 requires a 3 3 V card Card sizes of 16 32 64 and 128 megabytes have been tested on the DN5000k10 We ha
140. rt any power rails or signals to these metal bars they can carry a lot of current The PCI bracket BRK1 is also connected to the ground plane at each of the screw mounts The 200 Pin Connectors J9 J10 J16 8 4 The DN5000k10 contains three 200 pin connectors J9 J10 and 116 Daughter cards of any sort may be plugged into these connectors The relative pin location of the powers grounds and signals is identical for each of the three connectors with the exception of a clock output on J9 A hole that can be used to attach a standoff is located at the same relative position from each connector seeFigure 8 4 This hole is grounded on the DN5000k10 so connect this mounting hole to digital ground on your daughter card The mechanical position of the 200 pin connectors on the DN5000k10 is shown in Figure 8 4 The 200 pin connector used on the DN5000k10 is a Berg Electronics 91294 003 in the Micropax family This link will take you to the Berg website http www berg com This Berg connector was chosen because of its high pin density performance and availability The part number for the mating connector is 91403 003 We stock the mating connector at our offices in La Jolla CA so if you are designing a daughter card and are having trouble getting this part call us We would be happy to send you a few at our cost Appendix A contains a mechanical datasheet for both the Berg 91403 003 and 91294 003 connectors This style of connector
141. s correct For more information check www altera com for the Stratix datasheet The flip flop in each LE includes a clock enable input an asynchronous preset and reset synchronous set and reset logic and an asynchronous load function Data input can come from the LUT in the same LE to register addition or boolean outputs or the LUT and FF can be used inde pendently of each other For more information check www altera com for the Stratix datasheet Register chain routing from previous LE LAB wide Register Bypass Synchronous Load Programmable LAB wide Packed Synchronous Register Select LUT chain A routing to next LE E is Row column Synchronous B E B and direct link Load and routing Clear Logic ADATA E Row column gm L Jen l routing Register chain Register output Feedback Carry OutO Carry Out1 LAB Carry Out Figure 2 3 General LE Diagram 2 5 DN5000k10 Features Overview and General Description Embedded Memory Multipliers 2 6 Stratix has boatloads of embedded memory The EP1S80 contains 767 blocks of 576 bits 364 blocks of 4 5 Kbits and 9 blocks of 576 Kbits The smallest memory blocks called M512 RAM can be configured for data widths ranging from 32 x 18 bits to 512 x 1 bit medium sized blocks MAK RAM can be configured ranging from 128 x 36 bits to 4K x 1 bit and the largest blocks M RAM can be configured anywhere from 4K x 144 bits to 64K x 9 bits The embedde
142. should appear with the title STK500 At the bottom of the STK500 window if you see Detecting FAILED that means either there is no power on the DN5000k10 there is another program open that is using the serial port or the serial cable connecting the AVR tool is not connected properly If this happens you should close down the window titled STK500 correct the situa tion and then select TOOLS gt STK500 AVRISP JTAG ICE again You 2 13 DN5000k10 Features Overview and General Description will not be able to continue unless you see something very similar to the following at the bottom of the STK500 window Detecting AVRISP found on COMI Getting revisions HW 0x01 SW Major 0x01 SW Minor 0x07 0K On the PROGRAM tab select the ATmega128 under the DEVICE drop down menu and in the FLASH section where it says INPUT HEX FILE browse and select the file DN5000k10 128 290 that can be found in the downloaded zip file 0 CPLD zip from the Dini Group web site To program the device all you need to do is hit the PROGRAM but ton in the FLASH section When the programming is complete it takes about 45 seconds you should see a message at the bottom of the window that looks something like this Detecting AVRISP found on COMI Getting revisions HW 0x01 SW Major 0x01 SW Minor 0x07 0K Reading FLASH input file OK Setting device parameters serial programming mode OK Entering programming mode OK Erasing device OK Prog
143. signing the BARs for this device you may induce a memory conflict by using this option This option is for advanced users only Save Bar Configuration to File writes PCI Device ID Vendor ID and the BARs into a file from the active device This option is for advanced users only The memory menu Figure 9 5 allows you to perform a variety of tests of PCI memory along with some DN5000k10 specific tasks 1 3 8 9 a b c d e f g n p u M 0 des ASIC Emulator PCI Controller Driver v8 2 Read Memory Test 4 Memory Fill Write To Memory Test Write Read Test Memory Display Write Memory Byte Read Memory Byte Write Read Memory Byte memory test on SSRAM 1 memory test on SSRAM 2 memory test on SSRAM 3 memory test on SDRAM full memory test including blockram memory test on FPGA block memory bar memory range test SRAM memory test Main Menu Q Quit PCI BASE ADDRESS fd800000 1 e0000000 2 00000000 00000000 4 00000000 5 00000000 Figure 9 5 AETEST Memory Menu DN5000k10 User s Manual 9 9 Utilities Write to Memory Test write a selected number of long words to a specific PCI memory location Figure 9 6 Numbers Memory location hex 5000000 long word to write in hex aaaaaaaa long word to write in hex 55555555 Loop indefinitely y or n Hit a key to continue of long words to write in decimal 2 Fi
144. t are found in main txt file names for each FPGA as entered in main txt Maker ID Device ID and size of Smart Media card AI files found on Smart Media card If sanity check is chosen the RBF file attributes will be dis played part package date and time of the RBF file During configuration a will be printed out after each block 16 KB has successfully been transferred from the Smart Media to the current FPGA Sanity Check The Sanity Check if enabled verifies that the RBF file was created for the right part the right version of Altera was used and the Quartus options were set correctly If any of the settings found in the RBF file are not compatible with the FPGA a message will appear from the serial port and the user will be asked whether or not they want to continue with the RBF file Please see the section Creating RBF Files for Fast Passive Parallel on page 2 18 for details on which Quartus options need to be changed from the default settings Format The format of the main txt file is as follows The first nonempty uncommented line in main txt should be Verbose level X where X can be 0 1 or 2 If this line is missing or X is an invalid level then the default verbose level will be 2 The second nonempty uncommented line in main txt tells whether or not to perform a sanity check on the bit files before configuring an FPGA Sanity check y where y stands for yes n for no If
145. th the 200 pin connectors The exceptions that are not on the connectors are pins ZZ OE and CE So if an SSRAM is not needed one of the FPGAs connected to it may drive ZZ high putting the SSRAM to sleep so that it does not interfere with the 200 pin connector Alternatively the 200 pin connector is available to probe SSRAM signals for debugging purposes However if someone wanted to design a system where hard ware on a daughtercard can access an SSRAM directly some rework would be needed to connect it to the OE and CE pins The connections between the FPGAs and the SSRAMS is shown in Figure 5 1 The signal connections for SSRAM FB are shown in Figure 5 2 The signal connections for SSRAM AD are shown in Figure 5 3 The signal connections for SSRAM AB are shown in Figure 5 4 The signal connections for SSRAM ED are shown in Figure 5 5 Flowthrough SSRAMs are functionally the closest to ASIC style memories Pipeline SSRAMs can be clocked at faster frequencies ZBT SSRAMs are typi cally one generation behind in density The subtle differences between the styles of memories are described in the next section Memories J10 J16 MB 156 SSR AB AF 252 MB 154 153 FB 152 33 Es fine y AB 176 94 AB 70 aer AB 85 84 AB 68 1 AF 83 80 AB 82 33 AB 29 1 r e Q FB 129 FB 75 40 FPGA B FB 32 1 AF 79 77 19 AF 8 1 SSRAM AD AD 152 33 AD 74 38 AD 29 0 AD 32 1 FPGA F FPGA E FPGA D U11 U15 U20 ED 68 1
146. ting Started This manual uses the following conventions An example illustrates each convention The term PCI X will be used generically unless there is a specific instance where PCI applies This design guide generically refers to PCI X protocol When the PCI X HalfBridge core is in PCI mode PCI protocol will be followed Courier font denotes the following items Signals on PCI Bus side of the PCI X Interface FRAME IO PCI X Interface signal name FRAME PCI X Bus signal name Signals within the user application BACK UP START Command line input and output setenv XIL MAP LOC CLOSED HDL pseudocode assign question to be to be assign cannot have cake amp eat it Design file names pcim top v pcim top vhd Courier bold denotes the following items Signals on the user side of the LogiCORE PCI X Interface ADDR VLD Menu selections or button presses FILE gt OPEN Italic font denotes the following items Variables in statements which require user supplied values ngdbuild design name References to other manuals See the Libraries Guide for more information 1 3 Getting Started 1 4 Emphasis in text It is not a bug it is a feature Dark shading indicates items that are not supported or reserved SDONE I in out Snoop Done signal Not Supported Square brackets indicate an optional entry or a bus index ngdbuild option name design name DA
147. to Next DSP Block in the Column DN5000k10 User s Manual DN5000k10 Features Overview and General Description Multiplier Stage Optional Stage Configurable Output Selection as Accumulator or Dynamic Multiplexer Adder Subtractor gt D CLRN Adder Subtractor Accumulator 1 Optional Output Summation Stage Register Stage for Adding Four Multipliers Together Adder Subtractor Accumulator 2 Optional Pipeline Register Stage Optional Input Register Stage with Parallel Input or Shift Register Configuration to MultiTrack Interconnect Figure 2 5 DSP Block Diagram Summation pj p 2 7 DN5000k10 Features Overview and General Description Data A Data B 2 8 www altera com has more detailed information on how the multipliers and adders are configured for some common functions Figure 2 5 shows a DSP block configured for four 18x18 bit multipliers A DSP block can be configured as two parallel systems of 9x9 bit multipliers each of which is also described by Figure 2 5 The adder blocks can be used to add or subtract two or four multipliers such as in complex multi plication or to add a new result each clock cycle to an accumulated sum They are also used to configure the DSP block as a 36x36 bit multiplier with or without an accumulator All registers in Figure 2 5 are o
148. to 4 17 PLLIA 4 3 to 4 4 4 10 4 17 PLL1B 4 13 PLLIB N 4 10 PLLIB 4 3 The DINI Group Index Continued PLLIBN 4 13 PLLIBN 4 3 to 4 4 PLL2B 4 13 to 4 14 PLL2B N 4 10 PLL2B PRE 4 3 PLL2BN 4 13 to 4 14 PLL2BN 4 3 to 4 4 PLLSEL2 4 10 Processor Signals BCPUCLK 2 17 R W 5 10 RB C F F 4 10 4 13 RST 3 4 9 1 TCK 2 17 to 2 18 3 4 TDI 2 17 to 2 18 3 4 TDO 2 17 3 4 TMS 2 17 3 4 TRST 3 4 SmartMedia 2 1 2 3 2 9 to 2 10 2 14 to 2 15 2 17 to 2 18 2 22 to 2 24 9 1 configuration 2 1 2 3 2 20 2 24 8 3 speed 2 1 2 15 2 17 3 6 4 1 5 8 7 6 speed grade 2 3 3 1 speeds 3 1 SRAM 2 10 2 15 5 1 6 2 SSRAM 4 16 5 1 5 3 to 5 10 9 2 9 13 ssram 5 1 Startup 9 4 static electricity 1 1 DN5000k10 User s Manual Index Stratix 1 2 2 1 2 3 2 5 to 2 6 2 9 to 2 10 2 15 2 17 to 2 18 2 24 2 27 3 1 3 4 4 16 to 4 17 6 2 to 6 3 7 1 Synopsys 2 26 Synplicity 2 1 to 2 2 2 18 2 26 synthesis 1 2 2 26 synthesis tools 2 26 T target design 2 2 TCK 2 17 to 2 18 3 4 TDI 2 17 to 2 18 3 4 TDO 2 17 3 4 technical support 1 1 terminator technology 2 9 TMS 2 17 3 4 TRST 3 4 V Vendor ID 9 7 to 9 9 verbose level 2 20 to 2 23 Verilog 1 2 2 2 2 8 2 15 2 19 2 26 VHDL 1 2 2 8 2 26 voltage 2 9 2 11 2 19 3 4 4 11 4 13 6 2 7 5 to 7 6 1 5 Index Index Continued 1 6 The DINI Group
149. unction Displays the Vendor ID and Device ID of the active device and function number In the example above this would display the Vendor ID and Device ID of the PCI device at device number 0x7F function number 0x00 Loop on PCI device fun 7f 0 and Display Vendor and Device ID Reads and displays the Vendor ID and Device ID of the active device number and function number Repeats this action until the user hits a key to stop it DN5000k10 User s Manual 9 7 Utilities Loop on PCI device fun 7f 0 and Don t Display Vendor and Device ID Same as previous menu option except doesn t display results This menu option is useful when using an oscilloscope to debug configuration reads Loop on all PCI device numbers and Display Device Vendor ID s Loops on each device number reading the Vendor ID and Device ID for each It moves onto the next device number when you press any key That is it continually reads the Vendor ID and Device ID from device number 0 until you hit a key at which point it continually reads the Vendor ID and Device ID from device number 1 It moves all the way through device number 0 to device number 0x7F in case there are any bridges on your PCI bus Display all PCI information for PCI device function 71 0 Reads and displays all of the configuration space for the active device and function number Use options S and F to change between the active device number and function number and then use this opti
150. ve not seen 256 MB or larger cards for sale yet but when we do there will probably be an update to the CPLD and processor on our website to support them Table 2 4 Stratix FPGA Approximate File Sizes Number of Configuration Bytes Stratix FPGA SOF for EP1S80 2 954 672 RBF for EP1S80 2 992 071 We get our SmartMedia cards from http www computers4sure com A Delkin Devices 16 megabyte card part number DDSMFLS2 16 sells for about 15 A 32 megabyte card part number DDSMFLS2 32 will set you The DINI Group DN5000k10 Features Overview and General Description back about 20 see Figure 2 13 New SmartMedia cards do not require formatting before use NOTE SmartMedia cards do not need to be formatted before they are used The Windows format command does not work it is necessary to use the FlashPath utility to format a SmartMedia card omar Figure 2 13 Delkin 32 MB 3 3 V Smart Media Card Do not press down on the top of the SmartMedia Connector J1 if a Smart Media card is not installed The metal case shorts to the 43 3 V power supply and the case gets hot enough to burn your finger We suggest that you leave a SmartMedia card in the connector to prevent this from occur ring A polyswitch fuse F1 has been added so that the PWB and the SmartMedia connector are protected if you do accidently press on the top of the connector NOTE Do NOT press on the SmartMedia Connector J2
151. y result and loop indefinitely Figure 9 8 AETEST Write Read Test You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be read The program will prompt for the number of long words you with to write 1 to 1024 Three options are available 1 2 3 Read once and display Read indefinitely and display Read indefinitely and don t display Option 3 is a very useful scope loop Memory Fill Fill memory with a selected pattern Figure 9 9 Fill with O0 address data 0x55555555 Oxaaaaaaaa Oxffffffff data address Q P OO N Pp l I Input starting address hex and 32 bit aligned f b000000 Input number of bytes divisible by 4 1000 Figure 9 9 AETEST Memory Fill You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be written The program will prompt for the number of bytes in hex you wish to fill 4 to ox fffffc The following fill options are available 1 P pe od DN5000k10 User s Manual fill with 0 fill all the locations with 0x00000000 clear the memory address data fill each long word with its address alternating 0x55555555 OXAAAAAAAA Oxffffffff set all of memory data address fill each long word with the address each bit inverted Utilities Memory Display Display 160 long words of memory You are pro
152. you use the DN5000k10 stand alone with an ATX power supply the DN5000k10 may not draw enough current to meet the minimum current required by the switchers in the supply Connecting a disk drive to another connector will solve this problem P1 12V 9 Figure 6 2 Molex Connector P1 Auxiliary Power DN5000k10 User s Manual 6 3 Power Supplies and Power Distribution Figure 6 3 Example ATX Power Supply By specification a PCI board may consume a maximum of 25 watts from the fingers of the PCI connector This power limit is below that the DN5000k10 is capable of consuming even if daughter cards and or large SDRAM banks are installed The P1 connector can be used to augment the power obtained from the PCI fingers P1 can be used provided that the 5 V and 12 V power rails on the connector are supplied by the same power source as the PCI fingers NOTE P1 and PCI may provide power at the same time but ONLY if the same power source used to supply P1 is also supplying power to PCI 6 4 The DINI Group Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors Chapter 7 Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors The traditional approach to experiment with new devices involving wiring together some ICs on a breadboard is fast becoming impractical and inef fective Instead designers using new high density devices need custom PC boards rep

Download Pdf Manuals

Related Search

Related Contents

快 適 な ド ラ イ ビ ン グ を サ ポ ー ト す る  報告1 課題と今後の取り組みについて(PDF:442KB)  User Manual MP113E - Physik Instrumente  Télécharger  BLACK BULL PPWASH20 Use and Care Manual  Manual B-Speech Linga(es)  Cooper Lighting DE641 User's Manual  Cables Direct Cat6 Patch  保証書付  内食派にうれしい。  

Copyright © All rights reserved. Failed to retrieve file