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ADC128D818 12-Bit, 8-Channel, ADC Sys

1. GPO2 GPO3 An external temperature sensor can be connected to any of ADC128D818 s eight single ended input for additional temperature sensing One such temperature sensor can be TI s LM94022 a precision analog temperature sensor with selectable gains The application diagram shows LM94022 s gains GS1 and GSO both grounded indicating the lowest gain setting Four possible gains can be set using these GS1 and GSO pins According to the LM94022 data sheet SNIS140 the voltage to temperature output plot can be determined using the method of linear approximation as follows VaV1 V2 V1 T2 T1 x T T1 where e VisinmV e Tisin C V1 and T1 are the coordinates of the lowest temperature and T2 and V2 are the coordinates of the highest temperature 8 For example to determine the equation of a line over a temperature range of 20 C to 50 C first find V1 and V2 relative to those temperatures then use Equation 8 to find the transfer function V 925 mV 760 mV 925 mV 50 C 20 C x T 20 C 9 V 5 50 mV C x T 1035 mV 10 For more information and explanation of this example refer to the LM94022 SNIS140 data sheet Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 37 Product Folder Links ADC 128D818 I TEXAS INSTRUMENTS ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 www ti com 9 3 4 Bridge Sensors LM4140 Bridge
2. Code External VREF 5 V V 5 V for Unit 28 Units 0 75 1 5 0 50 1 0 10 25 a 0 5 m l m A ii A E 0 00 A AWT mA T a 0 0 Zz l Zz Q m 0 25 0 5 0 50 1 0 0 75 1 5 0 1050 2100 3150 4200 0 1050 2100 3150 4200 CODE CODE Figure 12 DNL vs Code External VREF 2 56 V for 1 Unit Figure 13 DNL vs Code External VREF 2 56 V for 28 Units Submit Documentation Feedback 11 Product Folder Links ADC128D818 ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 Typical Characteristics continued The following typical performance plots apply for the internal VREF 2 56 V V 3 3 V Pseudo Differential connection I TEXAS INSTRUMENTS www ti com unless otherwise specified All limits T T 25 C unless otherwise specified 0 040 0 025 0 024 0 023 0 030 Q g amp 0 022 a a O O 0 021 frd fh 0 020 fy 0 020 m m Ta a 0 019 E E 0 018 O 0 010 oe 0 017 0 016 0 000 0 015 3 2 3 7 4 1 4 6 5 0 5 5 50 0 14 0 22 0 58 0 94 0 130 0 V V TEMPERATURE Figure 14 Offset Error vs V Figure 15 Offset Error vs Temperature 0 100 0 230 0 075 0 188 0 050 00235 X 0 146 O O 6 939E 18 fe lw Lu Zz Z 0 104 Zz 0 025 z 0 0 0 050 0 062 0 075 0 100 0 020 3 0 3 5 4 0 4 5 5 0 55 50 0 14 0 22 0 58 0 94 0 1
3. Vso Electrostatic discharge ei aaa model CDM per JEDEC specification JESD22 1000 V Machine model 300 1 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process 2 JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links ADC128D818 ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 7 3 Recommended Operating Conditions over operating free air temperature range unless otherwise noted l TEXAS INSTRUMENTS www ti com MIN MAX UNIT Supply Voltage V 3 5 5 V Voltage on SCL SDA AO A1 INT 0 05 5 5 V Voltage on INO IN7 VREF 0 05 V 0 05 V Temperature Range for Electrical Characteristics 40 125 C Operating Temperature 40 125 C 1 All voltages are measured with respect to GND unless otherwise specified 7 4 Thermal Information ADC128D818 THERMAL METRIC PW TSSOP UNIT 16 PINS Resa Junction to ambient thermal resistance 130 C W 1 For more information about traditional and new thermal metrics see the Semiconductor and IC Package Thermal Metrics application report SPRA953 7 5 DC Electrical Characteristics The following specifications apply for 3 Vpc V lt 5 5 Vpc External VREF 2 56 V unless
4. 380 0 002 0 360 0 002 0 340 0 001 Oe 30 35 40 45 50 55 60 25 30 35 40 45 50 55 6 0 V V V V Figure 22 l vs V in Shutdown Mode Figure 23 l vs V in Deep Shutdown Mode Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 www ti com 8 Detailed Description 8 1 Overview The ADC128D818 provides 8 analog inputs a temperature sensor a delta sigma ADC an external or internal VREF option and WATCHDOG registers on a single chip An C Serial Bus interface is also provided The ADC128D818 can perform voltage and temperature monitoring for a variety of systems The ADC128D818 continuously converts the voltage input to 12 bit resolution with an internal VREF of 0 625 mV LSb Least Significant bit weighting yielding input range of 0 V to 2 56 V There is also an external VREF option that ranges from 1 25 V to V The analog inputs are intended to be connected to several power supplies present in a variety of systems Eight inputs can be configured for single ended and or pseudo differential channels Temperature can be converted to a 9 bit two s complement word with resolutions of 0 5 C per LSb The ADC128D818 provides a number of internal registers These registers are summarized in Table 19 The ADC128D818 supports Standard Mode Sm 100 kbps and Fast Mode Fm 400 kbps I C in
5. A High or Low limit has been exceeded 5 IN5 Error Read Only 1 A High or Low limit has been exceeded 6 IN6 Error Read Only 1 A High or Low limit has been exceeded 7 IN7 Error Read Only 1 A High or Low limit has been exceeded MODE 2 0 INO and IN1 Error Read Only 1 A High or Low limit has been exceeded 1 IN3 and IN2 Error Read Only 1 A High or Low limit has been exceeded 2 IN4 and IN5 Error Read Only 1 A High or Low limit has been exceeded 3 IN7 and IN6 Error Read Only 1 A High or Low limit has been exceeded 4 Reserved Read Only 5 Reserved Read Only 6 Reserved Read Only 20 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS ADC128D818 www ti com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 Table 5 Address 01h continued BIT BITNAME READ WRITE BIT DESCRIPTION 7 Hot Temperature Error Read Only 1 A High limit has been exceeded MODE 3 0 INO Error Read Only 1 A High or Low limit has been exceeded 1 IN1 Error Read Only 1 A High or Low limit has been exceeded 2 IN2 Error Read Only 1 A High or Low limit has been exceeded 3 IN3 Error Read Only 1 A High or Low limit has been exceeded 4 IN4 and IN5 Error Read Only 1 A High or Low limit has been exceeded 5 IN7 and IN6 Error Read Only 1 A High or Low limit has been exceeded 6 Reserved Read Only 7 Hot Temperature Error Read Only 1 A
6. High limit has been exceeded 8 6 4 Interrupt Mask Register Address 03h Default Value 7 0 0000_0000 binary Table 6 Address 03h BIT BIT NAME READ WRITE BIT DESCRIPTION MODE 0 0 INO Mask Read Write Lt interrupt status from propagating to the interrupt 1 IN1 Mask Read Write era as interrupt status from propagating to the interrupt 2 IN2 Mask Read Write ao interrupt status from propagating to the interrupt 3 IN3 Mask Read Write Soin interrupt status from propagating to the interrupt 4 IN4 Mask Read Write Heru ii interrupt status from propagating to the interrupt 5 IN5 Mask Read Write ne interrupt status from propagating to the interrupt 6 ING Mask Read Write ee interrupt status from propagating to the interrupt 7 Temperature Mask Read Write aera neta interrupt status from propagating to the interrupt MODE 1 0 INO Mask Read Write ae interrupt status from propagating to the interrupt 1 IN1 Mask Read Write a interrupt status from propagating to the interrupt 2 IN2 Mask Read Write A ae interrupt status from propagating to the interrupt 3 IN3 Mask Read Write crs etna interrupt status from propagating to the interrupt 4 IN4 Mask Read Write o interrupt status from propagating to the interrupt 5 IN5 Mask Read Write a ae interrupt status from propagating to the interrupt 6 IN6 Mask Read Write a interrupt status from propagating to the interrupt 7 IN7 Mask
7. Industrial and Medical Systems e Electronic Test Equipment and Instrumentation e Power Supply Monitoring and Supervision 3 Description The ADC128D818 1 C system monitor is designed for maximum flexibility The system monitor can be configured for single ended and or pseudo differential inputs An onboard temperature sensor combined with WATCHDOG window comparators and an interrupt output pin INT allow easy monitoring and out of range alarms for every channel A high performance internal reference is also available to provide for a complete solution in the most difficult operating conditions The ADC128D818 s 12 bit delta sigma ADC supports Standard Mode Sm 100 kbps and Fast Mode Fm 400 kbps IC interfaces The ADC128D818 includes a sequencer to control channel conversions and stores all converted results in independent registers for easy microprocessor retrieval Unused channels can be shut down independently to conserve power Device Information PACKAGE BODY SIZE NOM TSSOP 16 5 00 mm x 4 40 mm PART NUMBER ADC128D818 1 For all available packages see the orderable addendum at the end of the data sheet Typical Application Diagram Single Ended Positive Voltage O Pseudo Differential Positive Voltage RTRACE Delta Sigma ADC 10VIN Shutdown DC DC Margining Voltage A V VREF o O Interrupt Interrupt Masking Status and INT Interrupt Cont
8. LOW MID MID HIGH LOW HIGH LOW MID HIGH HIGH LOW HIGH Z HIGH LOW HIGH Z Z LOW HIGH MID HIGH Z HIGH LOW HIGH HIGH HIGH Z HIGH Z 9 3 2 Voltage Monitoring for Power Supplies 10VIN SHUTDOWN gt gining Voltage Microcontroller ADC128D818 RB_top RTRACE RB_bottom Figure 39 Power Supply Application Figure 39 shows a more complete systems application using a DC DC converter Such configuration can be used in a power supply application The point to make with this example diagram is the Serial Bus Address connections The previous example shows AO and A1 connected to four GPOs but this example shows a simpler AO and A1 connection using two resistor dividers This connection accomplishes the same goal as the GPO connection that is it can set AO and A1 high low or to midscale 36 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 I TEXAS INSTRUMENTS ADC128D818 www ti com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 For example to set AO high don t populate RB_bottom to set AO low don t populate RB_top and to set AO to midscale leave RB_top and RB_bottom as is and set them equal to each other A typical RB value ranges from 1 kOhm to 10 kOhm 9 3 3 Temperature Sensors GPO1 RA_top Microcontroller RA_bottom RA_top RA_bottom ND Figure 40 Temperature Sensor Applications ADC128D818
9. N 0 Logical 0 Input Voltage Ta Ty TMIN to Tmax GND 0 1 x V V 0 05 SERIAL BUS INPUTS SCL and SDA Vina Logical 1 Input Voltage Ta Ty Tmn to Tmax 0 7 x Vt 5 5 v Vno Logical 0 Input Voltage Thetis Tun to Tox A 03xV v v Hsi is Volt V 3 3 V 0 67 V steresis Voltage HYST ne 9 V 5 5V 1 45 v ALL DIGITAL INPUTS SCL SDA AO A1 Logical 1 Input Current Vy V 0 009 A IN ogica nput Curren IN H K Ta Ty Tmn to Tmax 1 l Logical 0 Input C t Vn 0V A IN O ogica nput Curren IN DC H 9 Ta Ty Tmn to Tmax 1 Cin Digital Input Capacitance 20 pF 8 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS ADC128D818 www ti com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 7 6 AC Electrical Characteristics The following specifications apply for 3 0 Vpc lt V lt 5 5 Vpc unless otherwise specified All limits Ta T 25 C unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SERIAL BUS TIMING CHARACTERISTICS ty SCL Clock Period Ta Ty Tmn to Tmax 2 5 100 us to Data In Set up Time to SCL High Ta Ty Tmn to Tmax 100 ns t3 Data Out Stable After SCL Low Ta Ty Tmn to Tmax 0 ns t4 SDA Low Set up Time to SCL Low Ta Ty Tmn to Tmax 100 ns start ts SDA High Hold Time After SCL High Ta Ty Tmn to Tmax 100 ns stop fico eg SDA time low for I C bus Ta Ty Twn
10. Read Write area ac interrupt status from propagating to the interrupt MODE 2 0 INO and IN1 Mask Read Write ne interrupt status from propagating to the interrupt Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links ADC128D818 I TEXAS INSTRUMENTS ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 www ti com Table 6 Address 03h continued BIT BIT NAME READ WRITE BIT DESCRIPTION 1 Mask the corresponding interrupt status from propagating to the interrupt 1 IN3 and IN2 Mask Read Write output pin INT 2 IN4 and IN5 Mask Read Write 1 Mask the corresponding interrupt status from propagating to the interrupt output pin INT 1 Mask the corresponding interrupt status from propagating to the interrupt 3 IN7 and IN6 Mask Read Write output pin INT 4 Reserved Read Only 5 Reserved Read Only 6 Reserved Read Only r 1 Mask the corresponding interrupt status from propagating to the interrupt 7 Temperature Mask Read Write output pin INT MODE 3 1 Mask the corresponding interrupt status from propagating to the interrupt 0 INO Mask Read Write output pin INT 1 Mask the corresponding interrupt status from propagating to the interrupt 1 IN1 Mask Read Write output pin INT 1 Mask the corresponding interrupt status from propagating to the interrupt 2 IN2 Mask Read Write output pin INT
11. SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 Table 13 Addresses 2Ah 39h continued ADDRESS REGISTER NAME READ WRITE REGISTER DESCRIPTION 35h Reserved Read Only 36h Reserved Read Only 37h Reserved Read Only 38h Temperature High Limit Read Write High Limit 39h Temperature Hysteresis Limit Read Write Hysteresis Limit MODE 3 2Ah INO High Limit Read Write High Limit 2Bh INO Low Limit Read Write Low Limit 2Ch IN1 High Limit Read Write High Limit 2Dh IN1 Low Limit Read Write Low Limit 2Eh IN2 High Limit Read Write High Limit 2Fh IN2 Low Limit Read Write Low Limit 30h IN3 High Limit Read Write High Limit 31h IN3 Low Limit Read Write Low Limit 32h IN4 and IN5 High Limit Read Write High Limit 33h IN4 and IN5 Low Limit Read Write Low Limit 34h IN7 and IN6 High Limit Read Write High Limit 35h IN7 and IN6 Low Limit Read Write Low Limit 36h Reserved Read Only 37h Reserved Read Only 38h Temperature High Limit Read Write High Limit 39h Temperature Hysteresis Limit Read Write Hysteresis Limit 8 6 13 Manufacturer ID Register Address 3Eh Default Value 7 0 0000_0001 binary Table 14 Address 3Eh ADDRESS REGISTER NAME READ WRITE REGISTER DESCRIPTION 3Eh Manufacturer ID Read Only Manufacturer s ID always defaults to 0000_0001 8 6 14 Revision ID Register Addresse
12. a pseudo differential input signal will provide better performance than with a single ended input See Modes of Operation for more information Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links ADC128D818 I TEXAS INSTRUMENTS ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 www ti com Feature Description continued Figure 25 Pseudo Differential Configuration 8 4 Device Functional Modes 8 4 1 Modes of Operation ADC128D818 allows 4 modes of operation as summarized in the following table Set the desired mode of operation using the Advanced Configuration Register Address OBh bits 2 1 Table 1 Modes of Operation CH MODE 0 MODE 1 MODE 2 MODE 3 INO and 1 INO INO IN1 INO IN3 and 2 IN1 IN1 IN2 IN1 IN4 and 3 IN2 IN2 IN5 IN2 IN7 and 4 IN3 IN3 IN6 IN3 IN4 and 5 IN4 IN4 IN5 IN7 and 6 IN5 IN5 IN6 7 IN6 IN6 8 ne IN7 Local Temp Yes No Yes Yes 1 nc No Connect 8 5 Programming 8 5 1 Interface The Serial Bus control lines include the SDA serial data SCL serial clock and AO A1 Serial Bus Address pins The ADC128D818 can only operate as a slave The SCL line only controls the serial interface and all of other clock functions within ADC128D818 are done with a separate asynchronous internal clock When the Serial Bus Interface is used
13. a write will always consists of the ADC128D818 Serial Bus Address byte followed by the Register Address byte then the Data byte Figure 26 and Figure 27 are two examples showing how to write to the ADC128D818 There are two cases for a read 1 If the Register Address is known to be at the desired address simply read the ADC128D818 with the Serial Bus Address byte followed by the Data byte read from the ADC128D818 Examples of this type of read can be seen in Figure 28 and Figure 29 2 If the Register Address value is unknown write to the ADC128D818 with the Serial Bus Address byte followed by the desired Register Address byte Then restart the Serial Communication with a Read consisting of the Serial Bus Address byte followed by the Data byte read from the ADC128D818 See Figure 30 and Figure 31 for examples of this type of read 16 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC 128D818 1 TEXAS INSTRUMENTS www ti com Programming continued ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 The Serial Bus Address can be found in the next section and the Register Address can be found in Register Maps For more information on the 1 C Interface refer to NXP s I C Bus Specification and User Manual rev 03 8 5 1 1 Serial Bus Address There are nine different configurations for the ADC128D818 Serial Bus Address thus nine devices are allowed on a s
14. com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 8 3 Feature Description 8 3 1 Supply Voltage V The ADC128D818 operates with a supply voltage V that has a range between 3 V to 5 5 V Take care to bypass this pin with a parallel combination of 1 uF electrolytic or tantalum capacitor and 0 1 uF ceramic bypass capacitor 8 3 2 Voltage References VREF The reference voltage VREF sets the analog input range The ADC128D818 has two options for setting VREF The first option is to use the internal VREF which is equal to 2 56 V The second option is to source VREF externally through pin 1 of ADC128D818 In this case the external VREF will operate in the range of 1 25 V to V The default VREF selection is the internal VREF If the external VREF is preferred use the Advanced Configuration Register Address OBh to change this setting VREF source must have a low output impedance and needs to be bypassed with a minimum capacitor value of 0 1 uF A larger capacitor value of 1 uF placed in parallel with the 0 1 uF is preferred VREF of the ADC128D818 like all ADC converters does not reject noise or voltage variations Keep this in mind if VREF is derived from the power supply Any noise and or ripple from the supply that is not rejected by the external reference circuitry will appear in the digital results The use of a reference source is recommended The LM4040 and LM4050 shunt reference families as well as the LM4120 and LM4140 series r
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17. 1 Product w Sample amp Folder Buy 1 TEXAS INSTRUMENTS Technical Documents s Support amp Community 4p Tools amp Software ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 ADC128D818 12 Bit 8 Channel ADC System Monitor With Temperature Sensor Internal External Reference and IC Interface Features 12 Bit Resolution Delta Sigma ADC Local Temperature Sensing Configurable Single Ended and or Pseudo Diff Inputs 2 56 V Internal VREF or Variable External VREF WATCHDOG Window Comparators with Status and Mask Registers of All Measured Values Independent Registers for Storing Measured Values INT Output Notifies Microprocessor of Error Event IC Serial Bus Interface Compatibility 9 Selectable Addresses TIME OUT Reset Function to Prevent C Bus Lock Up Individual Channel Shutdown to Limit Power Consumption Deep Shutdown Mode to Minimize Power Consumption TSSOP 16 Lead Package Key Specifications ADC Resolution 12 Bit Supply Voltage Range 3 V to 5 5 V Total Unadjusted Error 0 45 0 2 Integral Non Linearity 1 LSb Differential Non Linearity 1 LSb Operating Current 0 56 mA Deep Shutdown Current 10 pA Temperature Resolution C LSb Temperature Accuracy 40 C to 125 C 3 C Temperature Accuracy 25 C to 100 C 2 C 2 Applications e Communications Infrastructure e Thermal and Hardware Server Monitors e System Monitors e
18. 1 Mask the corresponding interrupt status from propagating to the interrupt 3 IN3 Mask Read Write output pin INT 7 1 Mask the corresponding interrupt status from propagating to the interrupt 4 IN4 and IN5 Mask Read Write output pin INT 1 Mask the corresponding interrupt status from propagating to the interrupt 5 IN7 and IN6 Mask Read Write output pin INT 6 Reserved Read Only 1 Mask the corresponding interrupt status from propagating to the interrupt 7 Temperature Mask Read Write output pin INT 8 6 5 Conversion Rate Register Address 07h Default Value 7 0 0000_0000 binary Table 7 Address 07h BIT BIT NAME READ WRITE BIT DESCRIPTION Controls the conversion rate 0 Low Power Conversion Mode 1 Continuous Conversion Mode o Conversion Rate Read Write Note This register must only be programmed when the device is in shutdown mode that is when the START bit of the Configuration Register address 00h 0 1 7 Reserved Read Only 8 6 6 Channel Disable Register Address 08h Default Value 7 0 0000_0000 binary e This register must only be programmed when the device is in shutdown mode that is when the START bit of the Configuration Register address 00h 0 e Whenever this register is programmed all of the values in the Channel Reading Registers and Interrupt Status Registers will return to their default values Table 8 Address 08h BIT BIT NAM
19. 2 6 Conversion Rate Register address 07h There are three options for controlling the conversion rate The first option is called the Low Power Conversion Mode where the device converts all of the enabled channels then enters shutdown mode This process takes approximately 728 ms to complete The second option is the Continuous Conversion Mode where the device continuously converts the enabled channels thus never entering shutdown mode A voltage conversion takes 12 2 ms and a temperature conversion takes 3 6 ms For example if operating in mode 2 and three voltage channels were enabled then each round robin monitor would take 40 2 ms 3 x 12 2ms 3 6ms to complete Use the Channel Disable Register address 08h to disable the desired channel s The third option is called the ON Shot mode which will be discussed in the next subsection 9 2 2 2 7 One Shot Register address 09h The One Shot register is used to initiate a single conversion and comparison cycle when the device is in shutdown mode or deep shutdown mode after which the device returns to the respective mode it was in The obvious advantage of using this mode is lower power consumption because the device is operating in shutdown or deep shutdown mode This register is not a data register and it is the write operation that causes the one shot conversion The data written to this address is irrelevant and is not stored A zero will always be read from this register 9 2 2
20. 2 8 Deep Shutdown Register address O0Ah The ADC128D818 can be placed in deep shutdown mode thus reducing more power consumption The procedures for deep shutdown entrance are 1 Enter shutdown by setting the START bit of the Configuration Register address 00h bit 0 to 0 2 Enter deep shutdown by setting the DEEP SHUTDOWN bit address OAh bit 0 to 1 3 A one shot conversion can be triggered by writing any values to register address 09h Deep Shutdown Exit Procedure 1 Set the DEEP SHUTDOWN bit to 0 9 2 2 2 9 Channel Readings Registers addresses 20h 27h The channel conversion readings are available in registers 20h to 27h Each register is 16 bit wide to accommodate the 12 bit voltage reading or 9 bit temperature reading Conversions can be read at any time and will provide the result of the last conversion If a conversion is in progress while a communication is started that conversion will be completed and the Channel Reading Registers will not be updated until the communication is complete 34 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC 128D818 1 TEXAS INSTRUMENTS ADC128D818 www ti com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 9 2 3 Application Curve 0 020 0 060 s 0 100 0 140 0 180 0 220 500 0 1 2k 1 9k 2 7k 3 4k 4 1k CODE TUE Figure 37 Total Unadjusted Error 9 3 Syst
21. 30 0 V V TEMPERATURE Figure 16 Gain Error vs V Figure 17 Gain Error vs Temperature 0 460 0 490 0 440 0 470 _ 0 420 _ 0 450 lt lt 0 400 0 430 0 380 0 410 0 360 0 390 50 0 14 0 22 0 58 0 94 0 130 0 2 7 3 3 3 8 4 4 4 9 TEMPERATURE C V V Figure 18 l vs Temperature Figure 19 l vs V Typical A Timing specifications are tested at the Serial Bus Input logic levels V IN 0 0 3 x V for a falling edge and V IN 1 0 7 x V for a rising edge if the SCL and SDA edge rates are similar 12 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS ADC128D818 www ti com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 Typical Characteristics continued The following typical performance plots apply for the internal VREF 2 56 V V 3 3 V Pseudo Differential connection unless otherwise specified All limits Ta Tj 25 C unless otherwise specified 1 340 1 70 1 298 1 60 1 256 1 50 1 214 1 40 1 172 1 30 1 130 Feo Fer Teen oo 25 30 35 40 45 50 55 60 25 30 35 40 45 50 55 6 0 V V V V i i Figure 20 I vs V for Voltage Conversion Figure 21 l vs V for Temperature Conversion 0 440 0 004 0 420 0 003 0 400 0 003 0
22. C 1_1011_0000 432 1_Bo In general the easiest way to calculate the temperature C is to use the following formulas If Dour MSb 0 Temp C Doyz dec 2 If Doyr MSb 1 Temp C 2 Doyr dec 2 an Q N Se aS 9 1 2 1 Temperature Limits One of the ADC128D818 features is monitoring the temperature reading This monitoring is accomplished by setting a temperature limit to the Temperature High Limit Register Thot address 38h and Temperature Hysteresis Limit Register Thot hyst address 39h When the temperature reading gt Thot an interrupt occurs How this interrupt occurs will be explained in Temperature Interrupt Each temperature limit is represented by an 8 bit two s complement word with a least significant bit LSb equal to 1 C Table 17 shows some sample temperatures that can be programmed to the Temperature Limit Registers In general use the following equations to calculate the digital code that represents the desired temperature limit If Temp Limit C 2 0 Digital Code dec Temp Limit C 4 If Temp Limit C lt 0 Digital Code dec 28 Temp Limit C 5 Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Links ADC128D818 I TEXAS INSTRUMENTS ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 www ti com Table 17 Temperature Limit Registers Sample Temperatures DIG
23. E 0 5 ln d h a a ni a 0 25 1 0 0 50 1 5 0 75 2 0 1 00 0 1050 2100 3150 4200 0 1050 2100 3150 4200 Code CODE Figure 6 INL vs Code External VREF 1 25 V for 1 Unit Figure 7 INL vs Code External VREF 1 25 V for 28 Units 10 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS www ti com Typical Characteristics continued ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 The following typical performance plots apply for the internal VREF 2 56 V V 3 3 V Pseudo Differential connection unless otherwise specified All limits Ta Tj 25 C unless otherwise specified Copyright 2010 2015 Texas Instruments Incorporated 4 0 2 0 3 5 3 0 1 5 2 5 _ 2 0 _ 1 0 a 15 a 1 0 3 0 8 05 0 0 FF 0 0 0 5 1 0 0 5 1 5 2 0 1 0 0 1050 2100 3150 4200 0 1050 2100 3150 4200 Code Code Figure 8 INL vs Code External VREF 2 56 V for 1 Unit Figure 9 INL vs Code External VREF 2 56 V for 28 Units 4 0 2 0 3 5 3 0 1 5 2 5 _ 2 0 _ 1 0 a 15 a 10 ie OD 05 zZ 0 0 0 0 0 5 1 0 0 5 1 5 2 0 1 0 0 1050 2100 3150 4200 0 1050 2100 3150 4200 Code Code Figure 10 INL vs Code External VREF 5 V V 5 V for 1 Figure 11 INL vs
24. E READ WRITE BIT DESCRIPTION MODE 0 1 Conversions are skipped and disabled value register reading will be 0 and 0 INO Disable Read Write error events will be suppressed 22 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS www ti com ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 Table 8 Address 08h continued BIT BIT NAME READ WRITE BIT DESCRIPTION 1 IN1 Disable Read Write en alia e disabled value register reading will be 0 and 2 IN2 Disable Read Write dah alia E Se disabled value register reading will be 0 and 3 IN3 Disable Read Write state eo disabled value register reading will be 0 and 4 IN4 Disable Read Write ai E Bee disabled value register reading will be 0 and 5 INS Disable Read Write Maa o disabled value register reading will be 0 and 6 IN6 Disable Read Write e a Poa disabled value register reading will be 0 and 7 Temperature Disable Read Write Ae ake el Tat disabled value register reading will be 0 and MODE 1 0 INO Disable Read Write Laat arte b eee disabled value register reading will be 0 and 1 IN1 Disable Read Write aea ea A e disabled value register reading will be 0 and 2 IN2 Disable Read Write re Eie tele a disabled value register reading will be 0 and 3 IN3 Disable Re
25. F FEBRUARY 2010 REVISED AUGUST 2015 I TEXAS INSTRUMENTS www ti com Table 8 Address 08h continued BIT BIT NAME READ WRITE BIT DESCRIPTION oar 1 Conversions are skipped and disabled value register reading will be 0 and 4 IN4 and IN5 Disable Read Write error events will be suppressed 3 1 Conversions are skipped and disabled value register reading will be 0 and 5 IN7 and IN6 Disable Read Write error events will be suppressed 6 Reserved Read Only 7 Temperature Disable Read Write 1 Conversions are skipped and disabled value register reading will be 0 and error events will be suppressed 8 6 7 One Shot Register Address 09h Default Value 7 0 0000_0000 binary Table 9 Address 09h BIT BITNAME READ WRITE BIT DESCRIPTION 1 Initiate a single conversion and comparison cycle when the device is in 0 One Shot Write Only shutdown mode or deep shutdown mode after which the device returns to the respective mode that it was in 1 7 Reserved Read Only 8 6 8 Deep Shutdown Register Address 0Ah Default Value 7 0 0000_0000 binary Table 10 Address 0Ah BIT BITNAME READ WRITE BIT DESCRIPTION A 1 When START 0 address OOh bit 0 setting this bit high will place the 0 Deep Shutdown Enable Read Write device in deep shutdown mode 1 7 Reserved Read Only 8 6 9 Advanced Configuration Register Address 0B
26. ITAL CODE TEMP LIMIT BINARY MSb LSb DECIMAL HEX 125 C 0111_1101 125 7D 25 C 0001_ 1001 25 19 1 0 C 0000_0001 1 01 0 C 0000_0000 0 00 1 0 C 1111_1111 255 FF 25 C 1110_1111 231 E7 40 C 1101_1000 216 D8 9 1 3 Interrupt Structure E ty ty i ty ty IN4 Watchdog E i i INT INS Watchdog Enable INT_Clear i IN6 Watchdog OOR 1 ooh s i IN7 Watchdog TEMP Watchdog Figure 34 Interrupt Structure Figure 34 shows the ADC128D818 s Interrupt Structure NOTE The number next to each bit name represents its register address and bit number For example INT_Clear 00h 3 refers to bit 3 of register address OOh 9 1 3 1 Interrupt Output INT ADC128D818 generates an interrupt as a result of each of its internal WATCHDOG registers on the voltage and temperature channels In general INT becomes active when all three scenarios as depicted in Figure 34 occur 1 INT_Clear 00h 3 0 2 INT Enable 00h 1 1 to enable interrupt output 3 The voltage reading gt the voltage high limit or lt the voltage low limit or the temperature reading gt Thot 9 1 3 2 Interrupt Clearing Reading the Interrupt Status Register addresses 01h will output the contents of the register and clear the register When the Interrupt Status Register clears the interrupt output pin INT also clears until this register is updated by the round robin monitoring loop Another method
27. Sensor Microcontrolle RB_top AO Fa ADC128D818 Instrumentation Op Amp RB_bottom V Figure 41 Bridge Sensor Application ADC128D818 is perfect for transducer applications such as pressure sensors These sensors measure pressure of gases or liquids and produce a pressure equivalent voltage at their outputs Figure 41 shows a typical connection of a pressure sensor represented by the bridge sensor Most pressure sensor has a low sensitivity characteristic which means its output is typically in the millivolts range Because of that reason an op amp such as an instrumentation amplifier can be used for the gain stage The positive aspect of this configuration is its ratiometric connection A ratiometric connection is when the ADC s VREF and GND are connected to the bridge sensor s voltage references With a ratiometric configuration external VREF accuracy can be ignored 10 Power Supply Recommendations The ADC128D818 operates with a supply voltage V that has a range between 3 V to 5 5 V Take care to bypass this pin with a parallel combination of 1 uF electrolytic or tantalum capacitor and 0 1 uF ceramic bypass capacitor The reference voltage VREF sets the analog input range The ADC128D818 has two options for setting VREF The first option is to use the internal VREF which is equal to 2 56 V The second option is to source VREF externally through pin 1 of ADC128D818 In this case the external VREF will oper
28. ad Only 2 NT cla pei ee een ee ee ne 4 Reserved Read Only 5 Reserved Read Only 6 Reserved Read Only 1 Restore default values to the following registers Configuration Interrupt Status Interrupt 7 Initialization Read Write Mask Conversion Rate Channel Disable One Shot Deep Shutdown Advanced o PaE P a Busy Status Channel Readings Limit Manufacturer ID Revision ID This bit 8 6 3 Interrupt Status Register Address 01h Default Value 7 0 0000_0000 binary Table 5 Address 01h BIT BITNAME READ WRITE BIT DESCRIPTION MODE 0 0 INO Error Read Only 1 A High or Low limit has been exceeded 1 IN1 Error Read Only 1 A High or Low limit has been exceeded 2 IN2 Error Read Only 1 A High or Low limit has been exceeded 3 IN3 Error Read Only 1 A High or Low limit has been exceeded 4 IN4 Error Read Only 1 A High or Low limit has been exceeded 5 IN5 Error Read Only 1 A High or Low limit has been exceeded 6 IN6 Error Read Only 1 A High or Low limit has been exceeded 7 Hot Temperature Error Read Only 1 A High limit has been exceeded MODE 1 0 INO Error Read Only 1 A High or Low limit has been exceeded 1 IN1 Error Read Only 1 A High or Low limit has been exceeded 2 IN2 Error Read Only 1 A High or Low limit has been exceeded 3 IN3 Error Read Only 1 A High or Low limit has been exceeded 4 IN4 Error Read Only 1
29. ad Write a tee Ae disabled value register reading will be 0 and 4 IN4 Disable Read Write eai et disabled value register reading will be 0 and 5 INS Disable Read Write a e et disabled value register reading will be 0 and 6 ING Disable Read Write ie sae disabled value register reading will be 0 and 7 IN7 Disable Read Write Lc aah tate o disabled value register reading will be 0 and MODE 2 0 INO and IN1 Disable Read Write ie en disabled value register reading will be 0 and 1 IN3 and IN2 Disable Read Write a an ae disabled value register reading will be 0 and 2 IN4 and IN5 Disable Read Write ie piel disabled value register reading will be 0 and 3 IN7 and IN6 Disable Read Write Late o disabled value register reading will be 0 and 4 Reserved Read Only 5 Reserved Read Only 6 Reserved Read Only 7 Temperature Disable Read Write eiii i a disabled value register reading will be 0 and MODE 3 0 INO Disable Read Write a tet oe disabled value register reading will be 0 and 1 IN1 Disable Read Write ei i a disabled value register reading will be 0 and 2 IN2 Disable Read Write a a oa disabled value register reading will be 0 and 3 IN3 Disable Read Write 1 Conversions are skipped and disabled value register reading will be 0 and error events will be suppressed Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links ADC128D818 23 ADC128D818 SNAS483
30. amp no Sb Br CIMT ADC128D818CIMTX NOPB ACTIVE TSSOP PW 16 2500 Green RoHS CU SN Level 1 260C UNLIM 40 to 125 128D818 5 E amp no Sb Br CIMT The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free ROHS Pb Free ROHS Exempt or Green ROHS amp no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between th
31. ate in the range of 1 25 V to V The default VREF selection is the internal VREF If the external VREF is preferred use the Advanced Configuration Register Address OBh to change this setting VREF source must have a low output impedance and needs to be bypassed with a minimum capacitor value of 0 1 uF A larger capacitor value of 1 uF placed in parallel with the 0 1 uF is preferred VREF of the ADC128D818 like all ADC converters does not reject noise or voltage variations Keep this in mind if VREF is derived from the power supply Any noise and or ripple from the supply that is not rejected by the external reference circuitry will appear in the digital results The use of a reference source is recommended The LM4040 SLOS746 and LM4050 SNOS455 shunt reference families as well as the LM4120 SNVS049 and LM4140 SNVS053 series reference families are excellent choices for a reference source 38 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS ADC128D818 www ti com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 11 Layout 11 1 Layout Guidelines Analog inputs will provide best accuracy when referred to the GND pin or a supply with low noise A separate low impedance ground plane for analog ground which provides a ground point for the voltage dividers and analog components will provide best performance but is not mandatory Analog components
32. c INx where 0 lt x lt 7 must be lt 4 55 Vpc to ensure accurate conversions 2 Limits are ensured to AOQL Average Outgoing Quality Level 3 Typicals are at Tj Ta 25 C and represent most likely parametric normal 4 Limit is specified by characterization 6 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS ADC128D818 www ti com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 DC Electrical Characteristics continued The following specifications apply for 3 Vpc V lt 5 5 Vpc External VREF 2 56 V unless otherwise specified All limits Ta Tj 25 C unless otherwise specified PARAMETER TEST CONDITIONS MN TYP MAX UNIT External VREF 1 25 V 0 36 Pseudo Differential V 3 LSb V to 3 3 V 4 Ta Ty Tmn to Tmax 1 1 External VREF 2 56 V 1 58 Pseudo Differential External VREF 5 V LSb Pseudo Differential V 5 TA T4 Tmin to Tmax 2 4 V to 5 5 V INL Integral Non Linearity 0 25 DNL Differential Non Linearity See LSb Ta Ty TMIN to Tmax 1 1 Internal VREF Single Ended V 3 V to 3 6 V Internal VREF Single Ta Ty Tmn to Tmax 0 5 0 5 of FS Ended V 4 5 V to 5 5 v Internal VREF Pseudo Differential V 3 V to 3 6 Ta Ty Tmn to Tmax 0 3 0 5 of FS V or V 4 5 V to 5 5 VO External VREF 1 25 V Sing
33. e die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free ROHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free ROHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 8 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature There may be additional marking which relates to the logo the lot trace code information or the environmental category on the device Multiple Device Markings will be inside parentheses Only one Device Marking contained in parentheses and separated by a will appear on a device If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device 6 ead Ball Finish Orderable Devices may have multiple material finish options Finish options are separated by a vertical ruled line Lead Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accu
34. ead Only Reading for this perspective channel 23h IN3 Reading Read Only Reading for this perspective channel 24h IN4 Reading Read Only Reading for this perspective channel 25h IN5 Reading Read Only Reading for this perspective channel 26h IN6 Reading Read Only Reading for this perspective channel 27h Temperature Reading Read Only Reading for this perspective channel MODE 1 20h INO Reading Read Only Reading for this perspective channel 21h IN1 Reading Read Only Reading for this perspective channel 22h IN2 Reading Read Only Reading for this perspective channel 23h IN3 Reading Read Only Reading for this perspective channel 24h IN4 Reading Read Only Reading for this perspective channel 25h IN5 Reading Read Only Reading for this perspective channel 26h IN6 Reading Read Only Reading for this perspective channel 27h IN7 Reading Read Only Reading for this perspective channel MODE 2 20h INO and IN1 Reading Read Only Reading for this perspective channel 21h IN3 and IN2 Reading Read Only Reading for this perspective channel 22h IN4 and IN5 Reading Read Only Reading for this perspective channel 23h IN7 and IN6 Reading Read Only Reading for this perspective channel 24h Reserved Read Only 25h Reserved Read Only 26h Reserved Read Only 27h Temperature Reading Read Only Reading for this perspective channel MODE 3 20h INO Reading Read Only Reading for this perspective channel 21h IN1 Reading Read Only Reading for this perspective cha
35. eference families are excellent choices for a reference source 8 3 3 Analog Inputs INO IN7 The ADC128D818 allows up to 8 single ended inputs or 4 pseudo differential inputs as selected by the modes of operation The input types are described in the next subsections 8 3 3 1 Single Ended Input ADC128D818 allows a maximum of 8 single ended inputs where the source s voltage is connected to INx 0 lt x lt 7 The source s ground must be connected to ADC128D818 s GND pin In theory INx can be of any value between OV and VREF 3LSb 2 where LSb VREF 2 To use the device single endedly refer to the Modes of Operation section and to bits 2 1 of the Advanced Configuration Register Address OBh Figure 24 shows the appropriate configuration for a single ended connection INO IN1 IN2 a ADC128D818 IN5 IN6 IN7 GND Figure 24 Single Ended Configuration 8 3 3 2 Pseudo Differential Input Pseudo differential mode is defined as the positive input voltage applied differentially to the ADC128D818 as shown in Figure 25 The input that is digitized is AVIN IN IN where IN IN is INO IN1 IN3 IN2 IN4 IN5 or IN7 IN6 Be aware of this input configuration because the order is swapped In theory AVIN can be of any value between 0 V and VREF 3LSb 2 where LSb VREF 2 By using this pseudo differential input small signals common to both inputs are rejected Thus operation with
36. em Examples 9 3 1 General Voltage Monitoring V V es iti 0 INT i Positive 6 IN2 oS Single Ended 2 GPO1 Input Voltage a RA top Microcontroller Q RA_bottom lt GPO2 GPO3 Positive O RA_top Pseudo Differential Input Voltage RA_bottom GPO4 Figure 38 Typical Analog Input Application A typical application for ADC128D818 is voltage monitoring In this application the inputs would most often be connected to linear power supplies of 2 5 V 3 3 V 5 V and 12 V inputs These inputs must be attenuated with external resistors to any desired value within the input range The attenuation is done with resistors R1 and R2 for the positive single ended voltage and R3 and R4 for the positive pseudo differential voltage A typical single ended application might select the input voltage divider to provide 1 9 V at the analog input of the ADC128D818 This is sufficiently high for good resolution of the voltage yet leaves headroom for upward excursions from the supply of about 25 To simplify the process of resistor selection set the value of R2 first Select a value for R2 between 10 kQ and 100 kQ This is low enough to avoid errors due to input leakage currents yet high enough to protect both the inputs under and overdrive conditions as well as minimize loading of the source Finally calculate R1 to provide a 1 9 V input using simple voltage divider derived formula R1 VS1 VIN2 VIN2 x R2 7 Copyrigh
37. erature Reading 9 2 Typical Application V VREF ADC128D818 7 Internal VREF 2 56V LM94022 Single Ended Positive Voltage Interrupt O Pseudo Differential Interrupt Masking o Positive Voltage Status and INT i Registers Interrupt JOVIN Delta Sigma Control Shutdown Margining Voltage AAA SDA SCL AO Al Temperature Sensor Figure 36 Hardware Monitor Application C Interface and Control Pa GND RTRACE 9 2 1 Design Requirements In this typical hardware monitor application several different sources are being monitored by the ADC128D818 First an external temperature sensor LM94022 is being monitored An external temperature sensor is frequently used to monitor ambient temperature of the system Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links ADC128D818 I TEXAS INSTRUMENTS ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 www ti com Typical Application continued 9 2 2 Detailed Design Procedure 9 2 2 1 Power Management To understand the average supply current I the conversion rates must be introduced ADC128D818 has three types of conversion rates Continuous Conversion Mode Low Power Conversion Mode and One Shot Mode In the Low Power Conversion Mode the device converts all of the enabled channels then enters shutdown mode this process takes approximately 728 ms to complete More in
38. formation on the conversion rate will be discussed in the Conversion Rate Register Address 07h and One Shot Register Address 09h sections Each type of conversion produces a different average supply current The supply current for a voltage conversion will be referred to as I1 _VOLTAGE a temperature conversion as I _TEMP and the shutdown mode as 1 SHUTDOWN These values can be obtained from Typical Performance Characteristics plots In general l is the average supply current while ADC128D818 is operating in the Low Power Conversion Mode with all of the available channels enabled Its plot can be seen in Typical Characteristics and its equation Equation 6 l 0 0168 b I _ VOLTAGE 4 932 10 a I _TEMP 1 4 932 10 a 0 0168 b I _ SHUTDOWN where ais the number of local temperature available bis the number of ENABLED voltage channel 6 Each mode of operation has a different a and b values The following table shows the value for a and the maximum value for b for each mode Table 18 A and B Values a b MAX Mode 0 1 7 Mode 1 0 8 Mode 2 1 4 Mode 3 1 6 9 2 2 2 Using the ADC128D818 Table 19 ADC128D818 Internal Registers REGISTER READ DEFAULT REGISTER REGISTER NAME WRITE gee VALUE 7 0 REGISTER DESCRIPTION FORMAT Configuration Register R W 00h 0000_1000 Provides control and confi
39. g 65 150 C 1 All voltages are measured with respect to GND unless otherwise specified 2 If Military Aerospace specified devices are required please contact the Texas Instruments Sales Office Distributors for availability and specifications 3 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions Exposure to absolute maximum rated conditions for extended periods may affect device reliability For soldering specifications SNOA549 5 If the input voltage at any pin exceeds the power supply that is VIN lt GND or VIN gt V but is less than the absolute maximum ratings then the current at that pin must be limited to 5 mA The 30 mA maximum package input current rating limits the number of pins that can safely exceed the power supply with an input current of 5 mA to six pins Parasitic components and or ESD protection circuitry are shown in the Pin Descriptions table 6 The maximum power dissipation must be derated at elevated temperatures and is dictated by Tywax Resa and the ambient temperature Ta The maximum allowable power dissipation at any temperature is Pp Tymax T a Rega 7 2 ESD Ratings VALUE UNIT Human body model HBM per ANSI ESDA JEDEC JS 001 3000
40. gle Byte Read With Internal Address Set Using a Repeat Start Copyright 2010 2015 Texas Instruments Incorporated 18 Submit Documentation Feedback Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS ADC128D818 www ti com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 1 9 1 9 eee SDA Start by Ack by Ack by Master ADC128D818 ADC128D818 Frame 1 Frame 2 lt _ Seerial Bus Address gt lt Register Address gt i Byte from Master H Byte from Master li 1 9 1 9 1 9 pee gg og Ey gg og gl gg Og og pg gp a continued SDA ese continued Repeat Ack by Stop Ack No Ack Start by ADC128D818 a 7 a Master Frame 3 Frame 4 Frame 5 Master ra Serial Bus Address Pit Data Byte gt i Data Byte from _ i Byte from Master from ADC128D818 l ADC128D818 Figure 31 Serial Bus Interface Read Example 4 Double Byte Read With Internal Address Set Using a Repeat Start 8 6 Register Maps 8 6 1 ADC128D818 Internal Registers Table 3 ADC128D818 Internal Registers REGISTER READ DEFAULT REGISTER REGISTER NAME WRITE arenas VALUE 7 0 REGISTER DESCRIPTION FORMAT Configuration Register R W 00h 0000_1000 Provides control and configuration 8 bit Provides status of each WATCHDOG limit or Interrupt Status Register R Oih 0000_0000 interrupt event 8 bit Interrupt Mask Register R W O3h oo00_0000 Maske the interrupt status from propagat
41. guration 8 bit Interrupt Status Register R Oth 0000_0000 a status of each WATCHDOG limit or interrupt 8 bit Interrupt Mask Register R W 03h 0000_0000 Masks the interrupt status from propagating to INT 8 bit Conversion Rate Register R W 07h 0000_0000 Controls the conversion rate 8 bit Channel Disable Register R W o8h 0000_0000 Seay c nversidn Tor e ch voltage r temperature 8 bit One Shot Register Ww 09h 0000_0000_ Initiates a single conversion of all enabled channels 8 bit Deep Shutdown Register R W OAh 0000_0000 Enables deep shutdown mode 8 bit Advanced Configuration Selects internal or external VREF and modes of i Register R W OBh 0000_0000 operation 8 bit Busy Status Register R OCh 0000_0010 Reflects the ADC128D818 Busy and Not Ready 8 bit statuses Channel Readings R 20h 27h me Report channels voltage or temperature readings 16 bit Registers 32 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 I TEXAS INSTRUMENTS ADC128D818 www ti com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 Table 19 ADC128D818 Internal Registers continued REGISTER READ DEFAULT REGISTER REGISTER NAME WRITE ea VALUE 7 0 REGISTER DESCRIPTION FORMAT Limit Registers R W 2Ah 39h ON Set the limits for the voltage and temperature 8 bit g channels Manufacturer ID Register R 3Eh 0000_0001 Reports the manufacturer s ID 8 bit Revision ID Register R 3Fh 0000_1001 Repor
42. h Default Value 7 0 0000_0000 binary Note Whenever the Advanced Configuration Register is programmed all of the values in the Channel Reading Registers and Interrupt Status Registers will return to their default values Table 11 Address OBh BIT BIT NAME READ WRITE BIT DESCRIPTION 0 External Reference Enable Read Write aes ie ee aie Mode Select 1 Mode Select 0 Mode 1 Mode Select 0 i o 9 a Read Write 0 1 Mode 1 1 0 Mode 2 2 Mode Select 1 1 1 Mode 3 3 7 Reserved Read Only 24 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS www ti com 8 6 10 Busy Status Register Address 0Ch Default Value 7 0 0000_0010 binary Table 12 Address 0Ch ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 BIT BITNAME READ WRITE BIT DESCRIPTION 0 Busy Read Only 1 ADC128D818 is converting 1 Not Ready Read Only 1 Waiting for the power up sequence to end 2 7 Reserved Read Only 8 6 11 Channel Readings Registers Addresses 20h 27h ADDRESS REGISTER NAME READ WRITE REGISTER DESCRIPTION MODE 0 20h INO Reading Read Only Reading for this perspective channel 21h IN1 Reading Read Only Reading for this perspective channel 22h IN2 Reading R
43. imit Read Write Low Limit 38h Temperature High Limit Read Write High Limit 39h Temperature Hysteresis Limit Read Write Hysteresis Limit MODE 1 2Ah INO High Limit Read Write High Limit 2Bh INO Low Limit Read Write Low Limit 2Ch IN1 High Limit Read Write High Limit 2Dh IN1 Low Limit Read Write Low Limit 2Eh IN2 High Limit Read Write High Limit 2Fh IN2 Low Limit Read Write Low Limit 30h IN3 High Limit Read Write High Limit 31h IN3 Low Limit Read Write Low Limit 32h IN4 High Limit Read Write High Limit 33h IN4 Low Limit Read Write Low Limit 34h IN5 High Limit Read Write High Limit 35h IN5 Low Limit Read Write Low Limit 36h IN6 High Limit Read Write High Limit 37h IN6 Low Limit Read Write Low Limit 38h IN7 High Limit Read Write High Limit 39h IN7 Low Limit Read Write Low Limit MODE 2 2Ah INO and IN1 High Limit Read Write High Limit 2Bh INO and IN1 Low Limit Read Write Low Limit 2Ch IN3 and IN2 High Limit Read Write High Limit 2Dh IN3 and IN2 Low Limit Read Write Low Limit 2Eh IN4 and IN5 High Limit Read Write High Limit 2Fh IN4 and IN5 Low Limit Read Write Low Limit 30h IN7 and IN6 High Limit Read Write High Limit 31h IN7 and IN6 Low Limit Read Write Low Limit 32h Reserved Read Only 33h Reserved Read Only 34h Reserved Read Only 26 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS www ti com ADC128D818
44. ing g pit Conversion Rate Register R W 07h 0000_0000 Controls the conversion rate 8 bit Disables conversion for each voltage or Channel Disable Register R W 08h 0000_0000 temperature channel 8 bit One Shot Register w 09h 0000_0000 Initiates a single conversion of all enabled 8 bit channels Deep Shutdown Register R W OAh 0000_0000 Enables deep shutdown mode 8 bit i Selects internal or external VREF and modes Advanced Configuration Register R W OBh 0000_0000 of operation 8 bit Busy Status Register R OCh 0000_0010 Reflects ADC128D818 Busy and Not Ready abit statuses Channel Readings Registers R 20h 27h Report the channels voltage or temperature 46 pit readings Set the limits for the voltage and temperature Limit Registers R W 2Ah 39h channels 8 bit Manufacturer ID Register R 3Eh 0000_0001 Reports the manufacturer s ID 8 bit Revision ID Register R 3Fh 0000_1001 Reports the revision s ID 8 bit Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links ADC128D818 I TEXAS INSTRUMENTS ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 www ti com 8 6 2 Configuration Register Address 00h Default Value 7 0 0000_ 1000 binary Table 4 Address 00h BIT BIT NAME READ WRITE BIT DESCRIPTION ALL MODES 0 Start Read Write i a E e fe R 1 INT_Enable Read Write 1 Enable the interrupt output pin INT 2 Reserved Re
45. ingle I C bus Examples to set each address bit low high or to midscale can be found in System Examples The Serial Bus Address can be set as follows Table 2 Serial Bus Address Table A1 AO PTA SERIAL BUS ADDRESS HEX LOW LOW 001_1101b 1Dh LOW MID 001_1110b 1Eh LOW HIGH 001_1111b 1Fh MID LOW 010_1101b 2Dh MID MID 010_1110b 2Eh MID HIGH 010_1111b 2Fh HIGH LOW 011_0101b 35h HIGH MID 011_0110b 36h HIGH HIGH 011_0111b 37h 8 5 1 2 Time out The ADC128D818 I C state machine resets to its idle state if either SCL or SDA is held low for longer than 35 ms This feature also ensures that ADC128D818 will automatically release SDA after driving it low continuously for 25 to 35 ms hence preventing I C bus lock up The TIME OUT feature should not be used when the device is operating in deep shutdown mode 8 5 1 2 1 Example Writes and Reads Ack by Ack by Stop by ADC128D818 ADC128D818 Master Frame 1 Frame 2 Serial Bus Address gt a Register Address Byte from Master Byte from Master Figure 26 Serial Bus Interface Write Example 1 Internal Address Register Set Only Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 Submit Documentation Feedback 17 I TEXAS INSTRUMENTS www ti com ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 Start by Ack by Ack by Master ADC128D818 ADC128D818 Frame 1 Frame 2
46. kly find helpful E2E forums along with design support tools and contact information for technical support 12 3 Trademarks E2E is a trademark of Texas Instruments All other trademarks are the property of their respective owners 12 4 Electrostatic Discharge Caution A These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam hid during storage or handling to prevent electrostatic damage to the MOS gates 12 5 Glossary SLYZ022 TI Glossary This glossary lists and explains terms acronyms and definitions 13 Mechanical Packaging and Orderable Information The following pages include mechanical packaging and orderable information This information is the most current data available for the designated devices This data is subject to change without notice and revision of this document For browser based versions of this data sheet refer to the left hand navigation 40 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC 128D818 H PACKAGE OPTION ADDENDUM I TEXAS INSTRUMENTS www ti com 21 Apr 2015 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Op Temp C Device Marking Samples a Drawing Qty 2 6 3 4 5 ADC128D818CIMT NOPB ACTIVE TSSOP PW 16 92 Green RoHS CU SN Level 1 260C UNLIM 40 to 125 128D818 5 l
47. le Ended V 3 Vto Ta T Tmn to Tmax 3 6 V External VREF 2 56 V Single Ended V 3 Vto Ta T Tmn to Tmax 5 5 V External VREF 1 25 V Pseudo Differential V 3 Ta Ty Twin to Tax V to 3 6 V External VREF 2 56 V Pseudo Differential V 3 Ta Ty Twin to Tmax V to 5 5 V Internal VREF V 3 V to 3 6 V Internal VREF V 4 5 V to 5 5 V External VREF 1 25 V or 2 56 V V 3 V to 3 6 V External VREF 2 56 V or 5 V V 4 5 V to 5 5 V Internal VREF Pseudo Ditferential Va 4 5 Vto Ta Ty TmIn to Tmax 0 15 0 2 of FS 5 5 VV External VREF 1 25 V or 2 56 V Single Ended V 3 V to 3 6 V External VREF 2 56 V or OE Offset Error 5 V Single Ended V 4 5 V to 5 5 V External VREF 1 25 V or 2 56 V Pseudo Differential V 3 V to 3 6 V External VREF 2 56 V or 5 V Pseudo Differential V 4 5 V to 5 5 V TUE Total Unadjusted Error 0 6 0 1 of FS 0 45 0 2 of FS Ta Ty Tmn to Tmax 0 25 0 45 of FS GE Gain Error Ta Ty Tmn to Tmax 0 45 0 2 of FS Ta Ty Tmn to Tmax 0 5 0 1 of FS Ta Ty Tmn to Tmax 0 2 0 15 of FS 5 Limit is specified by design 6 TUE Total Unadjusted Error includes Offset Gain and Linearity errors of the ADC 7 The range is up to 7 8 of full scale Copyright 2010 2015 Texas Instruments Incorp
48. lication Information 9 2 Typical Application ueeiaeinvedbads 9 3 System Examples ce eeeeceeceeseeeeceeeeseeeeeeaeeaeeees Device and Documentation Support 12 1 Documentation Support 12 2 Community Resources 12 3 Trademarks eee 12 4 Electrostatic Discharge Caution advected 12 5 GIOSSANY satssecieiess ge tested aaa iar Mechanical Packaging and Orderable Informati n sninen 40 Changes from Revision E March 2013 to Revision F Page e Added Pin Configuration and Functions section ESD Ratings table Feature Description section Device Functional Modes Application and Implementation section Power Supply Recommendations section Layout section Device and Documentation Support section and Mechanical Packaging and Orderable Information section ecccseeeeeeteeeee 1 Removed Product AIQHUONIS issis apneni eaae a Taa dunieb esas eea asiaa eina a eaaet 1 Changes from Revision D January 2011 to Revision E Page e Changed layout of National Data Sheet to TI format ee ecceeceeeeeeeneeeeee cnet eeaeeseeeeeaeeeaeesaeesaeeeaeesaeeseaeesaeeseeeseaeesieeseneeeaten 27 2 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS ADC128D818 www ti com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 5 Description continued The ADC can use either an internal 2 56 V reference or a
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50. lt ___ Serial Bus Address gt a Register Address gt f Byte from Master Byte from Master ar Annnnnnnir continued 99 SDA sss T Ant ii d i e e E Pd continued D7 X D6 X D5 XD4 XD3 XD2XD1XDO Ack by Stop by ADC128D818 Master ra Data Byte Figure 27 Serial Bus Interface Write Example 2 Internal Address Register Set With Data Byte Write Frame 3 gt No Ack Stop Start by Ack by Master ADC128D818 by by Frame 1 Frame 2 Master Master lt _ Serial Bus Address gt a Data Byte gt i from ADC128D818 H l Byte from Master Figure 28 Serial Bus Interface Read Example 1 Single Byte Read With Preset Internal Address Register Start by Ack by E pe ce aster Frame 1 a Frame 2 Master Frame 3 Master Master rae Serial Bus Address Data Byte Pit Data Byte i from ADC128D818 from ADC128D818 Byte from Master Figure 29 Serial Bus Interface Read Example 2 Double Byte Read With Preset Internal Address Register SDA Start by Ack by Ack by ADC128D818 ADC128D818 Master Frame 1 Frame 2 E Bus Address alli Register 7 Byte from Master Byte from Master SCL continued F SDA eee continued continued Repeat No Ack Stop Start b AOK by b b y ADC128D818 y y Master Master Byte from Master Master Frame 3 Frame 4 Serial Bus Address Data Byte from ADC128D818 Figure 30 Serial Bus Interface Read Example 3 Sin
51. nnel 22h IN2 Reading Read Only Reading for this perspective channel 23h IN3 Reading Read Only Reading for this perspective channel 24h IN4 and IN5 Reading Read Only Reading for this perspective channel 25h IN7 and IN6 Reading Read Only Reading for this perspective channel 26h Reserved Read Only 27h Temperature Reading Read Only Reading for this perspective channel Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links ADC128D818 ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 8 6 12 Limit Registers Addresses 2Ah 39h Table 13 Addresses 2Ah 39h I TEXAS INSTRUMENTS www ti com ADDRESS REGISTER NAME READ WRITE REGISTER DESCRIPTION MODE 0 2Ah INO High Limit Read Write High Limit 2Bh INO Low Limit Read Write Low Limit 2Ch IN1 High Limit Read Write High Limit 2Dh IN1 Low Limit Read Write Low Limit 2Eh IN2 High Limit Read Write High Limit 2Fh IN2 Low Limit Read Write Low Limit 30h IN3 High Limit Read Write High Limit 31h IN3 Low Limit Read Write Low Limit 32h IN4 High Limit Read Write High Limit 33h IN4 Low Limit Read Write Low Limit 34h IN5 High Limit Read Write High Limit 35h IN5 Low Limit Read Write Low Limit 36h IN6 High Limit Read Write High Limit 37h IN6 Low L
52. oduct or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products also referred to herein as components are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty in Tl s terms and conditions of sale of semiconductor products Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed Tl assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using TI components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI components or services are used Information published by TI regarding third party products or services does not constitute a license to use such products
53. orated Submit Documentation Feedback 7 Product Folder Links ADC128D818 I TEXAS INSTRUMENTS ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 www ti com DC Electrical Characteristics continued The following specifications apply for 3 Vpc V lt 5 5 Vpc External VREF 2 56 V unless otherwise specified All limits Ta Tj 25 C unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT i Each Enabled Voltage Channel 12 ms Continuous Conversion Mode te Internal Temperature Sensor 3 6 ms Enabled Voltage Channel s and Internal Low Power Conversion Mode Temperature Sensor 728 ms MULTIPLEXER ADC INPUT CHARACTERISTICS 2 Ron ON Resistance kQ Ta Ty TMN to Tmax 10 Input Current On Channel lon Leakage Current 0 005 HA loFF Off Channel Leakage Current 0 005 uA DIGITAL OUTPUTS INT lout 5 0 mA at V 4 5 Vout Logical 0 Output Voltage V lout 3 MA at Vt 3 Ta Ty Tmn to Tmax 0 4 V V OPEN DRAIN SERIAL BUS OUTPUT SDA pet Vout Logical 0 Output Voltage lour 30 mA at Vrms Ta Ty Tmn to Tmax 0 4 V l High Level Output Current V vt 0 095 A OH OUT H Ta Ty Tmn to Tmax 1 DIGITAL INPUTS AO and A1 ViNn t Logical 1 Input Voltage Ta Ty Tmn to Tmax 0 9 x V 5 5 V Vim Logical Middle Input Voltage Ta Ty Tmn to Tmax 0 43 x 0 57 x V V V
54. otherwise specified All limits Ta T 25 C unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY CHARACTERISTICS vt Supply Volt as u oltage ai j Ta Ty Tm to Tmax 3 5 5 2 56 V External Reference Voltage ToT iT toT 125 V o gt VREF A J MN MAX 2 56 V Internal Reference Voltage 23 ppm C Interface Inactive V 5 5 Ta Ty Twin to Tmax 0 74 mA V Mode 2 Interface Inactive V 3 6 V Mode 2 Ta Ty Tmn to Tmax 0 56 mA Supply Current see Power _ Managemenh iad Mode ViTa Ta Ty Tmn to Tmax 0 65 mA oo Mode V 3 6 Te T Thnit Trax 0 48 mA Deep Shutdown Mode Ta Ty Tmn to Tmax 10 HA TEMPERATURE to DIGITAL CONVERTER CHARACTERISTICS 40 lt Ta lt 125 C Ta Ty Tmn to Tmax 3 C Temperature Error 25 lt Ta lt 100 C Ta Ty Tmn to Tmax 2 C Resolution 0 5 C ANALOG to DIGITAL CONVERTER CHARACTERISTICS n Resolution 12 bit with full scale at VREF 2 56 V 0 625 mV 1 Each input and output is protected by an ESD structure to GND as shown in the Input voltage magnitude up to 0 3 V above V or 0 3 V below GND will not damage the ADC128D818 There are diodes that exist between some inputs and the power supply rails Errors in the ADC conversion can occur if these diodes are forward biased by more than 50 mV As an example if V is 4 5 Vp
55. put function properly 4 GND GROUND Internally connected to all of the circuitry 3 0 V to 5 5 V power Bypass with the parallel combination 5 V ES POWER of 1 uF electrolytic or tantalum and 0 1 uF ceramic E bypass capacitors Int ae Interrupt Request Active Low NMOS open drain G NE EJN Digital Output Requires external pullup resistor to function properly 7 AO Tri Level Serial Address pins that allow 9 devices on a r X EJN Tri Level Inputs Single C bus 4 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 I TEXAS INSTRUMENTS ADC128D818 www ti com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 Pin Functions continued PIN TYPE DESCRIPTION NO NAME ESD STRUCTURE 9 IN7 10 IN6 11 IN5 12 IN4 The full scale range will be controlled by the internal or Analog Inputs external VREF These inputs can be assigned as single 13 INS ended and or pseudo differential inputs 14 IN2 pi 15 IN1 L 4 16 INO 7 Specifications 7 1 Absolute Maximum Ratings over operating free air temperature range unless otherwise noted 2 9 4 MIN MAX UNIT Supply Voltage V 6 0 6 V Voltage on SCL SDA AO A1 INT 0 3 6 V Voltage on INO IN7 VREF 0 3 Vt 0 3 V Input Current at Any Pin 5 mA Package Input Current 30 mA Maximum Junction Temperature Tymax 150 C Storage Temperature Tst
56. racy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release Addendum Page 1 H PACKAGE OPTION ADDENDUM IA TEXAS INSTRUMENTS www ti com 21 Apr 2015 In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 2 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 6 Nov 2015 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS Mpapa Reel Diameter Dimension designed to accommodate the component width BO Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness y Overall width of the carrier tape 4 Pitch between successive cavity centers Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O O COO 0 0 Sprocket Holes Q1 1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants All dimen
57. rol Ha Registers An IMPORTANT NOTICE at the end of this data sheet addresses availability warranty changes use in safety critical applications intellectual property matters and other important disclaimers PRODUCTION DATA ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 NO oR WD I TEXAS INSTRUMENTS www ti com Table of Contents Feature Sossen oenen ene Mets eenia a EEEE 1 Applications 2033 3 2 ccieiee heres 1 Description vce cncies gece pice cesinteedetecirneuatice eet eaecens 1 Revision History 2 Description continued 3 Pin Configuration and Functions 4 Specifications c cc eeceeceeeeeeeeeeeeeteeeeneeeneetens 5 7 1 Absolute Maximum Ratings c eccrine 5 72 ESD Ratings isa3 eaa aa aani 5 7 3 Recommended Operating Conditions 6 7 4 Thermal Information 7 5 DC Electrical Characteristics 7 6 AC Electrical Characteristics 7 7 Typical Characteristics 0 ccceeeeceeseeeeeeteeeeeneeees Detailed Description cee eeeeeeeeneeeeeee 8 1 Overview 8 2 Functional Block Diagram ee 8 3 Feature DeSCription csscccsssseessccssssenseenseeseses 4 Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version 10 11 12 13 8 4 Device Functional Modes 8 5 Programming 8 6 Register Maps Application and Implementation 9 1 App
58. s 3Fh Default Value 7 0 0000_1001 binary Table 15 Addresses 3Fh ADDRESS REGISTER NAME READ WRITE REGISTER DESCRIPTION 3Fh Revision ID Read Only Revision s ID always defaults to 0000_1001 Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links ADC128D818 I TEXAS INSTRUMENTS ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 www ti com 9 Application and Implementation NOTE Information in the following applications sections is not part of the Tl component specification and Tl does not warrant its accuracy or completeness Tl s customers are responsible for determining suitability of components for their purposes Customers should validate and test their design implementation to confirm system functionality 9 1 Application Information 9 1 1 Digital Output Dour The digital output code for a 12 bit ADC can be calculated as Dour AVIN VREF x 2t 1 For Equation 1 AVIN INx GND where 0 lt x lt 7 for the single ended configuration and AVIN IN IN for the pseudo differential configuration In theory AVIN can be of any value between 0 V and VREF 3LSb 2 Any AVIN value outside of this range will produce a digital output code of O or 4095 Figure 32 shows a theoretical plot of Dour vs AVIN and some sample Dour calculation using Equation 1 Dout ro 3200d gt 1600d gt Uo i
59. s a power on reset POR on several of its registers which sets the registers to their default values These default values are shown in Table 19 or in Register Maps Registers whose default values are not shown have power on conditions that are indeterminate 9 2 2 2 3 Configuration Register address 00h The Configuration Register address 00h provides all control to the ADC128D818 After POR the START bit bit 0 is set low and the INT_Clear bit bit 3 is set high The Configuration Register has the ability to start and stop the ADC128D818 enable and disable the INT output and set the registers to their default values e Bit 0 START controls the monitoring loop of the ADC128D818 After POR set this bit high to start conversion Setting this bit low stops the ADC128D818 monitoring loop and puts the ADC128D818 in shutdown mode thus reducing power consumption Even though this bit is set low serial bus communication is possible with any register in the ADC128D818 After an interrupt occurs the INT pin will not be cleared if the user sets this bit low e Bit 1 INT_Enable enables the interrupt output pin INT when this bit is set high e Bit 3 INT_Clear clears the interrupt output pin INT when this bit is set high When this bit is set high the ADC128D818 monitoring function will stop The content of the Interrupt Status Register address 01h will not be affected e Bit 7 INITIALIZATION accomplishes
60. sions are nominal Device Pack Materials Page 1 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 6 Nov 2015 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm DC128D818CIMTX NOP TSSOP PW 16 2500 367 0 367 0 35 0 B Pack Materials Page 2 MECHANICAL DATA PW R PDSO G16 PLASTIC SMALL OUTLINE O i Gage P me fg 3 lt U I9 4040064 4 G 02 11 NOTES A All linear dimensions are in millimeters Dimensioning and tolerancing per ASME Y14 5M 1994 B This drawing is subject to change without notice Body length does not include mold flash protrusions or gate burrs Mold flash protrusions or gate burrs shall not exceed 0 15 each side Body width does not include interlead flash Interlead flash shall not exceed 0 25 each side E Falls within JEDEC MO 153 A Texas INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any pr
61. such as voltage dividers must be located physically as close as possible to the ADC128D818 11 2 Layout Example INO IN1 IN2 IN3 IN4 INS ING IN7 Figure 42 Sample Layout Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Links ADC128D818 I TEXAS INSTRUMENTS ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 www ti com 12 Device and Documentation Support 12 1 Documentation Support 12 1 1 Related Documentation For related documentation see the following e LM94022 22Q 1 5V SC70 Multi Gain Analog Temp Sensor w Class AB Output SNIS140 e LM4040 EP Precision Micropower Shunt Voltage Reference SLOS746 e LM4050 N LM4050 N Q1 Precision Micropower Shunt Voltage Reference SNOS455 e LM4120 Precision Micropower Low Dropout Voltage Reference SNVS049 e LM4140 High Precision Low Noise Low Dropout Voltage Reference SNVS053 12 2 Community Resources The following links connect to TI community resources Linked contents are provided AS IS by the respective contributors They do not constitute TI specifications and do not necessarily reflect TI s views see TI s Terms of Use TI E2E Online Community TI s Engineer to Engineer E2E Community Created to foster collaboration among engineers At e2e ti com you can ask questions share knowledge explore ideas and help solve problems with fellow engineers Design Support TI s Design Support Quic
62. t 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links ADC128D818 I TEXAS INSTRUMENTS ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 www ti com System Examples continued Take care to bypass V with decoupling 0 1 uF ceramic capacitor and 1 uF tantalum capacitor If using the external reference option VREF must be connected to a voltage reference such as the LM4140 and must also be decoupled to the ground plane by a 0 1 uF ceramic capacitor and a 1 uF tantalum capacitor For both supplies the 0 1 uF capacitor must be located as close as possible to the ADC128D818 Since SDA SCL and INT are open drain pins they must have external pullup resistors to ensure that the bus is pulled high until a master device or slave device sinks enough current to pull the bus low A typical pullup resistor R ranges from 1 1 kQ to 10 kQ Refer to NXP s I2C Bus Specification and User Manual for more information on sizing R Because there are two tri level address pins AO and A1 up to 9 devices can share the same C bus A trick to set these serial addresses uses four GPO general purpose output pins from the master device as shown in the example diagram Table 20 shows how to program these GPO pins Table 20 Setting Serial Bus Address Using GPO Al AO GPO1 GPO2 GPO3 GPO4 LOW LOW Z LOW Z LOW LOW MID Z LOW HIGH LOW LOW HIGH Z LOW HIGH Z MID LOW HIGH LOW Z
63. t et at tt x 1 gt AV jn 1y 2V VREF 3VREF 221 Figure 32 Dour vs AVIN for a 12 Bit ADC Assuming VREF 2 56 V 9 1 2 Temperature Measurement System The ADC128D818 delta Vge type temperature sensor and delta sigma ADC perform 9 bit two s complement conversions of the temperature This temperature reading can be obtained at the Temperature Reading Register address 27h This register is 16 bit wide and thus all 9 bits of the temperature reading can be read using a double byte read Figure 29 or Figure 31 The following Figure 33 and Figure 33 show the theoretical output code Dour vs temperature and some typical temperature to code conversions 28 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS ADC128D818 www ti com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 Application Information continued 0 1111 1010 j 0 0011 0010 0 0000 0001 Temperature 550C 1 4114 1111 125 C 1 1100 1110 1 1001 0010 Non Linear Scale for Clarity Figure 33 9 Bit Temperature to Digital Transfer Function Table 16 Temperature Registers Sample Temperatures DIGITAL OUTPUT D TEMP Dout BINARY MSb LSb DECIMAL HEX 125 C 0 _1111_1010 250 0_FA 25 C 0_0011_0010 50 0_32 0 5 C 0_0000_0001 1 0_01 0 C 0_0000_0000 0 0_00 0 5 C 1_1111_1111 511 1_FF 25 C 1_1100_1110 462 1_CE 40
64. terface modes of operation ADC128D818 includes an analog filter on the I C digital control lines that allows improved noise immunity The device also supports TIME OUT reset function on SDA and SCL to prevent I C bus lock up Two tri level address pins allow up to 9 devices on a single 1C bus At start up ADC128D818 cycles through each measurement in sequence and continuously loops through the sequence based on the Conversion Rate Register address 07h setting Each measured value is compared to values stored in the Limit Registers addresses 2Ah 39h When the measured value violates the programmed limit the ADC128D818 will set a corresponding interrupt bit in the Interrupt Status Registers address 01h An interrupt output pin INT is also available and fully programmable 8 2 Functional Block Diagram Watchdog Limi im mMm Lower pper ower Limi pper Lim ower Limi pper Limi ower Limi Limi INO IN1 IN2 IN3 IN4 IN5 ING IN7 CiciIcic D ke D S Interrupt Interrupt Masking Status and Registers ower Limi pper Lim ower Limi per Lim ower Limi eee Limi Lower Limit Temperature mee P Internal VREF 2 56V Interface and Control Control e J v GND SCL SDA AO Al Serial Bus Interface 14 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC128D818 1 TEXAS INSTRUMENTS ADC128D818 www ti
65. the same function as POR that is it initializes some of the registers to their default values This bit automatically clears after being set high Setting this bit high however does not reset the Channel Readings Registers addresses 20h 27h and the Limit Registers addresses 2Ah 39h These registers will be indeterminate immediately after power on If the Channel Readings Registers contain valid conversion results and or the Limit Registers have been previously set they will not be affected by this Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Links ADC 128D818 I TEXAS INSTRUMENTS ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 www ti com bit 9 2 2 2 4 Interrupt Status Register address 01h Each bit in this read only register indicates whether the voltage reading gt the voltage high limit or lt the voltage low limit or the temperature reading gt the temperature high limit For example if INO High Limit register address 2Ah were set to 2 V and if INO reading address 20h were 2 56 V then bit INO Error would be 1 indicating that the voltage high limit has been exceeded 9 2 2 2 5 Interrupt Mask Register address 03h This register masks the interrupt status from propagating to the interrupt output pin INT For example if bit INO Mask 1 then the interrupt output pin INT would not be pulled low even if an error event occurs at INO 9 2 2
66. to Tmax 25 35 ms 1 Limits are ensured to AOQL Average Outgoing Quality Level 2 Typicals are at Ty T 25 C and represent most likely parametric normal SDA 5 Data Out 5 Figure 1 Serial Bus Timing Diagram Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links ADC 128D818 I TEXAS INSTRUMENTS ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 www ti com 7 7 Typical Characteristics The following typical performance plots apply for the internal VREF 2 56 V V 3 3 V Pseudo Differential connection unless otherwise specified All limits Ta Tj 25 C unless otherwise specified 0 023 0 010 0 014 0 074 gt 0 004 0 138 x x Ww Ww 5 gt F 0 005 F 0 202 0 015 0 266 0 024 0 330 500 0 1 2k 19k 27k 34k 4 1k 500 0 1 2k 19k 27k 34k 4 1k CODE CODE Figure 2 TUE vs Code Figure 3 TUE vs Code External VREF 1 25 V 0 020 0 020 0 060 0 064 0 100 0 108 D D W W gt F 0 140 F 0 152 0 180 0 196 0 220 0 240 500 0 1 2k 19k 27k 34k 4 1k 500 0 1 2k 19k 27k 34k 4 1k CODE CODE Figure 4 TUE vs Code External VREF 2 56 V Figure 5 TUE vs Code External VREF 5 V V 5 V 2 0 1 00 1 5 0 75 1 0 0 50 T 05 a 0 25 a a 00 J 0 00 Zz Z
67. to clear the interrupt output pin INT is setting INT_Clear bit address 00h bit 3 1 When this bit is high the ADC128D818 round robin monitoring loop will stop 30 Submit Documentation Feedback Copyright 2010 2015 Texas Instruments Incorporated Product Folder Links ADC 128D818 I TEXAS INSTRUMENTS ADC128D818 www ti com SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 9 1 3 3 Temperature Interrupt One of the ADC128D818 features is monitoring the temperature reading This monitoring is accomplished by setting a temperature limit to the Temperature High Limit Register Thot address 38h and Temperature Hysteresis Limit Register Thot nyss address 39h These limit registers have an interrupt mode shown in Figure 35 that operates in the following way if the temperature reading gt Thon an interrupt will occur and will remain active indefinitely until reset by reading the Interrupt Status Register address 01h or cleared by the INT_Clear bit Once an interrupt event has occurred by crossing Tho then reset an interrupt will occur again once the next temperature conversion has completed The interrupts will continue to occur in this manner until the temperature reading is lt Thot nyst and a read of the Interrupt Status Register has occurred Thot 38h Thot hyst 39h Hot Temp Error 01h 7 INT pin 6 Figure 35 Temperature Response Structure Assuming the Interrupt Output Pin INT is Reset Before the Next Temp
68. ts the revision s ID 8 bit 9 2 2 2 1 Quick Start 1 Power on the device then wait for at least 33ms 2 Read the Busy Status Register address OCh If the Not Ready bit 1 then increase the wait time until Not Ready bit 0 before proceeding to the next step 3 Program the Advanced Configuration Register Address OBh a Choose to use the internal or external VREF bit 0 b Choose the mode of operation bits 2 1 4 Program the Conversion Rate Register address 07h Choose to enable or disable the channels using the Channel Disable Register address 08h 6 Using the Interrupt Mask Register address 03h choose to mask or not to mask the interrupt status from propagating to the interrupt output pin INT 7 Program the Limit Registers addresses 2Ah 39h Set the START bit of the Configuration Register address OOh bit 0 to 1 9 Set the INT_Clear bit address 00h bit 3 to 0 If needed program the INT_Enable bit address 00h bit 1 to 1 to enable the INT output g 0 The ADC128D818 then performs a round robin monitoring of enabled voltage and temperature channels The sequence of items being monitored corresponds to locations in the Channel Readings Registers except for the temperature reading Detailed descriptions of the register map can be found at the end of this data sheet 9 2 2 2 2 Poweron Reset POR When power is first applied the ADC 128D818 perform
69. variable external reference An analog filter is included on the IC digital control lines to provide improved noise immunity The device also includes a TIME OUT reset function on SDA and SCL to prevent 1 C bus lock up The ADC128D818 operates from 3 V to 5 5 V power supply voltage range 40 C to 125 C temperature range and the device is available in a 16 pin TSSOP package Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links ADC 128D818 ADC128D818 SNAS483F FEBRUARY 2010 REVISED AUGUST 2015 6 Pin Configuration and Functions PW Package 16 Pin TSSOP Top View I TEXAS INSTRUMENTS www ti com Pin Functions PIN TYPE DESCRIPTION NO NAME ESD STRUCTURE ADC external reference ADC128D818 allows two choices for sourcing VREF internal or external If the 2 56 V internal VREF is used leave this pin unconnected If the external VREF is used 1 VREF Analog Input source this pin with a voltage between 1 25 V and V At Power On Reset POR the default setting is the internal mi VREF Bypass with the parallel combination of 1 uF electrolytic or me tantalum and 0 1 uF ceramic capacitors we Serial Bus Bidirectional Data NMOS open drain output 2 SDA EJN Digital VO Requires external pullup resistor to function properly me Serial Bus Clock Requires external pullup resistor to 3 SCL EJN Digital In

ADC128D818 12-Bit, 8-Channel, ADC Sys

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