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7630 Group USER`S MANUAL

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1. transfer clock h write signal to SIO receive enable signal Sapy Serial Output SOUT V mammae memec ed Serial input SIN XB XC XC XC OCC XC OX i XC OX Y SIO interrupt request bit 1 Note When an internal clock is selected Sour pin will change to high impedance after 8 bits of data have been transmitted Fig 26 Timing of clock synchronous SI O function LSB first selected 1 28 7630 Group User s Manual HARDWARE SERIAL I Os SIO control register address 001346 SIOCON Clock divider selection bits b2 b1 b0 000 divided by 4 divided by 8 divided by 16 divided by 32 divided by 64 divided by 128 divided by 256 divided by 512 P2 Sin P21 Sour and P25 Sc function selection bit 0 1 0 port function 1 SI O function P23 Srpy function selection bit 0 1 0 port function 1 SI O function Transmission order selection bit 0 LSB first 1 MSB first Synchronization clock selection bit 0 Use external clock 1 Useinternal clock Not used 0 when read Fig 27 Structure of serial I O control register is internal system clock Clock Asynchronous Serial I O UART The UART is a full duplex asynchronous transmit receive unit The built in clock divider and baud rate generator enable a broad range of transmission speeds Please refer to Block diag
2. Data bus UART control register UART status register Bit counter Transmit buffer 9 Transmit buffer empty interrupt request Transmit buffer empty flag r Transmit register empty interrupt request Transmit shift register 9 O P2 UTXD Transmit register empty flag Transmission On Reception control O P2 URTS circuit s r Receive error interrupt request Receive shift register 9 C P2 URXD L gt Receive error flags Receive buffer 9 Receive buffer full interrupt request gt Receive buffer full flag Fig 28 Block diagram of UART 1 30 7630 Group User s Manual Fig 29 Structure of UART mode register Fig 30 Structure of UART control register HARDWARE SERIAL I Os UART mode register UMOD address 0020 g Not used 0 when read do not write 1 Clock divider selection bits b2 b1 0 0 divided by 1 01 divided by 8 1 0 divided by 32 1 1 divided by 256 Stop bits selection bit 0 1 One stop bit Two stop bits Parity selection bit 0 Even parity 1 Odd parity Parity enable bit 0 Parity disabled 1 Parity enabled UART word length selection bits b7 b6 00 7bits 01 8bits 10 Qbits 1 1 Notused UART control register UCON address 0022 6 Transmit enable bit 0 Transmit disabled an ongoing transmission will be finished correctly
3. Contents A BIT A BIT A ZP BIT ZP R BIT ZP ZP X ZP Y ABS ABS X ABS Y IND ZP IND IND X IND Y Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit relative addressing mode Accumulator bit addressing mode Zero page addressing mode Zero page bit relative addressing mode Zero page bit addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X modified arithmetic mode flag Overflow flag Negative flag oxXxT1 X TUU ONO M ADH ADL M 00 ADL Ai Mi OP n 7630 Group User s Manual Addition Subtraction Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high order bits of program counter 8 low order bits of program counter 8 high order bits of address 8 low order bits of address FF in Hexadecimal notation Immediate value Memory specified by address designation of any ad dres
4. Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 2 4 6 Structure of CAN acceptance code register 0 CACO 2 38 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module CAN acceptance code register 1 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance code register 1 CAC1 Address 003446 B Name Function At reset 0 Not used Undefined at read Standard identifier bit 0 Standard identifier bit 1 These bits except when masked by the Standard identifier bit 2 acceptance mask register 1 Figure 2 4 12 form the acceptance filtering condition for incoming CAN frames They must be initialized with the identifier pattern of CAN frames to be received Standard identifier bit 3 Standard identifier bit 4 Standard identifier bit 5 Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 2 4 7 Structure of CAN acceptance code register 1 CAC1 CAN acceptance code register 2 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance code register 2 CAC2 Address 003546 B Name Function O Extended identifier bit 14 These bits except when masked by the acceptance mask register 2 Figure 2 4 13 for
5. AAR AA INTO INT 78 A D Converter T 2 yY r Es i P xr 1 0 port P2 y I O port P1 9 CHICA Veer input y I O port PO INVHOVIG 19079 IWNOILONNA d IV AC IVH HARDWARE PIN DESCRIPTION PIN DESCRIPTION Table 1 Pin description Power source Vec V DOES voltage Input Output Description Power supply pins apply 4 0 to 5 5 V to Vec and 0 V to Vss Analog power AV BR source voltage Ground pin for A D converter Connect to Vss RESET Reset input Input Reset pin This pin must be kept at L level for more than 2 us to enter the reset state If the crystal or ceramic resonator requires more time to stabilize extend the L level period Xin Clock input Input Input and output pins of the internal clock generating circuit Connect a ceramic or XouT Clock output Output quartz crystal resonator between the Xiy and Xoyr pins When an external clock source is used connect it to Xin and leave Xour open Reference volt Vi REF age input Input Reference voltage input pin for A D converter POyAN PO AN I O port PO 1 0 CMOS I O ports or analog input ports P1 INTo P12 INT P13 TX0 P14 CNTRo I O port P1 P1 CNTR P1 PWM P1 CMOS input port or external interrupt input port The active edge rising or falling of
6. Propagation time duration control bits b7 b6 b5 000 One Time Quantum 001 Two Time Quanta R o Seven Time Quanta 1 1 Eight Time Quanta Fig 37 Structure of CAN bus timing control register 1 HARDWARE CAN MODULE 7630 Group User s Manual 1 35 HARDWARE CAN MODULE CAN bus timing control register 2 address 003246 CBTCON2 Phase buffer segment 1 duration control bits b2 b1 bO 0 0 0 One Time Quantum 0 0 1 Two Time Quanta 0 Seven Time Quanta 1 Eight Time Quanta 11 11 Phase buffer segment 2 duration control bits b5 b4 b3 0 0 0 One Time Quantum 0 0 1 Two Time Quanta 0 Seven Time Quanta T5 11 1 1 Eight Time Quanta Synchronization jump width control bits b7 b6 0 0 One Time Quantum 0 1 Two Time Quanta 1 0 Three Time Quanta 1 1 Four Time Quanta Fig 38 Structure of CAN bus timing control register 2 name 7 O address Acceptance code CACO 003316 Select the bit pattern of identifiers which allows to pass acceptance filtering 7 0 CAM 00391 ES Nous Notes Vetoes Nertusen MED MED WED MED Ae CAM3 003B CAM4 003C 6 0 Mask identifier bit do not care 1 Compare identifier bit with acceptance code register bit Not used write to 0 Fig 39 Structure of CAN mask and code registers 1 36 7630 Group User s Manual HARDWARE CAN MODULE name offset CTB6 CRB6 Data byte 0 000646 CTB7 CRB7 Data byte 1 000746
7. Data bus Port latch m SRDY output Fig 12 Structure of port I Os 2 7630 Group User s Manual HARDWARE I O PORTS Port Pull up pull down Function Each pin of ports PO to P4 except P1 is equipped with a programma ble pull up transistor P3 CRX and P4 KW to P47 KW 7 are equipped with programmable pull down transistors as well The pull up function of PO to P3 can be controlled by the corresponding port pull up control registers see Structure of port pull up down control ister Port Pi pull up control register address 002846 i i 0 2 PUPO PUP2 Pi pull up transistor control bit j 0 to 7 0 Pull up transistor disabled 1 Pull up transistor enabled Port P1 pull up control register address 002946 PUP1 Not used 0 when read do not write 1 P1 pull up transistor control bit j 2 to 7 Port P3 pull up control register address 002B g PUP3 P3 pull up transistor control bit j 0 1 P3 pull up down transistor control bit P3 pull up transistor control bit j 3 4 Not used 0 when read do not write 1 Port P4 pull up down control register address 002C g PUP4 P4 pull up down transistor control bit j 0 to 7 0 Pull up down transistor disabled 1 Pull up down transistor e
8. Standard identifier mask bi Standard identifier mask bi Standard identifier mask bi 0 Mask identifier bit don t care 1 Compare identifier bit Standard identifier mask bi These bits mask the corresponding bit of the acceptance code register 1 Figure 3 5 37 from the acceptance filtering Standard identifier mask bi Standard identifier mask bi Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 3 5 42 Structure of CAN acceptance mask register 1 CAM1 3 42 7630 Group User s Manual APPENDIX 3 5 List of registers CAN acceptance mask register 2 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance mask register 2 CAM2 Address 003A g B Name Function At reset O Extended identifier mask bit 14 2 Extended identifier mask bit 15 0 Mask identifier bit don t care 1 Compare identifier bit Extended identifier mask bit 16 These bits mask the corresponding bits of the acceptance code register 2 Figure 3 5 38 from the acceptance filtering Extended identifier mask bit 17 These bits must be set to 0 Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 3
9. Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 3 5 35 Structure of CAN bus timing control register 2 CBTCON2 CAN acceptance code register 0 b7 b6 b5 b4 b3 b2 bi b0 CAN acceptance code register 0 CACO Address 003346 B Name Function At reset 0 Standard identifier bit 6 Standard identifier bit 7 Standard identifier bit 8 Standard identifier bit 9 Standard identifier bit 10 These bits except when masked by the acceptance mask register 0 Figure 3 5 41 form the acceptance filtering condition for incoming CAN frames They must be initialized with the identifier pattern of CAN frames to be received Not used Undefined at read Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 3 5 36 Structure of CAN acceptance code register 0 CACO 7630 Group User s Manual 3 39 APPENDIX 3 5 List of registers CAN acceptance code register 1 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance code register 1 CAC1 Address 003446 B Name Function At reset 0 Not used Undefined at read Standard identifier bit 0 Standard identifier bit 1 These bits except when m
10. 7630 Group User s Manual 3 57 APPENDIX 3 10 Machine instructions Function Details Addressing mode A BIT A R ZP BIT ZP R n JOP n JOP OP n If addressing mode is ABS PCL ADL PCH lt ADH If addressing mode is IND PCL lt M ADH ADL PCH M ADH ADL 1 If addressing mode is ZP IND PCL M 00 ADL PCH amp M 00 ADL 1 Jumps to the specified address M S PCH Sc 8 1 M S PCL S 8 1 After executing the above if addressing mode is ABS PCL ADL PCH lt ADH if addressing mode is SP PCL ADL PCH amp FF If addressing mode is ZP IND PCL M 00 ADL PCH amp M 00 ADL 1 After storing contents of program counter in stack and jumps to the specified address LDA Note 2 When T 0 AM When T 1 M X M Load accumulator with contents of memory Load memory indicated by index register X with contents of memory specified by the ad dressing mode M amp nn Load memory with immediate value XM Load index register X with contents of memory Load index register Y with contents of memory 7 0 0 gt L_ E Shift the contents of accumulator or memory to the right by one bit The low order bit of accumulator or memory is stored in carry 7th bit is cleared M S A C A X M zz X S 8 1 Multiplies the
11. Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 2 4 14 Structure of CAN acceptance mask register 3 CAM3 2 42 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module CAN acceptance mask register 4 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance mask register 4 CAM4 Address 003C46 B Name Function At reset 0 These bits must be set to 0 Extended identifier mask bit 0 Extended identifier mask bit 1 Extended identifier mask bit 2 0 Mask identifier bit don t care 1 Compare identifier bit Extended identifier mask bit 3 These bits mask the corresponding bits of the acceptance code register 4 Figure 2 4 10 from the acceptance filtering Extended identifier mask bit 4 Extended identifier mask bit 5 Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 2 4 15 Structure of CAN acceptance mask register 4 CAMA CAN receive control register DILE Dy pi 9n Beo IND CAN receive control register CREC Address 003D 4g B Name Function Receive buffer empty undefined Receive buffer full Release clear receive buffer No operation CAN module idle or transmitting CAN
12. 3 9 3 3 1 Sta O 2 ld e Q A 3 3 2 eN 3 16 3 4 1 Wiring for the RESET input pin tee 3 17 3 4 2 Wiring for clock VO pins ee 3 17 3 4 3 Wiring for the VPP pin of the One Time PROM and the EPROM version 3 18 3 4 4 Bypass capacitor across the VSS line and the VCC ine 3 18 3 4 5 Analog signal line and a resistor and a capacitor 3 18 3 4 6 Wiring for a large current signal fine 3 19 3 4 7 Wiring to a signal line where potential levels change frequently 3 19 3 4 8 WSS pattern on the underside of an oscillator 3 20 a DERE AA 3 20 7630 GROUP USER S MANUAL vii List of figures Fig 3 4 10 Watchdog timer Dy software 3 21 Fig 3 5 1 Btructure of CPU mode register sss nennen 3 22 Fig 3 5 2 Structure of Interrupt request register A 3 22 Fig 3 5 3 Structure of Interrupt request register B 3 23 Fig 3 5 4 Structure of Interrupt request register C 3 23 Fig 3 5 5 Structure of Interrupt control register A 3 24 Fig 3 5 6 Structure of Interrupt control register BJ 3 24 Fig 3 5 7 Structure of Interrupt control register C sse 3 25 Fig 3 5 8 Structure of Port Pi register i 0 1 2 3 4 eccecccccscscssscssssssssssseseseseecseanenees 3 25 Fig 3 5 9 Structure of Port Pi direction register i 0 1 2 3 4 sss 3 26 Fig 3 5 10 Btructure of Serial VO shift register sss
13. 2 17 Fig 2 3 1 Memory map of timer related registers ssssssemm 2 18 Fig 2 3 2 Structure of Timer 1 Timer 3 2 19 Fig 2 3 3 Structure of Timer 2 Joennn nnn 2 19 Fig 2 3 4 Structure of Timer 123 mode TOS coccion cinco 2 20 Fig 2 3 5 Structure of Timer XL Timer XH Timer YL Timer YH 2 20 Fig 2 3 6 Structure of Timer X mode register 2 21 Fig 2 3 7 Structure of Timer Y mode register cccecceececeeeeeeeeececeeeeeseeseeeeeeeeeeeeaees 2 21 Fig 2 3 8 Timers connection and division ratios Clock functionl 2 23 Fig 2 3 9 Setting of related registers Clock function 2 24 Fig 2 3 10 Control procedure Clock funcio loci conocen 2 25 Fig 2 3 11 A method for judging if input pulse exists 2 26 Fig 2 3 12 Setting of related registers Measurement of frequency 1 2 27 Fig 2 3 13 Setting of related registers Measurement of frequency 2 2 28 Fig 2 3 14 Control procedure Measurement of frequency sssss 2 29 Fig 2 3 15 Timer connection and division ratios Measurement of pulse width 2 30 Fig 2 3 16 Setting of related registers Measurement of pulse width 2 31 Fig 2 3 17 Control procedure Measurement of pulse width 1 s 2 32 Fig 2 3 18 Control procedure Measurement of pulse width 2 2 33 Fig 2 4 1 Block diagram of CAN modu
14. Step 3 Pull up down the ports of P4 used as key on wake up input pin b7 b0 Port P4 pull up down control register PUP4 Address 002C16 Port P40 pull up down transistor control bit Port P41 pull up down transistor control bit Port P42 pull up down transistor control bit Port P43 pull up down transistor control bit 0 No pull up down Port P44 pull up down transistor control bit 1 Pull up down Port P45 pull up down transistor control bit Port P46 pull up down transistor control bit Port P47 pull up down transistor control bit Step 4 Set the key on wake up polarity b7 bo Polarity control register PCON Address 002F 16 Key on wake up polarity control bit 0 Low level active P4 pull up 1 High level active P4 pull down Fig 2 2 12 Setting method for registers related to key on wake up interrupt 1 2 16 7630 Group User s Manual APPLICATION 2 2 Interrupts Clear the Key on wake up interrupt request bit to O no interrupt request b7 bO ler T IEFELRT Interrupt request register C IREQC Address 000416 Key on wake up interrupt request bit Set the Key on wake up interrupt enable bit to 1 interrupt enabled b7 bO BIET ETT Interrupt control register C ICONC Address 000716 Key on wake up interrupt enable bit When the Interrupt disable flag I is set to 1 in Step 1 clear the flag to 0 interrupt enabled Execute the STP WIT instruction to switch procedur
15. Standard identifier bit 4 Standard identifier bit 5 For CTB1 These bits represent part of the identifier field of a frame to be transmitted For CRB1 These bits represent part of the identifier field of a frame received Note 1 Identifier extension bit Note 2 Remote transmission request bit Note 3 Substitute remote request bit Fig 2 4 19 Structure of CAN transmit receive buffer registers 1 CTB1 CRB1 CAN transmit receive buffer registers 2 b7 b6 b5 b4 b3 b2 b1 bo CAN transmit buffer register 2 CTB2 Address 0042 g CAN receive buffer register 2 CRB2 Address 0052 g B Name Function 0 Extended identifier bit 14 Extended identifier bit 15 Extended identifier bit 16 Extended identifier bit 17 For CTB2 These bits represent part of the identifier field of a frame to be transmitted For CRB2 These bits represent part of the identifier field of a frame received Not used When these bits are read out the values are 0 Don t write to 1 Fig 2 4 20 Structure of CAN transmit receive buffer registers 2 CTB2 CRB2 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module CAN transmit receive buffer registers 3 b7 b6 b5 b4 b3 b2 b1 bo CAN transmit
16. Fig 3 5 48 Structure of CAN transmit receive buffer registers 0 CTBO CRBO 7630 Group User s Manual 3 45 APPENDIX 3 5 List of registers CAN transmit receive buffer registers 1 b7 b6 b5 b4 b3 b2 b1 bo CAN transmit buffer register 1 CTB1 Address 0041 g CAN receive buffer register 1 CRB1 Address 005146 B Name Function At reset 0 IDE bit 0 Standard format 1 Extended format RTR SRR bit RTR bit frames of standard format or SRR bit frames of extended format Standard identifier bit 0 Standard identifier bit 1 Standard identifier bit 2 Standard identifier bit 3 Standard identifier bit 4 Standard identifier bit 5 For CTB1 These bits represent part of the identifier field of a frame to be transmitted For CRB1 These bits represent part of the identifier field of a frame received Note 1 Identifier extension bit Note 2 Remote transmission request bit Note 3 Substitute remote request bit Fig 3 5 49 Structure of CAN transmit receive buffer registers 1 CTB1 CRB1 CAN transmit receive buffer registers 2 b7 b6 b5 b4 b3 b2 b1 bo CAN transmit buffer register 2 CTB2 Address 0042 g CAN receive buffer register 2 CRB2 Address 0052 g B Name Function 0 Extende
17. RO CPU access possible R1 CPU access not possible WO No operation W1 Lock transmit buffer Transmit buffer control bit Reserved 0 when read 0 CAN module idle or receiving 1 CAN module transmitting Transmit status bit Note 1 RO R1 denote read access WO W1 denote write access Fig 2 4 3 Structure of CAN transmit control register CTRM CAN bus timing control register 1 b7 b6 b5 b4 b3 b2 bi bO CAN bus timing control register 1 CBTCON1 Address 003146 B Name Function At reset 0 b3b2b1b0 0 0000 Divided by 1 0001 Divided by 2 Prescaler division ratio 0010 Divided by 3 selection bits 1101 Divided by 14 1110 Divided by 15 1111 Divided by 16 0 One sample per bit 1 Three samples per bit b7b6b5 000 One time quantum Propagation time duration 001 Two time quanta control bits Sampling control bit 110 Seven time quanta 111 Eight time quanta Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 2 4 4 Structure of CAN bus timing control register 1 CBTCON1 7630 Group User s Manual 2 37 APPLICATION 2 4 Controller Area Network CAN module CAN bus timing control register 2 b7 b6 b5 b4 b3 b2 bi bO CAN bus timing control register 2
18. level output PWM output enable bit 0 PWM output disabled 1 PWM output enabled 2 Timer 2 write control bit 0 Latch and counter 1 Latch only 3 Timer 2 count source selection bit i Timer 1 underflow Pre divider output 4 Timer 3 count source selection bit Timer 1 underflow Pre divider output 5 Not used 0 when read don t write 1 Pre divider division ratio bits divided by 1 Note divided by 8 Note divided by 32 Note divided by 128 Note Note The internal system clock q is divided f XIN by 2 or by 8 The division ratio is decided by the Internal system clock selection bit bit 6 of the CPU mode register address 000016 Fig 2 3 4 Structure of Timer 123 mode register Timer XL Timer XH Timer YL Timer YH b7 b6 b5 b4 b3 b2 bi bO Timer XL TXL Timer XH TXH Address 001A16 001B16 Timer YL TYL Timer YH TYH Address 001C16 001D16 Set 000016 to FFFF16 as timer count value Write access The timer value is written to Timer X or Timer Y and latch at the same timer or to the latch only Note Write first low byte TXL TYL and then high byte TXH TYH Read access To get the actual Timer X or Timer Y value read out the corresponding timer register A measurement value is read out in pulse period and pulse width measurement mode Read first high byte TXH TYH and then low byte TXL TYL Note Depinding on the Timer X
19. 1 2 How to reference the processor status register To reference the contents of the processor status register PS execute the PHP instruction once then read the contents of S 1 If necessary execute the PLP instruction to return the PS to its original status A NOP instruction must be executed after every PLP instruction S S 1 Stored PS PLP instruction execution Fig 3 3 1 Stack memory contents after instruction execution 7630 Group User s Manual 3 15 APPENDIX 3 3 Notes on use 3 Detection of BRK instruction interrupt source It can be detected that the BRK instruction interrupt event or the least priority interrupt event Co a a 7 4 0 by referring the stored B flag state Refer to the stored B flag state in the interrupt routine A ES B flag PCL Low order of program counter PCH High order of program counter Fig 3 3 2 Interrupt routine 4 Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation set the decimal mode flag D to 1 with the SED instruction After executing the ADC or SBC instruction execute another instruction before executing the SEC CLC or CLD instruction 5 Notes on status flags in decimal mode When decimal mode is selected the values of three of the flags in the status register the N V and Z flags are invalid after a ADC or SBC instruction is executed ADC or SBC instruct
20. 2 10 Development support tools M37630T RFS The M37630T RFS is a conversion board to use M37630E4FS as emulator MCU When an emulator is connected to the socket on the top surface user program debugging can be performed efficiently by using a real time trace function etc Since address bus signals data bus signals SYNC RD WR and f signals are output from the socket emulator can monitor all bus information in the microcomputer For details of development support systems for the M37630T RFS refer to the DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTER data book Figure 2 10 1 shows an example of configuration example of using M37630T RFS M38000T FPD or M38000TL FPD or M38000TL2 FPD M37630E4FS Emulation Pod Probe M37630T RFS TQPACK044SA Soldering x Foot pattern 44P6N A ZA User s target TQSOCKET044SAF TQSOCKET044SAG and TQPACK044SA are the products made by Tokyo Eletec Co Ltd Fig 2 10 1 Configuration example of using M37630T RFS 3 100 7630 Group User s Manual APPLICATION 2 11 Built in PROM version 2 11 Built in PROM version In contrast with the mask ROM version a microcomputer incorporating a programmable ROM is called built in PROM version There are two types of built in PROM version as shown below One Time PROM version Writing to the built in PROM can be performed only once Neither erase nor rewrite operation is enabled O Built in EPROM version The bu
21. Release communication functions the module becomes an active node on the network and may transmit and receive CAN frames For details on the transmit and receive operations as well as corresponding inter rupt functions see sections 2 4 8 to 2 4 11 2 48 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module Lock the following registers to prevent accidental modifications 1 acceptance code and mask registers CACi CAMi Figures 2 4 6 to 2 4 15 2 CAN bus timing control registers CBTCONI Figures 2 4 4 and 2 4 5 Release the internal fault confinement logic transmit and receive error counters the module may leave the error active state depending on the error counts refer to section 2 4 12 Ensure to initialize the module by using the above mentioned configuration mode before entering normal run mode for details refer to section 2 4 5 Within normal run mode the module can be in three different sub modes depending on which type of com munication functions are actually performed see Figure 2 4 26 Idle The module s receive and transmit sections are inactive Receiving The module is receiving a frame sent by another node Transmitting The module transmits a frame Simultaneously the module may receive its own frame this is called auto receive function for details refer to section 2 4 8 5 From CPU side the sub modes may be monitored by the receive and transmit status bits
22. The receive buffers support both standard and extended frame formats of data and remote type The buffers hold the following information on the received frame Identifier standard or extended Frame type data frame or remote frame Data length in case of a data frame and Data bytes in case of a data frame 1 Message storage As explained above the module features two receive buffers after initialization both buffers are empty unde fined Upon successful reception of the first relevant refer to section 2 4 7 frame the module will 1 Store the frame in one of the buffers 2 Switch the buffer to foreground to permit CPU access 3 Flag the reception by special function bits and interrupt service request details in section 2 The foreground buffer holding the message received is now under exclusive control of the CPU while the background buffer is still vacant After having processed the buffer contents the CPU should release the buffer and thereby return buffer con trol to the module Following to release the buffer content is not available to the CPU any more and can not be recaptured in any way 7630 Group User s Manual 2 55 APPLICATION 2 4 Controller Area Network CAN module A second message can be stored to the background buffer while the CPU still deals with the foreground buffer for an example see Figure 2 4 34 while the CPU still processes frame C the module simultaneously receives frame
23. tr CMOS CMOS output rise time F CMOS CMOS output fall time Measurement output pin O CMOS output Fig 51 Circuit for measuring output switching characteristics 7630 Group User s Manual 1 49 HARDWARE TIMING DIAGRAM TIMING DIAGRAM CNTRo CNTR INT INT Fig 52 Timing diagram 1 50 twu CNTR twL CNTR 1 0 8 Vcc 0 2 Voc tsu Sin Scik SSSXXXXXXXXX SRRI ZSSS SA ALIOS tp ScucSour OSOS OSOS SELLER tv ScucSour 7630 Group User s Manual CHAPTER 2 APPLICATION 2 1 I O Ports 2 2 Interrupts 2 3 Limers 2 4 Controller Area Network CAN module 2 5 Serial I O 2 6 A D converter 2 7 Watchdog timer 2 8 Reset 2 9 Oscillation circuit 2 10 Development support tools 2 11 Built in PROM version APPLICATION 2 1 1 0 ports 2 1 1 0 ports 2 1 1 Memory map of I O ports 000816 Port PO register PO 000916 Port PO direction register POD 000A16 Port P1 register ister P1 000816 Port P1 direction register P1D 000016 Port P2 register P2 000D16 Port P2 direction register P2D ister P3 ister P3D P4 000E16 000F16 001016 001116 002816 Port PO pull up control register PUPO 002916 Port P1 pull up control register PUP1
24. 003Di 0046 Timer 2 001716 0116 CAN transmit abort reg 003E 6 0016 Timer 3 001846 FFig Processor status reg PS 0446 Timer 123 mode reg 001946 4016 Program counter high order byte PCH contents of FFFBi Timer XL 001A 6 FFig Program counter low order byte PCL contents of FFFA Note The contents of RAM and registers other than the above registers are undefined after reset thus software initialization is required Fig 47 Internal status of microcomputer after reset 1 42 7630 Group User s Manual HARDWARE CLOCK GENERATING CIRCUIT CLOCK GENERATING CIRCUIT The 7630 group is equipped with an internal clock generating circuit Please refer to Fig 48 for a circuit example using a ceramic resona tor or quartz crystal oscillator For the capacitor values refer to the manufacturers recommended parameters which depend on each oscillators characteristics When using an external clock input it to the Xiy pin and leave Xoyy open Oscillation Control The 7630 group has two low power modes the stop and the wait mode Stop mode The microcomputer enters the stop mode by executing the STP instruction The oscillator stops with the internal clock at H level Timers 1 and 2 will be cascaded and initialized by their reload latches contents The count source for timer 1 will be set
25. 1 Transmit enabled Receive enable bit 0 Receive disabled an ongoing reception will be finished correctly 1 Receive enabled Transmission initialization bit 0 No action 1 Clear transmit buffer full flag and transmit shifter full flag set the transmit status register bits and stop transmission Receive initialization bit 0 No action 1 Clear receive status flags and the receive enable bit Not used 0 when read do not write 1 7630 Group User s Manual 1 31 HARDWARE SERIAL I Os Fig 31 Structure of UART status register 1 32 UART status register address 002346 USTS Transmission register empty flag 0 Register full 1 Register empty Transmission buffer empty flag 0 Buffer full 1 Buffer empty Receive buffer full flag 0 Buffer full 1 Buffer empty Receive parity error flag 0 No parity error detected 1 Parity error detected Receive framing error flag 0 No framing error detected 1 Framing error detected Receive overrun flag 0 No overrun detected 1 Overrun detected Receive error sum flag 0 No error detected 1 Error detected Not used 0 when read Note this register is read only writing does not affect its contents 7630 Group User s Manual HARDWARE CAN MODULE CAN MODULE The CAN Controller Area Network interface of the 7630 group com plies with the 2 0B specification enabling reception and transmis
26. 5 NT INTo INT1 input L pulse width tc SCLk Serial I O clock input cycle time twH SCLK Serial I O clock input H pulse width twL SCLK Serial I O clock input L pulse width tsu SIN SCLK Serial I O clock input set up time tH SCLK SIN Serial I O clock input hold time 7630 Group User s Manual APPENDIX 3 1 Electrical characteristics 3 1 6 Switching characteristics Table 3 1 6 Switching characteristics Vcc 4 0V to 5 5V Vss AVss OV Ta 40 C to 85 C unless otherwise noted Limits Typ Parameter Test conditions twH SCLK Serial I O clock output H pulse width 0 5 tc SCLK 50 twL SCLk Serial I O clock output L pulse width 0 5 tc ScLK 50 tD SCLK SOUT Serial I O output delay time Serial I O output valid time Serial I O clock output rise time CMOS output rise time CMOS output fall time Measurement output pin 100 pF CMOS output Fig 3 1 1 Circuit for measuring output switching characteristics 3 6 7630 Group User s Manual APPENDIX 3 1 Electrical characteristics tWH TXo tWL TX0 tWH CNTR tWL CNTR CNTRo CNTR1 tWH INT tWL INT INTO INT BP am Vy twL RESET RESET Ne P tC XIN TWH XIN tWL XIN tWL SCLk twH ScLk tsu SIN SCLK tH SCLK SIN NXXX KKK
27. 8 MHz is divided by a timer The clock is counted at intervals of 25 ms by the Timer 3 interrupt Figure 2 3 8 shows the timers connection and division ratios Figures 2 3 9 show a setting of related registers and Figure 2 3 10 shows a control procedure Pre divider Note 2 Timer 1 Timer3 Timer 3 f XIN 8 MHz 50 interrupt request 1 second The clock is divided by 40 by software Note 1 The internal system clock 6 is divided f XIN by 2 or by 8 The division ratio is decided by the Internal system clock selection bit bit 6 of the CPU mode register address 000016 Note 2 The division ratio is decided by the Pre divider division ratio bits bit 6 and bit 7 of the Timer 123 mode register address 001916 Fig 2 3 8 Timers connection and division ratios Clock function 7630 Group User s Manual 2 23 APPLICATION 2 3 Timers CPU mode register Address 000016 bO Internal system clock selection bit 4 f XIN divided by 2 high speed mode Timer 123 mode register Address 001916 b7 bO T123M lof Timer 3 count source selection bit Output signal from Timer 1 Pre divider division ratio bits 9 divided by 8 Timer 1 Address 001616 b7 bO T1 249 Set division ratio 1 Timer 1 Address 001816 b7 b0 Set division ratio 1 Interrupt request register B Address 000316 b7 bO IREQB DULL Timer 3 interrupt request bit becomes 1
28. Connect an approximately 1000 pF capacitor across Microcomputer the Vss pin and the analog input pin Besides connect the capacitor to the Vss pin as close as possible Also connect the capacitor across the Thermistor analog input pin and the Vss pin at equal length Note The resistor is used for dividing resistance with a thermistor Fig 3 4 5 Analog signal line and a resistor and a capacitor 3 18 7630 Group User s Manual 3 4 Reason APPENDIX 3 4 Countermeasures against noise Signals which is input in an analog input pin such as an A D converter comparator input pin are usually output signals from sensor The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer the wiring to an analog input pin is longer necessarily This long wiring functions as an antenna which feeds noise into the microcomputer which causes noise to an analog input pin If a capacitor between an analog input pin and the Vss pin is grounded at a position far away from the Vss pin noise on the GND line may enter a microcomputer through the capacitor 4 Consideration for oscillator Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals 1 Keeping oscillator away from large current 2 signal lines Install a microcomputer and especially an oscillator as far as possible from signal lines where a curr
29. Fig 2 5 19 Timing chart Communication using UARTT sss 2 79 vi 7630 GROUP USER S MANUAL Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig List of figures 2 5 20 Setting of related registers on transmitting side Communication using UARTI 2 81 2 5 21 Setting of related registers on receiving side Communication using UARTI 2 82 2 5 22 Control procedure on transmitting side Communication using UART 2 83 2 5 23 Control procedure on receiving side Communication using UART I 2 84 2 5 24 Connection diagram Communication using UARTI 2 85 2 5 25 Timing chart Communication using UART cnes 2 85 2 5 26 Setting of related registers on transmitting side Communication using UART 2 86 2 5 27 Setting of related registers on receiving side Communication using UART 2 87 2 5 28 Control procedure on transmitting side Communication using UAHT 2 88 2 5 29 Control procedure on receiving side Communication using UARTI 2 89 2 6 1 Memory map of A D conversion related registers 2 90 2 6 2 Structure of A D conversion register c ene 2 91 2 6 3 Structure of A D control register 2 91 2 6 4 Connection diagram Measurement of analog signals 2 92 2 6 5 Se
30. Inputs sx adore one a O A cdm hg 1 PIN CONFIGURATION TOP VIEW 32 P 1 P1 POJAN P20 Sin PO AN P2 Sour lt gt PO ANo P22 ScLk lt VREF P2 Saoy M37630M4T XXXFP Kd is M37630E4T XXXFP Voo P2 URxD Xour P2 UTxD lt Xn P2 Urts Vss P2 Ucts lt RESET P3 P4 KW 1 P3 CTX gt P3 CRX lt gt 2 Package type 44P6N A 44 pin plastic molded QFP Fig 1 Pin configuration of M37630M4T XXXFP 1 2 7630 Group User s Manual jenue N sasn dnoJ5 0 9 weibeip yooq jeuonoung z Biy M37630MXT XXXFP FUNCTIONAL BLOCK DIAGRAM PACKAGE 44P6N A Clock Clock output input Xour Xin Reset Vss AVss tl Clock generating circuit 8 a Y Y uM Timer X 16 Timer 1 8 Timer Y 16 Timer 2 8 Timer 3 8 n Serial I O y 4 y b P1 7 I O port P4 I O port P3
31. Mask ROM number Date SINGLE CHIP MICROCOMPUTER M37630M4T XXXFP a signature signature MITSUBISHI ELECTRIC Company name lt Customer Note Please fill in all items marked amp Submitted by Supervisor Date issued X 1 Confirmation Specify the type of EPROMs submitted Three EPROMs are required for each pattern Issuance signature If at least two of the three sets of EPROMs submitted contain identical data we will produce masks based on this data We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data Thus extreme care must be taken to verify the data in the submitted EPROMs Checksum code for entire EPROM 11 hexadecimal notation EPROM type indicate the type used 27512 EPROM address 000016 Product name ASCII code 000F16 M37630M4T 001016 CO7F16 C08016 data ROM 16K 132 bytes FFFF16 FFFB16 1 Set the data in the unused area the shaded area of the diagram to FF16 2 The ASCII codes of the product name M37630M4T must be entered in addresses 000016 to 000F16 And set the data FF16 in addresses 000A16 to OOOF 16 The ASCII codes and addresses are listed to the right in hexadecimal notation In the address space of the microcomputer the internal ROM area is from address C08016 to FFFB16 The reset vector is stored in addresses
32. P4o KWo t P41 KW1 M L4 P42 KW2 lt gt P43 KW3 lt gt L16 P44 KWa at LZ P45 KW5 gt Package type 80D0 Fig 2 11 1 Pin configuration of 7630 group s built in PROM 2 102 7630 Group User s Manual P4e KWe at L9 reserved reserved NC NC NC versions NC No Connection APPLICATION 2 11 Built in PROM version 2 11 3 Programming adapter To write or read data into from the internal PROM use the dedicated programming adapter and general purpose PROM programmer as shown in Table 2 11 2 Table 2 11 2 Programming adapter Programming adapter M37630E4FS PCA7431 M37630E4FP one time blank PCA7430 1 Write and read In PROM mode operation is the same as that of the M5M27C101 but programming conditions of PROM programmer are not set automatically because there are no internal device ID codes Accurately set the following conditions for data write read Take care not to apply 21 V to VPP pin or the product may be permanently damaged O Programming voltage 12 5 V O Setting of programming adapter switch Refer to Table 2 11 3 O Setting of PROM programmer address Refer to Table 2 11 4 Table 2 11 3 Setting of programming adapter switch PCA7431 PCA7430 CMOS CMOS Table 2 11 4 Setting of PROM programmer address PROM programmer start address PROM programmer completion address ERE Address C08016 Address FFFB16 M37630E4FP 2 Erasing Contents of t
33. Receive initialization End of communication q The Receive enable bit is cleared to 0 UCON Address 002216 bit 3 1 The Receive buffer full flag is set to 1 The Receive parity error flag is cleared to 0 Ax The Receive framing error flag is cleared to 0 The Receive overrun flag is cleared to 0 The Receive error sum flag is cleared to 0 E Fig 2 5 29 Control procedure on receiving side Communication using UART 7630 Group User s Manual 2 89 APPLICATION 2 6 A D converter 2 6 A D converter 2 6 1 Memory map of A D conversion 001416 A D conversion register AD 001516 A D control register ADCON Fig 2 6 1 Memory map of A D conversion related registers 2 90 7630 Group User s Manual APPLICATION 2 6 A D converter 2 6 2 Related registers A D conversion register b7 b6 b5 b4 b3 b2 bi bO ee Lar A D conversion register AD Address 001416 et Fumction ES O The read only register where A D conversion results are stored o x EXE folx olx olx folx EME folx Fig 2 6 2 Structure of A D conversion register A D control register b7 b6 b5 b4 b3 b2 bi bO Eu 11111 A D control register ADCON Address 001516 WwW POo ANo PO1 AN1 PO2 AN2 PO3 AN3 Ten EISE POS AN5 POe AN6 PO7 AN7 A D conversion completion bit 0 Conversion in progress 1 Conversion comp
34. SIOCON Address 001316 fe Name Function troset WI divided by 4 6 divided by 8 o divided by 16 6 divided by 32 6 divided by 64 o divided by 128 6 divided by 256 o divided by 512 P20 Sin P21 Sour and P22 ScLk 1 0 port P20 P21 P22 function selection bit SIN SOUT ScLk output pin P23 Srpy function selection bit I O port P23 E SRDY output pin 5 Transmission order selection bit T LSB first MSB first Synchronization clock selection bit d External clock Internal clock d Not used 0 when read EE Fig 3 5 11 Structure of Serial I O control register Clock divider selection bits 2200008 2200 A002Z 2000 08 A D conversion register b7 b6 b5 b4 b3 b2 bi bO ITITI A D conversion register AD Address 001416 Fig 3 5 12 Structure of A D conversion register 7630 Group User s Manual 3 27 APPENDIX 3 5 List of registers A D control register b7 b6 b5 b4 b3 b2 bi bO A D control register ADCON Address 001516 POo ANo PO1 AN1 PO2 AN2 PO3 AN3 PO4 AN4 POS AN5 POs AN6 PO7 AN7 3 A D conversion completion bit Conversion in progress Conversion completed Note 5 Not used 0 when read don t write 1 Note Don t set this bit to 1 during A D conversion Fig 3 5 13 Structure of A D control register Timer 1 Timer 3 b7 b6 b5
35. The Receive enable bit is cleared to 0 The Receive buffer full flag is set to 1 The Receive parity error flag is cleared to 0 The Receive framing error flag is cleared to 0 The Receive overrun flag is cleared to 0 The Receive error sum flag is cleared to 0 Receive enable Start of communication Output L from Unrs Check the completion of receiving with the Receive buffer full flag Read the first byte of received data The receive buffer full flag is cleared to 0 by reading data Check the Receive error sum flag Check the completion of receiving with the Receive buffer full flag Read the second byte of received data The receive buffer full flag is cleared to 0 by reading data Check the Receive error sum flag g for error Processin UCON Address 002216 bit 3 lt 1 Ax Receive initialization End of communication The Receive enable bit is cleared to 0 The Receive buffer full flag is set to 1 The Receive parity error flag is cleared to 0 The Receive framing error flag is cleared to 0 The Receive overrun flag is cleared to 0 The Receive error sum flag is cleared to 0 Fig 2 5 23 Control procedure on receiving side Communication using UART 2 84 7630 Group User s Manual APPLICATION 2 5 Serial I O 3 Communication transmit receive using asynchronous serial I
36. UART 1 Point 1 word data is transmitted and received through asynchronous serial I O Figure 2 5 18 shows a connection diagram and Figure 2 5 19 shows a timing chart Transmitting side Receiving side Ucrs URTS TxD RxD 7630 group 7630 group Fig 2 5 18 Connection diagram Communication using UART Specifications The Serial I O is used UART is selected Transfer bit rate 9600 bps f XIN 10 0 MHz is divided by 1024 Communication control using port URTS and UCTS Set to 1 Receiving side Receive enable bit URTS gt Ucrs Transmitting side Set to 1 Transmitting side Transmit enable bit Transmission buffer empty flag Receiving side oe 1ST 8DATA 2SP A Write transmit data to the UART transmit buffer register 1 Fig 2 5 19 Timing chart Communication using UART 7630 Group User s Manual 2 79 APPLICATION 2 5 Serial I O Table 2 5 1 shows setting examples of UART baud rate generator UBRG values and transfer bit rate values Figure 2 5 20 shows a setting of related registers on the transmitting side and Figure 2 5 21 shows a setting of related registers on the receiving side Table 2 5 1 Setting examples of Baud rate generator values and transfer bit rate values ato 10MHz 2 Transfer bit rate BRG count source at 8MHz 2 bps Note 1 Note 2 BRG setting value Actual time bps 12 0C16 75 12 BRG setting
37. UART control register b7 b6 b5 b4 b3 b2 bi bO 00 UART control register UCON Address 002216 Name Function Jatrsellr w ou enable bit e Transmit disabled Transmit enabled 1 Receive enable bit 0 Receive disabled 1 Receive enabled Transmission initialization bit 0 No action 1 Initialize the transmit enable bit and transmit status register flags Stop transmission Receive initialization bit 0 No action 1 Initialize the receive enable bit and receive status register flags Not used 0 when read don t write 1 Fig 3 5 22 Structure of UART control register 3 32 7630 Group User s Manual APPENDIX 3 5 List of registers UART status register b7 b6 b5 b4 b3 b2 bi bO BILLI UART status register USTS Address 002316 O ia C register empty flag n Register full Register empty 1 Transmission buffer empty flag 0 Buffer full 1 Buffer empty o Receive buffer full flag 0 Buffer full 1 x 1 Buffer empty 3 Receive parity error flag 0 No parity error detected x 1 Parity error detected 4 Receive framing error flag 0 No framing error detected x 1 Framing error detected 5 Receive overrun flag a No overrun detected x Overrun detected Receive error sum flag Pa No error detected Error detected 7 Not used 0 when read ce Fig 3 5 23 Structure of UART status register UART transmit buffer register 1 UART transmit buffer reg
38. at the same time Timer X mode bits Pulse width measurement mode CNTRo polarity selection bit Measure the H period Timer X stop control bit Stop counting Clear this bit to 0 to start counting Timer Y mode register Address 001F 16 b7 bO 1 w EE a E Timer X count source selection bits divided by 16 Timer XL Address 001A16 b7 bO TXL FF16 Set to FFFF16 before counting a pulse After being started the timer decrements Timer XH Address oor with each input pulse TXH FF16 J Interrupt control register B Address 000616 b7 bO ene e ee Timer X interrupt enable bit Interrupt enabled CNTRo interrupt enable bit Interrupt enabled Interrupt request register B Address 000316 b7 bO meae o EE E Timer X interrupt request bit This bit is set to 1 at underflow of Timer X CNTRo interrupt request bit This bit is set to 1 at the falling edge of the input signal of CNTRo pin Port P1 direction register Address 000B16 b7 bO P1D P14 Input mode Fig 2 3 16 Setting of related registers Measurement of pulse width 7630 Group User s Manual 2 31 APPLICATION 2 3 Timers Control procedure Figure 2 3 17 and Figure 2 3 18 show a control procedure X These bits are not used in this application Please set these bits to 0 or 1 appropriately Initialization SEI All interrupts Disabled CPUM Addr
39. every 25 ms Interrupt control register B Address 000616 b7 bO ss AMEN Timer 3 interrupt enable bit Interrupt enabled Fig 2 3 9 Setting of related registers Clock function 2 24 7630 Group User s Manual APPLICATION 2 3 Timers Control procedure Figure 2 3 10 shows a control procedure RESET X These bits are not used in this application Please set these bits to O or 1 appropriately Initialization SEI All interrupts Disabled CPUM Address 000016 lt 00000X002 f XiN divided by 2 high speed mode T123M Address 001916 0100XXXX2 Select each count source of the Timer 1 and Timer 3 ICONB Address 000616 bit 5 1 Ti Address 001616 lt 250 1 T3 Address 001816 lt 50 1 Set division ratio 1 to the Timer 1 and Timer 3 CLI Interrupts Enabled Main processing Processing for completion of setting clock Note 1 T1 Address 001616 lt 250 1 When restarting the clock from zero second T3 Address 001816 lt 50 1 after completing to set the clock reset timers 0 IREQB Address 000316 bit 5 Set the Timer 3 interrupt request bit to 0 Note 1 This processing is performed only at completing to set the clock Timer 3 interrupt processing routine CLT Note 2 Note 2 When using the Index X mode flag T CLD Note 3 Note 3 When using the Decimal mode fl
40. falling edge active For interrupt request rising edge active For pulse period measurement mode refer to rising edge Timer Y stop control bit Timer counting Timer stopped Note The internal system clock 9 is divided f XIN by 2 or by 8 The division ratio is decided by the Internal system clock selection bit bit 6 of the CPU mode register address 000016 Fig 3 5 19 Structure of Timer Y mode register UART mode register b7 b6 b5 b4 b3 b2 bi bO ITITI M UART mode register UMOD Address 002016 e Name Fuin farsa Not used 0 when read don t write 1 Clock divider selection bits b2 b divided by 1 divided by 8 0 divided by 32 Ge n ER EUH 01 10 1 1 0 divided by 256 3 Stop bits selection bit 0 One stop bit 1 Two stop bits 4 Parity selection bit 0 Even parity 1 Odd parity 5 Parity enable bit 0 Parity checking disabled 1 Parity checking enabled UART word length selection bits Fig 3 5 20 Structure of UART mode register 7630 Group User s Manual b7 b6 00 7 bits 01 8 bits 10 9 bits 11 Not used 3 31 APPENDIX 3 5 List of registers UART baud rate generator b7 b6 b5 b4 b3 b2 bi bO TITT UART baud rate generator UBRG Address 002116 a Function ES o A count value of baud rate generator is set Jojo Jefo Jefo Jelo ae Bae E Tels Jes Fig 3 5 21 Structure of UART baud rate generator
41. the module will execute the actions 2 and 3 The frame reception can be observed from CPU side either by polling of IREQA 4 or CREC O or by CSR interrupt service After having processed the buffer contents the receive buffer control bit should be cleared by the CPU in order to give control of the buffer back to the module This kind of handshaking enables the module to use the buffer to store the next frame to be received consequently data read from the receive buffer address range is undefined until the next frame reception Note If the reception function is implemented based on CSR interrupt service reconfirm the CREC O status after clearing it If both buffers are already occupied before entering the CSR interrupt service routine both buffers must be processed in one CSR interrupt service However it is recommended to optimize the timing of the interrupt system for minimum latency and short execution time to avoid the possibility of CAN overrun situations see section 4 If the requirements to avoid overrun situations are fullfilled one CSR interrupt service has to deal with one single frame only because each frame reception triggers one CSR interrupt service request Figure 2 4 33 shows the receive process flowcharts from CAN module and CPU side Section 3 discusses the timing details on the module s receive processing 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module CAN module Receive proc
42. 0 3 to 7 0 Input voltage P0 P0 P1 P1 P2 P2 P39 P3 0 3 to Voc 0 3 P4 P4 RESET Xn All voltages with respect to Vss and output transistors are off Output voltage POo P07 P1 P1 P2 gt P2 P35 P34 0 3 to Vec 0 3 P4o P47 Xour Power dissipation Ta 25 C 500 Operating temperature 40 to 85 Storage temperature 60 to 150 Table 10 RECOMMENDED OPERATING CONDITIONS Voc 4 0 to 5 5 V Vss AVss 0 V T 40 to 85 C unless otherwise noted Parameter Power source voltage H Input voltage PO o P07 P1 P17 P25 P27 P30 P34 P49 P4 RESET Xin Input voltage P0 P0 P1 P1 P2 P2 P3 P3 P4 P4 RESET Xin low peak sum peak output current P0 P0 P1 P1 P2 P2 P3 P3 P4 P4 Y lon avg sum average output current lo peak sum peak output current Y lo avg sum average output current lon peak peak output current lou avg average output current peak output current lo peak lo avg L average output current input current at overvoltage condi tion Vi gt Voc P1 P1 P2 P2 P3 P34 P4 P4 total input current at overvoltage condition Vi gt Voc P3 P34 PAgS P4 Timer inp
43. 1 004716 CTB8 Data byte 2 004816 CTB9 Data byte 3 004916 CTBA Data byte 4 004A16 CTBB Data byte 5 004B 6 CTBC Data byte 6 004Ci g CTBD Data byte 7 004Di Fig 2 4 36 Transmit buffer organization 3 Altogether the following items of the transmit buffer need to be initialized IDE bit CBT1 0 this bit represents the identifier extension IDE bit of a frame RTR SRR bit CBT1 1 for standard format frames this bit represents the remote transmission request RTR bit of the arbitration field for extended format frames it represents the substitute remote request SRR bit of the arbitration field RTR bit CBT4 1 this bit represents the remote transmission request RTR bit of the arbitration field of an extended format frame not relevant for standard format frames Reserved bit r0 CBT5 4 this bit represents the reserved bit rO of the control field of a standard or extended format frame should be set to 0 sent dominant refer to the CAN specification Reserved bit ri CBT4 0 this bit represents the reserved bit rO of the control field of an extended format frame not relevant for standard format frames should be set to 0 sent dominant refer to the CAN speci fication Identifier bits of CBTO to CBT4 these bits represent the identifier of the arbitration field of a frame CBT2 to CBT4 hold the extended identifier bits and are not relevant for standard format frames DLC bits of CBT5 these bits represent the data le
44. 1 43 TASTE RERO rere ener ee 1 44 rai A IA A tada 1 45 A A 1 46 1 47 ni aaa 1 48 1 49 1 50 21O DOE e e T 2 2 2 1 1 Memory map of I O ports nr na aaa iaaa aaa iaaa a 2 2 2 1 2 Related registers Iii ein KENANA EAKATE ARREK Ya Rae Iu aa ENTIRE a E TEARRE KERAKS KKKRKES 2 3 2 1 3 Overvoltage conditions at digital input portS o ooncccnnnnocccnnnnncccnnccnnoonnnccnnnnnonncnanan ono 2 7 2 1 4 Handling examples of unused pins 2 8 22 Interrupts I M EU ol bare eat br 2 9 2 2 1 Memory map of interrupt related registers 2 9 2 2 2 Related TE cir A ci ais 2 10 2 2 3 nterrupt setting method das 2 14 2 2 4 Key on wake up Interf bt ridad de trae 2 16 23 TIMES iii ida 2 18 2 3 1 Memory map of timer eieiei enne nnne nnne nnn nnn 2 18 232 Ral pt BIS Poe iive boe CiU tcd Oed ata aaa ceases 2 19 2 3 3 Timer application examples Leocoonnonnccnonicocccnonnccnonccononnnncconnnnnonccnnnnonnccnnnn nn nncnana rr nnncnnnn nos 2 22 7630 GROUP USER S MANUAL i Table of contents 2 4 Controller Area Network CAN MOdUIel cssscsssesssssessessesesseeeeeesseseesteasenesnssseneeatees 2 34 P NE TRISTE en eT OE 2 34 24 SERE function register MAP Laos 0070700 mp dm 2 35 OF E Rola ad ea EUR 2 87 2 4 4 Operational MOCES ccccccccccsccsscsseccseeseccseessecseesecseecsecsseeseccsecseccsseesscsa
45. 2 3 Power source current standard characteristics in high speed mode Measuring condition 25 C Vcc VREF 5 V in middle speed mode 14 CAN runs all peripherials run CAN stops all peripherials run 4 6 8 10 Power source current Icc mA Clock input oscillation frequency f XIN MHz Fig 3 2 4 Power source current standard characteristics in middle speed mode 7630 Group User s Manual 3 9 APPENDIX 3 2 Standard characteristics 3 2 2 Output current standard characteristics Figures 3 2 5 and Figure 3 2 6 show the output current standard characteristics Port P20 loH VoH characteristic P channel drive Pins with same characteristic PO P12 P17 P2 P30 P34 P4 Vcc 5 0V Ta 25 C Vcc 4 0V Ta 25 C lt x E E 9 2 c 0 Lum LL o 3 o 3 o 2 0 3 0 4 0 H output voltage VoH V Fig 3 2 5 Output current standard characteristics P channel Port P20 loL VOL characteristic N channel drive Pins with same characteristic PO P12 P17 P2 P30 P34 P4 40 35 30 25 Vcc 5 0V Ta 25 C Vcc 4 0V Ta 25 C L output current loL mA 2 0 3 0 4 0 L output voltage VoL V Fig 3 2 6 Output current standard characteristics N channel 3 10 7630 Group User s Manual APPENDIX 3 2 Standard characteristics 3 2 3 Input current standard characteristics Figure 3 2 7 and Figure 3 2 8 s
46. 2 5 1 Memory map of serial I O 001216 Serial I O shift register SIO 001316 Serial I O control register SIOCON 002016 UART mode register UMOD 002116 UART baud rate generator UBRG 002216 UART control register UCON Fig 2 5 1 Memory map of serial I O related registers 7630 Group User s Manual 2 67 APPLICATION 2 5 Serial I O 2 5 2 Related registers Serial I O shift register b7 b6 b5 b4 b3 b2 bi bO ITT Serial 1 O shift register SIO Address 001216 A shift register for serial transmission and reception At transmitting Set transmission data At receiving Store received data Note A content of the Transmit buffer register cannot be read out A data cannot be written to the Receive buffer register Fig 2 5 2 Structure of Serial I O shift register Serial I O control register b7 b6 b5 b4 b3 b2 bi bO Mittitt Serial I O control register SIOCON Address 001316 o divided by 4 6 divided by 8 6 divided by 16 6 divided by 32 6 divided by 64 6 divided by 128 6 divided by 256 divided by 512 P20 Sin P21 Sour and P22 ScLk 1 0 port P20 P21 P22 function selection bit SIN Sour ScLk output pin P23 Snpv function selection bit 1 0 port P23 SRDY output pin Transmission order selection bit LSB first MSB first Synchronization clock selection bit External clock Internal clock 7 Not used 0 when read
47. 4 VREF P23 SRDY1 aaa M37630M4T XXXFP PE Vss f GG Po4 Unxp ER M37630E4T XXXFP E P2s Urxp gt lt XIN P2e Unrs gt 42 Vss P27 Ucts O RESET P30 gt 12 4 gt p47 KW7 lt o n e 8 gt lt x e e Orn o s O do BESSSSSSESS al Sow 5 Y 55 a m ZAA Package type 44P6N A 7630 Group User s Manual 3 65 MITSUBISHI SEMICONDUCTORS USER S MANUAL 7630 Group JAN Second Edition 1999 Editioned by Committee of editing of Mitsubishi Semiconductor USER S MANUAL Published by Mitsubishi Electric Corp Semiconductor Marketing Division This book or parts thereof may not be reproduced in any form without permission of Mitsubishi Electric Corporation 1999 MITSUBISHI ELECTRIC CORPORATION 7630 Group User s Manual ENESAS Renesas Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan
48. 50 7630 Group User s Manual APPENDIX 3 7 Mark specification form 3 7 Mark specification form 44P6N 44 PIN QFP MARK SPECIFICATION FORM Please choose one of the marking types below A B C and enter the Mitsubishi IC catalog name and the special mark if needed A Standard Mitsubishi Mark 63 G9 Mitsubishi lot number Mitsubishi IC catalog name 6 digit or 7 digit I B Customer s Parts Number Mitsubishi IC Catalog Name G9 es E Customer s Parts Number Note The fonts and size of characters are standard Mitsubishi type d Mitsubishi IC catalog name and Mitsubishi lot number Note 4 If the Mitsubishi logo is not required check the box below Mitsubishi logo is not required KD Notes 1 The mark field should be written right aligned 2 The fonts and size of characters are standard Mitsubishi type 3 Customer s parts number can be up to 7 characters Only 0 to 9 Ato Z amp O period and Comma are usable Epa Ra uired Notes1 If the special mark is to be printed indicate the desired 63 23 layout of the mark in the left figure The layout will be duplicated as close as possible Mitsubishi lot number 6 digit or 7 digit and Mask ROM number 3 digit are always marked 2 If the customer s trade mark logo must be used in the special mark check the box below Please submit
49. 7630 Group User s Manual 1 41 HARDWARE RESET CIRCUIT Register Address Register contents Register Address Register contents CPU mode reg 000046 4846 Timer XH 001Bi FFig Interrupt request reg A 000246 0046 Timer YL 001Cig FFig Interrupt request reg B 000346 0046 Timer YH 001Dig FFig Interrupt request reg C 0004 56 00 6 Timer X mode reg 001E 0046 Interrupt control reg A 000546 0046 Timer Y mode reg 001F 6 0016 Interrupt control reg B 000616 0046 UART mode reg 002046 0016 Interrupt control reg C 000746 0046 UART control reg 002246 0016 Port PO reg 000846 0016 UART status reg 002346 0749 Port PO direction reg 000946 0046 Port PO pull up control reg 002846 0046 Port P1 reg 000A 6 0046 Port P1 pull up control reg 002946 0016 Port P1 direction reg 000B 6 0016 Port P2 pull up control reg 002A 6 0016 Port P2 reg 000Ci 0046 Port P3 pull up control reg 002B 0046 Port P2 direction reg 000D 6 0046 Port P4 pull up down control reg 002Cig 0016 Port P3 reg 000E 6 0016 Interrupt polarity selection reg 002Dig 0016 Port P3 direction reg 000F 6 0046 Watchdog timer reg 002E 6 3Fie Port P4 reg 001046 0016 Polarity control reg 002F ig 0046 Port P4 direction reg 001146 0016 CAN transmit control reg 003016 0246 Serial I O control reg 00134 0046 CAN bus timing control reg 1 003116 0016 A D control reg 001546 0846 CAN bus timing control reg 2 003246 0016 Timer 1 001646 FFig CAN receive control reg
50. 8 Port P1 pull up control register 005946 CAN receive buffer register 9 Port P2 pull up control register 005A 6 CAN receive buffer register A Port P3 pull up control register 005B 6 CAN receive buffer register B Port P4 pull up down control register 005C s CAN receive buffer register C Interrupt polarity selection register 005D g CAN receive buffer register D Watchdog timer register 005E Reserved Polarity control register 005F16 Reserved Fig 9 Memory map of special register SFR 1 12 7630 Group User s Manual HARDWARE I O PORTS l O PORTS The 7630 group has 35 programmable l O pins and one input pin arranged in five I O ports ports PO to P4 The I O ports are con trolled by the corresponding port registers and port direction regis ters each I O pin can be controlled separately When data is read from a port configured as an output port the port latch s contents are read instead of the port level A port configured as an input port becomes floating and its level can be read Data writ ten to this port will affect the port latch only the port remains floating Refer to Structure of port and port direction registe
51. CAN transmit pin Configure Port P3 CTX as CAN transmit output pin by setting the port double function control bit CTRM 2 Fig ure 2 4 3 before starting the communication functions of the module Example Figure 2 4 28 shows an example of the initialization sequence required At first the module is switched to configuration mode for details refer to section 2 4 4 to enable altering the special function registers After that the related SFRs are initialized with the corresponding parameters see below Finally the module is switched to normal run mode to enable the communication and to protect the critical SFRs from being altered accidentally The following table shows the conditions being used below Item Setting Description Acceptance filtering Filtering disabled accept all identifiers Tots 1 Tpbs1 4 These settings result in 10 time quanta per bit the corre sponding baudrate is 500kbps at f XIN 10MHz equiva Tobs2 4 lent to f 5MHz Prescaler division ratio 1 Resynchronisation jump width 4 Sampling single Dominant polarity low Auto receive disabled CAN interrupts not defined here should be initialized These conditions result in CAN bus timing control register values of CBTCON1 00 and CBTCON2 DB yg 7630 Group User s Manual 2 51 APPLICATION 2 4 Controller Area Network CAN module C Start of module initialization jj enter config mode 1 seb 1 CTRM
52. CBTCON2 Address 003246 B Name Function At reset 0 b2b1b0 0 000 One time quantum Phase buffer segment 1 001 Two time quanta duration control bits 110 Seven time quanta 111 Eight time quanta b5b4b3 000 One time quantum Phase buffer segment 2 001 Two time quanta duration control bits 110 Seven time quanta 111 Eight time quanta b7b6 00 One time quantum 01 Two time quanta 10 Three time quanta 11 Four time quanta Synchronization jump width control bits Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 2 4 5 Structure of CAN bus timing control register 2 CBTCON2 CAN acceptance code register 0 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance code register 0 CACO Address 003346 B Name Function At reset O Standard identifier bit 6 2 Standard identifier bit 7 These bits except when masked by the acceptance mask register 0 Figure 2 4 11 form the acceptance filtering condition for incoming CAN frames p They must be initialized with the identifier Standard identifier bit 9 pattern of CAN frames to be received Standard identifier bit 8 Standard identifier bit 10 Not used Undefined at read
53. CTB8 CRB8 Data byte 2 000846 CTB9 CRB9 Data byte 3 000946 CTBA CRBA Data byte 4 000Aig CTBB CRBB Data byte 5 000Bi CTBC CRBC Data byte 6 000C 1 CTBD CRBD Data byte 7 000D46 Calculate the actual address as follows TxD buffer address 004046 offset RxD buffer address 005046 offset Not used write to 0 Fig 40 Structure of CAN transmission and reception buffer registers Note 1 All CAN related SFRs must not be written in CAN sleep mode 7630 Group User s Manual 1 37 HARDWARE A D CONVERTER A D CONVERTER The A D converter uses the successive approximation method with 8 bit resolution The functional blocks of the A D converter are described below Refer to Block diagram of A D converter Comparison Voltage Generator The comparison voltage generator divides the voltage between AVss and Vrer by 256 and outputs the divided voltage Channel Selector The channel selector selects one of ports POy AN to P07 AN7 and inputs its voltage to the comparator A D conversion register AD The A D conversion register is a read only register that stores the result of an A D conversion This register must not be read during an A D conversion Data bus b7 bO A D control register PO ANo Comparator 8 o Do o o 3 z i I o A D control circuit A D conversion register comparison voltage generator Vner Input switch bit Fig 41 Block diagram of A D
54. FFFA16 and FFFB16 Address Address 000016 M 4D16 000816 T 5416 000116 3 3316 000916 2D16 000216 7 3716 000A16 FF16 000316 6 3616 000B16 FF16 000416 3 3316 000C16 FF16 000516 0 3016 000D16 FF16 000616 M 4D16 000E16 FF16 000716 4 3416 OOOF 16 FF16 1 2 7630 Group User s Manual 3 49 APPENDIX 3 6 Mask ROM ordering method GZZ SH52 70B lt 84A0 gt Mask ROM number P 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37630M4T XXXFP MITSUBISHI ELECTRIC We recommend the use of the following pseudo command to set the start address of the assembler source program EPROM type 27512 A 0000 The pseudo command BYTE A M37630M4T Note If the name of the product written to the EPROMs does not match the name of the mask confirmation form the ROM will not be processed 2 Mark specification Mark specification must be submitted using the correct form for the package being ordered Fill out the appropriate mark specification form 44P6N and attach it to the mask ROM confirmation form 3 Usage conditions Please answer the following questions about usage for use in our product inspection 1 How will you use the XIN XOUT oscillator Ceramic resonator Quartz crystal External clock input Other At what frequency f XIN E 3 MHz 4 Comments 2 2 3
55. Fig 2 5 3 Structure of Serial I O control register 2 68 7630 Group User s Manual WwW Jelo MEE MEE jeje KNEE EE ale E Tels Lele Ww APPLICATION 2 5 Serial I O UART mode register b7 b6 b5 b4 b3 b2 bi bO IT E UART mode register UMOD Address 002016 je Name Fuin fatese m w Not used 0 when read don t write 1 e fox p z TET Clock divider selection bits 0 0 divided by 1 EXE 0 1 0 divided by 8 10 6 divided by 32 1 1 0 divided by 256 Stop bits selection bit 0 One stop bit 1 Two stop bits 4 Parity selection bit 0 Even parity 1 Odd parity 5 Parity enable bit 0 Parity checking disabled 1 Parity checking enabled b7 b6 UART word length selection bits 0 0 7 bits 01 8 bits 10 9 bits 1 1 Not used Fig 2 5 4 Structure of UART mode register UART baud rate generator b7 b6 b5 b4 b3 b2 bi bO TTT TTT UART baud rate generator UBRG Address 002116 Fig 2 5 5 Structure of UART baud rate generator 7630 Group User s Manual 2 69 APPLICATION 2 5 Serial I O UART control register b7 b6 b5 b4 b3 b2 bi bO E 07 UART control register UCON Address 002216 Name Function At reset R w ef enable bit sE Transmit disabled Transmit enabled 1 Receive enable bit 0 Receive disabled 1 Receive enabled Transmission initialization bit 0 No action 1 Initialize the transmit enab
56. Figure 2 8 1 shows an example of power on reset circuit gt Power source 5 Output M51953AL 4 Delay capacity GND Vss 7630 group Fig 2 8 1 Example of Power on reset circuit Figure 2 8 2 shows system example which switch the microcomputer to the RAM backup mode by detecting a drop of the system power source voltage with the INT interrupt System power source voltage 5V Vcc1 M51953AL RESET 2 Vcc2 7630 group Fig 2 8 2 RAM back up system 2 96 7630 Group User s Manual APPLICATION 2 9 Oscillation circuit 2 9 Oscillation Circuit 2 9 1 Memory map of oscillation circuit related registers 000016 CPU mode register CPUM 002E16 Watchdog timer register WDT Fig 2 9 1 Memory map of oscillation circuit related registers 7630 Group User s Manual 2 97 APPLICATION 2 9 Oscillation circuit 2 9 2 Related registers CPU mode register b7 b6 b5 b4 b3 b2 bi bO A Ad CPU mode register CPUM Address 000016 Single chip mode Not available Not available Not available Stack page selection bit In page 0 1 In page 1 0 tolx Ed prem clock selection bit 2 high speed mode 8 middle speed mode g Not used 0 when read don t write 1 ac Fig 2 9 2 Structure of CPU mode register Watchdog timer register Note 1 b7 b6 b5 b4 b3 b2 bi bO TM Watchdog timer register WDT Address 002E16 St
57. O UART 2 Point 9 bit data is transmitted and received through asynchronous serial I O Figure 2 5 24 shows a connection diagram and Figure 2 5 25 shows a timing chart Transmitting side Receiving side 7630 group 7630 group Fig 2 5 24 Connection diagram Communication using UART Specifications The Serial I O is used UART is selected Transfer bit rate 9600 bps f XIN 10 0 MHz is divided by 1024 Communication control using port URTS and UCTS Set to 1 Initialize to 0 Receiving side Receive enable bit URTS gt Ucrs Transmitting side Set to 1 e Transmitting side Y Transmit enable bit Transmission register empty flag TxD RxD Receiving side ae 1ST 9DATA 2SP A 9 bits data written to the UART transmit buffer registers is transferred to the Transfer shift register Fig 2 5 25 Timing chart Communication using UART 7630 Group User s Manual 2 85 APPLICATION 2 5 Serial I O Figure 2 5 26 shows a Setting of related registers at a transmitting side and Figure 2 5 27 shows a setting of related registers at a receiving side Transmitting side CPU mode register Address 000016 bO CPUM T EBEN Internal system clock selection bit y f XIN divided by 2 high speed mode UART mode register Address 002016 b7 b0 umoD Jofo 1jo 1 Clock divider selection bits divided by 8 Stop bits selection bit Two
58. P20 P27 P30 P34 P40 P47 Y lOH avg H sum average output current Y lOL peak L sum peak output current Y l0L avg L sum average output current lOH peak H peak output current loH avg H average output current lOL peak L peak output current lOL avg L average output current lio Input current at overvoltage condition P11 P17 P20 P27 Vi gt Vcc P30 P34 P40 P47 Xo Total input current at overvoltage condition P11 P17 P20 P27 16 Vi VcC P30 P34 P40 P47 f CNTR Timer input frequency P14 CNTRo P15 CNTR1 f XiN 16 based on 50 duty except bi phase counter mode P13 TXo P14 CNTRo f XiN 32 bi phase counter mode Clock input oscillation frequency 10 7630 Group User s Manual 3 3 APPENDIX 3 1 Electrical characteristics 3 1 3 Electrical characteristics Table 3 1 3 Electrical characteristics Vcc 4 0V to 5 5V Vss AVss OV Ta 40 C to 85 C unless otherwise noted Limits Symbol Parameter Test conditions Min Te Max Unit VOH H output voltage POo P07 P12 P17 P20 P27 loH 5mA 0 8 Vcc V P30 P34 P40 P47 VoL L output voltage POo P07 P12 P17 P20 P27 loL 5mA 2 V P30 P34 P40 P47 VT VT Hysteresis P11 INTo P12 INT1 P13 TXo P14 CNTRo P15 CNTR1 0 5 V P20 SIN P22 SCLk P26 URTS P27 UCTS
59. P32 CRX 2 P40 KWo 5 P41 KW1 gt 6 P42 KWe 7 P43 KW3 18 P44 KWa lt t 9 P45 KWs p 10 P46 KWe t 11 Package type 44P6N A OD oo ce E E oo n o o o Em de z 2 a reserved reserved reserved reserved NC NC 4 h PO7 AN7 c P47 KW7 reserved reserved NC NC NC IE EE 2Z OQ wo ao ojo LO LO 9 lt gt POc AN6 48 lt PO5 AN5 47 a gt POA ANA 5 51 50 4 45 44 43 42 41 56 gt P12 NT1 5 a P11 INTo 60 63 82 P17 4 P20 SIN1 P21 Sour1 lt 67 P22 SCLK1 P23 SRDY1 t 69 reserved reserved Vss reserved reserved reserved P24 URxD lt gt P25 UTXD lt gt P26 URTS P27 Ucts P30 gt O M37630E4FS 461 P03 AN3 reserved 4 P02 AN2 38 gt PO1 AN1 P00 ANo reserved reserved 4 VREF AVss Vcc gt Xour 28 XIN Vss 4 RESET reserved reserved 25 lt gt P47 KW7 13 18 15 E reserved reserved P31 CTX lt t gt P32 CRX L6 reserved reserved reserved reserved
60. P32 CRX RESET IIH H input current POo PO07 P11 P17 P20 P27 Vi Vcc 5 LA P30 P34 P40 P47 RESET IIH H input current XIN Vi VCC 4 LA IIH H input current P32 VI Vss 20 200 LA P40 P47 Pull Down On liL L input current POo PO07 P11 P17 P20 P27 Vi VSS 5 LA P30 P34 P40 P47 RESET liL L input current XIN VI VSS 4 uA liL L input current PO0 PO7 P11 P17 VI Vss P20 P27 P30 P34 Pull Up On 200 20 LA P40 P47 RESET VRAM RAM hold voltage When clock stopped 2 V lec Power source current High speed mode f XIN 8MHz Vcc 5V 11 18 mA Output transistors off CAN module running ADC running High speed mode f XIN 8MHz Vcc 5V 9 16 mA Output transistors off CAN module stopped ADC running Middle speed mode f XIN 8MHz Vcc 5V 6 11 mA Output transistors off CAN module running ADC running Middle speed mode wait mode f XIN 8MHz Vcc 5V 2 mA Output transistors off CAN module stopped ADC running Stop mode f XIN OMHz Ta 25 C 0 1 1 uA Vcc 5V Stop mode f XIN OMHz Ta 85 C 10 uA Vcc 5V 7630 Group User s Manual 3 1 4 A D converter characteristics Table 3 1 4 A D converter characteristics Vcc 4 0V to 5 5V Vss Parameter Resolution AVss OV Ta Test conditions APPENDIX 3 1 Electrical characteristics 40 C to 85 C unless otherwise n
61. Routine Flag 0 to 1 Execute RTS Execute RTI Fetch the Jump Vector I A Restore Return S Address I lt Restore Contents of Processor Status Register PS M S S S 1 IPOD MEUS Restore Return Address S S 1 PCH EM S Note 1 The condition to enable the interrupt gt Interrupt enable bit is 1 Interrupt disable flag is 0 2 When an interrupt occurs the address of the next instruction to be executed is stored in the stack area When a subroutine is called the address one before the next instruction to be executed is stored in the stack area Fig 6 Register push and pop at interrupt generation and subroutine call Table 3 Push and pop instructions of accumulator or processor status register Push instruction to stack Pop instruction from stack Accumulator PHA PLA Processor status register PHP PLP 1 8 7630 Groop User s Manual Processor status register PS The processor status register is an 8 bit register consisting of flags which indicate the status of the processor after an arithmetic opera tion Branch operations can be performed by testing the Carry C flag Zero Z flag Overflow V flag or the Negative N flag In deci mal mode the Z V N flags are not valid After reset the Interrupt disable I flag is set to 1 but all other flags are undefined Since the In
62. Transfers the contents of the stack pointer to index register X TXA Transfers the contents of index register X to the accumulator TXS Transfers the contents of index register X to the stack pointer TYA Transfers the contents of index register Y to the accumulator Stops the internal clock Notes 1 The number of cycles n is increased by 3 when T is 1 The number of cycles n is increased by 2 when T is 1 The number of cycles n is increased by 1 when T is 1 The number of cycles n is increased by 1 when branching has occurred The number of cycles n is increased by 1 when branching to the same page area has occurred The number of cycles n is increased by 2 when branching to the differrent page area has occurred The number of cycles n is increased by 1 when branching to the differrent page area has occurred The number of cycles n is 2 when the STP instruction is disabled V flag is invalid in decimal operation mode aorhwon Ono 3 62 7630 Group User s Manual Addressing mode APPENDIX 3 10 Machine instructions Processor status register ABS X ABS Y IND ZP IND IND X IND Y REL 3 JOP n JOP JOP n JOP n JOP JOP JOP D 3 9D 5 3 99 3 81 2 91 2 Contents
63. accumulator with the contents of memory specified by the zero page X address ing mode and stores the high byte of the result on the stack and the low byte in the accumula tor PC PC 1 No operation 3 58 When T 0 ACAVM When T 1 M X MX VM Logical OR s the contents of memory and ac cumulator The result is stored in the accumulator Logical OR s the contents of memory indi cated by index register X and contents of memory specified by the addressing mode The result is stored in the memory specified by index register X 7630 Group User s Manual Addressing mode APPENDIX 3 10 Machine instructions Processor status register ABS ABS X ABS Y IND ZP IND IND X IND Y REL 3 OP n OP n OP n OP JOP n JOP n OP D 3 6C 5 3 B2 2 7630 Group User s Manual 3 59 APPENDIX 3 10 Machine instructions Addressing mode Function Details A BIT A R ZP BIT ZP R n JOP n OP OP n M S TA Saves the contents of the accumulator in 48 memory at the address indicated by the stack pointer and decrements the contents of stack pointer by 1 Saves the contents of the processor status 08 register in memory at t
64. and each cyclic timer interrupt request occurs Timer mode Use Generation of cyclic interrupts Clock function measurement of 25ms gt Application example 1 Control of a main routine cycle Function 3 Count of External pulse Timer X External pulses input to the CNTR pin are selected as a timer count source Bi phase mode Use Measurement of incremental sensor output signals Function 4 Count of External pulse Timer X Timer Y External pulses input to the CNTR pin are selected as a timer count source Event counter mode Use Measurement of frequency gt Application example 2 Division of external pulses Generation of interrupts in a cycle based on an external pulse count of a reel pulse Function 5 Measurement of External pulse width Timer X Timer Y The H or L level width of external pulses input to CNTR pin is measured Pulse width measurement mode Use Measurement of external pulse frequency Measurement of pulse width of FG pulse generated by motor gt Application example 3 Measurement of external pulse duty when the frequency is fixed FG pulse Pulse used for detecting the motor speed to control the motor speed 2 22 7630 Group User s Manual APPLICATION 2 3 Timers 2 Timer application example 1 Clock function measurement of 25 ms Outline The input clock is divided by a timer so that the clock counts up every 25 ms Specifications The clock f XIN
65. b4 b3 b2 bi bO Timer 1 T1 Address 001616 Timer 3 T3 Address 001816 To get the actual Timer 1 or Timer 3 value read out the corresponding timer register Fig 3 5 14 Structure of Timer 1 Timer 3 3 28 7630 Group User s Manual The timer value is written to timer and latch at the same time Ww VREF input switch bit Off On 9 je x e foll RAEE APPENDIX 3 5 List of registers Timer 2 b7 b6 b5 b4 b3 b2 b1 bO ITITI Timer 2 T2 Address 001716 Set 0016 to FF16 as Timer 2 count value The timer value is written to Timer 2 and latch at the same time or to the latch only Note To get the actual Timer 2 value read out the Timer 2 register Note Depinding on the Timer 2 write control bit bit 2 of the Timer 123 mode register address 001916 Fig 3 5 15 Structure of Timer 2 Timer 123 mode register b7 b6 b5 b4 b3 b2 bi bO RLL Timer 123 mode register T123M Address 001916 OOo Name Funcion Atroset s polarity selection bit a Start on H level output Start on L level output 1 PWM output enable bit 0 PWM output disabled 1 PWM output enabled 2 Timer 2 write control bit P Latch and counter Latch only Timer 2 count source selection bit A Timer 1 underflow Pre divider output Timer 3 count source selection bit re Timer 1 underflow Pre divider output Not used 0 when
66. converter A D control register Structure of A D control regis ter The A D control register controls the A D conversion process Bits 0 to 2 select a specific analog input pin Bit 3 signals the completion of an A D conversion The value of this bit remains 0 during an A D gt A D interrupt request conversion and changes to 1 when an A D conversion ends Writ ing 0 to this bit starts the A D conversion Bit 4 is the Vpe Input switch bit 1 38 7630 Group User s Manual HARDWARE A D CONVERTER A D control register address 001546 ADCON Analog input pin selection bits b2 b1 bO 0 0 0 POyANo PO4 AN 0 PO AN5 1 POJANs 0 PO4J AN4 1 POJANs5 0 1 P0 ANg PO AN A D conversion completion bit 0 Conversion in progress 1 Conversion completed Veer Input switch bit 0 Off 1 On Not used 0 when read do not write 1 Fig 42 Structure of A D control register A D Converter Operation bit to 1 The result of A D conversion can be obtained from the A D conversion register AD address 001446 Note that the comparator is linked to a capacitor so set f X to 500 kHz or higher during A D conversion The comparator and control circuit reference an analog input voltage with the reference voltage then stores the result in the A D conver sion register When an A D conversion is complete the control circuit Sets the A D conversion comp
67. count less than 128 Transmit error count greater than 255 128 occurrences of 11 recessive bits Fig 2 4 39 Error state diagram 7630 Group User s Manual 2 65 APPLICATION 2 4 Controller Area Network CAN module 2 4 13 Wake up via CAN The module features a function to wake up the CPU on CAN traffic This feature is implemented by an external interrupt function on the P3 CRX input port The wake up interrupt is requested upon a recessive to dominant edge by start of frame of a message sent by another node on the P3 CRX The initialization required to use the wake up function is 1 2 3 4 5 Clear CWKU interrupt request bit IREQB O Set CWKU interrupt control bit ICONB O Put module to sleep mode by setting the sleep control bit CTRM O Figure 2 4 3 see section 2 4 4 Set the pull transistor enable bit PUP3 2 this activates the pull transistor towards the recessive level depend ing on the dominant polarity selected by PCON 1 Put MCU to low power mode wait or stop mode The first frame sent by another node awakens the CPU by an CWKU interrupt request The module should be put to normal run mode again as part of the CWKU interrupt service also the pull transistor should be disabled as part of this interrupt service routine Note The frame triggering the wake up function can not be received and is lost 2 66 7630 Group User s Manual APPLICATION 2 5 Serial I O 2 5 Serial I O
68. do not make input levels of an input port and an I O port undefined especially for I O ports of the P channel and the N channel open drain Pull up connect the port to VCC or pull down connect the port to Vss these ports through a resistor When determining a resistance value note the following External circuit Variation of output levels during the ordinary operation When using built in pull up or pull down resistor note on varied current values When setting as an input port Fix its input level When setting as an output port Prevent current from flow to the external 1 stand by state The stop mode by executing the STP instruction or the wait mode by executing the WIT instruction Reason Even when setting as an output port with its direction register in the following state e P channel when the content of the data register port latch is O N channel when the content of the data register port latch is 1 the transistor becomes the OFF state which causes the ports to be the high impedance state Note that the level becomes undefined depending on external circuits Accordingly the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input port and an I O port are undefined This may cause power source current 3 14 7630 Group User s Manual APPENDIX 3 3 Notes on use 2 Modifying output data with bit managing When th
69. external interrupts can be selected This pin will be used as Vpp pin during PROM pro gramming of One Time PROM Versions CMOS O port or external interrupt input port The active edge rising or falling of external interrupts can be selected CMOS O port or input pin used in the bi phase counter mode CMOS O port or timer X input pin used for the event counter pulse width measure ment and bi phase counter mode CMOS I O port or timer Y input pin used for the event counter pulse width and pulse period measurement mode CMOS I O port or PWM output pin used in the PWM mode of timers 2 and 3 CMOS l O port P20 Sin P21 Sour P25 Sci P23 Sapy I O port P2 P2 URyD P2 UT D P2g Unrs P2 Ucrs CMOS I O ports or clock synchronous serial I O pins CMOS O ports or asynchronous serial I O pins P3 P3 CTX l O port P3 P3 CRX P3 P3 CMOS l O port CMOS I O port or CAN transmit data pin CMOS I O port or CAN receive data pin CMOS l O port PAyKW PAJ KW 1 O port P4 CMOS I O ports These ports can be used for key on wake up when configured as inputs 1 4 7630 Group User s Manual HARDWARE PART NUMBERING PART NUMBERING Product M37630 M 4 T XXX FP u Package type FP 44P6N A package FS 80D0 package ROM number Omitted in One Time PROM version blank and EPROM version T Automotive use ROM PROM size 4
70. flag is set and the corresponding interrupt request bit is cleared Notes on use When the active edge of an external interrupt INTo INT CNTRo CNTR CWKU or KOI is changed the corresponding interrupt request bit may also be set Therefore take the following sequence 1 Disable the external interrupt which is selected 2 Change the active edge in interrupt edge selection register in the case of CNTRo Timer X mode register in the case of CNTR Timer Y mode register 3 Clear the interrupt request bit to 0 4 Enable the external interrupt which is selected 7630 Group User s Manual 1 17 HARDWARE INTERRUPTS Table 5 Interrupt vector addresses and priority Interrupt source Priority Vector Address Note 1 High Low Interrupt Request Generating Conditions Remarks Reset Note 2 FFFB FFFA s At Reset Non maskable Watchdog timer FFF946 FFF846 At Watchdog timer underflow Non maskable INTO FFF746 FFF646 At detection of either rising or falling edge of INT interrupt External Interrupt active edge selectable INTA FFF546 FFF4 6 At detection of either rising or falling edge of INT interrupt External Interrupt active edge selectable CAN successful transmit FFF346 FFF246 At CAN module successful transmission of message Valid when CAN module is acti vated and request transmit CAN successful receive
71. from the memory at the ad dress indicated by index register X The results are stored into the memory of the ad dress indicated by index register X Ai or Mi 1 Sets the specified bit in the accumulator or memory to 1 Sets the contents of the carry flag to 1 Sets the contents of the decimal mode flag to F8 qe Sets the contents of the interrupt disable flag 78 3 60 7630 Group User s Manual APPENDIX 3 10 Machine instructions Addressing mode Processor status register ABS X ABS Y IND ZP IND IND X IND Y REL 3 OP n JOP n JOP n OP n OP n JOP n JOP D saved in stack saved in stack 7630 Group User s Manual 3 61 APPENDIX 3 10 Machine instructions Addressing mode Function Details A BIT A R ZP BIT ZP R n JOP n OP OP n STA Stores the contents of accumulator in memory STP Stops the oscillator Note 7 STX Stores the contents of index register X in memory STY Stores the contents of index register Y in memory TAX Transfers the contents of the accumulator to index register X TAY Transfers the contents of the accumulator to index register Y TST 7 Tests whether the contents of memory are 0 or not TSX
72. hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Re
73. initialized simultaneously when set to 1 only the reload latch will be initialized on an underflow the counter will be set to the modified reload value Writing to timer 3 initializes latch and counter both Timer 2 or 3 underflow causes the timer 2 or 3 interrupt request bit to be set to 1 1 26 7630 Group User s Manual HARDWARE TIMERS Timer 123 mode register address 001946 T123M PWM polarity selection bit 0 Starton H level output 1 Start on L level output PWM output enable bit 0 PWM output disabled 1 PWM output enabled Timer 2 write control bit 0 Latch and counter 1 Latch only Timer 2 count source selection bit 0 Timer 1 underflow 1 Pre divider output Timer 3 count source selection bit 0 Timer 1 underflow 1 Pre divider output Not used 0 when read do not write 1 Pre divider division ratio bits b7 b6 divided by 1 divided by 8 divided by 32 divided by 128 Fig 24 Timer 123 mode register configuration 0 is internal system clock Operating Modes 2 PWM Mode A This mode is available with timer 2 and 3 1 Timer Mode Count source The count source can be separately selected to be either the pre divider output or timer 1 underflow This mode is available with timers 1 to 3 Count source For timer 1 the count source is the output of the corresponding Operation pre divider For timers 2 and 3 the count source
74. latches and one com mon pre divider Timer 1 can operate in the timer mode only whereas timers 2 and 3 can be used to generate a PWM output signal timing as well Timers 1 to 3 are down count timers See Fig 23 T1 latch 8 T1 counter 8 gt Ti interrupt T2 latch 8 T2 counter 8 T2 interrupt 4 A o O T123M O To Qi T123M T3 latch 8 T3 counter 8 T3interrupt P1 latch P1 PWM O Fig 23 Block diagram of timers 1 to 3 is internal system clock Timer 1 The count source of timer 1 is the output of timer 123 pre divider The division ratio of the pre divider can be selected by the pre divider divi sion ratio bits of timer 123 mode register T123M Refer to Timer 123 mode register configuration f is internal system clock On a timer 1 underflow the timer 1 interrupt request bit will be set to A Writing to timer 1 initializes the latch and counter Timers 2 and 3 The count source of timers 2 and 3 can be either the output of the timer 123 pre divider or the timer 1 underflow The count source can be selected by the timer count source selection bits of timer 123 mode register T123M Writing to timer 2 register affects the reload latch only or both of the reload latch and counter depending on the timer 2 write control bit of T123M When the timer write control bit is set to 0 both latch and counter will be
75. level is L start transmission Note Check the shift completion of the Transmit shift register with the Transmit shift register shift completion flag Transmit initialization End of communication The Transmit enable bit is cleared to 0 The Transmission register empty flag is set to 1 The Transmission buffer empty flag is set to 1 UCON Address 002216 bit 2 4 0 Note Controlled by the serial I O logic Fig 2 5 22 Control procedure on transmitting side Communication using UART 7630 Group User s Manual 2 83 APPLICATION 2 5 Serial I O e Receiving side RESET Initialization CPUM Address 000016 00000X002 UMOD Address 002016 010X101X2 UCON Address 002216 XXXX10002 UBRG Address 002116 4 1 p Ax UCON Address 002216 bit 1 lt 1 USTS Address 002316 bit 2 1 Read the received data from URBR1 Address 002616 USTS Address 002316 bit 6 USTS Address 002316 bit 2 1 Read the received data from URBR1 Address 002616 USTS Address 002316 bit 6 X These bits are not used in this application Please set these bits to O or 1 appropriately f XiN divided by 2 high speed mode Transfer data format 1ST 8DATA 2SP Receive initialization
76. low impedance of the power and ground supply to keep Vcc and Vss within the specified limits In particular avoid subjecting ports to overvoltage causing Vcc Vss to rise above 5 5 V Port PO must not be subjected to overvoltage conditions Overvoltages causing input current flowing through the internal port protection circuits have a negative effect on the ports noise immunity Therefore careful and intense testing of the target system s noise immunity is required Because of the above noise immunity issue it is not recommended to subjects ports with interrupt functions such as ports for external interrupt to overvoltage conditions Refer to the 3 4 Countmeasures against noise 7630 Group User s Manual 2 7 APPLICATION 2 1 1 0 ports 2 1 4 Handling examples of unused pins Table 2 1 1 Handling of unused pins Name of Pins Ports Handling PO P11 Note P12 to P17 P2 P3 P4 Configure as inputs and pull to Vcc or Vss via a resistor of 1 kQ to 10 kQ or configure as outputs and leave open expect P11 VREF Connect to Vss GND or leave open AVSS Connect to Vss GND XOUT Leave open only when using external clock Note The P11 pin of the built in programmable ROM version is used in common with the VPP pin insert a register of about 5 kQ in series and connect by the shortest wiring 2 8 7630 Group User s Manual APPLICATION 2 2 Interrupts 2 2 Interrupts 2 2 1 Memory m
77. normal run mode refer to section 2 4 4 q Start of module reset bo 1 0 enter config mode 1 7 7 7 seb 1 CTRM i Module in configuration mode No transmission request CPU access possible Module idle or receiving 2 Cleared by module CTRM 3 CTRM 5 CTRM 7 CREC 0 CREC 1 Receive buffer empty CABORT 0 Module idle 2 CABORT Y No transmit abort request enter normal mode 3 clo I CIBM bo 0 0 4 End of module reset Module in normal mode p previous value of the bit retained Fig 2 4 29 Module reset sequence Note Do not reset the module starting from sleep mode 7630 Group User s Manual 2 53 APPLICATION 2 4 Controller Area Network CAN module 2 4 7 Acceptance filtering The module contains a hardware filtering circuit to screen out the useless messages out of the message stream and thereby reduce CPU load This filter probes the identifier field of any frame on the bus and decides which frames are relevant to the given node and which may be abandoned 1 Register structure The hardware implements a single condition identifier filter by a set of acceptance code CACi Figures 2 4 6 to 2 4 10 and acceptance mask CAMi Figures 2 4 11 to 2 4 15 registers These registers cover the
78. of the identifier field of a frame to be transmitted For CRB4 These bits represent part of the identifier field of a frame received Note 1 Remote transmission request bit Fig 2 4 22 Structure of CAN transmit receive buffer registers 4 CTB4 CRB4 2 46 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module CAN transmit receive buffer registers 5 b7 b6 b5 b4 b3 b2 b1 bo CAN transmit buffer register 5 CTB5 Address 0045 g CAN receive buffer register 5 CRB5 Address 0055 g B Name Function At reset The data length code indicates the DLC bit 0 number of data bytes in a data frame b3b2b1b0 0000 Zero data bytes 0001 One data byte 0010 Two data bytes DLC bit 1 DLC bit 2 0111 Seven data bytes 1000 Eight data bytes For CTB5 Set this bit to 0 must be sent dominant DLC bit 3 rO bit reserved bit 0 When these bits are read out the value are 0 Don t write to 1 Fig 2 4 23 Structure of CAN transmit receive buffer registers 5 CTB5 CRB5 CAN transmit receive buffer registers 6 to D b7 b6 b5 b4 b3 b2 b1 bo CAN transmit buffer registers 6 to D CTB6 to CTBD Addresses 004646 to 004D g CAN receive buffer registers 6 to D CRB6 to CRBD Addresses 005646 to 005D
79. of 7600 series addressing modes and machine instruc tions or the 7600 series Software Manual for details on the instruc tion set Machine resident 7600 series instructions are as follows The MUL DIV WIT and STP instruction can be used The central processing unit CPU has the six registers Accumulator A The accumulator is an 8 bit register Data operations such as data transfer etc are executed mainly through the accumulator Index register X X Index register Y Y Both index register X and index register Y are 8 bit registers In the index addressing modes the value of the OPERAND is added to the contents of register X or register Y and specifies the real address When the T flag in the processor status register is set to 1 the value contained in index register X becomes the address for the sec ond OPERAND HARDWARE FUNCTIONAL DESCRIPTION Stack pointer S The stack pointer is an 8 bit register used during sub routine calls and interrupts The stack is used to store the current address data and processor status when branching to subroutines or interrupt rou tines The lower eight bits of the stack address are determined by the con tents of the stack pointer The upper eight bits of the stack address are determined by the Stack Page Selection Bit If the Stack Page Selection Bit is 0 then the RAM in the zero page is used as the stack area If the Stack Page Selection Bit is 1 th
80. read don t write 1 Pre divider division ratio bits divided by 1 Note divided by 8 Note divided by 32 Note divided by 128 Note Note The internal system clock q is divided f XIN by 2 or by 8 The division ratio is decided by the Internal system clock selection bit bit 6 of the CPU mode register address 000016 Fig 3 5 16 Structure of Timer 123 mode register 7630 Group User s Manual 3 29 APPENDIX 3 5 List of registers Timer XL Timer XH Timer YL Timer YH b7 b6 b5 b4 b3 b2 b1 bO Timer XL TXL Timer XH TXH Address 001A16 001B16 Timer YL TYL Timer YH TYH Address 001C16 001D16 Set 000016 to FFFF16 as timer count value Write access The timer value is written to Timer X or Timer Y and latch at the same timer or to the latch only Note Write first low byte TXL TYL and then high byte TXH TYH Read access To get the actual Timer X or Timer Y value read out the corresponding timer register A measurement value is read out in pulse period and pulse width measurement mode Read first high byte TXH TYH and then low byte TXL TYL Note Depinding on the Timer X or Timer Y data write control bit bit O of the Timer X or Timer Y mode register address 001E16 001F 16 Fig 3 5 17 Structure of Timer XL Timer XH Timer YL Timer YH Timer X mode register b7 b6 b5 b4 b3 b2 bi bO Ce Timer X mode register TXM Address 001E1
81. register the transistor pulling toward the recessive level is selected Fig 2 2 9 Structure of Polarity control register 7630 Group User s Manual 2 13 APPLICATION 2 2 Interrupts 2 2 3 Interrupt setting method Figure 2 2 10 and Figure 2 2 11 show interrupt setting method Step 1 Disable all interrupts or the setting interrupts to prevent unnecessary interrupts occurring during setting In the former set the Interrupt disable flag I to 1 In the latter clear the corresponding interrupt enable bits to 0 b7 bo Interrupt control register A ICONA Address 000516 External interrupt INTo enable bit External interrupt INT1 enable bit CAN successful transmission interrupt enable bit CAN successful receive interrupt enable bit CAN overrun interrupt enable bit CAN error passive interrupt enable bit CAN bus off interrupt enable bit bo Interrupt control register B ICONB Address 000616 CAN wake up interrupt interrupt disabled Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit CNTRo interrupt enable bit CNTR interrupt enable bit bo Interrupt control register C ICONC Address 000716 UART receive complete receive buffer full interrupt enable bit UART transmit complete transmit register empty interrupt enable bit UART transmit buffer empty interrupt enable bit UART receive er
82. shortly before the recessive to dominant edge of the start of frame field 2 Set CAN successful transmit interrupt request bit IREQA 3 within the last bit time of the end of frame field 3 Clear transmit request bit CTRM 3 and transmit buffer control bit CTRM 5 within the first bit time after the end of frame field 4 Clear transmit status bit CTRM 7 within the first bit time after the intermission field Upon arbitration loss the module changes to receiving state beginning with the next bit time after the occur rence of arbitration loss The transition from transmitting to receiving state is flagged by clearing of CTRM 7 and setting of CREC 1 see Figure 2 4 26 2 4 10 Abort transmission A low priority frame in the transmit buffer may not gain bus access if the bus carries heavy traffic by medium priority frames The low priority frame blocks the transmit buffer and causes significant delay in scheduling of further even high priority frames to be sent This scenario is known as priority inversion 2 62 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module To overcome this situation the module features an abort transmission request function This function is controlled by the transmit abort control bit CABORT O Figure 2 4 17 setting this bit withdraws the transmit request of the frame currently occupying the transmit buffer Requesting transmit abort during the transmission process CTRM 7 1 does no
83. the Timer Y interrupt request bit to O Initialize the count value Set the Timer Y division ratio so that the Timer Y interrupt occurs every 2 ms TXM Address 001E16 bit 7 0 Timer X Start counting TYM Address 001F16 bit 7 0 Timer Y Start counting CLI Interrupts Enabled Timer Y interrupt processing routine CLT Note 1 Note 1 When using the Index X mode flag T CLD Note 2 Note 2 When using the Decimal mode flag D Push registers to the stack area Push the registers used in the interrupt processing routine on the stack When the count value is 256 or more TXH Address 001B16 the processing is performed as out of range Compare the count value with the reference value D616 lt TXL Address 001A16 lt E416 In range Store the comparison result in flag Fpulse Out of range gt Fpulse lt 0 Fpulse lt 1 TXL Address 001416 lt FF 16 TXH Address 001B16 0016 i Initialize the count value Processing for a result of judgment Pop registers from the stack area Pop registers which are pushed on the stack RTI Fig 2 3 14 Control procedure Measurement of frequency 7630 Group User s Manual 2 29 APPLICATION 2 3 Timers 4 Timer application example 3 Measurement of pulse width of FG pulse generated b
84. up E No interrupt request interrupt request bit Interrupt requested 1 Timer X interrupt request bit 0 No interrupt request 1 Interrupt requested 2 Timer Y interrupt request bit 0 No interrupt request 1 Interrupt requested 3 Timer 1 interrupt request bit 0 No interrupt request 1 Interrupt requested 4 Timer 2 interrupt request bit 0 No interrupt request 1 Interrupt requested 5 Timer 3 interrupt request bit 0 No interrupt request x 1 Interrupt requested CNTRo interrupt request bit 0 No interrupt request 1 Interrupt requested CNTR interrupt request bit 0 No interrupt request 7 1 Interrupt requested Can be cleared to 0 by software but cannot be set to 1 Fig 2 2 3 Structure of Interrupt request register B 2 10 7630 Group User s Manual APPLICATION 2 2 Interrupts Interrupt request register C b7 b6 b5 b4 b3 b2 bi bO iillilJj Interrupt request register C IREQC Address 000416 S __Name__Furefon_ wveset n UART receive complete receive E No interrupt request buffer full interrupt request bit Interrupt requested UART transmit complete transmit T No interrupt request register empty interrupt request bit Interrupt requested UART transmit buffer empty be No interrupt request interrupt request bit Interrupt requested 3 UART receive error 0 No interrupt request interrupt request bit 1 Interrupt requested 4 Serial 1 O interrupt request b
85. 0 D Module awake i Switch to config mode and reset Select P3 as CTX output port bo Wake up 1 clb 0 CTRM Dominant L 1 2 clb 1 PCON CBTCON1 Activate CTX 1 seb 2 CTRM CAN baud rate prescaler 1 Baud rate 2 3 One sample per bit ldm 0 CBTCON1 Propagation time segment 1 idm 0DBh CBTCON2 no auto receive 4 3 seb 6 CREC CBTCON2 1 p E Phase buffer segment 1 4 Phase buffer segment 2 4 Sychronization jump width 4 0 A cleared by module acceptance filtering 5 auto receive interrupt disabled ldm 0 CAMO ldm 0 CAM1 Y ldm 0 CAM2 ldm 0 CAM3 ldm 0 CAM4 Mask all identifier bits y enter normal mode 6 clb 1 CTRM bo 0 0 y End of module initialization N m Switch to normal mode Fig 2 4 28 Module initialization sequence 2 52 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module 2 4 6 Module reset The sequence shown in Figure 2 4 29 initiates a module reset by switching the module from normal run to config uration mode and back to normal run mode again For details on configuration and
86. 0 Divided by 1 0001 Divided by 2 Prescaler division ratio 0010 Divided by 3 selection bits 1101 Divided by 14 1110 Divided by 15 1111 Divided by 16 0 One sample per bit 1 Three samples per bit Sampling control bit b7b6b5 000 One time quantum Propagation time duration 001 Two time quanta control bits 110 Seven time quanta 111 Eight time quanta Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 3 5 34 Structure of CAN bus timing control register 1 CBTCON1 3 38 7630 Group User s Manual CAN bus timing control register 2 b7 b6 b5 b4 b3 b2 bi b0 CAN bus timing control register 2 CBTCON2 Address 003246 APPENDIX 3 5 List of registers B Name Function At reset 0 Phase buffer segment 1 duration control bits b2b1b0 000 One time quantum 001 Two time quanta 110 Seven time quanta 111 Eight time quanta 0 Phase buffer segment 2 duration control bits b5b4b3 000 One time quantum 001 Two time quanta 110 Seven time quanta 111 Eight time quanta control bits Synchronization jump width b7b6 00 One time quantum 01 Two time quanta 10 Three time quanta 11 Four time quanta
87. 0 Group User s Manual APPLICATION 2 3 Timers CPU mode register Address 000016 bO Internal system clock selection bit 4 f XIN divided by 2 high speed mode Timer X mode register Address 001E16 b7 bO TXM 4 ana Timer X data write control bit Write to latch and timer at the same time Timer X mode bits Event counter mode CNTRo polarity selection bit Count at falling edge Timer X stop control bit Stop counting Clear this bit to 0 to start counting Timer Y mode register Address 001 F 16 bO b7 WUEBCOUEUE Timer Y count source selection bits divided by 8 Timer Y operation bits Timer mode Timer Y stop control bit Stop counting Clear this bit to 0 to start counting Timer XL Address 001416 b7 bO TXL FF16 Set to OOFF16 before counting a pulse Timer XH Address 001B16 After being started the timer decrements with each input pulse b7 bO TXH 0016 Timer YL Address 001C16 b7 bO TYL E716 Set to division ratio 1 to generate underflow Timer YH Address 001D16 every 2 ms at f X n 8 MHz b7 bO TYH 0316 Fig 2 3 12 Setting of related registers Measurement of frequency 1 7630 Group User s Manual 2 27 APPLICATION 2 3 Timers Interrupt request register B Address 000316 b7 bO eee E TE e 0 Timer Y interrupt request bit becomes 1 every 2 ms Interrupt control registe
88. 002016 b7 bO d ETC elo Clock divider selection bits 4 divided by 8 Stop bits selection bit Two stop bits Parity enable bit Parity checking disabled Word length selection bits 8 bits UART control register Address 002216 b7 bO UCON 1 0 0 Transmit enable bit Transmit disabled Receive enable bit Receive disabled Set this bit to 1 at starting communication Transmission initialization bit No action Receive initialization bit Initialize the receive eneble bit and receive status register flags UART baud rate generator Address 0021 16 b7 bO ael Transfer bit rate X 16 X p 1 The value p is decided by the Clock divider selection bits bit 1 and bit 2 of the UART mode register address 002016 Refer to Table 2 5 2 UART status register Address 002316 b7 bO Receive buffer full flag This flag is set to 1 at receive completed Check whether the receive data is readable out from the Receive buffer register with this flag Receive framing error flag This flag is set to 1 at framing error detected Receive overrun flag This flag is set to 1 at overrun detected Receive error sum flag This flag is set to 1 at some error detected Fig 2 5 21 Setting of related registers on receiving side Communication using UART 2 82 7630 Group User s Manual APPLICATION 2 5 Serial I O Control procedure Figure 2 5 22 shows a c
89. 002A16 Port P2 pull up control register PUP2 002B16 Port P3 pull up control register PUP3 002C16 Port P4 pull up down control register PUP4 002F16 Polarity control register PCON Fig 2 1 1 Memory map of I O port related registers 2 2 7630 Group User s Manual APPLICATION 2 1 1 0 ports 2 1 2 Related registers Port Pi register b7 b6 b5 b4 b3 b2 bi bO Port Pi register Pi i 0 1 2 3 4 Address 000816 000A16 000C16 000E16 001016 In output mode Wri ne Port latch Port Pit in In input mode Write Port latch 2 pu Port Pia m Note The bits corresponding to P10 P35 P3e and P37 are reserved 0 when read don t write 1 Fig 2 1 2 Structure of Port Pi register i 0 1 2 3 4 Port Pi direction register b7 b6 b5 b4 b3 b2 bi bO Port Pi direction register PiD i 0 1 2 3 4 Address 000916 000B16 000D16 OOOF 16 001116 e Nme Fion atrselm w Port Pi direction register 0 Port Pio input mode x 1 Port Pio output mode 0 Port Pi1 input mode x 1 Port Pi1 output mode 0 Port Pi2 input mode x 1 Port Piz output mode 0 Port Pis input mode x 1 Port Piz output mode 0 Port Pi4 input mode x 1 Port Pi4 output mode 0 Port Pis input mode x 1 Port Pis output mode 0 Port Pie input mode x 1 Port Pie output mode 0 Port Pi7 input mode x 1 Port Pi7 output mode Note The direction control bits corresponding
90. 01 One data byte 0010 Two data bytes DLC bit 1 DLC bit 2 0111 Seven data bytes 1000 Eight data bytes For CTB5 Set this bit to 0 must be sent dominant DLC bit 3 rO bit reserved bit 0 When these bits are read out the value are 0 Don t write to 1 Fig 3 5 53 Structure of CAN transmit receive buffer registers 5 CTB5 CRB5 CAN transmit receive buffer registers 6 to D b7 b6 b5 b4 b3 b2 b1 bo CAN transmit buffer registers 6 to D CTB6 to CTBD Addresses 004646 to 004D g CAN receive buffer registers 6 to D CRB6 to CRBD Addresses 005646 to 005D 46 B Name Function At reset 0 Data bit 0 2 Data bit 1 For CTBi These bits represent the byte Data bit 2 number i 6 of the data field of a frame to be transmitted Data bit 3 For CRBi These bits represent the byte Data bit 4 number i 6 of the data field of a frame received Data bit 5 i 6to Die Data bit 6 Data bit 7 Fig 3 5 54 Structure of CAN transmit receive buffer registers 6 to D CTB6 D CRB6 D 3 48 7630 Group User s Manual APPENDIX 3 6 Mask ROM ordering method 3 6 Mask ROM ordering method GZZ SH52 70B lt 84A0 gt 740 FAMILY MASK ROM CONFIRMATION FORM
91. 01F16 Timer Y mode register 002116 UART baud rate generator UBRG 002316 UART status register USTS 002516 UART transmit buffer register 2 UTBR2 002716 UART receive buffer register 2 URBR2 002916 Port P1 pull up control register PUP1 002Bt6 Port P3 pull up control register PUP3 002Dt6 Interrupt polarity selection register IPOL 002E16 Watchdog timer register WDT 002F16 Polarity control register PCON 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F 16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 CAN transmit control register CTRM CAN bus timing control register 1 CBTCON1 CAN bus timing control register 2 CBTCON2 CAN acceptance code register O CACO CAN acceptance code register 1 CAC1 CAN acceptance code register 2 CAC2 CAN acceptance code register 3 CAC3 CAN acceptance code register 4 CAC4 CAN acceptance mask register 0 CAMO CAN acceptance mask register 1 CAM1 CAN acceptance mask register 2 CAM2 CAN acceptance mask register 3 CAM3 CAN acceptance mask register 4 CAM4 CAN receive control register CREC CAN transmi
92. 16384 bytes The first 128 bytes and the last 4 bytes of ROM are reserved areas They cannot be used Memory type M Mask ROM version E EPROM or One Time PROM version Fig 3 Part numbering 7630 Group User s Manual 1 5 HARDWARE GROUP EXPANSION GROUP EXPANSION Mitsubishi plans to expand the 7630 group as follows Memory Size ROM PROM size 0 000 c eee eee 16 Kbytes RAM SiZ nA cro ier BE a eee ile As ee Re 512 bytes Memory Type Package Support mask ROM One Time PROM and EPROM versions 44P6N A 02 00 cece 0 8mm pitch plastic molded QFP 80DO 0 8mm pitch ceramic LCC EPROM version ROM External 60K a 48K 32K 28K 24K aon ES Under development 16K P n is 12K eee FERREA 8K ENT l l l l l l l l l l l 640 768 RAM size bytes Fig 4 Memory expansion plan Currently supported products are listed below Table 2 List of supported products As of March 1998 P ROM size bytes ROM size for User M37630M4T XXXFP Mask ROM version M37630E4T XXXFP One Time PROM version M37630E4FP One Time PROM version blank M37630E4FS EPROM version Product RAM size bytes Package Remarks 1 6 7630 Group User s Manual FUNCTIONAL DESCRIPTION Central Processing Unit CPU The 7630 group uses the standard 740 family instruction set Refer to the table
93. 179 3 61 2 71 2 7630 Group User s Manual 3 55 APPENDIX 3 10 Machine instructions Symbol Function Details Addressing mode A BIT A R ZP BIT ZP R n JOP n JOP OP n BVC Note 5 Branches when the contents of overflow flag is g BVS Note 5 Branches when the contents of overflow flag is I CLB Clears the contents of the bit specified in the accumulator or memory to 0 CLC Clears the contents of the carry flag to 0 CLD Clears the contents of decimal mode flag to Q CLI Clears the contents of interrupt disable flag to p CLT Clears the contents of index X mode flag to sp CLV Clears the contents of overflow flag to 0 CMP Note 3 Compares the contents of accumulator and memory Compares the contents of the memory speci fied by the addressing mode with the contents of the address indicated by index register X Forms a one s complement of the contents of memory and stores it into memory Compares the contents of index register X and memory Compares the contents of index register Y and memory A lt A 1or Mc M 1 Decrements the contents of the accumulator or memory by 1 Xe X 1 Decrements the con
94. 3 26 Fig 3 5 11 Structure of Serial l O control register 3 27 Fig 3 5 12 Structure of A D conversion register 3 27 Fig 3 5 13 Structure of A D control register 3 28 Fig 3 5 14 Btructure or Timer 1 Timer east 3 28 Fig 3 5 15 Btructure of Timer A II A 3 29 Fig 3 5 16 Btructure of Timer 123 mode register oxisonrsicerisniciciras ici 3 29 Fig 3 5 17 Structure of Timer XL Timer XH Timer YL Timer YH 3 30 Fig 3 5 18 Structure of Timer X mode register 3 30 Fig 3 5 19 Structure of Timer Y mode register eene 3 31 Fig 3 5 20 Structure of UART mode register sss 3 31 Fig 3 5 21 Structure of UART baud rate generator ssssssssssssss 3 32 Fig 3 5 22 Structure of UART control register 3 32 Fig 3 5 23 Btructure of UART status register tenentes 3 33 Fig 3 5 24 Btructure of UART transmit buffer register 1 2 3 33 Fig 3 5 25 Structure ot UART receive buffer register 1 2 3 34 Fig 3 5 26 Structure of Port Pi pull up control register i 0 2 3 34 Fig 3 5 27 Structure of Port P1 pull up control register 3 35 Fig 3 5 28 Structure of Port P3 pull up control register eee eeeee eens 3 35 Fig 3 5 29 Structure of Port P4 pull up down control register 3 36 Fig 3 5 30 Structure of Interrupt polarity Selection register eee eee eeeeees 3 36 Fig 3 5 31 St
95. 4 Pulse width measurement mode This mode is available with timer X only Count source The count source is the output of timer X clock divider The divi sion ratio can be selected by the timer Y mode register Operation The timer counts down while the input signal level on P1 CNTRo matches the active polarity selected by the CNTR polarity selec tion bit of TXM Structure of Timer X mode register On a timer underflow the timer X interrupt request bit will be set to 1 the contents of the timer latches are reloaded to the counters and counting continues When the input level changes from active polarity as selected the CNTRo interrupt request bit will be set to 1 The measurement result may be obtained by reading timer X during interrupt service 5 Pulse period measurement mode This mode is available with timer Y only Count source The count source is the output of timer Y clock divider HARDWARE TIMERS Operation The active edge of input signal to be measured can be selected by CNTR polarity selection bit Fig 20 When this bit is set to 0 the time between two consecutive falling edges of the signal input to P15 CNTR pin will be measured when the polarity bit is set to 1 the time between two consecutive rising edges will be mea sured The timer counts down On detection of an active edge of input signal the contents of the TY counters will be transferred to t
96. 4 divided by 8 Stop bits selection bit Two stop bits Parity enable bit Parity checking disabled Word length selection bits 9 bits UART control register Address 002216 b7 bO UCON fofofo Transmit enable bit Transmit disabled Receive enable bit Receive disabled Set this bit to 1 at starting communication Transmission initialization bit No action Receive initialization bit Initialize the receive eneble bit and receive status register flags hod baud rate generator Address 002116 Transfer bit rate X 16 X p The value p is decided by the Clock divider selection bits bit 1 and bit 2 of the UART mode register address 002016 Refer to Table 2 5 2 UART status register Address 002316 b7 bo Receive buffer full flag This flag is set to 1 at receive completed Check whether the receive data is readable out from the Receive buffer register with this flag Receive framing error flag This flag is set to 1 at framing error detected Receive overrun flag This flag is set to 1 at overrun detected Receive error sum flag This flag is set to 1 at some error detected Fig 2 5 27 Setting of related registers on receiving side Communication using UART 7630 Group User s Manual 2 87 APPLICATION 2 5 Serial I O Control procedure Figure 2 5 28 shows a control procedure on the transmitting side and Figure 2 5 29 sho
97. 46 B Name Function At reset 0 Data bit 0 2 Data bit 1 For CTBi These bits represent the byte Data bit 2 number i 6 of the data field of a frame to be transmitted Data bit 3 For CRBi These bits represent the byte Data bit 4 number i 6 of the data field of a frame received Data bit 5 i 6to Die Data bit 6 Data bit 7 Fig 2 4 24 Structure of CAN transmit receive buffer registers 6 to D CTB6 D CRB6 D 7630 Group User s Manual 2 47 APPLICATION 2 4 Controller Area Network CAN module 2 4 4 Operational modes The module features three operational modes which can be selected by the sleep control bit CTRM O and the reset configuration control bit CTRM 1 of the CAN transmit control register Figure 2 4 3 Mode transitions may be carried out according to Figure 2 4 25 Normal run mode CTRM 1 0 CTRM 0 0 Configuration mode CTRM 1 1 CTRM 0 0 Sleep mode CTRM 1 1 CTRM O 1 Fig 2 4 25 Transitions among operational modes 1 Configuration mode This mode is used to initialize refer to section 2 4 5 or reset refer to section 2 4 6 the module Entering the configuration mode initiates the following functions by the module Suspend communication functions Set P3 CTX output to recessive if P34 is configured as CT
98. 5 43 Structure of CAN acceptance mask register 2 CAM2 CAN acceptance mask register 3 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance mask register 3 CAM3 Address 003B g B Name Function O Extended identifier mask bit 6 Extended identifier mask bit 7 Extended identifier mask bit 8 Extended identifier mask bit 9 0 Mask identifier bit don t care 1 Compare identifier bit Extended identifier mask bit 10 Extended identifier mask bit 11 These bits mask the corresponding bits of the acceptance code register 3 Figure 3 5 39 from the acceptance filtering Extended identifier mask bit 12 Extended identifier mask bit 13 Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 3 5 44 Structure of CAN acceptance mask register 3 CAM3 7630 Group User s Manual 3 43 APPENDIX 3 5 List of registers CAN acceptance mask register 4 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance mask register 4 CAM4 Address 003C46 B Name Function At reset 0 These bits must be set to 0 Extended identifier mask bit 0 Extended identifier mask bit 1 Extended identifier mask bit 2 0 Mask identifier bit don t care 1 Compare identif
99. 6 nO Tae rum X data write control bit Data is written to latch and timer Data is written to latch only a Top o fox Timer mode fofo Bi phase counter mode Event counter mode Pulse width measurement mode For event counter mode rising edge active For interrupt request falling edge active For pulse width measurement mode measure H period For event counter mode falling edge active For interrupt request rising edge active For pulse width measurement mode measure L period 7 Timer X stop control bit 0 Timer counting 1 Timer stopped Fig 3 5 18 Structure of Timer X mode register 3 30 7630 Group User s Manual Timer Y mode register b7 b6 b5 b4 b3 b2 bi bO APPENDIX 3 5 List of registers EXE SIE Timer Y mode register TYM Address 001F 16 Timer X count source selection bits Timer Y count source selection bits Timer Y operation mode bits CNTRt polarity selection bit divided by 4 Note divided by 16 Note divided by 64 Note divided by 128 Note divided by 2 Note divided by 8 Note divided by 32 Note divided by 64 Note Timer mode Pulse period measurement mode Event counter mode H L pulse width measurement mode 0 For event counter mode rising edge active For interrupt request falling edge active For pulse period measurement mode refer to falling edge 1 For event counter mode
100. AD conversion complete interrupt request bit Key on wake up interrupt request bit Step 4 Set the using interrupt enable bits to 1 interrupt enabled Refer to Step 1 Step 5 When the Interrupt disable flag I is set to 1 in Step 1 clear the flag to O interrupt enabled Step 6 Operate the each functions related the using interrupts Note 2 Note 2 For details refer to setting method of each function Fig 2 2 11 Interrupt setting method 2 7630 Group User s Manual 2 15 APPLICATION 2 2 Interrupts 2 2 4 Key on wake up interrupt Figure 2 2 12 and Figure 2 2 13 show setting method for registers related to the key on wake up interrupt Step 1 Disable the key on wake up interrupt or all interrupts to prevent unnecessary interrupts occurring during setting In the former set the Interrupt disable flag I to 1 In the latter clear the Key on wake up interrupt enable bit to 0 b7 o IITTI Interrupt control register C ICONC Address 000716 Key on wake up interrupt enable bit Step 2 Set the ports of P4 used as key on wake up input pin to input mode b7 bo Port P4 direction register PAD Address 001116 Port P40 direction register Port P41 direction register Port P42 direction register Port P43 direction register 0 Input mode Port P44 direction register 1 Output mode Port P45 direction register Port P46 direction register Port P47 direction register
101. CREC 1 Figure 2 4 16 and CTRM 7 Figure 2 4 3 Module idle CTRM 7 0 start a CREC 1 0 detect an transmission SOF finish finish transmission reception Module transmitting Module receiving CTRM 7 1 CTRM 7 0 CREC 1 0 CREC 1 1 loose arbitration Fig 2 4 26 Transitions among module sub modes 3 Sleep mode This mode enables reduced power consumption by stopping the clock of the module consequently all func tions incl communication are suspended Setting the sleep control bit CTRM 1 Figure 2 4 3 switches the module to sleep mode Upon entering this mode the module s clock supply stops immediately CAN related registers retain their contents upon entering sleep mode Enter or leave sleep mode via configuration mode only refer to Figure 2 4 25 Warning Switching the module from normal run mode straight to sleep mode bypassing configuration mode may cause erroneous frames being sent to the bus or a CTX terminal forcing the bus to dominant level permanently 7630 Group User s Manual 2 49 APPLICATION 2 4 Controller Area Network CAN module 2 4 5 Module initialization Initializing the module comprises several steps Before attempting to access the registers involved the following items must be considered Acceptance filter The CAN acceptance code registers CACi Figures 2 4 6 to 2 4 10 and CAN acceptance mask registers CAMi Figures 2 4 11 to 2 4 15 need to be initialized For details on the
102. D The control of the buffers is done via the receive buffer control bit CREC O Figure 2 4 16 as shown in Figure 2 4 32 In normal run mode CREC 0 can be cleared by the CPU but can only be set by the CAN module Set by CAN module bs lt A Receive buffer control bit CREC O Foreground receive buffer content Y CRBO to CRBD undefined undefined d u Cleared by user s w Fig 2 4 32 Receive buffer handling 2 2 56 Receive process The receive sequence is initialized by the start of frame of a new incoming message The user software can check this status by the transmit status bit CTRM 7 and the receive status bit CREC 1 The module status changes from idle transmitting to receiving During the reception of a message the receive status bit CREC 1 is kept high It is cleared after the end of frame for details refer to section 3 below If the message is accepted and received without any errors the module initiates the following actions 1 Set CAN successful receive CSR interrupt request bit IREQA 4 2 Enable CPU access to the buffer i e switch it from background to foreground 3 Set receive buffer control bit CREC O If the CPU still processes a previously received frame in the foreground buffer and has not released the buffer yet the actions 2 and 3 are postponed In this case the module will continuously monitor CREC O and wait for the flag being cleared by user s w After that
103. FFF1 16 FFFO 6 At CAN module successful reception of message Valid when CAN module is acti vated CAN overrun FFEF 1g FFEEig If CAN module receives message when receive buffers are full Valid when CAN module is acti vated CAN error passive FFEDi FFECi When CAN module enters into error passive state Valid when CAN module is active CAN error bus off FFEB e FFEAig When CAN module enters into bus off state Valid when CAN module is active CAN wake up FFE9 amp FFE8 6 When CAN module wakes up via CAN bus Timer X FFE746 FFEG 6 At Timer X underflow or overflow Timer Y FFE546 FFE446 At Timer Y underflow Timer 1 FFE346 FFE246 At Timer 1 underflow Timer 2 FFE146 FFE046 At Timer 2 underflow Timer 3 FFDF 16 FFDE At Timer 3 underflow CNTRO FFDD 6 FFDC 6 At detection of either rising or falling edge in CNTRo input External Interrupt active edge selectable CNTR1 FFDBi FFDA 6 At detection of either rising or falling edge in CNTR input External Interrupt active edge selectable UART receive FFD9y6 FFD8 At completion of UART receive Valid when UART is selected UART transmit FFD74 FFD64 At completion of UART transmit Valid when UART is selected UART transmit buffer empty FFD54 FFD 446 At UART transmit buffer empty Valid w
104. Fig 37 Structure of CAN bus timing control register 1 1 35 Fig 38 Structure of CAN bus timing control register 2 1 36 Fig 39 Btructure of CAN mask and code registers 10101211 1n 1 36 Fig 40 Structure of CAN transmission and reception buffer registers 1 37 Fig 41 Block diagram of A D converter 1 38 Fig 42 Structure of A D Control teglster ooccccccccnccnccncococccnnccnncnncnnnnnnnnononccnncnnnnnncnnannnnns 1 39 Fig 43 Block diagram of watchdog time 1 40 Fig 44 Structure of watchdog timer register 1 40 Fig 45 Example of reset CirGUltl coooonnnnnnicnnnnnnnnnnncnnncccnnncccnnnnrcc cnn 1 41 Fig 46 Reset o eterne eene Rx nene xa dea ER ERA n DRE A t X EN 1 41 Fig 47 Internal status of microcomputer after reset sseemmm 1 42 iv 7630 GROUP USER S MANUAL List of figures Fig 48 Ceramic resonator circultl ooconccccncccoconoocnnocnnonanooonnnonnconnnonononnnnnonnnonnnonnnananonnno 1 43 Fig 49 Block diagram of clock generating circuit ceete ten 1 43 Fig 50 Programming and testing of One Time PROM version 1 44 Fig 51 Circuit for measuring output switching characteristics 1 49 Fig 52 Timing diagram tennis 1 50 HAPTER 2 APPLICATION Fig 2 1 1 Memory map of I O port related registers ssseeee 2 2 Fig 2 1 2 Structure of Port Pi register 1 0 1 2 3 4 2 3 F
105. I O application examples 1 Output of serial data control of a peripheral IC Outline 4 byte data is transmitted and received using the clock synchronous serial I O The CS signal is output to a peripheral IC through the port P33 7630 group Peripheral IC Fig 2 5 13 Connection diagram Output of serial data Specifications The Serial I O is used the clock synchronous serial I O is selected e Synchronous clock frequency 125 kHz f XIN 8 MHz is divided by 64 Transfer direction LSB first e The Serial I O interrupt is not used Port P33 is connected to the CS pin L active of the peripheral IC for transmission control the output level of port P33 is controlled by software Figre 2 5 14 shows an output timing chart of serial data DATA fpe X joo f f Do A A Do A Note The Sour pin is in high impedance state after completion of data transfer Fig 2 5 14 Timing chart Output of serial data 7630 Group User s Manual 2 75 APPLICATION 2 5 Serial I O Figure 2 5 15 shows a setting of serial I O related registers and Figure 2 5 16 shows a setting of serial I O transmission data 1 O control i Address 001316 seco ToS HIST Ol Clock divider selection bits y divided by 32 P20 Sin P21 Sour P22 ScLk function selection bit Use the serial I O P23 SrDY function selection bit SRDY output disabled Transmission order selection bit LSB first Synchronization clock selection bit Int
106. IX 3 5 List of registers CAN transmit abort register CAN transmit abort register CABORT Address 003E g b7 b6 b5 b4 b3 b2 bi b0 B Name Function At reset RO No transmit abort requested R1 Transmit abort requested WO Clear transmit abort request W1 Transmit abort requested Transmit abort control bit Not used Undefined at read Note 1 RO R1 denote read access WO W1 denote write access Note 2 Setting this bit to 1 is enabled only when CTRM 3 Figure 3 4 21 is set Fig 3 5 47 Structure of CAN transmit abort register CABORT CAN transmit receive buffer registers 0 b7 b6 b5 b4 b3 b2 b1 bo CAN transmit buffer register O CTBO Address 0040 g CAN receive buffer register 0 CRBO Address 0050 g B Name Function O Standard identifier bit 6 For CTBO These bits represent part of the identifier field of a frame to be transmitted Standard identifier bit 7 Standard identifier bit 8 Dou For CRBO These bits represent part of Standard identifier bit 9 the identifier field of a frame received Standard identifier bit 10 When these bits are read out the values Not used are 0 Don t write to 1
107. K TE 0 8Vcc KK KKK KKK NENI NZI POS aoee DXO tD SCLK SOUT tv ScLk souT Fig 3 1 2 Timing diagram 7630 Group User s Manual 3 7 APPENDIX 3 2 Standard characteristics 3 2 Standard characteristics 3 2 1 Power source current standard characteristics Figure 3 2 1 to Figure 3 2 4 show the power source current standard characteristics vs VCC and f XIN is both high and middle speed mode Measuring condition 25 C f XIN 10MHz in high speed mode 18 CAN runs all peripherials run CAN stops all peripherials run In wait mode E oO 9 oO 2 o oO o _ o o p 0 o a 4 5 5 5 5 Power source voltage VCC V Fig 3 2 1 Icc Vcc standard characteristics in high speed mode Measuring condition 25 C f XIN 10MHz in middle speed mode 18 CAN runs all peripherials run Power source current Icc mA CAN stops all peripherials run 4 5 5 5 5 Power source voltage Vcc V Fig 3 2 2 Icc Vcc standard characteristics in middle speed mode 3 8 7630 Group User s Manual APPENDIX 3 2 Standard characteristics Measuring condition 25 C Vcc VREF 5 V in high speed mode 14 CAN runs all peripherials run CAN stops all peripherials run In wait mode lt x E Q 2 c o _ _ 2 o o o 2 o a _ o z o 4 6 8 10 Clock input oscillation frequency f XIN MHz Fig 3
108. No pull up 1 Pull up 7 Pi7 pull up transistor control bit 0 No pull up 1 Pull up Fig 3 5 26 Structure of Port Pi pull up control register i 0 2 3 34 7630 Group User s Manual APPENDIX 3 5 List of registers Port P1 pull up control register b7 b6 b5 b4 b3 b2 bi bO T NI Port P1 pull up control register PUP1 Address 002916 D NE AN O ne pull up transistor control bit ME No pull up Pull up Not used 0 when read don t write 1 3 P13 pull up transistor control bit 0 No pull up 1 Pull up 4 P14 pull up transistor control bit 0 No pull up 1 Pull up 5 P15 pull up transistor control bit 0 No pull up 1 Pull up P16 pull up transistor control bit 0 No pull up 1 Pull up 7 P17 pull up transistor control bit 0 No pull up 1 Pull up Fig 3 5 27 Structure of Port P1 pull up control register Port P3 pull up control register b7 b6 b5 b4 b3 b2 bi bO ns Port P3 pull up control register PUP3 Address 002B16 Name Function At reset R w nm pull up transistor control bit a No pull up Pull up P31 pull up transistor control bit 0 No pull up 1 Pull up 2 P32 pull up down transistor 0 No pull up down control bit 1 Pull up down Note 3 P33 pull up transistor control bit 4 No pull up Pull up P34 pull up transistor control bit m No pull up Pull up 5 Not used 0 when read don t write 1 EXE DE Note Enables the p
109. Note a Timer Y operation mode bits Timer mode Pulse period measurement mode 009 sun 9 OF 00 Event counter mode H L pulse width measurement mode CNTR polarity selection bit O For event counter mode rising edge active For interrupt request falling edge active For pulse period measurement mode refer to falling edge For event counter mode falling edge active For interrupt request rising edge active For pulse period measurement mode refer to rising edge 7 Timer Y stop control bit O Timer counting 1 Timer stopped Note The internal system clock q is divided f XIN by 2 or by 8 The division ratio is decided by the Internal system clock selection bit bit 6 of the CPU mode register address 000016 Fig 2 3 7 Structure of Timer Y mode register 7630 Group User s Manual 2 21 APPLICATION 2 3 Timers 2 3 3 Timer application examples 1 Basic functions and uses Function 1 Control of Event interval Timer X Timer Y Timer 1 Timer 2 Timer 3 The Timer count stop bit is set to O after setting a count value to a timer Then a timer interrupt request occurs after a certain period Timer mode Use Generation of an output signal timing Generation of a waiting time Function 2 Control of Cyclic operation Timer X Timer Y Timer 1 Timer 2 Timer 3 The value of a timer latch is automatically written to a corresponding timer every time a timer underflows
110. Port P4 direction register P4D 004146 CAN transmit buffer register 1 CTB1 Serial I O shift register SIO 004246 CAN transmit buffer register 2 CTB2 Serial I O control register SIOCON 0043 65 CAN transmit buffer register 3 CTB3 A D conversion register AD 004446 CAN transmit buffer register 4 CTB4 A D control register ADCON 004546 CAN transmit buffer register 5 CTB5 Timer 1 T1 004646 CAN transmit buffer register 6 CTB6 Timer 2 T2 004716 CAN transmit buffer register 7 CTB7 Timer 3 T3 0048 65 CAN transmit buffer register 8 CTB8 Timer 123 mode register 0049 65 CAN transmit buffer register 9 CTB9 Timer XL 004A 6 CAN transmit buffer register A CTBA Timer XH 004B 6 CAN transmit buffer register B CTBB Timer YL 004C s CAN transmit buffer register C CTBC Timer YH 004D46 CAN transmit buffer register D CTBD Timer X mode register 004E Reserved Timer Y mode register 004F Reserved UART mode register 005046 CAN receive buffer register 0 UART baud rate generator 005116 CAN receive buffer register 1 UART control register 005246 CAN receive buffer register 2 UART status register 0053 56 CAN receive buffer register 3 UART transmit buffer register 1 005446 CAN receive buffer register 4 UART transmit buffer register 2 005546 CAN receive buffer register 5 UART receive buffer register 1 005646 CAN receive buffer register 6 UART receive buffer register 2 005716 CAN receive buffer register 7 Port PO pull up control register 005846 CAN receive buffer register
111. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry ENESAS 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted
112. X output port see CTRM 2 in Figure 2 4 3 Unlock the following configuration register to enable initialization 1 acceptance code and mask registers CACI CAMIi Figures 2 4 6 to 2 4 15 2 CAN bus timing control registers CBTCONi Figures 2 4 4 and 2 4 5 Set module to error active state and clear the internal error counters refer to section 2 4 12 Clear transmit request transmit buffer control and transmit status bits of CTRM Figure 2 4 3 Clear receive buffer control and receive status bits of CREC Figure 2 4 16 Clear transmit abort bit of CABORT Figure 2 4 17 The values of the remaining bits of CTRM CREC and of other CAN module related configuration registers PCON CBTCON1 CBTCON2 CACO to CAC4 CAMO to CAM4 retain the values they had before entering the configuration mode The contents of the transmit and receive buffer registers CTBi CRBi Figures 2 4 19 to 2 4 24 are undefined in configuration mode The module is set to configuration mode upon MCU reset Note Switching the module from normal run to configuration mode during an ongoing transmission sus pends communication immediately this causes a corrupted frame on the bus To avoid the corrupt frame either await the successful transmission see section 2 4 9 or issue an abort transmission request see sec tion 2 4 10 before attempting the mode transition 2 Normal run mode Entering this mode initiates the following functions by the module
113. Y is a 16 bit timer with a 16 bit reload latch supporting the fol lowing operating modes 1 Timer mode 3 Event counter mode 5 Pulse period measurement mode 6 H L pulse width measurement mode These modes can be selected by the timer Y mode register TYM In the timer pulse period and pulse width measurement modes the timer s count source can be selected by the timer Y count source selection bits Please refer to Fig 21 On read or write access to timer Y note that the high order and low Read method When reading the timer Y read the high order byte first This causes the timer Y high and low order bytes to be transferred to temporary registers being assigned to the same addresses as TYy and TYL Next read the low order byte which is read from the temporary regis ter This method assures the correct timer value can be read during timer count operation order bytes must be accessed in a specific order Write method When writing to timer Y write the low order byte first The data written is stored in a temporary register which is assigned to the same Timer Y count stop control Regardless of the actual operating mode timer Y can be stopped by setting the timer Y count stop bit bit 7 of the timer Y mode register to in s 7630 Group User s Manual 1 23 HARDWARE TIMERS Timer Y mode register address 001F 4 TYM Timer X count source selection bits b1 bO 0 0 divided by 4 01 divided by 16 1 0
114. a clean original of the logo For the new special character fonts a clean font origi nal ideally logo drawing must be submitted Special logo required The standard Mitsubishi font is used for all characters except for a logo 7630 Group User s Manual 3 51 APPENDIX 3 8 Package outline 3 8 Package outline 44P6N A Plastic 44pin 10X10mm body QFP EIAJ Package Code JEDEC Code Weight g Lead Material QFP44 P 1010 0 80 0 59 Alloy 42 Mo HD o DI 7 D a m n 2 b 2 U0 Recommended Mount Pad Symbol Dimension in Millimeters y Min Nom Max A 3 05 A1 0 0 1 0 2 A2 2 8 b 0 3 0 35 0 45 A C 0 13 0 15 0 2 D 9 8 10 0 10 2 L1 E 9 8 10 0 10 2 e 0 8 HD 12 5 12 8 13 1 HE 12 5 12 8 13 1 L 0 4 0 6 0 8 Li 1 4 y 0 1 E 0 0 10 lt b2 0 5 l2 1 3 Detail F MD Z 10 6 Z ME 10 6 80D0 Glass seal 80pin QFN EIAJ Package Code JEDEC Code Weight g T 21 0 0 2 gt 3 32MAX 18 4 0 15 1 78TYP _0 8TYP 0 6TYP A HI 1 a gt N 5 o e q P d 2 a gt E N i a A ONEEK gt INDEX G S 3 52 7630 Group User s Manual APPENDIX 3 9 Li
115. acceptance filter see section 2 4 7 Bit timing The time for the transmission of a single bit consists of four segments Synchronization segment SS Propagation time segment PTS Phase buffer segment 1 PBS1 Phase buffer segment 2 PBS2 SS is of fixed length one time quantum but the length of PTS PBS1 2 must be programmed by the bus timing control registers CBTCONI Figures 2 4 4 and 2 4 5 Figure 2 4 27 shows the segmentation of one bit time and the possible range for each segment to be programmed Note The CAN specification defines the sum of all time quanta within one bit time between 8 and 25 Range in time quanta Min Max Tss 1 fixed T Segment Le bit time tht SS PTS PBS1 PBS2 pts T pts Tobst Tobs2 Tpbs1 sample point 7 pbs2 Fig 2 4 27 Segmentation of bit time The sample point is the point within a bit time where the bus level is known as the value of that respective bit Its position is between phase buffer segment 1 and phase buffer segment 2 The sample point must be defined in common for all active nodes on the network Resynchronization jump width The resynchronization jump width can be programmed via CBTCON2 Figure 2 4 5 Note The CAN specification defines resynchronization jump width as min 4 Tops Sampling The sampling control bit CBTCON1 4 Figure 2 4 4 allows to decide the bit level based on eithe
116. aded to the counters and counting continues 2 Bi phase counter mode quadruplicate This mode is available with timer X only Count source The count sources are P1 CNTRo and the P13 TXg pins Count direction Operation Timer X will count both rising and falling edges on both input pins see above Refer to Timer X bi phase counter mode operation On a timer over or underflow the corresponding interrupt request for the timing chart of the bi phase counter mode bit will be set to 1 and counting continues 1 24 7630 Group User s Manual P14 TXy input signal P1 CNTRg input signal TX counter Count direction Fig 22 Timer X bi phase counter mode operation 3 Event counter mode This mode is available with timer X and timer Y Count source The count source for timer X is the input signal to the P1 CNTR y pin and for timer Y the input signal to P15 CNTR pin Operation The timer counts down On a timer underflow the corresponding timer interrupt request bit will be set to 1 the contents of the cor responding timer latches will be reloaded to the counters and counting continues The active edge used for counting can be selected by the polarity selection bit of the corresponding pin P14 ONTR or P1s CNTR These bits are part of TXM Structure of Timer X mode register and TYM Structure of timer Y mode register f is internal system clock registers
117. ag D Push registers to the stack area Push the registers used in the interrupt processing routine on the stack Check if the clock has already been set N Clock count up 1 40 second to year Count up the clock Pop registers from the stack area Popregisters which are pushed on the stack RTI Fig 2 3 10 Control procedure Clock function 7630 Group User s Manual 2 25 APPLICATION 2 3 Timers 3 Timer application example 2 Measurement of frequency Outline To judge if the frequency is within a given range the following two values are compared Timer value representing the number of pulses at P14 CNTRo Referance value Specifications The pulse is input to the P14 CNTRo pin and counted by the Timer X A count value is read out at the interval of about 2 ms Timer Y interrupt interval When the count value is between 28 and 40 the input signal is judged valid Because the timer is a down counter the count value is compared with 227 to 215 227 to 215 255 initialized value of counter 28 to 40 the number of valid value Figure 2 3 11 shows a method for judging if input pulse exists and Figure 2 3 12 and Figure 2 3 13 show a setting of related registers More than 71 4 us 714 50 Less than 50 us Less than 14 kHz More than 20 kHz Invalid i Invalid 28 counts 2 40 counts 50 us Fig 2 3 11 A method for judging if input pulse exists 2 26 763
118. agram of timers X and Y o is internal system clock Timer X Timer X is a 16 bit timer with a 16 bit reload latch supporting the fol lowing operating modes 1 Timer mode 2 Bi phase counter mode 3 Event counter mode 4 Pulse width measurement mode These modes can be selected by the timer X mode register TXM In the timer and pulse width measurement mode the timer s count source can be selected by the timer X count source selection bits of the timer Y mode register TYM Please refer to the Figures below for the TXM and TYM bit assignment On read or write access to timer X note that the high order and low order bytes must be accessed in the specific order Write method When writing to the timer X write the low order byte first The data written is stored in a temporary register which is assigned to the same address as TX Next write the high order byte When this is finished the data is placed in the timer X high order reload latch and the low order byte is transferred from its temporary register to the timer X low order reload latch Depending on the timer X write control bit the latch contents are reloaded to the timer immediately write control bit O or on the next timer underflow write control bit 1 Read method When reading the timer X read the high order byte first This causes the timer X high and low order bytes to be transferred to temporary registers being assigned to the sam
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120. ap of interrupt related registers 000416 Interrupt request register C IREQC 000716 Interrupt control register C ICONC 002D16 Interrupt polarity selection register IPOL 002F 16 Polarity control register PCON Fig 2 2 1 Memory map of interrupt related registers 7630 Group User s Manual 2 9 APPLICATION 2 2 Interrupts 2 2 2 Related registers Interrupt request register A b7 b6 b5 b4 b3 b2 bi bO OT A Interrupt request register A IREQA Address 000216 e Name Furion atesa R W Not used 0 when read BUE External interrupt INTo request bit d No interrupt request Interrupt requested 2 External interrupt INT request bit 0 No interrupt request 1 Interrupt requested 3 CAN successful transmission 0 No interrupt request interrupt request bit 1 Interrupt requested 4 CAN successful receive 0 No interrupt request x interrupt request bit 1 Interrupt requested 5 CAN overrun 0 No interrupt request interrupt request bit 1 Interrupt requested CAN error passive 0 No interrupt request interrupt request bit 1 Interrupt requested 7 CAN bus off 0 No interrupt request x interrupt request bit 1 Interrupt requested Can be cleared to 0 by software but cannot be set to 1 Fig 2 2 2 Structure of Interrupt request register A Interrupt request register B b7 b6 b5 b4 b3 b2 bi bO ee Interrupt request register B IREQB Address 000316 O lala om wake
121. asked by the Standard identifier bit 2 acceptance mask register 1 Figure 3 5 42 form the acceptance filtering condition for incoming CAN frames They must be initialized with the identifier pattern of CAN frames to be received Standard identifier bit 3 Standard identifier bit 4 Standard identifier bit 5 Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 3 5 37 Structure of CAN acceptance code register 1 CAC1 CAN acceptance code register 2 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance code register 2 CAC2 Address 003546 B Name Function O Extended identifier bit 14 These bits except when masked by the acceptance mask register 2 Figure 3 5 43 form the acceptance filtering condition for incoming CAN frames They must be initialized with the identifier pattern of CAN frames to be received Extended identifier bit 15 Extended identifier bit 16 Extended identifier bit 17 Not used Undefined at read Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 3 5 38 Structure of CAN acceptance code register 2 CAC2 3 40 7630 Group User s Manual APPENDIX 3 5 List of registers CAN acceptan
122. ble wiring Besides separate this Vss pattern from other Vss patterns 3 4 5 Setup for I O ports Setup I O ports using hardware and software as follows lt Hardware gt e Connect a resistor of 100 Q or more to an I O port in series lt Software gt As for an input port read data several times by a program for checking whether input levels are equal or not As for an output port since the output data may reverse because of noise rewrite data to its data register at fixed periods Rewrite data to direction registers and pull up control registers only the product having it at fixed periods When a direction register is set for input port again at fixed periods a several nanosecond short pulse may be output from this port If this is undesirable connect a capacitor to this port to remove the noise pulse 3 20 An example of Vss patterns on the underside of a printed circuit board Oscillator wiring pattern example Separate the Vss line for oscillation from other Vss lines Fig 3 4 8 Vss pattern on the underside of an oscillator Direction register Port latch Fig 3 4 9 Setup for I O ports 7630 Group User s Manual APPENDIX 3 4 Countermeasures against noise 3 4 6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation This is e
123. buffer register 3 CTB3 Address 0043 g CAN receive buffer register 3 CRB3 Address 005346 B Name Function At reset 0 Extended identifier bit 6 Extended identifier bit 7 Extended identifier bit 8 Extended identifier bit 9 Extended identifier bit 10 Extended identifier bit 11 Extended identifier bit 12 Extended identifier bit 13 For CTB3 These bits represent part of the identifier field of a frame to be transmitted For CRB3 These bits represent part of the identifier field of a frame received Fig 2 4 21 Structure of CAN transmit receive buffer registers 3 CTB3 CRB3 CAN transmit receive buffer registers 4 b7 b6 b5 b4 b3 b2 b1 bo CAN transmit buffer register 4 CTB4 Address 0044 g CAN receive buffer register 4 CRB4 Address 005446 B Name Function r1 bit reserved bit 1 For CTB4 Set this bit to 0 must be sent dominant applicable for extended format only RTR bit 0 Data frame 1 Remote frame Extended identifier bit 0 Extended identifier bit 1 Extended identifier bit 2 Extended identifier bit 3 Extended identifier bit 4 Extended identifier bit 5 For CTB4 These bits represent part
124. can be programmed to be 1 to 8 Time Quanta by the CAN bus timing control register 1 and 2 see Fig 37 and Fig 38 The whole bit time has to consist of minimum 8 and maximum 25 Time Quanta The duration of one Time Quantum is the cycle time of fcang For example assuming 5 MHz p 0 one Time Quantum will be 200 ns long This allows the maximum transmission rate of 625 kb s to be reached assuming 8 Time Quanta per bit time Polarity control CAN status control Bus timing control Acceptance mask Acceptance code register registers register register register P3 CTX Protocol controller P3 CRX O Wake up logic Receive buffer 1 Acceptance filter o Q O Receive buffer 2 Transmit buffer CAN wake up Data bus Fig 33 Block diagram of CAN module 7630 Group User s Manual 1 33 HARDWARE CAN MODULE CAN transmit control register address 003046 CTRM Sleep control bit 0 CAN module in normal mode 1 CAN module in sleep mode Reset configuration control bit 0 CAN module in normal mode 1 CAN module in configuration mode plus reset when write Port double function control bit 0 P3 CTX serves as I O port 1 P3 CTX serves as CTX output port Transmit request bit 0 No transmission requested 1 Transmission requested write 0 has no effect Not used no operation 0 when read Transmit buffer control bit 0 CPU access possible 1 No CPU access w
125. can be sepa When the PWM mode is enabled timer 2 starts counting As soon rately selected to be either the pre divider output or timer 1 under flow Operation The timer counts down On a timer underflow the corresponding timer interrupt request bit will be set to 1 the contents of the cor responding timer latch will be reloaded to the counter and count ing continues as timer 2 underflows timer 2 stops and timer 3 starts counting If bit O is set timer 2 determines the low duration and the initial out put level is low Timer 3 determines the high duration If bit O is zero timer 2 determines the high duration and the initial output level is high In this case timer 3 determines the low duration Note Be sure to configure the P15 PWM pin as an output port before using PWM mode 7630 Group User s Manual 1 27 HARDWARE SERIAL I Os SERIAL I Os The serial I O section of 7630 group consists of one clock synchro nous and one asynchronous UART interface Clock Synchronous Serial I O SI O The clock synchronous interface allows full duplex communication based on 8 bit word length The transfer clock can be selected from an internal or external clock When an internal clock is selected a programmable clock divider allows eight different transmission SIOCON 0 Clock divider P23 Sroy O n P2 latch ZU Sync circuit speeds Refer to Block diagram of clock synchronous O f is internal syste
126. ce code register 3 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance code register 3 CAC3 Address 003646 B Name Function At reset O Extended identifier bit 6 2 Extended identifier bit 7 Extended identifier bit 8 These bits except when masked by the Extended identifier bit 9 acceptance mask register 3 Figure 3 5 44 form the acceptance filtering condition for incoming CAN frames They must be initialized with the identifier pattern of CAN frames to be received Extended identifier bit 10 Extended identifier bit 11 Extended identifier bit 12 Extended identifier bit 13 Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 3 5 39 Structure of CAN acceptance code register 3 CAC3 CAN acceptance code register 4 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance code register 4 CAC4 Address 003746 B Name Function 0 Not used Undefined at read Extended identifier bit 0 Extended identifier bit 1 These bits except when masked by the acceptance mask register 4 Figure 3 5 45 form the acceptance filtering condition for incoming CAN frames They must be initialised with the identifier pattern of CAN frames to be received Extended id
127. ceive does not affect the receive function related to the protocol controller block required to monitor the bus level while transmitting 2 4 9 Message transmission The module is equipped with one transmit buffer Similar to the receive section the architecture allows to transmit CAN frames on a one by one basis Both standard and extended frame formats of data and remote type are sup ported The programming sequence required to initiate a transmission comprises four steps each step shall be described in detail below 1 Check the module status i e the availability of the transmit buffer 2 Initialize the transmit buffer the buffer content defines the frame to be transmitted 3 Lock the transmit buffer hands the buffer control to the module and protects the buffer from accidental modifi cations by the CPU 4 Issue the transmit request triggers the module to start the transmission Once the transmission of a frame has been requested the module takes care about bus arbitration error handling and acknowledgement of the frame by other nodes The frame is considered transmitted successfully if The frame could win arbitration no errors were detected during transmission and the frame gained acknowledgement by another node on the bus In case of unsuccessful transmissions the module attempts to re transmit the frame until transmission can be fin ished successfully or the transmit request is withdrawn by user software re
128. cted active level caused by the STP or WIT instruction Any terminal of port P4 can be applied the key on wake up interrupt request will be set to 1 used to generate the key on wake up interrupt request The active Please refer to Fig 18 polarity can be selected by the key on wake up polarity control bit of key on wake up control bit r P4Dj PUP4 port PA KW L key on wake up interrupt port P4 I O circuit Fig 18 Block diagram of key on wake up circuit 7630 Group User s Manual 1 21 HARDWARE TIMERS TIMERS The 7630 group has five timers two 16 bit timers and three 8 bit tim ers All these timers will be described in detail below TXMs a 00 tt TXM 16 bit Timers Timers X and Y are 16 bit timers with multiple operating modes Please refer to Fig 19 TX latch 8 TXy latch 8 i O Count control P14 TXo Down O 44 BS direction Edge detector 00 10 TX interrupt request TX counter 8 H TX counter 8 Sign generator Edge detector P1 CNTR On TM TXMg 11 so qqr Med CNTRO interrupt request TY interrupt request oe P1 CNTR Rising edge detector TYM5 4 11 44 CNTR1 interrupt request gt Fig 19 Block di
129. ctors for each event successful transmission successful reception overrun error passive bus off allow efficient and rapid interrupt service routine operation Low power sleep mode To reduce power consumption the module can be set to sleep mode wake up from CAN traffic is supported by a dedicated interrupt source and vector Priority based message management support To cope with the problem of priority inversion the contents of the transmission buffer can be released in order to let another higher priority message to take over Baud rate prescaler This programmable divider provides a flexible baud rate selection up to 625kbps at f XIN 10MHz Programmable bit timing The durations of propagation time segment PTS phase buffer segments 1 PBS1 and 2 PBS2 are programmable Physical interface A two terminal CMOS compatible interface formed by ports P3 and P35 allows direct con nection to the most popular transceiver devices e g ISO 11898 ISO 11519 Refer to the block diagram in Figure 2 4 1 2 34 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module CAN module clock control CAN receive control register sleep control Baud rate prescaler Acceptance mask registers Jj C Acceptance code registers Bus timing control registers y message handling receive control logic P3 CTX Bn otocol controller status buffer co
130. d identifier bit 14 Extended identifier bit 15 Extended identifier bit 16 Extended identifier bit 17 For CTB2 These bits represent part of the identifier field of a frame to be transmitted For CRB2 These bits represent part of the identifier field of a frame received Not used When these bits are read out the values are 0 Don t write to 1 Fig 3 5 50 Structure of CAN transmit receive buffer registers 2 CTB2 CRB2 3 46 7630 Group User s Manual CAN transmit receive buffer registers 3 b7 b6 b5 b4 b3 b2 b1 bo CAN transmit buffer register 3 CTB3 Address 0043 g CAN receive buffer register 3 CRB3 Address 005346 APPENDIX 3 5 List of registers B Name Function At reset 0 Extended identifier bit 6 Extended identifier bit 7 Extended identifier bit 8 Extended identifier bit 9 Extended identifier bit 10 Extended identifier bit 11 Extended identifier bit 12 Extended identifier bit 13 For CTB3 These bits represent part of the identifier field of a frame to be transmitted For CRB3 These bits represent part of the identifier field of a frame received Fig 3 5 51 Structure of CAN transmit receive buffer reg
131. d value before enabling recep tion or transmission UART control register UCON Structure of UART control register The UART control register consists of four control bits bit O to bit 3 which allow to control reception and transmission UART status register USTS Structure of UART sta tus register The read only UART status register consists of 7 bits bit O to bit 6 which indicate the operating status of the UART function and various errors 7630 Group User s Manual 1 29 HARDWARE SERIAL I Os 3 Handshaking signals When used as transmitter the UART will recognize the clear to send signal via P2 UCTS terminal for handshaking When used as receiver it will issue a request to send signal through P2 URTS pin Clear to send input When used as a transmitter transmit enable bit set to 1 the UART starts transmission after recognizing L level on P27 UCTS After started the UART will continue to transmit regardless of the actual level of P2 UCTS or status of the transmit enable bit Request to send output The UART controls the P2 URTS output according to the following conditions Table 7 Output control conditions Condition P2 URTS Receive enable bit is set to 1 Reception completed during receive enable bit set to 1 Start bit falling edge detected Receive enable bit is set to 0 before recep tion started Hardware reset Receive initialization bit is set to 1
132. de Zero page SFR area CAN SFRs Not used Reserved ROM area Special page Interrupt vector area Reserved ROM area 7630 Group User s Manual 1 11 HARDWARE FUNCTIONAL DESCRIPTION SPECIAL FUNCTION REGISTERS SFR CPU mode register CPUM 0030 56 CAN transmit control register CTRM Not used 003146 CAN bus timing control register 1 CBTCON1 Interrupt request register A IREQA 00321 CAN bus timing control register 2 CBTCON2 Interrupt request register B IREQB 003346 CAN acceptance code register 0 CACO Interrupt request register C IREQC 003446 CAN acceptance code register 1 CAC1 Interrupt control register A ICONA 0035 CAN acceptance code register 2 CAC2 Interrupt control register B ICONB 003646 CAN acceptance code register 3 CAC3 Interrupt control register C ICONC 00371 CAN acceptance code register 4 CAC4 Port PO register PO 003846 CAN acceptance mask register O CAMO Port PO direction register POD 0039 CAN acceptance mask register 1 CAM1 Port P1 register P1 003A 6 CAN acceptance mask register 2 CAM2 Port P1 direction register P1D 003B 6 CAN acceptance mask register 3 CAM3 Port P2 register P2 003C s CAN acceptance mask register 4 CAM4 Port P2 direction register P2D 003D46 CAN receive control register CREC Port P3 register P3 003E 6 CAN transmit abort register CABORT Port P3 direction register P3D O03F s Reserved Port P4 register P4 004046 CAN transmit buffer register 0 CTBO
133. dex X mode T and Decimal mode D flags directly affect arithmetic operations they should be initialized in the beginning of a program 1 Carry flag C The C flag contains a carry or borrow generated by the arithmetic logic unit ALU immediately after an arithmetic operation It can also be changed by a shift or rotate instruction 2 Zero flag Z The Z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 and cleared if the result is anything other than 0 3 Interrupt disable flag I The flag disables all interrupts except for the interrupt generated by the BRK instruction Interrupts are disabled when the flag is 1 When an interrupt occurs this flag is automatically set to 1 to prevent other interrupts from interfering until the current interrupt is serviced 4 Decimal mode flag D The D flag determines whether additions and subtractions are executed in binary or decimal Binary arithmetic is executed when this flag is 0 decimal arithmetic is executed when it is 1 Decimal correction is automatic in decimal mode Only the ADC and SBC instructions can be used for decimal arithmetic HARDWARE FUNCTIONAL DESCRIPTION 5 Break flag B The B flag is used to indicate that the current interrupt was generated by the BRK instruction The BRK flag in the processor status register is always 0 When the BRK instruction is used to generate an interrupt
134. dinary mode gt Wait mode 1 Switing procedure from Ordinary mode to Stop mode Figure 2 9 4 shows the switching procedure to Stop mode Step 1 Set the Timer 1 interrupt and Timer 2 interrupt for stabilizing oscillation Set to the Timer 1 interrupt and Timer 2 interrupt disabled b7 b0 FII Jofof T Interrupt control register B ICONB Address 000616 Timer 1 interrupt enable bit Interrupt disabled Timer 2 interrupt enable bit Interrupt disabled Set the the Timer 1 and Timer 2 b7 b0 Timer 1 T1 Address 001616 Set the count data Note 1 b7 bo Timer 2 T2 Address 001716 Set the count data Note 1 Note 1 Set enough count data for stabilizing oscillation For the oscillation stabilizing time ask the oscillator maker for information Step 2 Set the external interrupt source used for return from the stop mode Note 2 Note 2 Refer to 2 2 Interrupt Step 3 Execute the STP instruction to switch procedure to the stop mode Fig 2 9 4 Switching procedure to Stop mode 2 Switching procedure from Ordinary mode to Wait mode Figure 2 9 5 shows the switching procedure to Wait mode Step 1 Set the interrupt source used for return from the wait mode Note Note Refer to 2 2 Interrupt Step 2 Execute the WIT instruction to switch procedure to the wait mode Fig 2 9 5 Switching procedure to Wait mode 7630 Group User s Manual 2 99 APPLICATION 2 10 Development support tools
135. duct data diagrams and charts represent information on products at the time of publication of these materials and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein O Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use O The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials O l these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of JAPAN and or the country of destination is prohibited Pleas
136. e of serial l O clock synchronous serial I O X These bits are not used in this application Please set these bits to 0 or 1 appropriately Initialization SIOCON Address 001316 lt X10010112 Set the Serial I O control register ICONC Address 000716 bit 4 lt 0 Set the Interrupt control register C P3 Address 000E16 bit 8 lt 1 P3D Address 000F 16 XXXX1XXX2 Set the CS signal output port H level output Ax gt P3 tAdcress 00066 bts lt 0 Set the CS signal output level to L gt REQ Address 000415 bi 4 0 Set the Serial I O interrupt request bit to 0 SIO Address 001216 lt Transmission data Write transmit data start to transmit 1 byte data IREQC Address 000416 bit 4 Check the completion of 1 byte data transmission Use any a counter to count the number of transmitted bytes Check whether the transmission of the target bytes has been completed Complete to transmit data Y P3 Address 000E16 bit 3 1 Return the CS signal output level to H when transmission of the target bytes has been completed Fig 2 5 17 Control procedure of clock synchronous serial I O Output of serial data 2 78 7630 Group User s Manual APPLICATION 2 5 Serial I O 2 Communication transmit receive using asynchronous serial I O
137. e addresses as TXy and TX Next read the low order byte which is read from the temporary regis ter This method assures the correct timer value can be read during the timer count operation Timer X count stop control Regardless of the actual operating mode timer X can be stopped by setting the timer X count stop bit bit 7 of the timer X mode register to qr 1 22 7630 Group User s Manual HARDWARE TIMERS Timer X mode register address 001E g TXM Timer X data write control bit 0 Data is written to latch and timer 1 Data is written to latch only Not used 0 when read do not write 1 Timer X mode bits b5 b4 O 0 Timer mode 0 1 Bi phase counter mode 1 0 Event counter mode 1 1 Pulse width measurement mode CNTR polarity selection bit 0 For event counter mode rising edge active For interrupt request falling edge active For pulse width measurement mode measure H period For event counter mode falling edge active For interrupt request rising edge active For pulse width measurement mode measure L period Timer X stop control bit 0 Timer counting 1 Timer stopped Fig 20 Structure of Timer X mode register address as TY Next write the high order byte When this is fin ished the data is placed in the timer Y high order reload latch and the low order byte is transferred from its temporary register to the timer Y low order reload latch Timer Y Timer
138. e contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein REVISION DESCRIPTION LIST 7630 GROUP USER S MANUAL REVISION MODIFICATIONS First Edition CAN controller is replaced by CAN module in whole documents Schematics 1 is modified Schematics 8 and 11 are corrected Replaced PUPDJ with PUPAJ Replaced URXD with SOUT Replaced URXD with SIN Fig 41 is modified Replaced FFFBH with FFFB16 Replaced FFFAH with FFFA16 Values changed lih 35 113 to 20 200 and lih 122 70 to 200 20 typical values are removed 1 1 Preface This user s manual describes Mitsubishi s CMOS 8 bit microcomputers 7630 Group After reading this manual the user should have a through knowledge of the functions and features of the 7630 Group and should be able to fully utilize the product The manual starts with specifications and ends with application examples For details of software refer to the SERIES MELPS 7600 lt SOFTWARE gt USER S MANUAL For details of development support tools refer to the DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS data book BEFORE USING THIS USER S MANUAL This user s manual consists of the following three chapters Refer to the chapter appropriate to your conditions such as hardware design or software developmen
139. e data register port latch of an I O port is modified with the bit managing instruction the value of the unspecified bit may be changed Reason The bit managing instructions are read modify write form instructions for reading and writing data by a byte unit Accordingly when these instructions are executed on a bit of the port latch of an I O port the following is executed to all bits of the data register As for a bit which is set for an input port The pin state is read in the CPU and is written to this bit after bit managing As for a bit which is set for an output port The bit value is read in the CPU and is written to this bit after bit managing Note the following Even when a port which is set as an output port is changed for an input port its data register holds the output data As for a bit of which is set for an input port its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its data register contents bit managing instructions SEB and CLB instructions 3 3 5 Notes on programming 1 Initialization of processor status register Flags which affect program execution must be initialized after a reset In particular it is essential to initialize the T Initializing of flags and D flags because they have an important AS Reason After a reset the contents of the processor status register PS are undefined except for the flag which is
140. e high order counter WDH 7 bit counter is set to 7F16 The low order counter WDL 4 bit counter is set to F16 The time out period of the watchdog timer is n cycles of the internal system clock 6 n 524288 when the Upper byte count source selection bit is 0 e n 32768 when the Upper byte count source selection bit is 1 On a watchdog timer underflow the watchdog timer interrupt non maskable occurs Set the watchdog timer counters to the default values prevent from underflow by writing to this register in main processing Once the watchdog timer has been started it cannot be stopped except by reset Note 2 Once the Stop instruction is disabled it cannot be enabled again except by reset Fig 3 5 31 Structure of Watchdog timer register Polarity control register b7 b6 b5 b4 b3 b2 bi bO INNEN Polarity control register PCON Address 002F 16 B name Funcion aesa Key on wake up polarity 0 Low level active P4 pull up control bit 1 High level active P4 pull down CAN module dominant level 0 Low level dominant P32 pull up i bit Note 1 High level dominant P32 pull down el Ed lolx Not used undefined when read 2 olx lolx x Note The selected dominant level also controls the polarity of the pull transistor enabled by the P32 pull up down transistor control bit bit 2 of the Port P3 pull up control register the transistor pulling t
141. e to the stop wait mode Fig 2 2 13 Setting method for registers related to key on wake up interrupt 2 7630 Group User s Manual 2 17 APPLICATION 2 3 Timers 2 3 Timers 2 3 1 Memory map of timer 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001Fie Fig 2 3 1 Memory map of timer related registers 2 18 7630 Group User s Manual APPLICATION 2 3 Timers 2 3 2 Related registers Timer 1 Timer 3 b7 b6 b5 b4 b3 b2 b1 bO Timer 1 T1 Address 001616 Timer 3 T3 Address 001816 1 O The timer value is written to timer and latch at the same time To get the actual Timer 1 or Timer 3 value read out the corresponding timer register Fig 2 3 2 Structure of Timer 1 Timer 3 Timer 2 b7 b6 b5 b4 b3 b2 b1 bO BERR Timer 2 T2 Address 001716 Hl The timer value is written to Timer 2 and latch at the same time or to the latch only Note To get the actual Timer 2 value read out the Timer 2 register Note Depinding on the Timer 2 write control bit bit 2 of the Timer 123 mode register address 001916 Fig 2 3 3 Structure of Timer 2 7630 Group User s Manual 2 19 APPLICATION 2 3 Timers Timer 123 mode register b7 b6 b5 b4 b3 b2 bi bO IINIIIIJ Timer 123 mode register T123M Address 001916 fe name Function fese PWM polarity selection bit 0 Start on H level output 1 Start on L
142. ed ADC running middle speed mode f Xiy 8MHz Vec 5V output transistors off CAN module running ADC running middle speed mode wait mode f Xjy 8MHz Voc 5V output transis tors off CAN module stopped ADC stopped stop mode f X y OMHz Vec 5V Ta 25 C stop mode f X y OMHz Voc 5V Ta 85 C 7630 Group User s Manual HARDWARE A D CONVERTER CHARACTERISTICS Table 12 A D converter characteristics Voc 4 0 to 5 5 V Vss AVgg OV T 40to85 C unless otherwise noted Limits Parameter Test conditions Resolution Absolute accuracy high speed mode Conversion time middle speed mode Reference input voltage Reference input current Voc Vrer 5 12 V Ladder resistor value Analog input current Vi Vss to Voc 7630 Group User s Manual 1 47 HARDWARE TIMING REQUIREMENTS Table 13 Timing requirements tw RESET Parameter Reset input L pulse width Vec 4 0 to 5 5 V Vss AVgg 0 V T 40 to 85 C Limits typ to Xin External clock input cycle time twH Xin External clock input H pulse width twi Xin External clock input L pulse width tc CNTR CNTRo CNTR input cycle time except bi phase counter mode CNTR input cycle time bi phase counter mode twa CNTR CNTRo CNTR input H pulse width excep
143. egister 2 CRB2 CAN receive buffer register 3 CRB3 CAN receive buffer register 4 CRB4 CAN receive buffer register 5 CRB5 CAN receive buffer register 6 CRB6 Receive buffer registers CAN receive buffer register 7 CRB7 double buffer concept CAN receive buffer register 8 CRB8 CAN receive buffer register 9 CRB9 CAN receive buffer register A CRBA CAN receive buffer register B CRBB CAN receive buffer register C CRBC CAN receive buffer register D CRBD Fig 2 4 2 Memory map of CAN related registers 2 36 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module 2 4 3 Related registers This section comprises the description of special function registers allocated to the CAN module CAN transmit control register b7 b6 b5 b4 b3 b2 bi bO CAN transmit control register CTRM Address 0030 g B Name Function At reset 0 Sleep control bit CAN module in normal mode 0 CAN module in sleep mode CAN module in normal mode Reset configuration control bit CAN module in configuration mode plus reset when write P3 CTX serves as l O port 1 P3 CTX serves as CTX output port RO No transmission requested R1 Transmission requested WO No operation W1 Request transmission Port double function control bit Transmit request bit Reserved 0 when read
144. em porary registers assigned to the same addresses as TY At the same time the contents of TY latches will be reloaded to the counters and counting continues The active edge of input signal also causes the CNTR interrupt request bit to be set to 1 The measurement result may be obtained by reading timer Y during interrupt service 6 H L pulse width measurement mode This mode is available with timer Y only Count source The count source is the output of the timer Y s clock divider Operation This mode measures both the H and L periods of a signal input to P15 CNTR pin continuously On detection of any edge rising or falling of input signal to P15 CNTR pin the contents of timer Y counters are stored to temporary registers which are assigned to the same addresses as timer Y At the same time the contents of timer Y latches are reloaded to the counters and counting contin ues The detection of an edge causes the CNTR1 interrupt request bit to be set to 1 as well The result of measurement may be obtained by reading timer Y during interrupt service This read access will address the temporary registers On a timer underflow the timer Y interrupt request bit will be set to 1 the contents of timer Y latches will be transferred to the counters and counting continues 7630 Group User s Manual 1 25 HARDWARE TIMERS TIMER 1 TIMER 2 TIMER 3 Timers 1 to 3 are 8 bit timers with 8 bit reload
145. emory map of oscillation circuit related registers 2 97 2 9 2 Related registers miosina A A ces 2 98 2 9 3 Application examples ooococicioionocociciciciciciccnnncnnonononononnnnononinnon no nono nono no ronca tenentes 2 99 2 10 Development support tools M37630T RFS eene 2 100 2 11 Built in PROM version Lo iii 2 101 2 11 1 ers WISUBEETSETRETI MOREM 2 101 2 11 2 Pin configuration csscccssccsssessescssessssessseesssecssscessacessscsssessaeessacessisesscsssnectaceesaces 2 102 2 11 3 Programming ON 2 103 A A rannt 2 104 3 1 Electrical CharacteriStiCS cscccssssssessscsssssssssssssssesssacesessssssssssseseeseesesavavenevessseessssesearaees 3 2 3 1 1 Absolute maximum Ta Sucina ita 3 2 3 1 2 Recommended operating CONO NS ereccion erre ediles 3 3 3 1 3 Electrical characteristics A ec aS Scand A 3 4 3 1 4 DENESULINSEESUEEq Gems 3 5 3 1 5 liming requirements 5 ct te tinte stri iii ia 3 5 3 1 6 ESLEHPESIUIDHDUCA TNT LEM 3 6 3 2 Standard characteristics scaena do ie bae i n Od etu coda EP HL eda d te a in dms 3 8 3 2 1 Power source current standard characteristics 3 8 7630 GROUP USER S MANUAL Table of contents 3 2 2 Dutput current standard characteristics cssccscsssecsssessssseecsssescssseessssecesssessseceesneen 3 10 3 2 3 Input current standard CHalacteristice ondaa iii 3 11 3 2 4 A D conversion standard CNaracteriStiCS ccccccsssessssessssessssessseecssseessscsse
146. en RAM in page 1 is used as the stack area The Stack Page Selection Bit is located in the SFR area in the zero page Note that the initial value of the Stack Page Selection Bit var ies with each microcomputer type Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed The operations of pushing register contents onto the stack and popping them from the stack are shown in Fig 7 Program counter PC The program counter is a 16 bit counter consisting of two 8 bit regis ters PCH and PCL It is used to indicate the address of the next in struction to be executed Accumulator Index Register X Index Register Y Stack Pointer Program Counter Processor Status Register PS Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Fig 5 740 Family CPU register structure 7630 Groop User s Manual 1 7 HARDWARE FUNCTIONAL DESCRIPTION On going Routine Interrupt request presas Note 1 EM MO PC Sole Store Return Address M S PCH on Stack Note 2 M S PCH l JEPE Store Return Address S S 1 on Stack Note 2 WIS PC M S PCL CK CEU S PS S S 1 EE o I I Ie A aa S Store Contents of Processor Status Register on Stack 1 S S Interrupt Service
147. enable bit Parity disabled Word length selection bits 8 bits UART control register Address 002216 b7 bO UCON fo 1 0 Transmit enable bit Transmit disabled Set this bit to 1 at starting communication Receive enable bit Receive disabled Transmission initialization bit Initialize the transmit enable bit and transmit status register flags Receive initialization bit No action UART baud rate generator Address 002116 b7 The value p is decided by the Clock divider selection bits bit 1 and bit 2 of the UART mode register address 002016 Refer to Table 2 5 2 Set 9 1 Transfer bit rate X 16 X p UART status register Address 002316 b7 bo I Transmission register empty flag This flag is set to 1 at transmit shift completed Check a completion of transmitting 1 word data with this flag Transmission buffer empty flag This flag is set to 1 at transfer data from the Transmit buffer register to the Transmit shift register Check whether the next transmission data is writable to the Transmit buffer register with this flag Fig 2 5 20 Setting of related registers on transmitting side Communication using UART 7630 Group User s Manual 2 81 APPLICATION 2 5 Serial I O Receiving side CPU mode register Address 000016 bO CPUM ppg Internal system clock selection bit y f XIN divided by 2 high speed mode UART mode register Address
148. ent larger than the tolerance of current value flows Reason In the system using a microcomputer there are signal lines for controlling motors LEDs and thermal heads or others When a large current flows through those signal lines strong noise occurs because of mutual inductance Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently Also do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise Reason Signal lines where potential levels change frequently such as the CNTR pin signal line may affect other lines at signal rising edge or falling edge If such lines cross over a clock line clock waveforms may be deformed which causes a microcomputer failure or a program runaway Mutual inductance Large current Fig 3 4 6 Wiring for a large current signal line Fig 3 4 7 Wiring to a signal line where potential levels change frequently 7630 Group User s Manual 3 19 APPENDIX 3 4 Countermeasures against noise 3 Oscillator protection using Vss pattern As for a two sided printed circuit board print a Vss pattern on the underside soldering side of the position on the component side where an oscillator is mounted Connect the Vss pattern to the microcomputer Vss pin with the shortest possi
149. entifier bit 2 Extended identifier bit 3 Extended identifier bit 4 Extended identifier bit 5 Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 3 5 40 Structure of CAN acceptance code register 4 CAC4 7630 Group User s Manual 3 41 APPENDIX 3 5 List of registers CAN acceptance mask register 0 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance mask register 0 CAMO Address 003846 B Name Function At reset These bits mask the corresponding bits 2 of the acceptance code register 0 Figure f 3 5 36 from the acceptance filtering 0 Standard identifier mask bi Standard identifier mask bi 0 Mask identifier bit don t care 1 Compare identifier bit Standard identifier mask bi Standard identifier mask bi Standard identifier mask bit 10 These bits must be set to 0 Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 3 5 41 Structure of CAN acceptance mask register 0 CAMO CAN acceptance mask register 1 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance mask register 1 CAM1 Address 003946 B Name Function 0 These bits must be set to 0
150. entire 29 bit identifier scale extended format however 11 bit identifiers standard format can be handled as well The registers shown in Figure 2 4 30 can be modified in configuration mode refer to section 2 4 5 only name 7 O Address Acceptance code CACO rT I CSD CSIDg CSIDg CSID CSIDg 003316 Select the bit pattern of identifiers which should pass acceptance filtering 0 Mask identifier bit 1 Compare identifier bit with acceptance code register bit Shaded bits of CAMi must be cleared Fig 2 4 30 Structure of acceptance mask code registers 2 Operation Acceptance filtering starts after detecting the start of frame of a CAN message The content of the accept ance mask registers define which identifier bits have to be subjected to comparison with the corresponding bits of the acceptance code registers If the acceptance filter judges an incoming frame relevant the frame is depending on the availability of a receive buffer either stored in a receive buffer or a CAN overrun interrupt COVR is issued by setting the corresponding interrupt request bit For further details on the receive buffer system and the overrun interrupt refer to sections 2 4 8 and 2 4 11 3 Schematic of acceptance filter The acceptance filter mechanism see Figure 2 4 31 comprises one gate which compares the acceptance code register bit with the corresponding identifier bit of the frame being received and one gate which tests the rel
151. er registers 3 2 46 Fig 2 4 22 Structure of CAN transmit receive buffer registers 4 2 46 Fig 2 4 23 Structure of CAN transmit receive buffer registers 5 2 47 Fig 2 4 24 Structure of CAN transmit receive buffer registers 6 to D 2 47 Fig 2 4 25 Transitions between operational modes see 2 48 Fig 2 4 26 Transitions among module sub modes sss 2 49 Fig 2 4 27 Segmentation of bit time sss 2 50 Fig 2 4 28 Module initialization Sequence sssseeen 2 52 Fig 2 4 29 Module reset sequence sssssssssssssssseseeeeeeennn een 2 53 Fig 2 4 30 Btructure of acceptance mask code registers ssssssses 2 54 Fig 2 4 31 Acceptance filter logic ntn ttes 2 55 Fig 2 4 32 Receive buffer handling caricia 2 56 Fig 2 4 33 Flowchart of the receve process Jo cssecscssssscssssssssssccsssecsssssessssecssseesssscessnseesseess 2 57 Fig 2 4 34 Receive sequence TIMING espiga Dri darlo 2 58 Fig 2 4 35 Receive sequense timing overrun condition sssssesee 2 59 Fig 2 4 36 Transmit buffer organization sssssssssssseeeenn 2 61 Fig 2 4 37 Transmit sequence timing arbitration win 2 62 Fig 2 4 38 Flowchart of transmit process apendicitis toss 2 64 Fig 2 4 39 Error state diagram 2 65 Fig 2 5 1 Memory map of serial VO related registers ss
152. ernal clock Interrupt request register C Address 000416 b7 bO me ME ej Serial I O interrupt request bit Use this bit to check if transmission of 1 byte is complete 1 Transmit complete Interrupt control register C Address 000716 b7 bO icono M of I Serial I O interrupt enable bit Interrupt disabled Port P3 Address 000E 16 b7 bO 3 EDENE Set to 0 before transmission starts TM P3 direction register Address 000F16 P33 Output mode Fig 2 5 15 Setting of serial I O related registers Output of serial data 2 76 7630 Group User s Manual APPLICATION 2 5 Serial I O Serial I O shift register Address 001216 b7 bO Write data to be transmitted Check whether transmission of the previous data has been completed before writing data bit 4 of the Interrupt request register C is set to 1 Fig 2 5 16 Setting of serial I O transmission data Output of serial data 7630 Group User s Manual 2 77 APPLICATION 2 5 Serial I O Control procedure When the registers are set as shown in Figure 2 5 15 the Serial I O transmits 1 byte data simply by writing data to the Serial I O shift register Thus after setting the CS signal to L write the transmission data to the Serial I O shift register on 1 byte base and return the CS signal to H when the desired number of bytes have been transmitted Figure 2 5 17 shows a control procedur
153. ers 1 15 Fig 14 Structure of Polarity control register 1 15 Fig 15 Interrupt control reine aii 1 19 Fig 16 Structure of Interrupt polarity selection register 1 19 Fig 17 Structure of Interrupt request and control registers A B and C 1 20 Fig 18 Block diagram of key on wake up CirCUit 0 2 eee cececeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaees 1 21 Fig 19 Block diagram o and Fig 20 Fig 21 Structure of Timer Y mode register 1 24 Fig 22 Timer X biphase counter mode operation 1 25 Fig 23 Block diagram of timers 1 to 3 1 26 Fig 24 Timer 123 mode register configulation sssssssss 1 27 Fig 25 Block diagram of clock syncronous SV O e 1 28 Fig 26 Timing of clock syncronous SI O function 1 28 Fig 27 Structure of Serial 1 0 control register enrete 1 29 Fig 28 Block diagram of UART ccec ttc 1 30 Fig 29 Structure of UART mode register 1 31 Fig 30 Structure of UART control register 1 31 Fig 31 Structure of UART status register teen 1 32 Fig 32 Bit time of CAN Module esses 1 33 Fig 33 Block diagram of CAN module 1 83 Fig 34 Structure of CAN transmit Control TEGISTOT ccscsssessssssssssecsesescesssescsseseessneseeees 1 34 Fig 35 Structure of CAN receive control register 1 34 Fig 36 Structure of CAN transmit abort request register 1 35
154. ess 000016 lt 00000X002 y f XiN divided by 2 high speed mode TXM Address 001E16 101100002 Timer X Pulse width measurement mode Count H level width of pulse P1D Address 000B16 lt XXX0XX002 input from ENTRO pint Stop counting TYM Address 001F16 XXXXXX012 Timer X count source o divided by 16 TXL Address 001A16 FF 16 TXH Address 001B16 FF 16 ICONB Address 000616 bit 1 1 Timer X interrupt Enabled ICONB Address 000616 bit 6 1 CNTRo interrupt Enabled IREQB Address 000316 bit 1 0 Set the Timer X interrupt request bit to 0 IREQB Address 000316 bit 6 0 Set the CNTRo interrupt request bit to 0 Initialize the count value of the Timer X TXM Address 001Et6 bit 7 Timer X Start counting CLI Interrupts Enabled Timer X interrupt processing routine Note 1 Error occurs Note 1 The Timer X interrupt occurs at a level except a measurement level when it is L level in this application example Process by software in accordance with the necessity like as a processing for errors is per formed only at a measurement level the CNTRo input level is judged by reading a content of the Port P14 register Fig 2 3 17 Control procedure Measurement of pulse width 1 2 32 7630 Group User s Manual APPLICATION 2 3 Timers CNTRo interrupt process
155. ess from user side and CAN module side Receiving new message Set receive status bit Acceptance filter passed success fully Buffer available yes Y Set CAN over run interrupt request bit Receive Store message to receive buffer Y Set CAN successful Y receive interrupt request bit Finish frame reception Y Receive buffer control bit 0 Yes Y Switch buffer from back ground to foreground User software Write 1 Y Set receive buffer control bit Write 0 a HN Y Clear receive status bit Await CSR interrupt or poll receive buffer C control bit Y Read process receive buffer gt lt The two actions in the Yes branch switching buffer set receive buffer full flag will be postponed until the receive buffer full flag has been cleared by user s w Y The module monitors this bit continuously Clear receive buffer Write UM control bit crec P Y Receive buffer CREC N control bit 1 Read a CSR interrupt request bit 1 sk xk If both buffers are already occupied before the CSR interrupt acceptence CREC O will be 1 and the CSR interrupt has not been requested again request bit 0 Under this condition both buffer
156. ested Can be cleared to 0 by software but cannot be set to 1 Fig 3 5 3 Structure of Interrupt request register B Interrupt request register C b7 b6 b5 b4 b3 b2 bi bO BIIIIIII Interrupt request register C IREQC Address 000416 e Name Funetion atrse r w UART receive complete receive de No interrupt request x buffer full interrupt request bit Interrupt requested UART transmit complete transmit No interrupt request register empty interrupt request bit Interrupt requested UART transmit buffer empty No interrupt request interrupt request bit Interrupt requested RO cu e UART receive error No interrupt request interrupt request bit Interrupt requested No interrupt request Serial 1 O interrupt request bit Interrupt requested 5 AD conversion complete No interrupt request interrupt request bit Interrupt requested Key on wake up No interrupt request interrupt request bit Interrupt requested Not used 0 when read O Can be cleared to 0 by software but cannot be set to 1 Fig 3 5 4 Structure of Interrupt request register C 7630 Group User s Manual 3 23 APPENDIX 3 5 List of registers Interrupt control register A b7 b6 b5 b4 b3 b2 bi bO ITITI E Interrupt control register A ICONA Address 000516 B mamo Funcion JAtrest R W Not used 0 when read e fox External inter
157. evance of this bit for the acceptance filter process When all acceptance bits are true the module rates the frame relevant and attempts to store it to a receive buffer 2 54 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module Acceptance mask bit 0 Acceptance code bit 0 Identifier bit O Acceptance bit 0 Acceptance mask bit N Acceptance code bit N Identifier bit N Acceptance bit N Acceptance mask bit 28 Acceptance code bit 28 Identifier bit 28 N 1 to 27 Acceptance bit 28 ld match 29 B Fig 2 4 31 Acceptance filter logic 2 4 8 Message reception The module is equipped with two physical receive buffers This double buffer architecture allows simultaneous CPU processing of a previously received frame and reception storage of a new frame by the module To simplify the software handling both buffers are memory mapped to the same address range 005046 to 005D g The mod ule s internal receive logic controls access to the buffers so that one buffer later on called foreground buffer can be read out by the CPU while the other buffer background buffer can be written to by the module The user is able to switch back and forth between both buffers by one control bit however the individual buffers can not be addressed directly This architecture allows sequential handling of the incoming frames on an one by one basis
158. fer to section 2 4 10 In case of an arbi tration loss the module transits to sub mode receiving refer to section 2 4 8 and Figure 2 4 26 The programming sequence and functionality is explained below and by the flow charts in Figure 2 4 38 1 Check for availability of the transmit buffer Before the transmit buffer can be initialized its availability must be checked the transmit buffer control bit CTRM 5 must be 0 indicating the availability of the buffer and completion of the previous transmission The user software can now initialize the transmit buffer 2 Initialize the transmit buffer In the user software the identifier standard or extended the frame type data or remote frame length code data bytes in case of a data frame have to be written to the transmit buffer Figures 2 4 18 to 2 4 24 Only the transmit buffer registers relevant for the specific CAN frame need to be initialized e g if only stand ard CAN frames are concerned the transmit buffer registers CTB2 and CTB3 can be ignored If the transmit buffer has been used for a previous transmission the contents of the buffer are retained there fore only the transmit buffer contents which need to be changed versus the previous frame have to be initial ized Figure 2 4 36 shows the transmit buffer register organisation 2 60 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module Name Offset CTB6 Data byte 0 004616 CTB7 Data byte
159. gisters relat ing to functions such as I O ports and timers RAM RAM is used for data storage and for stack area of subroutine calls and interrupts ROM ROM is used for storing user s program code as well as the interrupt vector area RAM area RAM size byte Address XXXXi6 192 011F 46 256 015Fi 384 01DFi 512 025F 16 640 02DF i 768 035F 46 896 03DF 6 1024 045F46 1536 06DF 6 2048 085F 16 ROM area User RAM ROM size byte Address YYYYi6 Address 22ZZZ 6 4096 F00016 F08016 8192 E000 E0801 12288 D0004 D08046 16384 C00046 C0801 20480 B0001 B080 6 24576 A000 6 A080 6 28672 900056 908046 32768 800016 808016 36864 700046 708046 40960 600046 608046 45056 500046 508046 49152 400046 408046 53248 300046 308046 57344 200046 208046 61440 100046 108046 Fig 8 Memory map diagram Interrupt Vector Area The interrupt vector area is for storing jump destination addresses used at reset or when an interrupt is generated Zero Page This area can be accessed most efficiently by means of the zero page addressing mode Special Page This area can be accessed most efficiently by means of the special page addressing mo
160. he address indicated by the stack pointer and decrements the contents of the stack pointer by 1 Increments the contents of the stack pointer by 1 and restores the accumulator from the memory at the address indicated by the stack pointer Ses 1 Increments the contents of stack pointer by 1 PS M S and restores the processor status register from the memory at the address indicated by the stack pointer Shifts the contents of the memory or accumu lator to the left by one bit The high order bit is shifted into the carry flag and the carry flag is shifted into the low order bit Shifts the contents of the memory or accumu lator to the right by one bit The low order bit is shifted into the carry flag and the carry flag is shifted into the high order bit Rotates the contents of memory to the right by 4 bits SeSs 1 Returns from an interrupt routine to the main 40 PS M S routine Sses 1 PCL M S Ses 1 PCH M S SesS 1 Returns from a subroutine to the main routine PCL M S ne Ses 1 PCH M S PC PC 1 SBC WhenT 0 __ Subtracts the contents of memory and Note 1 AC A M C complement of carry flag from the contents of Note 8 accumulator The results are stored into the When T 1 E accumulator M X E MX M C Subtracts contents of complement of carry flag and contents of the memory indicated by the addressing mode
161. he windowed EPROM are erased through an ultraviolet light source of the wavelength 2537 Angstrom At least 15 W sec cm are required to erase EPROM contents 7630 Group User s Manual 2 103 APPLICATION 2 11 Built in PROM version 2 11 4 Notes on use The notes on using the built in PROM version are shown below 1 All built in PROM version products E Precautions at write operation Be careful not to apply an overvoltage to pins because a high voltage is used for a write operation Exercise special care when turning on the power supply O For writing the contents of the PROM use a dedicated programming adapter This permits using a general purpose PROM programmer for writing data For details of dedicated programming adapters refer to 2 11 3 Programming adapter E Precautions at read operation When reading the contents of the PROM use a dedicated programming adapter so that reading can be performed by a general purpose PROM programmer For details of dedicated programming adapters refer to 2 11 3 Programming adapter 2 One Time PROM version MW Precautions before use O The PROM of the One Time PROM version is not tested or screened in the assembly Programming with PROM programmer process and the following processes To U ensure proper operation after programming the procedure shown in Figure 2 11 2 is Screening Caution Leave at 150 C for 40 hours recommended to verify programming Ver
162. hen UART is selected UART receive error FFD34 FFD2 6 When UART reception error occurs Valid when UART is selected Serial I O FFD 1i FFDOi At completion of serial I O data transmit and receive Valid when serial I O is selected A D conversion FFCF 1 FFCE46 At completion of A D conversion Key on wake up FFCD46 At detection of either rising or falling edge of P4 input External Interrupt active edge selectable BRK instruction FFCBi FFCAi At BRK instruction execution Notes 1 Vector addresses contain interrupt jump destination address 2 Reset function in the same way as an interrupt with the highest priority Non maskable 7630 Group User s Manual HARDWARE INTERRUPTS Interrupt request bit Interrupt enable bit Interrupt disable flag BRK instruction gt Interrupt request Reset Fig 15 Interrupt control For the external interrupts INTO and INT1 the active edge causing the interrupt request can be selected by the INTO and INT1 interrupt edge selection bits of the interrupt polarity selection register IPOL please refer to Fig 16 below Interrupt polarity selection register Address 002D g IPOL Not used returns to 0 when read do not write 1 in this bit INT interrupt edge selection bit INT interrupt edge selection bit Not used returns to 0 when read do not write 1 in these b
163. how the input current standard characteristics Port P4o liL characteristic at pull up Pins with same characteristic PO P12 P17 P2 P30 P34 P4 0 16 0 14 0 12 0 10 VCC 5 0V Ta 25 0 08 0 06 Vcc 4 0V Ta 25 C 0 04 Supply current liL mA 0 02 2 0 3 0 4 0 Supply voltage VI V Fig 3 2 7 Pull up transistor standard characteristics liL VI Port P4o liL characteristic at pull down Pins with same characteristic P4 0 16 0 14 0 12 Vcc 5 5V Ta 25 C 0 10 0 08 Vcc 5 0V Ta 25 C 0 06 Vcc 4 0V Ta 25 C lt E c o Lum _ 3 o gt o o 3 n 0 04 2 0 3 0 4 0 Supply voltage VI V Fig 3 2 8 Pull down transistor standard characteristics liL Vi 7630 Group User s Manual 3 11 APPENDIX 3 2 Standard characteristics 3 2 4 A D conversion standard characteristics Figure 3 2 9 shows the A D conversion standard characteristics The lower side line on the graph indicates the absolute precision error ERROR It represents the deviation from the ideal value For example the conversion of output code from 0 to 1 occurs ideally at the point of ANo 10 mV but the measured value is 2 mV Accordingly the measured point of conversion is represented as 10 2 12 mV The upper side line on the graph indicates the width of input voltages 1 LSB WIDTH equivalent to output codes For example the mea
164. ier bit Extended identifier mask bit 3 These bits mask the corresponding bits of the acceptance code register 4 Figure 3 5 40 from the acceptance filtering Extended identifier mask bit 4 Extended identifier mask bit 5 Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 3 5 45 Structure of CAN acceptance mask register 4 CAM4 CAN receive control register b7 b6 b5 b4 b3 b2 bi bO CAN receive control register CREC Address 003D 4g B Name Function Receive buffer empty undefined Receive buffer full Release clear receive buffer No operation CAN module idle or transmitting CAN module receiving Receive buffer control bit Receive status bit When these bits are read out the values are 0 Don t write to 1 Reserved 0 Auto receive enabled 1 Auto receive disabled Auto receive disable bit When these bits are read out the values are 0 Don t write to 1 Reserved Note 1 RO R1 denote read access WO W1 denote write access Note 2 Suppresses reception of self initiated transmitted frames for details see section 2 4 8 5 Fig 3 5 46 Structure of CAN receive control register CREC 3 44 7630 Group User s Manual APPEND
165. ification with PROM programmer Functional check in target device Caution The screening temperature is far higher than the storage temperature Never expose to 150 C exceeding 100 hours Fig 2 11 2 Programming and testing of One Time PROM version 2 104 7630 Group User s Manual APPLICATION 2 11 Built in PROM version 3 Built in EPROM version E Precautions on erasing O Sunlight and fluorescent light include light that may erase the information written in the built in PROM When using the built in EPROM version in the read mode be sure to cover the transparent glass portion with a seal O This seal to cover the transparent glass portion is prepared on our side Be careful that the seal does not touch the microcomputer lead wires when covering the glass portion with the seal because this seal is made of metal aluminum O Before erasing data clean the transparent glass If any finger stain or seal adhesive is stuck to the transparent glass this prevents ultraviolet rays passing thereby affecting the erase characteristic adversely E Precautions on mounting M37630E4FS Package type 80DO has the reserved pins It uses those pins at emulator MCU mode Please open these pins described in 2 11 2 Pin configuration as reserved 7630 Group User s Manual 2 105 CHAPTER 3 APPENDIX 3 1 Electrical characteristics 3 2 Standard characteris
166. ig 2 1 3 Structure of Port Pi direction register i 0 1 2 8 4 2 3 Fig 2 1 4 Structure of Port Pi pull up register 1 0 2 2 4 Fig 2 1 5 Structure of Port P1 pull up register sseseees 2 4 Fig 2 1 6 Structure of Port P3 pull up control register 2 5 Fig 2 1 7 Structure of Port P4 pull up down control register 2 5 Fig 2 1 8 Structure of Porarity control register 2 6 Fig 2 1 9 External circuit example applying overvoltage to digital inputs Fig 2 2 1 Memory map of interrupt related registers sssen 2 9 Fig 2 2 2 Structure of Interrupt request register A 2 10 Fig 2 2 3 Structure of Interrupt request register Blocca 2 10 Fig 2 2 4 Structure of Interrupt request register C 2 11 Fig 2 2 5 Structure of Interrupt control register A sssseee 2 11 Fig 2 2 6 Structure of Interrupt control register B 2 12 Fig 2 2 7 Structure of Interrupt control register C 2 12 Fig 2 2 8 Structure of Interrupt polarity selection register 2 13 Fig 2 2 9 Structure of Polarity control register sss 2 13 Fig 2 2 10 mtemupt setting method C 1 L udceceveut qua huit tire tkt d as 2 14 Fig 2 2 11 Interrupt setting method ellas 2 15 Fig 2 2 12 Betting method for registers related to key on wake up interrupt 1 2 16 Fig 2 2 13 Setting method for registers related to key on wake up interrupt 2
167. ilt in EPROM version is a programmable microcomputer with a window and can perform write erase and rewrite operations The built in PROM version has the EPROM mode for writing to the built in PROM in addition to the same functions as those of the mask ROM version For an outline of performance and a functional block diagram of the built in PROM version refer to 1 Hardware 2 11 1 Product expansion The 7630 group supports the built in PROM versions shown in Table 2 11 1 Table 2 11 1 7630 group s built in PROM version supporting products e is I O Ports Package Remarks M37630E4T XXXFP One Time PROM version M37630E4FP 16252 512 i e AMPGN Tone Time PROM version blank M37630E4FS put pori l aopg EPROM version 7630 Group User s Manual 2 101 APPLICATION 2 11 Built in PROM version 2 11 2 Pin configuration The pin configurations of the built in PROM versions are shown in Figure 2 11 1 PIN CONFIGURATION TOP VIEW P11 INTo gt P07 AN7 t P06 ANe PO5 AN5 PO4 AN4 lt gt P15 CNTR1 1 gt P14 CNTRO 3d gt P13 TXo 34 gt P16 PWM 82 3 2d gt P12 INT1 128 4 27 5 24 gt P21 Souri gt P22 Scua 9 P23 Snpvi gt 38 Vss P24 URxp 9 P2s Urxp t P2e Unrs P27 Ucts C gt P02 AN2 gt PO1 AN1 74 9 PO0 ANo VREF AVss Vcc XOUT 74 XN Vss RESET P39 gt 44 P31 CTX 1
168. immunity is required Refer to the counter measures against noise of the corresponding users manual Port PO must not be subjected to overvoltage conditions 1 16 7630 Group User s Manual HARDWARE INTERRUPTS INTERRUPTS There are 24 interrupts 6 external 17 internal and 1 software Interrupt Control Each interrupt except the BRK instruction interrupt has both an inter rupt request bit and an interrupt enable bit and is controlled by the interrupt disable flag An interrupt occurs when the corresponding interrupt request and enable bits are 1 and the interrupt disable flag is 0 Interrupt enable bits can be cleared or set by software Inter rupt request bits can be cleared by software but cannot be set by software The BRK instruction interrupt and reset cannot be disabled with any flag or bit The flag disables all interrupts except the BRK instruction interrupt and reset If several interrupt requests occur at the same time the interrupt with the highest priority is accepted first Interrupt Operation Upon acceptance of an interrupt the following operations are auto matically performed 1 The processing being executed is stopped 2 The contents of the program counter and processor status register are automatically pushed onto the stack 3 Concurrently with the push operation the interrupt jump destination address is read from the vector table into the program counter 4 The interrupt disable
169. ing routine Note 2 CLT Note 3 Note 3 When using the Index X mode flag T CLD Note 4 Note 4 When using the Decimal mode flag D Push registers to the stack area Push the registers used in the interrupt processing routine on the stack RAM for high order 8 bit of a measurement result RAM for low order 8 bit of a measurement result lt TXH A complemented count value is read out and stored to RAM lt XL Pop registers from the stack area Pop registers which is pushed on the stack Note 2 The first measurement with Timer X is invalid as shown in the following figure Example 1 Make sure to start the Timer X count at L level of the CNTRo input signal A level of the CNTRo input signal is judged by reading a content of the Port P14 register 2 Be sure to invalidate the first CNTRo interrupt after starting the Timer X count When the Timer X count is started at L level of the CNTRo input signal 000016 t2 tl Timer X Start Timer X A measurement result Valid A measurement result Valid CNTRo input Y Y CNTRo interrupt CNTRo interrupt When the Timer X count is started at H level of the CNTRo input signal Timer X Start Timer X A measurement result Invalid A measurement result Valid CNTRo input Y Y CNTRo interrupt CNTRo interrupt Fig 2 3 18 Control procedure Measurement of pulse width 2 7630 Group User s Manual 2 33 APPLICATION 2 4 Cont
170. instruction Clear the interrupt request bit to 0 to an interrupt request bit of an interrupt request no interrupt issued register immediately after this bit is set to 0 by using a data transfer instruction execute one or more instructions before executing the NOP one or more instructions BBC or BBS instruction data transfer instructions LDM LDA STA STX f Execute the BBC or BBS instruction and STY instruction Reason If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to 0 the value of the interrupt request bit before being cleared to 0 is read 3 Stack operation of the program status register If the current program status register is stored on the stack after executing the PHP instruction the PLP instruction has to be entered to get the old program status register back Before the PLP instruction can be executed the SEI PLP instruction instruction has to be executed pull program status register form stack SEI instruction all interrupt disabled 3 3 2 Notes on A D converter 1 Analog input pin Make the signal source impedance for analog input low or equip an analog input pin with an external capacitor of 0 01 uF to 1 uF Further be sure to verify the operation of application products on the user side Reason An analog input pin includes the capacitor for analog voltage comparison Accordingly when signa
171. ion The carry flag C is set to 1 if a carry is generated as a result of the calculation or is l cleared to 0 if a borrow is generated To determine whether a calculation has generated a carry the C flag must be initialized to 0 before each calculation To check for a borrow the C flag must be initialezed to 1 before each calculation 6 JPM instruction When using the JMP instruction in indirect addressing mode do not specify the last address on a page as an indirect address 3 16 7630 Group User s Manual APPENDIX 3 4 Countermeasures against noise 3 4 Countermeasures against noise Countermeasures against noise are described below The following countermeasures are effective against noise in theory however it is necessary not only to take measures as follows but to evaluate before actual use 3 4 1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer The shorter the total wiring length by mm unit the less the possibility of noise insertion into a microcomputer 1 Wiring for the RESET input pin Make the length of wiring which is connected to the RESET input pin as short as possible Especially connect a capacitor across the RESET input pin and the Vss pin with the shortest possible wiring within 20mm Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions If noise ha
172. ister 2 b7 b6 b5 b4 b3 b2 bi bO UART transmit buffer register 1 UTBR1 Address 002416 UART transmit buffer register 2 UTBR2 Address 002516 CG Transmit data is written to this buffer register consisting of low order x o and high order byte xJol xo xo ENE x xo xlo Fig 3 5 24 Structure of UART transmit buffer register 1 2 7630 Group User s Manual 3 33 APPENDIX 3 5 List of registers UART receive buffer register 1 UART receive buffer register 2 b7 b6 b5 b4 b3 b2 bi bO UART receive buffer register 1 URBR1 Address 002616 UART receive buffer register 2 URBR2 Address 002716 Receive data is read from this buffer register consisting of low order and high order byte Fig 3 5 25 Structure of UART receive buffer register 1 2 Port Pi pull up control register b7 b6 b5 b4 b3 b2 bi bO ITITI Port Pi pull up control register PUPI i 0 2 Address 002816 002A16 e Nme Function Ateset W Pio pull up transistor control bit 0 No pull up 1 Pull up 1 Pit pull up transistor control bit 0 No pull up 1 Pull up o Pi2 pull up transistor control bit 0 No pull up 1 Pull up 3 Pis pull up transistor control bit 0 No pull up 1 Pull up 4 Pi4 pull up transistor control bit 0 No pull up 1 Pull up 5 Pis pull up transistor control bit 0 No pull up 1 Pull up Pie pull up transistor control bit 0
173. isters 3 CTB3 CRB3 CAN transmit receive buffer registers 4 b7 b6 b5 b4 b3 b2 b1 bo CAN transmit buffer register 4 CTB4 Address 0044 g CAN receive buffer register 4 CRB4 Address 005446 B Name Function r1 bit reserved bit 1 For CTB4 Set this bit to 0 must be sent dominant applicable for extended format only RTR bit 0 Data frame 1 Remote frame Extended identifier bit 0 Extended identifier bit 1 Extended identifier bit 2 Extended identifier bit 3 Extended identifier bit 4 Extended identifier bit 5 For CTB4 These bits represent part of the identifier field of a frame to be transmitted For CRB4 These bits represent part of the identifier field of a frame received Note 1 Remote transmission request bit Fig 3 5 52 Structure of CAN transmit receive buffer registers 4 CTB4 CRB4 7630 Group User s Manual APPENDIX 3 5 List of registers CAN transmit receive buffer registers 5 b7 b6 b5 b4 b3 b2 b1 bo CAN transmit buffer register 5 CTB5 Address 0045 g CAN receive buffer register 5 CRB5 Address 0055 g B Name Function At reset The data length code indicates the DLC bit 0 number of data bytes in a data frame b3b2b1b0 0000 Zero data bytes 00
174. it 0 No interrupt request 1 Interrupt requested 5 AD conversion complete i No interrupt request interrupt request bit Interrupt requested Key on wake up 2 No interrupt request interrupt request bit Interrupt requested Not used 0 when read ud Can be cleared to 0 by software but cannot be set to 1 Fig 2 2 4 Structure of Interrupt request register C Interrupt control register A b7 b6 b5 b4 b3 b2 bi bO OT A Interrupt control register A ICONA Address 000516 B Nme Funton fatreselm w Not used 0 when read ENEE External interrupt INTo enable bit Interrupt disabled Interrupt enabled o External interrupt INT enable bit Interrupt disabled Interrupt enabled 3 CAN successful transmission O Interrupt disabled interrupt enable bit 1 Interrupt enabled 4 CAN successful receive 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 5 CAN overrun 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled CAN error passive 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 7 CAN bus off 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled Fig 2 2 5 Structure of Interrupt control register A 7630 Group User s Manual 2 11 APPLICATION 2 2 Interrupts Interrupt control register B b7 b6 b5 b4 b3 b2 bi bO ee Interrupt control register B ICONB Address 000616 HE m wake up interrupt enable bit Inte
175. its 0 Falling edge active 1 Rising edge active Fig 16 Structure of interrupt polarity selection register 7630 Group User s Manual 1 19 HARDWARE INTERRUPTS Interrupt request register A address 000246 IREQA Not used returns to 0 when read External interrupt INT request bit External interrupt INT request bit CAN successful transmission interrupt request bit CAN successful receive interrupt request bit CAN overrun interrupt request bit CAN error passive interrupt request bit CAN bus off interrupt request bit Interrupt request register B address 000316 IREQB CAN wake up interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit CNTRo interrupt request bit CNTR interrupt request bit Interrupt request register C address 000416 IREQC UART receive complete receive buffer full interrupt request bit UART transmit complete transmit register empty interrupt request bit UART transmit buffer empty interrupt request bit UART receive error interrupt request bit Serial I O interrupt request bit AD conversion complete interrupt request bit Key on wake up interrupt request bit Not used returns to 0 when read Interrupt control register A address 000516 ICONA Not
176. k register 2 CAM2 Address 003A g B Name Function At reset O Extended identifier mask bit 14 2 Extended identifier mask bit 15 0 Mask identifier bit don t care 1 Compare identifier bit Extended identifier mask bit 16 These bits mask the corresponding bits of the acceptance code register 2 Figure 2 4 8 from the acceptance filtering Extended identifier mask bit 17 These bits must be set to 0 Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 2 4 13 Structure of CAN acceptance mask register 2 CAM2 CAN acceptance mask register 3 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance mask register 3 CAM3 Address 003B g B Name Function O Extended identifier mask bit 6 Extended identifier mask bit 7 Extended identifier mask bit 8 Extended identifier mask bit 9 0 Mask identifier bit don t care 1 Compare identifier bit Extended identifier mask bit 10 Extended identifier mask bit 11 These bits mask the corresponding bits of the acceptance code register 3 Figure 2 4 9 from the acceptance filtering Extended identifier mask bit 12 Extended identifier mask bit 13
177. l identifier bits Buffer content processing by CAN successful receive CSR interrupt service Execution time of CSR service routine shorter than the frames on the bus Interrupt system of the application optimised for minimum latency of interrupts Start of frame P3 CRX receive status bit CREC 1 a tack rsb 9 tpt CAN successful receive lack csr 6 tpi receive buffer control bit tack rbo 8 tot CREC 0 i P3 CRX p T4 receive status bit CREC 1 CAN successful receive receive buffer control bit CREC O contents CRBO to CRBD 77 undefined foreground receive buffer Fig 2 4 34 Receive sequence timing 4 2 58 During a successful reception the module alters the special function bits CREC 1 IREQA 4 and CREC O according to the following sequence 1 Set CREC 1 within the start of frame bit 2 Set IREQA 4 and CREC O within the seventh bit time of the end of frame field 3 Clear CREC 1 after the second bit time of the intermission field Avoiding CAN overrun interrupts The CAN overrun interrupt COVR is requested upon reception of a relevant frame when both receive buff ers are preoccupied by previously received frames because the CPU has not released a buffer yet The frame causing the CAN overrun inter
178. le 2 35 Fig 2 4 2 Memory map of CAN related registers 2 36 Fig 2 4 3 Structure of CAN transmit control register e 2 37 Fig 2 4 4 Structure of CAN bus timing control register 1 2 37 Fig 2 4 5 Structure of CAN bus timing control register 2 2 38 7630 GROUP USER S MANUAL V List of figures Fig 2 4 6 Structure of CAN acceptance code register 0 2 38 Fig 2 4 7 Structure of CAN acceptance code register 1 sss 2 39 Fig 2 4 8 Structure of CAN acceptance code register 2 2 39 Fig 2 4 9 Structure of CAN acceptance code register 3 2 40 Fig 2 4 10 Structure of CAN acceptance code register 4 2 40 Fig 2 4 11 Btructure of CAN acceptance mask register 0 sssuss 2 41 Fig 2 4 12 Structure of CAN acceptance mask register 1 2 41 Fig 2 4 13 Btructure of CAN acceptance mask register 2 2 42 Fig 2 4 14 Structure of CAN acceptance mask register 3 2 42 Fig 2 4 15 Structure of CAN acceptance mask regiater 4 2 43 Fig 2 4 16 Structure of CAN receive control register sess 2 43 Fig 2 4 17 Structure of CAN transmit abort register 2 44 Fig 2 4 18 Structure of CAN transmit receive buffer registers O J ssssessssss 2 44 Fig 2 4 19 Btructure of CAN transmit receive buffer registers T 2 45 Fig 2 4 20 Btructure of CAN transmit receive buffer registers 2 2 45 Fig 2 4 21 Structure of CAN transmit receive buff
179. le bit and transmit status register flags Stop transmission Receive initialization bit 0 No action 1 Initialize the receive enable bit and receive status register flags Not used 0 when read don t write 1 Fig 2 5 6 Structure of UART control register UART status register b7 b6 b5 b4 b3 b2 bi bO iillilj UART status register USTS Address 002316 e mame Funton fates R w Transmission register empty flag 0 Register full 1 Xx 1 Register empty Transmission buffer empty flag 0 Buffer full 4 x 1 1 Buffer empty 2 Receive buffer full flag 0 Buffer full 1 x 1 Buffer empty 3 Receive parity error flag 0 No parity error detected x 1 Parity error detected 4 Receive framing error flag 0 No framing error detected x 1 Framing error detected 5 Receive overrun flag No overrun detected x Overrun detected Receive error sum flag No error detected Error detected y Not used 0 when read Face Fig 2 5 7 Structure of UART status register 2 70 7630 Group User s Manual APPLICATION 2 5 Serial I O UART transmit buffer register 1 UART transmit buffer register 2 b7 b6 b5 b4 b3 b2 bi bO UART transmit buffer register 1 UTBR1 Address 002416 UART transmit buffer register 2 UTBR2 Address 002516 Transmit data is written to this buffer register consisting of low order and high order byte Fig 2 5 8 Structure of UART
180. leted Note VREF input switch bit E Off On El Not used 0 when read don t write 1 o o x Escola ENEE Note Don t set this bit to 1 during A D conversion Fig 2 6 3 Structure of A D control register 7630 Group User s Manual 2 91 APPLICATION 2 6 A D converter 2 6 3 A D conversion application example Measurement of analog signals Outline A sensor s analog output voltage is converted to digital values Figure 2 6 4 shows a connection related registers Sensor Reference voltage 7630 group Fig 2 6 4 Connection diagram Measurement of analog signals Specifications The analog input voltage injected from the sensor is converted into digital values Note e The PO1 AN1 pin is used as an analog input pin Note Example When a reference voltage 5 12 V is input to the VREF pin and a voltage 4 V to the P01 AN1 pin the input voltage is converted to following value 256 5 12 V X 4 V 200 C816 Figure 2 6 5 shows a setting of related registers Port PO direction register Address 000916 bO b7 Poo LTT TT fey NEN P01 AN1 pin Input mode used as the analog input pin A D control register Address 001516 b7 bO anes dadas NENNEN Analog input pin selection bits The PO1 AN1 pin A D conversion completion bit Conversion completed Clear to 0 to start A D conversion Don t set this bit to 1 during A D conversion VREF input s
181. letion bit and the A D interrupt request 7630 Group User s Manual 1 39 HARDWARE WATCHDOG TIMER WATCHDOG TIMER The watchdog timer consists of two separate counters one 7 bit counter WDy and one 4 bit counter WD Cascading both counters or using the high order counter allows only to select the time out from either 524288 or 32768 cycles of the internal clock 9 Refer to Fig 43 and Fig 44 Both counters are addressed by the same watchdog timer register WDT When writing to this register both counters will be set to the following default values the high order counter will be set to address 7F46 the low order counter will be set to address F46 regardless of the data written to the WDT register Reading the watchdog timer register will return the corresponding control bit sta tus not the counter contents o WDT register 8 Fig 43 Block diagram of watchdog timer Once the WDT register is written to the watchdog timer starts count ing down and the watchdog timer interrupt is enabled Once it is run ning the watchdog timer cannot be disabled or stopped except by reset On a watchdog timer underflow a non maskable watchdog timer interrupt will be requested To prevent the system being stopped by STP instruction this instruc tion can be disabled by the STP instruction disable bit of WDT regis ter Once the STP instruction is disabled it cannot be enabled again except by RESET WDT interr
182. ll up P16 pull up transistor control bit 0 No pull up 1 Pull up 7 P17 pull up transistor control bit 0 No pull up 1 Pull up Fig 2 1 5 Structure of Port P1 pull up register 2 4 7630 Group User s Manual APPLICATION 2 1 1 0 ports Port P3 pull up control register b7 b6 b5 b4 b3 b2 bi bO EU 11111 Port P3 pull up control register PUP3 Address 002B16 je Name Fuin Ares R w P30 pull up transistor control bit 0 No pull up 1 Pull up 1 P31 pull up transistor control bit No pull up Pull up P32 pull up down transistor e No pull up down control bit Pull up down Note P33 pull up transistor control bit 7 No pull up Pull up P34 pull up transistor control bit E No pull up Pull up 5 Not used 0 when read don t write 1 Note Enables the pull transistor towards the CAN module recessive level This level depends on the CAN module dominant level control bit bit 1 of the Polarity control register address 002F 16 Fig 2 1 6 Structure of Port P3 pull up control register Port P4 pull up down control register b7 b6 b5 b4 b3 b2 bi bO EET EJ Port P4 pull up down control register PUP4 Address 002C16 e name Function faee P4o pull up down transistor E No pull up down control bit Pull up down Note P41 pull up down transistor eb No pull up down control bit Pull up down Note P42 pull up down transistor A No pull up down control bit 1 Pull up do
183. logy Corp C T D m 0 ay 5 C 2 ENESAS 7630 Group User s Manual MITSUBISHI 8 BIT SINGLE CHIP MICROCOMPUTER 740 FAMILY 7600 SERIES Renesas Electronics m New publication 1999 01 www renesas com keep safety first in your circuit designs O Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials O These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party O Mitsubishi Electric Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts or circuit application examples contained in these materials O All information contained in these materials including pro
184. lost Fig 2 4 35 Receive sequence timing overrun condition To avoid an overrun condition the time between a successful reception and the release of receive buffer by the CPU must be shorter than the shortest possible frame in the network This can be accomplished by opti mization of the applications interrupt system towards minimum latency and interrupt execution times 5 Auto receive function The auto receive disable bit CREC 6 Figure 2 4 16 allows to select two options regarding the handling of frames sent by the module Enabling auto receive by clearing CREC 6 causes the module to subject a self generated frame to the reception process described above however the following deviations apply Self generated frames are not self acknowledged CREC 1 remains 0 during the auto receive process The corresponding sub mode according to Figure 2 4 26 is transmitting A frame rated relevant by the acceptance filtering causes a successful receive interrupt request and possi bly an overrun interrupt request see section 4 7630 Group User s Manual 2 59 APPLICATION 2 4 Controller Area Network CAN module Disabling auto receive by setting CREC 6 causes the module to suspend all receive functions related to the receive control logic block Figure 2 4 1 during the transmission process The transmitting receiving sub mode of the normal mode shown in Figure 2 4 25 is disabled Note Disabling auto re
185. low or equip an analog input pin with an external capacitor of 0 01uF to 1uF Further be sure to verify the operation of application products on the user side Reason An analog input pin includes the capacitor for analog voltage comparison Accordingly when signals from signal source with high impedance are input to an analog input pin charge and discharge noise generates This may cause the A D conversion precision to be worse 2 Reference voltage input pin VREF Apply a voltage of 2V to Vcc to the reference voltage input pin VREF during A D conversion Note that if the reference voltage is lowered below the above value the A D conversion precision will be degraded 3 Oscillation frequency during A D conversion The comparator is configured by capacity coupling so the charge is lost if the clock input oscillation frequency is low Set f XIN at 500kHz or more during A D conversion 4 Set the analog input pin to input mode Clear the bit of the Port PO direction register Address 000916 which correponds to the used analog input pin to 0 input mode 7630 Group User s Manual 2 93 APPLICATION 2 7 Watchdog timer 2 7 Watchdog timer The watchdog timer can detect a runaway program using either 7 bit or 11 bit timer prescaler 2 7 1 Related register Watchdog timer register Note 1 b7 b6 b5 b4 b3 b2 b bO NENNENN Watchdog timer register WDT Address 002E16 Stop instruction disable bit 0 St
186. ls from signal source with high impedance are input to an analog input pin charge and discharge noise generates This may cause the A D conversion precision to be worse 7630 Group User s Manual 3 13 APPENDIX 3 3 Notes on use 2 AVss pin AVss pin is the A D converter power source pin Regardless of using the A D conversion function or not connect AVss to the Vss line Reason If the AVss pin is opened the microcomputer may have a failure because of noise or others 3 Clock frequency during an A D conversion The comparator consists of a capacity coupling and a charge of the capacity will be lost if the clock frequency is too low Thus make sure the following during an A D conversion f XIN is 500 kHz or more Do not execute the STP instruction and WIT instruction 3 3 3 Notes on RESET pin In case where the RESET signal rise time is long connect a ceramic capacitor or others across the RESET pin and the Vss pin And use a 1000 pF or more capacitor for high frequency use When connecting the capacitor note the following Make the length of the wiring which is connected to a capacitor as short as possible Be sure to check the operation of application products on the user side Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin it may cause a microcomputer failure 3 3 4 Notes on input and output pins 1 Notes in stand by state In stand by state for low power dissipation
187. m clock The operation of the clock synchronous serial I O can be configured by the serial I O control register SIOCON refer to Fig 27 SIOCON Onn SIO counter 3 0 P2 latch SIOCON O DT SIO shift register 8 P P2 latch SIOCON SIO interrupt Oa ijr P2 latch Fig 25 Block diagram of clock synchronous I O is internal system clock 1 Clock synchronous serial I O operation Either an internal or external transfer clock can be selected by bit 6 of SIOCON The internal clock divider can be programmed by bits 0 to 2 of SIOCON Bit 3 of SIOCON determines whether the double func tion pins P2 to P2 will act as I O ports or serve as SIO pins Bit 4 of SIOCON allows the same selection for pin P23 When an internal transfer clock is selected transmission can be trig gered by writing data to the SI O shift register SIO address 001246 After an 8 bit transmission has been completed the Sour pin will change to high impedance and the SIO interrupt request bit will be set to 1 When an external transfer clock is selected the SIO interrupt request bit will be set to 1 after 8 cycles but the contents of the SI O shift register continue to be shifted while the transfer clock is being input Therefore the clock needs to be controlled externally the Sour pin will not change to high impedance automatically synchronous clock
188. m the acceptance filtering condition for incoming CAN frames They must be initialized with the identifier pattern of CAN frames to be received Extended identifier bit 15 Extended identifier bit 16 Extended identifier bit 17 Not used Undefined at read Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 2 4 8 Structure of CAN acceptance code register 2 CAC2 7630 Group User s Manual 2 39 APPLICATION 2 4 Controller Area Network CAN module CAN acceptance code register 3 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance code register 3 CAC3 Address 003646 B Name Function At reset O Extended identifier bit 6 2 Extended identifier bit 7 Extended identifier bit 8 These bits except when masked by the Extended identifier bit 9 acceptance mask register 3 Figure 2 4 14 form the acceptance filtering condition for incoming CAN frames They must be initialized with the identifier pattern of CAN frames to be received Extended identifier bit 10 Extended identifier bit 11 Extended identifier bit 12 Extended identifier bit 13 Note 1 Writing to this register is enabled in configuration mode only refer to sec
189. module receiving Receive buffer control bit Receive status bit When these bits are read out the values are 0 Don t write to 1 Reserved 0 Auto receive enabled 1 Auto receive disabled Auto receive disable bit When these bits are read out the values are 0 Don t write to 1 Reserved Note 1 RO R1 denote read access WO W1 denote write access Note 2 Suppresses reception of self initiated transmitted frames for details see section 2 4 8 5 Fig 2 4 16 Structure of CAN receive control register CREC 7630 Group User s Manual 2 43 APPLICATION 2 4 Controller Area Network CAN module CAN transmit abort register CAN transmit abort register CABORT Address 003E g b7 b6 b5 b4 b3 b2 bi b0 B Name Function At reset RO No transmit abort requested R1 Transmit abort requested WO Clear transmit abort request W1 Transmit abort requested Transmit abort control bit Not used Undefined at read Note 1 RO R1 denote read access WO W1 denote write access Note 2 Setting this bit to 1 is enabled only when CTRM 3 Figure 2 4 3 is set Fig 2 4 17 Structure of CAN transmit abort register CABORT CAN transmit receive buffer registe
190. nabled Fig 13 Structure of port pull up down control registers Fig 14 Structure of polarity control register Polarity control register address 002F g PCON Key on wake up polarity control bit 0 Low level active 1 High level active CAN module dominant level control bit 0 Low level dominant 1 High level dominant Not used undefined when read registers The pull up down function of ports P32 and P4 can be con trolled by the corresponding port pull up pull down registers together with the polarity control register see Structure of polarity control reg 7630 Group User s Manual HARDWARE I O PORTS Port Overvoltage Application When configured as input ports P1 to P4 may be subjected to over voltage V gt Vcc if the input current to the applicable port is limited to the specified values see Table 10 Use a serial resistor of appropriate size to limit the input current To estimate the resistor value assume the port voltage to be Vcc at overvoltage condition Notes Subjecting ports to overvoltage may effect the supply voltage Assure to keep Vcc and Vss within the target limits Avoid to subject ports to overvoltage causing Vcc to rise above 5 5 V The overvoltage condition causing input current flowing through the internal port protection circuits has a negative effect on the ports noise immunity Therefore careful and intense testing of the target system s noise
191. nesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office eq
192. ng are necessary when ordering a mask ROM production 1 Mask ROM Order Confirmation Form 2 Mark Specification Form 3 Contents of Mask ROM in EPROM form three identical copies PROM PROGRAMMING METHOD The built in PROM of the blank One Time PROM version and built in EPROM version can be read or programmed with a general purpose PROM programmer using a special programming adapter Set the address of PROM programmer to the user ROM area For the programming adapter type name please refer to the following table Table 8 Programming adapter name MCU type Programming adapter type One Time PROM PCA7430 EPROM PCA7431 The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes To ensure proper operation after programming the procedure shown in Fig 50 is recommended to verify programming Programming with PROM programmer Y Screening Note 150 C for 40 hours Y Verification with PROM programmer Functional test in target unit Note on screening The screening temperature is far higher than the storage temper ature Never subject the device to 150 C exceeding 100 hours Fig 50 Programming and testing of One Time PROM version 1 44 7630 Group User s Manual HARDWARE ABSOLUTE MAXIMUM RATING Table 9 ABSOLUTE MAXIMUM RATINGS Parameter Power source voltage Conditions Ratings
193. ngth code of the data field of a data frame not relevant for remote frames Data bits of CBT6 to CBTD these bits represent the data field of a data frame not relevant for remote frames For settings of the IDE RTR SRR RTR r0 and r1 bits to be programmed refer to the table below Frame format Frame type IDE RTR SRR RTR ro ri standard format data frame 0 0 X o x 11 bit identifier remote frame 0 1 X extended format data frame 1 1 0 No f 0 0 29 bit identifer remote frame 1 1 1 Lock the transmit buffer Once the transmit buffer is initialized the transmit buffer control bit of CTRM Figure 2 4 3 should be set to 1 This locks the transmit buffer thereby protects it from being altered accidentally After locking data read from the address range of the transmit buffer is undefined The buffer remains locked until either the trans 7630 Group User s Manual 2 61 APPLICATION 2 4 Controller Area Network CAN module mission process could be finished successfully or a transmit abort is requested see section 2 4 10 the buffer can not be unlocked by clearing the transmit buffer control bit from CPU side 4 Issue transmission request Finally the transmission can be started by setting the transmission control bit of CTRM Figure 2 4 3 Setting this bit gives control of the buffer to the CAN module the module attempts to transmit the frame defined by the transmit buffer content
194. nrs SIO1 input 14 Port P3 CTX 9 Port P2 Sout Pull up control bit Pull up control bit CAN port selection bit SIO port selection bit Transmit complete signal S Direction Direction register register Data bus Port latch Port latch I 1 CTX output SIO output 15 Port P32 CRX CAN dominant level control bit e Pull up down control bit 10 Port P22ScLk Direction ai Pull up control bi register jock selection bit Port selection bit zT 3 Data bus s Port latch direction 5 i register Y Data bus gt Port latch ERR interrupt 4 I CM d Nc SIO clock output External clock in ut lt _ 4 RX input 1 16 Ports P4 KW to P4 KW Key on wake up control bit Pull up down control bit 1 1 Port P23 Sroy Pull up control bit Direction register SRDY output selection bit Direction register Data bus Port latch La Key on wake up interrupt lt C
195. nstruction C flag Z flag flag D flag B flag T flag V flag N flag SEC SEI SED SET Clear instruction CLC CLI 7630 Groop User s Manual CLD CLT CLV 1 9 HARDWARE FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION Central Processing Unit CPU The core of 7630 group microcomputers is the 7600 series CPU This core is based on the standard instruction set of 740 series however the performance is improved by allowing to execute the same instruc tions as that of the 740 series in less cycles Refer to the 7600 Series Software Manual for details of the instruction set CPU Mode Register CPUM The CPU mode register contains the stack page selection bit and internal system clock selection bit The CPU mode register is allo cated to address 000046 CPU mode register address 0000 g CPUM Processor mode bits set these bits to 00 b1 bO 0 0 Single chip mode 1 Notused 0 Not used 1 Notused Stack page selection bit 0 Opage 1 1page Not used 0 when read do not write 1 Internal system clock selection bit 0 4 f X n divided by 2 high speed mode 1 o f X y divided by 8 middle speed mode Not used 0 when read do not write 1 Fig 7 Structure of CPU mode register 1 10 7630 Group User s Manual HARDWARE FUNCTIONAL DESCRIPTION MEMORY Special Function Register SFR Area The special function register SFR area contains the re
196. ntrol Receive buffers and interface P3JCRX acceptance filter transmit control logic Transmit buffer status buffer control CAN transmit control register CAN transmit abort register interrupt control logic Successful receive interrupt Successful transmit interrupt Overrun interrupt wake up logic Error passive interrupt Polarity control register Bus off interrupt CAN wake up interrupt Interrupt control registers j Interrupt request registers j Notation in this diagram Special function register Fig 2 4 1 Block diagram of CAN module 2 4 2 Special function register map The CAN module s programming interface consists of the registers listed below Transmit control register Bus timing control registers Acceptance code and mask registers Receive control register Transmit abort register Transmit receive buffers Polarity control register Interrupt request and control registers Figure 2 4 2 shows the memory map of these registers The next section explains each register in detail for the polarity control register and the interrupt registers refer to section 2 2 7630 Group User s Manual 2 35 APPLICATION 2 4 Controller Area Network CAN module Interrupt request register A IREQA Interrupt request register B IREQB Interrupt re
197. o 1 Note Controlled by the serial I O logic Fig 2 5 28 Control procedure on transmitting side Communication using UART 2 88 7630 Group User s Manual APPLICATION 2 5 Serial I O e Receiving side RESET X These bits are not used in this application Please set these bits to 0 or 1 appropriately Initialization CPUM Address 000016 4 00000X002 f XiN divided by 2 high speed mode UMOD Address 002016 lt _ 100X101 X2 Transfer data format 1ST 9DATA 2SP UCON Address 002216 XXXX10002 Receive initialization The Receive enable bit is cleared to 0 lt A UBRE Agdress 0021e m The Receive buffer full flag is set to 1 The Receive parity error flag is cleared to 0 The Receive framing error flag is cleared to 0 The Receive overrun flag is cleared to 0 The Receive error sum flag is cleared to 0 Receive enable Start of communication UCON Address 002216 bit 1 1 Output L from URTS USTS Address 002316 bit 2 Check the completion of receiving with the Receive buffer full flag Read the received data from URBR1 Address 002616 Read the received 9 bits data and URBR2 Address 002716 The receive buffer full flag is cleared to 0 by reading data USTS Address 002316 bit 6 Check the Receive error sum flag Processing for error
198. o divided by 64 1 1 divided by 128 Timer Y count source selection bits b3 b2 0 0 q divided by 2 6 divided by 8 divided by 32 divided by 64 Timer Y operation mode bits b5 b4 0 0 Timer mode Pulse period measurement mode Event counter mode H L pulse width measurement mode CNTR polarity selection bit 0 For event counter mode rising edge active For interrupt request falling edge active For pulse period measurement mode refer to falling edges For event counter mode falling edge active For interrupt request rising edge active For pulse period measurement mode refer to rising edges Timer Y stop control bit 0 Timer counting 1 Timer stopped Fig 21 Structure of timer Y mode register 0 is internal system clock Operating Modes The count direction is determined by the edge polarity and level of count source inputs and may change during the count operation Refer to the table below Table 6 Timer X count direction in Bi phase counter mode 1 Timer mode This mode is available with timer X and timer Y Count source The count source for timer X and Y is the output of the corre P1JCNTR sponding clock divider The division ratio can be selected by the timer Y mode register Operation Both timers X and Y are down counters On a timer underflow the corresponding timer interrupt request bit will be set to 1 the con tents of the corresponding timer latches will be relo
199. ol register Interrupt polarity selection register b7 b6 b5 b4 b3 b2 bi bO DEREN M Interrupt polarity selection register IPOL Address 002D16 e Name Function Ares g Not used 0 when read don t write 1 9 fox 1 INTo interrupt edge selection bit 0 Falling edge active Note 1 Rising edge active 2 INT interrupt edge selection bit 0 Falling edge active Note 1 Rising edge active E 2 olx Not used 0 when read don t write 1 o olx x o olx e je x EE Note To use the external interrupt functions the pull up transistor corresponding to the selected active level must be enabled by the corresponding pull up transistor control bits of the Port P1 pull up control register Fig 3 5 30 Structure of Interrupt polarity selection register 3 36 7630 Group User s Manual APPENDIX 3 5 List of registers Watchdog timer register Note 1 b7 b6 b5 b4 b3 b2 bi bO LI Eas Watchdog timer register WDT Address 002E16 Stop instruction disable bit 0 Stop instruction enabled 1 Stop instruction disabled Executed two NOP instructions instead of STP instruction Note 2 Upper byte count source selection A Underflow of the low order counter bit divided by 256 Note 1 Writing to this register reloads the watchdog timer counters with the following initial values irrespective of the value written After reload the watchdog timer counts down Th
200. ontrol procedure on the transmitting side and Figure 2 5 23 shows a control procedure on the receiving side Transmitting side RESET X These bits are not used in this application Please set these bits to O or 1 appropriately Initialization CPUM Address 000016 lt 00000X002 f XiN divided by 2 high speed mode UMOD Address 002016 lt 010X101 X2 Transfer data format 1ST 8DATA 2SP UCON Address 002216 XXXX01 002 Transmit initialization UBRG Address 002116 4 1 The Transmit enable bit is cleared to 0 The Transmission register empty flag is set to 1 The Transmission buffer empty flag is set to 1 UCON Address 002216 bit 0 lt 1 Transmit enable Start of communication UTBR1 Address 002416 e Write the first byte of transmission data to the Transmit buffer register The first byte of transmission data The Transmit buffer empty flag is cleared to 0 by this writing When the Ucrs input level is L start transmission Note Check whether the data has been transferred from the Transmit buffer USTS Address 002316 bit 1 register to the Transmit shift register with the Transmit buffer empty flag UTBR1 Address 00241 2n Mibi 2 2 adicit ne to e ena ed lt The second byte of transmission data to 0 by ihis nino eue ede When the Ucrs input
201. op instruction disable bit 0 Stop instruction enabled 1 Stop instruction disabled Executed two NOP instructions instead of STP instruction Note 2 Upper byte count source selection PR Underflow of the low order counter bit 6 divided by 256 Note 1 Writing to this register reloads the watchdog timer counters with the following initial values irrespective of the value written After reload the watchdog timer counts down The high order counter WDH 7 bit counter is set to 7F16 The low order counter WDL 4 bit counter is set to F16 The time out period of the watchdog timer is n cycles of the internal system clock 6 x n 524288 when the Upper byte count source selection bit is 0 n 32768 when the Upper byte count source selection bit is 1 On a watchdog timer underflow the watchdog timer interrupt non maskable occurs Set the watchdog timer counters to the default values prevent from underflow by writing to this register in main processing Once the watchdog timer has been started it cannot be stopped except by reset Note 2 Once the Stop instruction is disabled it cannot be enabled again except by reset Fig 2 9 3 Structure of Watchdog timer register 2 98 7630 Group User s Manual APPLICATION 2 9 Oscillation circuit 2 9 3 Application examples As examples of application switching procedures to Stop and Wait modes are shown below 1 Ordinary mode gt Stop mode 2 Or
202. op instruction enabled 1 Stop instruction disabled Executed two NOP instructions instead of STP instruction Note 2 Upper byte count source selection 0 Underflow of the low order counter bit 1 6 divided by 256 Note 1 Writing to this register reloads the watchdog timer counters with the following initial values irrespective of the value written After reload the watchdog timer counts down e The high order counter WDH 7 bit counter is set to 7F16 The low order counter WD 4 bit counter is set to Fie The time out period of the watchdog timer is n cycles of the internal system clock 6 n 524288 when the Upper byte count source selection bit is 0 n 32768 when the Upper byte count source selection bit is 1 On a watchdog timer underflow the watchdog timer interrupt non maskable occurs Set the watchdog timer counters to the default values prevent from underflow by writing to this register in main processing Once the watchdog timer has been started it cannot be stopped except by reset Note 2 Once the Stop instruction is disabled it cannot be enabled again except by reset Fig 2 7 1 Structure of Watchdog timer register 2 94 7630 Group User s Manual APPLICATION 2 7 Watchdog timer 2 7 2 Watchdog timer cycle The watchdog timer cycle varies depending on the internal clock and the frequency division ratio of the prescaler selected Table 2 7 1 shows the watchdog time
203. operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles at the fixed interrupt processing count Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less Interrupt processing routine SWDT SWDT 1 Interrupt processing Main processing Interrupt processing Main routine errors routine errors Fig 3 4 10 Watchdog timer by software 7630 Group User s Manual 3 21 APPENDIX 3 5 List of registers 3 5 List of registers CPU mode register b7 b6 b5 b4 b3 b2 bi bO E E CPU mode register CPUM Address 000016 Single chip mode Not available Not available Not available es clock selection bit 2 high speed mode 8 middle speed mode Not used 0 when read don t write 1 B Fig 3 5 1 Structure of CPU mode register Interrupt request register A b7 b6 b5 b4 b3 b2 bi bO ITITI M Interrupt request register A IREQA Address 000216 e Name Furion Ateset w a Not used 0 when read BEL External interrupt INTo request bit n No interrupt request Interrupt requested 2 External interrupt INT1 request bit 0 No interrupt request 1 Interrupt requested 3 CAN successful transmission 0 No interrupt req
204. or Timer Y data write control bit bit O of the Timer X or Timer Y mode register address 001E16 001F 16 Fig 2 3 5 Structure of Timer XL Timer XH Timer YL Timer YH 2 20 7630 Group User s Manual APPLICATION 2 3 Timers Timer X mode register b7 b6 b5 b4 b3 b2 bi bo ll NEN Timer X mode register TXM Address 001E16 e name Funcion atresel Timer X data write control bit O Data is written to latch and timer 1 Data is written to latch only 1 Timer mode Bi phase counter mode Event counter mode Pulse width measurement mode 9 For event counter mode rising edge active For interrupt request falling edge active For pulse width measurement mode measure H period For event counter mode falling edge active For interrupt request rising edge active For pulse width measurement mode measure L period 7 Timer X stop control bit O Timer counting 1 Timer stopped Fig 2 3 6 Structure of Timer X mode register Timer Y mode register b7 b6 b5 b4 b3 b2 b1 bO LTT TTT TT Timer Y mode register TYM Address 001F16 fe name Function atrese Timer X count source selection divided by 4 Note bits divided by 16 Note divided by 64 Note divided by 128 Note KAGE 6 divided by 2 Note 2 fofo divided by 8 Note EH c o Timer Y count source selection bits divided by 32 Note divided by 64
205. oted Limits Absolute accuracy tCONV Conversion time High speed mode Middle speed mode VREF Reference input voltage IREF Reference input current Vcc VREF 5 12V RLADDER Ladder resistor value IIAN Analog input current 3 1 5 Timing requirements Table 3 1 5 tw RESET Timing requirements Vcc 4 0V to 5 5V Vss Reset input L pulse width Vi Vss to VCC AVss OV Ta 40 C to 85 C unless otherwise noted Parameter tC XIN External clock input cycle time tWH XIN External clock input H pulse width tWL XIN External clock input L pulse width tc CNTR CNTRo CNTR1 input cycle time except bi phase counter mode CNTRo input cycle time bi phase counter mode tWH CNTR CNTRo CNTR input H pulse width except bi phase counter mode CNTRo input H pulse width bi phase counter mode tWL CNTR CNTRo CNTR input L pulse widt h except bi phase counter mode CNTRo input L pulse width bi phase counter mode tL CNTRo TXo Lag of CNTRo and TXo input edges bi phase counter mode tc TXo TXo input cycle time tWH TXo TXo input H pulse width bi phase counter mode TXo input L pulse width bi phase counter mode bi phase counter mode twL TXo INT INTO INT1 input H pulse width twH
206. oup User s Manual 3 25 APPENDIX 3 5 List of registers Port Pi direction register b7 b6 b5 b4 b3 b2 bi bO Port Pi direction register PiD i 0 1 2 3 4 Address 000916 000B16 000D16 000F16 001116 W 0 Port Pio input mode x 1 Port Pio output mode 0 Port Pi1 input mode x 1 Port Pi1 output mode 0 Port Pi2 input mode x 1 Port Pi output mode 0 Port Pis input mode x 1 Port Pi3 output mode 0 Port Pia input mode x 1 Port Pi4 output mode 0 Port Pis input mode x 1 Port Pis output mode 0 Port Pie input mode x 1 Port Pie output mode 0 Port Piz input mode x 1 Port Pi7 output mode Note The direction control bits corresponding to P10 P11 P35 P3s and P37 are reserved 0 when read don t write 1 Fig 3 5 9 Structure of Port Pi direction register i 0 1 2 3 4 Serial I O shift register b7 b6 b5 b4 b3 b2 bi bO LEELLE Serial 1 O shift register SIO Address 001216 A shift register for serial transmission and reception At transmitting Set transmission data At receiving Store received data Note A content of the Transmit buffer register cannot be read out A data cannot be written to the Receive buffer register Fig 3 5 10 Structure of Serial I O shift register 3 26 7630 Group User s Manual APPENDIX 3 5 List of registers Serial I O control register b7 b6 b5 b4 b3 b2 bi bO BIIIIIII Serial I O control register
207. oward the recessive level is selected Fig 3 5 32 Structure of Polarity control register 7630 Group User s Manual 3 37 APPENDIX 3 5 List of registers CAN transmit control register b7 b6 b5 b4 b3 b2 bi bO CAN transmit control register CTRM Address 003046 B Name Function At reset 0 Sleep control bit CAN module in normal mode 0 CAN module in sleep mode CAN module in normal mode Reset configuration control bit CAN module in configuration mode plus reset when write P34 CTX serves as I O port P34 CTX serves as CTX output port RO No transmission requested R1 Transmission requested WO No operation W1 Request transmission Port double function control bit Transmit request bit Reserved 0 when read RO CPU access possible R1 CPU access not possible WO No operation W1 Lock transmit buffer Transmit buffer control bit Reserved 0 when read 0 CAN module idle or receiving 1 CAN module transmitting Transmit status bit Note 1 RO R1 denote read access WO W1 denote write access Fig 3 5 33 Structure of CAN transmit control register CTRM CAN bus timing control register 1 b7 b6 b5 b4 b3 b2 b1 bO CAN bus timing control register 1 CBTCON1 Address 0031 6 B Name Function At reset 0 b3b2b1b0 0 000
208. pt control register B 3 24 7630 Group User s Manual APPENDIX 3 5 List of registers Interrupt control register C b7 b6 b5 b4 b3 b2 bi bO Bill Interrupt control register C ICONC Address 000716 nurses mum 18 UART receive complete receive Interrupt disabled buffer full interrupt enable bit Interrupt enabled UART transmit complete transmit Interrupt disabled register empty interrupt enable bit i Interrupt enabled UART transmit buffer empty Interrupt disabled interrupt enable bit Interrupt enabled 3 UART receive error Interrupt disabled interrupt enable bit i Interrupt enabled 4 Serial 1 O interrupt enable bit O Interrupt disabled 1 Interrupt enabled 5 AD conversion complete Interrupt disabled interrupt enable bit Interrupt enabled Key on wake up Interrupt disabled interrupt enable bit Interrupt enabled Not used 0 when read olx Fig 3 5 7 Structure of Interrupt control register C Port Pi register b7 b6 b5 b4 b3 b2 bi bO Port Pi register Pi i 0 1 2 3 4 Address 000816 000A16 000C16 000E16 001016 In output mode Wri rite Port latch Port Pit dues In input mode Write Port latch Port Pi2 Read Value of pins qu Note The bits corresponding to P10 P35 P3e and P37 are reserved 0 when read don t write 1 Fig 3 5 8 Structure of Port Pi register i 0 1 2 3 4 7630 Gr
209. qual to or more effective than program runaway detection by a hardware watchdog timer The following shows an example of a watchdog timer provided by software In the following example to reset a microcomputer to normal operation the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine This example assumes that interrupt processing is repeated multiple times in a single main routine processing lt The main routine gt Assigns a single byte of RAM to a software watchdog timer SWDT and writes the initial value N in the SWDT once at each execution of the main routine The initial value N should satisfy the following condition N 1 gt Counts of interrupt processing executed in each main routine As the main routine execution cycle may change because of an interrupt processing or others the initial value N should have a margin Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case If the SWDT contents do not change after interrupt processing lt The interrupt processing routine gt Decrements the SWDT contents by 1 at each interrupt processing Determines that the main routine
210. quest control registers Interrupt control register A ICONA Interrupt control register B ICONB Polarity control register PCON CAN transmit control register CTRM CAN bus timing control register 1 CBTCON1 CAN bus timing control register 2 CBTCON2 CAN acceptance code register 0 CACO CAN acceptance code register 1 CAC1 CAN acceptance code register 2 CAC2 CAN acceptance code register 3 CAC3 CAN acceptance code register 4 CAC4 CAN acceptance mask register 0 CAMO CAN acceptance mask register 1 CAM1 Control registers and acceptance filter registers CAN acceptance mask register 2 CAM2 CAN acceptance mask register 3 CAM3 CAN acceptance mask register 4 CAM4 CAN receive control register CREC CAN transmit abort register CABORT CAN transmit buffer register 0 TBO CAN transmit buffer register 1 CAN transmit buffer register 2 CAN transmit buffer register 3 CAN transmit buffer register 4 CAN transmit buffer register 5 CAN transmit buffer register 6 CAN transmit buffer register 7 CAN transmit buffer register 8 CAN transmit buffer register 9 TB9 CAN transmit buffer register A CTBA CAN transmit buffer register B CTBB CAN transmit buffer register C CTBC CAN transmit buffer register D CTBD Transmit buffer registers C C C C C C C C C C CAN receive buffer register 0 CRBO CAN receive buffer register 1 CRB1 CAN receive buffer r
211. r B Address 000616 b7 bO cone OPA ooo Timer X interrupt enable bit Interrupt disabled Timer Y interrupt enable bit Interrupt enabled Port P1 direction register Address 000B16 b7 bO ey LE ee Port P14 Input mode Fig 2 3 13 Setting of related registers Measurement of frequency 2 2 28 7630 Group User s Manual APPLICATION 2 3 Timers Control procedure Figure 2 3 14 shows a control procedure X These bits are not used in this application Please set these bits to 0 or 1 appropriately Initialization SEI All interrupts Disabled CPUM Address 000016 00000X002 p f XiN divided by 2 high speed mode TXM Address 001E16 111000002 Timer X Event counter mode Count at falling edge of pulse input P1D Address O00B16 lt XXX0XX002 from CNTRo pin stop counting TXL Address 001416 FF 16 TXH Address 001B168 0016 TYM Address 001F16 1X0001XX2 Timer Y Timer mode divided by 8 as count source stop counting TYL Address 001C16 E716 TYH Address 001D16 0316 ICONB Address 000616 bit 2 1 Timer Y interrupt Enabled ICONB Address 000616 bit 1 0 Timer X interrupt Enabled IREQB Address 000316 bit 2 0 Set
212. r a single or three samples With single sampling the level is sampled at the defined sample point refer to Figure 2 4 27 Tri ple sampling takes two additional samples two and four cycles of f XIN before the defined sample point the bit level is decided on the majority of the three samples Triple sampling implements a means of digital filtering being appropriate if the bus signal is contaminated by noise Baud rate The module contains a programmable prescaler which is clocked by the MCUs internal clock frequency fo This prescaler allows division ratios of 1 to 1 16 refer to Figure 2 4 4 The baud rate can be calculated as follows where p is the prescaler division ratio f 1 f CAN tor p i Tots Tobs1 Tobs2 Dominant polarity The polarity control register PCON Figure 2 2 9 allows to select the dominant level either high or low This setting depends on the transceiver please refer to the specification of the device circuit in use 2 50 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module Auto receive function If receiving of CAN frames originating by the module itself are not required the auto receive disable bit CREC 6 Figure 2 4 16 should be set CAN interrupts The module features six interrupts each of them can be either enabled or disabled by the corresponding control bits of the interrupt control registers ICONA and ICONB refer to section 2 4 11 Enable
213. r cycle Table 2 7 1 Watchdog timer cycle Internal clock selection bit Upper byte count source selection bit bit 6 of CPU mode register address 000016 bit 7 of Watchdog timer register address 002E16 0 Approx 104 9 ms f XIN 2 5 MHz Approx 6 6 ms 1 Approx 419 4 ms Period f XIN 8 1 25 MHz Approx 26 2 ms 0 Approx 131 1 ms f XIN 2 4 MHz Approx 8 2 1 Approx 524 3 f XIN 8 1 MHz Approx 32 8 ms 2 7 3 Watchdog timer procedure Figure 2 7 2 shows the set up procedure of watchdog timer RESET X These bits are not used in this application Please set these bits to 0 or 1 appropriately Initialization CPUM Address 000016 00000X002 f XiN divided by 2 high speed mode WDT Address 002E16 XOXXXXXX2 The watchdog timer starts counting down Main processing The watchdog timer counters are set to the initial values WDT Address 002E16 lt XOXXXXXX2 by this writing WDH is set to 7F16 WD is set to F16 Watchdog timer interrupt processing routine If a microcomputer runs away because of noise or others the watchdog timer is not initialized and underflows Then the watchdog timer occurs reset the software Software reset Fig 2 7 2 Set up procedure of watchdog timer 7630 Group User s Manual 2 95 APPLICATION 2 8 Reset 2 8 Reset
214. ram of UART 1 Description The transmit and receive shift registers have a buffer consisting of high and low order byte each Since the shift registers cannot be written to or read from directly transmit data is written to the transmit buffer and receive data is read from the receive buffer A transmit or receive operation will be triggered by the transmit enable bit and receive enable bit of the UART control register UCON see Structure of UART control register The double function terminals P2 UT D P2 URTS and P24 URxD P27 UCTS will be switched to the UART pins automatically 2 Baud rate selection The baud rate of transmission and reception is determined by the setting of the prescaler and the contents of the UART baud rate gen erator register It is calculated by E 16 p n 1 where pis the division ratio of the prescaler and n is the contents of the UART baud rate generator register The prescalers division ration can be selected by the UART mode register see page 1 31 UART mode register UMOD Structure of UART mode register The UART mode register allows to select the transmission and reception format with the following options word length 7 8 or 9 bits parity none odd or even Stop bits 1 or 2 It allows to select the prescalers division ratio as well UART baud rate generator UBRG This 8 bit register allows to select the baud rate of the UART see above Set this register to the desire
215. rite 0 has no effect while CTRM 3 1 Not used no operation 0 when read Transmit status bit read only 0 CAN module idle or receiving 1 CAN module transmitting Fig 34 Structure of CAN transmit control register CAN receive control register address 003D g CREC Receive buffer control bit 0 Receive buffer empty 1 Receive buffer full write 1 has no effect Receive status bit read only 0 CAN module idle or transmitting 1 CAN module receiving Not used do not write 1 read as 0 Auto receive disable bit 0 Auto receive enabled 1 Auto receive disabled Note Suppresses reception of self initiated transmitted frames Not used do not write 1 O when read Fig 35 Structure of CAN receive control register 1 34 7630 Group User s Manual CAN transmit abort register address 003E g CABORT Transmit abort control bit 0 No transmit abort request 1 Transmit abort request write 1 has no effect while CTRM 3 0 Not used No operation 0 when read Fig 36 Structure of CAN transmit abort register CAN bus timing control register 1 address 003116 CBTCON1 Prescaler division ratio selection bits b3 b2 b1 bO 0000 divided by 1 0001 divided by 2 0010 divided by 3 divided by 15 divided by 16 Sampling control bit 0 One sample per bit 1 Three sample per bit 1 4
216. roller Area Network CAN module 2 4 Controller Area Network CAN module This section outlines the Controller Area Network CAN module of the MCU First the module s architecture and the programming interface with its related special function registers are explained Second after having defined the fun damental operational modes of the module the programming sequences to initialize and reset the module are clari fied Third the module s communication functions that is acceptance filtering reception and transmission are discussed in detail The closing of the section goes into the interrupt capabilities CAN error conditions and the wake up function 2 4 1 Description The CAN module can be characterized as follows Compatibility The module s protocol controller complies with CAN specification version 2 0 part B as defined by Bosch in September 1991 this document is later on called CAN specification The receive and transmit sec tions of the module are capable of handling standard 11 bit identifier as well as extended 29 bit identifier for mat frames of either data or remote type CPU interface The module is memory mapped with sixteen control registers two interrupt control registers one transmission and two receive buffer register sets Acceptance filtering Up to 29 bit identifiers can be filtered by using one set of acceptance mask and code regis ters Multi channel interrupt capability Separate interrupt ve
217. ror interrupt enable bit Serial I O interrupt enable bit AD conversion complete interrupt enable bit Key on wake up interrupt enable bit Step 2 Set the each function related the setting interrupts Note 1 Note 1 For details refer to setting method of each function Fig 2 2 10 Interrupt setting method 1 2 14 7630 Group User s Manual APPLICATION 2 2 Interrupts Step 3 Clear the setting interrupt request bits to 0 no interrupt request b7 bO Interrupt request register A IREQA Address 000216 External interrupt INTo request bit External interrupt INT1 request bit CAN successful transmission interrupt request bit CAN successful receive interrupt request bit CAN overrun interrupt request bit CAN error passive interrupt request bit CAN bus off interrupt request bit bO Interrupt request register B IREQB Address 000316 CAN wake up interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit CNTRo interrupt request bit CNTR1 interrupt request bit bo Interrupt request register C IREQC Address 000416 UART receive complete receive buffer full interrupt request bit UART transmit complete transmit register empty interrupt request bit UART transmit buffer empty interrupt request bit UART receive error interrupt request bit Serial I O interrupt request bit
218. rrupt disabled Interrupt enabled 1 Timer X interrupt enable bit Interrupt disabled Interrupt enabled Timer Y interrupt enable bit Interrupt disabled Interrupt enabled Timer 1 interrupt enable bit Interrupt disabled Interrupt enabled Timer 2 interrupt enable bit Interrupt disabled Interrupt enabled 5 Timer 3 interrupt enable bit Interrupt disabled i Interrupt enabled CNTRo interrupt enable bit O Interrupt disabled 1 Interrupt enabled CONTR interrupt enable bit O Interrupt disabled 7 1 Interrupt enabled Fig 2 2 6 Structure of Interrupt control register B Interrupt control register C b7 b6 b5 b4 b3 b2 b bO BILLI Interrupt control register C ICONC Address 000716 e usc cum receive complete receive Interrupt disabled buffer full interrupt enable bit Interrupt enabled 1 UART transmit complete transmit 0 Interrupt disabled register empty interrupt enable bit 1 Interrupt enabled 2 UART transmit buffer empty O Interrupt disabled interrupt enable bit 1 Interrupt enabled 3 UART receive error 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled Serial 1 O interrupt enable bit O Interrupt disabled 4 1 Interrupt enabled 5 AD conversion complete i Interrupt disabled interrupt enable bit Interrupt enabled Key on wake up Interrupt disabled interrupt enable bit Interrupt enabled Not used 0 when read 9 fox Fig 2 2 7 St
219. rs Structure of port I Os 1 and Structure of port I Os 2 Port Pi register i 0 to 4 address 000846 2 i Pi Port Pi control bit j 0 to 7 0 L level 1 H level Note The control bits corresponding to P19 P35 P3 and P3 are not used 0 when read do not write 1 Port Pi direction register i 0 to 4 address 000946 2 i PiD Port Pi direction control bit j 0 to 7 0 Port configured as input Port configured as output The direction control bits corresponding to P19 P14 P35 P3 and P3 are not used 0 when read do not write 1 Port direction registers are undefined when read write only 1 Ports PO AN to PO AN Pull up control bit 4 Analog input selection Direction 5 register Data bus e Port latch ADC input Analog input selection 2 Port P1 INT Interrupt input qi Data bus ERE 3 Port P1 INT Pull up control bit Direction register Data bus e s Port latch eal nterrupt input Fig 11 Structure of port I Os 1 4 Port P13 TXp Pull up control bit direction register J Data bus Port latch RS Timer bi phase mode input 5 Po
220. rs 0 b7 b6 b5 b4 b3 b2 b1 bo CAN transmit buffer register O CTBO Address 0040 g CAN receive buffer register 0 CRBO Address 0050 g B Name Function O Standard identifier bit 6 Standard identifier bit 7 For CTBO These bits represent part of the identifier field of a frame to be transmitted Standard identifier bit 8 Dou For CRBO These bits represent part of Standard identifier bit 9 the identifier field of a frame received Standard identifier bit 10 When these bits are read out the values are 0 Don t write to 1 Not used Fig 2 4 18 Structure of CAN transmit receive buffer registers 0 CTBO CRBO 2 44 7630 Group User s Manual CAN transmit receive buffer registers 1 APPLICATION 2 4 Controller Area Network CAN module b7 b6 b5 b4 b3 b2 b1 bo CAN transmit buffer register 1 CTB1 Address 004146 CAN receive buffer register 1 CRB1 Address 0051 g B Name Function At reset 0 IDE bit 0 Standard format 1 Extended format RTR SRR bit RTR bit frames of standard format or SRR bit frames of extended format Standard identifier bit 0 Standard identifier bit 1 Standard identifier bit 2 Standard identifier bit 3
221. rs 3 3 47 Fig 3 5 52 Structure of CAN transmit receive buffer registers 4 3 47 viii 7630 GROUP USER S MANUAL NNNNE 3 48 AN transmit receive butter registers Fig 3 5 53 Fig 3 5 54 Structure of CAN transmit receive buffer registers 6 to D 7630 GROUP USER S MANUAL List of figures List of tables List of tables CHAPTER 1 HARDWARE Table 1 Pi 1 4 Table 2 List of supported producig ett ttt 1 6 Table 3 Push and pop instructions of accumulator of processor status register 1 8 Table 4 Set and clear instructions of each bit of processor status register 1 9 Table 5 Interrupt vector addresses and priority 1 18 Table 6 Timer X count direction in bi phase counter MOE ecco 1 24 Table 7 Output control conditions ttes 1 30 Table 8 Programming adapter name t ttes 1 44 Table 9 Absolute maximum ratings ctt ttt 1 45 Table 10 Recommended operating conditions sse 1 45 Table 11 Electrical characteristics cett ttt 1 46 Table 12 A D converter characteristic eot t thia rk rab Rf a RA RN 1 47 Table 13 Timing requirements tt ttt 1 48 Table 14 Switching Characteristics 1 49 Table 2 1 1 Handling of unused pins ttes 2 8 Table 2 5 1 Setting examples of Baud rate generator values and transfer bit rate values 2 80 Table 2 5 2 Clock divider selection for serial VO sss
222. rts P14 CNTRo P15 CNTR Pull up control bit 4 Direction register Data bus 9 Port latch aa Timer bi phase mode input 6 Port P1 PWM Pull up control bit PWM output enable Direction register Data bus gt Port latch PWM output 7630 Group User s Manual 1 13 HARDWARE I O PORTS 7 Ports P17 P39 P33 P34 12 Ports P2 UR D P2 Ucrs Transmission or reception in Pull up control bit 4 Pull up control bit 4 progress Transmit or receive enable bit 3 Direction Direction register 7 register jm Data bus Port latch Data bus Port latch y Uso Or Uerg input 8 Port P2 Sin 13 Ports P25 UTxD P2e Unrs Transmission or reception in Pull up control bit 4 Pull up control bit progress Transmit or receive enable bi SIO Port Select Direction Direction H t register register La Port latch Data bus Port latch y j f Urxp or Upts outpu for Ucts 5 for U
223. ructure of Interrupt control register C 2 12 7630 Group User s Manual APPLICATION 2 2 Interrupts Interrupt polarity selection register b7 b6 b5 b4 b3 b2 bi bO NENENN Interrupt polarity selection register IPOL Address 002D16 8 mame Function Not used 0 when read don t write 1 1 INTo interrupt edge selection bit 0 Falling edge active Note 1 Rising edge active INT interrupt edge selection bit 0 Falling edge active Note 1 Rising edge active Not used 0 when read don t write 1 Note To use the external interrupt functions the pull up transistor corresponding to the selected active level must be enabled by the corresponding pull up transistor control bits of the Port P1 pull up control register Fig 2 2 8 Structure of Interrupt polarity selection register Polarity control register b7 b6 b5 b4 b3 b2 bi bO EANNAN Polarity control register PCON Address 002F 16 B Name Function jese Key on wake up polarity 0 Low level active P4 pull up control bit 1 High level active P4 pull down 1 CAN module dominant level 0 Low level dominant P32 pull up control bit Note 1 High level dominant P32 pull down Not used undefined when read Note The selected dominant level also controls the polarity of the pull transistor enabled by the P32 pull up down transistor control bit bit 2 of the Port P3 pull up control
224. ructure of Watchdog timer register 3 37 Fig 3 5 32 Structure of Polarity control register 3 37 Fig 3 5 33 Structure of CAN transmit control register sssssssee 3 38 Fig 3 5 34 Structure of CAN bus timing control register 1 3 38 Fig 3 5 35 Structure of CAN bus timing control register 2 3 39 Fig 3 5 36 Structure of CAN acceptance code register 0 3 39 Fig 3 5 37 Structure of CAN acceptance code register 1 3 40 Fig 3 5 38 Structure of CAN acceptance code register 2 3 40 Fig 3 5 39 Structure of CAN acceptance code register 3l ooooccocnoconocococccoocnnocancnnnnos 3 41 Fig 3 5 40 Structure of CAN acceptance code register 4 3 41 Fig 3 5 41 Structure of CAN acceptance mask register Ol coonnoncccinnnncccccnnnocncccconaanncncnnnn 3 42 Fig 3 5 42 Structure of CAN acceptance mask register 1 3 42 Fig 3 5 43 Structure of CAN acceptance mask register 2 3 43 Fig 3 5 44 Structure of CAN acceptance mask register 3j sss 3 43 Fig 3 5 45 Structure of CAN acceptance mask reglater 4 3 44 Fig 3 5 46 Structure of CAN receive control register 3 44 Fig 3 5 47 Structure of CAN transmit abort register 3 45 Fig 3 5 48 Structure of CAN transmit receive buffer registers OQ 3 45 Fig 3 5 49 Structure of CAN transmit receive buffer registers 1 3 46 Fig 3 5 50 Structure of CAN transmit receive buffer registers 2 3 46 Fig 3 5 51 Structure of CAN transmit receive buffer registe
225. rupt INTo enable bit Interrupt disabled Interrupt enabled 2 External interrupt INT1 enable bit Interrupt disabled a Interrupt enabled 3 CAN successful transmission O Interrupt disabled interrupt enable bit 1 Interrupt enabled 4 CAN successful receive 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 5 CAN overrun 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled CAN error passive 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 7 CAN bus off 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled Fig 3 5 5 Structure of Interrupt control register A Interrupt control register B b7 b6 b5 b4 b3 b2 bi bO ITITI Interrupt control register B ICONB Address 000616 s Nae Function fese CAN wake up interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled 1 Timer X interrupt enable bit O Interrupt disabled 1 Interrupt enabled 2 Timer Y interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled 3 Timer 1 interrupt enable bit O Interrupt disabled 1 Interrupt enabled Timer 2 interrupt enable bit 0 Interrupt disabled 4 1 Interrupt enabled 5 Timer 3 interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled CNTRo interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled 7 CNTR interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled Fig 3 5 6 Structure of Interru
226. rupt can not be stored and hence is lost 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module The timing diagram in Figure 2 4 35 shows one example for a condition leading to a COVR request The conditions used in the timing diagram are Module in virgin condition as after module reset Acceptance filtering disabled mask all identifier bits Buffer content processing by CAN successful receive CSR interrupt service Execution time of the CSR interrupt service routine onger than the frames on the bus Interrupt system of the application optimised for minimum latency of interrupts sum O O EH 1 1 1 receive status bit CREC 1 CAN successful receive interrupt request bit IREQA 4 receive buffer control bit CREC 0 foreground receive buffer contents CRBO to CRBD CAN overrun interrupt request bit IREQA 5 Arbitration field control field I P3 CRX L CAN overrun i E interrupt request bit IREQA 5 gt lack covr 7 tbt undefined foreground receive buffer s w clears CREO after end of frame C module sets CREO one cycle later CPU still processes frame C in foreground buffer while the background buffer holds frame D frame E can not be stored and is
227. s following the rules of the CAN specification After a successful transmission without errors the module will Clear the transmit buffer control bit CTRM 5 Clear the transmit request bit CTRM 3 Setthe CAN successful transmit CST interrupt request bit IREQA 3 Note The CAN successful receive interrupt CSR interrupt may also be requested unless disabled by the auto receive interrupt disable bit of CREC Figure 2 4 16 refer to section 2 4 8 too 5 Timing of transmit sequence The timing diagram in Figure 2 4 37 shows the status of the internal special function bits during transmit sequence if the module wins bus arbitration End of frame Intermission P3 CRX PETTE transmit status bit CTRM ttsb sof 0 1 tack tsb 1O tpr transmit request bit CTRM 3 lt ttrb sof min 30 f XIN tack trb 7 8 tbt transmit buffer control bit CTRM 5 lack tbc 7 8 tot CAN successful transmit i interrupt request bit IREQA 3 tack cst 6 7 tot Fig 2 4 37 Transmit sequence timing arbitration win After a transmission has been requested by setting CTRM 3 the module attempts to start the transmission at the next possible time depending on the bus condition During a successful transmission process the mod ule alters the special function bits as follows 1 Set transmit status bit CTRM 7
228. s products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics To all our customers Regarding the change of names mentioned in the document such as Mitsubishi Electric and Mitsubishi XX to Renesas Technology Corp The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003 These operations include microcomputer logic analog and discrete devices and memory chips other than DRAMs flash memory SRAMs etc Accordingly although Mitsubishi Electric Mitsubishi Electric Corporation Mitsubishi Semiconductors and other Mitsubishi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute any alteration to the contents of the document itself Note Mitsubishi Electric will continue the business operations of high frequency amp optical devices and power devices Renesas Technology Corp Customer Support Dept April 1 2003 424 N SAS Renesas Techno
229. s should be read out Register symbols End or Return from interrupt service routine If the receive processing scheme in use in based on polling CREC O only not CSR inter rupt service CREC 0 must be sampled only once at the beginning of the routine Fig 2 4 33 Flowchart of the receive process 7630 Group User s Manual Read or write Read or write 0 Read or write 1 Reserved 2 57 APPLICATION 2 4 Controller Area Network CAN module 3 interrupt request bit IREQA 4 interrupt request bit IREQA 4 foreground receive buffer Timing of receive sequence The timing diagrams in Figure 2 4 34 shows the status of the internal special function bits and the contents of the foreground receive buffer during receive sequence Of course this timing diagram depends on the appli cation software and actual communication model i e scheduling of messages on the bus therefore the dia gram should be considered an example The time between the occurrence of the receive interrupt request and the clearing of this request bit depends on the interrupt system of the actual application The latency of the interrupt depends on the execution time of all interrupt service routines of the application unless interrupt nesting is enabled The conditions used in the timing diagram are Module in virgin condition as after module reset Acceptance filtering disabled mask al
230. s suited to drive automotive equipments The Clock synchronous sse 1 channel CAN module complies with CAN specification version 2 0 part B and DART eS A d ru AA EET es 1 channel allows priority based message management CAN module In addition to the microcomputers simple instruction set the ROM CAN specification version 2 0 part B 1 channel RAM and I O addresses are placed in the same memory map to SACD PONV EOI Patel af ies Mera i 8 bits x 8 channels enable easy programming Watchdog timer g a e a e E a pa a 1 The built in ROM is available as mask ROM or One Time PROM For e Clock Generating Circuit u u cece sess sss 4 development purposes emulator and EPROM type microcomputers Built in with internal feedback resistor are available as well e Power source volta ge at 10 MHz oscillation frequency 4 0to 5 5 V FEATURES Power dissipation A In high speed mode nananana nauan 55 mW a BASIE machine languade instructions d DEI A at MH oscillation frequency at 5 V power source voltage e Minimum instruction execution time e o tina temperature ran 40 to 85 C at 10 MHz oscillation frequency 0 2 us Pe emperane NS naro y s e Package de oobis 44QFP 44P6N A Memory size ROM aeneum 16252 bytes M37630M4T XXXFP RAM Eus uy mates 512 bytes M37630M4T XXXFP APPLICATION e O ports Automotive controls Programmable I O ports l i esee 35
231. sesscsaeeeeasaeees 2 48 245 Modules mala adas 2 50 A nn A o O a 2 53 2 4 7 Acceptance Mem RI nanen nrst atenn rnat nt 2 54 2 4 8 Message receptiori ecssceccsceccsessssssssssssssessssscsssessssscssssesssssstsesssecsstsessseesssecateceatecessecen 2 55 2 4 9 Message transmission cscscssseccccsessscsesssssssssseseseseseecsesesesessesseeseseseseaeseeceeeees 2 60 2 4 10 Abort transmissiar A 2 62 EN RR CF Mites OE Ten RR lll 2 65 2 4 12 Error condition s essent tnnntntnenene n 2 65 BALAI WY aie e tis Vick CAN NETT RE 2 66 BS Sera I O sree heer cc eae eee hrs tae No 2 67 2 5 1 Memory map of serial l Ol ooccncccunnocccnonccanionnnnnooncnconnnnnnononoonnnonononcnnnnnrnonanennnnnn 2 67 PRSETER 2 68 2 5 3 Serial I O connection examples 2 72 2 5 4 Setting of serial 1 0 transfer data format sssssssstttttttnnennnnnnne 2 74 2 5 5 Serial VO application examples ccn nate tn erac mtt ctn 2 75 8 A D converter ii aaa dnd dm MEN MR UMEN EM EE 2 90 2 6 1 Memory map of A D conversion 2 90 A 2 91 2 6 3 A D conversion application example 2 92 2 6 4 Conversion A eects E 2 93 AA RR 2 93 2 7 Waichdog a metet eire teet tetti de gess costas tnus cincti edet tonis 2 94 2 7 1 Related SEI c usosmesona Grm nen x Xa ea cep n cash nips ON cba GG fimo aad nia L E 2 94 2 7 2 Watchdog timer Ol si id da 2 95 2 7 3 Watchdog Mar proc mao 2 95 O A Em 2 96 2 Oscillation Circ it Et 2 97 2 9 1 M
232. sesteeeseeeen 3 12 33 NOS Cin Se MENU 3 13 AAPP A 3 13 3 3 2 Notes on A D converter ntes 3 13 3 3 3 Notes on RESET pin luisa 3 14 3 3 4 Notes on input and Output PITIS escisiones 3 14 A E m 3 15 3 4 Countermeasures against noise esecsssscssssscssssecsssseessueessnseessuseessuesssueeesoneeessueessaneessaseesss 3 17 zu i shortest wiring AP PP A 3 17 3 4 2 Connection of a bypass capacitor across the Vss line and the Vcc line 3 18 3 4 3 Wiring to analog input PINS ee cece ent eene nnns 3 18 3 4 4 3 11 BFR memory map nenas puckictia doti oh reta tecintttomsin nets etsi 3 64 3 12 Pin configuration aducir ria m 3 65 7630 GROUP USER S MANUAL iil List of figures List of figures HAPTER 1 HARDWARE Fig 1 Pin configuration of M37630MAT XXXEP ttn 1 2 Fig 2 Functional block diagram 1 3 Fig 3 O di 1 5 Fig 4 Memory expansion A cc 1 6 Fig 5 740 Family CPU register structure 1 7 Fig 6 Register push and pop at interrupt generation and subroutine call 1 8 Fig 7 Structure of CPU mode register 1 10 Fig 8 Memory map diagram nnne nnne se rsen enne 1 11 Fig 9 Memory map of special register SFR 1 12 Fig 10 Structure of Port and Port direction registers eiiean 1 13 Fig 11 Structure of Port VOs Di as 1 13 Fig 12 Structure of Port l Os 2 seen 1 14 Fig 13 Structure of Port pull up down control regist
233. sing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by ADH and ADL in ADH is 8 high order bits and ADL is 8 low or der bits Contents of address indicated by zero page ADL 1 bit of accumulator 1 bit of memory Opcode Number of cycles Number of bytes 3 63 APPENDIX 3 11 SFR memory map 3 11 SFR memory map 3 64 000016 CPU mode register 000116 Not used 000216 Interrupt request register A 000316 Interrupt request register B 000416 Interrupt request register C IREQC 000516 Interrupt control register A ICONA 000616 Interrupt control register B 000716 Interrupt control register C 000816 Port PO register 000916 Port PO direction register 000A16 Port P1 register P1 000B16 Port P1 direction register P1D 000C16 Port P2 register P P 2 000D 6 Port P2 direction register 2D 000E16 Port P3 register P3 000F16 Port P3 direction register P3D 001016 Port P4 register P4 001116 Port P4 direction register P4D 001216 Serial I O shift register SIO 001316 Serial I O control register SIOCON 001416 A D conversion register AD 001516 A D control register ADCON 001616 Timer 1 T 1 001716 Timer 2 T2 001816 Timer 3 T3 001916 Timer 123 mode register T123M 001A16 Timer XL TXL 001B16 Timer XH TXH 001C16 Timer YL L TY A S Hi i i TYM 0
234. sion of frames with either 11 or 29 bit identifier length Refer to Fig 33 for a block diagram of the CAN interface The programmer s interface to the CAN module is formed by three status control registers Fig 34 Fig 35 Fig 36 two bus timing con trol registers Fig 37 Fig 38 several registers for acceptance filter ing Fig 39 the transmit and receive buffer registers Fig 40 and one dominant level control bit Fig 24 Baud Rate Selection A programmable clock prescaler is used to derive the CAN module s basic clock from the internal system clock frequency 6 Bit O to bit 3 of the CAN bus timing control register represent the prescaler allow ing a division ratio from 1 to 1 16 to be selected So the CAN module basic clock frequency fcang can be calculated as follows Toans p 1 where pis the value of the prescaler selectable from 1 to 15 The effective baud rate of the CAN bus communication depends on the CAN bus timing control parameters and will be explained below CAN Bus Timing Control Each bit time consists of four different segments see Fig 32 Synchronization segment SS Propagation time segment PTS Phase buffer segment 1 PBS1 and Phase buffer segment 2 PBS2 Bit time SS PTS PBS1 PBS2 Sample point Fig 32 Bit time of CAN module The first of these segments is of fixed length one Time Quantum and the latter three
235. sistor is used in the Mask ROM version the microcomputer operates correctly Reason The VPP pin of the One Time PROM and the EPROM version is the power source input pin Approximately for the built in PROM When programming in 5kQ the built in PROM the impedance of the VPP pin is low to allow the electric current for writing flow into the PROM Because of this noise can enter easily If noise enters the VPP pin 7630 group abnormal instruction codes or data are read from the built in PROM which may cause a Fig 3 4 3 Wiring for the VPP pin of the One Time program runaway PROM and the EPROM version 3 4 2 Connection of a bypass capacitor across the Vss line and the Vcc line Connect an approximately 0 1 uF bypass capacitor across the Vss line and the Vcc line as follows Connect a bypass capacitor across the Vss pin and the Vcc pin at equal length Connect a bypass capacitor across the Vss pin and the Vcc pin with the shortest possible wiring Use lines with a larger diameter than other signal lines for Vss line and Vcc line Connect the power source wiring via a bypass capacitor to the Vss pin and the VCC pin Fig 3 4 4 Bypass capacitor across the Vss line and the Vcc line 3 4 3 Wiring to analog input pins Connect an approximately 100 Q to 1 kQ resistor to an analog signal line which is connected to an analog input pin in series Besides connect the resistor to the microcomputer as close as possible Note
236. snne 2 80 Table 2 7 1 Watchdog timer cycle tenentes 2 95 Table 2 11 1 7630 group s built in PROM version supporting products 2 101 Table 2 11 2 Programming adapter stt tenen 2 103 Table 2 11 3 Setting of programming adapter _switCh cocioconononinaninanicacacnrnananananas 2 103 Table 2 11 4 Setting of PROM programmer address sss 2 103 Table 3 1 1 Absolute maximum ratings stet 3 2 Table 3 1 2 Recommended operating conditions sssttne 3 3 Table 3 1 3 Electrical characteristics tentant tette teta tnnt ta tette tanta 3 4 Table 3 1 4 A D converter characteristics cetttt ttes 3 5 Table 3 1 5 Timing requirements tette 3 5 Table 3 1 6 Switching characteristics 3 6 7630 GROUP USER S MANUAL ix CHAPTER 1 HARDWARE DESCRIPTION FEARURES APPLICATION FUNCTION BLOCK DIAGRAM PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION HARDWARE DESCRIPTION DESCRIPTION Interrupts 0000 24 sources 24 vectors Timers The 7630 group is a single chip 8 bit microcomputer designed with 16 bit Timers 0 cc esses 2 channels CMOS silicon gate technology 8 bit TImetS ee oes baie tows ot beac aig ane ESSA 3 channels Being equipped with a CAN Controller Area Network module circuit Serial I Os the microcomputer i
237. ss 2 67 Fig 2 5 2 Structure of Serial 170 shift register 2 68 Fig 2 5 3 Structure of Serial 1 0 control register rettet site bestie 2 68 Fig 2 5 4 Structure of UART mode register ssssse 2 69 Fig 2 5 5 Structure of UART baud rate generator 2 69 Fig 2 5 6 Structure of UART control reQiSter cccssssssssscssssesssssssssssccsssecssssseessecessnesessnes 2 70 Fig 2 5 7 Structure of UART status register scsccsscsssssccsssesssssnsseessssesssetessseessenesetes 2 70 Fig 2 5 8 Structure of UART transmit buffer register 1 2 sss 2 71 Fig 2 5 9 structure of UART receive buffer register 1 2 2 71 Fig 2 5 10 Serial 1 0 connection examples 1 sssseeen 2 72 Fig 2 5 11 Serial 1 O connection examples 2 cscccccccscscssscscsestscecessssssssesesesescecsesnenees 2 73 Fig 2 5 12 Setting of serial 1 O transfer data format sssssssss 2 74 Fig 2 5 13 Connection diagram Output of serial data s 2 75 Fig 2 5 14 Timing chart Output of Serial data 2 75 Fig 2 5 15 Setting of serial I O related registers Output of serial data 2 76 Fig 2 5 16 Setting of serial I O transmission data Output of serial data 2 77 Fig 2 5 17 Control procedure of clock synchronous serial 1 0 Output of serial data 2 78 Fig 2 5 18 Connection diagram Communication using UARTT ss 2 79
238. st of instruction codes 3 9 List of instruction codes Hexadecimal 3 byte instruction 2 byte instruction 1 byte instruction 7630 Group User s Manual 3 53 APPENDIX 3 10 Machine instructions 3 10 Machine instructions Symbol Function Details Addressing mode A BIT A R ZP BIT ZP R n JOP n JOP OP n ADC Note 1 Note 8 When T 0 AA M C When T 1 M X MX M C Adds the carry accumulator and memory con tents The results are entered into the accumulator Adds the contents of the memory in the ad dress indicated by index register X the contents of the memory specified by the ad dressing mode and the carry The results are entered into the memory at the address indi cated by index register X AND Note 1 When T 0 A lt AAM When T 1 M X M X AM AND s the accumulator and memory con tents The results are entered into the accumulator AND s the contents of the memory of the ad dress indicated by index register X and the contents of the memory specified by the ad dressing mode The results are entered into the memory at the address indicated by index register X CH Shifts the contents of accumulator or contents of memory one bit to the left The low order bit of the acc
239. stop bits Parity enable bit Parity disabled Word length selection bits 9 bits UART control register Address 002216 b7 bO UCON fo 1 0 o Transmit enable bit Transmit disabled Set this bit to 1 at starting communication Receive enable bit Receive disabled Transmission initialization bit Initialize the transmit enable bit and transmit status register flags Receive initialization bit No action UART baud rate generator Address 002116 b7 bO pet Transfer bit rate X 16 X p The value p is decided by the Clock divider selection bits bit 1 and bit 2 of the UART mode register address 002016 Refer to Table 2 5 2 UART status register Address 002316 b7 bO USTS Transmission register empty flag This flag is set to 1 at transmit shift completed Check a completion of transmitting 1 word data with this flag Transmission buffer empty flag This flag is set to 1 at transfer data from the Transmit buffer register to the Transmit shift register Fig 2 5 26 Setting of related registers on transmitting side Communication using UART 2 86 7630 Group User s Manual APPLICATION 2 5 Serial I O e Receiving side CPU mode register Address 000016 b7 bO CPUM ppp Internal system clock selection bit y f XIN divided by 2 high speed mode UART mode register Address 002016 b7 bO 1 1 1 amoo ETE CIR ER CIE Clock divider selection bits
240. sured width of the input voltage for output code 7 is 19 mV so the differential nonlinear error is represented as 19 20 1 mV 0 05 LSB A D CONVERTER STEP WIDTH MEASUREMENT VCC 5 12 V VREF 5 12 V XIN 10 MHz Analog port POo Temp 25 deg 1LSB WIDTH ERROR mV Absolute precision error Au HLGIM 8gs71 20 1LSB 30 80 88 96 104 112 120 128 MA a al ale A pul eel a A Aa Aol ay ERROR mV Au HLGIM gs71 20 1LSB 30 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256 STEP No Measured when a power source voltage is stable in the single chip mode and the high speed mode Fig 3 2 9 A D conversion standard characteristics 3 12 7630 Group User s Manual APPENDIX 3 3 Notes on use 3 3 Notes on use 3 3 1 Notes on interrupts 1 Switching an external interrupt detection edge When the external interrupt detection edge must Clear an interrupt enable bit to 0 interrupt disabled be switched make sure the following sequence Reason The interrupt circuit recognizes the switching of the detection edge as the change of external input signals This may cause an unnecessary Clear an interrupt request bit to 0 interrupt no interrupt request issued Set the interrupt enable bit to 1 interrupt enabled 2 Check of interrupt request bit When executing the BBC or BBS
241. t xk Symbols PRES SE Y Clear transmit status bit Write O Read or Write O Read or Write 1 Reserved Fig 2 4 38 Flowchart of transmit process 2 64 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module 2 4 11 CAN interrupts The module provides six interrupt sources with separate interrupt vectors each interrupt is requested by setting the corresponding interrupt request bit Vector Address Interrupt name Requested upon Description dcus id High Low CAN successful transmit CST Pv pede EL ora section 2 4 9 FFF3 FFF21 IREQA 3 ICONA3 CAN successful receive CSR ea reception fa CAN section 2 4 8 FFF116 FFFOig IREQA 4 ICONA 4 detecting a relevent frame on the Avoiding CAN over CAN overrun COVR bus while no receive buffer is run interrupts FFEFig FFEE g IREQA 5 ICONA 5 vacant Figure 2 4 35 CAN error passive CERP EMT SHfor active section 2 4 12 FFEDi FFECig IREQA 6 ICONA 6 CAN bus off CBOF ae from error pas section 2 4 12 FFEB FFEA g IREQA 7 ICONA 7 CAN wake up CWKU ite ed todomi section 2 4 13 FFE9 FFE8 g IREQB 0 ICONBO 2 4 12 Error condition As defined in the CAN specification the module features internal transmit and receive error counters these coun
242. t Chapter 3 also includes necessary information for systems denelopment Be sure to refer to this chapter 1 Organization CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions based mainly on setting examples of related registers CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer electric characteristics a list of registers the masking confirmation mask ROM version and mark specifications which are to be submitted when ordering 2 Structure of register The figure of each register structure describes its functions contents at reset and attributes as follows Note 2 Bit attributes Note 1 CPU mode register Contents immediately after reset release b7 b6 b5 b4 b3 b2 b1 bO HE CPU mode register CPUM Address 000016 Single chip mode Not available Not available Not available clock selection bit ed e 2 high speed mode 8 middle speed mode Not used 0 when read don t write 1 Bit in which nothing is arranged Note 1 Contents immediately after reset release O ese 0 at reset release 1 ee 1 at reset release undefined Undefined at reset release k eeeeee Contents determined by option at reset release Note 2 Bit attrib
243. t abort register CABORT Reserved CAN transmit buffer register 0 CTBO CAN transmit buffer register 1 CTB1 CAN transmit buffer register 2 CTB2 CAN transmit buffer register 3 CTB3 CAN transmit buffer register 4 CTB4 CAN transmit buffer register 5 CTB5 CAN transmit buffer register 6 CTB6 CAN transmit buffer register 7 CTB7 CAN transmit buffer register 8 CTB8 CAN transmit buffer register 9 CTB9 CAN transmit buffer register A CTBA CAN transmit buffer register B CTBB CAN transmit buffer register C CTBC CAN transmit buffer register D CTBD Reserved Reserved CAN receive buffer register 0 CRBO CAN receive buffer register 1 CRB1 CAN receive buffer register 2 CRB2 CAN receive buffer register 3 CRB3 CAN receive buffer register 4 CRB4 CAN receive buffer register 5 CRB5 CAN receive buffer register 6 CRB6 CAN receive buffer register 7 CRB7 CAN receive buffer register 8 CRB8 CAN receive buffer register 9 CRB9 CAN receive buffer register A CRBA CAN receive buffer register B CRBB CAN receive buffer register C CRBC CAN receive buffer register D CRBD Reserved Reserved 7630 Group User s Manual APPENDIX 3 12 Pin configuration 3 12 Pin configuration j 49 P16 PWM gt P12 INT1 pel 4 P11 INTo gt PO7 AN7 gt P06 ANe t gt P05 AN5 4 9 P04 AN4 gt P03 AN3 27 25 al 23 4 9 P02 AN2 V P01 AN1 4 9 POo ANO Piz P20 Sini 4 9 P21 Sour1 gt 36 P22 Scuk1 4 9
244. t bi phase counter mode CNTR input H pulse width bi phase counter mode tw CNTR CNTRo CNTR input L pulse width except bi phase counter mode CNTR input L pulse width bi phase counter mode t CNTR TXj Lag of CNTR and TX input edges bi phase counter mode tc TXo TX input cycle time bi phase counter mode twH TXo TX input H pulse width bi phase counter mode tw TXo TX input L pulse width bi phase counter mode twn INT INTo INT input H pulse width twi INT INTo INT input L pulse width tc Scu Serial I O clock input cycle time twa Scu Serial I O clock input H pulse width twi Scu Serial I O clock input L pulse width tsu Siy Scik Serial I O input setup time tu Scix Sin 1 48 Serial I O input hold time 7630 Group User s Manual unless otherwise noted HARDWARE SWITCHING CHARACTERISTICS Table 14 Switching characteristics Vec 4 0 to 5 5 V Vss AVss 0 V T4 40 to 85 C unless otherwise noted Limits Parameter typ twa Sci Serial I O clock output H pulse width 0 5 to Scix 50 twi Sci Serial I O clock output L pulse width 0 5 to Scix 50 tp Scuc Sour Serial I O output delay time tv Scuc Sour Serial I O output valid time ta Scik Serial I O clock output rise time
245. t interrupt the process to avoid causing erroneous frames being sent In result of the abort transmit request the module will 1 Clear the transmit buffer control bit CTRM 5 thereby release the buffer 2 Clear the transmit request bit CTRM 3 3 Clear the transmit abort control bit CABORT O As the abort transmission request might fall together with an ongoing transmission the buffer might not be availa ble immediately after issuing the abort transmission request Therefore the re initialization of the buffer should not be started before having confirmed its availability via CTRM 5 refer to section 2 4 9 7630 Group User s Manual 2 63 APPLICATION 2 4 Controller Area Network CAN module Transmit process from user side and CAN module side transmit buffer vacant CTRM 5 0 initialize transmit buffer registers set transmit buffer control bit CTRM 5 set transmit request bit Write 1 CAN module CTRM 3 z Await CAN successful j transmission transmit request CTRM 3 1 Write 1 Va User software Write 1 set transmit status bit CTRM 7 y start transmission bus arbitration win continue transmission no errors detected Clear transmit request bit Write 0 clear transmit buffer control bit CTRM 3 5 set CST interrupt request bi
246. tents of index register X by 1 Ys Y 1 Decrements the contents of index register Y by 1 A M zz X 1 M zz X A M S 1 s complememt of Remainder S 8 1 Divides the 16 bit data that is the contents of M zz x 1 for high byte and the contents of M zz x for low byte by the accumulator Stores the quotient in the accumulator and the 1 s complement of the remainder on the stack When T 0 ASAWYM When T 1 M X M X VM Exclusive ORs the contents of accumulator and memory The results are stored in the ac cumulator Exclusive ORs the contents of the memory specified by the addressing mode and the contents of the memory at the address indi cated by index register X The results are stored into the memory at the address indi cated by index register X AA 1or MM 1 Increments the contents of accumulator or memory by 1 X X 1 Increments the contents of index register X by 1 3 56 Yc Y 1 Increments the contents of index register Y by C8 7630 Group User s Manual Addressing mode APPENDIX 3 10 Machine instructions Processor status register ABS X ABS Y IND ZP IND IND X IND Y REL 3 OP n OP n JOP n JOP n JOP n JOP n JOP 50 70
247. ters serve to define the state of the module between the options error active error passive and bus off In nor mal run mode the error counters are increased upon detection of an error and decreased upon successful trans mission or reception of CAN frames following the rules of the CAN specification These counters are internal registers and not available to the CPU the transitions from error active to error passive state and from error pas sive to bus off are flagged by a request of the corresponding error passive CERP and bus off CBOF interrupts In normal run mode the receive and transmit error counters are under control of the module an can not be altered or read by the CPU Upon switching to configuration mode however the counters are cleared and the module is put to error active state As defined in the CAN specification the module takes part in normal bus communication and flags errors detected by sending an active error flag After the module has transit to error passive state the module continues communication but errors detected are flagged by a passive error flag In bus off state the module sus pends the communication and does not influence the bus any more the CTX pin is kept at recessive level Please refer to the state diagram in Figure 2 4 39 and to the CAN specification for details on the conditions leading to state transitions Transmit or receive error count greater than 127 Error passive Transmit and receive error
248. the processor status register is pushed onto the stack with the break flag set to 1 The saved processor status is the only place where the break flag is ever set 6 Index X mode flag T When the T flag is 0 arithmetic operations are performed between accumulator and memory e g the results of an operation between two memory locations is stored in the accumulator When the T flag is 1 direct arithmetic operations and direct data transfers are enabled between memory locations i e between memory and memory memory and I O and I O and 1 0 In this case the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1 The address of memory location 1 is specified by index register X and the address of memory location 2 is specified by normal addressing modes 7 Overflow flag V The V flag is used during the addition or subtraction of one byte of signed data It is set if the result exceeds 127 to 128 When the BIT instruction is executed bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag 8 Negative flag N The N flag is set if the result of an arithmetic operation or data transfer is negative When the BIT instruction is executed bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag Table 4 Set and clear instructions of each bit of processor status register Set i
249. tics 3 3 Notes on use 3 4 Countermeasures against noise 3 5 List of registers 3 6 Mask ROM ordering method 3 7 Mark specification form 3 8 Package outline 3 9 List of instruction codes 3 10 Machine instructions 3 11 SFH memory map 3 12 Pin configuration APPENDIX 3 1 Electrical characteristics 3 1 Electrical characteristics 3 1 1 Absolute maximum ratings Table 3 1 1 Absolute maximum ratings Parameter Power source voltage Input voltag P00 PO7 P11 P17 P20 P27 P30 P34 P40 P47 RESET XIN Output voltage P0o PO07 P12 P17 P20 P27 P30 P34 P40 P47 XouT Conditions All voltages with respect to Vss and output transistors are off Ratings 0 3 to 7 0 0 3 to Vcc 0 3 0 3 to Vcc 0 3 Power dissipation Ta 25 C 500 Operating temperature Storage temperature 3 2 7630 Group User s Manual 40 to 85 60 to 150 APPENDIX 3 1 Electrical characteristics 3 1 2 Recommended operating conditions Table 3 1 2 Recommended operating conditions Vcc 4 0V to 5 5V Vss AVss OV Ta 40 C to 85 C unless otherwise noted Limits Parameter Power source voltage Vss VIH H input voltage P00 P07 P11 P17 P20 P27 P30 P34 P40 P47 RESET XIN ViL L input voltage P00 P07 P11 P17 P20 P27 P30 P34 P40 P47 RESET XIN Y lOH peak H sum peak output current P00 P07 P12 P17
250. tifier bit don t care 1 Compare identifier bit Standard identifier mask bi Standard identifier mask bi Standard identifier mask bit 10 These bits must be set to 0 Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 2 4 11 Structure of CAN acceptance mask register 0 CAMO CAN acceptance mask register 1 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance mask register 1 CAM1 Address 003946 B Name Function 0 These bits must be set to 0 Standard identifier mask bi Standard identifier mask bi Standard identifier mask bi 0 Mask identifier bit don t care 1 Compare identifier bit Standard identifier mask bi These bits mask the corresponding bit of the acceptance code register 1 Figure 2 4 7 from the acceptance filtering Standard identifier mask bi Standard identifier mask bi Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 2 4 12 Structure of CAN acceptance mask register 1 CAM1 7630 Group User s Manual 2 41 APPLICATION 2 4 Controller Area Network CAN module CAN acceptance mask register 2 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance mas
251. ting an external clock 7630 group Microcomputer 7630 group Microcomputer 5 Using UART URTS UCTS not use 7630 group Microcomputer Note Port is an output port controlled by software Fig 2 5 11 Serial I O connection examples 2 7630 Group User s Manual 2 73 APPLICATION 2 5 Serial I O 2 5 4 Setting of serial I O transfer data format A clock synchronous or clock asynchronous UART is selected as a data format Figure 2 5 12 shows a setting of serial I O transfer data format 1ST 9DATA 1SP E NSTAGB AXA A A AX A A msy s 1ST 8DATA 1SP m ASABA XA A A A A Ansa sp 1ST 7DATA 1SP m NSTAGB A A A A __Xusey sp 1ST 9DATA 1PAR 1SP m NSTAGB AXA A A A A A AMBA PAR sp 1ST 8DATA 1PAR 1SP m NSTAGB XX X A A XMSBXPARI sp 1ST 7DATA 1PAR 1SP m AsTASBX A A X A AMSB A PAR SP 1ST 9DATA 2SP m NSTAGB X XA A X A A A ANS 2sp 1ST 8DATA 2SP m NSTAGB X A XX A AMBY asp 1ST 7DATA 2SP AsTASSBX AXA A A A XUsB asp 1ST 9DATA 1PAR 2SP AsTASSBX A A A A A A XMSBXPARI asp 1ST 8DATA 1PAR 2SP m LstAsaX__ A A A A A AMBA Par Y asp 1ST 7DATA 1PAR 2SP NSTAGB X A X X AMSB X PARY 2sp Serial l O LSB first Clock synchronous serial I O HU ae BT Start bit SP Stop bit PAR Parity bit Fig 2 5 12 Setting of serial I O transfer data format 2 74 7630 Group User s Manual APPLICATION 2 5 Serial I O 2 5 5 Serial
252. tion 2 4 4 Fig 2 4 9 Structure of CAN acceptance code register 3 CAC3 CAN acceptance code register 4 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance code register 4 CAC4 Address 003746 B Name Function 0 Not used Undefined at read Extended identifier bit 0 Extended identifier bit 1 These bits except when masked by the acceptance mask register 4 Figure 2 4 15 form the acceptance filtering condition for incoming CAN frames They must be initialised with the identifier pattern of CAN frames to be received Extended identifier bit 2 Extended identifier bit 3 Extended identifier bit 4 Extended identifier bit 5 Note 1 Writing to this register is enabled in configuration mode only refer to section 2 4 4 Fig 2 4 10 Structure of CAN acceptance code register 4 CAC4 2 40 7630 Group User s Manual APPLICATION 2 4 Controller Area Network CAN module CAN acceptance mask register 0 b7 b6 b5 b4 b3 b2 bi bO CAN acceptance mask register 0 CAMO Address 003846 B Name Function At reset These bits mask the corresponding bits 2 of the acceptance code register 0 Figure f 2 4 6 from the acceptance filtering 0 Standard identifier mask bi Standard identifier mask bi 0 Mask iden
253. to P10 P11 P35 P3s and P37 are reserved 0 when read don t write 1 Fig 2 1 3 Structure of Port Pi direction register i 0 1 2 3 4 7630 Group User s Manual 2 3 APPLICATION 2 1 1 0 ports Port Pi pull up control register b7 b6 b5 b4 b3 b2 bi bO oes Port Pi pull up control register PUPI i 0 2 Address 002816 002A16 Nam Function aese ON pull up transistor control bit me No pull up Pull up 1 Pit pull up transistor control bit 0 No pull up 1 Pull up o Pi2 pull up transistor control bit 0 No pull up 1 Pull up 3 Pis pull up transistor control bit 0 No pull up 1 Pull up Pi4 pull up transistor control bit 0 No pull up 4 1 Pull up 5 Pis pull up transistor control bit 0 No pull up 1 Pull up Pie pull up transistor control bit O No pull up 1 Pull up 7 Pi7 pull up transistor control bit 0 No pull up 1 Pull up Fig 2 1 4 Structure of Port Pi pull up register i 0 2 Port P1 pull up control register b7 b6 b5 b4 b3 b2 bi bO T I Port P1 pull up control register PUP1 Address 002916 fe Name Function Ateset W 0 when read don t write 1 o olx o ox 2 P12 pull up transistor control bit O No pull up 1 Pull up P13 pull up transistor control bit 0 No pull up 3 1 Pull up 4 P14 pull up transistor control bit 0 No pull up 1 Pull up 5 P15 pull up transistor control bit 0 No pull up 1 Pu
254. to f Xi 16 Oscillation is restarted if an external interrupt is accepted or at reset When using an external interrupt the internal clock y remains at H level until timer 2 underflows allowing a time out until the clock oscil Xin O Fig 48 Ceramic resonator circuit lation becomes stable When using reset a fixed time out will be gen erated allowing oscillation to stabilize Wait mode The microcomputer enters the wait mode by executing the WIT instruction The internal clock stops at H level while the oscillator keeps running Recovery from wait mode can be done in the same way as from stop mode However the time out period mentioned above is not required to return from wait mode thus no such time out mechanism has been implemented Note Set the interrupt enable bit of the interrupt source to be used to return from stop or wait mode to 1 before executing STP or WIT instruction Internal clock for Interrupt request Interrupt disable flag RESET STP peripherals Internal clock Oscillator countdown for CPU timer 1 and 2 Fig 49 Block diagram of clock generating circuit 7630 Group User s Manual 1 43 HARDWARE DATA REQUIRED FOR MASK ORDERS DATA REQUIRED FOR MASK ORDERS The followi
255. transmit buffer register 1 2 UART receive buffer register 1 UART receive buffer register 2 b7 b6 b5 b4 b3 b2 bi bO UART receive buffer register 1 URBR1 Address 002616 UART receive buffer register 2 URBR2 Address 002716 CG Receive data is read from this buffer register consisting of low order olx and high order byte ox olx AOK ex jobs olx elx Fig 2 5 9 Structure of UART receive buffer register 1 2 7630 Group User s Manual 2 71 APPLICATION 2 5 Serial I O 2 5 3 Serial I O connection examples 1 Control of peripheral IC equipped with CS pin Figure 2 5 10 shows connection examples with peripheral ICs using clock synchronous serial I O mode 1 Only transmission 2 Transmission and reception using the SIN pin as an I O port 7630 group Peripheral IC 7630 i OSD controller etc iia Fenpheral Ic E2PROM etc 3 Connecting ICs 7630 group Peripheral IC 2 Note Port is an output port controlled by software Fig 2 5 10 Serial I O connection examples 1 2 72 7630 Group User s Manual APPLICATION 2 5 Serial I O 2 Connection with microcomputer Figure 2 5 11 shows connection examples with other microcomputers using serial I O 1 Selecting an internal clock 2 Selecting an external clock 7630 group Microcomputer 7630 group Microcomputer 3 Using the SRDY signal output function 4 Using UART Selec
256. tructure of Polarity control register 2 6 7630 Group User s Manual APPLICATION 2 1 1 0 ports 2 1 3 Overvoltage conditions at digital input ports This section describes how to use digital input ports of the 7630 group at overvoltages The terms over voltage refer to voltage levels beyond Vcc 0 3V When subjected to such input voltage levels the built in protection circuit of the input port attempts to limit the input voltage in order to avoid permanent damage to the device This condition causes input current to the port The built in protection circuit tolerates input currents up to specified limits refer to 3 1 Electrical characteristics The input current levels must be limited by appropriate design of the application circuit connected to the coresponding port Figure 2 1 9 shows an example circuit Protection circuit Fig 2 1 9 External circuit example applying overvoltage to digital inputs Assume VIN the voltage to be connected to the MCU The resistor R limits the input current to satisfy the recommended operatiing conditions For an estimation of the resistor the port voltage VP should be assumed to be Vcc at overvoltage VIN gt Vcc 0 3V To determine the appropriate resistor size refer to the below Vin max Vcc is lio VIN gt VCC 0 3V Notes Subjecting ports to overvoltage may effect the supply voltage and ground levels of the application and the device Ensure appropriate design
257. tting of related registers Measurement of analog signals 2 92 2 6 6 Control procedure Measurement of analog signals 2 93 2 7 1 Structure of Watchdog timer TESTO cocoa 2 94 2 7 2 Setup procedure of watchdog timer e 2 95 2 8 1 Example of Power on reset circult ctrrttten 2 96 2 8 2 RAM back up System 2 96 2 9 1 Memory map of oscillation circuit related registers e 2 97 2 9 2 Structure of CPU mode register 2 98 2 9 3 Structure of Watchdog timer register 2 98 2 9 4 Switching procedure to Stop model e 2 99 2 9 5 Switching procedure to Wait MOG cccecccccccsccscssssssssssssssssescesssessssesessessstsseseteeeee 2 99 2 10 1 Configuration example of using M37630T RFS eee 2 100 2 11 1 Pin configuration of 7630 group s built in PROM versions 2 102 2 11 2 Programming and testing of One Time PROM version 2 104 CHAPTER 3 APPENDIX Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 3 1 1 Circuit for measuring output switching characteristics ss 3 6 a MGR MAKING MEMINI 3 7 3 2 1 cc Voc standard characteristics in high speed mode 3 8 3 2 2 cc Vcc standard characteristics in middle speed mode sss 3 8 3 2 3 Power source current standard characteristics in high speed mode
258. uest interrupt request bit 1 Interrupt requested 4 CAN successful receive 0 No interrupt request gt interrupt request bit 1 Interrupt requested 5 CAN overrun 0 No interrupt request x interrupt request bit 1 Interrupt requested CAN error passive 0 No interrupt request interrupt request bit 1 Interrupt requested 7 CAN bus off 0 No interrupt request gt interrupt request bit 1 Interrupt requested Can be cleared to 0 by software but cannot be set to 1 Fig 3 5 2 Structure of Interrupt request register A 3 22 7630 Group User s Manual APPENDIX 3 5 List of registers Interrupt request register B b7 b6 b5 b4 b3 b2 bi bO LTT TTT TI Interrupt request register B IREQB Address 000316 fe Name Function fase w CAN wake up 0 No interrupt request interrupt request bit 1 Interrupt requested 1 Timer X interrupt request bit 0 No interrupt request 1 Interrupt requested 2 Timer Y interrupt request bit 0 No interrupt request 1 Interrupt requested 3 Timer 1 interrupt request bit 0 No interrupt request 1 Interrupt requested Timer 2 interrupt request bit 0 No interrupt request 4 1 Interrupt requested 5 Timer 3 interrupt request bit 0 No interrupt request x 1 Interrupt requested CNTRo interrupt request bit 0 No interrupt request 1 Interrupt requested CNTA1 interrupt request bit 0 No interrupt request 7 1 Interrupt requ
259. uipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under cert
260. ull transistor towards the CAN module recessive level This level depends on the CAN module dominant level control bit bit 1 of the Polarity control register address 002F 16 Fig 3 5 28 Structure of Port P3 pull up control register 7630 Group User s Manual 3 35 APPENDIX 3 5 List of registers Port P4 pull up down control register b7 b6 b5 b4 b3 b2 bi bO ITITI Port P4 pull up down control register PUP4 Address 002C16 e tame Fion fese P40 pull up down transistor 0 No pull up down control bit 1 Pull up down Note 1 P41 pull up down transistor 0 No pull up down control bit 1 Pull up down Note 2 P42 pull up down transistor 0 No pull up down control bit 1 Pull up down Note 3 P43 pull up down transistor 0 No pull up down control bit 1 Pull up down Note 4 P44 pull up down transistor 0 No pull up down control bit 1 Pull up down Note 5 P45 pull up down transistor 0 No pull up down control bit 1 Pull up down Note P46 pull up down transistor 0 No pull up down control bit 1 Pull up down Note 7 P47 pull up down transistor 0 No pull up down control bit 1 Pull up down Note Note Enables the pull transistor towards the passive polarity of key on wake up interrupt This level depends on the Key on wake up polarity control bit bit O of the Polarity control register address 002F t6 Fig 3 5 29 Structure of Port P4 pull up down contr
261. umulator or memory is cleared and the high order bit is shifted into the carry flag Ai or Mi 0 Branches when the contents of the bit speci fied in the accumulator or memory is 0 Ai or Mi 1 Branches when the contents of the bit speci fied in the accumulator or memory is 1 BCC Note 5 Branches when the contents of carry flag is g BCS Note 5 Branches when the contents of carry flag is qr BEQ Note 5 Branches when the contents of zero flag is 1 BIT AND s the contents of accumulator and memory The results are not entered any where BMI Note 5 Branches when the contents of negative flag is q BNE Note 5 Branches when the contents of zero flag is 0 BPL Note 5 Branches when the contents of negative flag is g BRA Note 6 PC lt PC offset Jumps to address specified by adding offset to the program counter BRK 3 54 B 1 PC PC 2 M S E PCH S 8 1 M S PCL Sc 8 1 M S PS S 8 1 1 PCL ADL PCH lt ADH Executes a software interrupt 7630 Group User s Manual Addressing mode APPENDIX 3 10 Machine instructions Processor status register ABS X ABS Y IND ZP IND IND X IND Y REL 3 OP JOP JOP n JOP n JOP JOP OP D 3 7D 3
262. upt Watchdog timer register address 002E g WDT Not used undefined when read Stop instruction disable bit 0 Stop instruction enabled 1 Execute two NOP instructions instead once this bit is set to 1 it can t be cleared to 0 again except on RESET Upper byte count source selection bit 0 Underflow of the low order counter 1 divided by 256 Fig 44 Structure of watchdog timer register is internal clock system 1 40 7630 Group User s Manual HARDWARE RESET CIRCUIT RESET CIRCUIT The 7630 group is reset according to the sequence shown in Fig 46 It starts program execution from the address formed by the contents of the addresses FFFB4 and FFFA g when the RESET pin is held at Power on Power source voltage 4 0V ov Reset input voltage 0 8V ov 7630 group Fig 45 Example of reset circuit L level for more than 2 us while the power supply voltage is in the recommended operating condition and then returned to H level Refer to Fig 45 for an example of the reset circuit internal reset Address Data Fig 46 Reset sequence Xin T1 T2 X X OK EFFA 16 X FFFBis XAD ADX X 2 X 2 X t X ADL X AD Kistop code 8192 cycles of 28 to 34 cycles of Xi l 24 cycles of X y 4L 20 cycles of Xv gt
263. used returns to 0 when read External interrupt INT enable bit External interrupt INT enable bit CAN successful transmission interrupt enable bit CAN successful receive interrupt enable bit CAN overrun interrupt enable bit CAN error passive interrupt enable bit CAN bus off interrupt enable bit Interrupt control register B address 000616 ICONB CAN wake up interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit CNTRj interrupt enable bit CNTR interrupt enable bit Interrupt control register C address 000716 ICONC UART receive complete receive buffer full interrupt enable bit UART transmit complete transmit register empty interrupt enable bit UART transmit buffer empty interrupt enable bit UART receive error interrupt enable bit Serial I O interrupt enable bit AD conversion complete interrupt enable bit Key on wake up interrupt enable bit Not used returns to 0 when read 0 No interrupt request 0 Interrupt disabled 1 Interrupt requested 1 Interrupt enabled Fig 17 Structure of interrupt request and control registers A B and C 1 20 7630 Group User s Manual HARDWARE KEY ON WAKE UP KEY ON WAKE UP Key on wake up is one way of returning from a power down state PCON see Fig 14 If any pin of port P4 has the sele
264. ut frequency based on 50 duty P1 4 CNTRo P16 CNTR except bi phase counter mode P14 TXo P14 CNTRo bi phase counter mode Clock input oscillation frequency 7630 Group User s Manual 1 45 HARDWARE ELECTRICAL CHARACTERISTICS Table 11 ELECTRICAL CHARACTERISTICS Parameter H output voltage PO PO P1 P1 P2 P2 P3 P3 P4 P4 Voc 4 0 to 5 5 V Vgg AVss 0 V Ta 40 to 85 C unless otherwise noted Test conditions L output voltage PO P0 P1 P15 P2 P2 P35 P3 Hysteresis P1 INT P12 INT P14 TXp P14 CNTRo P1 CNTR P2o Swy P22 Seik P2 Urts P2 Ucrs P32 CRX RESET input current PO PO P1 P1 P2 P2 P3 P3 P4 P4 RESET Vcc input current Xin Voc input current PO PO0 P1 P 17 P2 P2 P3y P3a P4 P47 RESET Vss input current Xin Vss input current P3 P4 P4 Voc ull Down On input current PO P0 P1 P17 P2 P27 P3 P34 P4 P4 RESET Vi Vss Pull Up On RAM hold voltage When clock stopped 1 46 Power source current high speed mode f Xiy 8MHz Vec 5V output transistors off CAN module running ADC running high speed mode f Xin 8MHz Voc 5V output transistors off CAN module stopp
265. utes The attributes of control register bits are classified into 3 types read only write only and read and write In the figure these attributes are represented as follows R Read W ecceee Write O see Read enabled O ses Write enabled X ss Read disabled X eeeeee Write disabled Table of contents Table of contents CHAPTER 1 HARDWARE NO 1 2 FEATURE Sucia ds acia 1 2 C 1 2 PRE PO 1 2 FUNCTIONAL BLO DIAGRAM iia dad 1 3 PIN DESGHRIPTIGON 2 c since kat based hei gen tan eet ta taeda EEE E enia daa e ea aaa ade ena argent 1 4 re 1 5 a eee 1 6 Memory Type vtrescacneiciacagos nana i a deste scausesueatassantaswass NEUEN ERR ERAN ERARR RE 1 6 Di tia A E E lauecubesuses A s 1 6 m n 1 6 FUNG TIONAL DESGQGHRIB HQON eccesso ct rer nha rae dens tr rae urhe eng en denn un 1 7 Central Processing Unit CPU nennen nentes nnne 1 7 meme coma MEO 1 11 VO PONS e 1 13 1 17 MERO RPM UAR 12 MD NR NO 1 22 1 28 POCO 1 33 1 38 b oes cus M M ME MI EE 1 40 A A a E aa EAA RA EEEE EEE EEA AE EEEE 1 41 lock Generating Cit CUltl ococcocccccnnncnnonnonoccconccnnnnnnnnnnnnnononcnnnnnnnnnnnnnnnne men nnnncnnnnnncanannanas
266. value Actual time bps 15 OF 16 76 29 162 76 N 152 58 300 48 TI r o 305 17 600 96 o Tn o 2 610 35 1 302 08 o E e 1220 70 2403 84 2441 40 o T o 2 5208 33 4882 81 10416 66 o e S9 o 9765 62 19230 76 o 1 o 2 19531 25 31 250 00 o 31250 00 62500 00 62500 00 Notes 1 Equation of transfer bit rate Transfer bit rate bps 83333 33 9 vo A volo o o ess ese os le es le ls le ee ie oo o o M DD o ajaja 78125 00 BRG setting value 1 X 16 X p Notes 2 BRG count source p is selected by the Clock divider selection bits bit 1 and 2 of the UART mode register Address 002016 The Value p is decided by the Clock divider selection bits bit 1 and 2 of the UART mode register Address 002016 Refer to Table 2 5 2 Table 2 5 2 Clock divider selection for serial I O Clock divider selection bits Clock divider p bit bit 1 2 80 7630 Group User s Manual 0 0 0 1 1 0 1 1 APPLICATION 2 5 Serial I O Transmitting side CPU mode register Address 000016 b7 bO CPUM ppp Internal system clock selection bit y f XIN divided by 2 high speed mode UART mode register Address 002016 7 bo poe OO Clock divider selection bits 4 divided by 8 Stop bits selection bit Two stop bits Parity
267. ving a shorter pulse width than the standard is input to the RESET input pin the reset is released before the internal state of the microcomputer is completely initialized This may cause a program runaway Reset j f Reset _ circuit circuit 7630 group Fig 3 4 1 Wiring for the RESET input pin 2 Wiring for clock input output pins Make the length of wiring which is connected to clock I O pins as short as possible Make the length of wiring within 20mm across the grounding lead of a capacitor which is connected to an oscillator and the Vss pin of a microcomputer as short as possible Separate the Vss pattern only for oscillation from other Vss patterns Reason If noise enters clock I O pins clock waveforms may be deformed This may cause a program failure or program runaway Also if a potential difference is caused by the noise between the Vss level of a microcomputer and the Vss level of an oscillator the correct clock will not be input in the microcomputer Fig 3 4 2 Wiring for clock I O pins 7630 Group User s Manual 3 17 APPENDIX 3 4 Countermeasures against noise 3 Wiring for the VPP pin of the One Time PROM version and the EPROM version Connect an approximately 5 kQ resistor to the VPP pin the shortest possible in series When not connecting the resistor make the length of wiring for the VPP pin the shortest possible Note Even when a circuit which included an approximately 5 kQ re
268. witch bit On A D conversion register Address 001416 b7 b0 AD The result of A D conversion stored This register is read only Read the result of A D conversion after the A D conversion completion bit is set to 1 This bit is cleared to 0 at this reading Fig 2 6 5 Setting of related registers Measurement of analog signals 2 92 7630 Group User s Manual APPLICATION 2 6 A D converter Control procedure By setting the related registers as shown in Figure 2 6 6 the analog voltage input from the sensor are converted into digital values X These bits are not used in this application Please set these bits to O or 1 appropriately ADCON Address 001516 XXX110012 Select the PO1 AN pin as an analog input pin POD Address 000916 XXXXXX0X2 PO1 AN pin Input mode ADCON Address 001516 bit 3 0 Start A D conversion ADCON Address 001516 bit 3 Check the completion of A D conversion with the A D conversion completion bit Read out the conversion result Read out AD Address 001416 The A D conversion completion bit is cleared to 0 at this reading Fig 2 6 6 Control procedure Measurement of analog signals 2 6 4 Conversion time On A D conversion process takes 53 to 54 cycles of the internal system clock 6 2 6 5 Notes on use 1 Analog input pin Make the signal source impedance for analog input
269. wn Note P43 pull up down transistor AS No pull up down control bit Pull up down Note P44 pull up down transistor E No pull up down control bit Pull up down Note P45 pull up down transistor E No pull up down control bit Pull up down Note P46 pull up down transistor No pull up down control bit 1 Pull up down Note P47 pull up down transistor de No pull up down control bit Pull up down Note Note Enables the pull transistor towards the passive polarity of key on wake up interrupt This level depends on the Key on wake up polarity control bit bit O of the Polarity control register address 002F 16 Fig 2 1 7 Structure of Port P4 pull up down control register 7630 Group User s Manual 2 5 APPLICATION 2 1 I O ports Polarity control register b7 b6 b5 b4 b3 b2 bi bO E Polarity control register PCON Address 002F16 Nam Funcion eeoj e on wake up polarity 0 Low level active P4 pull up control bit 1 High level active P4 pull down CAN module dominant level 0 Low level dominant P32 pull up control bit Note 1 High level dominant P32 pull down Not used undefined when read Note The selected dominant level also controls the polarity of the pull transistor enabled by the P32 pull up down transistor control bit bit 2 of the Port P3 pull up control register the transistor pulling toward the recessive level is selected Fig 2 1 8 S
270. ws a control procedure on the receiving side Transmitting side RESET X These bits are not used in this application Please set these bits to 0 or 1 appropriately Initialization CPUM Address 000016 00000X002 f XiN divided by 2 high speed mode UMOD Address 002016 100X101 X2 Transfer data format 1ST 9DATA 2SP UCON Address 002216 XXXX01002 Transmit initialization UBRG Address 002116 4 1 The Transmit enable bit is cleared to 0 The Transmission register empty flag is set to 1 The Transmission buffer empty flag is set to 1 UCON Address 002216 bit 0 1 Transmit enable Start of communication UTBR1 Address 002416 e Write 9 bits of transmission data to the Transmit buffer register UTBR2 Address 002516 bit O The Transmit shift register shift completion flag is cleared to 0 by lt Transmission data 9 bits this writing When the Ucrs input level is L start transmission Note Check the shift completion of the Transmit shift register with the Transmit shift register shift completion flag y Transmit initialization End of communication UCON Address 002216 bit 2 lt 0 The Transmit enable bit is cleared to 0 The Transmission register empty flag is set to 1 The Transmission buffer empty flag is set t
271. y motor Outline The H level width of a pulse input to the P14 CNTRo pin is counted by Timer X An underflow is detected by Timer X interrupt and an end of the input pulse H level is detected by a CNTRo interrupt Specifications The H level width of FG pulse input to the P14 CNTRo pin is counted by Timer X Example When the clock frequency is 8 MHz the count source would be 4 us that is obtained by dividing the clock frequency by 32 Measurement can be made up to 262 144 ms in the range of FFFF16 to 000016 Figure 2 3 15 shows timer connection and division ratio and Figure 2 3 16 shows a setting of related registers Note 1 Note 2 Timer X Timer X interrupt request Note 1 The internal system clock 6 is divided f XIN by 2 or by 8 The division ratio is decided by the Internal system clock selection bit bit 6 of the CPU mode register address 000016 Note 2 The division ratio is decided by the Timer count source selection bits bit O and bit 1 of the Timer X mode register address 001E16 Fig 2 3 15 Timer connection and division ratio Measurement of pulse width 2 30 7630 Group User s Manual APPLICATION 2 3 Timers CPU mode register Address 000016 b7 bO CPUM o WE Internal system clock selection bit f XIN divided by 2 high speed mode Timer X mode register Address 001E16 b7 bO TXM 1 fo 111 1 Timer X data write control bit Write to latch and timer

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